Uniform Sector

Standard and Dual Serial Flash GD25WD80C

GD25WD80C

DATASHEET

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Standard and Dual Serial Flash GD25WD80C

CONTENTS

1. FEATURES ................................................................................................................................................................ 4

2. GENERAL DESCRIPTION ..................................................................................................................................... 5

3. MEMORY ORGANIZATION .................................................................................................................................. 7

4. DEVICE OPERATION ............................................................................................................................................. 8

5. DATA PROTECTION ............................................................................................................................................... 9

6. STATUS REGISTER ............................................................................................................................................... 10

7. COMMANDS DESCRIPTION............................................................................................................................... 11

7.1. WRITE ENABLE (WREN) (06H) ......................................................................................................................... 13

7.2. WRITE DISABLE (WRDI) (04H) ......................................................................................................................... 13
7.3. READ STATUS REGISTER (RDSR) (05H)............................................................................................................. 14
7.4. WRITE STATUS REGISTER (WRSR) (01H) .......................................................................................................... 14
7.5. READ DATA BYTES (READ) (03H)..................................................................................................................... 15
7.6. READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH) ................................................................................ 15
7.7. DUAL OUTPUT FAST READ (3BH) ...................................................................................................................... 16
7.8. PAGE PROGRAM (PP) (02H)................................................................................................................................ 17
7.9. SECTOR ERASE (SE) (20H) ................................................................................................................................. 18
7.10. 32KB BLOCK ERASE (BE) (52H) ....................................................................................................................... 18
7.11. 64KB BLOCK ERASE (BE) (D8H) ...................................................................................................................... 19
7.12. CHIP ERASE (CE) (60/C7H)................................................................................................................................ 19
7.13. DEEP POWER-DOWN (DP) (B9H) ....................................................................................................................... 20
7.14. RELEASE FROM DEEP POWER-DOWN / READ DEVICE ID (ABH) ........................................................................ 21
7.15. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ........................................................................................ 22
7.16. READ IDENTIFICATION (RDID) (9FH) ................................................................................................................ 23
7.17. READ UNIQUE ID (4BH) .................................................................................................................................... 24

8. ELECTRICAL CHARACTERISTICS .................................................................................................................. 25

8.1. POWER-ON TIMING ....................................................................................................................................... 25

8.2. INITIAL DELIVERY STATE ............................................................................................................................ 25
8.3. ABSOLUTE MAXIMUM RATINGS ............................................................................................................... 25
8.4. CAPACITANCE MEASUREMENT CONDITIONS ........................................................................................ 26
8.5. DC CHARACTERISTICS................................................................................................................................. 27
8.6. AC CHARACTERISTICS................................................................................................................................. 30

9. ORDERING INFORMATION ............................................................................................................................... 37

9.1. VALID PART NUMBERS ............................................................................................................................................. 38

10. PACKAGE INFORMATION ............................................................................................................................. 40

10.1. PACKAGE SOP8 150MIL .................................................................................................................................... 40

10.2. PACKAGE SOP8 208MIL .................................................................................................................................... 41
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10.3. PACKAGE TSSOP8 173MIL ............................................................................................................................... 42
10.4. PACKAGE DIP8 300MIL ..................................................................................................................................... 43
10.5. PACKAGE USON8 (1.5*1.5MM) ......................................................................................................................... 44
10.6. PACKAGE USON8 (3*2MM, THICKNESS 0.45MM) ............................................................................................... 45

11. REVISION HISTORY ........................................................................................................................................ 46

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1. FEATURES
◆ 8M-bit Serial Flash ◆ Fast Program/Erase Speed
-1024K-byte -Page Program time: 1.6ms typical
-256 bytes per programmable page -Sector Erase time: 150ms typical
-Block Erase time: 0.5/0.8s typical
◆ Standard, Dual Output -Chip Erase time: 12s typical
-Standard SPI: SCLK, CS#, SI, SO, WP#
-Dual Output: SCLK, CS#, IO0, O1, WP# ◆ Flexible Architecture
-Uniform Sector of 4K-byte
◆ Clock Frequency -Uniform Block of 32/64k-byte
-100MHz for fast read on 3.0~3.6V power supply
◆ Dual Output Data Transfer up to 160Mbits/s ◆ Low Power Consumption
-70MHz for fast read on 2.1~3.0V power supply -0.1uA typical standby current
◆ Dual Output Data Transfer up to 120Mbits/s -0.1uA typical power down current
-50MHz for fast read on 1.65~2.1V power supply
◆ Dual Output Data Transfer up to 80Mbits/s ◆ Advanced Security Features
-128-bit Unique ID for each device
◆ Software/Hardware Write Protection
-Write protect all/portion of memory via software ◆ Single Power Supply Voltage
-Enable/Disable protection with WP# Pin -Full voltage range: 1.65~3.6V

◆ Minimum 100,000 Program/Erase Cycles ◆ Package option

-SOP8 150MIL
◆ Data Retention -SOP8 208MIL
-20-year data retention typical -TSSOP8 173MIL
-DIP8 300MIL
-USON8 1.5*1.5MM
-USON8 3*2MM

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2. GENERAL DESCRIPTION
The GD25WD80C (8M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual Output: Serial Clock, Chip Select, Serial Data I/O0 (SI), O1 (SO). The Dual Output data is transferred with maximum
speed of 160Mbits/s.

CONNECTION DIAGRAM

CS# 1 8 VCC CS# 1 8 VCC

SO SO
2 7 NC 2 7 NC
(O1) (O1)
Top View Top View
WP# 3 6 SCLK WP# 3 6 SCLK

SI SI
VSS 4 5 VSS 4 5
(IO0) (IO0)
8–LEAD
8–LEAD USON
SOP/TSSOP/DIP

PIN DESCRIPTION
Pin Name I/O Description
CS# I Chip Select Input
SO (O1) O Data Output (Data Output 1)
WP# I Write Protect Input
VSS Ground
SI (IO0) I/O Data Input (Data Input Output 0)
SCLK I Serial Clock Input
NC No Connection
VCC Power Supply

Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.

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BLOCK DIAGRAM

WP# Write Control

Logic

Status

Write Protect Logic

and Row Decode
Register

Flash
High Voltage
Memory
Generators
SPI
SCLK Command &
Control Logic Page Address
Latch/Counter
CS#

SI(IO0) Column Decode And

256-Byte Page Buffer
SO(O1)
Byte Address
Latch/Counter

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3. MEMORY ORGANIZATION

GD25WD80C
Each device has Each block has Each sector has Each page has
1M 64/32K 4K 256 bytes
4K 256/128 16 - pages
256 16/8 - - sectors
16/32 - - - blocks

UNIFORM BLOCK SECTOR ARCHITECTURE

GD25WD80C 64K Bytes Block Sector Architecture
Block Sector Address range

255 0FF000H 0FFFFFH

15 …… …… ……
240 0F0000H 0F0FFFH
239 0EF000H 0EFFFFH
14 …… …… ……
224 0E0000H 0E0FFFH
…… …… ……
…… …… …… ……
…… …… ……
…… …… ……
…… …… …… ……
…… …… ……
47 02F000H 02FFFFH
2 …… …… ……
32 020000H 020FFFH
31 01F000H 01FFFFH
1 …… …… ……
16 010000H 010FFFH
15 00F000H 00FFFFH
0 …… …… ……
0 000000H 000FFFH

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4. DEVICE OPERATION

SPI Mode
Standard SPI
The GD25WD80C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the
rising edge of SCLK and data shifts out on the falling edge of SCLK.

Dual SPI
The GD25WD80C supports Dual Output operation when using the “Dual Output Fast Read” (3BH) commands. These
commands allow data to be transferred to or from the device at twice the rate of the standard SPI. When using the Dual
Output command the SI and SO pins become bidirectional I/O pins: IO0 and O1.

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5. DATA PROTECTION
The GD25WD80C provides the following data protection methods:
◆ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
reset to 0 in the following situations:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
◆ Software Protection Mode: The Block Protect (BP2, BP1, BP0) bits define the section of the protected memory area
which is read-only and unalterable.
◆ Hardware Protection Mode: WP# goes low to protect the BP0~BP2 bits and SRP bits.
◆ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command.
◆ Write Inhibit Voltage (VWI): Device would reset automatically when VCC is below a certain threshold VWI.

Table1. GD25WD80C Protected area size

Status Register Content Memory Content

BP2 BP1 BP0 Blocks Addresses Density Portion

0 0 0 NONE NONE NONE NONE
0 0 1 Sector 0 to 253 000000H-0FDFFFH 1016KB Lower 254/256
0 1 0 Sector 0 to 251 000000H-0FBFFFH 1008KB Lower 252/256
0 1 1 Sector 0 to 247 000000H-0F7FFFH 992KB Lower 248/256
1 0 0 Sector 0 to 239 000000H-0EFFFFH 960KB Lower 240/256
1 0 1 Sector 0 to 223 000000H-0DFFFFH 896KB Lower 224/256
1 1 0 Sector 0 to 191 000000H-0BFFFFH 768KB Lower 192/256
1 1 1 All 000000H-0FFFFFH 1024KB ALL

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6. STATUS REGISTER

S7 S6 S5 S4 S3 S2 S1 S0
SRP Reserved Reserved BP2 BP1 BP0 WEL WIP

The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit is set to 1, it means the device is busy in program/erase/write status register progress. when WIP bit is cleared
to 0, it means the device is not in program/erase/write status register progress. The default value of WIP is 0.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted. The default value of WEL is 0.
BP2, BP1, BP0 bits.
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected
against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the
Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table1).becomes protected against
Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP2, BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, if the
Block Protect (BP2, BP1, BP0) bits are all 0. The default value of BP2:0 are 0s.
SRP bit
The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The Status Register
Write Protect (SRP) bit and Write Protect (WP#) signal set the device to the Hardware Protected mode. When the Status
Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low. In this mode, the non-volatile bits of the Status
Register(SRP, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is not execution.
The default value of SRP is 0.

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7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device by the host system, with the most significant
bit first. On the first rising edge of SCLK after CS# is driven low, the one-byte command code must be shifted into the device,
with the most significant bit first on SI, and each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might
be followed by address bytes, or data bytes, or dummy bytes. CS# must be driven high after the last bit of the command
sequence has been completed.
For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device
ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can be completed after any
bit of the data-out sequence is being shifted out, and then CS# must be driven high to return to deselected status.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, which means the clock
pulse number should be an exact multiple of eight. Otherwise the command is rejected to executed. Especially for Page
Program command, if at any time the input end is not a completed byte, nothing will be written into the memory array, neither
would WEL bit be reset.

Table2. Commands
Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes
Write Enable 06H
Write Disable 04H
Read Status Register 05H (S7-S0) (continuous)
Write Status Register 01H S7-S0
Read Data 03H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) (continuous)
Fast Read 0BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous)
Dual Output 3BH A23-A16 A15-A8 A7-A0 dummy (D7-D0)(1) (continuous)
Fast Read
Page Program 02 H A23-A16 A15-A8 A7-A0 D7-D0 Next byte
Sector Erase 20H A23-A16 A15-A8 A7-A0
Block Erase(32K) 52H A23-A16 A15-A8 A7-A0
Block Erase(64K) D8H A23-A16 A15-A8 A7-A0
Chip Erase C7/60H
Deep Power-Down B9H
Release From Deep ABH dummy dummy dummy (DID7- (continuous)
Power-Down, And DID0)
Read Device ID
Release From Deep ABH
Power-Down
Manufacturer/ 90H 00H 00H 00H (MID7- (DID7- (continuous)
Device ID MID0) DID0)
Read Identification 9FH (MID7- (JDID15- (JDID7- (continuous)
MID0) JDID8) JDID0)
Read Unique ID 4BH 00H 00H 00H dummy (UID7- (continuous)
UID0)

NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
O1 = (D7, D5, D3, D1)

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TABLE OF ID DEFINATION:
GD25WD80C
Operation Code M7-M0 ID15-ID8 ID7-ID0
9FH C8 64 14
90H C8 13
ABH 13

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7.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit to 1. The Write Enable Latch
(WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write
Status Register (WRSR) command.
The Write Enable (WREN) command sequence: CS# goes low  sending the Write Enable command  CS# goes
high.
Figure1. Write Enable Sequence Diagram

CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
06H
High-Z
SO

7.2. Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit to 0. The WEL bit is reset by following
condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip
Erase commands.
The Write Disable command sequence: CS# goes lowSending the Write Disable command CS# goes high.
Figure2. Write Disable Sequence Diagram

CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
04H
High-Z
SO

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7.3. Read Status Register (RDSR) (05H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending
a new command to the device. It is also possible to read the Status Register continuously. For command code “05H”, the
SO will output Status Register bits S7~S0.
Figure3. Read Status Register Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

Command
SI
05H
S7~S0 out S7~S0 out
SO High-Z
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB

7.4. Write Status Register (WRSR) (01H)

The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. A Write Enable
(WREN) instruction must be executed previously to set the Write Enable Latch (WEL) bit, before it can be accepted.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction
code and the data byte on Serial Data Input (SI).
The Write Status Register (WRSR) instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6 and S5
are always read as 0. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been latched in.
Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High, the
self-timed Write Status Register cycle (the duration is tW) is initiated. While the Write Status Register cycle is in progress,
reading Status Register to check the Write In Progress (WIP) bit is achievable.
The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and turn to 0 on the completion
of the Write Status Register. When the cycle is completed, the Write Enable Latch (WEL) is reset to 0.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1,
BP0) bits, which are utilized to define the size of the read-only area.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect (SRP)
bit in accordance with the Write Protect (WP#) signal, by setting which the device can enter into Hardware Protected Mode
(HPM). The Write Status Register (WRSR) instruction is not executed once enter into the Hardware Protected Mode (HPM).
Figure4. Write Status Register Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

Command Status Register in

SI 01H 7 6 5 4 3 2 1 0
MSB High-Z
SO

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7.5. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit being latched-in on
the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at
a Max frequency fR, on the falling edge of SCLK. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore,
be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase,
Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure5. Read Data Bytes Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

Command 24-bit address

SI
03H 23 22 21 3 2 1 0
MSB Data Out1 Data Out2
SO High-Z
7 6 5 4 3 2 1 0
MSB

7.6. Read Data Bytes At Higher Speed (Fast Read) (0BH)

The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, and each bit being latched-in on the rising edge of SCLK. Then the memory content,
at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency fC, on the falling edge of SCLK. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out.
Figure6. Read Data Bytes at Higher Speed Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24-bit address

SI
0BH 23 22 21 3 2 1 0

SO High-Z

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI 7 6 5 4 3 2 1 0
Data Out1 Data Out2
SO 7 6 5 4 3 2 1 0 7 6 5
MSB MSB

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7.7. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit being
latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure7. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure7. Dual Output Fast Read Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24-bit address

SI
3BH 23 22 21 3 2 1 0

SO High-Z

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI 6 4 2 0 6 4 2 0 6
Data Out1 Data Out2
SO 7 5 3 1 7 5 3 1 7
MSB MSB

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7.8. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address
bytes and at least one data byte on SI.
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-
A0) are all zero). CS# must be driven low for the entire duration of the sequence.
The Page Program command sequence: CS# goes low  sending Page Program command  3-byte address on SI
 at least 1 byte data on SI  CS# goes high. The command sequence is shown in Figure8.
If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are
guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are
correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS#
must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP) command
is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command is not executed when it is applied to a page protected by the Block Protect (BP2,
BP1, BP0).
Figure8. Page Program Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK

Command 24-bit address Data Byte 1

SI
02H 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
CS#
2073

2075
2076

2078
2072

2074

2077

2079

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK

Data Byte 2 Data Byte 3 Data Byte 256

SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB

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7.9. Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the specific sector. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered
by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-byte address on SI 
CS# goes high. The command sequence is shown in Figure9. CS# must be driven high after the eighth bit of the last address
byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the
self-timed Sector Erase cycle (whose duration is t SE) is initiated. While the Sector Erase cycle is in progress, the Status
Register is accessed to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Sector Erase cycle, and becomes 0 when it is completed. At some unspecified time before the cycle is completed,
the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block
Protect (BP2, BP1, BP0) bit (see Table1) is not executed.
Figure9. Sector Erase Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bits Address

SI
20H 23 22 2 1 0
MSB

7.10. 32KB Block Erase (BE) (52H)

The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE)
command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside
the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the
sequence.
The 32KB Block Erase command sequence: CS# goes low  sending 32KB Block Erase command  3-byte address
on SI  CS# goes high. The command sequence is shown in Figure10. CS# must be driven high after the eighth bit of the
last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register is accessed to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and becomes 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP2, BP1, BP0) bits (see Table1) is not executed.
Figure10. 32KB Block Erase Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bits Address

SI
52H 23 22 2 1 0
MSB

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Standard and Dual Serial Flash GD25WD80C
7.11. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE)
command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside
the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the
sequence.
The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-byte address
on SI  CS# goes high. The command sequence is shown in Figure11. CS# must be driven high after the eighth bit of the
last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register is accessed to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and becomes 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP2, BP1, BP0) bits (see Table1) is not executed.
Figure11. 64KB Block Erase Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

Command 24 Bits Address

SI
D8H 23 22 2 1 0
MSB

7.12. Chip Erase (CE) (60/C7H)

The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving
CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the
sequence.
The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. The
command sequence is shown in Figure12. CS# must be driven high after the eighth bit of the command code has been
latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase
cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check
the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and
is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, BP0) bits are all 0. The Chip Erase (CE)
command is not excuted if any sector is under protection.
Figure12. Chip Erase Sequence Diagram

CS#

0 1 2 3 4 5 6 7
SCLK

Command
SI
60H or C7H

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7.13. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to enter the lowest consumption mode (the Deep
Power-Down Mode). Unlike deselecting the device by driving CS# high, or entering into the Standby Mode (if there is no
internal cycle currently in progress), the Deep Power-Down Mode provides an extra software protection mechanism while
the device is not in active use. The only access to this mode is by executing the Deep Power-Down (DP) command. Since
in the Deep Power-Down mode, the device ignores all Write, Program and Erase commands. Once the device is in the
Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI)
command. This releases the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI)
command also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby
Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS#
must be driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low  sending Deep Power-Down command  CS# goes
high. The command sequence is shown in Figure13. CS# must be driven high after the eighth bit of the command code has
been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires
a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-
Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
Figure13. Deep Power-Down Sequence Diagram

CS#

0 1 2 3 4 5 6 7 tDP
SCLK

Command Stand-by mode Deep Power-down mode

SI
B9H

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7.14. Release from Deep Power-Down / Read Device ID (ABH)
The Release from Power-Down and Read Device ID command is a multi-purpose command, which can be used to
release the device from the Power-Down state or obtain the devices electronic identification (ID) number.
When used to release the device from the Power-Down state, the command is issued by driving the CS# pin low,
shifting the instruction code “ABH” and driving CS# high as shown in Figure14. Release from Power-Down will take the
time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are
accepted. The CS# pin must keep high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the
CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure15. The Device ID value for the
GD25WD80C is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The
command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the same
as previously described, and shown in Figure15, except that after CS# is driven high it must remain high for a time
duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other
command will be accepted. If the Release from Power-Down and Read Device ID command is issued while an Erase,
Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the
current cycle.
Figure14. Release Power-Down Sequence Diagram
CS#

0 1 2 3 4 5 6 7 t RES1
SCLK

Command
SI
ABH

Deep Power-down mode Stand-by mode

Figure15. Release Power-Down and Read Device ID Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38
SCLK

Command 3 Dummy Bytes t RES2

SI ABH 23 22 2 1 0
MSB Device ID
SO High-Z
7 6 5 4 3 2 1 0
MSB
Deep Power-down Mode Stand-by Mode

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7.15. Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command
that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address
(A23-A0) of 000000H. After that, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure16. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.

Figure16. Read Manufacture ID/ Device ID Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24-bit address

SI
90H 23 22 21 3 2 1 0
SO High-Z

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK

SI

Manufacturer ID Device ID
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB

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7.16. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes
of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the
device in the second byte. Any Read Identification (RDID) command while an Erase or Program cycle is in progress is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is
followed by the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock.
The command sequence is shown in Figure17. The Read Identification (RDID) command is terminated by driving CS# high
at any time during data output. When CS# is driven high, the device is in the Standby Mode. Once in the Standby Mode,
the device waits to be selected, so that it can receive, decode and execute commands.
Figure17. Read Identification ID Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

SI 9FH
Command Manufacturer ID
SO 7 6 5 4 3 2 1 0
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK

SI

SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Memory Type Capacity
MSB JDID15-JDID8 MSB JDID7-JDID0

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7.17. Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The
Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low  sending Read Unique ID command  3-Byte Address
(000000H) Dummy Byte128bit Unique ID Out CS# goes high.
Figure18. Read Unique ID Sequence Diagram

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24-bit address

SI
4BH 23 22 21 3 2 1 0

SO High-Z

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI 7 6 5 4 3 2 1 0
Data Out1 Data Out2
SO 7 6 5 4 3 2 1 0 7 6 5
MSB MSB

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8. ELECTRICAL CHARACTERISTICS

8.1. POWER-ON TIMING

Figure19. Power-On Timing Sequence Diagram

VCC
VCC(max.)
Chip Selection is not allowed

VCC(min.)
tVSL Full Device
Access
Allowed
VPWD(max.)

tPWD
Time

Table 3. Power-Up Timing and Write Inhibit Threshold

Symbol Parameter Min. Max. Unit

tVSL VCC(min.)to device operation 0.3 ms
VWI Write Inhibit Voltage 1 1.55 V
VPWD VCC voltage needed to below VPWD for ensuring initialization will occur 0.5 V
tPWD The minimum duration for ensuring initialization will occur 300 us

8.2. INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register
contains 00H (all Status Register bits are 0).

8.3. ABSOLUTE MAXIMUM RATINGS

Parameter Value Unit
Ambient Operating Temperature -40 to 85 ℃
-40 to 105
-40 to 125
Storage Temperature -65 to 150 ℃
Applied Input/Output Voltage -0.6 to VCC+0.4 V
Transient Input/Output Voltage (note: overshoot) -2.0 to VCC+2.0 V
VCC -0.6 to 4.2 V

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Figure20. Maximum Negative/positive Overshoot Diagram
Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform

20ns 20ns
20ns
Vss
Vcc + 2.0V

Vss-2.0V
20ns Vcc
20ns 20ns

8.4. CAPACITANCE MEASUREMENT CONDITIONS

Symbol Parameter Min Tpy Max Unit Conditions
CIN Input Capacitance 6 pF VIN=0V
COUT Output Capacitance 8 pF VOUT=0V
CL Load Capacitance 30 pF
Input Rise And Fall time 5 ns
Input Pulse Voltage 0.1VCC to 0.8VCC V
Input Timing Reference Voltage 0.2VCC to 0.7VCC V
Output Timing Reference Voltage 0.5VCC V

Figure 21. Input Test Waveform and Measurement Level

Input timing reference level Output timing reference level

0.8VCC 0.7VCC
AC Measurement Level 0.5VCC
0.1VCC 0.2VCC

Note: Input pulse rise and fall time are <5ns

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8.5. DC CHARACTERISTICS
(T= -40℃~85℃, VCC=1.65~3.6V)
Symbol Parameter Test Condition Min. Typ. Max. Unit.
ILI Input Leakage Current ±2 μA
ILO Output Leakage Current ±2 μA
ICC1 Standby Current CS#=VCC, 0.1 2 μA
VIN=VCC or VSS
ICC2 Deep Power-Down Current CS#=VCC, 0.1 2 μA
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 100MHz, 3 6 mA
Q=Open(*1 I/O)
CLK=0.1VCC / 0.9VCC
at 80MHz, 2.5 4.5 mA
Q=Open(*1 I/O,*2 Output)
CLK=0.1VCC / 0.9VCC
ICC3 Operating Current (Read) at 50MHz, 1.3 3.5 mA
Q=Open(*1 I/O)
CLK=0.1VCC / 0.9VCC
at 40MHz, 1.6 4 mA
Q=Open(*1 I/O,*2 Output)
CLK=0.1VCC / 0.9VCC
at 16MHz, 1.2 2.5 mA
Q=Open(*1 I/O,*2 Output)
ICC4 Operating Current (PP) CS#=VCC 20 mA
ICC5 Operating Current (WRSR) CS#=VCC 20 mA
ICC6 Operating Current (SE) CS#=VCC 20 mA
ICC7 Operating Current (BE) CS#=VCC 20 mA
ICC8 Operating Current (CE) CS#=VCC 20 mA
VIL Input Low Voltage -0.5 0.2VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL =100μA 0.4 V
VOH Output High Voltage IOH =-100μA VCC-0.2 V
Note:
1. Typical value tested at T = 25℃. Icc3 (>80MHz) tested at VCC = 3.3V. Icc3 (<80MHz) tested at VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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(T= -40℃~105℃, VCC=1.65~3.6V)

Symbol Parameter Test Condition Min. Typ. Max. Unit.
ILI Input Leakage Current ±2 μA
ILO Output Leakage Current ±2 μA
ICC1 Standby Current CS#=VCC, 0.1 10 μA
VIN=VCC or VSS
ICC2 Deep Power-Down Current CS#=VCC, 0.1 10 μA
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 100MHz, 3 22 mA
Q=Open(*1 I/O)
CLK=0.1VCC / 0.9VCC
at 80MHz, 2.5 20 mA
Q=Open(*1 I/O,*2 Output)
ICC3 Operating Current (Read)
CLK=0.1VCC / 0.9VCC
at 40MHz, 1.6 7 mA
Q=Open(*1 I/O,*2 Output)
CLK=0.1VCC / 0.9VCC
at 16MHz, 1.2 5.5 mA
Q=Open(*1 I/O,*2 Output)
ICC4 Operating Current (PP) CS#=VCC 30 mA
ICC5 Operating Current (WRSR) CS#=VCC 30 mA
ICC6 Operating Current (SE) CS#=VCC 30 mA
ICC7 Operating Current (BE) CS#=VCC 30 mA
ICC8 Operating Current (CE) CS#=VCC 30 mA
VIL Input Low Voltage -0.5 0.2VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL =100μA 0.4 V
VOH Output High Voltage IOH =-100μA VCC-0.2 V
Note:
1. Typical value tested at T = 25℃. Icc3 (>50MHz) tested at VCC = 3.3V. Icc3 (<50MHz) tested at VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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(T= -40℃~125℃, VCC=1.65~3.6V)

Symbol Parameter Test Condition Min. Typ. Max. Unit.
ILI Input Leakage Current ±2 μA
ILO Output Leakage Current ±2 μA
ICC1 Standby Current CS#=VCC, 0.1 15 μA
VIN=VCC or VSS
ICC2 Deep Power-Down Current CS#=VCC, 0.1 15 μA
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 100MHz, 3 22 mA
Q=Open(*1 I/O)
CLK=0.1VCC / 0.9VCC
at 80MHz, 2.5 20 mA
Q=Open(*1 I/O,*2 Output)
ICC3 Operating Current (Read)
CLK=0.1VCC / 0.9VCC
at 40MHz, 1.6 7 mA
Q=Open(*1 I/O,*2 Output)
CLK=0.1VCC / 0.9VCC
at 16MHz, 1.2 5.5 mA
Q=Open(*1 I/O,*2 Output)
ICC4 Operating Current (PP) CS#=VCC 30 mA
ICC5 Operating Current (WRSR) CS#=VCC 30 mA
ICC6 Operating Current (SE) CS#=VCC 30 mA
ICC7 Operating Current (BE) CS#=VCC 30 mA
ICC8 Operating Current (CE) CS#=VCC 30 mA
VIL Input Low Voltage -0.5 0.2VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL =100μA 0.4 V
VOH Output High Voltage IOH =-100μA VCC-0.2 V
Note:
1. Typical value tested at T = 25℃. Icc3 (>50MHz) tested at VCC = 3.3V. Icc3 (<50MHz) tested at VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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8.6. AC CHARACTERISTICS
(T= -40℃~85℃, VCC=1.65~3.6V, CL=30pf)
Symbol Parameter Min. Typ. Max. Unit.
Serial Clock Frequency For: Fast read (0BH), on 3.0 – 3.6V
fC1 100 MHz
power supply
Serial Clock Frequency For: Fast read (0BH), on 2.1 – 3.0V
fC2 70 MHz
power supply
Serial Clock Frequency For: Fast read (0BH), on 1.65 – 2.1V
fC3 50 MHz
power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
fR1 80 MHz
3.0 – 3.6V power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
fR2 60 MHz
2.1 – 3.0V power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
fR3 40 MHz
1.65 – 2.1V power supply
tCLH1 Serial Clock High Time for 2.1 – 3.6V Power Supply 4 ns
tCLH2 Serial Clock High Time for 1.65 – 2.1V Power Supply 8 ns
tCLL1 Serial Clock Low Time for 2.1 – 3.6V Power Supply 4 ns
tCLL2 Serial Clock Low Time for 1.65 – 2.1V Power Supply 8 ns
tCLCH Serial Clock Rise Time (Slew Rate) 0.1 V/ns
tCHCL Serial Clock Fall Time (Slew Rate) 0.1 V/ns
tSLCH CS# Active Setup Time 10 ns
tCHSH CS# Active Hold Time 10 ns
tSHCH CS# Not Active Setup Time 10 ns
tCHSL CS# Not Active Hold Time 10 ns
tSHSL CS# High Time (Read/Write) 40 ns
tSHQZ Output Disable Time 12 ns
tCLQX Output Hold Time 0 ns
tDVCH Data In Setup Time 4 ns
tCHDX Data In Hold Time 4 ns
tCLQV Clock Low To Output Valid 12 ns
tWHSL Write Protect Setup Time Before CS# Low 20 ns
tSHWL Write Protect Hold Time After CS# High 100 ns
tDP CS# High To Deep Power-Down Mode 0.1 μs
CS# High To Standby Mode Without Electronic Signature
tRES1 0.1 μs
Read
tRES2 CS# High To Standby Mode With Electronic Signature Read 0.1 μs
tW Write Status Register Cycle Time 5 40 ms
tBP1 Byte Program Time (First Byte) 30 60 μs
tBP2 Addition Byte Program Time (After First Byte) 5 10 μs
tPP Page Programming Time 1.6 6 ms
tSE Sector Erase Time 150 500 ms

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tBE1 Block Erase Time (32K Bytes) 0.5 2 s
tBE2 Block Erase Time (64K Bytes) 0.8 3 s
tCE Chip Erase Time (GD25WD80C) 12 30 s
Note:
1. Typical values given for TA=25°C VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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(T= -40℃~105℃, VCC=1.65~3.6V, CL=30pf)

Symbol Parameter Min. Typ. Max. Unit.
Serial Clock Frequency For: Fast read (0BH), on 3.0 – 3.6V
fC1 100 MHz
power supply
Serial Clock Frequency For: Fast read (0BH), on 2.1 – 3.0V
fC2 70 MHz
power supply
Serial Clock Frequency For: Fast read (0BH), on 1.65 – 2.1V
fC3 50 MHz
power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
fR1 80 MHz
3.0 – 3.6V power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
fR2 60 MHz
2.1 – 3.0V power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
fR3 40 MHz
1.65 – 2.1V power supply
tCLH1 Serial Clock High Time for 2.1 – 3.6V Power Supply 4 ns
tCLH2 Serial Clock High Time for 1.65 – 2.1V Power Supply 8 ns
tCLL1 Serial Clock Low Time for 2.1 – 3.6V Power Supply 4 ns
tCLL2 Serial Clock Low Time for 1.65 – 2.1V Power Supply 8 ns
tCLCH Serial Clock Rise Time (Slew Rate) 0.1 V/ns
tCHCL Serial Clock Fall Time (Slew Rate) 0.1 V/ns
tSLCH CS# Active Setup Time 10 ns
tCHSH CS# Active Hold Time 10 ns
tSHCH CS# Not Active Setup Time 10 ns
tCHSL CS# Not Active Hold Time 10 ns
tSHSL CS# High Time (Read/Write) 40 ns
tSHQZ Output Disable Time 12 ns
tCLQX Output Hold Time 0 ns
tDVCH Data In Setup Time 4 ns
tCHDX Data In Hold Time 4 ns
tCLQV Clock Low To Output Valid 12 ns
tWHSL Write Protect Setup Time Before CS# Low 20 ns
tSHWL Write Protect Hold Time After CS# High 100 ns
tDP CS# High To Deep Power-Down Mode 0.1 μs
CS# High To Standby Mode Without Electronic Signature
tRES1 0.1 μs
Read
tRES2 CS# High To Standby Mode With Electronic Signature Read 0.1 μs
tW Write Status Register Cycle Time 5 40 ms
tBP1 Byte Program Time (First Byte) 40 110 μs
tBP2 Addition Byte Program Time (After First Byte) 5 12 μs
tPP Page Programming Time 1.6 6 ms
tSE Sector Erase Time 150 550 ms
tBE1 Block Erase Time (32K Bytes) 0.5 2.2 s

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tBE2 Block Erase Time (64K Bytes) 0.8 3.5 s
tCE Chip Erase Time (GD25WD80C) 12 36 s
Note:
1. Typical values given for TA=25°C VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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(T= -40℃~125℃, VCC=1.65~3.6V, CL=30pf)

Symbol Parameter Min. Typ. Max. Unit.
Serial Clock Frequency For: Fast read (0BH), on 3.0 – 3.6V
fC1 100 MHz
power supply
Serial Clock Frequency For: Fast read (0BH), on 2.1 – 3.0V
fC2 70 MHz
power supply
Serial Clock Frequency For: Fast read (0BH), on 1.65 – 2.1V
fC3 50 MHz
power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
fR1 80 MHz
3.0 – 3.6V power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
fR2 60 MHz
2.1 – 3.0V power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
fR3 40 MHz
1.65 – 2.1V power supply
tCLH1 Serial Clock High Time for 2.1 – 3.6V Power Supply 4 ns
tCLH2 Serial Clock High Time for 1.65 – 2.1V Power Supply 8 ns
tCLL1 Serial Clock Low Time for 2.1 – 3.6V Power Supply 4 ns
tCLL2 Serial Clock Low Time for 1.65 – 2.1V Power Supply 8 ns
tCLCH Serial Clock Rise Time (Slew Rate) 0.1 V/ns
tCHCL Serial Clock Fall Time (Slew Rate) 0.1 V/ns
tSLCH CS# Active Setup Time 10 ns
tCHSH CS# Active Hold Time 10 ns
tSHCH CS# Not Active Setup Time 10 ns
tCHSL CS# Not Active Hold Time 10 ns
tSHSL CS# High Time (Read/Write) 40 ns
tSHQZ Output Disable Time 12 ns
tCLQX Output Hold Time 0 ns
tDVCH Data In Setup Time 4 ns
tCHDX Data In Hold Time 4 ns
tCLQV Clock Low To Output Valid 12 ns
tWHSL Write Protect Setup Time Before CS# Low 20 ns
tSHWL Write Protect Hold Time After CS# High 100 ns
tDP CS# High To Deep Power-Down Mode 0.1 μs
CS# High To Standby Mode Without Electronic Signature
tRES1 0.1 μs
Read
tRES2 CS# High To Standby Mode With Electronic Signature Read 0.1 μs
tW Write Status Register Cycle Time 5 40 ms
tBP1 Byte Program Time (First Byte) 40 120 μs
tBP2 Addition Byte Program Time (After First Byte) 5 14 μs
tPP Page Programming Time 1.6 6 ms
tSE Sector Erase Time 150 600 ms
tBE1 Block Erase Time (32K Bytes) 0.5 2.5 s

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tBE2 Block Erase Time (64K Bytes) 0.8 4 s
tCE Chip Erase Time (GD25WD80C) 12 40 s
Note:
1. Typical values given for TA=25°C VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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Figure22. Serial Input Timing

tSHSL
CS#

tCHSL tSLCH tCHSH tSHCH

SCLK
tDVCH tCHCL
tCHDX tCLCH

SI MSB LSB

SO High-Z

Figure23. Output Timing

CS#
tCLH tSHQZ
SCLK
tCLQV tCLQV tCLL
tCLQX tCLQX
SO LSB

SI
Least significant address bit (LIB) in

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9. ORDERING INFORMATION

GD XX XX XX X X X X X

Packing
T or no mark: Tube
Y: Tray
R: Tape and Reel

Green Code
G: Pb Free + Halogen Free Green Package

Temperature Range
I: Industrial (-40℃ to +85℃)
J: Industrial (-40℃ to +105℃)
E: Industrial (-40℃ to +125℃)
F: Industrial+ (-40℃ to +85℃)
3: Automotive (-40℃ to +85℃)*
2: Automotive (-40℃ to +105℃)*
A: Automotive (-40℃ to +125℃)*

Package Type
T: SOP8 150mil
S: SOP8 208mil
O: TSSOP8 173mil
P: DIP8 300mil
K: USON8 (1.5x1.5mm)
E: USON8 (3x2mm, 0.45mm thickness)

Generation
C: C Version

Density
80: 8M bit

Series
WD: 1.65~3.6V, 4KB Uniform Sector

Product Family
25: SPI Interface Flash

* Please contact GigaDevice sales for automotive products.

37
 Uniform Sector
Standard and Dual Serial Flash GD25WD80C
9.1. Valid Part Numbers

Please contact GigaDevice regional sales for the latest product selection and available form factors.

Temperature Range I: Industrial (-40℃ to +85℃)

Product Number Density Package Type

GD25WD80CTIG 8Mbit SOP8 150mil

GD25WD80CSIG 8Mbit SOP8 208mil
GD25WD80COIG 8Mbit TSSOP8 173mil
GD25WD80CPIG 8Mbit DIP8 300mil
GD25WD80CKIG 8Mbit USON8 (1.5x1.5mm)
GD25WD80CEIG 8Mbit USON8 (3x2mm, 0.45mm thickness)

Temperature Range J: Industrial (-40℃ to +105℃)

Product Number Density Package Type

GD25WD80CTJG 8Mbit SOP8 150mil

GD25WD80CSJG 8Mbit SOP8 208mil
GD25WD80COJG 8Mbit TSSOP8 173mil
GD25WD80CPJG 8Mbit DIP8 300mil
GD25WD80CKJG 8Mbit USON8 (1.5x1.5mm)
GD25WD80CEJG 8Mbit USON8 (3x2mm, 0.45mm thickness)

Temperature Range E: Industrial (-40℃ to +125℃)

Product Number Density Package Type

GD25WD80CTEG 8Mbit SOP8 150mil

GD25WD80CSEG 8Mbit SOP8 208mil
GD25WD80COEG 8Mbit TSSOP8 173mil
GD25WD80CPEG 8Mbit DIP8 300mil
GD25WD80CKEG 8Mbit USON8 (1.5x1.5mm)
GD25WD80CEEG 8Mbit USON8 (3x2mm, 0.45mm thickness)

38
 Uniform Sector
Standard and Dual Serial Flash GD25WD80C
Temperature Range F: Industrial+ (-40℃ to +85℃)

Product Number Density Package Type

GD25WD80CTFG 8Mbit SOP8 150mil

GD25WD80CSFG 8Mbit SOP8 208mil
GD25WD80COFG 8Mbit TSSOP8 173mil
GD25WD80CPFG 8Mbit DIP8 300mil
GD25WD80CKFG 8Mbit USON8 (1.5x1.5mm)
GD25WD80CEFG 8Mbit USON8 (3x2mm, 0.45mm thickness)

39
 Uniform Sector
Standard and Dual Serial Flash GD25WD80C
10. PACKAGE INFORMATION

10.1. Package SOP8 150MIL

D
8 5

E E1

h
L1
L
1 4
“A” θ

b
Base Metal
A A2 c

A1 Detail “A”
b e

Dimensions
Symbol
A A1 A2 b c D E E1 e L L1 h θ
Unit
Min - 0.10 1.25 0.31 0.10 4.80 5.80 3.80 0.40 0.25 0°
mm Nom - 0.15 1.45 0.41 0.20 4.90 6.00 3.90 1.27 - 1.04 - -
Max 1.75 0.25 1.55 0.51 0.25 5.00 6.20 4.00 0.90 0.50 8°
Note:
1. Both the package length and width include the mold flash.
2. Seating plane: Max. 0.1mm.

40
 Uniform Sector
Standard and Dual Serial Flash GD25WD80C
10.2. Package SOP8 208MIL

D
8 5

E E1

L1
L
1 4
“A” θ

b
Base Metal
A A2 c

Detail “A”
A1
b e

Dimensions
Symbol
A A1 A2 b c D E E1 e L L1 θ
Unit
Min - 0.05 1.70 0.31 0.15 5.13 7.70 5.18 0.50 0°
mm Nom - 0.15 1.80 0.41 0.20 5.23 7.90 5.28 1.27 - 1.31 -
Max 2.16 0.25 1.90 0.51 0.25 5.33 8.10 5.38 0.85 8°
Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.

41
 Uniform Sector
Standard and Dual Serial Flash GD25WD80C
10.3. Package TSSOP8 173MIL

D
8 5

E E1

L L1
1 4
“A” θ

b
Base Metal
A A2 c

b A1 Detail “A”
e

Dimensions
Symbol
A A1 A2 b c D E E1 e L L1 θ
Unit
Min - 0.05 0.80 0.19 0.09 2.90 6.20 4.30 0.45 0°
mm Nom - 0.10 1.00 0.25 0.15 3.00 6.40 4.40 0.65 - 1.00 -
Max 1.20 0.15 1.05 0.30 0.20 3.10 6.60 4.50 0.75 8°
Notes:
1. Both package length and width do not include mold flash.
2. Seating plane: Max. 0.1mm.

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 Uniform Sector
Standard and Dual Serial Flash GD25WD80C
10.4. Package DIP8 300MIL

4 1
E

E1

5 8 θ
eA
D

A2 A

A1
L

b1 e

Dimensions
Symbol
A A1 A2 b b1 C D E E1 e L eA θ
Unit
Min - 0.38 3.00 1.14 0.36 0.20 9.02 7.62 6.10 2.92 8.45 0°
mm Nom - - 3.30 1.52 0.46 0.25 9.27 7.87 6.35 2.54 3.30 8.90 -
Max 3.88 - 3.50 1.78 0.56 0.35 9.59 8.26 6.60 3.81 9.35 11°
Note: Both the package length and width do not include the mold flash.

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 Uniform Sector
Standard and Dual Serial Flash GD25WD80C
10.5. Package USON8 (1.5*1.5mm)

A3
D
A2

PIN 1#

A1

A
Top View Side View

L D2
K1
L1 K2
4 5

E2 e

E1 1 8 b

D1 K

Bottom View

Dimensions
Symbol
A A1 A2 A3 b D E D1 E1 D2 E2 e L L1 K K1 K2
Unit
Min 0.40 0.00 0.13 1.40 1.40 0.60 1.20 0.15
0.33 0.127 0.20 0.05 0.40 0.06 0.20 0.10 0.15
mm Nom 0.45 0.02 0.18 1.50 1.50 0.70 1.30 0.20
REF REF REF REF REF REF REF REF REF
Max 0.50 0.05 0.25 1.60 1.60 0.80 1.40 0.25
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package factories. These lead shapes
are compatible with each other.

44
 Uniform Sector
Standard and Dual Serial Flash GD25WD80C
10.6. Package USON8 (3*2mm, thickness 0.45mm)

D c

PIN 1#

A1
A
Top View Side View

8 1 b

E1 e

5 4

L1
D1

Bottom View

Dimensions
Symbol
A A1 c b D D1 E E1 e L L1
Unit
Min 0.40 0.00 0.10 0.20 2.90 0.15 1.90 1.55 0.30
mm Nom 0.45 0.02 0.15 0.25 3.00 0.20 2.00 1.60 0.50 0.35 0.10
Max 0.50 0.05 0.20 0.30 3.10 0.25 2.10 1.65 0.40
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package factories. These lead shapes
are compatible with each other.

45
 Uniform Sector
Standard and Dual Serial Flash GD25WD80C
11. REVISION HISTORY
Version No Description Page Date
1.0 Initial Release All 2018-1-17
Add 4BH command P11
Modify tVSL min value from 5ms to 0.3ms P24
Modify Icc4-8 max value from 15mA to 20mA P29
1.1 Add DC/AC characteristics @-40℃~105℃ P27/31 2018-8-15
Add DC/AC characteristics @-40℃~125℃ P28/32
Modify Ordering Information P36
Add the package of USON8 1.5x1.5mm P43
Modify VWI max value from 1.5V to 1.55V P25
Modify Icc3 typ. value @100MHz from 13mA to 3mA P27, 28, 29
Modify Icc3 typ. value @80MHz from 12mA to 2.5mA P27, 28, 29
Modify Icc3 typ. value @40MHz from 3.5mA to 1.6mA P27, 28, 29
Modify Icc3 typ. value @16MHz from 2.2mA to 1.2mA P27, 28, 29
1.2 Modify Icc3 max. value @100MHz @-40℃ to 85℃ from 18mA P27 2019-4-30
to 6mA
Modify Icc3 max. value @80MHz @-40℃ to 85℃ from 15mA to P27
4.5mA Add Icc3 @50MHz @-40℃-85℃ of 1.3~3.5mA P27
Modify “L” (min) of USON8 1.5x1.5 package from 0.125mm to P44
0.15mm

46
 Uniform Sector
Standard and Dual Serial Flash GD25WD80C

Important Notice

This document is the property of GigaDevice Semiconductor (Beijing) Inc. and its subsidiaries (the "Company"). This
document, including any product of the Company described in this document (the “Product”), is owned by the Company
under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The
Company reserves all rights under such laws and treaties and does not grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. The names and brands of third party referred thereto (if any) are the property
of their respective owner and referred to for identification purposes only.
The Company makes no warranty of any kind, express or implied, with regard to this document or any Product,
including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company
does not assume any liability arising out of the application or use of any Product described in this document. Any information
provided in this document is provided only for reference purposes. It is the responsibility of the user of this document to
properly design, program, and test the functionality and safety of any application made of this information and any resulting
product. Except for customized products which has been expressly identified in the applicable agreement, the Products are
designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only.
The Products are not designed, intended, or authorized for use as components in systems designed or intended for the
operation of weapons, weapons systems, nuclear installations, atomic energy control instruments, combustion control
instruments, airplane or spaceship instruments, traffic signal instruments, life-support devices or systems, other medical
devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or Product could cause personal injury, death, property or
environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling the
Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, and
customers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage,
or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold the
Company as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products.
Customers shall discard the device according to the local environmental law.
Information in this document is provided solely in connection with the Products. The Company reserves the right
to make changes, corrections, modifications or improvements to this document and the Products and services
described herein at any time, without notice.

47