PSoC 3, PSoC 5 TRM

PSoC® 3, PSoC® 5 Architecture TRM

(Technical Reference Manual)

Document No. 001-50235 Rev. *E

December 23, 2010

Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone (USA): 800.858.1810
Phone (Intnl): 408.943.2600
http://www.cypress.com
Copyrights

Copyrights

Copyright © 2008–2010 Cypress Semiconductor Corporation. All rights reserved.

PSoC and CapSense are registered trademarks of Cypress Semiconductor Corporation. PSoC Designer is a trademark of
Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are the property of
their respective owners.

Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Phil-
ips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name, NXP Semicon-
ductors.

The information in this document is subject to change without notice and should not be construed as a commitment by
Cypress. While reasonable precautions have been taken, Cypress assumes no responsibility for any errors that may appear
in this document. No part of this document may be copied, or reproduced for commercial use, in any form or by any means
without the prior written consent of Cypress. Made in the U.S.A.

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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PAR-
TICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein.
Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress
does not authorize its products for use as critical components in life-support systems where a malfunction or failure may rea-
sonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems appli-
cation implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Flash Code Protection

Cypress products meet the specifications contained in their particular Cypress PSoC Datasheets. Cypress believes that its
family of PSoC products is one of the most secure families of its kind on the market today, regardless of how they are used.
There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our
knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guaran-
tee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously improving the code protection features of our products.

2 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Contents Overview

Section A: Overview 21
1. Introduction ........................................................................................................... 23
2. Getting Started ...................................................................................................... 29
3. Document Construction ......................................................................................... 31

Section B: CPU System 35

4. 8051 Core ............................................................................................................. 37
5. Cortex™-M3 Microcontroller .................................................................................. 67
6. PSoC 3 Cache Controller ....................................................................................... 81
7. PSoC 5 Cache Controller ...................................................................................... 87
8. PHUB and DMAC .................................................................................................. 91
9. Interrupt Controller .............................................................................................. 107

Section C: Memory 119

10. Nonvolatile Latch ................................................................................................. 121
11. SRAM ................................................................................................................. 125
12. Flash Program Memory........................................................................................ 129
13. EEPROM............................................................................................................. 131
14. EMIF ................................................................................................................... 133
15. Memory Map ....................................................................................................... 141

Section D: System Wide Resources 145

16. Clocking System .................................................................................................. 147
17. Power Supply and Monitoring .............................................................................. 163
18. Low Power Modes ............................................................................................... 169
19. Watchdog Timer .................................................................................................. 175
20. Reset .................................................................................................................. 179
21. I/O System .......................................................................................................... 187
22. Flash, Configuration Protection ............................................................................ 205

Section E: Digital System 211

23. Universal Digital Blocks (UDBs) ........................................................................... 213
24. UDB Array and Digital System Interconnect ......................................................... 255
25. Controller Area Network (CAN) ............................................................................ 263
26. USB .................................................................................................................... 279
27. Timer, Counter, and PWM .................................................................................... 295

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Contents Overview

28. I 2 C ....................................................................................................................... 311

29. Digital Filter Block (DFB) ..................................................................................... 327

Section F: Analog System 343

30. Switched Capacitor/Continuous Time................................................................... 345
31. Analog Routing ................................................................................................... 359
32. Comparators ....................................................................................................... 375
33. Opamp ................................................................................................................ 379
34. LCD Direct Drive ................................................................................................. 383
35. CapSense ® ..................................................................................................................................... 397
36. Temperature Sensor ............................................................................................ 403
37. Digital-to-Analog Converter ................................................................................. 409
38. Precision Reference ............................................................................................ 413
39. Delta Sigma Converter ........................................................................................ 417
40. Successive Approximation Register ADC ............................................................. 437

Section G: Program and Debug 441

41. Test Controller .................................................................................................... 443
42. 8051 Debug on-Chip ........................................................................................... 455
43. Cortex-M3 Debug and Trace................................................................................ 465
44. Nonvolatile Memory Programming ....................................................................... 473

Glossary 479
Index 495

4 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Contents

Section A: Overview 21
Document Revision History ..............................................................................................................21
1. Introduction 23
1.1 Top Level Architecture............................................................................................................23
1.2 Features..................................................................................................................................26
1.3 CPU System ...........................................................................................................................26
1.3.1 Processor...............................................................................................................26
1.3.2 Interrupt Controller .................................................................................................26
1.3.3 DMA Controller ......................................................................................................26
1.3.4 Cache Controller ....................................................................................................26
1.4 Memory...................................................................................................................................26
1.5 System Wide Resources ........................................................................................................27
1.5.1 I/O Interfaces .........................................................................................................27
1.5.2 Internal Clock Generators ......................................................................................27
1.5.3 Power Supply.........................................................................................................27
1.5.3.1 Boost Converter .....................................................................................27
1.5.3.2 Sleep Modes ..........................................................................................27
1.6 Digital System.........................................................................................................................27
1.7 Analog System........................................................................................................................28
1.7.1 Delta Sigma ADC...................................................................................................28
1.7.2 Successive Approximation Register ADC..............................................................28
1.7.3 Digital Filter Block ..................................................................................................28
1.7.4 Digital-to-Analog Converters..................................................................................28
1.7.5 Additional Analog Subsystem Components...........................................................28
1.8 Program and Debug ...............................................................................................................28
2. Getting Started 29
2.1 Support ...................................................................................................................................29
2.2 Product Upgrades...................................................................................................................29
2.3 Development Kits ...................................................................................................................29
3. Document Construction 31
3.1 Major Sections ........................................................................................................................31
3.2 Documentation Conventions ..................................................................................................31
3.2.1 Register Conventions.............................................................................................31
3.2.2 Numeric Naming ....................................................................................................32
3.2.3 Units of Measure....................................................................................................32
3.2.4 Acronyms ...............................................................................................................32
Section B: CPU System 35
Top Level Architecture .....................................................................................................................35

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Contents

4. 8051 Core 37
4.1 Features ................................................................................................................................. 37
4.2 Block Diagram ........................................................................................................................ 37
4.3 How It Works .......................................................................................................................... 38
4.3.1 Memory Spaces ..................................................................................................... 38
4.3.2 Instruction Set........................................................................................................ 38
4.3.3 8051 Core Enhancements ..................................................................................... 38
4.3.4 Interrupt Controller Interface.................................................................................. 38
4.4 CY 8051 Wrapper................................................................................................................... 39
4.4.1 SFR – I/O Interface................................................................................................ 39
4.5 8051 Instructions .................................................................................................................... 39
4.5.1 Internal Data Space Map ....................................................................................... 39
4.5.2 Addressing Modes ................................................................................................. 39
4.5.3 Arithmetic Logic Unit Functions ............................................................................. 40
4.5.3.1 Arithmetic Instructions............................................................................ 40
4.5.3.2 Logical Instructions ................................................................................ 41
4.5.3.3 Data Transfer Instructions...................................................................... 42
4.5.3.4 Boolean Instructions1............................................................................. 43
4.5.3.5 Program Branching Instructions............................................................. 43
4.5.3.6 Instruction Set Details ............................................................................ 44
4.6 8051 Special Function Registers (SFRs) ............................................................................... 62
4.6.1 SFRs......................................................................................................................62
4.6.2 Dual Data Pointer SFRs ........................................................................................ 63
4.6.3 24-Bit Data Pointer SFRs ...................................................................................... 64
4.6.4 I/O Port Access SFRs............................................................................................ 65
4.6.5 Interrupt Enable (IE) ..............................................................................................65
4.7 Program and External Data Spaces ....................................................................................... 66
4.7.1 Program Space ...................................................................................................... 66
4.7.2 External Data Space ..............................................................................................66
4.8 CPU Halt Mechanisms ...........................................................................................................66
5. Cortex™-M3 Microcontroller 67
5.1 Features ................................................................................................................................. 67
5.2 How it Works .......................................................................................................................... 69
5.2.1 Registers ............................................................................................................... 69
5.2.1.1 Special Registers ................................................................................... 71
5.2.2 Operating Modes ................................................................................................... 72
5.2.3 Pipelining ............................................................................................................... 73
5.2.4 Thumb-2 Instruction Set ........................................................................................ 73
5.2.4.1 Data Processing Operations .................................................................. 73
5.2.4.2 Load Store Operations ........................................................................... 74
5.2.4.3 Branch Operations ................................................................................. 74
5.2.4.4 Instruction Barrier and Memory Barrier Instructions............................... 74
5.2.4.5 Saturation Operations ............................................................................ 74
5.2.5 SysTick Timer ........................................................................................................ 74
5.2.6 Debug and Trace: .................................................................................................. 75
5.3 Memory Map........................................................................................................................... 75
5.3.1 Bus Interface to SRAM Memory ............................................................................ 75
5.4 Exceptions .............................................................................................................................. 76
5.4.1 Priority Definitions.................................................................................................. 77
5.4.2 Fault Exceptions .................................................................................................... 77
5.4.3 System Call Exceptions ......................................................................................... 78
5.5 Nested Vector Interrupt Controller (NVIC).............................................................................. 78

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5.5.1 Basic Interrupt Configuration .................................................................................79

5.5.1.1 Example Procedures in Setting Up an Interrupt .....................................79
5.5.2 Nested Interrupts ...................................................................................................79
5.5.3 Tail-Chaining Interrupts ..........................................................................................79
5.5.4 Late Arrivals ...........................................................................................................79
5.5.5 Interrupt Latency ....................................................................................................80
5.5.6 Faults Related to Interrupts....................................................................................80
6. PSoC 3 Cache Controller 81
6.1 Features..................................................................................................................................81
6.2 Block Diagram ........................................................................................................................81
6.3 Cache Memory Organization and Addressing ........................................................................82
6.3.1 Cache Operation....................................................................................................83
6.3.2 Cache Line Locking: ..............................................................................................83
6.3.3 Cache Line Loading in Firmware ...........................................................................83
6.3.4 Cache Line Replacement Policy ............................................................................83
6.3.5 Background Fill (BFILL): ........................................................................................84
6.3.6 ECC (Error Correction Code).................................................................................84
6.3.6.1 Interrupts ................................................................................................84
6.3.7 Flash Low Power Mode .........................................................................................85
7. PSoC 5 Cache Controller 87
7.1 Features..................................................................................................................................87
7.2 Block Diagram ........................................................................................................................87
7.3 Cache Enabling and Disabling................................................................................................88
7.4 Code Protection and Security .................................................................................................88
7.5 Invalidating the Cache Line ....................................................................................................88
7.5.1 Measuring Cache Hits or Misses ...........................................................................88
7.6 Cache Induced Flash Low Power Mode .................................................................................88
7.7 Sleep Mode Behavior .............................................................................................................88
7.8 Cache Limitations ...................................................................................................................88
8. PHUB and DMAC 91
8.1 PHUB......................................................................................................................................91
8.1.1 Features.................................................................................................................91
8.1.2 Block Diagram........................................................................................................91
8.1.3 How It Works..........................................................................................................92
8.1.4 Arbiter ....................................................................................................................93
8.2 DMA Controller .......................................................................................................................93
8.2.1 Local Memory ........................................................................................................93
8.2.2 How the DMAC Works ...........................................................................................93
8.2.2.1 Interspoke Transfers ..............................................................................94
8.2.2.2 Intraspoke Transfer ................................................................................95
8.2.2.3 Handling Multiple DMA Channels...........................................................96
8.2.2.4 DMA Channel Priority.............................................................................96
8.2.2.5 DMA Latency in case of Nonideal Conditions ........................................98
8.2.2.6 Request per Burst Bit ...........................................................................103
8.2.2.7 Work Sep Bit ........................................................................................104
8.3 DMA Transaction Modes ......................................................................................................104
8.3.1 Simple DMA .........................................................................................................104
8.3.2 Auto Repeat DMA ................................................................................................104
8.3.3 Ping Pong DMA ...................................................................................................104
8.3.4 Circular DMA........................................................................................................104

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Contents

8.3.5 7.3.5 Indexed DMA ..............................................................................................104

8.3.6 Scatter Gather DMA ............................................................................................105
8.3.7 Packet Queuing DMA ..........................................................................................105
8.3.8 Nested DMA ........................................................................................................105
8.4 Register List .........................................................................................................................106
9. Interrupt Controller 107
9.1 Features ...............................................................................................................................107
9.2 Block Diagram ......................................................................................................................107
9.3 How It Works ........................................................................................................................108
9.3.1 Enabling Interrupts...............................................................................................108
9.3.2 Pending Interrupts ...............................................................................................109
9.3.3 Interrupt Priority ...................................................................................................109
9.3.4 Level versus Pulse Interrupt ................................................................................ 110
9.3.5 Interrupt Execution .............................................................................................. 110
9.4 PSoC 3 Features ..................................................................................................................112
9.4.1 Active Interrupts................................................................................................... 112
9.4.2 Interrupt Nesting .................................................................................................. 112
9.4.3 Interrupt Vector Addresses .................................................................................. 113
9.4.4 Sleep Mode Behavior .......................................................................................... 113
9.5 PSoC 5 Features ..................................................................................................................114
9.5.1 Active Interrupts................................................................................................... 114
9.5.2 Interrupt Nesting .................................................................................................. 114
9.5.3 Interrupt Vector Addresses .................................................................................. 116
9.5.4 Tail Chaining ........................................................................................................ 116
9.5.5 Late Arrival Interrupts .......................................................................................... 116
9.5.6 Exceptions ........................................................................................................... 117
9.5.7 Interrupt Masking ................................................................................................. 117
9.6 Interrupt Controller and Power Modes..................................................................................117
Section C: Memory 119
Top Level Architecture ...................................................................................................................119
10. Nonvolatile Latch 121
10.1 Features ...............................................................................................................................121
10.2 Device Configuration NV Latch ............................................................................................121
10.2.1 PRTxRDM[1:0].....................................................................................................121
10.2.2 XRESMEN ...........................................................................................................122
10.2.3 CFGSPEED .........................................................................................................122
10.2.4 DPS[1:0] ..............................................................................................................122
10.2.5 ECCEN ................................................................................................................122
10.2.6 DIG_PHS_DLY[3:0] .............................................................................................122
10.3 Write Once NV Latch............................................................................................................122
10.4 Programming NV Latch ........................................................................................................123
10.5 Sleep Mode Behavior ...........................................................................................................123
11. SRAM 125
11.1 Features ...............................................................................................................................125
11.2 Block Diagram ......................................................................................................................125
11.3 How It Works ........................................................................................................................128
12. Flash Program Memory 129
12.1 Features ...............................................................................................................................129
12.2 Block Diagram ......................................................................................................................129

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 Contents

12.3 How It Works ........................................................................................................................130

12.4 ECC Error Detection and Interrupts......................................................................................130
13. EEPROM 131
13.1 Features................................................................................................................................131
13.2 Block Diagram ......................................................................................................................131
13.3 How It Works ........................................................................................................................132
14. EMIF 133
14.1 Features................................................................................................................................133
14.2 Block Diagram ......................................................................................................................133
14.3 How It Works ........................................................................................................................134
14.3.1 List of EMIF Registers..........................................................................................134
14.3.2 External Memory Support ....................................................................................134
14.3.3 Sleep Mode Behavior...........................................................................................137
14.4 EMIF Timing .........................................................................................................................138
14.5 Using EMIF with Memory-Mapped Peripherals ....................................................................140
14.6 Additional Configuration Guidelines......................................................................................140
14.6.1 Address Bus Configuration ..................................................................................140
14.6.2 Data Bus Configuration........................................................................................140
14.6.3 16-bit Memory Transfers ......................................................................................140
14.6.4 8-bit Memory Transfers ........................................................................................140
15. Memory Map 141
15.1 Features................................................................................................................................141
15.2 Block Diagram ......................................................................................................................141
15.3 How It Works ........................................................................................................................141
15.3.1 PSoC 3 Memory Map...........................................................................................142
15.3.2 PSoC 5 Memory Map...........................................................................................143
Section D: System Wide Resources 145
Top Level Architecture ...................................................................................................................145
16. Clocking System 147
16.1 Features................................................................................................................................147
16.2 Block Diagram ......................................................................................................................148
16.3 Clock Sources.......................................................................................................................148
16.3.1 Internal Oscillators ...............................................................................................148
16.3.1.1 Internal Main Oscillator.........................................................................149
16.3.1.2 Internal Low Speed Oscillator ..............................................................149
16.3.2 External Oscillators ..............................................................................................150
16.3.2.1 MHz Crystal Oscillator.........................................................................150
16.3.2.2 32.768 kHz Crystal Oscillator ...............................................................151
16.3.3 Oscillator Summary..............................................................................................152
16.3.4 DSI Clocks ...........................................................................................................152
16.3.5 Phase-Locked Loop .............................................................................................153
16.4 Clock Distribution..................................................................................................................154
16.4.1 Master Clock Mux ................................................................................................155
16.4.2 USB Clock............................................................................................................156
16.4.3 Clock Dividers ......................................................................................................157
16.4.3.1 Single Cycle Pulse Mode .....................................................................157
16.4.3.2 50% Duty Cycle Mode..........................................................................157
16.4.3.3 Early Phase Option ..............................................................................158
16.4.4 Clock Synchronization .........................................................................................158

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16.4.5 Phase Selection and Control ...............................................................................159

16.4.6 Divider Update .....................................................................................................160
16.4.7 Power Gating of Clock Outputs ...........................................................................160
16.4.8 System Clock.......................................................................................................160
16.4.9 Asynchronous Clocks ..........................................................................................160
16.5 Low Power Mode Operation .................................................................................................160
16.6 Clock Naming Summary.......................................................................................................161
17. Power Supply and Monitoring 163
17.1 Features ...............................................................................................................................163
17.2 Block Diagram ......................................................................................................................164
17.3 How It Works ........................................................................................................................165
17.3.1 Regulator Summary.............................................................................................165
17.3.1.1 Internal Regulators...............................................................................165
17.3.1.2 Sleep Regulator ...................................................................................165
17.3.1.3 Hibernate Regulator .............................................................................165
17.3.2 Boost Converter...................................................................................................166
17.3.2.1 Modes of Operation..............................................................................166
17.3.2.2 Status Monitoring .................................................................................166
17.3.3 Voltage Monitoring ...............................................................................................167
17.3.3.1 Low Voltage Interrupt ...........................................................................167
17.3.3.2 High Voltage Interrupt ..........................................................................167
17.3.3.3 Processing a Low/High Voltage Detect Interrupt .................................168
17.3.3.4 Reset on a Voltage Monitoring Interrupt ..............................................168
17.4 Register Summary................................................................................................................168
18. Low Power Modes 169
18.1 Features ...............................................................................................................................169
18.2 Active Mode..........................................................................................................................171
18.2.1 Entering Active Mode ..........................................................................................171
18.2.2 Exiting Active Mode .............................................................................................171
18.3 Alternative Active Mode........................................................................................................171
18.3.1 Entering Alternative Active Mode ........................................................................171
18.3.2 Exiting Alternative Active Mode ...........................................................................171
18.4 Sleep Mode ..........................................................................................................................171
18.4.1 Entering Sleep Mode ...........................................................................................171
18.4.2 Exiting Sleep Mode..............................................................................................172
18.5 Hibernate Mode ....................................................................................................................172
18.5.1 Entering Hibernate Mode.....................................................................................172
18.5.2 Exiting Hibernate Mode .......................................................................................172
18.6 Timewheel ............................................................................................................................172
18.6.1 Central Timewheel (CTW) ...................................................................................172
18.6.2 Fast Timewheel (FTW) ........................................................................................172
18.7 Register List .........................................................................................................................173
19. Watchdog Timer 175
19.1 Features ...............................................................................................................................175
19.2 Block Diagram ......................................................................................................................175
19.3 How It Works ........................................................................................................................176
19.3.1 Enabling and Disabling the WDT.........................................................................176
19.3.2 Setting the WDT Time Period and Clearing the WDT .........................................176
19.3.3 Operation in Low Power Modes ..........................................................................176
19.3.4 Watchdog Protection Settings .............................................................................176

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19.4 Register List .........................................................................................................................177

20. Reset 179
20.1 Reset Sources ......................................................................................................................179
20.1.1 Power-on Reset ...................................................................................................179
20.1.2 Watchdog Reset ..................................................................................................179
20.1.3 Software Initiated Reset.......................................................................................179
20.1.4 External Reset .....................................................................................................179
20.1.5 Identifying Reset Sources ....................................................................................180
20.2 Reset Diagram......................................................................................................................180
20.3 Reset Summary ....................................................................................................................181
20.4 Boot Process and Timing......................................................................................................182
20.4.1 Manufacturing Configuration NV Latch ................................................................183
20.4.1.1 Device Configuration NV Latch ............................................................183
20.4.2 Boot Phase ..........................................................................................................183
20.4.3 User Mode ...........................................................................................................184
20.5 Register List .........................................................................................................................185
21. I/O System 187
21.1 Features................................................................................................................................187
21.2 Block Diagrams.....................................................................................................................188
21.3 How It Works ........................................................................................................................190
21.3.1 Usage Modes and Configuration .........................................................................190
21.3.2 I/O Drive Modes ...................................................................................................191
21.3.2.1 Drive Mode on Reset............................................................................192
21.3.2.2 High Impedance Analog .......................................................................192
21.3.2.3 High Impedance Digital ........................................................................192
21.3.2.4 Resistive Pull Up or Resistive Pull Down .............................................192
21.3.2.5 Open Drain, Drives High and Drives Low.............................................192
21.3.2.6 Strong Drive .........................................................................................192
21.3.2.7 Resistive Pull Up and Pull Down ..........................................................192
21.3.3 Slew Rate Control ................................................................................................192
21.3.4 Digital I/O Controlled by Port Register .................................................................192
21.3.4.1 Port Configuration Registers ................................................................193
21.3.4.2 Pin Wise Configuration Register Alias..................................................193
21.3.4.3 Port Wide Configuration Register Alias ................................................194
21.3.5 SFR to GPIO........................................................................................................194
21.3.6 Digital I/O Controlled Through DSI ......................................................................194
21.3.6.1 DSI Output............................................................................................194
21.3.6.2 DSI Input ..............................................................................................195
21.3.6.3 DSI for Output Enable Control..............................................................195
21.3.7 Analog I/O ............................................................................................................196
21.3.8 LCD Drive ............................................................................................................196
21.3.9 CapSense ............................................................................................................197
21.3.10 External Memory Interface (EMIF).......................................................................197
21.3.11 SIO Functions and Features ................................................................................197
21.3.11.1 Regulated Output Level........................................................................197
21.3.11.2 Adjustable Input Level ..........................................................................197
21.3.11.3 Hot Swap..............................................................................................198
21.3.12 Special Functionality ............................................................................................198
21.3.13 I/O Port Reconfiguration ......................................................................................200
21.3.14 Power Up I/O Configuration .................................................................................200
21.3.15 Overvoltage Tolerance .........................................................................................200

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21.3.16 I/O Power Supply.................................................................................................200

21.3.17 Sleep Mode Behavior ..........................................................................................200
21.3.18 Low Power Behavior............................................................................................200
21.4 Port Interrupt Controller Unit.................................................................................................201
21.4.1 Features ..............................................................................................................201
21.4.2 Interrupt Controller Block Diagram ......................................................................201
21.4.3 Function and Configuration .................................................................................202
21.5 Register Summary................................................................................................................202
22. Flash, Configuration Protection 205
22.1 Flash Protection....................................................................................................................205
22.2 Device Security.....................................................................................................................206
22.3 Configuration Segment Protection........................................................................................206
22.3.1 Locking/Unlocking Segment Configuration Register ...........................................207
22.3.2 Locking and Protecting Segments .......................................................................207
22.3.3 Example...............................................................................................................209
22.4 Frequently Asked Questions About Best Practices for Flash Protection and Device Security...
209
Section E: Digital System 211
Top Level Architecture ...................................................................................................................212
23. Universal Digital Blocks (UDBs) 213
23.1 Features ...............................................................................................................................213
23.2 Block Diagram ......................................................................................................................213
23.3 How It Works ........................................................................................................................214
23.3.1 PLDs ....................................................................................................................214
23.3.1.1 PLD Macrocells ....................................................................................215
23.3.1.2 PLD Carry Chain ..................................................................................217
23.3.1.3 PLD Configuration................................................................................217
23.3.2 Datapath ..............................................................................................................217
23.3.2.1 Overview ..............................................................................................219
23.3.2.2 Datapath FIFOs....................................................................................220
23.3.2.3 FIFO Status..........................................................................................227
23.3.2.4 Datapath ALU.......................................................................................227
23.3.2.5 Datapath Inputs and Multiplexing.........................................................230
23.3.2.6 CRC/PRS Support ...............................................................................230
23.3.2.7 Datapath Outputs and Multiplexing ......................................................233
23.3.2.8 Datapath Parallel Inputs and Outputs ..................................................235
23.3.2.9 Datapath Chaining ...............................................................................235
23.3.2.10 Dynamic Configuration RAM................................................................236
23.3.3 Status and Control Module ..................................................................................237
23.3.3.1 Status and Control Mode .....................................................................238
23.3.3.2 Control Register Operation ..................................................................240
23.3.3.3 Parallel Input/Output Mode ..................................................................241
23.3.3.4 Counter Mode ......................................................................................242
23.3.3.5 Sync Mode ...........................................................................................243
23.3.3.6 Status and Control Clocking.................................................................243
23.3.3.7 Auxiliary Control Register.....................................................................243
23.3.3.8 Status and Control Register Summary.................................................244
23.3.4 Reset and Clock Control Module .........................................................................244
23.3.4.1 Clock Control........................................................................................245
23.3.4.2 Reset Control .......................................................................................247

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23.3.4.3 UDB POR Initialization .........................................................................249

23.3.5UDB Addressing ..................................................................................................250
23.3.5.1 Working Register Address Space ........................................................250
23.3.5.2 Configuration Register Address Space ................................................252
23.3.5.3 UDB Configuration Address Space ......................................................252
23.3.5.4 Routing Configuration Address Space .................................................252
23.3.6 System Bus Access Coherency...........................................................................253
23.3.6.1 Simultaneous System Bus Access.......................................................253
23.3.6.2 Coherent Accumulator Access (Atomic Reads and Writes) .................253
23.4 UDB Working Register Reference ........................................................................................254
24. UDB Array and Digital System Interconnect 255
24.1 Features................................................................................................................................255
24.2 Block Diagram ......................................................................................................................255
24.3 How It Works ........................................................................................................................256
24.4 UDB Array System Interface ................................................................................................258
24.4.1 UDB Array POR Initialization ...............................................................................258
24.4.2 UDB POR Configuration Sequence ....................................................................259
24.4.2.1 Quadrant Route Disable ......................................................................260
24.4.3 UDB Sleep and Power Control ...........................................................................260
24.4.4 UDB Register References and Address Mapping................................................260
25. Controller Area Network (CAN) 263
25.1 Features................................................................................................................................263
25.2 Block Diagram ......................................................................................................................264
25.3 CAN Message Frames .........................................................................................................264
25.3.1 Data Frames ........................................................................................................264
25.3.1.1 Standard Data Frame...........................................................................264
25.3.1.2 Extended Data Frame ..........................................................................265
25.3.2 Remote Frame .....................................................................................................266
25.3.3 Error Frame..........................................................................................................266
25.3.4 Overload Frame ...................................................................................................266
25.4 Transmitting Messages in CAN ............................................................................................266
25.4.1 Message Arbitration .............................................................................................268
25.4.2 Message Transmit Process .................................................................................268
25.4.3 Message Abort.....................................................................................................269
25.4.4 Transmitting Extended Data Frames ...................................................................269
25.5 Receiving Messages in CAN ................................................................................................269
25.5.1 Message Receive Process ..................................................................................270
25.5.2 Acceptance Filter .................................................................................................270
25.5.2.1 Example ...............................................................................................270
25.5.3 DeviceNet Filtering...............................................................................................272
25.5.4 Filtering of Extended Data Frames ......................................................................272
25.5.5 Receiver Message Buffer Linking ........................................................................273
25.6 Remote Frames ....................................................................................................................273
25.6.1 Transmitting a Remote Frame by the Requesting Node......................................274
25.6.2 Receiving a Remote Frame .................................................................................274
25.6.3 RTR Auto Reply ...................................................................................................274
25.6.4 Remote Frames in Extended Format...................................................................274
25.7 Bit Time Configuration ..........................................................................................................274
25.7.1 Allowable Bit Rates and System Clock (CLK_BUS) ............................................274
25.7.2 Setting Bit Rate TSEG1 and TSEG2 ...................................................................275
25.7.2.1 Example ...............................................................................................276

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25.8 Error Handling and Interrupts in CAN...................................................................................276

25.8.1 Types of Errors ....................................................................................................276
25.8.1.1 BIT Error...............................................................................................276
25.8.1.2 FORM Error..........................................................................................276
25.8.1.3 ACKNOWLEDGE Error........................................................................276
25.8.1.4 CRC Error ............................................................................................276
25.8.1.5 STUFF Error.........................................................................................277
25.8.2 Error States in CAN .............................................................................................277
25.8.3 Interrupt Sources in CAN.....................................................................................277
25.9 Operating Modes in CAN......................................................................................................278
25.9.1 Listen Only Mode.................................................................................................278
25.9.2 Run/Stop Mode....................................................................................................278
26. USB 279
26.1 Features ...............................................................................................................................279
26.2 Block Diagram ......................................................................................................................280
26.2.1 Serial Interface Engine (SIE) ...............................................................................281
26.2.2 Arbiter ..................................................................................................................282
26.2.2.1 SIE Interface Module............................................................................282
26.2.2.2 CPU Interface Block.............................................................................282
26.2.2.3 Memory Interface .................................................................................282
26.2.2.4 DMA Interface ......................................................................................282
26.2.2.5 Arbiter Logic .........................................................................................282
26.2.2.6 Synchronization Block..........................................................................283
26.3 How it Works ........................................................................................................................283
26.3.1 Operating Frequency ...........................................................................................283
26.3.2 Operating Voltage ................................................................................................283
26.3.3 Transceiver ..........................................................................................................283
26.3.4 Endpoints.............................................................................................................284
26.3.5 Transfer Types.....................................................................................................284
26.3.6 Interrupts..............................................................................................................284
26.4 Logical Transfer Modes ........................................................................................................285
26.4.1 Store and Forward Mode .....................................................................................286
26.4.1.1 No DMA Access ...................................................................................286
26.4.1.2 Manual DMA Access............................................................................287
26.4.2 Cut Through Mode...............................................................................................289
26.4.3 Control Endpoint Logical Transfer .......................................................................291
26.5 PS/2 and CMOS I/O Modes .................................................................................................292
26.6 Register List .........................................................................................................................293
27. Timer, Counter, and PWM 295
27.1 Features ...............................................................................................................................295
27.2 Block Diagram ......................................................................................................................295
27.3 How It Works ........................................................................................................................296
27.3.1 Clock Selection ....................................................................................................296
27.3.2 Enabling and Disabling Block ..............................................................................297
27.3.3 Input Signal Characteristics .................................................................................297
27.3.3.1 Enable Signal .......................................................................................298
27.3.3.2 Capture Signal .....................................................................................298
27.3.3.3 Timer Reset Signal...............................................................................300
27.3.3.4 Kill Signal .............................................................................................300
27.3.4 Operating Modes .................................................................................................301
27.3.4.1 Timer Mode – Free Run Mode .............................................................301

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27.3.4.2 Gated Timer Mode ...............................................................................302

27.3.4.3 Pulse-width Modulator Mode................................................................306
27.3.4.4 One Shot Mode ....................................................................................309
27.3.5 Interrupt Enabling.................................................................................................309
27.3.6 Sleep Mode Behavior...........................................................................................310
27.4 Register Listing .....................................................................................................................310

28. I 2C 311
28.1 Features................................................................................................................................311
28.2 Block Diagram ......................................................................................................................311
28.3 Background Information........................................................................................................313
28.3.1 I2C Bus Description..............................................................................................313
28.3.2 Typical I2C Data Transfer.....................................................................................313
28.4 How It Works ........................................................................................................................313
28.4.1 Bus Stalling (Clock Stretching).............................................................................314
28.4.2 System Management Bus....................................................................................314
28.4.3 Pin Connections...................................................................................................314
28.4.4 I2C Interrupts .......................................................................................................314
28.4.5 Control by Registers ............................................................................................314
28.4.6 Operating the I2C Interface ..................................................................................315
28.4.6.1 Slave Mode ..........................................................................................316
28.4.6.2 Master Mode ........................................................................................317
28.4.6.3 Multi-Master Mode................................................................................318
28.5 Hardware Address Compare ................................................................................................318
28.6 Wake from Sleep ..................................................................................................................318
28.7 Slave Mode Transfer Examples............................................................................................319
28.7.1 Slave Receive ......................................................................................................320
28.7.2 Slave Transmit .....................................................................................................321
28.8 Master Mode Transfer Examples..........................................................................................322
28.8.1 Single Master Receive .........................................................................................322
28.8.2 Single Master Transmit ........................................................................................323
28.9 Multi-Master Mode Transfer Examples.................................................................................324
28.9.1 Multi-Master, Slave Not Enabled..........................................................................324
28.9.2 Multi-Master, Slave Enabled ................................................................................325
29. Digital Filter Block (DFB) 327
29.1 Features................................................................................................................................327
29.2 Block Diagram ......................................................................................................................327
29.3 How It Works ........................................................................................................................328
29.3.1 Controller .............................................................................................................328
29.3.1.1 FSM RAM.............................................................................................329
29.3.1.2 Program Counter..................................................................................330
29.3.1.3 Control Store ........................................................................................330
29.3.1.4 Next State Decoder ..............................................................................330
29.3.2 Datapath ..............................................................................................................331
29.3.2.1 MAC .....................................................................................................332
29.3.2.2 ALU ......................................................................................................332
29.3.2.3 Shifter and Rounder .............................................................................332
29.3.3 Address Calculation Unit......................................................................................333
29.3.4 Bus Interface and Register Descriptions..............................................................333
29.3.4.1 Streaming Mode ...................................................................................333
29.3.4.2 Block Transfer Modes ..........................................................................334
29.3.4.3 Result Handling ....................................................................................335

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29.3.4.4 Data Alignment.....................................................................................337

29.3.4.5 DMA and Semaphores.........................................................................337
29.3.4.6 DSI Routed Inputs and Outputs ...........................................................337
29.4 DFB Instruction Set ..............................................................................................................338
29.5 Usage Model ........................................................................................................................341
Section F: Analog System 343
Top Level Architecture ...................................................................................................................343
30. Switched Capacitor/Continuous Time 345
30.1 Features ...............................................................................................................................345
30.2 Block Diagram ......................................................................................................................345
30.3 How it Works ........................................................................................................................347
30.3.1 Operational Mode of Block is Set ........................................................................347
30.4 Naked Opamp ......................................................................................................................347
30.4.1 Bandwidth/Stability Control ..................................................................................347
30.4.1.1 BIAS_CONTROL .................................................................................347
30.4.1.2 SC_COMP[1:0] ....................................................................................348
30.4.1.3 SC_REDC[1:0] .....................................................................................348
30.5 Continuous Time Unity Gain Buffer ......................................................................................349
30.6 Continuous Time Programmable Gain Amplifier ..................................................................349
30.7 Continuous Time Transimpedance Amplifier........................................................................350
30.8 Continuous Time Mixer.........................................................................................................352
30.9 Sampled Mixer......................................................................................................................353
30.10 Delta Sigma Modulator .........................................................................................................355
30.10.1 First-Order Modulator, Incremental Mode............................................................356
30.11 Track and Hold Amplifier ......................................................................................................357
31. Analog Routing 359
31.1 Features ...............................................................................................................................359
31.2 Block Diagram ......................................................................................................................359
31.3 How it Works ........................................................................................................................362
31.3.1 Analog Globals (AGs) ..........................................................................................362
31.3.2 Analog Mux Bus (AMUXBUS) .............................................................................362
31.3.3 Liquid Crystal Display Bias Bus (LCDBUS) .........................................................362
31.3.4 Analog Local Bus (abus) .....................................................................................364
31.3.5 Switches and Multiplexers ...................................................................................364
31.3.5.1 Control of Analog Switches ..................................................................364
31.4 Analog Resource Blocks – Routing and Interface ................................................................366
31.4.1 Digital-to-Analog Converter (DAC) ......................................................................367
31.4.2 Comparator..........................................................................................................368
31.4.3 Delta Sigma Modulator (DSM).............................................................................369
31.4.4 Switched Capacitor..............................................................................................370
31.4.5 Opamp .................................................................................................................371
31.4.6 Low Pass Filter (LPF) ..........................................................................................371
31.5 Low Power Analog Routing Considerations .........................................................................372
31.5.1 Mitigating Analog Routes with Degraded Low Power Signal Integrity .................372
31.6 Analog Routing Register Summary ......................................................................................373
32. Comparators 375
32.1 Features ...............................................................................................................................375
32.2 Block Diagram ......................................................................................................................375
32.3 How it Works ........................................................................................................................376
32.3.1 Input Configuration ..............................................................................................376

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32.3.2 Power Configuration ............................................................................................376

32.3.3 Output Configuration............................................................................................376
32.3.4 Hysteresis ............................................................................................................377
32.3.5 Wake Up from Sleep ............................................................................................377
32.3.6 Comparator Clock ................................................................................................377
32.3.7 Offset Trim ...........................................................................................................377
32.3.8 Register Summary ...............................................................................................378
33. Opamp 379
33.1 Features...............................................................................................................................379
33.2 Block Diagram ......................................................................................................................380
33.3 How it Works.........................................................................................................................380
33.3.1 Input and Output Configuration............................................................................380
33.3.2 Power Configuration ............................................................................................380
33.3.3 Buffer Configuration .............................................................................................381
33.3.4 Register Summary ...............................................................................................381
34. LCD Direct Drive 383
34.1 Features................................................................................................................................383
34.2 LCD System Operational Modes ..........................................................................................383
34.3 LCD Always Active ...............................................................................................................384
34.3.1 Functional Description .........................................................................................385
34.3.1.1 LCD DAC..............................................................................................385
34.3.1.2 LCD Driver Block..................................................................................386
34.3.1.3 UDB......................................................................................................389
34.3.1.4 DMA .....................................................................................................389
34.4 LCD Low Power Mode..........................................................................................................389
34.4.1 Functional Description .........................................................................................391
34.4.1.1 LCD Timer ............................................................................................391
34.4.1.2 UDB......................................................................................................391
34.4.1.3 DMA .....................................................................................................392
34.4.1.4 LCD DAC and Driver: Low Power Feature...........................................392
34.4.2 Timing Diagram for LCD Low Power Mode..........................................................393
34.5 LCD Usage Models...............................................................................................................395

35. CapSense ® 397

35.1 Features................................................................................................................................397
35.2 Block Diagram ......................................................................................................................397
35.3 How It Works ........................................................................................................................398
35.3.1 Reference Driver..................................................................................................398
35.3.2 Low Pass Filter ....................................................................................................398
35.3.3 Analog Mux Bus...................................................................................................398
35.3.4 GPIO Configuration for CapSense.......................................................................398
35.3.5 Other Resources..................................................................................................399
35.4 CapSense Delta Sigma Algorithm ........................................................................................400
36. Temperature Sensor 403
36.1 Features................................................................................................................................403
36.2 Block Diagram ......................................................................................................................403
36.3 How It Works ........................................................................................................................404
36.4 Command and Status Interface ............................................................................................404
36.4.1 Status Codes........................................................................................................405
36.4.2 Temperature Sensor Commands .........................................................................405

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36.4.2.1 Get Temperature..................................................................................405

36.4.2.2 Setup Temperature Sensor..................................................................406
36.4.2.3 Disable Temperature Sensor ...............................................................407
37. Digital-to-Analog Converter 409
37.1 Features ...............................................................................................................................409
37.2 Block Diagram ......................................................................................................................409
37.3 How It Works ........................................................................................................................410
37.3.1 Current DAC ........................................................................................................410
37.3.2 Voltage DAC ........................................................................................................410
37.3.3 Output Routing Options .......................................................................................410
37.3.4 Making a Higher Resolution DAC ........................................................................ 411
37.4 Register List .........................................................................................................................412
38. Precision Reference 413
38.1 Block Diagram ......................................................................................................................413
38.2 How It Works ........................................................................................................................413
39. Delta Sigma Converter 417
39.1 Features ...............................................................................................................................417
39.2 Block Diagram ......................................................................................................................417
39.3 How It Works ........................................................................................................................418
39.3.1 Input Buffer ..........................................................................................................418
39.3.2 Delta Sigma Modulator .......................................................................................419
39.3.2.1 Clock Selection ....................................................................................420
39.3.2.2 Capacitance Configuration...................................................................420
39.3.2.3 Gain Configuration ...............................................................................421
39.3.2.4 Power Configuration.............................................................................422
39.3.2.5 Other Configuration Options ................................................................426
39.3.2.6 Quantizer..............................................................................................426
39.3.2.7 Reference Options ...............................................................................426
39.3.2.8 Reference for DSM: Usage Guidelines ................................................429
39.3.3 Analog Interface ..................................................................................................430
39.3.3.1 Conversion of Thermometric Code to Two’s Complement ..................431
39.3.3.2 Modulation Input...................................................................................431
39.3.3.3 Clock Selection and Synchronization...................................................431
39.3.4 Decimator ............................................................................................................431
39.3.4.1 Shifters .................................................................................................431
39.3.4.2 CIC Filter ..............................................................................................432
39.3.4.3 Post Processing Filter ..........................................................................432
39.3.5 Coherency Protection ..........................................................................................433
39.3.5.1 Protecting Writes (Gain/Offset) with Coherency Checking ..................433
39.3.5.2 Protecting Reads (Output Sample) with Coherency Checking ............433
39.3.6 Modes of Operation .............................................................................................434
40. Successive Approximation Register ADC 437
40.1 Features ...............................................................................................................................437
40.2 How It Works ........................................................................................................................438
40.2.1 Input Selection .....................................................................................................438
40.2.2 Clock Selection ....................................................................................................438
40.2.3 Input Sampling.....................................................................................................438
40.2.4 Power Modes.......................................................................................................438
40.2.5 Reference Selection ............................................................................................438
40.2.6 Operational Modes ..............................................................................................438

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 Contents

40.2.7 SAR ADC Output .................................................................................................439

Section G: Program and Debug 441
Top Level Architecture ...................................................................................................................441
41. Test Controller 443
41.1 Features................................................................................................................................443
41.2 Block Diagram ......................................................................................................................443
41.3 Background Information........................................................................................................444
41.3.1 JTAG Interface .....................................................................................................444
41.3.2 Serial Wire Debug Interface.................................................................................447
41.4 How It Works on PSoC 3 and PSoC 5 Devices....................................................................448
41.4.1 Clocking ...............................................................................................................448
41.4.2 PSoC 3 and PSoC 5 JTAG Instructions...............................................................448
41.4.3 DP/AP Access Register .......................................................................................449
41.4.4 JTAG/SWD Addresses (PSoC 3) .........................................................................449
41.4.5 Debug Port and Access Port Registers (PSoC 3)................................................450
41.4.6 PSoC 3 Register Access Examples.....................................................................450
41.4.7 Debug Port and Access Port Registers (PSoC 5)................................................450
41.5 Boundary Scan Pin Order.....................................................................................................451
41.6 Test Controller Interface Pins ...............................................................................................452
41.7 Test Controller Acquisition....................................................................................................452
41.7.1 Changing Interface from SWD to JTAG ...............................................................452
41.7.2 Changing Interface from JTAG to SWD ...............................................................452
41.7.3 Boundary Scan ....................................................................................................452
41.7.4 Functional Test.....................................................................................................452
41.7.5 Programming Flash/EEPROM .............................................................................452
41.7.6 Program Debug/Trace .........................................................................................453
42. 8051 Debug on-Chip 455
42.1 Features................................................................................................................................455
42.2 Block Diagram ......................................................................................................................456
42.3 How it Works.........................................................................................................................457
42.3.1 Enabling and Activating .......................................................................................457
42.3.2 Halting, Stepping..................................................................................................457
42.3.3 Accessing PSoC Memory And Registers.............................................................457
42.3.4 Breakpoints ..........................................................................................................458
42.3.4.1 Program Address Breakpoints .............................................................458
42.3.4.2 Memory Access Breakpoint..................................................................458
42.3.4.3 Watchdog Trigger Breakpoint...............................................................458
42.3.4.4 Breakpoint Chaining .............................................................................458
42.3.5 CPU Reset ...........................................................................................................459
42.3.6 Tracing Program Execution .................................................................................459
42.3.6.1 Reading Traces ....................................................................................460
42.3.6.2 Trace Time Stamp................................................................................460
42.3.7 DOC Registers.....................................................................................................461
42.4 Serial Wire Viewer ................................................................................................................461
42.4.1 SWV Protocols.....................................................................................................461
42.4.1.1 Manchester Encoding...........................................................................462
42.4.1.2 UART Encoding....................................................................................462
42.4.2 SWV Registers.....................................................................................................463
43. Cortex-M3 Debug and Trace 465
43.1 Features................................................................................................................................465

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43.2 How It Works ........................................................................................................................466

43.2.1 Test Controller (TC) ............................................................................................466
43.2.2 PSoC 5 JTAG Instructions ...................................................................................467
43.2.2.1 Debug Port and Access Port Registers................................................467
43.2.2.2 Test Controller Interface Pins...............................................................467
43.2.3 TRACEPORT.......................................................................................................467
43.3 Core Debug ..........................................................................................................................467
43.3.1 Enabling the Debug .............................................................................................467
43.3.2 Halting .................................................................................................................467
43.3.3 Stepping...............................................................................................................467
43.3.4 Accessing PSoC Memory and Registers.............................................................468
43.4 System Debug ......................................................................................................................468
43.4.1 Flash Patch and Breakpoint (FPB) Unit...............................................................468
43.4.2 Data Watchpoint and Trace (DWT)......................................................................469
43.4.3 Instrumentation Trace Macrocell (ITM) ................................................................469
43.4.4 Embedded Trace Macrocell (ETM)......................................................................470
43.5 Tracing Interface...................................................................................................................470
43.5.1 Single Wire Viewer (SWV)...................................................................................471
43.5.1.1 Enabling SWV ......................................................................................471
43.5.1.2 Communicating with SWV....................................................................471
43.5.2 TRACEPORT.......................................................................................................471
43.5.2.1 Enabling TRACEPORT ........................................................................471
43.5.2.2 Communicating with TRACEPORT......................................................471
43.5.3 Using Multiple Interfaces Simultaneously ............................................................471
44. Nonvolatile Memory Programming 473
44.1 Features ...............................................................................................................................473
44.2 Block Diagram ......................................................................................................................473
44.3 How It Works ........................................................................................................................474
44.3.1 Commands ..........................................................................................................474
44.3.1.1 Command Code Descriptions ..............................................................475
44.3.1.2 Command Failure Codes .....................................................................477
44.3.2 Register Summary ...............................................................................................477
44.3.3 Flash Protection Settings.....................................................................................477

Glossary 479

Index 495

20 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Section A: Overview

This document encompasses the PSoC® 3 CY8C38 Family and the PSoC® 5 CY8C55 Family. In conjunction with the device
datasheet, it contains complete and detailed information about how to use and design with the IP blocks that construct a
PSoC 3 or PSoC 5 device. This document describes the analog and digital architecture to give the designer a better under-
standing of features and limitations of PSoC 3. The routing of both digital and analog signals should be left to the tool
(PSoC Creator™). Hand routing, analog or digital, by use of registers, may conflict with the routing performed by PSoC Cre-
ator and produce unexpected results.
This section encompasses the following chapters:
■ Introduction chapter on page 23
■ Getting Started chapter on page 29
■ Document Construction chapter on page 31

See the PSoC® 3 Registers TRM (Technical Reference Manual) and the PSoC® 5 Registers TRM (Technical Reference Man-
ual) for complete register sets.

Document Revision History

Table 1-1. PSoC® 3, PSoC® 5 Architecture TRM (Technical Reference Manual) Revision History
Origin of
Revision Issue Date Description of Change
Change
** 12.15.2008 HMT Preliminary release of the PSoC 3: CY8C38 Family Technical Reference Manual.
*A 02.12.2009 HMT Release for ES10.
*B 06.22.2009 HMT Initial silicon release.
*C 07.14.2009 HMT Initial non NDA release.
*D 09.08.2009 DSG Addressed many issues, changes throughout document.
*E 12.23.2010 DSG Document rewrite to reflect product development.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 21

 Section A: Overview

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 22

 1. Introduction

With a unique array of configurable digital and analog blocks, the Programmable System-on-Chip (PSoC®) is a true system-
level solution, offering a modern method of signal acquisition, processing, and control with exceptional accuracy, high band-
width, and superior flexibility. Its analog capability spans the range from thermocouples (DC voltages) to ultrasonic signals.

PSoC 3 (CY8C38xxxx, CY8C36xxx, CY8C34xxx, CY8C32xxx) and PSoC 5 (CY8C55xxx, CY8C54xxx, CY8C53xxx,
CY8C52xxx) families are fully scalable 8-bit and 32-bit PSoC platform devices that share these characteristics:
■ Fully pin, peripheral compatible
■ Same integrated development environment software
■ High performance, configurable digital system that supports a wide range of communication interfaces, such as USB, I2C,
and CAN
■ High precision, high performance analog system with up to 20-bit ADC, DACs, comparators, opamps, and programmable
blocks to create PGAs, TIAs, mixers, etc.
■ Easily configurable logic array
■ Flexible routing to all pins
■ High performance, 8-bit single-cycle 8051 (PSoC 3) or 32-bit ARM Cortex-M3 (PSoC 5) core

This document describes PSoC 3 and PSoC 5 devices in detail. Using this information, designers can easily create system-
level designs, using a rich library of prebuilt components, or custom verilog, and a schematic entry tool that uses the standard
design blocks. PSoC 3 and PSoC 5 devices provide unparalleled opportunities for analog and digital bill of materials (BOM)
integration, while easily accommodating last-minute design changes.

1.1 Top Level Architecture

Figure 1-1 on page 24 shows the major components of PSoC 3 architecture and Figure 1-2 on page 25 shows the major
components of PSoC 5 devices. The PSoC 3 device uses the 8051 core and the PSoC 5 device uses the 32-bit Cortex M3
core.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 23

Introduction

Figure 1-1. Top Level Architecture for PSoC 3 Devices

Analog Interconnect
Digital Interconnect

SIO
SYSTEM WIDE DIGITAL SYSTEM
GPIOs

Universal Digital Block Array (N x UDB)

4 to 33 MHz
RESOURCES Quadrature Decoder 16-Bit PWM 16-Bit PRS
CAN I2C
8-Bit 2.0 Master/Slave

Usage Example for UDB

(Optional) Timer

Sequencer
UDB UDB UDB UDB

Xtal
FS USB USB
Osc
Clock Tree UDB UDB UDB UDB
8-Bit Nx 2.0 PHY
8-Bit SPI Timer
I2C Slave
12-Bit SPI
Logic Timer,
Counter,
UDB UDB UDB UDB
PWM
GPIOs

IMO

GPIOs
Logic
32.768 kHz
UDB UDB UDB UDB
(Optional)
UART 12-Bit PWM

RTC
Timer
SYSTEM BUS

GPIOs
MEMORY SYSTEM CPU SYSTEM Program,
WDT Debug
and 8051 CPU Interrupt
EEPROM SRAM Program
Wake Controller
Debug,
GPIOs

Trace
EMIF FLASH PHUB
Boundary
DMA
ILO Scan

Clocking System

GPIOs
Digital
ANALOG SYSTEM
Power Management LCD Direct
SIOs

System
Filter +
Drive
Block ADCs Nx
POR and Opamp 3 per
LVD –
Auxiliary Opamp
N x SC/CT Blocks ADC
Sleep (TIA, PGA, Mixer, etc.)
Power
+
1.71 to

Temperature

GPIOs
5.5 V

Sensor Nx Nx
1.8-V LDO
N x DAC DEL SIG CMP
ADC –
SMP CapSense

0.5 to 5.5 V
(Optional)

24 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Introduction

Figure 1-2. Top Level Architecture for PSoC 5 Devices

Analog Interconnect
Digital Interconnect

SIO
SYSTEM WIDE DIGITAL SYSTEM
GPIOs

Universal Digital Block Array (N x UDB)

4 to 33 MHz
RESOURCES Quadrature Decoder 16-Bit PWM 16-Bit PRS
CAN I2C
8-Bit 2.0 Master/Slave

Usage Example for UDB

(Optional) Timer

Sequencer
UDB UDB UDB UDB

Xtal D+
FS USB USB
Osc

Clock Tree
UDB UDB UDB UDB
8-Bit Nx 2.0 PHY D-
8-Bit SPI Timer
I2C Slave
12-Bit SPI
Logic Timer,
Counter,
UDB UDB UDB UDB
PWM
GPIOs

IMO

GPIOs
Logic
32.768 kHz
UDB UDB UDB UDB
(Optional)
UART 12-Bit PWM

RTC
Timer
SYSTEM BUS

GPIOs
MEMORY SYSTEM CPU SYSTEM Program,
WDT Debug
and Cortex-M3 CPU Interrupt
EEPROM SRAM Program
Wake Controller
Debug,
GPIOs

Trace
EMIF FLASH PHUB
Boundary
DMA
ILO Scan

Clocking System

GPIOs
Digital
ANALOG SYSTEM
Power Management LCD Direct
SIOs

System
Filter +
Drive
Block Nx
ADCs Opamp
POR and N x SAR 3 per
LVD ADC –
Opamp
N x SC/CT Blocks
Sleep (TIA, PGA, Mixer, etc.)
Power Auxiliary
ADC
+
1.71 to

Temperature

GPIOs
5.5 V

1.8-V LDO Sensor Nx

N x DAC Nx CMP
DEL SIG –
SMP CapSense ADC

0.5 to 5.5 V
(Optional)

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 25

Introduction

1.2 Features interrupt service routine, bypassing the jump instruction

required by other architectures.
PSoC 3 and PSoC 5 devices have these major compo-
The PSoC 5 interrupt controller also offers a few advanced
nents. See Figure 1-1 on page 24 and Figure 1-2 on
interrupt management capabilities, such as interrupt tail
page 25.
chaining to improve stack management with multiple pend-
■ 8051 or Cortex-M3 Central Processing Unit (CPU) with a ing interrupts providing lower latency.
nested vectored interrupt controller and a high perfor-
mance DMA controller
1.3.3 DMA Controller
■ Several types of memory elements including SRAM,
flash, and EEPROM The DMA controller allows peripherals to exchange data
without CPU involvement. This allows the CPU to run
■ System integration features, such as clocking, a feature-
slower, save power, or use its cycles to improve the perfor-
rich power system, and versatile programmable inputs
mance of firmware algorithms.
and outputs
■ Digital system that includes configurable Universal Digi-
1.3.4 Cache Controller
tal Blocks (UDBs) and specific function peripherals, such
as CAN and USB In PSoC 5 devices, the flash cache also reduces system
■ Analog subsystem that includes configurable switched power consumption by reducing the frequency with which
capacitor (SC) and continuous time (CT) blocks, up to flash is accessed. The processor speed itself is configurable
20-bit Delta Sigma converters, 8-bit DACs that can be allowing for active power consumption tuned for specific
configured for 12-bit operation, more than one SAR applications.
ADC, comparators, PGAs, and more
■ Programming and debug system through JTAG, Serial 1.4 Memory
Wire Debug (SWD), and Single Wire Viewer (SWV)
The PSoC nonvolatile subsystem consists of Flash, byte-
writable EEPROM, and nonvolatile configuration options.
1.3 CPU System The CPU can reprogram individual blocks of Flash, enabling
The PSoC 3 and PSoC 5 CPUs are different. These sec- boot loaders. An Error Correcting Code (ECC) can enable
tions discuss the differences. high reliability applications.

A powerful and flexible protection model allows the user to

1.3.1 Processor selectively lock blocks of memory for read and write protec-
PSoC 3 and PSoC 5 CPUs are different. These sections tion, securing sensitive information. The byte-writable
discuss the differences: EEPROM is available on-chip for the storage of application
data. Additionally, selected configuration options, such as
■ PSoC 3 CPU subsystem is built around an 8-bit single
boot speed and pin drive mode, are stored in nonvolatile
cycle pipelined 8051 processor, running up to 67 MHz.
memory, allowing settings to become active immediately
The single cycle 8051 CPU runs ten times faster than a
after power on reset (POR).
standard 8051 processor. The PSoC 3 instruction set is
compatible with the original MCS-51 instruction set.
■ The PSoC 5 CPU subsystem is built around a 32-bit
three stage pipelined ARM Cortex-M3 processor running
up to 80 MHz. The PSoC 5 instruction set is the same as
the Thumb-2 instruction set available on standard Cor-
tex- M3 devices.

1.3.2 Interrupt Controller

The CPU subsystem includes a programmable Nested Vec-
tored Interrupt Controller (NVIC), DMA (Direct Memory
Access) controller, Flash cache ECC, and RAM. The NVIC
of both PSoC 3 and PSoC 5 devices provides low latency by
allowing the CPU to vector directly to the first address of the

26 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Introduction

1.5 System Wide Resources 1.5.3 Power Supply

The individual elements of system wide resources are dis- PSoC 3 and PSoC 5 devices support extensive supply oper-
cussed in these sections. ating ranges from 1.7 V to 5.5 V, allowing operation from
regulated supplies such as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ±
10%, 5.0V ± 10%, or directly from a wide range of battery
1.5.1 I/O Interfaces
types.
PSoC 3 and PSoC 5 devices have three I/O types:
■ General Purpose Input/Output (GPIO) – Every GPIO 1.5.3.1 Boost Converter
has analog I/O, digital I/O, LCD drive, CapSense®, flexi- The PSoC platform provides an integrated high efficiency
ble interrupt, and slew rate control capability. All I/Os synchronous boost converter that is used to power the
have a large number of drive modes that are set at POR. device from supply voltages as low as 0.5V. This converter
PSoC 3 and PSoC 5 devices also provide up to four indi- enables the device to power directly from a single battery or
vidual I/O voltage domains through the VDDIO pins. solar cell. A user can employ the boost converter to gener-
■ Special Input/Output (SIO) – The SIOs on PSoC 3 and ate other voltages required by the device, such as a 3.3 V
PSoC 5 devices allow the user to set VOH indepen- supply for LCD glass drive. The boost output is available on
dently of VDDIO when used as outputs. When SIOs are the VBOOST pin, allowing other devices in the application to
in input mode, they are high impedance, even when the draw power from the PSoC device.
device is not powered or when the pin voltage goes
above the supply voltage. This makes the SIO ideally 1.5.3.2 Sleep Modes
suited for use on an I2C bus where the PSoC 3 and
The PSoC platform supports five low power sleep modes,
PSoC 5 devices are not powered, even though other
from the lowest current RAM retention mode (hibernation) to
devices on the bus are powered. The SIO pins also have
the full function active mode. A 1.0 A RTC mode runs the
high current sink capability for applications such as LED
optional 32.768 kHz watch crystal continuously to drive the
drive.
RTC timer that is used to maintain RTC. Power to all major
■ USB Input/Output (USBIO) – For devices with Full functional blocks, including the programmable digital and
Speed USB, the USB physical interface is also provided analog peripherals, is controlled independently by firmware.
(USBIO). When not using USB, these pins can be used
for limited digital functionality and device programming. This function allows low power background processing
when some peripherals are not in use.

1.5.2 Internal Clock Generators

PSoC devices incorporate flexible internal clock generators,
1.6 Digital System
designed for high stability and factory-trimmed for absolute The digital subsystems of PSoC 3 and PSoC 5 devices pro-
accuracy. The Internal Main Oscillator (IMO) is the master vide these devices their first half of unique configurability.
clock base for the system with 1% absolute accuracy at 3
MHz. The IMO can be configured to run from 3 MHz up to The subsystem connects a digital signal from any peripheral
48 MHz. Multiple clock derivatives are generated from the to any pin through the Digital System Interconnect (DSI). It
main clock frequency to meet application needs. also provides functional flexibility through an array of small,
fast, low-power Universal Digital Blocks (UDBs).
PSoC 3 and PSoC 5 devices provide a PLL to generate sys-
tem clock frequencies up to the maximum operating fre- Each UDB contains Programmable Array Logic (PAL) and
quency of the device (67 MHz or 80 MHz, respectively). The Programmable Logic Device (PLD) functionality, together
PLL can be driven from the IMO, an external crystal, or an with a small state machine engine to support a wide variety
external reference clock. The devices also contain a sepa- of peripherals.
rate, very low power Internal Low Speed Oscillator (ILO) for In addition to the flexibility of the UDB array, PSoC devices
the sleep and watchdog timers. The ILO provides two pri- provide configurable digital blocks targeted at specific func-
mary outputs, 1 kHz and 100 kHz. A 32.768 kHz external tions.
watch crystal is also supported for use in Real Time Clock
(RTC) applications. The clocks, together with programmable These blocks include 16-bit timer/counter/PWM blocks, I2C
clock dividers, provide the flexibility to integrate most timing slave/master/multi-master, Full Speed USB, and CAN 2.0b.
requirements See the device data sheet for a list of available specific func-
tion digital blocks.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 27

Introduction

1.7 Analog System 1.7.4 Digital-to-Analog Converters

The PSoC analog subsystem provides the device the sec- Four high speed voltage or current DACs support 8-bit out-
ond half of its unique configurability. All analog performance put signals at waveform frequencies up to 8 MHz and can
is based on a highly accurate absolute voltage reference be routed out of any GPIO pin. These DACs can be com-
with less than ±0.1% error over temperature and voltage. bined together to create a higher resolution 12-bit DAC.

The configurable analog subsystem includes: Higher resolution voltage DAC outputs are created using the
UDB array to create a pulse width modulated (PWM) DAC of
■ Analog muxes
up to 10 bits, at up to 48 kHz. The digital DACs in each UDB
■ Comparators support PWM, PRS, or Delta Sigma algorithms with pro-
■ Voltage references grammable widths.
■ Opamps
■ Mixers 1.7.5 Additional Analog Subsystem
■ Trans Impedance Amplifiers (TIA)
Components
■ Analog-to-Digital Converters (ADC) In addition to the ADCs, DACs, and the DFB, the analog
subsystem provides components such as multiple compara-
■ Digital-to-Analog Converters (DAC)
tors, uncommitted opamps, and configurable Switched
■ Digital Filter Block (DFB) Capacitor/Continuous Time (SC/CT) blocks supporting trans
All GPIO pins can route analog signals into and out of the impedance amplifiers, programmable gain amplifiers, and
device, using the internal analog bus. This feature allows mixers.
the device to interface up to 62 discrete analog signals.
1.8 Program and Debug
1.7.1 Delta Sigma ADC
TAG (4-wire) or Serial Wire Debugger (SWD) (2-wire) inter-
The heart of the analog subsystem is a fast, accurate, con-
faces are used for programming and debug. The 1-wire Sin-
figurable Delta Sigma ADC. With less than 100 µV offset, a
gle Wire Viewer (SWV) can also be used for “printf” style
gain error of ±0.1%, Integral Non-Linearity (INL) less than 1
debugging. By combining SWD and SWV, the designer can
LSB, Differential Non-Linearity (DNL) less than 0.5 LSB, and
implement a full debugging interface with just three pins.
signal-to-noise ratio (SNR) better than 90 dB (Delta Sigma)
in 16-bit mode, this converter addresses a wide variety of Using these standard interfaces enables the designer to
precision analog applications, including some of the most debug or program the PSoC device with a variety of hard-
demanding sensors. ware solutions from Cypress or third party vendors.

PSoC 3 and PSoC 5 devices support on-chip break points,

1.7.2 Successive Approximation and an instruction and data trace memory for debug. The
Register ADC PSoC 5 device offers many more advanced debugging fea-
tures, such as Flash patch breakpoint capability to update
Another type of ADC seen on PSoC 3 and PSoC 5 devices
instructions without reprogramming, fast “printf” style debug-
is the Successive Approximation Register (SAR) ADC. Fea-
ging using the Trace Port Interface Unit (TPIU) module,
turing 12-bit conversions at up to 1 Msps, it offers low non-
clock cycle counting capability, and various other features
linearity, low offset errors, and an SNR better than 70 dB; it
with Data Watchpoint and Trace (DWT) modules. JTAG also
is well suited for a variety of higher-speed analog applica-
supports standard JTAG scan chains for board level test
tions. Some PSoC devices offer both types of ADC and can
and chaining multiple JTAG devices.
have multiple instances of each. See the device datasheet
for specific details.

1.7.3 Digital Filter Block

The output of the ADC can optionally feed the programma-
ble Digital Filter Block (DFB) via DMA without CPU interven-
tion. The DFB can be configured to perform IIR and FIR
digital filters and a variety of user defined custom functions.
The DFB can implement filters with up to 64 taps.

28 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 2. Getting Started

The quickest path to understanding any PSoC® device is to read the device datasheet and use PSoC Designer™ or
PSoC Creator™ Integrated Development Environments (IDEs) software. This technical reference manual helps to under-
stand the details of the PSoC 3 and PSoC 5 integrated circuit and its implementation.

For the most up-to-date ordering, packaging, or electrical specification information, refer to the individual PSoC device’s data-
sheet or go to http://www.cypress.com/psoc.

2.1 Support
Free support for PSoC products is available online at http://www.cypress.com. Resources include Training Seminars, Discus-
sion Forums, Application Notes, PSoC Consultants, TightLink Technical Support Email/Knowledge Base, and Application
Support Technicians.

Applications Assistance can be reached at http://www.cypress.com/support/ or by phone at:

1-800-541-4736.

2.2 Product Upgrades

Cypress provides scheduled upgrades and version enhancements for PSoC Creator free of charge. Upgrades are available
from your distributor on CD-ROM or download them directly from http://www.cypress.com under the Software tab. Also pro-
vided are critical updates to system documentation under the Documentation tab.

2.3 Development Kits

Development Kits are available from Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development
kits, C compilers, and the accessories you need to successfully develop PSoC projects. Go to the Cypress Online Store web
site at http://www.cypress.com/shop/. Under Product Categories click PSoC (Programmable System-on-Chip) to view a cur-
rent list of available items.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 29

Getting Started

30 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 3. Document Construction

The content sections of this technical reference manual start after this section – Section A: Overview on page 21. The follow-
ing sections include these topics:
■ Section B: CPU System on page 35
■ Section C: Memory on page 119
■ Section D: System Wide Resources on page 145
■ Section E: Digital System on page 211
■ Section F: Analog System on page 343
■ Section G: Program and Debug on page 441

3.1 Major Sections

The major sections of the technical reference manual are:
■ Sections – Presents the top-level architecture, how to get started and conventions and overview information about any
particular area that help inform the reader about the construction and organization of the product.
■ Chapter – Presents the chapters specific to some individual aspect of the Section topic. These are the detailed implemen-
tation and use information for some aspect of the integrated circuit.
■ Glossary – Defines the specialized terminology used in this technical reference manual. Glossary terms are presented in
bold, italic font throughout.
■ PSoC® 3 Registers TRM (Technical Reference Manual) and the PSoC® 5 Registers TRM (Technical Reference Manual)
– Supply all device register details summarized in the technical reference manual. These are additional documents.

For ease of use, information is organized into sections and chapters that are divided according to device functionality. Each
section begins with some interpretation detail and contains a top level architectural explanation. This is followed by chapters
that contain detailed explanation required for the implementation and use of the individual functions described. The PSoC® 3
Registers TRM (Technical Reference Manual) and the PSoC® 5 Registers TRM (Technical Reference Manual) are contained
in separate .pdf files.

3.2 Documentation Conventions

There are only four distinguishing font types used in this document, besides those found in the headings.
■ The first is the use of italics when referencing a document title or file name.
■ The second is the use of bold italics when referencing a term described in the Glossary of this document.
■ The third is the use of Times New Roman font, distinguishing equation examples.
■ The fourth is the use of Courier New font, distinguishing code examples.

3.2.1 Register Conventions

Register conventions are detailed in the PSoC® 3 Registers TRM (Technical Reference Manual) and the PSoC® 5 Registers
TRM (Technical Reference Manual).

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 31

Document Construction

3.2.2 Numeric Naming 3.2.4 Acronyms

Hexadecimal numbers are represented with all letters in This table lists the acronyms that are used in this document
uppercase with an appended lowercase ‘h’ (for example,
‘14h’ or ‘3Ah’) and hexadecimal numbers may also be repre- Table 3-2. Acronyms
sented by a ‘0x’ prefix, the C coding convention. Binary Symbol Unit of Measure
numbers have an appended lowercase ‘b’ (for example, ABUS analog output bus
01010100b’ or ‘01000011b’). Numbers not indicated by an AC alternating current
‘h’ or ‘b’ are decimal. ADC analog-to-digital converter
API application programming interface
3.2.3 Units of Measure APOR analog power-on reset

This table lists the units of measure used in this document. BC broadcast clock
BIFC bit implemented functioning connection
Table 3-1. Units of Measure BINC bit implemented no connection
Symbol Unit of Measure BOM bill of materials
°C degrees Celsius BR bit rate
dB decibels BRA bus request acknowledge
fF femtofarads BRQ bus request
Hz Hertz CAN controller area network
k kilo, 1000 CBUS comparator bus
K kilo, 2^10 CI carry in
KB 1024 bytes, or approximately one thousand bytes CMP compare
Kbit 1024 bits CMRR common mode rejection ratio
kHz kilohertz (32.000) CO carry out
k kilohms CPU central processing unit
MHz megahertz CRC cyclic redundancy check
M megaohms CT continuous time
µA microamperes DAC digital-to-analog converter
µF microfarads DAP debug access port on ARM Cortex™-M3 of PSoC 5
µs microseconds DC direct current
µV microvolts DFB digital filter block
µVrms microvolts root-mean-square DOC debug on-chip module/block in PSoC 3
mA milliamperes DoC debug on-chip mode in PSoC 3 and PSoC 5
ms milliseconds DI digital or data input
mV millivolts DMA direct memory access
nA nanoamperes DMAC direct memory access controller
ns nanoseconds DNL differential nonlinearity
nV nanovolts DO digital or data output
 ohms DSI digital signal interface
pF picofarads ECO external crystal oscillator
pp peak-to-peak EEPROM electrically erasable programmable read only memory
ppm parts per million EMIF external memory interface
SPS samples per second FB feedback
 sigma: one standard deviation FSR full scale range
V volts GIE global interrupt enable
GPIO general purpose I/O

I2C inter-integrated circuit

ICE In-circuit emulator

IDE integrated development environment

32 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Document Construction

Table 3-2. Acronyms (continued) Table 3-2. Acronyms (continued)

Symbol Unit of Measure Symbol Unit of Measure
ILO internal low-speed oscillator RW read/write
IMO internal main oscillator SAR successive approximation register
INL integral nonlinearity SC switched capacitor
I/O input/output SIE serial interface engine
IOR I/O read SIO special I/O
IOW I/O write SE0 single-ended zero
IRES initial power on reset SNR signal-to-noise ratio
IRA interrupt request acknowledge SOF start of frame
IRQ interrupt request SOI start of instruction
ISR interrupt service routine SP stack pointer
ISSP In-system serial programming SPD sequential phase detector
IVR interrupt vector read SPI serial peripheral interconnect
LFSR linear feedback shift register SPIM serial peripheral interconnect master
LRb last received bit SPIS serial peripheral interconnect slave
LRB last received byte SRAM static random-access memory
LSb least significant bit SROM supervisory read only memory
LSB least significant byte SSADC single slope ADC
LUT lookup table SSC supervisory system call
MISO master-in-slave-out SWD single wire debug
MOSI master-out-slave-in SWV single wire viewer
MSb most significant bit TC terminal count
MSB most significant byte TD transaction descriptors
nested vectored interrupt controller on Cortex-M3 of TIA transimpedance amplifier
NVIC
PSoC 5
UDB universal digital block
PC program counter
USB universal serial bus
PCH program counter high
USBIO USB I/O
PCL program counter low
VCO voltage controlled oscillator
PD power down
WDT watchdog timer
PGA programmable gain amplifier
WDR watchdog reset
PHUB peripheral hub
XRES_N external reset, active low
PICU port interrupt control unit
PM power management
PMA PSoC memory arbiter
POR power-on reset
PPOR precision power-on reset
PRS pseudo random sequence
® Programmable System-on-Chip
PSoC
PSRAM pseudo SRAM
PSRR power supply rejection ratio
PSSDC power system sleep duty cycle
PVT process voltage temperature
PWM pulse-width modulator
RAM random-access memory
RAS row address strobe
RETI return from interrupt
RO relaxation oscillator
ROM read only memory

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 33

Document Construction

34 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Section B: CPU System

The PSoC® 3 and PSoC® 5 Central Processing Units (CPUs) are different. The PSoC 3 8051 CPU subsystem is built around
a single cycle pipelined 8051 8-bit processor, running up to 67 MHz. The single cycle 8051 CPU runs ten times faster than a
standard 8051 processor. The PSoC 3 instruction set is compatible with the original MCS-51 instruction set. The PSoC 5 CPU
subsystem is built around a 32-bit three stage pipelined ARM Cortex-M3 processor running up to 80 MHz.

This section encompasses the following chapters:

■ 8051 Core chapter on page 37
■ Cortex™-M3 Microcontroller chapter on page 67
■ PHUB and DMAC chapter on page 91
■ Interrupt Controller chapter on page 107

Top Level Architecture

PSoC 3, PSoC 5 CPU System Block Diagram

System Bus

CPU SYSTEM
8051 or Interrupt
Cortex M3 CPU Controller
MEMORY PROGRAM
SYSTEM and DEBUG

PHUB
DMA

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 35

 Section B: CPU System

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 36

 4. 8051 Core

The PSoC® 3 CY8C38xx 8051 core is a high performance, speed optimized 8-bit Central Processing Unit (CPU). It is 100%
binary compatible with the industry standard 8051. The CY8C38 family includes wrapper logic around the 8051 core. This
wrapper includes internal data Random Access Memory (RAM), an external data space interface, a Special Function Register
– Input/Output (SFR – I/O) interface, and a CPU clock divider.

4.1 Features
The PSoC 3 8051 has the following features:
■ Pipelined RISC architecture that executes ten times faster than the industry standard 8051
■ 100% binary compatible with the industry standard 8051 instruction set
■ Most instructions executed in one or two cycles
■ 256 bytes of internal data RAM
■ Dual DPTR extension to the standard 8051 architecture
■ 24-bit external data space that enables access to on-chip memory and registers, and to off-chip memory
■ New interrupt interface that enables direct interrupt vectoring. See 4.3.4 Interrupt Controller Interface on page 38
■ New special function registers (SFRs) enable fast access to PSoC 3 I/O ports

4.2 Block Diagram

Figure 4-1 on page 38 shows a diagram of the wrapper around the 8051 and its interface to different blocks on the device.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 37

8051 Core

Figure 4-1. CY8C38 Family 8051 Wrapper Block Diagram

8051 WRAPPER

8051 CPU
Program
Flash
Memory
Memory
Interface

External
SRAM
Data Interrupt Interrupt
Memory Interface Controller
PHUB Interface

Internal Internal
Data Data Debug
RAM Memory on-Chip
(256x8) Interface

Special
SFR to
I/O Function
I/O
Ports Registers
Interface
(SFRs)

4.3 How It Works

The PSoC 3 8051 core is fully compatible with the standard See 4.5.3 Arithmetic Logic Unit Functions on page 40.
8051 microcontroller, maintaining all instruction mnemon-
ics and binary compatibility. The CY8C38 8051 core incor- 4.3.3 8051 Core Enhancements
porates enhancements that allow it to execute instructions
with high performance. The PSoC 3 8051 core has several enhancements:
■ Dual DPTRs – see 4.6.2 Dual Data Pointer SFRs on
4.3.1 Memory Spaces page 63
■ 24-bit external data space with DPTR extension SFRs –
The PSoC 3 8051 memory map is very similar to the stan-
see 4.6.3 24-Bit Data Pointer SFRs on page 64
dard 8051 memory map. There are separate address
spaces for program and data memory. The data space is ■ Vectored interrupt controller interface removes the need
further divided into internal and external data spaces. See for hard interrupt vectors in the program space – see
4.5.1 Internal Data Space Map on page 39, and 4.7 Pro- 4.3.4 Interrupt Controller Interface on page 38
gram and External Data Spaces on page 66.
4.3.4 Interrupt Controller Interface
4.3.2 Instruction Set With the PSoC 3 8051 there is no need to place a JMP
The PSoC 3 8051 core instruction set is highly optimized for instruction at address zero, because the interrupt controller
8-bit processing and Boolean operations. Types of instruc- interface jumps directly to ISRs with dynamic vector
tions supported include: addresses. When an interrupt occurs, the current instruction
is completed and the program counter pushed onto the
■ Arithmetic
stack. Code execution then jumps to the program address
■ Logical provided by the vector.
■ Data Transfer
After the ISR has completed, an RETI instruction returns
■ Boolean execution to the instruction following the previously inter-
■ Program Branching

38 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 8051 Core

rupted instruction, by popping the program counter from the 4.5 8051 Instructions
stack.
The 8051 has a full-featured set of instructions that supports
a number of flexible addressing modes.
4.4 CY 8051 Wrapper
The wrapper logic around the 8051 core provides an inter- 4.5.1 Internal Data Space Map
face to the rest of the PSoC 3 device. See Figure 4-1 on A diagram of the 8051 internal data space is shown in
page 38. The wrapper has the following features: Figure 4-2.
■ The 8051 is one of two bus masters, the other is the
Figure 4-2. 8051 Internal Data Space
DMA controller – see the PHUB and DMAC chapter on
page 91 0xFF
RAM Shared with SFRs
■ The two bus slaves are the on-chip SRAM and the Stack Space Special Function Registers
(indirect addressing, idata space) (direct addressing, data space)
PHUB: 0x80
❐ Accessed within the 8051 external data space 0x7F
RAM Shared with Stack Space
❐ Enables access to all PSoC 3 registers and to exter- (direct and indirect addressing, shared idata and data spaces)
0x30
nal memory
0x2F
Bit Addressable Area
■ An SFR – I/O interface allows direct access to some I/O 0x20
port registers using SFRs – see 4.4.1 SFR – I/O 0x1F
4 Banks, R0-R7 Each
Interface on page 39 0x00

4.4.1 SFR – I/O Interface 4.5.2 Addressing Modes

Each I/O port supports two interfaces: The following addressing modes are supported by the 8051:
■ SFRs in the 8051 – allows faster access to a limited set ■ Direct Addressing – The operand is specified by a direct
of I/O port registers 8-bit address field. Only the lower 128 bytes of internal
■ PHUB – allows boot configuration and access to all I/O RAM, and the SFRs, are accessed using this mode.
port registers ■ Indirect Addressing – The instruction specifies the regis-
ter that contains the address of the operand. Registers
R0, R1, or SP are used to specify the 8-bit address for
all 256 bytes of internal RAM. The data pointer (DPTR)
register is used to specify the 16-bit address for the pro-
gram and external data spaces.
■ Register Addressing – Certain instructions access one of
the registers in the specified register bank. These
instructions are more efficient because there is no need
for an address field.
■ Register Specific Instructions – Some instructions are
specific to certain registers. For example, some instruc-
tions always act on the Accumulator. In this case, there
is no need to specify the operand.
■ Immediate Constants – The instruction contains a con-
stant value.
■ Bit Addressing – The operand is one of 256 bits.

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4.5.3 Arithmetic Logic Unit Functions

The Arithmetic Logic Unit (ALU) section of the processor performs extensive data manipulation (see 4.5 8051 Instructions on
page 39) and includes:
■ 8-bit ALU – performs:
❐ Typical arithmetic operations – such as addition, subtraction, multiplication, and division
❐ Additional operations – such as increment, decrement, BCD decimal adjust, and compare
❐ AND, OR, Exclusive OR, complement, and rotation
❐ Bit operations – such as set, clear, complement, jump-if-not-set, jump-if-set-and-clear, and move to/from carry
■ ACC (SFR 0xE0) register – accumulator for results of most instructions
■ B (SFR 0xF0) register – used during multiply and divide operations. In other cases, it is used as a general purpose regis-
ter, directly addressable
■ PSW (SFR 0xD0) register – used as the program status word, which contains several bits that reflect the current state of
the CPU

PSW 0xD0 (Program Status Word SFR)

7 6 5 4 3 2 1 0
Access: POR RW: 00
Bit Name CY AC F0 RS1 RS0 OV F1 P

Bits Name Description

7 CY Carry flag – affected by arithmetic and bit instructions
6 AC Auxiliary carry – affected by ADD, ADDC, SUBB instructions
5 F0 General purpose flag 0
4, 3 RS[1:0] Register bank select bits:
00 – Bank 0, data address 0x00-0x07
01 – Bank 1, data address 0x08-0x0F
10 – Bank 2, data address 0x10-0x17
11 – Bank 3, data address 0x18-0x1F
2 OV Overflow flag – affected by ADD, ADDC, SUBB, MUL, DIV instructions
1 F1 General purpose flag 1
Parity flag – set/cleared after each instruction to indicate an odd/even number
0 P
of 1s in the accumulator

4.5.3.1 Arithmetic Instructions

Arithmetic instructions support the direct, indirect, register, immediate, and register-specific addressing modes. They support
addition, subtraction, multiplication, division, increment, and decrement operations. Standard 8051 8 x 8 multiplications and
divisions are done in just 2 and 6 cycles, respectively. Table 4-1 lists the various arithmetic instructions.

Table 4-1. Arithmetic Instructions

Mnemonic Description Bytes Cycles
ADD A,Rn Add register to accumulator 1 1
ADD A,Direct Add direct byte to accumulator 2 2
ADD A,@Ri Add indirect RAM to accumulator 1 2
ADD A,#data Add immediate data to accumulator 2 2
ADDC A,Rn Add register to accumulator with carry 1 1
ADDC A,Direct Add direct byte to accumulator with carry 2 2
ADDC A,@Ri Add indirect RAM to accumulator with carry 1 2

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Table 4-1. Arithmetic Instructions (continued)

Mnemonic Description Bytes Cycles
ADDC A,#data Add immediate data to accumulator with carry 2 2
SUBB A,Rn Subtract register from accumulator with borrow 1 1
SUBB A,Direct Subtract direct byte from accumulator with borrow 2 2
SUBB A,@Ri Subtract indirect RAM from accumulator with borrow 1 2
SUBB A,#data Subtract immediate data from accumulator with borrow 2 2
INC A Increment accumulator 1 1
INC Rn Increment register 1 2
INC Direct Increment direct byte 2 3
INC @Ri Increment indirect RAM 1 3
DEC A Decrement accumulator 1 1
DEC Rn Decrement register 1 2
DEC Direct Decrement direct byte 2 3
DEC @Ri Decrement indirect RAM 1 3
INC DPTR Increment data pointer 1 1
MUL Multiply accumulator and B 1 2
DIV Divide accumulator by B 1 6
DAA Decimal adjust accumulator 1 3

4.5.3.2 Logical Instructions

Logical instructions perform Boolean operations such as AND, OR, XOR, rotate and swap of nibbles. The Boolean operations
on the bytes are performed on the bit-by-bit basis. Table 4-2 lists logical instructions and their descriptions.

Table 4-2. Logical Instructions

Mnemonic Description Bytes Cycles
ANL A,Rn AND register to accumulator 1 1
ANL A,Direct AND direct byte to accumulator 2 2
ANL A,@Ri AND indirect RAM to accumulator 1 2
ANL A,#data AND immediate data to accumulator 2 2
ANL Direct, A AND accumulator to direct byte 2 3
ANL Direct, #data AND immediate data to direct byte 3 3
ORL A,Rn OR register to accumulator 1 1
ORL A,Direct OR direct byte to accumulator 2 2
ORL A,@Ri OR indirect RAM to accumulator 1 2
ORL A,#data OR immediate data to accumulator 2 2
ORL Direct, A OR accumulator to direct byte 2 3
ORL Direct, #data OR immediate data to direct byte 3 3
XRL A,Rn XOR register to accumulator 1 1
XRL A,Direct XOR direct byte to accumulator 2 2
XRL A,@Ri XOR indirect RAM to accumulator 1 2
XRL A,#data XOR immediate data to accumulator 2 2
XRL Direct, A XOR accumulator to direct byte 2 3
XRL Direct, #data XOR immediate data to direct byte 3 3
CLR A Clear accumulator 1 1

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Table 4-2. Logical Instructions (continued)

Mnemonic Description Bytes Cycles
CPL A Complement accumulator 1 1
RL A Rotate accumulator left 1 1
RLC A Rotate accumulator left through carry 1 1
RR A Rotate accumulator right 1 1
RRC A Rotate accumulator right though carry 1 1
SWAP Swap nibbles within accumulator 1 1

4.5.3.3 Data Transfer Instructions

There are three types of data transfer instructions:
■ Internal data – includes transfer between any two internal RAM locations or SFRs. These instructions use direct, indirect,
register, and immediate addressing.
■ External data – includes only the transfer between the accumulator and the external address. It uses only the MOVX
instruction.
■ Lookup tables – includes only the transfer between the accumulator and the program memory address. It can use only the
MOVC instruction.

Table 4-3 lists the available data transfer instructions.

Table 4-3. Data Transfer Instructions

Mnemonic Description Bytes Cycles
MOV A,Rn Move register to accumulator 1 1
MOV A,Direct Move direct byte to accumulator 2 2
MOV A,@Ri Move indirect RAM to accumulator 1 2
MOV A,#data Move immediate data to accumulator 2 2
MOV Rn,A Move accumulator to register 1 1
MOV Rn,Direct Move direct byte to register 2 3
MOV Rn, #data Move immediate data to register 2 2
MOV Direct, A Move accumulator to direct byte 2 2
MOV Direct, Rn Move register to direct byte 2 2
MOV Direct, Direct Move direct byte to direct byte 3 3
MOV Direct, @Ri Move indirect RAM to direct byte 2 3
MOV Direct, #data Move immediate data to direct byte 3 3
MOV @Ri, A Move accumulator to indirect RAM 1 2
MOV @Ri, Direct Move direct byte to indirect RAM 2 3
MOV @Ri, #data Move immediate data to indirect RAM 2 2
MOV DPTR, #data16 Load data pointer with 16 bit constant 3 3
MOVC A, @A+DPTR Move code byte relative to DPTR to accumulator 1 5
MOVC A, @A + PC Move code byte relative to PC to accumulator 1 4
MOVX A,@Ri Move a byte from external data space to accumulator 1 4
MOVX A, @DPTR Move a byte from external data space to accumulator 1 3
MOVX @Ri, A Move a byte from accumulator to external RAM 1 5
MOVX @DPTR, A Move a byte from accumulator to external RAM 1 4
PUSH Direct Push direct byte onto stack 2 3
POP Direct Pop direct byte from stack 2 2

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Table 4-3. Data Transfer Instructions (continued)

Mnemonic Description Bytes Cycles
XCH A, Rn Exchange register with accumulator 1 2
XCH A, Direct Exchange direct byte with accumulator 2 3
XCH A, @Ri Exchange indirect RAM with accumulator 1 3
XCHD A, @Ri Exchange low order indirect digit RAM with accumulator 1 3

4.5.3.4 Boolean Instructions1

The 8051 core has a bit addressable memory with 128 bits of bit addressable RAM (at internal data addresses 0x20 - 0x2F),
and a set of SFRs that are bit addressable. The instruction set includes move, set, clear, toggle, and OR and AND instruc-
tions, as well as conditional jump instructions. An abundance of bit-level instructions makes the 8051 an excellent bit proces-
sor.

Table 4-4 lists the available Boolean instructions.

Table 4-4. Boolean Instructions

Mnemonic Description Bytes Cycles
CLR C Clear carry 1 1
CLR bit Clear direct bit 2 3
SETB C Set carry 1 1
SETB bit Set direct bit 2 3
CPL C Complement carry 1 1
CPL bit Complement direct bit 2 3
ANL C, bit AND direct bit to carry 2 2
ANL C, /bit AND complement of direct bit to carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to carry 2 2
MOV C, bit Move direct bit to carry 2 2
MOV bit, C Move carry to direct bit 2 3
JC rel Jump if carry is set 2 3
JNC rel Jump if no carry is set 2 3
JB bit, rel Jump if direct bit is set 3 5
JNB bit, rel Jump if direct bit is not set 3 5
JBC bit, rel Jump if direct bit is set and clear bit 3 5

4.5.3.5 Program Branching Instructions

The 8051 supports a set of conditional and unconditional jump instructions to modify the program execution flow.

Table 4-5 shows the list of jump instructions.

Table 4-5. Jump Instructions

Mnemonic Description Bytes
ACALL addr11 Absolute subroutine call 2 4
LCALL addr16 Long subroutine call 3 4
RET Return from subroutine 1 4
RETI Return from interrupt 1 4
AJMP addr11 Absolute jump 2 3

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Table 4-5. Jump Instructions (continued)

Mnemonic Description Bytes
LJMP addr16 Long jump 3 4
SJMP rel Short jump (relative address) 2 3
JMP @A + DPTR Jump Indirect relative to DPTR 1 5
JZ rel Jump if accumulator is zero 2 4
JNZ rel Jump if accumulator is non zero 2 4
CJNE A,Direct, rel Compare direct byte to accumulator and jump if not equal 3 5
Compare immediate data to accumulator and jump if not
CJNE A, #data, rel 3 4
equal
CJNE Rn, #data, rel Compare immediate data to register and jump if not equal 3 4
Compare immediate data to indirect RAM and jump if not
CJNE @Ri, #data, rel 3 5
equal
DJNZ Rn,rel Decrement register and jump if non zero 2 4
DJNZ Direct, rel Decrement direct byte and jump if non zero 3 5
NOP No operation 1 1

4.5.3.6 Instruction Set Details

The following instructions are supported by the 8051 and are listed in alphabetical order.

ACALL addr11
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2 0x11,

0x31,
(SP)  (SP) + 1
0x51,
((SP))  (PC7-0) 0x71,
ACALL addr11 Absolute call None 2 4
(SP)  (SP) + 1 0x91,
0xB1,
((SP))  (PC15-8)
0xD1,
(PC10-0)  page address 0xF1

Unconditionally calls a subroutine located at the indicated address. The destination address is obtained by concatenating the five high-order
bits of the incremented PC, opcode bits 7-5, and the second byte of the instruction. The subroutine called must start within the same 2K block
of program memory as the first byte of the instruction following the ACALL.

ADD A, Rn
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1 0x28 –

ADD A, Rn Add a register to ACC C, AC, OV 1 1
(A)  (A) + (Rn) 0x2F

Adds the register indicated to the accumulator, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively,
if there is a carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the overflow (OV) flag indicates an overflow
occurred. OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise OV is cleared. When
adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative
operands.

ADD A, direct
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
ADD A, direct Add a direct byte to ACC C, AC, OV 0x25 2 2
(A)  (A) + (direct)

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Adds the direct byte indicated to the accumulator, leaving the result in the accumulator. The carry, auxiliary carry, and overflow flags are set
as described above.

ADD A, @Ri
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Add an indirect byte to (PC)  (PC) + 1 0x26,

ADD A, @Ri C, AC, OV 1 2
ACC (A)  (A) + ((Ri)) 0x27

Adds a byte pointed to by R0 or R1 to the accumulator, leaving the result in the accumulator. The carry, auxiliary carry, and overflow flags are
set as described above.

ADD A, #data
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Add an immediate byte to (PC)  (PC) + 2

ADD A, #data C, AC, OV 0x24 2 2
ACC (A)  (A) + data

Adds an immediate byte (the second byte of the instruction) to the accumulator, leaving the result in the accumulator. The carry, auxiliary
carry, and overflow flags are set as described above.

ADDC A, Rn
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Add a register and C to (PC)  (PC) + 1 0x38 –

ADDC A, Rn C, AC, OV 1 1
ACC (A)  (A) + (C) + (Rn) 0x3F

Adds the register indicated, and the carry flag, to the accumulator, leaving the result in the accumulator. The carry and auxiliary carry flags
are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the overflow flag indicates
an overflow occurred. OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise OV is
cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum
from two negative operands.

ADDC A, direct
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Add a direct byte and C to (PC)  (PC) + 2

ADDC A, direct C, AC, OV 0x35 2 2
ACC (A)  (A) + (C) + (direct)

Adds the direct byte indicated, and the carry flag, to the accumulator, leaving the result in the accumulator. The carry, auxiliary carry, and
overflow flags are set as described above.

ADDC A, @Ri
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Add an indirect byte and C (PC)  (PC) + 1 0x36,

ADDC A, @Ri C, AC, OV 1 2
to ACC (A)  (A) + (C) + ((Ri)) 0x37

Adds a byte pointed to by R0 or R1, and the carry flag, to the accumulator, leaving the result in the accumulator. The carry, auxiliary carry,
and overflow flags are set as described above.

ADDC A, #data
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Add an immediate byte (PC)  (PC) + 2

ADDC A, #data C, AC, OV 0x34 2 2
and C to ACC (A)  (A) + (C) + data

Adds an immediate byte (the second byte of the instruction), and the carry flag, to the accumulator, leaving the result in the accumulator. The
carry, auxiliary carry, and overflow flags are set as described above.

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AJMP addr11
Mnemonic Function Operation Flags Opcodes Bytes Cycles

0x01,
0x21,
0x41,
(PC)  (PC) + 2 0x61,
AJMP addr11 Absolute jump None 2 3
(PC10-0) page address 0x81,
0xA1,
0xC1,
0Xe1

Unconditionally transfers program control to the indicated address. The address is obtained by concatenating the five high-order bits of the
incremented PC, opcode bits 7-5, and the second byte of the instruction. The destination must be within the same 2K block of program mem-
ory as the first byte of the instruction following the AJMP.

ANL A, Rn
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical AND for byte oper- (PC)  (PC) + 1 0x58 –

ANL A, Rn None 1 1
ands (A)  (A) and (Rn) 0x5F

Performs a bitwise logical AND operation between the accumulator and a register, leaving the result in the accumulator.

ANL A, direct
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical AND for byte oper- PC)  (PC) + 2

ANL A, direct None 0x55 2 2
ands (A)  (A) and (direct)

Performs a bitwise logical AND operation between the accumulator and a direct byte, leaving the result in the accumulator.

ANL A, @Ri
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical AND for byte oper- (PC)  (PC) + 1 0x56,

ANL A, @Ri None 1 2
ands (A)  (A) and ((Ri)) 0x57

Performs a bitwise logical AND operation between the accumulator and a byte pointed to by R0 or R1, leaving the result in the accumulator.

ANL A, #data
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical AND for byte oper- (PC)  (PC) + 2

ANL A, #data None 0x54 2 2
ands (A)  (A) and data

Performs a bitwise logical AND operation between the accumulator and an immediate byte (the second byte of the instruction), leaving the
result in the accumulator.

ANL direct A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical AND for byte oper- (PC)  (PC) + 2

ANL direct A None 0x52 2 3
ands (direct)  (direct) and (A)

Performs a bitwise logical AND operation between a direct byte and the accumulator, leaving the result in the direct byte.

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ANL direct, #data

Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical AND for byte oper- (PC)  (PC) + 2

ANL direct, #data None 0x53 3 3
ands (direct)  (direct) and data

Performs a bitwise logical AND operation between a direct byte and an immediate byte (the third byte of the instruction), leaving the result in
the direct byte.

ANL C, bit
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical AND for bit oper- (PC)  (PC) + 2

ANL C, bit C 0x82 2 2
ands (C)  (C) and (bit)

Performs a bitwise logical AND operation between the carry flag and a bit, leaving the result in the carry flag.

ANL C, /bit
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical AND for bit oper- (PC)  (PC) + 2

ANL C, /bit C 0xB0 2 2
ands (C)  (C) and / (bit)

Performs a bitwise logical AND operation between the carry flag and the inversion of a bit, leaving the result in the carry flag.

CJNE A, direct, rel

Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 3
If (A)  (direct) then
Compare and jump if not (PC)  (PC) + rel
CJNE A, direct, rel If (A) < (direct) then C 0xB5 3 5
equal
(C)  1
Else
(C)  0

Compares the magnitudes of the accumulator and the direct byte, and branches if their values are not equal. The branch destination is com-
puted by adding the signed relative displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next
instruction. The carry flag is set if the unsigned integer value of the accumulator is less than the unsigned integer value of the direct byte; oth-
erwise, the carry is cleared. Neither operand is affected.

CJNE A, #data, rel

Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 3
If (A)  data then
Compare and jump if not (PC)  (PC) + rel
CJNE A, #data, rel If (A) < data then C 0xB4 3 4
equal
(C)  1
Else
(C)  0

Compares the magnitudes of the accumulator and the immediate byte (the second byte of the instruction), and branches if their values are
not equal. The branch destination and carry flag are set as described above. The accumulator is not affected.

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CJNE Rn, #data, rel

Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 3
If (Rn)  data then
Compare and jump if not (PC)  (PC) + rel 0xB8 –
CJNE Rn, #data, rel If (Rn) < data then C 3 4
equal 0xBF
(C)  1
Else
(C)  0

Compares the magnitudes of the indicated register and the immediate byte (the second byte of the instruction), and branches if their values
are not equal. The branch destination and carry flag are set as described above. The register is not affected.

CJNE @Ri, #data, rel

Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 3
If ((Ri))  data then
Compare and jump if not (PC)  (PC) + rel 0xB6,
CJNE @Ri, #data, rel If ((Ri)) < data then C 3 5
equal 0xB7
(C)  1
Else
(C)  0

Compares the magnitudes of the byte pointed to by R0 or R1 and the immediate byte (the second byte of the instruction), and branches if
their values are not equal. The branch destination and carry flag are set as described above. The byte pointed to by R0 or R1 is not affected.

CLR A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
CLR A Clear accumulator None None 1 1
(A)  0

All bits of the accumulator are cleared (set to zero).

CLR bit
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
CLR bit Clear bit None 0xC2 2 3
(bit)  0

The indicated bit is cleared (set to zero).

CLR C
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
CLR C Clear carry None 0xC3 1 1
(C)  0

The carry flag is cleared (set to zero).

CPL A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
CPL A Complement accumulator None 0xF4 1 1
(A)  /(A)

Each bit of the accumulator is logically complemented (one’s complement). Bits that previously contained a one are changed to zero and vice
versa.

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CPL bit
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
CPL bit Complement bit None 0xB2 2 3
(bit)  /(bit)

The bit variable specified is complemented. A bit that had been a one is changed to zero and vice versa. CPL can operate on the carry or any
directly addressable bit. When this instruction is used to modify an output pin, the value used as the original data will be read from the output
data latch, not the input pin.

CPL C
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
CPL C Complement carry C 0xB3 1 1
(C)  /(C)

The carry flag is complemented. A bit that had been a one is changed to zero and vice versa.

DAA
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
if [[(A3-0) > 9] ^ [(AC) = 1]]
then
DA A
Decimal adjust accumula- (A3-0)  (A3-0) + 6 C 0xD4 1 3
tor for addition next
if [[(A7-4) > 9] ^ [(C) = 1]]
then
(A7-4)  (A7-4) + 6

Adjusts the value in the accumulator resulting from the earlier addition of two variables (each in packed BCD format), producing two four-bit
digits. Any ADD or ADDC instruction may have been used to perform the addition. If accumulator bits 3-0 are greater than nine (xxxx1010-
xxxx1111), or if the AC flag is one, six is added to the accumulator producing the proper BCD digit in the low- order nibble. This internal addi-
tion sets the carry flag if a carry-out of the low order four-bit field propagated through all high-order bits, but does not clear the carry flag oth-
erwise.
If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx-1111xxxx), these high-order bits are incremented by six,
producing the proper BCD digit in the high-order nibble. Again, this sets the carry flag if there was a carry-out of the high-order bits, but does
not clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple precision
decimal addition. OV is not affected.
All of this occurs during the one instruction cycle. Essentially; this instruction performs the decimal conversion by adding
00H, 06H, 60H, or 66H to the accumulator, depending on initial accumulator and PSW conditions. DA A cannot simply convert a hexadecimal
number in the accumulator to BCD notation, nor does DA A apply to decimal subtraction.

DEC A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
DEC A Decrement accumulator None 0x14 1 1
(A)  (A) – 1

The accumulator is decremented by 1. An original value of 0 will underflow to 0xFF.

DEC Rn
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1 0x18 –

DEC Rn Decrement register None 1 2
(Rn)  (Rn) – 1 0x1F

The indicated register is decremented by 1. An original value of 0 will underflow to 0xFF.

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DEC direct
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
DEC direct Decrement direct byte None 0x15 2 3
(direct)  (direct) – 1

The indicated direct byte is decremented by 1. An original value of 0 will underflow to 0xFF. When this instruction is used to modify an output
port, the value used as the original port data will be read from the output data latch, not the input pins.

DEC @Ri
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1 0x16,

DEC @Ri Decrement indirect byte None 1 3
((Ri))  ((Ri)) – 1 0x17

The byte pointed to by R0 or R1 is decremented by 1. An original value of 0 will underflow to 0xFF. When this instruction is used to modify an
output port, the value used as the original port data will be read from the output data latch, not the input pins.

DIV
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
(A15-8)  (A) / (B) result’s bits
DIV Divide C, OV 0x84 1 6
15..8
(B7-0)  (A) / (B) result’s bits 7..0

Divides the unsigned integer in the accumulator by the unsigned integer in register B. The accumulator receives the integer part of the quo-
tient; register B receives the integer remainder. If B had originally contained 0, the values returned in the accumulator and register B are
undefined and the overflow flag is set. Otherwise the overflow flag is cleared. The carry flag is cleared.

DJNZ Rn, rel

Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
Decrement and jump if not (Rn)  (Rn) - 1 0xD8 –
if (Rn)  0 then
DJNZ Rn, rel None 2 4
zero 0xDF
(PC)  (PC) + rel

Decrements the register indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An
original value of 0 will underflow to 0xFF. The branch destination would be computed by adding the signed relative-displacement value in the
last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction.

DJNZ direct, rel

Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 3
Decrement and jump if not (direct)  (direct) - 1
if (direct)  0 then
DJNZ direct, rel None 0xD5 3 5
zero
(PC)  (PC) + rel

Decrements the direct byte indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An
original value of 0 will underflow to 0xFF. The branch destination would be computed as described above. When this instruction is used to
modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.

INC A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
INC A Increment accumulator None 0x04 1 1
(A)  (A) + 1

The accumulator is incremented by 1. An original value of 0xFF will overflow to 0.

50 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 8051 Core

INC Rn
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1 0x08 –

INC Rn Increment register None 1 2
(Rn)  (Rn) + 1 0x0F

The indicated register is incremented by 1. An original value of 0xFF will overflow to 0.

INC direct
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
INC direct Increment direct byte None 0x05 2 3
(direct)  (direct) + 1

The indicated direct byte is incremented by 1. An original value of 0xFF will overflow to 0. When this instruction is used to modify an output
port, the value used as the original port data will be read from the output data latch, not the input pins.

INC @Ri
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1 0x06,

INC @Ri Increment indirect byte None 1 3
((Ri))  ((Ri)) + 1 0x07

The byte pointed to by R0 or R1 is incremented by 1. An original value of 0xFF will overflow to 0. When this instruction is used to modify an
output port, the value used as the original port data will be read from the output data latch, not the input pins.

INC DPTR
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
INC DPTR Increment data pointer None 0xC3 1 1
(DPTR)  (DPTR) + 1

Increment the 16-bit data pointer by 1. A 16-bit increment is performed; an overflow of the low-order byte of the data pointer (DPL) from 0xFF
to 0 will increment the high-order byte (DPH). This is the only 16-bit register that can be incremented.

JB bit, rel
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 3
JB bit, rel Jump if bit is set if (bit) = 1 then None 0x20 3 5
(PC)  (PC) + rel

If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by
adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruc-
tion. The bit tested is not modified.

JBC bit, rel

Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 3
Jump if bit is set and clear if (bit) = 1 then
JBC bit, rel None 0x10 3 5
bit bit  0
(PC)  (PC) + rel

If the indicated bit is one, branch to the address indicated; otherwise proceed with the next instruction. In either case, clear the designated bit.
The branch destination is computed as described above. When this instruction is used to test an output pin, the value used as the original
data will be read from the output data latch, not the input pin.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 51

8051 Core

JC rel
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
JC rel Jump if carry is set if (C) = 1 then None 0x40 2 3
(PC)  (PC) + rel

If the carry flag is set, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed as
described above.

JMP @A + DPTR
Mnemonic Function Operation Flags Opcodes Bytes Cycles

JMP @A + DPTR Jump indirect (PC)  (A) + (DPTR) None 0x73 1 5

Add the 8-bit unsigned contents of the accumulator with the 16-bit data pointer, and load the resulting sum to the program counter. This will
be the address for subsequent instruction fetches. 16-bit addition is performed: a carry-out from the low-order 8 bits propagates through the
high order bits. Neither the accumulator nor the data pointer is altered.

JNB bit, rel

Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 3
JNB bit, rel Jump if bit is not set if (bit) = 0 then None 0x30 3 5
(PC)  (PC) + rel

If the indicated bit is a zero, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed
by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified.

JNC rel
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
JNC rel Jump if carry is not set if (C) = 0 then None 0x50 2 3
(PC)  (PC) + rel

If the carry flag is set, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed as
described above.

JNZ rel
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
if (A)  0 then
Jump if accumulator is not
JNZ rel None 0x70 2 4
zero
(PC)  (PC) + rel

If any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is
computed as described above. The accumulator is not modified.

JZ rel
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
Jump if accumulator is
JZ rel if (A) = 0 then None 0x60 2 4
zero
(PC)  (PC) + rel

If all bits of the accumulator are zero, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is
computed as described above. The accumulator is not modified.

52 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 8051 Core

LCALL addr16
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 3
(SP)  (SP) + 1
((SP))  (PC7-0)
LCALL addr16 Long call None 0x12 3 4
(SP)  (SP) + 1
((SP))  (PC15-8)
(PC)  addr15-0

Calls a subroutine located at the indicated address. The high-order and low-order bytes of the PC are loaded, respectively, with the second
and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore
begin anywhere in the full 64 KB program memory address space.

LJMP addr16
Mnemonic Function Operation Flags Opcodes Bytes Cycles

LJMP addr16 Long jump (PC)  addr15…addr0 None 0x02 3 4

Does an unconditional branch to the indicated address, by loading the high- order and low-order bytes of the PC (respectively) with the sec-
ond and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space.

MOV A, Rn
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1 0xE8 –

MOV A, Rn Copy a register to ACC None 1 1
(A)  (Rn) 0xEF

Copies the register indicated to the accumulator. The register is not affected.

MOV A, direct
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
MOV A, direct Copy a direct byte to ACC None 0xE5 2 2
(A)  (direct)

Copies the direct byte indicated to the accumulator. The direct byte is not affected.

MOV A, @Ri
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Copy an indirect byte to (PC)  (PC) + 1 0xE6,

MOV A, @Ri None 1 2
ACC (A)  ((Ri)) 0xE7

Copies a byte pointed to by R0 or R1 to the accumulator. The byte pointed to by R0 or R1 is not affected.

MOV A, #data
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Load ACC with immediate (PC)  (PC) + 2

MOV A, #data None 0xE4 2 2
data (A)  data

Loads the accumulator with an immediate byte (the second byte of the instruction).

MOV Rn, A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1 0xF8 –

MOV Rn, A Copy ACC to a register None 1 1
(Rn)  (A) 0xFF

Copies the accumulator to the register indicated. The accumulator is not affected.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 53

8051 Core

MOV Rn, direct

Mnemonic Function Operation Flags Opcodes Bytes Cycles

Copy a direct byte to a reg- (PC)  (PC) + 2 0xA8 –

MOV Rn, direct None 2 3
ister (Rn)  (direct) 0xAF

Copies the direct byte indicated to the register indicated. The direct byte is not affected.

MOV Rn, #data

Mnemonic Function Operation Flags Opcodes Bytes Cycles

Load a register with imme- (PC)  (PC) + 2 0x78 –

MOV Rn, #data None 2 2
diate data (Rn)  data 0x7F

Loads the register indicated with an immediate byte (the second byte of the instruction).

MOV direct, A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
MOV direct, A Copy ACC to a direct byte None 0xF5 2 2
(direct)  (A)

Copies the accumulator to the direct byte indicated. The accumulator is not affected.

MOV direct, Rn
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Copy a register to a direct (PC)  (PC) + 2 0x88 –

MOV direct, Rn None 2 2
byte (direct)  (Rn) 0x8F

Copies the register indicated to the direct byte indicated. The register is not affected.

MOV direct, direct

Mnemonic Function Operation Flags Opcodes Bytes Cycles

Copy a direct byte to a (PC)  (PC) + 3

MOV direct, direct None 0x85 3 3
direct byte (direct)  (direct)

Copies the direct source byte indicated to the direct destination byte indicated. The direct source byte is not affected.

MOV direct, @Ri

Mnemonic Function Operation Flags Opcodes Bytes Cycles

Copy an indirect byte to a (PC)  (PC) + 2 0x86,

MOV direct, @Ri None 2 3
direct byte (direct)  ((Ri)) 0x87

Copies the byte pointed to by R0 or R1 to the direct byte indicated. The byte pointed to by R0 or R1 is not affected.

MOV direct, #data

Mnemonic Function Operation Flags Opcodes Bytes Cycles

Load a direct byte with (PC)  (PC) + 3

MOV direct, #data None 0x75 3 3
immediate data (direct)  data

Loads the direct byte indicated with an immediate byte (the third byte of the instruction).

54 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 8051 Core

MOV @Ri, A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Copy ACC to an indirect (PC)  (PC) + 1 0xF6,

MOV @Ri, A None 1 2
byte ((Ri))  (A) 0xF7

Copies the accumulator to a byte pointed to by R0 or R1. The accumulator is not affected.

MOV @Ri, direct

Mnemonic Function Operation Flags Opcodes Bytes Cycles

Copy a direct byte to an (PC)  (PC) + 2 0xA6,

MOV @Ri, direct None 2 3
indirect byte ((Ri))  (direct) 0xA7

Copies the direct byte indicated to a byte pointed to by R0 or R1. The direct byte is not affected.

MOV @Ri, #data

Mnemonic Function Operation Flags Opcodes Bytes Cycles

MOV @Ri, Load an indirect byte with (PC)  (PC) + 2 0x76,

None 2 2
#data immediate data ((Ri))  data 0x77

Loads a byte pointed to by R0 or R1 with an immediate byte (the second byte of the instruction).

MOV C, bit
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
MOV C, bit Copy a bit to C C 0xA2 2 2
(C)  (bit)

The Boolean variable indicated (directly addressable bit) is copied into the carry flag.

MOV bit, C
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
MOV bit, C Copy C to a bit None 0x92 2 3
(bit)  (C)

The carry flag is copied into the Boolean variable indicated (directly addressable bit).

MOV DPTR, #data16

Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 3
DPH  immediate
Load DPTR with immedi-
MOV DPTR, #data16 data15...8 None 0x85 3 3
ate data
DPL  immediate
data7...0

Loads the data pointer with the 16-bit constant indicated. The 16 bit constant is loaded into the second and third bytes of the instruction. The
second byte (DPH) is the high-order byte, while the third byte (DPL) holds the low-order byte. This is the only instruction that moves 16 bits of
data at once.

MOVC A, @A + DPTR
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Load ACC with a code (PC)  (PC) + 1

MOVC A, @A + DPTR None 0x93 1 5
byte (A)  ((A) + (DPTR))

Loads the accumulator with a code byte, or constant from program memory. The address of the byte fetched is the sum of the original
unsigned accumulator contents and the contents of the 16-bit DPTR. A 16-bit addition is performed so a carry-out from the low-order eight
bits may propagate through higher-order bits.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 55

8051 Core

MOVC A, @A + PC
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Load ACC with a code (PC)  (PC) + 1

MOVC A, @A + PC None 0x83 1 4
byte (A)  ((A) + (PC))

Loads the accumulator with a code byte, or constant from program memory. The address of the byte fetched is the sum of the original
unsigned accumulator contents and the contents of the 16-bit PC. The PC is incremented to the address of the following instruction before
being added to the accumulator. 16-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order
bits.

MOVX A, @Ri
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Copy an external byte to (PC)  (PC) + 1 0xE2,

MOVX A, @Ri None 1 3
ACC (A)  (MXAX : P2 : (Ri)) 0xE3

Copies a byte of external data memory to the accumulator. The 24-bit external address is formed by concatenating the MXAX register (SFR
address 0xEA), the P2AX register (SFR address 0xA0), and the contents of R0 or R1. The external byte is not affected.

MOVX A, @DPTR
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Copy an external byte to (PC)  (PC) + 1

MOVX A, @DPTR None 0xE0 1 2
ACC (A)  (DPX : DPTR)

Copies a byte of external data memory to the accumulator. The 24-bit external address is formed by concatenating the DPX register (SFR
address 0x93 or 0x95) and the contents of DPTR. The external byte is not affected.

MOVX @Ri, A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Copy ACC to an external (PC)  (PC) + 1 0xF2,

MOVX @Ri, A None 1 4
byte (MXAX : P2 : (Ri))  (A) 0xF3

Copies the accumulator to the external data memory address indicated. The 24-bit external address is formed as described in MOVX A, @Ri
above. The accumulator is not affected.

MOVX @DPTR, A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Copy ACC to an external (PC)  (PC) + 1

MOVX @DPTR, A None 0xF0 1 3
byte (DPX : DPTR)  (A)

Copies the accumulator to the external data memory address indicated. The 24-bit external address is formed as described above. The accu-
mulator is not affected.

MUL
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
MUL Multiply (A)  (A) x (B) result’s bits 7…0 C, OV 0xA4 1 2
(B)  (A) x (B) result’s bits 15…8

Multiplies the unsigned 8-bit integers in the accumulator and register B. The low-order byte of the 16-bit product is left in the accumulator, and
the high-order byte in B. If the product is greater than 255 (0xFF) the overflow flag is set; otherwise it is cleared. The carry flag is always
cleared.

56 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 8051 Core

NOP
Mnemonic Function Operation Flags Opcodes Bytes Cycles

NOP No operation (PC)  (PC) + 1 None 0x00 1 1

No operation. Execution continues at the following instruction.

ORL A, Rn
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical OR for byte oper- (PC)  (PC) + 1 0x48 –

ORL A, Rn None 1 1
ands (A)  (A) or (Rn) 0x4F

Performs a bitwise logical OR operation between the accumulator and a register, leaving the result in the accumulator.

ORL A, direct
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical OR for byte oper- (PC)  (PC) + 2

ORL A, direct None 0x45 2 2
ands (A)  (A) or (direct)

Performs a bitwise logical OR operation between the accumulator and a direct byte, leaving the result in the accumulator.

ORL A, @Ri
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical OR for byte oper- (PC)  (PC) + 1 0x46,

ORL A, @Ri None 1 2
ands (A)  (A) or ((Ri)) 0x47

Performs a bitwise logical OR operation between the accumulator and a byte pointed to by R0 or R1, leaving the result in the accumulator.

ORL A, #data
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical OR for byte oper- (PC)  (PC) + 2

ORL A, #data None 0x44 2 2
ands (A)  (A) or data

Performs a bitwise logical OR operation between the accumulator and an immediate byte (the second byte of the instruction), leaving the
result in the accumulator.

ORL direct, A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical OR for byte oper- (PC)  (PC) + 2

ORL direct, A None 0x42 2 3
ands (direct)  (direct) or (A)

Performs a bitwise logical OR operation between a direct byte and the accumulator, leaving the result in the direct byte. When this instruction
is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.

ORL direct, #data

Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical OR for byte oper- (PC)  (PC) + 2

ORL direct, #data None 0x43 3 3
ands (direct)  (direct) or data

Performs a bitwise logical OR operation between a direct byte and an immediate byte (the third byte of the instruction), leaving the result in
the direct byte. When this instruction is used to modify an output port, the value used as the original port data will be read from the output
data latch, not the input pins.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 57

8051 Core

ORL C, bit
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical OR for bit oper- (PC)  (PC) + 2

ORL C, bit C 0x72 2 2
ands (C)  (C) or (bit)

Performs a bitwise logical OR operation between the carry flag and a bit, leaving the result in the carry flag.

ORL C, /bit
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical OR for bit oper- (PC)  (PC) + 2

ORL C, /bit C 0xA0 2 2
ands (C)  (C) or / (bit)

Performs a bitwise logical OR operation between the carry flag and the inversion of a bit, leaving the result in the carry flag.

POP direct
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
POP direct Pop from stack (direct)  ((SP)) None 0xD0 2 2
(SP)  (SP) – 1

The contents of the internal RAM location addressed by the stack pointer are read, and the stack pointer is decremented by one. The value
read is copied to the direct byte indicated.

PUSH direct
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
PUSH direct Push to stack (SP)  (SP) + 1 None 0xC0 2 3
((SP))  (direct)

The stack pointer is incremented by one. The contents of the direct byte indicated are then copied into the internal RAM location addressed
by the stack pointer.

RET
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC15-8)  ((SP))
(SP)  (SP) - 1
RET Return from subroutine None 0x22 1 4
(PC7-0)  ((SP))
(SP)  (SP) - 1

Pops the high and low-order bytes of the PC successively from the stack, decrementing the stack pointer by two. Program execution contin-
ues at the resulting address, generally the instruction immediately following an ACALL or LCALL.

RETI
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC15-8)  ((SP))
(SP)  (SP) - 1
RETI Return from interrupt None 0x32 1 4
(PC7-0)  ((SP))
(SP)  (SP) - 1

Pops the high and low-order bytes of the PC successively from the stack, and restores the interrupt logic to accept additional interrupts at the
same priority level as the one just processed. The stack pointer is left decremented by two. No other registers are affected; the PSW is not
automatically restored to its pre-interrupt status. Program execution continues at the resulting address, which is generally the instruction
immediately after the point at which the interrupt request was detected. If a lower or same-level interrupt is pending when the RETI instruction
is executed, that one instruction will be executed before the pending interrupt is processed.

58 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 8051 Core

RL A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
RL A Rotate ACC left (An + 1)  (An) n = 0-6 None 0x23 1 1
(A0)  (A7)

The eight bits in the accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position.

RLC A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
(An + 1)  (An) n = 0-6
RLC A RLC A C 0x33 1 1
(A0)  (C)
(C)  (A7)

The eight bits in the accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of
the carry flag moves into the bit 0 position.

RR A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
RR A Rotate ACC right (An)  (An + 1) n = 0-6 None 0x03 1 1
(A7)  (A0)

The eight bits in the accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position.

RRC A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
Rotate ACC right through (An)  (An + 1) n = 0-6
RRC A C 0x13 1 1
C (A7)  (C)
(C)  (A0)

The eight bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original state
of the carry flag moves into the bit 7 position.

SETB bit
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
SETB bit Set bit None 0xD2 2 3
(bit)  1

The indicated bit is set (to one).

SETB C
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
SETB C Set carry None 0xD3 1 1
(C)  1

The carry flag is set (to one).

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 59

8051 Core

SJMP rel
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 2
SJMP rel Short jump None 0x80 2 3
(PC)  (PC) + rel

Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement
in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes pre-
ceding this instruction to 127 bytes following it. Note the an SJMP with a displacement of 0xFE would be a one-instruction infinite loop.

SUBB A, Rn
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Subtract a register and C (PC)  (PC) + 1 0x98 –

SUBB A, Rn C, AC, OV 1 1
from ACC (A)  (A) - (C) - (Rn) 0x9F

Subtracts the register indicated, and the carry flag, from the accumulator, leaving the result in the accumulator. The carry (borrow) flag is set
if a borrow is needed for bit 7, and otherwise C is cleared. (If C was set before executing the instruction, this indicates that a borrow was
needed for the previous step in a multiple precision subtraction, so the carry is subtracted from the accumulator along with the source oper-
and). AC is set if a borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6 but not into bit 7, or into bit 7
but not bit 6. When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a posi-
tive value, or a positive result when a positive number is subtracted from a negative number.

SUBB A, direct
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Subtract a direct byte and (PC)  (PC) + 2

SUBB A, direct C, AC, OV 0x95 2 2
C from ACC (A)  (A) - (C) - (direct)

Subtracts the direct byte indicated, and the carry flag, from the accumulator, leaving the result in the accumulator. The carry, auxiliary carry,
and overflow flags are set as described above.

SUBB A, @Ri
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Subtract an indirect byte (PC)  (PC) + 1 0x96,

SUBB A, @Ri C, AC, OV 1 2
and C from ACC (A)  (A) - (C) - ((Ri)) 0x97

Subtracts a byte pointed to by R0 or R1, and the carry flag, from the accumulator, leaving the result in the accumulator. The carry, auxiliary
carry, and overflow flags are set as described above.

SUBB A, #data
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Subtract an immediate (PC)  (PC) + 2

SUBB A, #data C, AC, OV 0x94 2 2
byte and C from ACC (A)  (A) - (C) - data

Subtracts an immediate byte (the second byte of the instruction), and the carry flag, from the accumulator, leaving the result in the accumula-
tor. The carry, auxiliary carry, and overflow flags are set as described above.

SWAP
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1
SWAP Swap nibbles within ACC (A3-0)  (A7-4), None 0xC4 1 1
(A7-4)  (A3-0)

SWAP A interchanges the low and high-order nibbles (four-bit fields) of the accumulator (bits 3-0 and bits 7-4). The operation can also be
thought of as a four-bit rotate instruction.

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 8051 Core

XCH A, Rn
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Exchange a register with (PC)  (PC) + 1 0xC8 –

XCH A, Rn None 1 2
ACC (A)  (Rn) 0xCF

Exchanges the register indicated with the accumulator.

XCH A, direct
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Exchange a direct byte (PC)  (PC) + 2

XCH A, direct None 0xC5 2 3
with ACC (A)  (direct)

Exchanges the direct byte indicated with the accumulator.

XCH A, @Ri
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Exchange an indirect byte (PC)  (PC) + 1 0xC6,

XCH A, @Ri None 1 3
with ACC (A)  ((Ri)) 0xC7

Exchanges a byte pointed to by R0 or R1 with the accumulator.

XCHD A, @Ri
Mnemonic Function Operation Flags Opcodes Bytes Cycles

(PC)  (PC) + 1 0xD6,

XCHD A, @Ri Exchange a digit None 1 3
(A3-0)  ((Ri)3-0) 0xD7

XCHD exchanges the low-order nibble of the accumulator (bits 3-0, generally representing a hexadecimal or BCD digit), with that of the byte
pointed to by R0 or R1. The high-order nibbles (bits 7-4) are not affected.

XRL A, Rn
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical exclusive OR for (PC)  (PC) + 1 0x68 –

XRL A, Rn None 1 1
byte operands (A)  (A) xor (Rn) 0x6F

Performs a bitwise logical exclusive OR operation between the accumulator and a register, leaving the result in the accumulator.

XRL A, direct
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical exclusive OR for (PC)  (PC) + 2

XRL A, direct None 0x65 2 2
byte operands (A)  (A) xor (direct)

Performs a bitwise logical exclusive OR operation between the accumulator and a direct byte, leaving the result in the accumulator.

XRL A, @Ri
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical exclusive OR for (PC)  (PC) + 1 0x66,

XRL A, @Ri None 1 2
byte operands (A)  (A) xor ((Ri)) 0x67

Performs a bitwise logical exclusive OR operation between the accumulator and a byte pointed to by R0 or R1, leaving the result in the accu-
mulator.

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8051 Core

XRL A, #data
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical exclusive OR for (PC)  (PC) + 2

XRL A, #data None 0x64 2 2
byte operands (A)  (A) xor data

Performs a bitwise logical exclusive OR operation between the accumulator and an immediate byte (the second byte of the instruction), leav-
ing the result in the accumulator.

XRL direct, A
Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical exclusive OR for (PC)  (PC) + 2

XRL direct, A None 0x62 2 3
byte operands (direct)  (direct) xor (A)

Performs a bitwise logical exclusive OR operation between a direct byte and the accumulator, leaving the result in the direct byte. When this
instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.

XRL direct, #data

Mnemonic Function Operation Flags Opcodes Bytes Cycles

Logical exclusive OR for (PC)  (PC) + 2

XRL direct, #data None 0x63 3 3
byte operands (direct)  (direct) xor data

Performs a bitwise logical exclusive OR operation between a direct byte and an immediate byte (the third byte of the instruction), leaving the
result in the direct byte. When this instruction is used to modify an output port, the value used as the original port data will be read from the
output data latch, not the input pins.

4.6 8051 Special Function Registers (SFRs)

The Special Function Registers (SFRs) provide access to I/Os and other functions. All 8051 registers except the PC - ACC, B,
PSW, SP, DPTR - can also be accessed as SFRs.

4.6.1 SFRs
Table 4-6 shows the map for the SFRs space.
Table 4-6. SFR Map
0/8
1/9 2/A 3/B 4/C 5/D 6/E 7/F
(Bit Addressable)
0xF8 SFRPRT15DR SFRPRT15PS SFRPRT15SEL
0xF0 B SFRPRT12SEL
0xE8 SFRPRT12DR SFRPRT12PS MXAX
0xE0 ACC
0xD8 SFRPRT6DR SFRPRT6PS SFRPRT6SEL
0xD0 PSW
0xC8 SFRPRT5DR SFRPRT5PS SFRPRT5SEL
0xC0 SFRPRT4DR SFRPRT4PS SFRPRT4SEL
0xB8
0xB0 SFRPRT3DR SFRPRT3PS SFRPRT3SEL
0xA8 IE
0xA0 P2AX SFRPRT1SEL
0x98 SFRPRT2DR SFRPRT2PS SFRPRT2SEL
0x90 SFRPRT1DR SFRPRT1PS DPX0 DPX1
0x88 SFRPRT0PS SFRPRT0SEL
0x80 SFRPRT0DR SP DPL0 DPH0 DPL1 DPH1 DPS

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 8051 Core

4.6.2 Dual Data Pointer SFRs

Dual data pointer (DPTR) SFRs are implemented to speed up data block copying. DPTR0 and DPTR1 are located at four
SFR addresses. The active DPTR register is selected by the SEL bit (0x86.0). If the SEL bit is equal to 0, DPTR0 (SFRs
0x83:0x82) is selected; if not, DPTR1 (SFRs 0x85:0x84) is used.

4.6.2.1 DPTR0 (Data Pointer 0 SFR)

Bits 7 6 5 4 3 2 1 0
Access: POR R/W:00
Name DPH0 (0x83)
Bits 7 6 5 4 3 2 1 0
Access: POR R/W:00
Name DPL0 (0x82)

Bits Name Description

7:0 DPH0[7:0] Upper Byte of DPTR0 register
7:0 DPL0[7:0] Lower Byte of DPTR0 register

4.6.2.2 DPTR1 (Data Pointer 1 SFR)

Bits 7 6 5 4 3 2 1 0
Access: POR R/W:00
Name DPH1 (0x85)
Bits 7 6 5 4 3 2 1 0
Access: POR R/W:00
Name DPL1 (0x84)

Bits Name Description

7:0 DPH1[7:0] Upper Byte of DPTR1 register
7:0 DPL1[7:0] Lower Byte of DPTR1 register

4.6.2.3 DPS 0x86 (Data Pointer Select SFR)

Bits 7 6 5 4 3 2 1 0
Access: POR R/W:00
Name SEL

Bits Name Description

7:1 Reserved
0 SEL Select current DPTR

The data pointer select register is used in the following instructions:

■ MOVX @DPTR,A
■ MOVX A, @DPTR
■ MOVC A, @A+DPTR
■ JMP @A+DPTR
■ INC DPTR
■ MOV DPTR, #data16

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8051 Core

4.6.3 24-Bit Data Pointer SFRs

Extended data pointer SFRs DPX0, DPX1, MXAX, and P2AX hold the most significant parts of memory addresses during
access to the external data memory space. After reset, each of these registers have 0x00 values.

4.6.3.1 DPX0 0x93 (Data Pointer 0 eXtended SFR)

Bits 7 6 5 4 3 2 1 0
Access: POR R/W:00
Name DPX0

Bits Name Description

During MOVX instruction using DPTR0 register, the most significant part of address
7:0 DPX0[7:0]
XRAMADDR[23:16] is always equal to the contents of DPX0 (SFR 0x93).

4.6.3.2 DPX1 0x95 (Data Pointer 1 eXtended SFR)

Bits 7 6 5 4 3 2 1 0
Access: POR R/W:00
Name DPX1

Bits Name Description

During MOVX instruction using DPTR1 register, the most significant part of address
7:0 DPX1[7:0]
XRAMADDR[23:16] is always equal to the contents of DPX1 (SFR 0x95).

4.6.3.3 MXAX 0xEA (MOVX @Ri eXtended SFR)

Bits 7 6 5 4 3 2 1 0
Access: POR R/W:00
Name MXAX

Bits Name Description

During MOVX using R0 or R1 register, XRAMADDR[23:16] is always equal to contents
7:0 MXAX[7:0]
of MXAX (SFR 0xEA).

4.6.3.4 P2AX 0xA0 (P2 Read-Write SFR)

Bits 7 6 5 4 3 2 1 0
Access: POR R/W:00
Name P2AX

Bits Name Description

During MOVX using R0 or R1 register, XRAMADDR[15:8] is always equal to the contents
7:0 P2AX[7:0]
of P2AX (SFR 0xA0).

During a MOVX instruction using the DPTR0/DPTR1 register, XRAMADDR[23:16] is always equal to the contents of DPX0
(SFR 0x93) / DPX1 (SFR 0x95).
During a MOVX instruction using the R0 or R1 register, XRAMADDR[23:16] is always equal to the contents of MXAX (SFR
0xEA), and XRAMADDR[15:8] is always equal to the contents of P2AX (SFR 0xA0).

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 8051 Core

4.6.4 I/O Port Access SFRs

Each I/O port supports two interfaces:
■ PHUB bus – allows boot configuration and access to all I/O port registers

■ SFR bus – allows faster access to a limited set of I/O port registers
SFR registers contain three registers for each I/O port, making a total of 27 registers for 9 I/O ports. The registers function in
this manner:
■ SFRPRTxDR – sets the output data state of the port (where x is port number and includes ports 0-6, 12, and 15)

■ SFRPRTxSEL – selects each SFRPRTxDR register bit to set the output state of corresponding pin:
❐ If the SFRPRTxSEL[y] bit is high, the SFRPRTxDR[y] bit sets the output state for the pin
❐ If the SFRPRTxSEL[y] bit is low, PRTxDR[y] of port logic sets the output state of the pin (where y varies from 0 to 7)
■ SFRPRTxPS – a read-only register that contains pin state values of the port pins

Figure 4-3 shows the connections between the 8051 and the I/O ports.

Figure 4-3. SFR – I/O Connections

SFRPRT0DR
I/O
SFRPRT0SEL Port 0

SFRPRT15DR
I/O
8051
SFRs SFRPRT15SEL Port 15
Core

SFRPRT15PS

SFRPRT0PS

4.6.5 Interrupt Enable (IE)

Bit 7 of IE (SFR 0xA8) enables or disables all 8051 interrupts.

4.6.5.1 Interrupt Enable 0xA8

7 6 5 4 3 2 1 0
Access: POR RW: 00
Bit Name EA

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8051 Core

4.7 Program and External Data 4.7.2 External Data Space

Spaces The 8051 can address up to 16 MB external data memory
(see the Memory Map chapter on page 141). This memory
The 8051 has separate address spaces for program and is accessed by MOVX instructions only.
data memory. The Internal, External, SFRs, and Program
memory areas have their own address spaces. Data mem-
ory is divided onto 16 MB of external and 256 bytes of inter- 4.8 CPU Halt Mechanisms
nal data memory, with an additional 128 bytes of SFR
The CPU halts in the following circumstances:
memory area.
■ Boot Logic – asserted when the part comes out of reset
4.7.1 Program Space – the CPU remains halted until the boot process com-
pletes.
Program memory space begins at address 0x0000 and
■ Miscellaneous Logic – writing a ‘1’ to the stop bit in regis-
ends at address 0xFFFF. The 16-bit Program Counter regis-
ter MLOGIC.CPU.SCR[0] asserts a halt request to the
ter (PC) points to the next instruction to be read. Data can
CPU. The CPU remains stopped until a DMA, reset, or
be read from the program space, but only through the
the DoC sets this bit to ‘0’.
MOVC instruction.
■ Debug on-Chip (DoC) – when the debugger is enabled,
On reset, the PC is set to 0x0000. In the standard 8051, the a DoC halt request is asserted by writing to
instruction at address 0x0000 is usually a JMP, because DBG_CTRL[1]. See the 8051 Debug on-Chip chapter on
interrupt vectors are hard-located at addresses 0x0003, page 455.
0x000B, 0x0013, 0x001B, and so on. Because CY8C38 has
a vectored interrupt controller, the 8051 can simply start
executing code at address 0x0000.

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 5. Cortex™-M3 Microcontroller

The PSoC 5 ARM Cortex-M3 core is a high performance, low power 32-bit Central Processing Unit (CPU). It has an efficient
Harvard 3-stage pipeline core, a fixed 4 GB memory map, and supports the 16/32-bit Thumb-2 instruction set. The Cortex-M3
also features hardware divide instructions and low-latency ISR (Interrupt Service Routine) entry and exit.

The Cortex-M3 processor includes a number of other components that are tightly linked to the CPU core. These include a
Nested Vectored Interrupt Controller (NVIC), a SYSTICK timer, and numerous debug and trace blocks.

This section gives an overview of the Cortex-M3 processor. For further details please see the ARM Cortex-M3 Technical Ref-
erence Manual available at http://www.arm.com. Figure 5-1 shows a diagram of the Cortex-M3 and its interface to different
blocks on the device.

5.1 Features
■ Three stage pipelining operating at 1.25 DMIPS/MHz. This helps to increase execution speed or reduce power.
■ Supports Thumb-2 instruction set:
❐ The Thumb-2 instruction set supports complex operations with both 16- and 32-bit instructions
❐ Atomic bit level read and write instructions
❐ Support for unaligned memory access
■ Improved code density, ensuring efficient use of memory.
■ Easy to use, ease of programmability and debugging:
❐ Ensures easier migration from 8- and 16-bit processors
■ Nested Vectored Interrupt Controller (NVIC) unit to support interrupts and exceptions:
❐ Helps to achieve rapid interrupt response
■ Extensive debug support including:
❐ Serial Wire Debug Port (SWD-DP), Serial Wire JTAG Debug Port (SWJ-DP)
❐ Break points
❐ Flash patch
❐ Instruction tracing
❐ Code tracing

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Cortex™-M3 Microcontroller

Figure 5-1. PSoC 5 Cortex-M3 Block Diagram

Data
Nested
Interrupt Inputs Watchpoint and
Vectored Cortex M3 CPU Core Embedded
Trace (DWT)
Interrupt Trace Module
Controller (ETM)
(NVIC)
Instrumentation
Trace Module
I- Bus D-Bus S-Bus (ITM)
Trace Pins:
JTAG/SWD Debug Block Trace Port 5 for TRACEPORT or
(Serial and Flash Patch Interface Unit 1 for SWV mode
JTAG) and Breakpoint (TPIU)
(FPB)
C-Bus Cortex M3 Wrapper

AHB AHB

32 KB Bus
SRAM Matrix Bus 256 KB
Matrix Cache ECC
Flash

AHB

32 KB Bus
SRAM Matrix
AHB Bridge & Bus Matrix DMA

PHUB

AHB Spokes

GPIO & Prog. Prog. Special

EMIF Digital Analog Functions

Peripherals

The bus interfaces in the Cortex-M3 are based on AHB-Lite

(Advanced High Performance Bus-Lite) and the APB
(Advanced Peripheral Bus) protocols.

The bus interfaces available in the Cortex-M3 are:

■ I-Code Bus for instruction fetches
■ D-Code Bus for data fetches
■ System Bus for instruction and data fetches in memory
regions 0x20000000 to 0xDFFFFFFF and 0xE0100000
to 0xFFFFFFFF
■ External Private Peripheral Bus used to debug compo-
nents
■ Debug Access Port used to connect the debug interface
blocks such as SWJ-DP

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 Cortex™-M3 Microcontroller

5.2 How it Works

The Cortex-M3 is a 32-bit processor with a 32-bit data path,
32-bit register, and a 32-bit memory interface. It supports
both 16-bit and 32-bit instructions in the Thumb-2 instruction
set. Since the Cortex-M3 does not support the ARM instruc-
tion set it is not backward compatible with the ARM7 proces-
sor.

The processor supports two operating modes: a single cycle

32-bit multiplication instruction, and hardware divide instruc-
tions.

5.2.1 Registers
The Cortex-M3 has 16 32-bit registers (Figure 5-2). They
are:
■ R0 to R12 - general purpose registers
❐ R0 to R7 – can be accessed by all instructions
❐ R8 to R12 – can be accessed by all 32-bit and some
16-bit instructions
■ R13 – Stack Pointer (SP). There are two stack pointers,
with only one available at a time. The SP is always 32-bit
word aligned; bits [1:0] are always ignored and consid-
ered to be ‘0’.
■ R14 – Link register. Stores the return program counter
during function calls.
■ R15 – Program counter. This register can be written to
control program flow.

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Cortex™-M3 Microcontroller

Figure 5-2. Cortex-M3 Registers

R0 General Purpose Register

R1 General Purpose Register

R2 General Purpose Register

R3 General Purpose Register

R4 General Purpose Register

R5
General Purpose Register

Low Registers
R6 General Purpose Register

R7 General Purpose Register

R8 General Purpose Register

R9 General Purpose Register

High Registers

R10 General Purpose Register

R11 General Purpose Register

R12 General Purpose Register

R13 (MSP) R13 (PSP) Main Stack Pointer (MSP),

Process Stack Pointer (PSP)

R14 Link Register

R15 Program Counter

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 Cortex™-M3 Microcontroller

5.2.1.1 Special Registers

The special registers can be accessed only using special instructions and cannot be used for normal data processing. Cortex-
M3 supports three sets of special registers:

Figure 5-3. Cortex-M3 Special Registers

xPSR Program Status registers

PRIMASK

Special registers
FAULTMASK Interrupt Mask registers

BASEPRI

CONTROL Control register

Program Status Registers

These registers consist of:

■ Application Program Status Register (APSR)
■ Interrupt Program Status Register (IPSR)
■ Execution Program Status Register (EPSR)

These registers provide ALU flags (zero, carry), execution status, and current executing interrupt number. The three PSRs
can be accessed separately or collectively, using the special instructions MSR and MRS. They can be collectively addressed
as xPSR.

Figure 5-4. Cortex-M3 Program Status Registers

xPSR 31 30 29 28 27 26:25 24 23:20 19:16 15:10 9 8:0

N Z C V Q ICI/IT T -- -- ICI/IT - Exception Number

Where: Interrupt Mask Registers

■ N – Negative Flag ■ PRIMASK – Used to disable all interrupts except the
■ Z – Zero Flag Nonmaskable Interrupt (NMI) and HardFault

■ C – Carry/Borrow Flag ■ FAULTMASK – Used to disable all interrupts except NMI

■ V – Overflow Flag ■ BASEPRI – Used to disable interrupts of specified or

lower priority levels.
■ Q – Sticky Saturation Flag
■ ICI / IT – Interrupt-Continual Instruction (ICI) bits / IF- These registers are used by the NVIC to mask an interrupt
THEN instruction status bit or exception.

■ T – Thumb-2 Instruction. Always set to 1. Clearing this

results in an exception
■ Exception Number – Indicates which exception the pro-
cessor is currently handling

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Cortex™-M3 Microcontroller

Control Register When the code is in user level, it cannot access the debug
resources and certain important registers.
This register controls the stack pointer selection and the
privilege level of the processor. It has only two bits: In addition to the privilege levels, the processor supports
two types of operating modes:
CONTROL[0]
■ Thread Mode – Thread mode is used by all normal
‘0’ Privileged in Thread Mode applications. During the thread mode the Process Stack
‘1’ User state in Thread mode Pointer (PSP) is used. The thread mode can exist in
both privileged level and user level. Switching from privi-
CONTROL[1] leged level to user level can be done by just writing to
‘0’ Default stack is used the control register but the reverse cannot be done.
When an exception occurs, the system is automatically
‘1’ Alternate stack is used taken to privileged level and at the exit of the exception it
comes back to the user level. Restoring to the privileged
5.2.2 Operating Modes level can be done only by going through an exception
handler that programs the control register for the privi-
The Cortex-M3 supports two privilege levels:
leged mode.
■ Privileged – Code has no limit to resources
■ Handle Mode – Handle mode is used by OS kernel and
■ User – Code has some limits to the resources exception handlers. During this mode, the main stack
Privilege level can be controlled using the control register. pointer (MSP) is used. The handle mode can exist only
in the privileged level.

Figure 5-5. Operating Modes

Privilege Level

User Privileged

n/a Handle Mode

Thread Mode

Handle Mode: running an interrupt service routine

Thread Mode: running background code

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 Cortex™-M3 Microcontroller

Figure 5-6. Operating Mode Transitions

Privileged Handle
Exception Mode
Entry / Exit
Exception
Program Entry / Exit
Control
Register Privileged Thread Default
User Thread Mode
Mode

5.2.3 Pipelining ■ Saturation

■ Miscellaneous
The three stage pipelining includes:
■ Fetch – The instruction is fetched from memory Cortex-M3 supports unique instructions. The following table
is a summary of the important instructions:
■ Decode – Generating the addresses and branch predic-
tion Table 5-1. Cortex-M3 Unique Instructions
■ Execute – Instruction execution based on the address
Instruction Functionality
and branches
MSR, MRS To access special registers
The branch prediction unit has been enhanced so that it IF-THEN instruction supporting up to 4 succeed-
IT
gives nearly no ALU usage penalty. ing instructions
CBZ, CBNZ Compare and then branch
Pipelining can give zero to two wait states when executing
SDIV, UDIV Signed and Unsigned Divide
an instruction.
Reverse the byte order in data word, upper half
REV, REVH, REVSH
word, lower half word, respectively
5.2.4 Thumb-2 Instruction Set RBIT Reverses bit order in a data word
SXTB, SXTH, UXTB,
The Cortex-M3 supports a wide range of 16- and 32-bit UXTH
Extend a byte or half word into a word
instructions. It does not support all ARM instructions, includ-
BFC - Clears any number of adjacent bits in any
ing: position
BFC, BFI
■ Branch with link and exchange state BFI – Copies any number of bits from any register
to another register to any mentioned location
■ Switch endian UBFX, SBFX Unsigned and signed bit field extract instructions
■ Certain coprocessor instructions LDRD, STRD Transfer 2 words of data from or into 2 registers

■ Hint instructions TBB, TBH

Table Branch Byte and Table Branch Halfword for
branch tables
■ DSP instructions
■ Change process instructions The sections beginning with 5.2.3.1 detail some of the
instruction types. For the entire summary of the instruction
The instruction includes these data processing operations:
set, refer to the ARMv7-M Application Level Architecture
■ Multiply and divide Reference Manual available at http://www.arm.com.
■ Bit
■ Shift 5.2.4.1 Data Processing Operations
■ Load store The Cortex-M3 provides many different instructions for data
■ Branch processing. A few basics are introduced here. Many data
operation instructions can have multiple instruction formats.
■ Barrier
■ Exception generating The Cortex-M3 supports arithmetic functions ADD, SUB
(subtract), MUL (multiply), and UDIV/SDIV (unsigned and
■ System
signed divide).

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Cortex™-M3 Microcontroller

The Cortex-M3 supports 32-bit multiply instructions and mul- ■ Call and Unconditional branch instructions
tiply accumulate instructions that give 64-bit results. These ■ Decision and Conditional branch instructions
instructions support signed or unsigned values.
■ Combined Compare and Conditional Branch
Another group of data processing instructions are logical ■ Conditional Branching using IT instructions
operations such as AND, ORR (or), EOR (exclusive OR),
and rotate and shift functions. In some cases the rotate The IT (IF-THEN) instruction block is very useful for han-
operation can be combined with other operations. dling small conditional code. It avoids branch penalties
because there is no change to program flow. It can provide a
Another group of data processing instructions is used for maximum of four conditionally executed instructions with
reversing data bytes in a register. These instructions are one condition check.
usually used for conversion between little endian and big
endian data. 5.2.4.4 Instruction Barrier and Memory
The last group of data processing instructions is for bit field Barrier Instructions
processing. Instructions such as BFC, BFI, SBFX, and The Cortex-M3 supports a number of barrier instructions.
UBFX are used to clear, set, and copy bits with sign exten- These instructions are needed with complex memory sys-
sion or zero extension. tems. In some cases, if memory barrier instructions are not
used, race conditions can occur.
5.2.4.2 Load Store Operations
There are three barrier instructions in the Cortex-M3:
One of the most basic functions in a processor is transfer of
■ DMB (Data Memory Barrier) – Ensures that all memory
data. In the Cortex-M3, data transfers can be one of the fol-
accesses are completed before new memory access is
lowing types:
committed. For example, when you do a data write fol-
■ Moving data between register and register lowed immediately by a read on a dual port memory, if
■ Moving data between memory and register the memory write is buffered, the DMB instruction can be
■ Moving data between special register and register used to ensure the read gets the updated value.
■ Moving an immediate data value into a register ■ DSB (Data Synchronization Barrier) – Ensures that all
memory accesses are completed before the next
The command to move data between registers is MOV instruction is executed
(move). For example, moving data from register R3 to regis-
■ ISB (Instruction Synchronization Barrier) – Flushes the
ter R8 looks like this:
pipeline and ensures that all previous instructions are
MOV R8, R3 completed before executing new instructions

Another instruction can generate the negative value of the 5.2.4.5 Saturation Operations
original data; it is called MVN (move negative).
The Cortex-M3 supports two instructions that provide signed
The basic instructions for accessing memory are Load and and unsigned saturation operations: SSAT and USAT (for
Store. Load (LDR) transfers data from memory to registers, signed data type and unsigned data type, respectively).
and Store transfers data from registers to memory. The
transfers can be in different data sizes (byte, half word, Saturation is commonly used in signal processing, for exam-
word, and double word). ple, in signal amplification.

Multiple Load and Store operations can be combined into The saturation operation does not prevent the distortion of
single instructions called LDM (Load Multiple) and STM the signal, but the amount of distortion is greatly reduced in
(Store Multiple). the signal waveform.

ARM processors also support memory accesses with pre- 5.2.5 SysTick Timer
indexing and post-indexing. Two other types of memory
operation are stack PUSH and stack POP. The SysTick timer is integrated with the NVIC and gener-
ates the SYSTICK interrupt. This interrupt can be used for
The Cortex-M3 has a number of special registers. To access task management in a real time system. The timer has a
these registers, use the instructions MRS and MSR. reload register with 24 bits available to use as a countdown
value. The timer can take an internal clock (the free running
5.2.4.3 Branch Operations clock on the CM3 processor) or an external clock through
The branch operations include:

74 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Cortex™-M3 Microcontroller

the STCLK. In PSoC 5 devices use one of three sources as, tions. Some instructions cannot support unaligned
ILO (1 kHz), ILO_100 (100 kHz), or the SYSCLK (BUSCLK). accesses.

You can execute code from within the code, SRAM, or the
5.2.6 Debug and Trace: external RAM space.
The Cortex-M3 provides a wide range of debugging compo- The Cortex-M3 uses little-endian format.
nents. The debug unit is tightly linked with the core.

The important features of the debug and trace are: 5.3.1 Bus Interface to SRAM Memory
■ Debug access to all memory and registers in the system The 64 KB of SRAM in PSoC 5 is split into two 32 KB of
including Cortex-M3 register bank when the core is run- SRAM. The SRAM can be accessed by the C-Bus, S-Bus,
ning, halted, or held in reset. and the PHUB's DMA. The priority decoder gives a higher
■ Serial Wire Debug Port (SW-DP) and Serial Wire JTAG priority to the C-Bus in the upper 32 KB of SRAM, whereas
Debug Port (SWJ-DP) debug access. the PHUB DMA takes a higher priority in the lower 32 KB of
■ Flash Patch and Breakpoint (FPB) unit for implementing SRAM. The upper and lower halves of SRAM can be
breakpoints and code patches. accessed simultaneously but with different buses.

■ Data Watchpoint and Trace (DWT) unit for implementing

watchpoints, data tracing, and system profiling.
■ Support for six breakpoints and four watchpoints.
■ Instrumentation Trace Macrocell (ITM) for support of
printf style debugging.
■ Embedded Trace Macrocell (ETM) for instruction trace.
■ Trace Port Interface Unit (TPIU) for bridging to a Trace
Port Analyzer (TPA).

The Cortex-M3 supports a separate debug and trace inter-

face. The debug interface uses the APB (Access Port Bus),
which supports both JTAG and SWD. The trace interface
uses the TPIU (Trace Port Interface Unit).

For further details about the debug and trace feature, refer
to the Test Controller chapter on page 443 and the 8051
Debug on-Chip chapter on page 455.

5.3 Memory Map

The Cortex-M3 has a linear 32-bit (4 GB) address space, as
shown in Figure 5-7. See also the Memory Map chapter on
page 141.

The address space includes two bit-band alias regions, one

for the SRAM space and the other for the Peripherals space.
Accesses to a bit-band alias region affect individual bits in
the corresponding bit-band region. For example, writing a 1
to address 0x22000000 sets bit 0 of address 0x20000000,
and writing a 0 to address 0x42000004 clears bit 1 of
address 0x40000000. Reading address 0x22000008 returns
a 1 or 0, depending on the value of bit 2 of address
0x20000000.

The processor supports unaligned accesses. Unlike aligned

access where the data can be situated only at even
addresses, the unaligned accesses support data operations
at odd addresses also. Unaligned accesses have limita-

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 75

Cortex™-M3 Microcontroller

Figure 5-7. Cortex-M3 Memory Map

0xE00FF000
ROM Table
0xE00FEFFF
External Private
Peripheral Bus
0xE0042000
ETM
0xE0041000
0xFFFFFFFF
TPIU
0xE0040000
Vendor Specific
0xE0100000
Private Peripheral Bus: 0xE00FFFFF
Debug/External 0xE0040000
0xE003FFFF Private Peripheral Bus: 0xE003FFFF
Reserved
Internal 0xE0000000
0xE000F000
NVIC 0xDFFFFFFF
0xE000DFFF
Reserved
0xE0003000 External Device
FPB
0xE0002000
DWT
0xE0001000
ITM 1 GB
0xE0000000 0xA0000000
0x9FFFFFFF

0x43FFFFFF
External RAM
Bit-Band Alias
0x42000000 32 MB
0x41FFFFFF 1 GB
31 MB 0x60000000
0x40100000 0x5FFFFFFF
Bit-Band region
0x40000000 1 MB Peripherals
0.5 GB 0x40000000
0x3FFFFFFF
0x23FFFFFF

Bit-Band Alias SRAM

0x22000000 32 MB 0.5 GB 0x20000000
0x21FFFFFF
0x1FFFFFFF
31 MB
0x20100000
Bit-Band region Code
0x20000000 1 MB
0.5 GB 0x00000000

5.4 Exceptions system exceptions and 16 and above for external interrupt
inputs. PSoC 5 architecture supports 32 external interrupts.
The Cortex-M3 provides a feature-packed exception archi-
The exceptions are handled by the NVIC.
tecture that supports a number of system exceptions and
external interrupts. Exceptions are numbered 1 to 15 for

76 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Cortex™-M3 Microcontroller

Most of the exceptions have programmable priority, and a few have fixed priority. Table 5-2 shows the list of exceptions avail-
able in the Cortex-M3:

Table 5-2. PSoC 5 Exceptions

Interrupt
Exception Type Priority Comment
Number
1 Reset -3 (highest) Not programmable Reset
2 NMI -2 Not programmable Non-Maskable Interrupt
3 Hard Fault -1 Not Programmable All fault conditions if the corresponding handler is not enabled
4 MemManage Fault Programmable Memory management fault; access to illegal locations
Bus error occurs when AHB interface receives an error response from a
5 Bus Fault Programmable bus slave (also called prefetch abort if it is an instruction fetch or data
abort if it is a data access)
6 Usage Fault Programmable Exceptions due to program error
7 Reserved NA –
8 Reserved NA –
9 Reserved NA –
10 Reserved NA –
11 SVCall Programmable System Service Call
12 Debug Monitor Programmable Debug monitor (watchpoints, breakpoints, external debug request)
13 Reserved NA –
14 PendSV Programmable Pendable request for system device
15 SYSTICK Programmable System Tick Timer

The value of the current running exception is indicated by ■ Bus faults

the special register IPSR or from the NVIC's Interrupt Con- ■ Memory Management Faults
trol State Register (the VECTACTIVE field).
■ Usage Faults
Interrupts are a subset of exceptions. So exceptions are ■ Hard Faults
handled the same way as an interrupt. The exception han-
dler for each exception is stored in the interrupt vector table. The faults can be enabled by setting the corresponding bits
The vector table begins with the exception handler and is in the handler control and state register. The reason for a
followed by the interrupt service routine addresses. The vec- particular fault is updated in the corresponding status regis-
tor table pointer is dynamically changeable. Also, if the vec- ter (for example, BFSR register for bus fault, MFSR for
tor table is in SRAM, then vectors can be dynamically memory management fault, UFSR for Usage Fault, HFSR
changeable. for Hard Fault). These registers can be read to know the
exact reason for fault.
5.4.1 Priority Definitions When these types of faults (except vector fetches) take
place, and if the corresponding exception handler is enabled
In the Cortex-M3, whether and when an exception can be
and no other exceptions with the same or higher priority are
carried out can be affected by the priority of the exception. A
running, the fault exception handler will be executed. If the
higher priority (smaller number in priority level) exception
exception handler is enabled but at the same time the core
can preempt a lower priority (larger number in priority level)
receives another exception handler/interrupt with higher pri-
exception; this is the nested exception/interrupt scenario.
ority, this fault exception handler will be pending and will be
From the above table, you can see that some of the excep-
executed after the high priority exception/interrupt has com-
tions (reset, NMI, and hard fault) have fixed priority levels.
pleted its execution.
They are negative numbers to indicate that they are higher
priority than other exceptions. Other exceptions have pro- If the fault handler is not enabled or when the fault happens
grammable priority levels. in an exception handler that has the same or higher priority
than the current fault handler, the hard fault handler will be
5.4.2 Fault Exceptions executed instead.

A number of system exceptions are useful for fault handling. Bus Faults
There are several categories of faults:

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Cortex™-M3 Microcontroller

Bus faults are produced when an error response is received SVC

during a transfer on the AHB interfaces. It can happen dur-
SVC is for generating system function calls. It can be config-
ing prefetch, data read/write, or during stacking and un-
ured to generate an interrupt. This interrupt can be used for
stacking operations.
task management in a realtime system. SVC is generated
using the SVC instruction.
Memory Management Faults
Memory management faults can be caused by certain illegal PendSV
accesses, including the following:
PendSV works with SVC in the OS. Although SVC (by SVC
■ Trying to execute code from non-executable memory instruction) cannot be pended (an application calling SVC
regions will expect the required task to be done immediately),
■ Writing to read-only regions PendSV can be pended and is useful for an OS to pend an
■ Access in the user state to a region defined as privileged exception so that an action can be performed after other
access only important tasks are completed. PendSV is generated by
writing ‘1’ to the NVIC PendSV pending register. A typical
Usage Faults use of PendSV is context switching.

Usage faults can be caused by a number of things, including SysTick Timer Exception
the following:
The SysTick Timer exception takes the vector number 15.
■ Undefined instructions
Cortex-M3 supports a 24-bit down counter. This timer is very
■ Coprocessor instructions (the Cortex-M3 processor does useful to perform task management where the software can
not support a coprocessor, but it is possible to use the be handled inside the timer interrupt.
fault exception mechanism to run software compiled for
other Cortex processors via coprocessor emulation) The SYSTICK Timer can be used to generate interrupts. It
has a dedicated exception type and exception vector. It
■ Trying to switch to the ARM state (software can use this
makes porting operating systems and software easier
faulting mechanism to test whether the processor on
because t he process is the same across different Cortex-
which it runs supports ARM code; since the Cortex-M3
M3 products.
does not support the ARM state, a usage fault takes
place if there is an attempt to switch) The SYSTICK Timer is controlled by four registers. Of the
■ Invalid interrupt return (link register contains invalid/ four registers, TICKINT is used to enable or disable the
incorrect values) timer exception.

■ Unaligned memory accesses using multiple load or store

instructions 5.5 Nested Vector Interrupt
It is also possible, by setting up certain control bits in the Controller (NVIC)
NVIC, to generate usage faults for:
The Nested Vectored Interrupt Controller, or NVIC, is an
■ Divide by zero
integral part of the Cortex-M3 processor. It is closely linked
■ Any unaligned memory accesses to the Cortex-M3 CPU core logic. Its control registers are
accessible as memory-mapped devices. Besides control
Hard Faults registers and control logic for interrupt processing, the NVIC
The hard fault handler can be caused by: also contains control registers for the SYSTICK Timer, and
debugging controls.
■ Usage faults, bus faults, and memory management
faults if their handler cannot be executed. Following are the important features of the NVIC:
■ Bus faults during vector fetch (reading of a vector table ■ Supports 32 interrupts and 16 exceptions.
during exception handling). ■ Configurable priority levels.
■ Dynamic reprioritization of interrupts.
5.4.3 System Call Exceptions
■ Support for nested interrupts
SVC (System Service Call) and PendSV (Pended System
■ Programmable interrupt vector
Call) are two exceptions targeted at software and operating
■ Supports tail-chaining and late arrival interrupts. This
systems.
enables back-to-back interrupt processing without the

78 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Cortex™-M3 Microcontroller

overhead of state saving and restoration between inter- 5.5.1.1 Example Procedures in Setting Up
rupts. an Interrupt
■ Processor state automatically saved upon interrupt
Here is a simple example procedure for setting up an inter-
entry, and restored upon interrupt exit, with no instruc-
rupt:
tion overhead.
1. Copy the Hard Fault and NMI handlers to a new vector
table location if vector table relocation is required. (In
5.5.1 Basic Interrupt Configuration simple applications, this might not be needed.)
Each external interrupt has several associated registers. 2. The Vector Table Offset register should also be set up to
■ Enable and Clear Enable get the vector table ready (optional).
3. Set up the interrupt vector for the interrupt. Since the
■ Set Pending and Clear Pending
vector table could have been relocated, you might need
■ Priority Level to read the Vector Table Offset register; then calculate
■ Active Status the correct memory location for your interrupt handler.
This step might not be needed if the vector is hardcoded
■ Exception-masking registers (PRIMASK, FAULTMASK,
in ROM.
and BASEPRI)
4. Set up the priority level for the interrupt.
■ Vector Table Offset
5. Enable the interrupt.
The interrupt enable and clear enable registers are 32-bit
registers. They are used to enable/disable an interrupt. An 5.5.2 Nested Interrupts
interrupt that is waiting for the CPU execution sets the pend-
Nested interrupt support is built into the Cortex-M3 proces-
ing bit in the set pending register. Once the interrupt has
sor core and the NVIC. The nesting is done based on the
been executed by the CPU, the interrupt is cleared automat-
priority of the interrupts. When the processor is handling an
ically by setting the clear-pending register. The interrupts
exception, all other exceptions with the same or lower prior-
can take priorities 0 to 7. The priorities are configured using
ity will be blocked. When a high priority interrupt occurs, the
the 3-bit priority registers. They can be dynamically config-
low priority interrupt is nested and the high priority interrupt
ured during run time.
completes the execution. Since automatic hardware stack-
The Active Status register stores the details of the interrupt ing and unstacking is done, nesting is done without risk of
currently active. A bit set in this register indicates that the losing data in registers. Since Cortex-M3 uses the main
corresponding interrupt is currently active. An interrupt is stack to store the nesting interrupt details, care should be
called active if it is currently executed by the CPU or if it is taken to ensure sufficient stack space is available.
already nested and put to the stack. Once the interrupt exe-
Reentrant exceptions are not supported in the Cortex-M3.
cution is complete, the active status bit of the interrupt is
automatically cleared. With PSoC 5 devices, the addresses
of the interrupt service routine are stored in the Interrupt 5.5.3 Tail-Chaining Interrupts
vector table. The interrupt vector table can be located either The Cortex-M3 uses a number of methods to improve inter-
in RAM or ROM. The position of the vector table is con- rupt latency. Tail-chaining is one such method.
trolled using the Vector Table Offset register.
When an exception takes place but the processor is han-
The exception masking registers, PRIMASK, FAULTMASK dling another exception of the same or higher priority, the
and BASEPRI, are special registers used to mask the inter- exception will be pended. When the processor has finished
rupts and exceptions. executing the current exception handler, instead of POP, the
■ PRIMASK – When set, all interrupts except NMI and registers go back into the stack and PUSH it back in again,
Fault interrupts are masked skipping the unstacking and the stacking. In this way the
■ FAULTMASK – When set, all interrupts except NMI are timing gap between the two exception handlers is greatly
masked reduced.

■ BASEPRI – Masks all interrupts at the specified priority

and lower priorities 5.5.4 Late Arrivals
Another feature that improves interrupt performance is late
arrival exception handling. When an exception takes place
and the processor has started the stacking process, and if
during this delay a new exception arrives with higher pre-

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Cortex™-M3 Microcontroller

emption priority, the late arrival exception will be processed

first.

For example, if Exception #1 (lower priority) takes place a

few cycles before Exception #2 (higher priority), the proces-
sor will behave such that Handler #2 is executed as soon as
the stacking completes. After this the Handler #1 will be exe-
cuted.

5.5.5 Interrupt Latency

The term interrupt latency refers to the delay from the start
of the interrupt request to the start of interrupt handler exe-
cution.
■ In the Cortex-M3 processor, if the memory system has
zero latency, and provided that the bus system design
allows vector fetch and stacking to happen at the same
time, the interrupt latency can be as low as 12 cycles.
This includes stacking the registers, vector fetch, and
fetching instructions for the interrupt handler. However,
this depends on memory access wait states and a few
other factors.
■ For tail-chaining interrupts, since there is no need to
carry out stacking operations, the latency of switching
from one exception handler to another exception handler
can be as low as 6 cycles.
■ When the processor is executing a multi-cycle instruc-
tion such as divide, load double, or store double, the
instruction could be abandoned and restarted after the
interrupt handler completes.
■ To reduce exception latency, the Cortex-M3 processor
allows exceptions in the middle of multiple load and
store instructions (LDM/STM). If the LDM/STM instruc-
tion is executing, the current memory accesses will be
completed, and the next register number will be saved in
the stacked xPSR (ICI bits). After the exception handler
completes, the multiple load/store will resume from the
point at which the transfer stopped.

5.5.6 Faults Related to Interrupts

Faults (bus fault, memory fault) can happen during the fol-
lowing stages of interrupt execution:
■ Stacking
■ Unstacking
■ Vector Fetches

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 6. PSoC 3 Cache Controller

The cache block is an instruction cache only. It is responsible for servicing instruction fetches from the CPU. It stores lines of
code from the flash in its internal buffer for fast accesses made by the CPU at a later time.

6.1 Features
■ Single Port Cache RAM (CRAM) – either one read or one write at a time
■ Instruction cache
■ Fully associative
■ 512 bytes total cache memory in PSoC 3
■ Control to enable and disable cache
■ Designed to put flash into sleep automatically to save power

6.2 Block Diagram

The PSoC 3 cache controller block diagram is in Figure 6-1.

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PSoC 3 Cache Controller

Figure 6-1. Cache Controller Block Diagram

CPU PHUB

LRU CPUIF BFILL PHUBIF

FLASHIF FLASHIF
CRAMIF CSRs
(clk_cpu ver) (clk_bus ver)

CRAM
64x64

ECC NV_WRAPPER

FLASH

CRAMIF logic handles the communication between the Figure 6-2. Cache Lines
cache and the other blocks -CPU, background fill (BFILL),
and PHUB requests.

6.3 Cache Memory Organization

and Addressing
PSoC 3 has a total of 512 bytes of cache memory, which is
divided into eight lines. A line is the cache channel where
group of bytes move in or out. Each line has an eight word
capacity and each word contains eight bytes. This gives
each cache line a 64 byte capacity. Bytes within a word are organized into a little endian format
With this structure, a cache location is addressed by where byte 0 is least significant byte.
addressing the line, the word in the line, and the byte in the Figure 6-3. Word Byte Order
word.

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 PSoC 3 Cache Controller

Each cache line has tag information. The address that is 6.3.2 Cache Line Locking:
used to look up the cache is broken down into these fields:
Each cache line can be locked so that it is not replaced at
Figure 6-4. Cache Byte Format next the flash instruction request. A cache line can be
locked by setting TAG_LOCK bit of corresponding tag regis-
ter CACHE_TAG [0…7] to 1.

6.3.3 Cache Line Loading in Firmware

Instruction fetch access selects the particular line with Firmware can be used to load instructions into the cache
matching tag value, word offset selects the particular word in directly and set the tags to allow the CPU to fetch instruc-
the line and byte offset selects a byte in a word. Firmware tions from the cache instead of flash.
can access these CRAM bytes and tag information.
Follow the steps
Tag information is available using the CACHE_TAG[0..7] 1. Clear CACHE_EN bit of CACHE_CR register to prevent
register. Cache RAM memory has the base address of instruction fetch from causing writes to CRAM during
0x30000. update.
2. Invalidate lines by clearing the appropriate tag register
6.3.1 Cache Operation bits (TAG_VALID bits of CACHE_TAG register) to pre-
vent instruction fetch from causing reads from the lines
You enable the cache by setting the CACHE_EN bit of the being loaded.
CACHE_CR register to 1. 3. Write CRAM locations corresponding to the bytes invali-
The CPU sends out instruction fetch request to CPUIF; dated in step 2.
CPUIF, which interfaces to Cache IF and Flash IF, deter- 4. Update appropriate tag register bits to mark as valid and
mines whether the instruction that is requested by CPU is lock modified lines. Setting lock bits will ensure that
already present in Cache (hit) or if not (miss), then it bytes do not get evicted from the cache.
accesses the instruction from either Flash, 8 byte pre-fetch 5. Set CACHE_EN to reactivate writes to cache CRAM
buffer of CPUIF or 8 byte prefetch buffer of BFILL (Back- caused by the cache misses.
ground fill).
6.3.4 Cache Line Replacement Policy
On cache miss and if the cache is enabled, CPUIF writes
the instruction fetched from the flash into CRAM, so that it is An instruction fetch requested by the CPU may not exist in
available in the next time CPU requests the same location. the cache. If the cache is full, then an existing valid cache
Moreover CPUIF has an 8-byte prefetch buffer that is used line is evicted from the cache to create room for new line.
to save all the instructions and operands each time the CPU The algorithm to select a line for eviction is the Least
requests. Note that each time the flash is requested it is Recently Used (LRU) line that is not locked.
always an 8 byte fetch. These 8 bytes are loaded into the
cache (if enabled) and the prefetch buffer of the CPUIF. The
CPUIF prefetch buffer contains its own tag information. This
forms an alternative to CRAM and allows the data in the
prefetch buffer to be immediately returned to the CPU if
there is address match rather than fetching from CRAM or
flash, thus reducing power and improving performance.

If the cache is disabled it is never updated by the hardware.

However, CPUIF still performs cache look ups and may pro-
duce hits. The instruction fetch request from the CPU is ser-
viced from the cache as a regular hit. In this mode, firmware
can update the cache and the tag values. This is useful for
the ISRs that require minimal latency, which can be loaded
into the cache manually in firmware.

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PSoC 3 Cache Controller

Figure 6-5. Replacement Policy

The LRU points to the cache line, which is the oldest of the it is good idea to also turn ON BFILL to improve cache per-
used cache lines. The cache line that is evicted can be the formance. However since background fill is a speculative
line which is pointed by the LRU, however if the line pointed function, it could be create what turns out to be wasteful
by LRU is locked, then the unlocked line which is closer is reads from the flash. Thus for highly power sensitive appli-
evicted. The process of replacing the cache line can be cations, it may be desirable to disable the BFILL function to
understood by above figure. save some power at the expense of performance.

An instruction fetch that produces a hit will mark that line as

the Most Recently Used (MRU) regardless of that line is 6.3.6 ECC (Error Correction Code)
locked or not. The ECC block checks the data read from the flash. It is
responsible for error detection and correction. The cache
6.3.5 Background Fill (BFILL): gets the error status from the ECC block. The error status
gets logged into firmware visible registers. If the error is cor-
Background fill fetches the data from the flash and writes
rectable, ECC block corrects it and updates the
into CRAM. When the CPU is waiting for an instruction fetch
CACHE_INT_LOG3 register. If the error is not correctable, it
and the cache controller encounter a miss on either a cache
updates the details of the flash location where error
line or an invalid word in a valid cache line, the background
occurred, into CACHE_INT_LOG4 register. This block can
fill state machine starts requesting the data from flash to fill
issue interrupt to the CPU, explained in the “interrupt” sec-
any invalid words on the MRU line of the cache. When the
tion.
BFILL reaches the end of the line, it wraps back to the
beginning of the MRU line.
6.3.6.1 Interrupts
Figure 6-6. Background Fill
There are four interrupts related to the cache controller that
are issued to the CPU. The interrupts can be enabled by
setting appropriate bits of CACHE_INT_MSK register.
1. ISR loading violation: If the cache is enabled and if firm-
ware tries to write into Cache tag or CRAM, then this
interrupt is issued. The write into the tag or CRAM will
not be executed. A log is created (the associated cache
line number where the violation happened), in
CACHE_INT_LOG0 register.
2. Coherency violation: This interrupt is caused by:
a. If the CACHE_EN bit of CACHE_CR register is set to
0 and write to tag register (CACHE_TAG) except bits
(23:16) is attempted
b. If the CACHE_EN bit is set to 0 and a write to line in
BFILL can be enabled by setting the BFILL_EN bit of CRAM is attempted whose corresponding
CACHE_CR register. Generally whenever cache is enabled, TAG_VALID is set

84 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 PSoC 3 Cache Controller

In both cases the write is allowed so that the.

CACHE_INT_LOG1 register can be accessed to see in
which cache line the error happened.
3. Duplicate Tag Violation: This interrupt occurs when
CACHE_EN bit is set to 0 and if firmware tries to create
two tags with the same tag address. CACHE_INT_LOG2
register can be accessed to see which two lines have
got the identical tags and the tag address.
4. ECC - Single Bit: This interrupt occurs when a single bit
error is encountered during a fill operation and was fixed.
CACHE_INT_LOG3 register is updated with the flash
location address where error occurred.
5. ECC- Multiple bits: This interrupt occurs when multiple
bit error is encountered during a fill operation. This error
cannot be fixed.CACHE_INT_LOG4 register is updated
with the flash location address where error occurred.

6.3.7 Flash Low Power Mode

The cache controller has the ability to send the flash into a
low power mode while continuing to run normally. When the
number of cache hits reaches the programmed threshold,
cache puts the flash into sleep thus saving the power.
Threshold value can be set in CACHE_LP_MODE register.
The flash is in low power mode until the next cache miss
occurs.

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PSoC 3 Cache Controller

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 7. PSoC 5 Cache Controller

The cache block is an Instruction cache only. It services instruction fetches from the CPU. It stores lines of code from the
flash in its internal buffer for fast accesses made by the CPU at a later time.

7.1 Features
■ Instruction cache
■ Direct mapped
■ 128 bytes total cache memory
■ Registers for measuring cache hit/miss ratios
■ Error correction code (ECC) support
■ Error logging and interrupt generation
■ Designed to put flash into sleep automatically to save power

7.2 Block Diagram

Figure 7-1 shows the system interaction with the cache block as well as the cache interfaces and data/instruction flow.

Figure 7-1. Cache Interfaces

CPU

2
5
Cache Control RAM PHUB
4

Flash Interface 3

FLASH SPC EMIF

11

External
Memory

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PSoC 5 Cache Controller

Table 7-1. Cache Operational Interfaces

Interface Function
1 CPU sends instruction fetch request through this interface to the cache and eventually receives back the instruction
2 When the CPU instruction fetch that gets a hit in the cache, it is retrieved from the cache memory (RAM) through this interface.
CPU instruction fetch (interface #1) that gets a miss in the cache is translated into one fetch request from the FLASH. The FLASH access time
3
is much larger than the Cache RAM access time, up to 4 CPU clock cycles.
Instructions returned from the FLASH are cached through this interface for later CPU use. Note that requests from the PHUB interface are
4
never cached.
The CPU can read and write data using this interface. The internal cache registers and RAM are also accessible and FLASH contents are
5
readable using this interface through PHUB’s special register spoke.

7.3 Cache Enabling and is executed and at the end of the code under measurement,
the HITMISS register should be read. The cache hit ratio
Disabling can be computed as-
To enable the cache, set the DISABLE bit (Bit 0) of Cache hit ratio = the number of cache hits (HITMISS
CACHE.CC_CTL register t to 0. [31:16])/Number of cache misses (HITMISS[15:0])

7.4 Code Protection and 7.6 Cache Induced Flash Low

Security Power Mode
The ECC block is responsible for error detection and correc- Flash is put to low power mode when the cache predicts that
tion. The cache gets the error status from the ECC block for a flash access is not needed in the near future, based on
requested fills from the flash. The error status gets logged reaching a programmed number of sequential hits. This fea-
into software visible registers in the cache. An uncorrectable ture helps to reduce the overall power consumption of the
error will prevent the fill data from being written into the device. The threshold value of sequential hits can be pro-
cache RAM and causes entire line to be invalidated. grammed in LP_MODE bits of CACHE.CC_CTL register. To
ECC_ADDR[0:28] field of CACHE.ECC_CORR register put the FLASH into low power mode immediately,
gives the flash address where error was detected; this LP_MODE bits should be set to 0. This should be done
address field is valid only when INT_VALID field of this reg- when executing code from SRAM.
ister is set to 1. Interrupt can also be generated on ECC cor-
rection by setting INT_ENB bit of CACHE.ECC_CORR 7.7 Sleep Mode Behavior
register.
When the device wakes up from low power modes, all cache
If ECC correction fails, then the flash address where error
data and tags are invalidated. However, all the cache regis-
happened can be obtained from CACHE.ECC_ERR regis-
ters (where cache settings are made) maintain their state
ter.
and are not reset. The cache will be refilled as the CPU
begins fetching instructions.
7.5 Invalidating the Cache Line Cache status on system reset:
Software can invalidate all cached data associated with an On reset, cache is invalidated and begins to fill with the first
interface by setting the Flush bit (Bit 2) of CACHE.CC_CTL request from the CPU.
register. Invalidate takes effect in 1 cycle and affects all
lines.
7.8 Cache Limitations
7.5.1 Measuring Cache Hits or Misses All instructions are assumed to be in the flash. There is no
The CACHE.HITMISS register provides two 16-bit counters direct path from the cache to the external memory. Instruc-
that count the number of cache hits and misses. To mea- tions from the external memory must be explicitly moved
sure the cache performance, reset the HITMISS register to into the flash by software, before they can be used by the
0 at the start of the block of code to measure. Then the code CPU.

88 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 PSoC 5 Cache Controller

Cache coherency is the software's responsibility; no hard-

ware mechanism exists to ensure coherency. If the software
modifies the FLASH or memory contents, it also needs to
invalidate the cache and ensure the new instruction is
fetched into the cache.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 89

PSoC 5 Cache Controller

90 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 8. PHUB and DMAC

PSoC® 3 and PSoC® 5 devices use a high-performance bus for peripheral access and bulk data transfer. The high-perfor-
mance bus and the associated central controller are known as the peripheral hub (PHUB). The PHUB is a programmable and
configurable central bus backbone within a PSoC 3 or PSoC 5 device that ties the various on-chip system elements together.
It consists of multiple spokes; each spoke is connected to one or more peripheral blocks. The PHUB also includes a direct
memory access controller (DMAC), which is used for data transfer. The DMAC supports multiple DMA channels.

There are two bus masters (blocks that can initiate bus traffic) in PSoC 3 and PSoC 5 devices. These are the DMAC and the
CPU. An arbiter in the PHUB is responsible for arbitrating requests from the CPU and the DMAC. Upon receiving a request
from the microcontroller or the DMAC, the PHUB relays the request to the appropriate peripheral spoke.

8.1 PHUB
PHUB manages arbitration between the CPU and the DMAC.

8.1.1 Features
The PHUB has the following features:
■ Industry-standard Advanced Microcontroller Bus Architecture High-performance Bus (AMBA -HB) lite protocol
■ 8 spokes connected to various peripherals
■ 8-/16-/32-bit data-width support
■ Peripherals of various address widths connected to the same spoke
■ Includes programmable DMAC with 24 direct memory access (DMA) channels
■ Byte order and data width difference translation

8.1.2 Block Diagram

Figure 8-1 on page 92 is the block diagram of the PHUB. The DMAC is also shown.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 91

PHUB and DMAC

Figure 8-1. PHUB Block Diagram

CPU

PHUB
CPU
Interface CHn
CSRs
Channel[n]
CHn
CSRs
Config/
Status

Channel
Arbitration

CFGMEM Spoke 0
Local
DMAC SRAM
Memory
TDMEM

Local Spoke /
PHUB
Config/Status Spoke Arbitration

Spokes to Peripherals

8.1.3 How It Works Table 8-1. Spoke Configuration

The PHUB is used to connect the CPU to memory and Address Data
Spoke Width Width Peripheral Names
peripherals, including SRAM, flash, EEPROM, analog sub- (in bits) (in bits)
system, digital blocks, digital filter block, and others. 0 14 32 SRAM

The PHUB connects to the peripherals using a spoke. There IO interface, port interrupt control unit
1 9 16
(PICU), external memory interface (EMIF)
are eight spokes. Each spoke connects to one or more
PHUB local spoke, power management,
peripherals. Each spoke is configured for: 2 19 32
clock, serial wire viewer (SWV), EEPROM
■ Address width – The address width of a spoke depends 3 11 16 Delta-sigma ADC, analog interface
on the maximum number of addresses required for the USB, CAN, fixed-function I2C, fixed-function
4 10 16
peripherals connected to the spoke. timers
5 11 32 Digital filter block (DFB)
■ Data width – The data width of a spoke can be 16 or
32 bits. Eight-bit data transfer can be performed on 16- UDB set 0 registers (including DSI, configu-
6 17 16
ration, and control registers), UDB interface
and 32-bit spokes.
UDB set 1 registers (including DSI, configu-
7 17 16
■ Number of peripherals – This depends on the device ration, and control registers)
architecture. Each spoke is usually connected to multiple
■ The peripherals connected to each spoke can have data
peripherals.
widths longer than the spoke. For example, a Delta-
Table 8-1 shows the address width, data width, and periph- Sigma ADC can support up to 20-bit data although it is
erals connected to each spoke in PSoC 3 and PSoC 5 placed in the 16-bit spoke (spoke 03).
device.
In this case, the PHUB uses an internal FIFO to accom-
modate the width differences during data transfer.

92 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 PHUB and DMAC

■ One peripheral can extend across multiple spokes. In 8.2 DMA Controller
this case, the peripheral will have different address
spaces that are connected to each spoke. The DMA Controller (DMAC) transfers data between mem-
For example, Table 8-1 shows that UDB registers ory and peripherals.
extend across two spokes. UDB registers can be ■ Uses the PHUB for data transfer
accessed in 8-bit mode and also in 16-bit mode. In this ■ Includes 24 DMA channels
case, the 8-bit mode access needs a different address
space than the 16-bit mode access though they reside in ■ Includes 128 transaction descriptors (TD)
the same spoke. ■ Eight levels of priority per channel
■ Peripherals of different data widths can be connected to ■ Transactions can be triggered by any digitally routable
a single spoke. signal, the CPU, or another DMA channel
An example of this is spoke 3, which is connected to the ■ Transactions can be stalled or canceled
analog interface (digital-to-analog converter) and delta-
■ Each transaction can be from 1 to 64 KB
sigma ADC. The delta-sigma ADC can support up to
20-bit data, and the digital-to-analog converter register is ■ Large transactions can be broken into smaller bursts of 1
8-bit. to 127 bytes.
■ Spoke 0 is connected to SRAM. The CPU can access ■ Each channel can be configured to generate an interrupt
the SRAM without going through the PHUB. The DMAC at the end of transfer
accesses the SRAM through PHUB. ■ Supports byte swapping, for conversion between big-
The spoke address width, data width, and peripherals are endian and little-endian formats
fixed in a device and cannot be changed. The spoke and the ■ Handles data-width differences
peripheral details affect the time required for data transfer.
interspoke and intraspoke transfers take different amounts 8.2.1 Local Memory
of time.
As shown in Figure 8-1 on page 92, the PHUB includes
The effects of spoke data width, and interspoke and intra- local memory to store configuration data. The local memo-
spoke transfer, on latency of data transfer are explained in ries are called
8.1.4 Arbiter.
■ Configuration memory (CFGMEM)
■ Transaction descriptor memory (TDMEM)
8.1.4 Arbiter
The PHUB also includes a 16-byte FIFO for data handling
The PHUB receives data read or write requests from either
during data transfers.
the CPU or the DMAC. The PHUB processes each request
to determine which spoke and peripheral should be The CGFMEM is used to store the DMA channel configura-
accessed, and then manages the data access. tion data. There are two registers: CFGMEMn.CFG0 and
CFGMEMn.CFG1 (where n can be from 0 to 23) for each
When the DMAC and CPU initiate transactions in the PHUB
channel. Each register is 32 bits, so the size of CFGMEM is
at the same time, the arbiter decides which request has pri-
8 bytes × 24 channels = 192 bytes.
ority. The priority can be configured for every spoke except
spoke 0. Spoke 0 is accessed only by the DMAC because The TDMEM is used to store the TD configuration data,
the CPU has a separate interface to SRAM. You can config- which includes the number of bytes to transfer, source
ure priority using the “spk_cpu_pri” bits in the PHUB_CFG address, destination address, next TD, and other configura-
register. tion data. Each TD has two registers: TDMEMn.ORIG_TD0
and TDMEMn.ORIG_TD1. Each register is 32 bits, so the
When the CPU and DMAC access different spokes simulta-
size of TDMEM is 8 bytes × 128 TDs = 1 KB of memory.
neously, both accesses are independent and arbitration is
not necessary. This enables a multiprocessing environment. The local memory is accessed through the local spoke of
The exception is the SRAM, which has direct access by the the PHUB (see Table 8-1 on page 92).
CPU and PHUB. In this case, there is no arbitration required
for SRAM. This helps to reduce the SRAM latency access. 8.2.2 How the DMAC Works
The arbitration issues when the CPU and DMA want to The DMAC is one of the bus masters for PHUB. The DMAC
access the same spoke simultaneously are detailed in fur- can perform the following data transfers:
ther sections.
■ Memory to memory

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PHUB and DMAC

■ Memory to peripheral The source engine selects the spoke to which the source
■ Peripheral to memory peripheral is connected. Once the spoke is available for
data transfer, the data transfer from the source begins.
■ Peripheral to peripheral
■ Destination engine phase
Any DMA channel goes through the following phases to per- This phase selects the spoke on which the destination
form data transfers: peripheral is available. Once the spoke is available, the
■ Arbitration phase data collected in the source engine phase is transferred
to the destination peripheral.
■ Fetch phase
■ Write back phase
■ Source engine phase
This phase is the completion phase were the TD and
■ Destination engine phase DMA channel configurations are updated after data
■ Write back phase transfer.
The total time required for a DMA transfer depends on the Ideal conditions for data transfer are:
time taken for each phase. The DMA transfer can be either ■ Single requestor
an intraspoke DMA transfer or interspoke DMA transfer
■ CPU doesn't interrupt the fetch phase
In an intraspoke transfer, the data transfer happens within ■ Both source and destination spoke are readily available
the same spoke. This transfer makes use of the internal
■ Source spoke and destination spoke are of same width
FIFO.
■ Source and destination address start at even addressing
■ Arbitration phase
■ Transfer count is a multiple of burst count
The DMAC selects which DMA channel to process
based on the priority. ■ Burst count matches the spoke width
■ Fetch phase The number of bursts for transfer (N) =
The DMAC fetches the TD and DMA channel details Transfer count  Spoke width
from the configuration registers.
■ Source engine phase 8.2.2.1 Interspoke Transfers
The timing diagram for an interspoke transfer under ideal
conditions is shown in Figure 8-2.

Figure 8-2. Interspoke Transfer Cycle Timing

Bus Clock

Arbitration Phase

Fetch Phase
Command Data Control Data Control Burst = 1 Burst = 2 Burst = N
Source Engine
Phase

Burst = 1 Burst = 2 Burst = N

Destination Engine
Phase

Write Back
Phase

The total number of cycles for data transfer in the case of interspoke DMA transfers is the sum of cycles required for each
phase.

Total cycle time = Arbitration phase time (1) + Fetch phase (1) + Source Engine phase (N + 3) + Destination engine phase (0,
because it happens in parallel with the source engine phase) + Write back phase (1)

Total cycle time = N + 6 cycles (where N = Transfer count  Spoke width)

Example

94 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 PHUB and DMAC

You want to move five samples of 16-bit ADC data to memory.

Notes
■ The ADC (decimator) is connected to spoke 3 which is a 16-bit spoke.
■ Memory is in Spoke 0, which is a 32-bit spoke)

The DMA configuration includes:

■ DMA channel burst count (configured in CFGMEMn.CFG0) = 2
■ TD transfer count (configured in TDMEMn.ORIG_TD0) = 2 bytes × 5 samples = 10
■ TD configuration includes an Increment Destination Address to copy data to an array in the memory (configured in
TDMEMn.ORIG_TD0)
■ N = Transfer count Spoke width = 10 2 = 5

For more information about the DMA configuration, refer to the PHUB registers in PSoC 3 Registers TRM and PSoC 5 Regis-
ters TRM.

The source engine phase needs N + 3 cycles = 8 cycles.

Total cycle time required for interspoke transfer is N + 6 = 5 + 6 = 11 cycles.

8.2.2.2 Intraspoke Transfer

The timing diagram for intraspoke transfer under ideal conditions is shown in Figure 8-3.

Figure 8-3. Intraspoke Transfer Cycle Timing

Bus Clock

Arbitration Phase

Fetch Phase
Command Burst = 1 Burst = 2 Burst = N
Source Engine
Phase

Command Burst = 1 Burst = 2 Burst = N

Destination Engine
Phase

Write Back
Phase

The total number of cycles for data transfer in the case of intraspoke DMA transfer is the sum of the cycles required for each
phase.

Total cycle time = Arbitration phase time (1) + Fetch phase (1) + Source engine phase (N + 1) + Destination engine
phase (N + 1) + Write back phase (1)

Total cycle time = 2N + 5 cycles (where N = Transfer count Spoke width)

In intraspoke DMA transfers, because the source and destination reside in the same spoke, the 16-byte internal FIFO of the
PHUB is used as an intermediate buffer. Once the FIFO is full, the PHUB waits for the FIFO to be emptied and the destination
engine to read the data, and then fills the next set of data. This is the reason why the destination engine phase cannot happen
in parallel with the source engine phase.

Example

You want to move four 32-bit data words from one SRAM location to another SRAM location.

Notes
■ SRAM lies in spoke 0, which is a 32-bit spoke.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 95

PHUB and DMAC

■ In this case, both source and destination is SRAM.

The DMA configuration includes:

■ Burst count (configured in CFGMEMn.CFG0)  4
■ Transfer count (configured in TDMEMn.ORIG_TD0)  4 bytes × 4 words = 16
■ TD configuration includes increment source address and increment destination address to copy data from one array to
another (configured in TDMEMn.ORIG_TD0)
■ N = Transfer count Spoke width = 16 4 = 4

The source and destination engine phase needs

2N + 2 cycles = (2 × 4) + 2 cycles = 10 cycles

Total cycle time required for intraspoke transfer is 2N + 5 = (2 × 4 + 5) = 13 cycles

8.2.2.3 Handling Multiple DMA Channels

The DMAC can perform phases in parallel. This helps to reduce the latency for executing data transfer. When multiple chan-
nels need to execute, the channels can be pipelined.

Figure 8-4 shows processing of two DMA channels that were requested at the same time. The figure shows only the inter-
spoke transfer. The same is applicable also for intraspoke transfer.

Figure 8-4. Multiple DMA Channel Processing

Bus Clock

Arbitration phase for

Channel 1

Fetch phase for

Channel 1

Arbitration phase for

Channel 2
Command Data Control Data Control Burst = 1 Burst = 2 Burst = N
Source Engine
Phase for Channel 1
Burst = 1 Burst = 2 Burst = N
Destination Engine
Phase for Channel 1

Fetch phase for

Channel 2

Write back
Phase for Channel 1
Command Data Control Data Control Burst = 1 Burst = 2 Burst = N
Source Engine
Phase for Channel 2
Burst = 1 Burst = 2 Burst = N
Destination Engine
Phase for Channel 2

Write Back phase for

Channel 2

8.2.2.4 DMA Channel Priority DMA Channel of priority 0 and priority 1 occupy the bus
100%. Rest of the priorities share the bus based on the
Each channel can take a priority from 0 to 7 with 0 being the
number of channels requested at that time. Since priority
highest priority.
0 has higher priority than 1, priority 0 can interrupt prior-
The DMAC supports two different methods to handle the pri- ity 1.
ority: simple priority, and grant allocation fairness algorithm.
In both the cases, a DMA channel of low priority can be
The priority handling method can be changed by writing to interrupted by a high priority channel only during the source
register PHUB.CFG bit “simple_pri” (bit 23). engine phase
■ Simple Priority: This method handles the channels like The Arbitration phase time depends on the number of chan-
any normal priority algorithm where high priority channel nels requesting the DMAC (non-ideal conditions).
can interrupt low priority channel
When there is only 1 channel requesting an idle DMAC, the
■ Grant allocation Fairness algorithm: In this method, the
arbitration phase takes 1 cycle.
channel 0 and 1 take highest priority and no other prior-
ity can interrupt the channels with priority 0 and 1. A

96 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 PHUB and DMAC

When there is more than 1 channel requesting a free DMAC, the arbitration phase takes 2 cycles.

Examples using the Grant allocation Fairness Algorithm

Scenario 1

DMAC is free. Channel A with Priority 0 comes

Figure 8-5. Priority 0 and Idle DMAC

Bus Clock

Channel A 100 % Bus Use

Arbitration Fetch Data Transfer Write Back
Priority 0

Scenario 2
DMAC is free. Channel B with Priority 1 is executing. Channel A with Priority 0 comes

Figure 8-6. Priority 0 and Priority 1

Bus Clock

Burst 1 Burst 2 Burst 3 Burst N

Channel B 100 % Bus Use before
Arbitration Fetch Data Transfer Data Transfer Data Transfer Data Transfer Write Back Interruption and after high
Priority 1
Priority Channel Completion

Request for Channel A Channel B resumes Channel B completed

(Priority 0) arrives
Burst 1 Burst M
Channel A completed
Channel A Data
Priority 0 Arbitration Fetch Data Transfer Write Back 100 % usage of bus
Transfer

Scenario 3

DMAC is free. Channel B with Priority 2 is executing. Channel A with Priority 0/1 comes

Figure 8-7. Priority 0/1 and Other Low Priority

Bus Clock

Burst 1 Burst 2 Burst 3 Burst N

Channel B 100 % Bus Use before
Arbitration Fetch Data Transfer Data Transfer Data Transfer Data Transfer Write Back Interruption and after High
Priority 2
Priority Channel Completion

Request for Channel A Channel B resumes Channel B completed

(Priority 0/ 1) arrives
Burst 1 Burst M
Channel A completed
Channel A Data
Priority 0/ 1 Arbitration Fetch Data Transfer Write Back 100 % Bus Use
Transfer

Scenario 4

DMAC is free. Channel B with Priority 3 is executing. Channel A with Priority 2 comes

Figure 8-8. Lower Priority Channels with Grant Allocation

Bus Clock

Burst 1 Burst 2 Burst 3 Burst 4

Channel B
Priority 3 Arbitration Fetch Data Transfer Data Transfer Data Transfer Data Transfer

Channel A and B The sharing of bus goes on

share the bus until either of the channels
Request for Channel A
completes the data transfer
(Priority 2) Arrives
Burst 1 Burst 2 Burst 3 Burst 4 Burst 5
Channel A Data Channel A gets more share of
Priority 2 Arbitration Fetch Data Transfer Data Transfer Data Transfer Data Transfer
Transfer the bus because of it’s priority

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 97

PHUB and DMAC

The below table shows the minimum guarantee for a DMA Since there are as many 24 DMA Channels but only 8 prior-
channel priority to get bus access ity levels, there can be multiple channels taking the same
priority levels.
Table 8-2. Priority Levels and Bus Allocation
DMAC uses the Round Robin method to handle DMA Chan-
Priority Level Bus Allocation Percentage
0 100
nels with same priority. In case of Round Robin algorithm,
1 100 the DMA channel which was not executed recently takes a
2 50 higher priority. The execution of same priority DMA channels
3 25 when round robin algorithm is enabled depends on
4 12.5 ■ The last time when the channel was enabled
5 6.3
■ If the last time is the same for 2 channels, then DMA
6 3.1
7 1.5 Channel with lower number takes higher priority

Figure 8-9. Round Robin Scheduling

All Channels have the

same priority X
Ch 5

Ch 1 Ch 2 Ch 3 Ch 4

Last executed
time (t)

Ch 4 Ch 5 Ch 3 Ch 2 Ch 1

Order of
execution

8.2.2.5 DMA Latency in case of Nonideal spoke. When CPU interrupts the fetch phase, the latency
Conditions depends on when the CPU releases the configuration regis-
ters. Typically CPU takes 2 cycles for the access of configu-
The previous section explained the latency in case of ideal ration registers.
condition. But in real time, the ideal condition rarely exists.
This section explains the latency calculation in case of non- Also, there might be some high priority DMA channel in the
ideal conditions. The latency calculation in case of nonideal Fetch phase. These scenarios will also add to the DMA
conditions cannot be explained using formula as against the Channel execution latency.
ideal condition. Source and Destination Spokes in Use
Multiple Requestors The source and destination for a particular DMA Channel
In real time system the PHUB will be requested by multiple should be free for the channel to use it. In real time, a
channels and by CPU also. source or destination spoke may be already used by CPU or
another DMA channel
If there are multiple DMA channels sending request at the
same time, the arbitration phase will take 2 cycles instead of When source and destination spoke is already in use, the
the ideal 1 cycle PHUB does the arbitration. The following flow chart shows
the arbitration mechanism.
CPU Interrupts with Fetch Phase

The fetch phase ideally takes only 1 cycle for the PHUB to
access the configuration registers through the PHUB local

98 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 PHUB and DMAC

Figure 8-10. DMA Channel Arbitration

Assume Channel A is the DMA

Channel trying to access the spoke
Is CPU using
the spoke

Yes
Channel B using spoke

Is it a CPU Does Channel B have high

No No
Priority spoke Priority

Yes Yes
No
Latency depends on CPU
processing time No
Current burst for Current burst for
CPU is completed Channel B is
Has the CPU completed
released the spoke? Latency depends on burst
Is the burst
length of the other DMA
completed for
channel
Channel B
CPU process is Yes
interrupted Channel B is
interrupted
Yes
DMA channel accesses
the spoke
The Channel A accesses
DMA channel the spoke
accesses the Channel A
spoke accesses the
spoke

DMA Channel
completes transfer
Channel A
completes transfer

Spoke released
for the DMA

This latency is not measurable and depends on the real time The spoke widths play a very important role in latency.
situation where same spoke can be accessed by multiple There are chances that the source spoke might be smaller
resources. than the destination spoke and vice versa. In this case the
burst count also plays an important role. Let's see some
Source and destination peripherals are not Ready
examples for this condition
When the source or the destination peripheral is not ready to
Scenario 1 (Inter spoke: 16 bit spoke to 32 bit spoke; Burst
send or receive data, then the DMA channel has to wait till it
of 2)
is ready. In case of source peripheral not ready, the DMA
channel will wait for the source peripheral to become ready ■ Source: 16 bit spoke (ADC)
■ Destination: 32 bit spoke (DFB)
In case of destination peripheral not ready, the DMA channel
will use the 16 byte FIFO of the PHUB. It reads the data ■ Burst count: 2 (for 16 bit ADC data)
from the source and fills it in the FIFO till the destination
peripheral is ready. Thus the internal 16 byte FIFO is used
during intra-spoke transfer and also during the conditions
where the source and destination peripherals are no ready.

Source and destination spoke are of different width

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PHUB and DMAC

Figure 8-11. Data Transfer between 16-bit and 32-bit Spoke

Bus clock

Peripheral A (16
16 bit spoke 32 bit spoke Peripheral B
bit data)
2 Bytes 2 Bytes 2 Bytes

Burst Count = 2

Scenario 2 (Inter spoke: 16 bit spoke to 32 bit spoke; Burst of 4)

■ Source: 16 bit spoke (ADC)
■ Destination: 32 bit spoke (DFB)
■ Burst count: 4 (for 20 bit ADC data)

Figure 8-12. Data Transfer Between 16 bit and 32 bit Spoke

Bus clock

Peripheral A (32
16 bit spoke 32 bit spoke Peripheral B
bit data)
2 Bytes
SourceAddr++
Burst Count = 4
2 Bytes

Source address incremented

by source spoke width to read
the next 2 bytes of data

Scenario 3 (Inter spoke: 32 bit spoke to 16 bit spoke; Burst of 4)

■ Source: 32 bit spoke (Memory)
■ Destination: 16 bit spoke (UDB peripheral)
■ Burst count: 4

Figure 8-13. Data Transfer Between 16 bit and 32 bit Spoke

Bus clock

Peripheral A (32 Peripheral B (32

32 bit spoke 16 bit spoke
bit data) bit data)
2 Bytes
DestAddr++

Burst Count = 4 2 Bytes

Destination address
incremented by destination
spoke width to write the next 2
bytes of data

Scenario 4 (Inter spoke: 16 bit spoke to 16 bit spoke; Burst of 2)

■ Source: 16 bit spoke

100 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 PHUB and DMAC

■ Destination: 16 bit spoke

■ Burst count: 2

Figure 8-14. Data Transfer Between Two 16 bit Spoke

Bus clock

Peripheral A (16 Peripheral B (16

16 bit spoke 16 bit spoke
bit data) bit data)
2 Bytes 2 Bytes

Burst Count = 2

Scenario 5 (Inter spoke: 16 bit spoke to 16 bit spoke; Burst of 4)

■ Source: 16 bit spoke ■ Burst count: 4
■ Destination: 16 bit spoke

Figure 8-15. Data Transfer Between Two 16 bit Spoke

Bus clock

Peripheral A (32 Peripheral B (32

16 bit spoke 16 bit spoke
bit data) bit data)
2 Bytes
SourceAddr++,
DestAddr++

Burst Count = 4 2 Bytes

Source and Destination

address incremented by their
spoke widths to read and write
the next 2 bytes of data

Scenario 6 (Intra spoke: 16 bit spoke; Burst of 1)

■ Source and destination: Same spoke (16 bit)
■ Burst count: 1

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PHUB and DMAC

Figure 8-16. Intra Spoke Data Transfer

Peripheral A (8 bit
data)

16 bit spoke

Peripheral B (8 bit
data)
Bus clock

1 Byte to PHUB FIFO

Burst Count = 1
PHUB FIFO to Destination

Data read and write using

intermediate PHUB FIFO

Scenario 6 (Intra spoke: 16 bit spoke; Burst of 2)

■ Source and destination: Same spoke (16 bit) ■ Burst count: 2

Figure 8-17. Intra Spoke Data Transfer

Peripheral A (16
bit data)

16 bit spoke

Peripheral B (16
bit data)
Bus clock

2 Bytes to PHUB FIFO

Burst Count = 2
PHUB FIFO to Destination

Data read and write using

intermediate PHUB FIFO

102 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 PHUB and DMAC

Source and destination address do not have even addressing

The address of the source and destination play a very important role in deciding the latency. The AHB protocol supports read-
ing from even addresses.

Use this notation for a 32 bit spoke.

Figure 8-18. Addressing in 32 bit Spoke

Address n Byte 0 Byte 1 Byte 2 Byte 3

Address n + 1 Byte 0 Byte 1 Byte 2 Byte 3

Figure 8-19. Addressing in 16 bit Spoke

Address n Byte 0 Byte 1

Address n + 1 Byte 0 Byte 1

Scenario 1: 32 bit spoke, Burst count of 4, Address begins at Byte 1

Figure 8-20. Odd Addressing in 32-Bit Spoke

Bus Clock

Byte 1
Data Read cycles
for Burst = 4
Byte 2 and 3

Byte 0 of
Addr + 1

As seen from the above figure, when the even addressing is not met, the bus cycle increases. In ideal condition where the
address begins at Byte 0, a single cycle is sufficient to read all the 4 bytes.

Scenario 2: 16 bit spoke, Burst count of 2, Address begins at Byte 1

Figure 8-21. Odd Addressing In 16 bit Spoke

Bus Clock

Byte 1
Data Read cycles
for Burst = 2
Byte 0 of
Addr + 1

8.2.2.6 Request per Burst Bit

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 103

PHUB and DMAC

The data to be transferred can be split into multiple burst - 8.3.2 Auto Repeat DMA
each of same size. This feature is useful under the following
situations: A static pattern is repetitively read from system memory and
written to a peripheral. This is done with a single TD that
■ When the user doesn't want to hog the bus with a single
chain to itself.
channel which has huge data to transfer
■ When the user needs to control the transfer times Figure 8-23. Auto Repeat DMA

The “Request per bit” is bit 7 in CFGMEMn.CFG0 register.

This bit is available for individual channel. When this bit is
set, the DMA needs a request to transfer the next burst of DMA Channel A TD A
data. When this bit is set, the DMA channel should go
through the whole process from Arbitration phase till Write
back phase for every burst. Thus the “Request per bit”
parameter will significantly increase the transfer time
8.3.3 Ping Pong DMA
8.2.2.7 Work Sep Bit Double buffering is used to allow one buffer to be filled by
The “work_sep” bit is bit 5 of the CHn.BASIC_CFG register. one client, while another client is consuming the data previ-
This bit is available for individual channel. When this bit is ously received in the other buffer. In its simplest form, this is
cleared, a TD mapped to that particular DMA channel can- done by chaining two TDs together where each TD calls the
not restore its initial configuration after the data transfer. The opposite TD when complete.
TD will retain its last source address, destination address Figure 8-24. Ping Pong DMA
and transfer count details at the end of transfer.

When this bit is set, a TD mapped to that particular DMA

channel restores its initial configuration after the data trans- DMA Channel A TD A
fer. This is very useful when the TD should be repeated.
When the “work_sep” bit is set, DMA uses a separate pro-
TD B
cessing area to store the TD configuration details.

8.3 DMA Transaction Modes 8.3.4 Circular DMA

The DMA channels can be chained to perform complex This is similar to ping pong DMA except that it contains
operation. Similarly TDs can be nested or chained to per- more than two buffers. In this case, there are multiple TDs
form complex operations. Chaining of TDs is done using the where after the last TD is complete it chains back to the first
bit “next_td_ptr” in TDMEMn.ORID_TD0 register. This flexi- TD.
bility of the DMA channel and TD helps to create both sim- Figure 8-25. Circular DMA
ple and complex cases

General use cases might include the following types

DMA Channel A TD A

8.3.1 Simple DMA

TD B
A single TD is used to transfer data between two peripherals
or memory locations.
TD C
Figure 8-22. Simple DMA Transfer

TD D

DMA Channel A TD A

8.3.5 7.3.5 Indexed DMA

An external master requires access to locations on the sys-
tem bus as if those locations were shared memory.

104 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 PHUB and DMAC

Example: If a peripheral was configured as an SPI or I2C (or a series of data phase TDs) can begin (potentially using
slave where an address is received by the external master, scatter gather). After the data phase TDs finish, a status
that address becomes an index or offset into the internal phase TD could be invoked that reads some memory
system bus memory space. This is accomplished with an ini- mapped status information from the peripheral and copies it
tial “address fetch” TD that reads the target address location to a location in system memory specified by the CPU for
from the peripheral and writes that value into a subsequent later inspection. Multiple sets of configuration/data/status
TD in the chain. This causes the TD chain to be modified phase sub-chains can be strung together to create larger
during the process. When the “address fetch” TD completes, chains that transmit multiple packets in this way. A similar
it can move onto the next TD, which has the new address concept exists in the opposite direction for the reception of
information embedded in it. This TD carries out the data the packets.
transfer with the address location requested by the external
master. 8.3.8 Nested DMA
Figure 8-26. Indexed DMA One TD can modify another TD, as the TD configuration
space is memory mapped, just as any other peripheral.
Index
Example: A first TD loads a second TDs configuration and
DMA Channel A TD A TD B then calls the second TD. The second TD moves data as
required by the application. When complete, the second TD
TD C calls the first TD, which again updates the second TDs con-
figuration. This process repeats as often as necessary.
TD D

TD E

8.3.6 Scatter Gather DMA

Multiple noncontiguous sources or destinations are required
to effectively carry out an overall DMA transaction.

Example: A packet can be required to be transmitted off of

the device and the packet elements, including the header,
payload, and trailer exist in various non-continuous loca-
tions in memory. Scatter-gather DMA allows the segments
to concatenate together by using multiple TDs in a chain
that gathers data from multiple locations.

A similar concept applies for the reception of data onto the

device. Certain parts of the received data may need to be
scattered to various locations in memory for software- pro-
cessing convenience. Each TD in the chain specifies the
location for each discrete element in the chain.

8.3.7 Packet Queuing DMA

This is similar to scatter gather DMA, but it specifically con-
notes packet protocols whereby there can be separate con-
figuration, data, and status phases associated with sending
or receiving a packet.

Example: For transmitting a packet, a memory mapped con-

figuration register could be written inside a peripheral speci-
fying the overall length of the ensuing data phase. This
configuration information can be setup by the CPU any-
where in system memory and copied with a simple TD to the
peripheral. After the configuration phase, a data phase TD

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 105

PHUB and DMAC

8.4 Register List

Table 8-3. PHUB and DMA Register List
Register Name Comments Features
Specifies prune_clock delay, number of wait states, allocation fairness
PHUB_CFG PHUB General Configuration register
algorithm, priority, priority spoke, CPU_CLOCK_EN setting
PHUB detects the following errors:
1. Bus Timeout
2. Unpopulated address access
3. Peripheral AHB ERROR response
PHUB_ERR PHUB Error Detection register
If the error was detected as a result of a CPU access then PHUB will
send an AHB ERROR response to the CPU. If the error was detected as
a result of either a CPU or DMA access then PHUB will set the corre-
sponding bit in the following ERR register.
PHUB_ERR_ADDR PHUB Error Address register Contains the address that caused an error to trigger

PHUB_CH[0..23]_BASIC_CFG Channel Basic Configuration register Sets basic channel configurations in gates inside PHUB

PHUB_CH[0..23]_ACTION Channel Action register Sets action for each channel

PHUB_CH[0..23]_BASIC_STATUS Channel Basic Status register Provides status information in gates inside PHUB

PHUB_CFGMEM[0..23]_CFG0 PHUB Channel Configuration register 0 Each channel has some configuration information stored in RAM. This
configuration information is called CHn_CFG0/1.
PHUB_CFGMEM[0..23]_CFG1 PHUB Channel Configuration register 1 CHn_CFG0/1 are stored in CFGMEM at {CH_NUM[5:0], 000}.
PHUB_TDMEM[0..127]_ORIG_TD0 PHUB Original Transaction Descriptor 0 Each channel has a TD chain (as short as one TD in length) that pro-
vides instructions to the DMAC for carrying out a DMA sequence for the
channel. The TD chain is comprised of one or more CHn_ORIG_TD0/1
TDs.
PHUB_TDMEM[0..127]_ORIG_TD1 PHUB Original Transaction Descriptor 1
DMAC accesses the CHn_ORIG_TD0/1 chain from TDMEM and the
address in TDMEM of the current TD in the chain is {TD_PTR[7:0], 000}.

106 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 9. Interrupt Controller

The Interrupt Controller provides the mechanism for hardware resources to change the program address to a new location
independent of the current execution in the main code. The interrupt controller also handles continuation of the interrupted
code being executed after the completion of the interrupt service routine.

9.1 Features
The following are features of the interrupt controller:
■ Supports 32 interrupt lines
■ Programmable interrupt vector
■ Configurable priority levels from 0 to 7
■ Support for dynamic change of priority levels
■ Support for individual enable/ disable of each interrupt
■ Nesting of interrupts
■ Multiple sources for each interrupt line (can be either fixed function, UDB, or from DMA)
■ Supports both level trigger and pulse trigger
■ Tail chaining, late arrivals and exceptions are supported in PSoC® 5 devices

9.2 Block Diagram

Figure 9-1 is a block diagram of the interrupt controller.

Figure 9-1. Interrupt Controller Block Diagram

Interrupt
Signals
0
16-bit Interrupt Vector
1
Address (IAV)
2

Interrupt Request (IRQ)

Interrupt
CPU
Controller
Acknowledgment for
Interrupt Entry (IRA)
Acknowledgment for
31
Interrupt Exit (IRC)

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 107

Interrupt Controller

9.3 How It Works

The interrupt controller supports 32 interrupt signals. The interrupt signal can come from one of the three sources (see
Figure 9-2):
■ Fixed function block
■ DMA channels
■ UDB blocks

The interrupt signal routing is very flexible with PSoC 3 and PSoC 5 architectures. The interrupt lines pass through a multi-
plexer. The mux selects one among the following: Fixed function IRQ (Interrupt request), UDB IRQ with level, UDB IRQ with
Edge, and DMA IRQ. The IDMUX.IRQ_CTL register is used to configure the mux for the IRQ selection.

Figure 9-2. Interrupt and DMA Processing in the IDMUX

Fixed Function IRQs

0

1
Interrupt
Controller
UDB IRQs
2
UDB Array
Edge
3
Detect
UDB DRQs
DMA termout (IRQs)

0
Fixed Function DRQs
DMA
1
Controller

Edge
2
Detect

The interrupt controller unit prioritizes and sends the request Table 9-1. Bit Status During Read and Write
to the CPU for execution. The list of interrupt sources and Bit
Register Operation Comment
the corresponding interrupt number is available in the device Value
datasheet. 1 To enable the interrupt
Write
0 No effect
SETEN
9.3.1 Enabling Interrupts 1 Interrupt is enabled
Read
0 Interrupt is disabled
The interrupt controller provides features to enable and dis-
able individual interrupt lines. The Enable register (SETEN) 1 To disable the interrupt
Write
and the Clear Enable register (CLREN), respectively, enable 0 No effect
CLREN
and disable the interrupt lines. Each bit in the register corre- 1 Interrupt is enabled
Read
sponds to an interrupt line; these registers enable and dis- 0 Interrupt is disabled
able interrupts and read the enable status of interrupts. The
register that is updated latest (SETEN or CLREN register)
determines the interrupt enable status. Table 9-1 shows the
status of bits during read and write.

108 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Interrupt Controller

9.3.2 Pending Interrupts 9.3.3 Interrupt Priority

When the interrupt controller receives the interrupt signal, it The interrupt controller provides a priority handling feature
sets the pending bit. to help a user assign priority for each interrupt. Characteris-
tics of this feature are as follows:
“Set Pending register” (SETPEND) and the “Clear Pending
register” (CLRPEND) also allow the pending bit to be set ■ Eight levels of interrupt priorities from 0 to 7.
and cleared through software. Each bit in the register corre- ■ Priority level 0 is highest and level 7 is lowest.
sponds to an interrupt line. The pending bit status can be ■ Priority levels set using the Interrupt Priority Registers
read by reading these registers. For both pulse/level inter- PRI_[x].
rupts, the pending bit is cleared immediately upon receiving
■ Support of dynamic configuration of priority levels – A
the acknowledgement from the CPU on interrupt entry
change of priority level of an interrupt on the fly does not
(IRA). For pulse interrupts, the pending bit can be set again
affect the current execution of the same interrupt; it
by arrival of a new pulse interrupt on the same line after the
takes effect for the next assertion.
IRA. But for level interrupt, the interrupt controller checks
the status of the interrupt line when it receives the acknowl- Priority handling is very important in the following cases:
edgement from the CPU on interrupt exit (IRC). During that ■ Case 1 – If an interrupt (INT B) is asserted when another
time, if the interrupt line is still asserted, the pending bit is interrupt (INT A) is being executed, there are three pos-
reset. If there is no assertion on the interrupt line, the pend- sibilities with unique handling sequences:
ing bit remains in cleared state.
❐ If INT A has lower priority than INT B:
Table 9-2. Pending Bit Status 1.INT A is stopped at the point of execution.
Bit 2.The details of INT A are pushed to the stack, and
Register Operation Comment
Value INT B begins to execute.
1 To put an interrupt to pending 3.After the execution of INT B, INT A execution is
Write
0 No effect resumed from the point of its interruption.
SETPEND
1 Interrupt is pending ❐ If INT A has higher priority than INT B:
Read
0 Interrupt is not pending 1.INT B has to wait until INT A has been executed.
1 To clear a pending interrupt 2.After the execution of INT A, INT B can start exe-
Write
0 No effect cution.
CLRPEND
1 Interrupt is pending ❐ If INT A and INT B have equal priority:
Read
0 Interrupt is not pending 1.If INT A is being executed; INT B has to wait until
INT A has been executed. After the execution of
The pending register can also be written by software. When INT A, INT B can start execution.
the software writes a 1 to the pending bit, it activates the 2.If INT B is being executed; INT A has to wait until
interrupt. When software clears the pending bit, the interrupt INT B has been executed. After the execution of
does not occur. When the software request to clear a pend- INT B, INT A can start execution.
ing bit and hardware request to set the pending bit occurs ■ Case 2 – During the simultaneous occurrence of inter-
simultaneously, the hardware request takes the higher rupts:
priority.
❐ If INT A has lower priority than INT B, then INT B
Setting of the pending bit when the same bit is already set wins arbitration and begins to execute.
results in only one execution of the interrupt. The pending bit ❐ If INT A has higher priority than INT B, then INT A
can be updated regardless of whether or not the corre- wins arbitration and begins to execute.
sponding enable bit is set. If the enable bit is not set, the ❐ If INT A and INT B have equal priority, then the inter-
interrupt line will be pended until the interrupt is enabled, rupt with the lower index number wins arbitration and
unless the user clears the bit. It is advisable to check the begins to execute.
state of the pending bit before enabling the interrupt. The
choice is left to the user, of whether to set the pending bit
before or after the enable bit is set, for enabling the corre-
sponding interrupt.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 109

Interrupt Controller

9.3.4 Level versus Pulse Interrupt 9.3.5 Interrupt Execution

The interrupt controller supports both Level and Pulse inter- The interrupt controller controls both Level and Pulse inter-
rupts. The interrupt controller includes the Pulse detection rupt in the following sequence:
logic, which detects the rising edge on the interrupt line. The 1. Interrupt execution corresponding to the interrupt signal
pulse detection logic pends the interrupt bit whenever it requires the interrupt to be enabled (assuming priority
detects the rising edge. The interrupt controller detects any and interrupt vector address are programmed already).
assertion in the interrupt signal and executes the interrupt 2. When an assertion occurs in the interrupt signal, the
as follows: pending bit corresponding to the interrupt number is set
■ Level Interrupt – With level interrupts, the interrupt in the pending register, indicating that the interrupt is
request bit in the corresponding peripheral register must waiting for its execution.
be cleared by the firmware inside the interrupt service 3. The Priority Decoding unit reads the priority and deter-
routine. If the interrupt request bit in the peripheral regis- mines when the interrupt can be executed.
ter is set, it results in a level high signal on the interrupt 4. The interrupt controller sends the interrupt request to the
line. At the interrupt exit, if the interrupt request bit is set CPU, along with the interrupt vector address for execu-
in the peripheral register, the interrupt pending bit is set tion.
again and the interrupt is processed again if it is 5. The CPU receives the request.
enabled. 6. Interrupt Entry (IRA) – The CPU acknowledges the
■ Pulse Interrupt – A pulse occurs at the interrupt line. interrupt entry. The next assertion in the same interrupt
The low to high edge of the pulse sets the pending bit line can be detected only after the interrupt entry. Any
and the corresponding interrupt is executed. If the pulse assertions before that are ignored. The interrupt control-
ler clears the pending bit upon receiving the acknowl-
occurs while the pending bit is already set, the second
edgement.
pulse has no effect, because the pending bit is already
set. The Pending bit is automatically cleared by the inter- 7. The current interrupt number and its priority are pushed
to the interrupt controller stack by the interrupt controller.
rupt controller at ISR entry. However, if the pulse comes
while the interrupt is currently active, the interrupt pend- 8. Interrupt Exit (IRC) – When interrupt execution has
ing bit is set again, and the interrupt is executed again. been completed, the processor is free to address the
next request.The CPU acknowledges the interrupt exit.
At the interrupt exit, the interrupt context (i.e., interrupt
number and priority) is popped from the stack.
Figure 9-3 lists the basic operations during an interrupt sig-
nal assertion and its handling.

110 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Interrupt Controller

Figure 9-3. Interrupt Signal Assertion and Handling

Assertion on the
interrupt Line

Set of Pending Bit

Send to Priority
Wait until all Decoding Unit
high priority
interrupts
No
finish

Is this the highest

priority Interrupt?

Yes

Send request to CPU

(with IRQ and IVA)

CPU accepts
request

Pending bit cleared

IRA sent by CPU (INTC pushes Interrupt for Pulse and Level
details to its stack) Interrupt

Interrupt execution

Interrupt line is checked

Interrupt Exit acknowledgment (IRC) in case of Level interrupt.
from CPU (INTC pops interrupt details If interrupt line has a high
from the stack)
level, the pending bit is
sent again.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 111

Interrupt Controller

9.4 PSoC 3 Features ❐ STK_INT_NUM – Stores the interrupt number infor-

mation.
PSoC 3 architecture handles active interrupts, stacks, and
Both of the stacks grow upwards. The push and pop in the
interrupt vector addresses differently from PSoC 5 architec-
interrupt controller stack is handled by the interrupt control-
ture. This section describes the following:
ler itself.
■ Registers for the active interrupt
■ CPU Stack – The CPU stack is used to store other gen-
■ Use of stacks during nesting of interrupts when a high eral registers, such as the PC, GPR, SFR, PSW, ACC,
priority interrupt is asserted during the execution of a low and B, depending on the application. The CPU handles
priority interrupt the automatic push/pop of the PC register (low byte
■ Registers that handle the vector addresses that corre- pushed first). The rest of the required registers must be
spond to every interrupt line pushed/popped using the firmware inside the interrupt
handler routine.
9.4.1 Active Interrupts The sequence of interrupt nesting is as follows:

The active interrupt is the one being executed currently. The 1. When a high priority interrupt assertion occurs during the
execution of the low priority interrupt, the low priority
interrupt priority and interrupt number of the active interrupt
interrupt execution is stopped at that point.
are stored in eight level hardware stacks. The hardware
stack is available with the Interrupt controller. There are two 2. The CPU accepts the request, stops the execution of the
low priority interrupt, and pushes the PC.
different stacks used to store the active interrupt details –
one stores the interrupt priority, and the other stores the 3. The CPU sends the acknowledgment (for the high prior-
interrupt number. Following are the details of the stacks: ity interrupt entry) to the interrupt controller.
4. The interrupt controller pushes the interrupt number and
■ STK – Stores the priority of the interrupt
interrupt priority of the low priority interrupt to its stack. It
■ STK_INT_NUM – Stores the interrupt number pushes the higher priority interrupt context to the top of
the stack.
The top of the above stacks have the details of the current
active interrupt and interrupt priority. The registers 5. The interrupt service routine can push the other regis-
ACT_INT_NUM and ACT_VECT store the details of the lat- ters, such as the PSW, GPR, SFR, ACC, and B, to the
CPU stack. The high priority interrupt execution begins.
est interrupt number execution requested to the CPU and its
corresponding vector address. The value in these registers 6. When the higher priority interrupt has been executed,
is valid only between the “Interrupt request to the CPU the CPU sends the IRC. The details of the high priority
interrupt are popped from the interrupt controller stack
(IRQ)” and “Interrupt Entry (IRA).” Any read outside this time
leaving the low priority interrupt at the top of the stack.
frame may result in invalid values.
The details of the low priority interrupt are popped from
the CPU stack. The low priority interrupt continues its
9.4.2 Interrupt Nesting execution from the point of suspension.
PSoC 3 devices support nesting of up to eight interrupts. 7. Because the push and pop of the stack are handled by
Nesting of an interrupt occurs when a high priority interrupt the hardware, there is minimum latency, because no
instruction is involved in the operation.
is asserted during a low priority interrupt execution. In
PSoC 3, the nesting of interrupts uses both the interrupt Figure 9-4 on page 113 shows the states of the stack during
controller stack and the CPU stack. the nesting operation.
■ Interrupt Controller Stack – The interrupt controller
stack is available with the interrupt controller and is used
to store the interrupt number and interrupt priority. There
are two stacks with a depth of eight levels. Following are
the stack details:
❐ STK – Stores the interrupt priority information.

112 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Interrupt Controller

Figure 9-4. Register States During Nesting

Assertion of INT A

Assertion of INT B

Execution of Continuation
INT A Execution of INT B
of INT A

Stacking of INT A Un-stacking of INT A

Register State Register State Register State After Register State After Register State After
Before During Stacking of INT A Execution of INT B All executions
All Executions Execution of INT A
STK_INT STACK_INT_NUM STK_INT STACK_INT_NUM STK_INT STACK_INT_NUM STK_INT STACK_INT_NUM STK_INT STACK_INT_NUM

0 XX XX 0 0 INT A INT A 0 0 INT B INT B 0 0 INT A INT B 0 0 XX XX 0

1 XX XX 1 1 XX XX 1 1 INT A INT A 1 1 XX XX 1 1 XX XX 1
2 XX XX 2 2 XX XX 2 2 XX XX 2 2 XX XX 2 2 XX XX 2
3 XX XX 3 3 XX XX 3 3 XX XX 3 3 XX XX 3 3 XX XX 3
4 XX XX 4 4 XX XX 4 4 XX XX 4 4 XX XX 4 4 XX XX 4
5 XX XX 5 5 XX XX 5 5 XX XX 5 5 XX XX 5 5 XX XX 5
6 XX XX 6 6 XX XX 6 6 XX XX 6 6 XX XX 6 6 XX XX 6
7 XX XX 7 7 XX XX 7 7 XX XX 7 7 XX XX 7 7 XX XX 7

In Figure 9-4, INT A is suspended, and the high priority 2. During the interrupt assertion, the address of the service
interrupt INT B is executed. During nesting, INT A is pushed routine is retrieved from these registers and given to the
to registers. After INT B is executed, the registers are CPU for execution of the interrupt.
popped. When an interrupt begins to execute the interrupt,
information is pushed to stack; when it finishes, the stack is 9.4.4 Sleep Mode Behavior
popped.
The Interrupt Controller works in all of the power modes
(Active, Stand by, Sleep and Hibernate) unless the user
9.4.3 Interrupt Vector Addresses switches the clocks off manually. All of the registers (status
PSoC 3 devices have a feature that allows a user to specify and configuration) except the pending register and interrupt
the interrupt service routine starting address for every inter- controller stack, retain their values during Sleep mode. The
rupt line. The address of the interrupt service routine is pro- Pending and Interrupt Controller Stack registers are set with
grammable. The call of the interrupt service routine the power on value at wakeup. Because the pending regis-
corresponding to an interrupt line is not a branch instruction. ters are nonretention registers, the requests that are pended
The address of the interrupt service routine is stored in the will be missed when the device goes to sleep.
vector address register, resulting in the direct call of the rou- Do not change the power mode change inside the Interrupt
tine, preventing latency. Service routine. If a change in mode is requested, the
1. The interrupt service routine address is programmable device will finish the ISR, exit the ISR, and then switch the
and is stored in Vector Address registers called power mode.
VECT[0…31].
The clock for the Interrupt Controller can be enabled and
There are 32 vector address registers corresponding to
disabled by setting the register bit “CLOCK_EN” in the
the 32 interrupt lines.
INTC_CLOCK_EN register. When the clock is switched off
Each Vector Address register is 16 bits.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 113

Interrupt Controller

for the Interrupt Controller, the CPU should not access the 9.5.2 Interrupt Nesting
ISR (as the IRA and IRC cannot be processed by the Inter-
rupt Controller). Nesting of an interrupt occurs when a high priority interrupt
is asserted during a low priority interrupt execution. With
PSoC 5 architecture, only the CPU stack is available to
9.5 PSoC 5 Features store all nesting interrupt details.
■ Current interrupt number, current interrupt priority
Because PSoC 5 architecture is based on the Cortex-M3
core, it has additional features supported by the Cortex-M3 ■ Program counter, PSR, R0 to R3, R12 and LR
core. In PSoC 5 devices, the interrupt controller is a part of ■ Depending on the application, other registers from R4 to
the Cortex-M3 core. For more detailed information about the R11
PSoC 5 Interrupt Controller, refer to the ARM Cortex-M3
Technical Reference Manual available at http:// The CPU stack grows down while the CPU handles push
www.arm.com. and pop.

The configuration controls how you use PSP and MSP. If

9.5.1 Active Interrupts both stacks are used, the Process Stack Pointer or Main
Stack Pointer, which ever is currently active, is used by the
An active interrupt is the one being executed currently. The
first interrupt. All other nested interrupts use only the MSP. If
interrupt priority and interrupt number of the active interrupt
only one stack is configured for use, the interrupt details are
are stored in the CPU stack. Whenever an interrupt begins
stored in the MSP. The sequence is:
to execute, the interrupt priority and number are pushed to
the stack. The contents of the stack can be read to find the 1. When the high priority interrupt comes during the execu-
Active Interrupt details. With PSoC 5 devices, the CPU tion of the low priority interrupt, the interrupt controller
sends a request to the CPU and low priority interrupt
stack is used. There are two stacks accessed using two dif-
execution is stopped by the CPU at that point.
ferent stack pointers: The Process Stack Pointer (PSP) and
the Main Stack Pointer (MSP). 2. The details, such as instruction pointer and other gen-
eral purpose registers for the low priority interrupt, are
Cortex-M3 can be configured to use two stacks. When it is pushed to the stack. (The stack used depends on nest-
configured to use both the stacks, the first interrupt uses the ing. It can be either MSP or PSP as explained previ-
PSP or the MSP to store interrupt details, depending on ously).
which is currently active. The stack grows downwards. A 3. The number of nesting supported depends on the avail-
nested interrupt uses only MSP to store the details. When it ability of stack space. Because system stack is used, the
is not configured to use two stacks, only the MSP is used. user should ensure that sufficient stack space is avail-
able. Insufficient stack space causes undetermined
PSoC 5 devices also support an ACTIVE register to store results. After the stack push for the low priority is done,
the active status of the interrupt. Its characteristics are: the details of the current active interrupt (high priority
■ Each bit in the register indicates the active state of the interrupt) is stored in the CPU stack. The high priority
corresponding interrupt. interrupt executes.
4. After the higher priority interrupt has executed, the inter-
■ When the bit is set to 1 in the ACTIVE register, the inter-
rupt details of the high priority interrupt are popped from
rupt is active. When the bit is set to 0, the interrupt is cur-
the stack. Following this, the details of the low priority
rently inactive. interrupt (PC and other register details) are popped from
■ When the current running interrupt is suspended due to the stack. The low priority interrupt continues its execu-
a high priority interrupt, the state of the current running tion from the point of suspension.
interrupt is maintained as “Active” because it continues 5. Because the push and pop of stack is handled by the
its execution after execution of the high priority interrupt. hardware, there is minimum latency; no instruction is
■ The active state of the bit is cleared only after execution involved in the operation.
of the interrupt. Figure 9-5 on page 115 shows a timing diagram of the regis-
ter states during the nesting operation.
PSoC 5 devices also supports exceptions other than inter-
rupts. The ACTIVE bits correspond only to interrupts and
not to exceptions. The active status details of exceptions are
stored in the Exception Status register. Exception Status
registers are not only used to read the active status but also
to enable exceptions.

114 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Interrupt Controller

Figure 9-5. Register Timing During Nesting

Assertion of INT A

Assertion of INT B

Assertion of INT C

Execution of Execution of Execution of Continuation Continuation

INT A INT B INT C of INT B of INT A

Stacking of Un-stacking Un-stacking

Stacking of
INT A of of
INT B
INT B INT A

Register state after Register state after

Register state before all Register state during
Stacking of INT A and Stacking of INT B and
executions execution of INT A
execution of INT B execution of INT C
PSP MSP PSP MSP PSP MSP PSP MSP
XX XX XX
INT A Details INT B details INT A Details
INT A Details INT C details

Other register INT B details

details of and other
INT A registers

Other register
details of
INT A

Register state after Register state after Register state after

un-Stacking of INT B and un-Stacking of INT A and all executions
execution of INT B execution of INT A
PSP MSP
PSP MSP PSP MSP
XX XX
INT A Details INT B details INT A Details XX

Other register
details of
INT A

In Figure 9-5, INT A is suspended, and the high priority interrupt INT B is executed. During nesting, the INT A is pushed to the
stack. During execution of INT B, INT C occurs. So INT B is pushed, and INT C is executed. After INT C is executed, INT B is
popped and executed. After INT B is executed, the stack is popped. When an interrupt begins to execute, interrupt informa-
tion is stored in the stack; when it completes, the stack is popped. The use of both PSP and MSP is shown. It is assumed that
PSP is active during the first interrupt and that the first active interrupt uses the PSP.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 115

Interrupt Controller

9.5.3 Interrupt Vector Addresses 9.5.4 Tail Chaining

PSoC 5 architecture has a feature that allows a user to Tail chaining is the process used to reduce interrupt latency.
specify the interrupt service routine for every interrupt line. When a new interrupt assertion occurs at the same time as
The call of the interrupt service routine corresponding to an another interrupt being executed with the same or higher
interrupt line is not a branch instruction. The address of the priority, the following sequence occurs:
interrupt service routine is stored in the vector table, which 1. The new interrupt with a lower priority is pended.
results in the direct call of the routine. This method of execu-
2. After the current interrupt has been executed, the details
tion prevents latency in the call of the interrupt service rou- of the current interrupt in the stack are not popped.
tine.
3. The details of the new interrupt are pushed to the stack
When interrupt assertion occurs, the following sequence and the new interrupt begins its execution.
occurs: 4. After the execution of the new interrupt, details of the
1. The address of the interrupt service routine is taken from new interrupt and the previous interrupt are popped from
the interrupt vector table and is executed. the stack.
2. The list of interrupt vector addresses is stored in the vec- Because stacking and unstacking are avoided between the
tor table. two, interrupts, latency is greatly reduced. Tail chaining can
The interrupt service routine address is programmable save a maximum of six cycles.
and is stored in the vector table. The vector table is a
location in the memory and has a base address; the 9.5.5 Late Arrival Interrupts
other vector addresses are accessed as offset from the
base address. By default, the vector table is at location A late arrival interrupt occurs when another interrupt is being
0x00 in the ROM. pushed to the stack for execution. Another feature reduces
The base address of the vector table can be changed; interrupt latency by handling such late arrival interrupts.
the vector table can be moved, either in the ROM itself
The following sequence describes the process:
or to the RAM. Each vector address is 32 bits long; when
moving the vector table, the user should ensure that 1. A low priority interrupt is asserted.
there is enough space to hold the supported 4-byte 2. The details of the low priority interrupt are being pushed
addresses for the 32 interrupt lines to the stack, when a high priority interrupt assertion hap-
3. PSoC 5 devices contain the Vector Table Offset register pens.
that contains two data: 3. After the stacking of the low priority interrupt, the high
Position of vector table in ROM/RAM. priority interrupt is stacked and executed, instead of the
low priority interrupt.
Offset value from the start ROM or RAM region. This off-
set value acts as the base address for the vector table. 4. After execution of the high priority interrupt, the low prior-
ity interrupt is executed.
4. When the vector table is moved, the boot image should
contain the stack pointer value, Reset vector, NMI vec-
tor, and hard Fault vector, because these are required
for the beginning of execution of code.
5. Because the vector address is 32 bits long, the LSB is
filled with 0x01, and the MSB contains the correspond-
ing 24-bit ISR address to be executed. The presence of
0x01 in the LSB indicates Thumb instructions.
6. During the interrupt signal assertion, the address of the
interrupt service routine (the Interrupt Vector Address
(IVA)) is retrieved from this table and given to the CPU
for execution of the interrupt.
7. Because PSoC 5 devices also support exceptions, the
vector table has the address corresponding to the 15
exceptions followed by the interrupt service routine
addresses.

116 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Interrupt Controller

9.5.6 Exceptions
PSoC 5 architecture supports 15 different exceptions, as shown in Table 9-3.

These exceptions are used to handle fault conditions that can occur in the system. Exceptions can have fixed priority or con-
figurable priority. Exceptions are handled in the same manner as interrupts. The State register is used to enable or disable
exceptions.

Table 9-3. PSoC 5 Exceptions

Interrupt
Exception Type Priority Comments
Number
1 Reset -3 (highest) not programmable Reset
2 NMI -2 not programmable Non-Maskable Interrupt
3 Hard Fault -1 not programmable All fault conditions if the corresponding handler is not enabled
4 MemManage Fault Programmable Memory management fault; MPU violation or access to illegal locations
Bus error; occurs when AHB interface receives an error response from a bus
5 Bus Fault Programmable slave (also called prefetch abort if it is an instruction fetch or data abort if it is
a data access)
6 Usage Fault Programmable Exceptions due to program error
7 Reserved NA --
8 Reserved NA --
9 Reserved NA --
10 Reserved NA --
11 SVCall Programmable System Service Call
12 Debug Monitor Programmable Debug monitor (watchpoints, breakpoints, external debug request)
13 Reserved NA --
14 PendSV Programmable Pendable request for system device
15 SYSTICK Programmable System Tick Timer

9.5.7 Interrupt Masking

PSoC 5 architecture supports special methods to mask PSoC 5 devices have special registers to provide masking
interrupts and exceptions, preventing them from execution. facilities, including:
Any new assertions in the interrupt lines are detected and ■ PRIMASK – When the bit in the PRIMASK register is
pended until the interrupts are unmasked. set, all interrupts and exceptions except NMI and Hard
Masking of interrupts is different from enabling or disabling. fault are blocked.
When masked, the interrupt is blocked for some time, even ■ FAULTMASK – When the bit in the FAULTMASK regis-
though it is enabled. This feature is useful when it is neces- ter is set, all interrupts and exceptions except NMI are
sary to protect some critical section of code. When inter- blocked.
rupts are masked, pending interrupts are not executed, even ■ BASEPRI – When interrupts below a certain priority
though the interrupts are enabled in the enable register. The level must be masked, the priority number can be speci-
interrupts are executed only when masking is cleared. fied in the BASEPRI register. All interrupts with a priority
number equal to or less than the priority level specified
in the BASEPRI register are masked.

9.6 Interrupt Controller and

Power Modes
The CPU core (8051/Cortex-M3) could be executing even
when the power or clock for the Interrupt Controller is
switched off. In this case, care should be taken during entry/

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 117

Interrupt Controller

exit into different low power modes (alternate active, sleep

and hibernate).

Do not do these steps before switching off the Interrupt Con-

troller clock.
1. Clear all pending interrupts and disable all interrupts in
Interrupt Controller.
2. NOP.
3. Disable the Global Interrupt bit.
4. Turn OFF the clock for Interrupt Controller in the
CLOCK_EN bit in the INTC.CLOCK_EN register.
It is preferred not to operate any Interrupt related functions
when the clock to the interrupt controller is not available.
When an Interrupt Service routine is executed by the CPU
when the clock to the interrupt controller is switched off, the
CPU should make sure the clock for the Interrupt Controller
is re-enabled before the exit from the ISR (to process the
IRC signal). If this is not taken care, it will lead to undefined
behavior.

When returning from the lower power mode or wants to con-

tinue in the alternate active mode, follow these steps:
1. Clock must be available to Interrupt Controller
2. Enable the Global interrupt bit
3. Enable the required interrupts in the Interrupt Controller
The CPU can run when the interrupt controller clock is
switched off only during active and alternate active modes.
When the user wants to switch from alternate active to
Active mode when the Interrupt controller clock is switched
off.
a. Follow the steps mentioned above to switch off the
clock for the Interrupt controller
b. Now the CPU can run any code that doesn't involve
the Interrupt functionality.
c. Switch to the active state whenever required
d. To switch to active mode only on wake up on inter-
rupt, then the CPU should keep polling the
PM.MODE_CSR register to find when the system
should switch to active mode.
e. When switching back to active mode, follow the pro-
cedures mentioned above for switching from low
power mode to active mode.

118 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Section C: Memory

The PSoC® nonvolatile subsystem consists of Flash, byte-writable EEPROM, and nonvolatile configuration options. The CPU
can reprogram individual blocks of Flash, enabling boot loaders. An Error Correcting Code (ECC) can enable high reliability
applications.

A powerful and flexible protection model allows the user to selectively lock blocks of memory for read and write protection,
securing sensitive information. The byte-writable EEPROM is available on-chip for the storage of application data. Addition-
ally, selected configuration options, such as boot speed and pin drive mode, are stored in nonvolatile memory, allowing set-
tings to become active immediately after power on reset (POR).

This section encompasses the following chapters:

■ Nonvolatile Latch chapter on page 121
■ SRAM chapter on page 125
■ Flash Program Memory chapter on page 129
■ EEPROM chapter on page 131
■ EMIF chapter on page 133
■ Memory Map chapter on page 141
■ Cache chapter on page 147

Top Level Architecture

(Block diagram here taken from main block diagram in Introduction.)

Memory Block Diagram

System Bus

MEMORY SYSTEM

EEPROM SRAM
CPU
SYSTEM
EMIF FLASH

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 119

 Section C: Memory

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 120

 10. Nonvolatile Latch

A Nonvolatile Latch (NVL or NV latch) is an array of programmable, nonvolatile memory elements whose outputs are stable at
low voltage. It is used to configure the device at Power on Reset. Each bit in the array consists of a volatile latch paired with a
nonvolatile cell. On POR release nonvolatile cell outputs are loaded to volatile latches and the volatile latch drives the output
of the NVL.

10.1 Features
NV latches include:
■ A 4x8-bit NV latch for device configuration
■ A 4x8-bit Write Once NV latch for device security

10.2 Device Configuration NV Latch

Device configuration NV latches allow configuration of PSoC® device parts before the CPU reset is released. For example,
the user may configure each I/O port to be in one of four drive modes before CPU reset is released. Device configuration NV
latch values have lower endurance and must be written in a narrower temperature window. Programming temperature range
and endurance have been traded off to meet the low voltage and wide temperature requirements. For endurance, retention,
and temperature specs for NV latches see the specific device datasheet. The Device Configuration NV Latch register map is
shown in Table 10-1.

Table 10-1. Device Configuration Register Map

Register Address 7 6 5 4 3 2 1 0
0x00 PRT3RDM[1:0] PRT2RDM[1:0] PRT1RDM[1:0] PRT0RDM[1:0]
0x01 PRT12RDM[1:0] PRT6RDM[1:0] PRT5RDM[1:0] PRT4RDM[1:0]
0x02 XRESMEN PRT15RDM[1:0]
0x03 DIG_PHS_DLY[3:0] ECCEN DPS[1:0] CFGSPEED

10.2.1 PRTxRDM[1:0]
Port Reset Drive mode NVL bits enable selection of one of four drive modes to be in effect between the release of POR and
the configuration of the device by user firmware. These four drive modes are a subset of the drive modes available by writing
to the port drive mode registers. Refer to the I/O System chapter on page 187 for more details. The following is a summary of
the four NVL drive mode settings:
■ 00b – High impedance analog
■ 01b – High impedance digital
■ 10b – Resistive pull up
■ 11b – Resistive pull down

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 121

Nonvolatile Latch

10.2.2 XRESMEN ■ …
■ 0X0A – 11.5 ns delay
GPIO pin (P1[2]) may be configured as an external reset
(XRES_N) pin. The configuration of that pin is controlled ■ 0x0B – 12.5 ns delay
with this NVL bit: ■ 0x0C – Clock disabled
■ 0 – GPIO ■ 0X0D – Clock disabled
■ 1 – XRES_N ■ 0X0E – Clock disabled
■ 0X0F – Clock disabled
10.2.3 CFGSPEED
The Configuration Speed NVL bit determines if the IMO 10.3 Write Once NV Latch
defaults to a fast or slow speed. Refer to the Clocking
System chapter on page 147 for more details. This configu- The Write Once (WO) latch is a type of nonvolatile latch.
ration is intended to balance the need for rapid boot and The cell itself is an NVL with additional logic wrapped
configuration against peak power consumption. around it. Each WO latch device contains 4 bytes (32 bits) of
■ 0 – Slow (12 MHz IMO frequency) data. The wrapper outputs a 1 if a super-majority (28 of 32)
of its bits match a pre-determined pattern (0x50536F43) and
■ 1 – Fast (48 MHz IMO frequency)
it outputs a 0 if this majority is not reached. When the output
is 1, the Write Once NV latch locks the part out of Debug
10.2.4 DPS[1:0] and Test modes; it also permanently gates off the ability to
Debug Port Select NVL bits allow the user to select a erase or alter the contents of the latch. Matching of all bits is
debugging port interface that is active after POR is released. intentionally not required, so that single (or few) bit failures
If the debug port’s disabled setting is used, the acquire func- do not deassert the WO latch output. The state of the NV
tions of the test controller must be used to activate the latch bits after wafer processing is truly random with no ten-
debug port. Refer to the Test Controller chapter on dency toward 1 or 0.
page 443 for more details. These NVL bits do not enable the The WOL only locks the part once the correct 32-bit key
debugger logic; they enable only the physical interface. The (0x50536F43) is loaded into the NVL's volatile memory, pro-
only way to enable the debug logic is for the user's firmware grammed into the NVL's nonvolatile cells, and the part is
or configuration to write the debugger enable bit. reset. The output of the WOL is only sampled on reset and
■ 00b – 5-wire JTAG used to disable the access.
■ 01b – 4-wire JTAG This precaution prevents anyone from reading, erasing, or
■ 10b – SWD (single wire debug) altering the content of the internal memory.
■ 11b – Debug ports disabled
If the device is protected with a WO
latch setting, Cypress cannot perform
10.2.5 ECCEN
failure analysis and, therefore, cannot
For devices that support an Error Correcting Code (ECC) in accept RMAs from customers. The WO
the Flash, this NVL bit is used to set whether ECC is latch can be read via the SWD to electri-
enabled. Refer to the Flash Program Memory chapter on cally identify protected parts.
page 129 for more details.
■ 0 – ECC disabled The user can write the key in WOL to lock out external
■ 1 – ECC enabled access only if no Flash protection is set. However, after set-
ting the values in the WOL, a user still has access to the part
until it is reset. Therefore a user could write the key into the
10.2.6 DIG_PHS_DLY[3:0] WOL, program the Flash protection data, and then reset the
This bit selects the digital clock phase delay in 1 ns incre- part to lock it. Refer to the Flash, Configuration
ments. Refer to the Clocking System chapter on page 147 Protection chapter on page 205 for details on Flash protec-
for more details, tion.
■ 0x00 – Clock disabled
■ 0x01 – 2.5 ns delay
■ 0x02 – 3.5 ns delay

122 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Nonvolatile Latch

10.4 Programming NV Latch

The volatile latch is intended to be initialized from a nonvola-
tile memory cell at POR release. NV Latches are configured
by writing to the volatile cells of the array and then program-
ming the volatile cell data into the nonvolatile cells (Write
Nonvolatile Cell Mode). See the Nonvolatile Memory
Programming chapter on page 473 for more details on NV
latch programming sequence.

NVL programming is done through a simple command/sta-

tus register interface. Commands and data are sent as a
series of bytes to either SPC_CPU_DATA or
SPC_DMA_DATA, depending on the source of the com-
mand. Response data is read via the same register to which
the command was sent. The following commands are used
to program NVLs:
■ Command 0x00 – Load Byte
Loads a single byte of data into the volatile cells at the
given address.
■ Command 0x10 – Read Byte
Reads a single byte of data from volatile cells at the
given address.
■ Command 0x06 – Write User NVL
Writes all nonvolatile cells in a User NVL with the corre-
sponding values in its volatile latches.
■ Command 0x03 – Read User NVL
Reads a single byte of data from nonvolatile cells at the
given address. Note that when this command is exe-
cuted, all of the bytes are transferred from nonvolatile
cells to the volatile cells of the array.

10.5 Sleep Mode Behavior

NV latches remain powered up during sleep, but they stay in
an idle state, not allowing any direct reads or writes. During
sleep, the outputs of the NVLs remain stable.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 123

Nonvolatile Latch

124 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 11. SRAM

PSoC® 3 and PSoC® 5 devices include on-chip SRAM. These families offer devices that range from 2 to 64 kilobytes. PSoC 3
devices offer an additional 4 kilobytes as a trace buffer.

11.1 Features
PSoC 3 and PSoC 5 SRAM has these features:
■ Organized as up to three blocks of 4 KB each, including the 4 KB trace buffer, for CY8C38 family.
■ Organized as up to 16 blocks of 4 KB each, for CY8C55 family.
■ Code can be executed out of portions of SRAM, for CY8C55 family.
■ 8-, 16-, or 32-bit accesses. In PSoC 3 devices the CPU has 8-bit direct access to SRAM.
■ Zero wait state accesses.
■ Arbitration of SRAM accesses by the CPU and the DMA controller.
■ Different blocks can be accessed simultaneously by the CPU and the DMA controller.

11.2 Block Diagram

Block diagrams for the CY8C38 and CY8C55 families are as indicated. Figure 11-1 shows CY8C38 family SRAM accesses.

Figure 11-1. CY8C38 Family SRAM Accesses

8051 Debug on-Chip

CPU (DOC)

SRAM
32 32
PHUB (Includes 4 KB
Trace Buffer)

Peripheral Peripheral

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 125

SRAM

Figure 11-2 shows internal SRAM organization for the CY8C38 family.

Figure 11-2. CY8C38 Family SRAM Organization

SRAM

8051
CPUIF
CPU

PHUB PHUBIF

SRAM
BANK0
(1 KB x 32)

SRAM
BANK1
(1 KB x 32)

SRAM
BANK2
(1KB x 32)
TC DOC_TRACEBUF_ACTIVE

126 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 SRAM

Figure 11-3 shows CY8C55 family SRAM accesses.

Figure 11-3. CY8C55 Family SRAM Accesses

Cortex-M3
CPU

32

32
PHUB SRAM

Peripheral Peripheral

Figure 11-4 shows internal SRAM organization for the CY8C55 family.

Figure 11-4. CY8C55 Family SRAM Organization

SRAM

Cortex-M3
CPUIF
CPU

PHUB PHUBIF

SRAM BANK0
(32 KB)
Lower SRAM

SRAM BANK1
(32 KB)
Upper SRAM

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 127

SRAM

11.3 How It Works

The CY8C38 family has up to 12 KB SRAM implemented as
three 4 KB blocks. All 12 KB are accessible by the 8051
CPU and by the PHUB DMA controller in normal operation.
During debug, the Debug on-Chip (DoC) accesses the
upper 4 KB of SYSMEM as a trace buffer. If the trace buffer
is not used for tracing, it may be used as additional SRAM
for normal operation.

The CY8C55 family has up to 64 KB SRAM implemented as

sixteen 4 KB blocks. All 64 KB are accessible by the Cortex-
M3 CPU and by the PHUB DMA controller in normal opera-
tion. The SRAM is further organized as two 32 KB memory
banks, centered at address 0x20000000. This allows
access to both SRAM banks with either the c-Bus (Cortex-
M3 I and D buses) or the s-Bus (Cortex-M3 system bus).
Code can be executed from all SRAM below address
0x20000000.

The PHUB can use SRAM as a DMA source or target.

All data paths to SRAM are 32 bits wide except the data
path from the 8051 CPU, which is 8 bits wide.

The CPU has a direct connection to SRAM without going

through the PHUB. In addition to faster SRAM access by the
CPU, this allows for simultaneous accesses to SRAM by
both the CPU and the PHUB DMA controller, because
SRAM is physically implemented as multiple separate
blocks. If the CPU and the PHUB are accessing separate
blocks, they both have simultaneous unimpeded access.

In case of contention, the following applies:

■ CY8C38 family – The 8051 has priority over the PHUB
for the lower and upper 4 KB (SRAM BANK0 and
BANK2), and the PHUB has priority over the CPU for the
middle 4 KB (SRAM BANK1). When DoC tracing is
active, the DoC has exclusive access to the upper 4 KB
(SRAM BANK2) – neither the CPU nor the PHUB can
access this bank while tracing is active.
■ CY8C55 family – In most cases, the Cortex-M3 CPU has
priority over the PHUB for all SRAM.

The SRAM responds to CPU, PHUB, and CY8C38 DoC

accesses with zero wait states for both reads and writes as
long as the access does not lose priority arbitration. Arbitra-
tion is done on a cycle-by-cycle basis at the time of SRAM
access. The losing master is held off until the winning mas-
ter has finished accessing the SRAM block; the losing mas-
ter gains access on the cycle immediately after.

SRAM data is maintained during all low power and sleep

modes. At reset, the SRAM contents are not initialized; they
power up as unknown values.

128 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 12. Flash Program Memory

PSoC® 3 and PSoC® 5 include on-chip Flash memory. These two families offer devices that range from 16 to 256 kilobytes.
Additional Flash is available for either error correction bytes or data storage.

12.1 Features
PSoC 3 and PSoC 5 Flash memory have the following features:
■ Organized in rows, where each row contains 256 data bytes plus 32 bytes for either error correcting codes (ECC) or data
storage.
■ For PSoC 3 architecture: CY8C38 Family, organized as one block of 64, 128, or 256 rows.
■ For PSoC 5 architecture: CY8C55 Family, organized as either one block of 128 or 256 rows, or as multiple blocks of 256
rows each.
■ Stores CPU program and bulk or nonvolatile data
■ For PSoC 5 architecture: CY8C55 Family, 8-, 16-, or 32-bit read accesses. PSoC 3 architecture has only 8-bit direct
access.
■ Programmable with a simple command / status register interface (see Nonvolatile Memory Programming chapter on
page 473).
■ Four levels of protection (see Nonvolatile Memory Programming chapter on page 473 and Flash, Configuration
Protection chapter on page 205).

12.2 Block Diagram

Figure 12-1 is a block diagram of the Flash programming system.

Figure 12-1. Flash Block Diagram

Test Controller (TC)

CPU Flash
Debug on-Chip (DOC)

Programming
PHUB
Interface

EEPROM NVL

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 129

Flash Program Memory

12.3 How It Works 12.4 ECC Error Detection and

Flash memory provides nonvolatile storage for firmware, Interrupts
device configuration data, bulk data storage, ECC data, fac-
The ECC detects conditions that may interfere with software
tory configuration data, and protection information.
operation. The information is logged into individual interrupt
Flash memory contains two regions – a main region, and a registers that become latched until the software clears the
much smaller, extended region. All user data is stored in the corresponding valid bit. All interrupt sources within the ECC
main region, including ECC data. Factory configuration and are passed through a mask condition; then, they are
user-defined protection data are stored in the extended reduced into a single interrupt request to the Interrupt Con-
region, also known as the hidden rows of Flash. troller unit.

The main region of Flash in the CY8C38 family is 72 KB, When the software has been notified about an existing inter-
consisting of 64 KB of user space and 8 KB of ECC. The rupt in the ECC, the following sequence occurs:
extended region is four rows of 256 bytes each. 1. The software reads the Interrupt Status register
CACHE_INT_SR that provides the valid bits of all inter-
For each row, protection bits control whether the Flash can
rupts in a single read operation.
be read or written by external debug devices and whether it
can be reprogrammed by a boot loader. For more informa- 2. The software examines individual interrupt registers for
more log information (CACHE_INT_LOG[0..5]).
tion see the Nonvolatile Memory Programming chapter on
page 473 and Flash, Configuration Protection chapter on 3. Stored log information is cleared on read of registers.
page 205. 4. After clearing of log information, the status register
(CACHE_INT_SR) is automatically cleared, because it is
Flash can be read by both the CPU and the DMA controller. a collection of valid bits of the log registers.
Flash is erased in 64-row sectors or in its entirety, and it is Logging is always enabled; reporting may be disabled
programmed in rows. Erase and programming operations through the Interrupt Mask Register (CACHE_INT_MSK).
are done by a programming system, using a simple com-
mand/status register interface. For more information see the The following conditions are detected by the hardware and
Nonvolatile Memory Programming chapter on page 473. logged as potential interrupt sources:
■ ECC – Single Bit – A single bit error was encountered
during a fill operation and was fixed.
■ ECC – Multi Bit – A multi-bit error was encountered dur-
ing a fill operation, but it could not be corrected.
■ Attempted Flash Write – If a write to Flash through the
PHUB is attempted.

130 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 13. EEPROM

PSoC® 3 and PSoC® 5 devices have on-chip EEPROM memory. These two families offer devices that range from 512 bytes
to 2 kilobytes.

13.1 Features
PSoC 3 and PSoC 5 EEPROM memory have the following features:
■ Organized in rows, where each row contains 16 bytes
■ Organized as one block of 32, 64, or 128 rows, depending on the device
■ Stores nonvolatile data
■ Write and erase using SPC commands
■ Byte read access by CPU or DMA using the PHUB
■ Programmable with a simple command/status register interface (see Nonvolatile Memory Programming chapter on
page 473)

13.2 Block Diagram

There is no block diagram associated with EEPROM.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 131

EEPROM

13.3 How It Works

EEPROM memory provides nonvolatile storage for user data. EEPROM write and erase operation is done using SPC com-
mands. It may be read by both the CPU and the DMA controller, using the PHUB. All read accesses are 8-bit.

If a PHUB access is attempted while the SPC is in control of EEPROM, a System Fault Interrupt is generated to the interrupt
controller and the bit EEPROM_error is set in SPC_EE_ERR[0]. Once set, this bit remains set until it is read from the PHUB.
EEPROM can be taken in and out of sleep mode by setting the bit EE_SLEEP_REQ in SPC_FM_EE_CR[4], as shown in
Table 13-1. Before a PHUB access of EEPROM is done, set the firmware EEPROM request bit AHB_EE_REQ in
SPC_EE_SCR[0], then poll for the EEPROM acknowledge bit EE_AHB_ACK in SPC_EE_SCR[1] to be set. Before a PHUB
access of EEPROM is done, firmware should set the EEPROM request bit AHB_EE_REQ in SPC_EE_SCR[0], then poll for
the EEPROM acknowledge bit EE_AHB_ACK in SPC_EE_SCR[1] to be set.

It is also possible to check the current sleep status of the EEPROM by reading the bit EE_AWAKE in SPC_FM_EE_CR[5], as

Table 13-1. Bit Settings for EE_SLEEP_REQ in SPC_FM_EE_CR[4]

Setting Description
0 (default) Wake up EEPROM
1 Put EEPROM to sleep

shown in Table 13-2.

Table 13-2. Bit Settings for EE_AWAKE in SPC_FM_EE_CR[5]

Setting Description
0 EEPROM is asleep
1 (default) EEPROM is awake

EEPROM is erased in 64-row sectors, or in its entirety, and is programmed in rows. Erase, programming and read operations
are done by a programming system using a simple command/status register interface. For more information see Nonvolatile
Memory Programming chapter on page 473.

132 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 14. EMIF

PSoC® 3 and PSoC® 5 architectures provide an external memory interface (EMIF) for connecting to external memory devices
and peripheral devices. The connection allows read and write access to the devices. The EMIF operates in conjunction with
UDBs, I/O ports, and other PSoC 3 and PSoC 5 components to generate the necessary address, data, and control signals.

The EMIF does not intercept address data between the PHUB and the I/O ports. It only generates the required control signals
to latch the address and data at the ports. The EMIF generates a clock to run external synchronous and asynchronous mem-
ories. It can generate four different clock frequencies, which are the bus clock divided by 1, 2, 3, or 4.

14.1 Features
The EMIF supports four types of external memory: synchronous SRAM, asynchronous SRAM, cellular RAM/PSRAM, and
NOR Flash. External memory can be accessed via the 8051 xdata space or the ARM Cortex-M3 external RAM space; up to
24 address bits can be used. The memory can be 8 or 16 bits wide.

14.2 Block Diagram

Figure 14-1 is the EMIF block diagram.

Figure 14-1. EMIF Block Diagram

PSoC 3 / 5 Address Ports

Addr[23:0]
AD
Address Data[15:0]

External Memory
CPU PHUB DQ
24 24 CLK
DMAC
WRn
Port Logic

CEn
AHB Bus ADSCn
Data Ports
OEn
Read / Write Data
ZZ_
16 16

EM_Clock
EM_WRn DSI Control Port
EM_CEn 6 no_udb mode
6
EM_ADSCn
udb mode

EM_OEn
EMIF
EM_Sleep
Xmem_wr
UDB
Xmem_rd
Custom
Udb_Ready 3 UDB Logic

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 133

EMIF

14.3 How It Works

The address component of the EMIF uses up to three I/O 14.3.2 External Memory Support
ports. The I/O ports used for external memory address are
selected by configuring the 3-bit portEmifCfg field in the Table 14-2 on page 137 shows how different external mem-
PRT*_CTL register. The register can be configured so that ory types can be connected to the PSoC 3 and PSoC 5
the port is selected as either the most significant byte, the devices. Address lines use up to three I/O ports. Data lines
middle byte, or the least significant byte of the address. (See use one or two ports, depending on whether the external
the I/O System chapter on page 187 for details of the memory is x8 or x16. Control lines use 3 to 6 pins on one I/O
PRT*_CTL register.) port. Spare pins on the address and data ports are not avail-
able for any other purpose. Spare pins on the control port
The data component of the EMIF uses one or two I/O ports. are available for other purposes.
The I/O port or ports used for external memory data are
selected by configuring the 3-bit portEmifCfg field in the
PRT*_CTL register. The register can be configured so that
the port is selected as either the most significant byte or the
least significant byte of the data. (See the I/O
System chapter on page 187 for details of the PRT*_CTL
register.)

The control component of the EMIF uses a single I/O port.

The I/O port used for external memory control is selected by
configuring the 3-bit portEmifCfg field in the PRT*_CTL reg-
ister. The I/O port must be further configured by setting the
byPass bit in the PRT*_BYP register. This allows the EMIF
to drive the pins. The control signals are sent from the EMIF
to the I/O port over the digital signal interface (DSI).

14.3.1 List of EMIF Registers

This table lists EMIF registers.

Table 14-1. EMIF Registers

Register Usage

Controls whether a synchronous or asynchro-

nous RAM is supported, versus a custom
EMIF_NO_UDB
memory interface requiring additional UDB
logic.

Number of additional wait states used in a

EMIF_RP_WAIT_STATES
read operation.

Puts the external memory into a power down

EMIF_MEM_DWN
state.

Sets the clock divider for the external memory

clock frequency, which can equal the bus
EMIF_MEMCLK_DIV clock frequency divided by 1, 2, 3 or 4. Note
that the external memory clock frequency can-
not exceed 33 MHz.

Enables/disables the clock for the EMIF block,

EMIF_CLOCK_EN
effectively turning the block on or off.

Controls whether to generate control signals

EMIF_EM_TYPE for a synchronous or asynchronous SRAM in
NO_UDB mode.

Number of additional wait states used in a

EMIF_WP_WAIT_STATES
write operation.

134 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 EMIF

Figure 14-2. Synchronous SRAM

[7:0]
ADDR
LO A0–A7
Port

ADDR [7:0]

SRAM (such as CY7C1342H)

MID A8–A15
Port
[0]
A16
ADDR
[7:1]
Hi Port
Unused

[7:0]
Data
LO D0–D7
Port

Synchronous
PSoC 3/ [7:0]
Data
PSoC 5 D8–D15
Hi
Port

CE -
CE1

OE -
OE

Control WE -
GW
Port
ADSC -
ADSC

EM-Clock
CLK

EM-Sleep
ZZ
Vddd
2
Spare
ADSA
ADV
CE2
BWE

CE3
BWA
BWB
Mode

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 135

EMIF

Figure 14-3. Asynchronous SRAM

[7:0]
ADDR
LO A0 – A7
Port

ADDR [7:0]
MID A8 – A15
Port
[1:0]
A16, A17
ADDR
[7:2]
Hi Port

Asynchronous
[7:0]
Data
LO D0 – D7
Port

SRAM or Flash (such as CY7C1041D)

PSoC3/5 Data [7:0]
Hi D8 – D15
Port

CE - CE

OE - OE

WE -
Control Port WE

ADSC -
Unused

EM-Clock
Unused

EM-Sleep
Unused

2 Spare

136 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 EMIF

Table 14-2. External Memory Connections to PSoC 3 and PSoC 5 Devices

PSoC 3, PSoC 5 Synchronous SRAM Asynchronous SRAM Pseudo SRAM NOR Flash
Connection Ex: CY7C1342H Ex: CY7C1041D Ex: CYK256K16MCCB Ex: Intel 28F800C3
3 I/O PORTs A0 - A16 A0 - A17 A0 - A17 A0 - A18
2 I/O PORTs D0 - D15 D0 - D15 D0 - D15 D0 - D15
1 I/O PORT pin: EM_CE CE1 CE CE CE
1 I/O PORT pin: EM_OE OE OE OE OE
1 I/O PORT pin: EM_WE GW WE WE WE
1 I/O PORT pin: EM_ADSC ADSC
1 I/O PORT pin: EM_CLOCK CLK
1 I/O PORT pin: EM_SLEEP ZZ RPa
tie high ADSP WP
tie high ADV
tie high CE2
tie high BWE
tie low CE3
tie low BWA BHE BHE
tie low BWB BLE BLE
tie low MODE
a. RP is opposite polarity from the ZZ signal on the synchronous SRAM. Either add an inverter to the EM_SLEEP signal or program the EMIF_MEM_DOWN
register with the opposite polarity.

14.3.3 Sleep Mode Behavior

All EMIF registers keep their value during sleep mode. The
MEM_DWN register controls external memory sleep mode;
the external control signal ZZ is asserted or deasserted. If
an external memory access happens when MEM_DWN is
set, ZZ is not asserted until after the current transfer is com-
pleted. ZZ is deasserted when the MEM_DWN register is
cleared; it then takes two external memory clock cycles for
the memory to wake up.

To completely turn off the EMIF block, clear the CLOCK_EN

register.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 137

EMIF

14.4 EMIF Timing An important limitation is that the maximum I/O rate of
PSoC 3 and PSoC 5 GPIO pins is 33 MHz. This makes the
The EMIF is clocked by bus clock – the same signal that maximum frequency of EM_CLOCK 33 MHz. The following
clocks the CPU and the PHUB. Within the EMIF block, the table shows limitations of EM_CLOCK frequency relative to
bus clock can be divided by 1, 2, 3, or 4; the output is the the bus clock:
EM_CLOCK signal to the external memory IC.
Table 14-4. Limitations of EM_CLOCK Relative to Bus
The following table shows the number of PHUB wait states Clock
generated by the EMIF depending on how much the input
Bus Clock Frequency EM_CLOCK = Bus Clock Divided By
clock is divided.
< 33 MHz 1, 2, 3, or 4
Table 14-3. PHUB Wait States Generated by EMIF 33 - 66 MHz 2, 3, or 4

EM_CLOCK = > 66 MHz 3 or 4

Read Wait States Write Wait States
Bus Clock Divided By
1 1 2 The maximum frequency of the bus clock is 67 MHz for
2 3 4
PSoC 3 devices and 80 MHz for PSoC 5 devices. In most
cases, EMIF_MEMCLK_DIV must be used to divide
3 5 6
EM_CLOCK to a frequency less than or equal to 33 MHz.
4 7 8
Given the above restriction on EM_CLOCK frequency, and
The EMIF.WAIT_STATES register can also be used to add the relation of EM_CLOCK to EM_ADSC-, EM_CE-, and
up to seven more wait states. EM_WE-, it can be seen that the minimum pulse widths of
these signals is 30.3 ns.

Figure 14-4. Synchronous Write Cycle Timing

EM_Clock

EM_CEn

EM_Addr Address

EM_OEn

EM_Data Data

EM_ADSCn

138 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 EMIF

Figure 14-5. Synchronous Read Cycle Timing

EM_Clock

EM_CEn

EM_Addr Address

EM_OEn

EM_Data Data

EM_ADSCn

Figure 14-6. Asynchronous Write Cycle Timing

EM_Addr Address

EM_CEn

EM_OEn

EM_WEn

EM_Data Data

Figure 14-7. Asynchronous Read Cycle Timing

EM_CEn

EM_Addr Address

EM_OEn

EM_WEn

EM_Data Data

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 139

EMIF

14.5 Using EMIF with Memory- itation here is the PSoC 5 cannot initiate 8 bit transfers to
16-bit memories and should not initiate unaligned 16-bit or
Mapped Peripherals 32-bit transfers to an external memory, as the processor
The EMIF can also be used with external peripheral devices may convert these into multiple 8 bit aligned accesses.
that have a bus interface similar to asynchronous memory However, 32 or 16-bit aligned transfers are handled cor-
devices, that is, they address, data, CE-, WE-, and OE-. The rectly by the processor and PHUB.
speed of the interface must be considered in the same man-
ner as described above. The maximum data bus size is 16 14.6.4 8-bit Memory Transfers
bits, and the minimum address bus size is 8 bits. If multiple DMA Transfers: For DMA transfers to/from an 8 bit external
external memory and peripheral devices are used, address memory, the burst count should always be 1, irrespective of
decoding to the multiple device selects may become com- the transfer count. For example, if the burst count is set as 2
plex and must be given careful consideration. in order to transfer two bytes to external memory, the PHUB
will try to do a 16-bit transfer in a single burst instead of
14.6 Additional Configuration breaking the transfer down into two individual transfers with
the 8-bit memory.
Guidelines
The PHUB assumes all peripherals including external mem-
ory are byte addressable. Port logic is natively 16 bits wide,
so care must be taken when setting up communication with
either an 8 or 16 bit external memory. The following section
describes some guidelines to configure the port pins and set
up the memory access methods (either CPU or DMA) for
optimal performance.

14.6.1 Address Bus Configuration

Configure three of the available ports as output EMIF
address ports. Since PHUB peripherals are byte address-
able regardless of the external memory data bus size, up to
2^24 bytes of external memory can be accessed. If an 8-bit
memory is used, up to 24-bit address lines can be directly
connected to the memory. If a 16-bit memory is used, the
LSB address line (A0) of the memory chip should be con-
nected to the second address line (A1) of the PSoC and the
LSB address line (A0) of the PSoC should be ignored. This
is because the PHUB increments the address by 2 while
doing 16-bit transactions.

14.6.2 Data Bus Configuration

For 16 bit memories, two ports should be configured as bidi-
rectional EMIF data ports. For 8bit memories, only one port
should be configured as a bidirectional EMIF data port.

14.6.3 16-bit Memory Transfers

DMA Transfers: For DMA transfers to/from 16bit external
memory, odd burst counts are not supported because 8 bit
transfers are not supported on a 16bit interface.

CPU Transfers: With the 8bit 8051 processor in PSoC 3, 16-

bit external memory cannot be directly accessed by the
CPU. With the 32 bit ARM M3 processor in PSoC 5, 16-bit
memory can be directly accessed by the CPU. The only lim-

140 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 15. Memory Map

All PSoC® 3 and PSoC® 5 memory (Flash, EEPROM, Nonvolatile Latch, and SRAM) and all registers are accessible by the
CPU, DMA controller, and in most cases by the debug systems. This chapter contains an overall map of the addresses of the
memories and registers.

15.1 Features
The PSoC 3 memory map has the following features:
■ Flash is accessed in the 16-bit (64 KB) 8051 code space.
■ All other memories, and all registers, are accessed in the 24-bit 8051 external memory space.
■ 8051 has internal SFRs to provide fast access to some registers. Refer to the 8051 Core chapter on page 37 for details.

The PSoC 5 memory map has the following features:

■ ARM Cortex-M3 32-bit linear address space, with regions for code, SRAM, peripherals, external RAM, and CPU internal
registers.
■ Flash is mapped to the Cortex-M3 code region.
■ Half of SRAM is mapped to the code region, the other half to the SRAM bitband region.
■ SRAM mapped to the code region is also accessible by DMA in the SRAM bitband region.
■ External memory (see the EMIF chapter on page 133) is mapped to the external RAM region.
■ All other memories, and all registers, are accessed in the Cortex-M3 peripheral bitband region.

15.2 Block Diagram

There is no block diagram associated with the memory map.

15.3 How It Works

The PSoC 3 and PSoC 5 memory maps are detailed in the following sections. For additional information refer to the PSoC® 3
Registers TRM (Technical Reference Manual) and the PSoC® 5 Registers TRM (Technical Reference Manual).

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 141

Memory Map

15.3.1 PSoC 3 Memory Map

The map of the 8051 external memory (xdata) space is listed in Table 15-1. For additional information, refer to the 8051
Core chapter on page 37.

Table 15-1. PSoC 3 Memory Map

Address Range Purpose
0x00 0000 - 0x00 1FFF SRAM
0x00 4000 - 0x00 42FF Clocking, PLLs, and oscillators
0x00 4300 - 0x00 43FF Power management
0x00 4400 - 0x00 44FF Interrupt controller
0x00 4500 - 0x00 45FF Ports interrupt control
0x00 4700 - 0x00 47FF Flash programming interface
0x00 4900 - 0x00 49FF I2C controller
0x00 4E00 - 0x00 4EFF Decimator
0x00 4F00 - 0x00 4FFF Fixed timer/counter/PWMs
0x00 5000 - 0x00 51FF General purpose I/Os
0x00 5300 - 0x00 530F Output port select register
0x00 5400 - 0x00 54FF External memory interface control registers
0x00 5800 - 0x00 5FFF Analog subsystem interface
0x00 6000 - 0x00 60FF USB controller
0x00 6400 - 0x00 6FFF UDB configuration
0x00 7000 - 0x00 7FFF PHUB configuration
0x00 8000 - 0x00 8FFF EEPROM
0x00 A000 - 0x00 A400 CAN
0x00 C000 - 0x00 C800 Digital filter block
0x01 0000 - 0x01 FFFF Digital interconnect configuration
0x05 0220 - 0x05 02F0 Debug controller – accessible via JTAG/SWD only, not accessible via PHUB
0x08 0000 - 0x08 1FFF Flash ECC bytes
0x80 0000 - 0xFF FFFF External Memory Interface (EMIF)

142 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Memory Map

15.3.2 PSoC 5 Memory Map

The ARM Cortex-M3 has a fixed address map allowing access to peripherals using simple memory access instructions. The
32-bit (4 GB) address space is divided into the regions shown in Table 15-2. Note that code can be executed from the code,
SRAM, and external RAM regions.

Table 15-2. PSoC 5 Memory Map

Address Range Size Use
0x00000000 – 0x1FFFFFFF 0.5 GB Program code. Includes the exception vector table at power up, which starts at address 0
SRAM. This includes a 1 MByte bit-band region starting at 0x20000000, and a 32 Mbyte bit-band alias
0x20000000 – 0x3FFFFFFF 0.5 GB
region starting at 0x22000000.
Peripherals. This includes a 1 MByte bit-band region starting at 0x40000000, and a 32 Mbyte bit-band
0x40000000 – 0x5FFFFFFF 0.5 GB
alias region starting at 0x42000000.
0x60000000 – 0x9FFFFFFF 1 GB External RAM
0xA0000000 – 0xDFFFFFFF 1 GB External peripherals
0xE0000000 – 0xFFFFFFFF 0.5 GB Internal peripherals, including the NVIC and debug and trace modules

The PSoC 5 address map is shown in Table 15-3. For more information refer to the Cortex-M3 chapter.

Table 15-3. PSoC 5 Address Map

Address Range Purpose
0x0000 0000 – 0x0003 FFFF Up to 256 KB Flash
0x1FFF 8000 – 0x1FFF FFFF Up to 32 KB SRAM in code region
0x2000 0000 – 0x2000 7FFF Up to 32 KB SRAM in SRAM region
0x2000 8000 – 0x2000 FFFF Alias of address range 0x1FFF 8000 – 0x1FFF FFFF, accessible by DMA
0x4000 4000 – 0x4000 42FF Clocking, PLLs, and oscillators
0x4000 4300 – 0x4000 43FF Power management
0x4000 4500 – 0x4000 45FF Ports interrupt control
0x4000 4700 – 0x4000 47FF Flash programming interface

0x4000 4900 – 0x4000 49FF I2C controller

0x4000 4E00 – 0x4000 4EFF Decimator
0x4000 4F00 – 0x4000 4FFF Fixed timer/counter/PWMs
0x4000 5000 – 0x4000 51FF General purpose I/Os
0x4000 5300 – 0x4000 530F Output port select register
0x4000 5400 – 0x4000 54FF External memory interface control registers
0x4000 5800 – 0x4000 5FFF Analog subsystem interface
0x4000 6000 – 0x4000 60FF USB controller
0x4000 6400 – 0x4000 6FFF UDB configuration
0x4000 7000 – 0x4000 7FFF PHUB configuration
0x4000 8000 – 0x4000 87FF EEPROM
0x4000 A000 – 0x4000 A400 CAN
0x4000 C000 – 0x4000 C800 Digital filter block
0x4001 0000 – 0x4001 FFFF Digital interconnect configuration
0x4800 0000 – 0x4800 7FFF Flash ECC bytes
0x6000 0000 – 0x60FF FFFF External Memory Interface (EMIF)
0xE000 0000 – 0xE00F FFFF Cortex-M3 PPB registers, including NVIC, debug, and trace

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 143

Memory Map

144 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Section D: System Wide Resources

The System Wide Resources section details three types of I/O, internal clock generators, power supply, boost converter, and
sleep modes.

This section contains these chapters:

■ Clocking System chapter on page 147
■ Power Supply and Monitoring chapter on page 163
■ Low Power Modes chapter on page 169
■ Watchdog Timer chapter on page 175
■ Reset chapter on page 179
■ Auxiliary ADC chapter on page 179
■ I/O System chapter on page 187
■ Flash, Configuration Protection chapter on page 205

Top Level Architecture

System Wide Resources Block Diagram

SYSTEM WIDE RESOURCES

Xtal System Bus

Osc
Clock Tree

WDT
RTC
and ILO
Timer
Wake
IMO

Clocking System

POR and Sleep

1.8V LDO SMP
LVD Power

Power Management System

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 145

 Section D: System Wide Resources

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 146

 16. Clocking System

The clock generator provides the main/master time bases for the entire device. It allows the user to trade off current, fre-
quency, and accuracy. A wide range of frequencies can be generated, using multiple sources of clock inputs combined with
the ability to set divide values.

16.1 Features
The clock system has these:
■ Four internal clock sources increase system integration:
❐ 3 to 67 MHz Internal Main Oscillator (IMO) ±1% at 3 MHz
❐ 1 kHz, 33 kHz, 100 kHz Internal Low Speed Oscillator (ILO) outputs
❐ 12 to 67 MHz clock doubler output, sourced from IMO, MHz External Crystal Oscillator (MHzECO), and Digital System
Interconnect (DSI)
❐ 24 to 67 MHz fractional Phase-Locked Loop (PLL) sourced from IMO, MHzECO, and DSI
■ DSI signal from an external I/O pin or other logic as well as a clock source
■ Two external clock sources provide high precision clocks:
❐ 4 to 33 MHz External Crystal Oscillator (MHzECO)
❐ 32.768 kHz External Crystal Oscillator (kHzECO) for Real Time Clock (RTC)
■ Dedicated 16-bit divider for bus clock
■ Eight individually sourced 16-bit clock dividers for the digital system peripherals
■ Four individually sourced 16-bit clock dividers for the analog system peripherals
■ IMO has a USB mode that auto locks to the USB bus clock, requiring no external crystal for USB. (USB equipped parts
only)

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 147

Clocking System

16.2 Block Diagram

Figure 16-1 gives a generic view of the Clocking System in PSoC® 3, PSoC® 5 devices.

Figure 16-1. Clocking System Block

External I/O
3 MHz -48 MHz 4 MHz - 33 1/33/100 kHz
or DSI 32 kHz ECO
IMO MHz ECO ILO
0 MHz - 33 MHz

dsi_clkin
12 MHz - clk_imo2x
48 MHz clk_imo
USB Clk Mux +
clk_pll
Doubler clk_dsi_glb Div2
clk_imo2x

CPU Clock Divider

clk_32k

clk_ilo
clk_dsi_glb

24 MHz - Master 4-Bit

67 MHz Clock Mux
clk_imo

clk_xtal

PLL 8-bit Clock

Divider
clk_pll clk_sync_d Bus Clock Divider
1Bit

7 7
Digital (User) 0 clk_sync_d
s
dsi_d[n] Clock Mux and 1 clk_imo Analog (User)
dsi_a[n] k
16-Bit Divider Clock Mux and 1-
2 clk_xtal e
clk_sync_a[n] Bit Divider w
3 clk_ilo
...

4 clk_pll

...
x8 5 clk_32k
6 clk_dsi_glb
x4

The components of the clocking system block diagram are 16.3 Clock Sources
defined as follows:
■ Internal Main Oscillator (IMO) Clock sources for the device are classified as internal oscil-
lators and external crystal oscillators. There is an option of
■ Internal Low-speed Oscillator (ILO)
using a PLL or a frequency doubler to derive higher fre-
■ A 4 to 33 MHz External Crystal Oscillator (MHzECO) quency outputs from existing clocks. Signals can be routed
■ A 32 kHz External Crystal Oscillator (kHzECO) from the DSI and used as clocks in the clock trees.
■ Digital System Interconnect (DSI) signal, which can be
the clocks developed in UDBs or off-chip clocks routed 16.3.1 Internal Oscillators
through pins PSoC devices have two internal oscillators: the Internal
■ A PLL to boost the clock frequency on select internal Main Oscillator (IMO) and the Internal Low Speed Oscillator
and external sources (ILO).
■ Five types of clock outputs:
❐ Digital clocks
❐ Analog clocks
❐ Special purpose clocks
❐ System clock
❐ USB clock

148 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Clocking System

Figure 16-2. IMO Block Diagram

FASTCLK_IMO_CR [2:0]

FASTCLK_IMO_CR [5]
Osc
(3/6/12/
IMOCLK
24/48
IMO
MHz) clk_imo
dsi_clkin OUT
CLK IMOCLK X 2
IMO Doubler MUX
XCLK MUX
SRC
MUX
clk_eco_Mhz

FASTCLK_IMO_CR [4] CLKDIST_CR[5:4]

CLKDIST_CR[6]

16.3.1.1 Internal Main Oscillator 16.3.1.2 Internal Low Speed Oscillator

The IMO operates with no external components and outputs The ILO produces two primary independent output clocks
a stable clock, clk_imo, at a variety of user-selectable fre- with no external components and with very low power con-
quencies: 3, 6, 12, 24, and 48 MHz. Frequencies are sumption. These two outputs operate at nominal frequen-
selected using the register FASTCLK_IMO_CR [2:0]. The cies of 1 kHz and 100 kHz. The two clocks run
clock accuracy is 1% typical at 3 MHz and it varies with fre- independently, are not synchronized to each other, and can
quency. See the device datasheet for IMO accuracy specifi- be enabled or disabled together or independently. The 1 kHz
cation. clock is typically used for a background central timewheel
and also for the watchdog timer. The 100 kHz clock can pro-
Clock Doubler vide a low power system clock, or it can be used to time
The block has one additional clock output. A doubled clock, intervals such as for sleep mode entry and exit. A third clock
IMOCLKX2 outputs a clock at twice the frequency of the output is available — a divide-by-3 of the 100 kHz output.
input clock. The doubler works for input frequencies in the In addition to the multiplexed output that can enter the clock
range 6 – 33 MHz. The doubler is enabled by register bit distribution, the output clocks route to the following func-
FASTCLK_IMO_CR[4]. The doubler can also take clock tions:
inputs (XCLK) other than IMO and have a DSI or MHzECO
■ clk_ilo1K – to the central timewheel (also called the
as input. This feature is enabled by the bit
sleep timer) and watchdog timer. Refer to the Low Power
FASTCLK_IMO_CR[5]. The DSI / MHzECO can be selected
Modes chapter on page 169 for more details.
in the CLKDIST_CR[6] register bit.
■ clk_ilo100K – to the fast timewheel.
The clock distribution register CLKDIST_CR[5:4] is respon-
■ clk_ilo33K – to the 32 kHz crystal oscillator (kHzECO)
sible for selecting between IMO or IMO × 2 outputs.
for start-up monitoring – This output has a dedicated
Figure 16-2 is a summary block diagram of the IMO. connection to the 32k-crystal oscillator block for this.
Operation of the 33 kHz crystal requires the 100 kHz ILO
Fast Start IMO (FIMO) clock to be enabled.
An alternate mode of the IMO is available for fast start-up This oscillator operates at very low current and is, therefore,
out of sleep modes. This Fast-start IMO (FIMO) mode pro- the best fit for use in low power modes. The two sources,
vides a clock output within 1 µs after exiting the power down 1 kHz and 100 kHz, can be enabled and disabled, using the
state. This alternate oscillator runs only at 48 MHz and is SLOWCLK_ILO_CR0 [1] and SLOWCLK_ILO_CR0 [2],
less precise (10%) than the primary IMO. This function is respectively. SLOWCLK_ILO_CR0 [5] enables the divide by
activated only when waking up and is selected by setting the 3 to create the 33 kHz output. The out puts from the ILO can
FASTCLK_IMO_CR [3] bit. When this mode is selected, the be routed to the clock distribution network. CLKDIST_CR
FIMO clock replaces the IMO clock at the next wakeup. [3:2] is responsible for this selection.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 149

Clocking System

Figure 16-3 is a summary block diagram of the ILO.

Figure 16-3. ILO Block Diagram

SLOWCLK_ILO_CR0 [1]

clk_ilo1K
1 kHz Osc

ILO
clk_ilo33K
Divide by 3 Out
BIAS Mux
SLOWCLK_ILO_CR0 [2]

SLOWCLK_ILO_CR0 [5]
clk_ilo100K
100 kHz Osc
CLKDIST_CR [3:2]

The ILO clocks are all disabled in the Hibernate mode. The crystal pins are shared with a standard I/O function
SLOWCLK_ILO_CR0 [4] is the power down mode bit gov- (GPIO / LCD / Analog Global), which must be tristated to
erning the wakeup speeds of the device. Setting the bit operate the crystal oscillator with an attached external crys-
slows down the startup, but it provides a low power opera- tal.
tion.
The crystal output routes to the clock distribution network as
a clock source option, and it can also route through the IMO
16.3.2 External Oscillators doubler to produce doubled frequencies, if the crystal fre-
PSoC devices have two external crystal oscillators: the MHz quency is in the valid range for the doubler.
Crystal Oscillator (MHzECO) and the 32.768 kHz Crystal The oscillator allows for a wide range of crystal types and
Oscillator (kHzECO). frequencies. Startup times vary with frequency and crystal
quality. The xcfg bits of the FASTCLK_XMHZ_CFG0 [4:0]
16.3.2.1 MHz Crystal Oscillator register are used to match the oscillator settings to the crys-
The 4-33 MHz external crystal oscillator MHzECO circuit tal. The oscillator can be enabled by
provides for precision clock signals. The block supports a FASTCLK_XMHZ_CSR [0].
variety of fundamental mode parallel resonance crystals.
Figure 16-4 is a block diagram of the MHzECO.
When used in conjunction with the on-chip PLL, a wide
range of precision clock frequencies can be synthesized, up
to 67 MHz.
Figure 16-4. MHzECO Block Diagram

External Xop
Components

clk_eco_Mhz
4-33 MHz
Crystal Osc

Caps 4-33 MHz

Crystal Xip

150 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Clocking System

Figure 16-5. MHzECO Oscillator Fault Recovery

FASTCLK_XMHZ_CSR[6]
Xerr and Xprot
FASTCLK_XMHZ_CSR[7]

Xosc Out
clk_eco_Mhz
MHz XOSC

clk_imo

Fault Recovery This clock routes to the clock distribution network as an

input clock source and also to the RTC timer. This oscillator
The block contains an option to detect crystal oscillator fail-
is one of the clock sources available to the clock distribution
ure. The clock failure can occur due to environmental condi-
logic. The kHzECO is enabled and disabled by the register
tions (such as moisture) that affect the crystal and cause
SLOWCLK_X32_CR [0].
oscillators to stop. Clock failure status is indicated by clock
error status bit (FASTCLK_XMHZ_CSR[7]). Figure 16-6 is a block diagram of the kHzECO.

If the FASTCLK_XMHZ_CSR[6] bit is set, the fault recovery Figure 16-6. kHzECO Block Diagram
option is enabled. In this case, when the crystal oscillator
External Xo
fails, the crystal oscillator output is driven low. The IMO is Components
enabled (if it is not already running), and the IMO output
routes through the crystal oscillator output mux. In this way, clk_eco_Khz
32 kHz
the system can continue to operate through a crystal fault. Crystal Osc
This functionality is diagrammed in Figure 16-5. Caps 32 kHz
Crystal Xi
Low Power Operation
The MHz crystal oscillator operation is not required in the Low Power Operation
SLEEP/HIBERNATE modes. This means that you need to
disable the oscillator in order to enter SLEEP/HIBERNATE The oscillator operates at two power levels, depending on
modes. The 32 kHz crystal oscillator can be kept active, for the state of the LPM bit (SLOWCLK_X32_CR [1]) and the
precise timing (RTC), in the SLEEP/HIBERNATE modes. If device sleep mode status. In Active mode, by default, a
the MHz crystal oscillator is not disabled when the device is hardware interlock forces the oscillator into its high power
put into any of these modes, the mode entry is skipped, and mode, which consumes 1-2 µA and minimizes sensitivity to
the code continues to execute in active mode. Because this noise. If the LPM mode is set for a low power mode, the
clock must be disabled to enter SLEEP mode, a typical oscillator goes into Low power only when the device goes to
approach is to switch clock trees to the IMO source and then SLEEP/HIBERNATE. If LP_ALLOW (SLOWCLK_X32_CFG
disable the crystal oscillator (and the PLL also, if it is on). [7]) is set, the oscillator enters low power mode immediately
Then SLEEP/HIBERNATE mode can be entered. After wak- when the LPM bit is set.
ing up from a sleep mode, the crystal oscillator can be reen- When enabled, the oscillator does not stabilize instantly, and
abled and used as a clock source when stable. requires some time to oscillate consistently. Two two status
monitors are available for this. The DIG_STAT
16.3.2.2 32.768 kHz Crystal Oscillator (SLOWCLK_X32_CR[4]) status bit indicates oscillation is
The 4 MHz to 33 MHz external crystal oscillator kHzECO cir- stable by comparing it with a signal (33 kHz ILO) that the
cuit produces a precision timing signal at very low power. user must enable with the ILO. The ANA_STAT
The circuit uses an inexpensive external 32.768 kHz crystal (SLOWCLK_X32_CR[5]) bit uses an internal analog monitor
and associated network capacitors that can be used to pro- to measure oscillator amplitude. The oscillator must always
duce a real time clock. Current consumption can be much be started in high power mode to avoid excessively long
less than 1 µA. startup delays.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 151

Clocking System

Real Time Clock

One of the major uses of the kHzECO oscillator is for RTC implementation. The block level illustration of the RTC implemen-
tation is shown in Figure 16-7.

The RTC timing is derived from the 32 kHz external crystal oscillator, as shown in Figure 16-7. Therefore, for the functioning
of the RTC, the 32 kHz external crystal must be enabled through the register SLOWCLK_X32_CR [0]. The generated 32 kHz
is divided to achieve a one pulse per second. The register PM_TW_CFG2[4] enables one pulse per second functionality.

By enabling the bit PM_TW_CFG2[5], the RTC generates an interrupt every second. The interrupt is routed through the DSI
and is brought out as an interrupt. Refer to the UDB Array and Digital System Interconnect chapter on page 255 for more
details on usage. RTC functionality is available for use in all power modes except the Hibernate mode.

Figure 16-7. RTC Implementation

To Clock
clk_eco_Khz Distribution
External 32 kHz
Oscillator Divide by Generates a
32768 one-pps
Interrupt
32 kHz En

Crystal
PM_TW_CFG2 [4] PM_TW_CFG2 [5]

SLOWCLK_X32_CR [0]

16.3.3 Oscillator Summary 16.3.4 DSI Clocks

An oscillator summary is listed in Table 16-1. Signals can be routed from the Digital Signal Interconnect
(DSI) and used as clocks in the clock trees. The sources of
Table 16-1. Oscillator Summary these clocks include:
Source Fmin Fmax ■ Clocks developed in UDBs
IMO 3 MHz 67 MHz
■ Off-chip clocks routed through pins
ILO 1 kHz 100 kHz
■ Clock outputs from the clock distribution; fed directly
MHzECO 4 MHz 33 MHz
back into the network through the routing fabric
kHzECO 32 kHz 32 kHz
PLL 12 MHz 67 MHz

Figure 16-8. PLL Block Diagram

clk_imo Q-Divider
CLK 4 Bits
clk_eco_Mhz UP clk_pll
MUX (1-16) Filter and
PFD
dsi_clkin FASTCLK_PLL_Q DOWN VCO
To Clock
Distribution
P-Divider
Lock Detect
8 Bits
FASTCLK_SR [0]
(4-256)
FASTCLK_PLL_P

PLL

152 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Clocking System

16.3.5 Phase-Locked Loop

The on-chip Phase-Locked Loop (PLL) can be used to boost
the clock frequency of the selected clock input (i.e., IMO,
MHzECO, and DSI clock) to run the device at maximum
operating frequency. The PLL can synthesize clock frequen-
cies in the range of 24 – 67 MHz. Its input and feedback
dividers allow fine enough resolution to create many desired
system clock frequency. The PLL output routes to the clock
distribution network as one of the possible input sources.
The PLL is shown in Figure 16-8.

The PLL uses a 4-bit input divider Q (FASTCLK_PLL_Q) on

the reference clock and an 8-bit feedback divider P
(FASTCLK_PLL_P). The outputs of these two dividers are
compared and locked, resulting in an output frequency that
is P/Q times the input reference clock. The PLL achieves
frequency lock in less than 100 µs, and provides a bit that
shows lock status (FASTCLK_PLL_SR[0]). When lock is
achieved, the PLL output clock can be routed into the clock
trees.

The PLL takes inputs from the IMO, the crystal oscillator
MHzECO, or the DSI, which can be an external clock.

Low Power Operation

The PLL must be disabled before going into SLEEP/HIBER-
NATE mode. This allows clean entry into SLEEP/HIBER-
NATE and wakeup. The PLL can be reenabled after wakeup
and when it is locked; then it can be used as a system clock.
The device is designed not to go into SLEEP/HIBERNATE
mode if the PLL is enabled when mode entry is attempted.
(Execution continues without going into SLEEP/HIBER-
NATE mode in this case.)

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Clocking System

16.4 Clock Distribution

All of the clock sources discussed are distributed into the various domains of the device through clock distribution logic.
Figure 16-9 shows a block diagram of the clock distribution system.

Figure 16-9. Clock Distribution System

dsi_clkin
clk_imo2x
USB CLK
IMO + clk_usb
MUX
Doubler PLL Mux 48 MHz
4-33 MHz clk_xtal dsi_gp
XTAL 3-62 MHz Prescale Master Clock
Mux
33KHz PLL 8-bit divider
clk_sync
Watch clk_imo
clk_pll
XTAL
clk_spc
ILO 36 MHz
1, 33, 100
KHz

dsi_g 4-bit clk_cpu

Divide

dsi_d0 clk_bus
resync

16-Bit clk_d0
Divide clk_d_ff0

resync
16-Bit
Phase
Divide
mod
dsi_d1
clk_d1
resync

16-Bit s8misc_delay_top
Divide clk_d_ff1 11
clk_sync_d
DigitalPhaseMux
dsi_d2
clk_d2
resync

16-Bit
Divide clk_d_ff2
Ana3 Phase Ana2 Phase Ana1 Phase Ana0 Phase
Mux Mux Mux Mux
dsi_d3
resync

16-Bit clk_d3 clk_ sync_a3

clk_d_ff3 clk_ sync_a2
Divide clk_ sync_a1
clk_ sync_a0

dsi_a0 resync
dsi_d4 clk_d4 16-Bit
resync

16-Bit clk_a0
Divide
Divide clk_d_ff4
Ph- Sel dig-resync clk_ad0

dsi_d5 dsi_a1
resync

clk_d5 16-Bit
resync

16-Bit clk_a1
clk_d_ff5 Divide
Divide
Ph- Sel dig-resync clk_ad1

dsi_d6 dsi_a2
resync
resync

16-Bit clk_d6 16-Bit

clk_a2
Divide clk_d_ff6 Divide

Ph- Sel dig-resync clk_ad2

dsi_d7 dsi_a3
resync
resync

16-Bit clk_d7 16-Bit clk_a3

Divide clk_d_ff7 Divide
Ph- Sel dig-resync clk_ad3

All of the clocks available in the device are routed across the ■ Digital clock
device through digital and analog clock dividers. There are ■ Analog clock
certain peripherals that require specific clock source for its
■ USB clock
operation. For example, Watchdog Timer (WDT) requires
Internal Low Speed Oscillator (ILO). In such cases, the cor- The clock distribution provides a set of eight dividers for the
responding clock source is directly routed to the peripheral. digital clock tree and four analog clock dividers for the ana-
log clock tree. All of the clock sources come as input options
The clock distribution can be considered to be a combina-
for all of the clock dividers through eight input mux. Also, the
tion of the following clock trees.
divider outputs are synchronized to their respective domain
■ System clock clocks.

154 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Clocking System

A Master Clock Mux is available for distributing the sync for the network: clk_sync_dig and the analog system clocks,
clocks. There are options to provide delay on the digital sync clk_sync_a. The master clock must be configured to be the
clock. All eight digital dividers are synchronized to the same fastest clock in the system. The master clock also provides
digital clock, but each of the analog clock divider outputs a mechanism for switching the clock source for multiple
can be synchronized to analog clocks of different delays. clock trees instantaneously, while maintaining clock align-
The clock distribution also is responsible for the generation ments. For systems that must maintain known clock rela-
of the major clock domains in the device, such as the Sys- tionships, clock trees select the clk_sync_dig (or
tem clock, bus clock, and others. clk_sync_a*) clock as their input source.

Therefore, when the source is changed (for example, when

16.4.1 Master Clock Mux moving from the IMO source initially to a new PLL- synthe-
The Master Clock Mux, shown in Figure 16-10, selects one sized frequency), all clocks change together through the
clock from among the PLL, selected IMO output, the MHz Master Clock Mux output. The Master Clock Mux contains
crystal oscillator, and the DSI input (dsi_clkin). This clock an 8-bit divider to generate lower frequency clocks,
source feeds the phase mod circuit to produce skewed (CLKDIST_MSTR0[7:0]). It outputs an approximately 50%
clocks that are selected by the digital and analog phase mux clock.
blocks. The Master Clock Mux provides the re-sync clocks
Figure 16-10. Master Clock Mux

CLKDIST_MSTR1_SRC_SEL [1:0]

Divide-by-1
clk_pll
clk_imo 8-Bit Divider
(1-256) D Q
clk_eco_MHz CLKDIST_MSTR0 clk_sync
dsi_clkin

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 155

Clocking System

16.4.2 USB Clock

The USB clock domain is unique because it can operate largely asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the device while being able to run on a potentially asynchronous clock to process
USB data. For full speed USB, the clock must have an accuracy of ±0.25%.

The USB Clock Mux, shown in Figure 16-11, provides the clock to the USB logic.

Figure 16-11. USB Clock Mux

CLKDIST_UCFG_SRC_SEL[1:0]

IMOCLK

IMOCLKX2

PLL clk_usb
Divide-by-2
DSI
dsi_glb_div[0]

CLKDIST_UCFG_DIV2

The USB clock mux selects the USB clock from these clock USB Mode Operation
sources.
This device works with an automatic clock frequency locking
■ imo1x (these options are available inside the IMO block): circuit for USB operation. This design allows for small fre-
❐ 48 MHz DSI clock subjected to the accuracy of the quency adjustments based on measurements of the incom-
source of the clock ing USB timing (frame markers) versus the IMO clock rate.
❐ Crystal oscillator will not work at 48 MHz, so it has to With this clock locking loop, the clock frequency can stay
be multiplied by PLL to get to 48 MHz within spec for the USB Full Speed mode (±0.25% accu-
❐ Cannot use 48 MHz IMO due to clock accuracy rate). The IMO must be operated at 24 MHz for proper clock
issues locking, with the doubler supplying 48 MHz for USB logic.
■ imo2x (these options are available inside the IMO block): The USB locking feature for the IMO can be enabled by the
register bit FASTCLK_IMO_CR [6].
❐ 24 MHz crystal with doubler
❐ 24 MHz IMO with doubler with USB lock Alternately, a 24 MHz crystal controlled clock (doubled to 48
❐ 24 MHz DSI input with doubler MHz) can be supplied for Full Speed USB operation. Other
crystal frequencies, such as 4 MHz could be used with the
■ clk_pll:
PLL to synthesize the necessary 48 MHz.
❐ Crystal with PLL to generate 48 MHz
Valid frequency for the PLL output, in this case, is 48 MHz.
❐ IMO with PLL to generate 48 MHz
The DSI signal, dsi_glb_div [0], provides another DSI signal
❐ DSI input with PLL to generate 48 MHz
choice in addition to the clk_imo option above. As with the
■ DSI input: PLL, this clock must have USB accuracy and be 48 MHz.
❐ 48 MHz
In this situation, any of the choices can produce a valid
48 MHz clock for the USB. If the internal main oscillator is
selected, it must be run with the oscillator locking function
enabled, in which case it self tunes to the required USB
accuracy when USB traffic arrives at the device.

156 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Clocking System

16.4.3 Clock Dividers

Clock dividers form the main part of the clock distribution module and are used to divide and synchronize clock domains. Var-
ious clock sources and divider modes may be used together to generate many frequencies with some control over the duty
cycle, as depicted in Figure 16-12.

Figure 16-12. Divider Implementation

Divide-by-4 Example (M=3)

3 2 1 0 3 2 1 0
Source Clock

Single Cycle Mode, Std. Phase

50% Mode, Std. Phase

Single Cycle Mode, Early Phase

50% Mode, Early Phase

Start (enable)

Divide-by-5 Example (M=4)

4 3 2 1 0 4 3 2 1 0
Source Clock

Single Cycle Mode, Std. Phase

50% Mode, Std. Phase 3 2

Single Cycle Mode, Early Phase

50% Mode, Early Phase

Start (enable)

The divider automatically reloads its divide count after Divider outputs can each be configured to give one of four
reaching the terminal count of zero. The divider count is set waveforms, as described below.
in the register CLKDIST_DCFG[0..7]_CFG0/1 for digital
dividers and CLKDIST_ACFG[0..3]_CFG0/1 for analog 16.4.3.1 Single Cycle Pulse Mode
dividers.The counter is driven by the clock source selected
In Single Cycle Pulse mode, by default, the divider gener-
from an 8-input mux, and the source selection is done in the
ates a single high pulse clock at either the cycle after the ter-
register CLKDIST_DCFG[0..7]_CFG2[2:0] for digital divid-
minal (zero) count or the half-count, and is otherwise low.
ers and CLKDIST_ACFG[0..7]_CFG2[2:0] for analog divid-
This produces an output clock that is high for one cycle of
ers. There are two divider output modes: single-cycle pulse
the input clock, resulting in a 1-of-N duty cycle clock. This is
and 50% duty cycle.
illustrated in Figure 16-12.
In either output mode, a divide value of 0 causes the divider
to be bypassed, giving a divide by 1. In this case, the input 16.4.3.2 50% Duty Cycle Mode
clock is passed to the output after a resync, if the sync In 50% Duty Cycle mode, the output produces a clock that
option is selected (see Clock Synchronization on page 158). has an approximate 50% duty cycle, depending on whether
For a load value of M, the total period of the output clock is the total number of counter cycles is even or odd. The 50%
N = M + 1 cycles (of the selected input clock). For example, clock rising edge occurs at the equivalent rising edge loca-
a load value of 4 gives a 5-cycle long output clock period. tion of the 1/N clock.

For a count of M, there are N = M + 1 input clock cycles in

the divider period. If M is odd, the total cycle count N is

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 157

Clocking System

even, allowing for a nominal 50% duty cycle. The clock is 16.4.4 Clock Synchronization
high for the first (M + 1)/2 cycles, and then goes low for the
remaining (M + 1)/2 cycles. All digital and analog divider outputs have an option to be
synchronized to the clk_sync_dig signals (CLKDIST_DCFG
If M is even, the total cycle count is odd, which means that [x]_CFG2[3] or CLKDIST_ACFG[x]_CFG2[3]), as shown in
the output clock is high longer than it is low (in standard Figure 16-13.
phase mode). Specifically, it is high for the first (M/2) + 1
cycles and then low for the remaining M/2 cycles. This is Each digital divider can be synchronized to the digital phase
illustrated in Figure 16-12 on page 157 for M = 3 and M = 4. mux output by setting the sync bit (CLKDIST_DCFG
[x]_CFG2[3]). The phase delay for the digital divider is
The CLKDIST_DCFG[x]_CFG2[4] or based on the phase shift field of Nonvolatile Latch (NVL) bits
CLKDIST_ACFG[x]_CFG2[4] bit in the configuration register DIG_PHS_DLY[3:0].
for each clock output can be set high to provide the 50%
duty cycle mode. An exact 50% duty cycle cannot be guar- Each of the four analog dividers can be synchronized to four
anteed in all cases, as it depends on the phase and fre- distinct phase shifted clocks. The phase on the respective
quency differences between the output clock and the sync analog dividers sync clocks can be provided in the
clock. PHASE_DLY field (CLKDIST_ACFG[x]_CFG3[3:0]). The
analog clocks become synchronized when the SYNC bit is
16.4.3.3 Early Phase Option set (CLKDIST_ACFG[x]_CFG2[3]). These divided clocks
synchronized to the analog clocks are called clk_a.
In addition to the two duty cycle choices, the outputs can be
phase shifted to either go high after the terminal count, or at The output of each clock tree provides for selection of one of
the half-period cycle. The default is referred to as Standard four output clocks:
phase, with the rising edge of the output after the terminal ■ Resynchronized clock – A clock running at a maximum
count. rate of clk_sync/2 is resynchronized by the phase
delayed clk_sync. This output is activated by setting the
The other option is referred to as the Early Phase because
sync bit.
the output can be considered to be shifted earlier in time to
an approximate count that is one-half of the divide value. ■ Phase delayed clk_sync (such as clk_sync_dig) –
The CLKDIST_DCFG_CFG2 [5] or CLKDIST_ACFG_CFG2 The clock tree runs at the same rate as clk_sync, but just
[5] bit in the configuration register for each clock output can outputs this clock with proper phase delay. Note that the
be set high to give the Early Phase mode, with the rising input clock source is ignored in this case. The output
edge near the half count. buffer is designed to match the final sync flop delay.
■ Unsynchronized divided clock – This produces an
Analog clock dividers are similar in their architecture to digi-
asynchronous clock, subject to the limitations described
tal dividers. However, they have an extra resync circuit to
in Asynchronous Clocks on page 160. This mode is
synchronize the analog clock to the digital domain clocks.
applicable when the sync bit is reset and the divider has
Therefore, each of the analog dividers also has an output
a nonzero divide value.
synchronized with the digital domain. This clock is synchro-
nized to the output of the digital phase mux. The digital syn- ■ Bypassed clock source – This routes the clock trees
chronized analog divider output is called clk_ad. This divider selected source to the output without going through the
is useful for clean communication between analog and digi- divider. This happens when the divider value is set to 0
tal domain. and sync bit is reset. As in the previous case, this also
produces an asynchronous clock.

Figure 16-13. Resync Option Diagram

clkout _ sel

clock source Divider D Q D Q D Q

clk_sync_d Clock
(or clk_sync_a0-a3) tree
output

Asynchronous clocks (limited use)

158 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Clocking System

16.4.5 Phase Selection and Control

To keep the environment quiet in the analog processing domain, a phase difference must exist between the analog and digital
system clocks. For this reason, in PSoC devices, a delay chain circuit provides taps to control the phase for the digital and
analog clocks. This delay chain provides up to a 10 ns phase adjustment with nominal steps of 0.5 ns. The phase shifter is
shown in Figure 16-14.

Figure 16-14. Phase Shifter

Clk_sync

Phase Delay Chain

1.5 ns 1 ns 0.5 ns 0 ns

Clk_sync_a0 Clk_sync_a2
Ana0 Ana2

CLKDIST_ACFG [0]_CFG3 [3:0]

CLKDIST_ACFG [2]_CFG3 [3:0]

Clk_sync_a1 Clk_sync_a3
Ana1 Ana3

CLKDIST_ACFG [1_CFG3 [3:0]

CLKDIST_ACFG [3]_CFG3 [3:0]

Digital
DIG_PHS_DLY [3:0]
Phase

Clk_sync_dig

The phase shifter consists of a chain of (nominally) 0.5 ns The clk_sync_dig phase shift selection must be applied at
buffers connected in cascade, with the output of each buffer power up through NVL settings, because changing its value
ported out of the circuit (21 outputs). The input to this chain can cause clock glitching; the clk_bus clock should not be
is clk_sync from the master clock divider. Five 5-bit muxes stopped for such a change. The analog phase shift selec-
select the sync clock to drive the resync circuits. One is tions can be made dynamically, because their output clocks
clk_sync_dig for the digital clock dividers (clk_bus and all can be disabled during any phase shift change.
digital clock dividers). The other four are independent delay
Outputs in the delay chain may have increased jitter. The
selections, one for each analog divider. The selected phase
expectation is that, in systems that need a low-jitter analog
value is defined in NVL bits for the digital and ACFG
clock, the undelayed output (first tap) is selected because it
[n]_CLKDIST_ACFG_CFG3}_PHASE_DLY for the analog
has the lowest jitter.
clocks.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 159

Clocking System

16.4.6 Divider Update 16.4.7 Power Gating of Clock Outputs

To allow for clean updates of the dividers while running, and Clock trees may be gated off (disabled). These gating sig-
to align the starting point for a group of dividers, a load nals come from the power manager, which contains a regis-
enable mechanism is provided. When a clock is running, it ter, {PM_ACT_CFG1, PM_ACT_CFG2*}, to allow user
automatically reloads its count value on the terminal count. selection of trees to enable or disable.
If a new value has been loaded during countdown of the
When a clock tree is disabled, its divider is reset so that
counter, this new value is loaded at the end of the count,
when reenabled, it reloads its count value. That is, the
and the next output clock period uses the new value.
divider counters do not pause and hold their counts when
Because the divide value is 16 bits, there is a possibility
disabled; they always start over with the latest configured
that, when updating this register with two 8-bit writes, the full
divide count when reenabled.
update might not complete when the terminal count occurs.
This would lead to an unexpected period being reloaded.
16.4.8 System Clock
To avoid this problem, a 16-bit shadow value (contained in
registers {CLKDIST_WRK0*} and {CLKDIST_WRK1*}) The System Clock is derived from the clk_sync_dig, which is
allows atomic loads of the dividers, so the 16-bit dividers a phase shifted version of clk_sync. The System Clock, also
can be safely updated dynamically (while running). The named clk_bus, is the clock that drives the PHUB and asso-
shadow value can be loaded with two separate 8-bit opera- ciated bus logic. This must be the fastest synchronous clock
tions. that outputs to the system. There is an option for a 16-bit
divider on the clk_sync_dig to generate the clk_bus
The mask registers ({CLKDIST_DMASK*} and CLKDIST_BCFG1/2. This also has the same resynchroniza-
{CLKDIST_AMASK*}) allow the user to select the target tion options as the other digital dividers.
dividers for this shadow value. When the load bit,
{CLKDIST_LD}_LOAD, register is written with a 1, all divid- 16.4.9 Asynchronous Clocks
ers selected in the mask registers have their period count
updated to the shadow value. (If the divider is not enabled, it Generally, all clocks used in the device must be derived
is safe to do partial writes directly to the divider period regis- from the same source, or synchronized to the main clk_sync
ter without using the shadow register.) clock. However there are possible exceptions:
■ A signal that comes on-chip routes through a GPIO,
To align clocks, the mask registers are used again, but this
routes to the UDB array, interacts only with self-con-
time, they select dividers for auto-alignment. When the
tained UDB functions, and routes out of the device.
{CLKDIST_LD}_SYNC_EN bit register is written with a 1, all
dividers selected in mask registers start (or re-start) ■ Similar to the previous, but the signal routes to the inter-
together. If the dividers are already enabled, they immedi- rupt controller instead of off-chip. The interrupt controller
ately reload and continue counting from this value. If they is able to handle arbitrarily phased events.
are not enabled, writing the SYNC_EN bit also sets any cor- ■ USB operation with the IMO locking to USB traffic.
responding enable bits in the divider enable registers Although unlikely, in this case, the rest of the device may
({PM_ACT_CFG*}), and the dividers begin counting. run off of a different clock, because the USB circuitry
contains its own clk_bus synchronous interface, even if
Writing a 1 to both of the {CLKDIST_LD}_LOAD and
its USB clock is not synchronous.
{CLKDIST_LD}_SYNC_EN bits can combine these two
operations. This causes all selected dividers to load the
shadow register value into their count value, to set all 16.5 Low Power Mode Operation
selected divider register enables (if not already enabled),
and then to start (or restart) with this setting. The sync load- During sleep modes, clock network outputs are gated off,
ing feature is not supported for clocks that are asynchro- and most clock sources are disabled automatically by the
nous to clk_bus. For instance, an external clock coming power manager. The low frequency (kHz) clocks may still
from the DSI that is not generated from clk_bus cannot have run, and various clocks are configured by the power man-
its divide value changed on the fly reliably. Glitching or tran- ager to support wakeup and buzz modes. Refer to the Low
sient improper divider loads may occur in this scenario. Power Modes chapter on page 169 for more details.

The system will not go into a sleep mode if either the MHz
crystal oscillator or the PLL are enabled. If either of these
clocks are enabled, the part will simply continue execution
without entering a sleep mode. Therefore, to enter a sleep

160 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Clocking System

mode when using either the MHz crystal oscillator or PLL,

the user must configure the part to run from the IMO and
then disable those clock sources. After that, the part may be
configured to enter a sleep mode. Wakeup will then occur
with the IMO as the main clock, and then the user may re-
activate alternate sources as desired. This is necessary for
fast wakeup and proper monitoring of PLL or crystal oscilla-
tor startup.

16.6 Clock Naming Summary

Table 16-2 lists clock signals and their descriptions.

Table 16-2. Clock Signals

Clock Signal Description

Synchronization clock from the Master clock mux used to

clk_sync
synchronize the dividers in the distribution

Clocks that are taken as input into the clock distribution

dsi_clkin
from DSI

clk_bus Bus clock for all peripherals

clk_d[0:7] Output clock from the seven digital dividers

Output clock from the four analog dividers synchronized to

clk_ad[0:3]
the digital domain clock

Output clock from the four analog dividers synchronized to

clk_a[0:3]
the analog synchronization clock

clk_usb Clock for USB block

clk_imo2x Output of the doubler in the IMO block

clk_imo IMO output clock

clk_ilo1k 1 kHz output from ILO

clk_ilo100k 100 kHz output from ILO

clk_ilo33k 33 kHz output from ILO

clk_eco_ kHz 32.768 kHz output from the kHz ECO

clk_eco_ MHz 4-33 MHz output of the MHz ECO

clk_pll PLL output

dsi_glb_div DSI global clock source to USB block

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 161

Clocking System

162 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 17. Power Supply and Monitoring

PSoC® 3 and PSoC® 5 devices have separate external analog and digital supply pins, labeled respectively Vdda and Vddd.
The devices have two internal 1.8V regulators that provide the digital (Vccd) and analog (Vcca) supplies for the internal core
logic. The output pins of the regulators (Vccd and Vcca) have very specific capacitor requirements that are listed in the data-
sheet.

17.1 Features
These regulators are available:
■ Analog regulator for the analog domain supply
■ Digital regulator for the digital domain supply
■ Sleep regulator for the sleep domain
■ I2C regulator for powering the I2C logic
■ Hibernate regulator for supplying keep alive power for state retention during hibernate mode

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 163

Power Supply and Monitoring

17.2 Block Diagram

The power system consists of separate analog, digital, and I/O supply pins, labeled Vdda, Vddd, and Vddiox, respectively. It
also includes two internal 1.8V regulators that provide the digital (Vccd) and analog (Vcca) supplies for the internal core logic.
The output pins of the regulators (Vccd and Vcca) and the Vddio pins must have capacitors connected as shown in
Figure 17-1. The power system also contains a sleep regulator, an I2C regulator, and a hibernate regulator.

Figure 17-1. Power Domain Block Diagram

Vddio2 1 µF Vddd

Vddio0
0.1 µF 0.1 µF

Vddd
Vccd

Vssd
Vddio2

I/O Supply I/ O Supply Vddio0

0.1 µF
I2C
Regulator

Sleep
Regulator
Digital
Vdda
Domain

Vdda

Analog Vcca
Vssd
Digital Regulator
0.1 µF
Regulators .
1 µF

Vssa
Analog
Domain

Hibernate
Regulator
Vddio1

Vddio3
Vccd

Vddd
Vssd

I/O Supply I/O Supply

0.1 µF 0.1 µF
0.1 µF
Vddio1 Vddd Vddio3

164 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Power Supply and Monitoring

17.3 How It Works

The regulators shown in Figure 17-1 on page 164 power the 17.3.1.2 Sleep Regulator
various domains of the device. All regulators, except the
The sleep regulator supplies power to these circuits during
analog regulator, draw their input power from the Vddd pin
the device sleep mode.
supply.
■ 32 kHz ECO
17.3.1 Regulator Summary ■ ILO
■ RTC Timer
Digital and analog regulators are active during the active or
alternate device active modes.They go into a low power ■ WDT
mode of operation in sleep or hibernate mode. The sleep ■ Central Timewheel (CTW)
and hibernate regulators are designed to fulfill power
■ Fast Timewheel (FTW)
requirements in the low power modes of the device.
17.3.1.3 Hibernate Regulator
17.3.1.1 Internal Regulators
The Hibernate regulator, whose output is called Keep Alive
For external supplies from 1.8 V to 5.5 V, regulators are
power (VpwrKA), powers domains of the device responsible
powered and the supply is provided through the Vddd / Vdda
for the state retention in hibernate mode. The VpwrKA is
pins. An external cap of ~1 µF is connected to the Vccd and
shorted to the active domain during active mode.
Vcca pins.

For the 1.71 V < Vcc < 1.89 V external supply, power up the
device with Vccd/Vcca pins. In this mode, short the Vddd pin
Vccd and short the Vdda pin to Vcca. The internal regulator
remains powered by default. After power up, disable the
regulators, using register PWRSYS. CR0 to reduce power
consumption.

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Power Supply and Monitoring

17.3.2 Boost Converter

PSoC devices also have a boost converter that accepts an input voltage supplied by a battery or other source and produces
a selectable, higher output voltage than the input voltage; the voltage is boosted.

The input voltage can be from various sources, such as a battery source or solar cells. The converter uses an external induc-
tor to boost the voltage. An external Schottky Diode must be connected between the pins IND and Vboost when boost voltage
is greater than 3.6V.

Figure 17-2 is an application diagram of the boost converter.

Figure 17-2. Boost Converter Application Diagram

Optional Schottky
Diode Required When
Vboost > 3.6V

10 µH
Vbat IND Vboost
Vdda
22 0.1 Vddd 0.1
µF µF 22 µF
PSoC µF
Vssb
Vssa
Vssd

The boost converter is enabled or disabled by the register on the rising and falling edge of the clock when the out-
bit BOOST_CR1 [3]. The device provides the option of put voltage is less than the programmed value. This is
changing the boost output voltage by writing into the register called automatic thump mode (ATM) and is enabled in
BOOST_CR0 [4:0]. By default, at startup the boost con- the BOOST_CR2[0].
verter is enabled and configured for a 1.8V output. If the In device sleep mode, all comparators and other circuits are
boost converter is not used, the pin Vbat should be tied to turned off, except for the band gap. This configuration inhib-
ground, and the IND pin should be left floating. its output; the boost output is High Z. Output voltage is the
voltage on the output load capacitor minus any loads being
17.3.2.1 Modes of Operation supplied by the capacitor during sleep time.
The boost converter has two main operating modes Over a prolonged period of time, output voltage decays. The
selected by the register BOOST_CR0 [6:5]; these are: microcontroller can manage power during periodic wakeups
■ Active – This is the normal mode of operation where the to implement a digital control loop and maintain the required
Boost Regulator actively generates a regulated output voltage during sleep mode.
voltage from the battery input. The switching frequency
is selected by BOOST_CR1 [1:0] and is not synchro- 17.3.2.2 Status Monitoring
nized to any other clock. The switching frequency selec-
Status monitoring for input and output voltages of the boost
tions are 2 MHz, 500 kHz, and 125 kHz, respectively.
converter are available in the status register BOOST_SR.
■ Standby – In this mode, only the band gap and boost
■ Output Voltage Monitor – The register
circuit comparators are active, while other systems are
BOOST_SR[4:0] gives a status of the output voltage
disabled, thus reducing power consumption of the boost
against the set nominal voltage output.
circuit itself. Output voltage is continuously monitored
and supervisory data provided in BOOST_SR [4:0]. This Bit 4: ov – Above overvoltage threshold (nominal + 50
mV).
register provides supervisory data against the output
voltage selected. Therefore, the processor can use the Bit 3: vhi – Above High regulation threshold (nominal
thump bit BOOST_CR0 [7] to switch the transistor ON +25 mV).
for a 1 µs pulse. Bit 2: vnom – Above Nominal threshold (nominal).
The converter can be configured to provide low power, Bit 1: vlo – Below Low regulation threshold (nominal to
low current regulation in the standby mode. A 32 kHz 25 mV).
clock is present which generates inductor boost pulses Bit 0: uv – Below undervoltage limit (nominal to 50 mV).

166 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Power Supply and Monitoring

17.3.3 Voltage Monitoring

The device has two circuits for detecting voltages that deviate from the selected threshold on the external digital / analog sup-
plies:
■ Low Voltage Interrupt (LVI) – The LVI circuit generates an interrupt when it detects a voltage below the set value.
■ High Voltage Interrupt (HVI) – The HVI circuit generates an interrupt when it detects a voltage above the set value.

The basic block diagram of voltage monitoring is shown in Figure 17-3.

Figure 17-3. Voltage Monitoring Block Diagram

Vdda Vddd

RESET_CR1[3]

Analog LVI (ALVI) AHVI Digital LVI (DLVI)

Triplevel = RESET_CR0[7:4] Triplevel = RESET_CR0[3:0]

RESET_CR1[1] RESET_CR1[2] RESET_CR1[0]

Interrupt Controller

17.3.3.1 Low Voltage Interrupt enabled. In addition, the real-time status of each LVI circuit
is available and captured in a real-time status register bit in
The LVI circuit generates an interrupt when it detects a volt-
RESET_SR2, so that the user can determine if an under /
age below the set value. These low voltage monitors are off
over voltage condition is still in effect.
by default, but the trip level for the LVI can be set in the reg-
ister RESET_CRO from 1.7V to 5.45V in steps of 250 mV. 17.3.3.2 High Voltage Interrupt
The LVI circuit has a persistent status register bit in The HVI circuit generates an interrupt when it detects a volt-
RESET_SR0 that is set until cleared by the user by reading age above the fixed, safe operating value of 5.75V on the
from the register or until a POR. This bit is set whenever the external analog supply. There is just one HVI for both analog
voltage goes below the set value. There is distinct monitor- and digital supplies. The selection between monitoring the
ing for low voltage on the analog and digital supply. The digital or analog supply is done by the RESET_CR1[3] bit.
analog low voltage interrupt (ALVI), enabled by These high voltage monitors are off by default, but this fea-
RESET_CR1[1] and RESET_CR0[7:4], sets the ALVI ture can be enabled in the register RESET_CR1 [2].
threshold. The digital low voltage interrupt (DLVI), enabled
by RESET_CR1[0] and RESET_CR0[3:0], sets the DLVI The HVI circuit has a persistent status register bit in
threshold. Apart from this, when the voltage monitoring is RESET_SR0 that is set until it is cleared by the user by
enabled and corresponding PRES bit is also enabled in reading or writing to the register or until a POR reset. This
RESET_CR3[7:6], the low voltage condition would trigger a bit is set when the analog voltage value goes beyond the
corresponding reset. threshold value.

The interrupt is generated only when the corresponding bit The interrupt is generated only when the corresponding bit
in register RESET_CR1 is set and corresponding bits in in the register RESET_CR1 [2] is unmasked. Even if the
RESET_CR3[7:6] cleared. Even if the interrupt output is not interrupt output is not used to generate a processor inter-
used to generate a processor interrupt, the status registers rupt, the status registers are updated by the circuit when-
are updated by the circuit whenever LVI functions are ever HVI functions are enabled. In addition the real-time

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 167

Power Supply and Monitoring

output of each HVI circuit is available and captured in a real- moment when voltage detection is being enabled. One way
time register bit in RESET_SR2, so that the user can deter- to achieve this is by disabling the LVD interrupt before
mine if an overvoltage condition is still in effect. enabling the voltage detection and enabling it after some
time, which avoids the potential glitch caused while
17.3.3.3 Processing a Low/High Voltage enabling.
Detect Interrupt
During Sleep mode, LVI and HVI circuits may be buzzed
Both low and high voltage interrupt circuits (LVI, HVI) cause (periodically activated). If an interrupt occurs during buzzing,
the same interrupt output signal, which is made available to the system will first go through its wakeup sequence; then
the Interrupt Controller. the interrupt is recognized and serviced.

Further execution of the interrupt depends on the enable

17.3.3.4 Reset on a Voltage Monitoring
status for the interrupt line in the Interrupt Controller. After
Interrupt
the interrupt occurs, the user code can interrogate status
registers to determine which LVI or HVI circuit detected an The ALVI and DLVI can be configured to directly reset the
under or over voltage condition. device by setting the corresponding bits in
RESET_CR3[7:6]. When this bit is set to 1 along with the
The actual interrupt output (LVD) is an OR function of the
RESET_CR1[0/1] set to 1, the corresponding lvi becomes
three persistent status register bits corresponding to LVI-D,
an additional reset source through the PRES reset path.
LVI-A, and HVI. Therefore, to clear the interrupt, the ISR
When this bit is cleared to 0 along with the RESET_CR1[0/
must clear these three register bits.
1] set to 1, the corresponding LVI is only used as an inter-
The LVI and HVI interrupts are prone to a glitch when they rupt source. If the RESET_CR1[0/1] is cleared to 0, the bit
are enabled. Exercise caution in the firmware to avoid any state (either a zero or a one) has no impact on the reset or
interrupt generated by the voltage detection circuitry at the interrupt functionality.

17.4 Register Summary

Table 17-1. Power Supply Register Summary
Register Function
PWRSYS_CR0 Regulator control
PWRSYS_CR1 Analog regulator control
BOOST_CR0 Boost Thump, voltage selection and mode select
BOOST_CR1 Boost enable and control
BOOST_CR2 Boost control
BOOST_CR3 Boost PWM duty cycle
BOOST_SR Boost status
RESET_CR0 LVI trip value setting
RESET_CR1 Voltage monitoring control
RESET_SR0 voltage monitoring status
RESET_SR2 Real-time voltage monitoring status

168 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 18. Low Power Modes

The PSoC® 3 and PSoC® 5 devices feature a set of four power modes with a goal of reducing the average power consump-
tion of the device.

18.1 Features
The PSoC 3 and PSoC 5 power mode features, in order of Sleep and Hibernate modes are used when processing is
decreasing power consumption, are: not necessary for an extended time. All subsystems are
■ Active automatically disabled in these two modes, regardless of the
settings in the active template register. Some subsystems
■ Alternative Active
have an additional available bit [PM_Avail_CRx] that can
■ Sleep mark a subsystem as unused and prevent it from waking
■ Hibernate back up. This reduces the power overhead of waking up the
part, in that not all subsystems are repowered.
Active and alternative active are the main processing
modes, and the list of enabled peripherals is programmable The allowable transitions between power modes are illus-
for each mode. trated in Figure 18-1.

Figure 18-1. State Diagram of Allowable Power Mode Transitions

Active

Manual
Sleep Hibernate

Alternate
Active

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 169

Low Power Modes

The various power modes reduce power by affecting the fol- Power savings, resume time, and supported wakeup
lowing resources: sources depend on the particular mode. The four global
■ Regulators for the digital and analog supply in the device power-reducing modes are described in Table 18-1 and are
listed in decreasing order of power consumption.
■ Clocks such as the IMO, ILO, and External crystal oscil-
lator (ECO32K, ECOM)
■ Central Processing Unit (CPU) and all other peripherals

Table 18-1. Power Consumption-Reducing Modes

Power Modes Description Entry Condition Wakeup Source Active Clocks Regulator
All regulators available.
Primary mode of opera-
Wakeup, reset, manual Digital and analog regula-
Active tion, all peripherals avail- Any (programmable)
register entry tors can be disabled if
able (programmable)
external regulation used.
Similar to Active mode, All regulators available.
Interrupt, PICU,
and is typically config-
CMP, RTC, CTW, Digital and analog regula-
Alternative Active ured to have lesser num- Manual register entry Any (programmable)
FTW, XRES_N, tors can be disabled if
ber of peripherals active
WDR, PPOR external regulation used.
to reduce power
Both digital and analog
PICU, CMP, RTC, regulators buzzed.
All subsystems automati-
Sleep Manual register entry CTW, XRES_N, ILO/ECO32K Digital and analog regula-
cally disabled
WDR, PPOR tors can be disabled if
external regulation used.
All subsystems automati-
cally disabled
Lowest power consum-
ing mode with all periph- PICU, CMP, Only hibernate regulator
Hibernate Manual register entry –
erals and internal XRES_N, active
regulators disabled
Configuration and mem-
ory contents retained

170 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Low Power Modes

18.2 Active Mode nate active mode. While in alternate active mode, if any
interrupt is generated, the device automatically transitions to
Active mode is the primary power mode of the PSoC device. active mode and begins executing the firmware in active
This mode provides the user with an option to use every mode.
possible subsystem/peripheral in the device. All of the
clocks in the device are available for use in this mode. 18.3.1 Entering Alternative Active Mode
Each power-controllable subsystem is enabled or disabled Alternative Active mode is entered by writing into
in Active mode, using the active power configuration tem- [PM_MODE_CSR]. Firmware must ensure the SPC Idle bit
plate bits [PM_ACT_CFGx registers]. This is a set of 14 reg- in the SPC_SR[1] register is '1' prior to writing to the
isters in which each bit is allocated to enable/disable a PM_MODE_CSR [2:0] register to ensure any SPC com-
distinct power controllable subsystem. When a subsystem is mands have completed.
disabled, the clocks are gated and/or analog bias currents
are reduced. The essential difference between Active and Alternative
Active mode is that the device cannot wake up from Sleep/
Firmware may be used to dynamically enable or disable Hibernate mode into the Alternative Active mode.
subsystems by setting or clearing bits in the active configu-
ration template. It is possible for the CPU to disable itself,
18.3.2 Exiting Alternative Active Mode
while the rest of the system remains in Active mode. The
CPU Active mode bit is not sticky; therefore the CPU is Any interrupt or writing the [PM_MODE_CSR] register can
always awakened whenever the system returns to Active return the system to Active mode.
mode.

18.4 Sleep Mode

18.2.1 Entering Active Mode
Sleep mode powers down the CPU and other internal cir-
Any wakeup event, any reset, or writing 0 into
cuitry to reduce power consumption. Supervisory services,
PM_MODE_CSR [2:0] register while in alternate active
such as the central timewheel, RTC, WDT, and periodic low
mode transitions the device into active mode. When a
voltage detection, remain available in this mode.
wakeup event occurs in alternate active/sleep/hibernate
mode, the global mode always returns to active and the When a wakeup event occurs, the system reactivates in a
CPU is automatically enabled, regardless of its template set- single phase and returns to Active mode. Both analog and
tings. Active mode is the default global power mode upon digital regulators are nominally disabled during Sleep mode.
boot. By default, regulators configured for internal regulation are
buzzed (periodically activated) to provide supervisory ser-
18.2.2 Exiting Active Mode vices and improve wakeup time by periodically charging the
external Vcca/Vccd capacitor.
A register write into PM_MODE_CSR [2:0] can transition to
another mode. Firmware must ensure the SPC Idle bit in the Buzz rates are programmable and can trade off between
SPC_SR[1] register is '1' prior to writing to the average current and wakeup time. It is not fatal if the capac-
PM_MODE_CSR [2:0] register to ensure any SPC com- itor discharges below the minimum voltage boundary listed
mands have completed. Any pending wakeup source pre- for Sleep mode. However, this discharge increases wake
vents the device from exiting Active mode. time, because the regulators must fully charge the capacitor
before it can enter Active mode. If the device is configured
for external regulation, the system returns to Active mode
18.3 Alternative Active Mode more quickly.
Alternative active mode is similar to active mode in most of
its functionality. Alternative active mode also has its own 18.4.1 Entering Sleep Mode
additional set of subsystem template bits Sleep mode is entered by writing the appropriate code into
[PM_STBY_CFGx], which determine whether a subsystem PM_MODE_CSR [2:0]. Firmware must ensure the SPC Idle
is enabled or disabled. This mode is made available for bit in the SPC_SR[1] register is '1' prior to writing to the
quick transitions between Active and an alternate low power PM_MODE_CSR [2:0] register to ensure any SPC com-
mode. mands have completed. Entry must be from a state where
For example, the user can write to the template bits to dis- the CPU is available (active). The system ignores any
able CPU and enable certain peripherals to operate in alter- request to enter sleep mode for the first 1 ms after POR.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 171

Low Power Modes

18.4.2 Exiting Sleep Mode 18.6 Timewheel

Only PICU interrupts, comparator wakeup, supervisory Timers and timewheels schedule events. They can be pro-
interrupts, or resets wake up the system. At wakeup, the grammed to generate periodic interrupts for timing or to
system activates all previously available domains from wake the system from a low power mode.
Active mode template and begins executing the firmware in
Active mode.
18.6.1 Central Timewheel (CTW)
The Central Timewheel (CTW) is a 1 kHz, free-running, 13-
18.5 Hibernate Mode bit counter clocked by the ILO. The CTW is always avail-
Hibernate mode consumes/dissipates the lowest power, and able, except in Hibernate mode and when the CPU is
nearly all internal functions are disabled. There is no buzz- stopped during Debug on-Chip (DoC) mode. The main func-
ing, and the external capacitors are permitted to discharge. tions of the CTW are:
The hibernate-regulator is always active to generate the ■ Buzzing during Sleep mode
keep-alive voltage (Vpwrka) used to retain the system state. ■ Waking up the device from a low power mode
Refer to 17.3.3 Voltage Monitoring on page 167.
■ Watchdog timer (WDT)
Configuration state and all memory contents are preserved ■ General timing purposes
in Hibernate mode. GPIOs configured as digital outputs
maintain their previous values, and pin interrupt settings are CTW settings are programmable, using
preserved. The voltage used to retain state is lower than the PM_TW_CFG1[3:0].
nominal core voltage. Although the CTW is free-running, separate settings are
In Hibernate mode, voltage is monitored with a lower degree used for the wakeup and watchdog timeouts. The CTW can
of precision than in the other power modes. The hibernate be programmed, using the {PM_TW_CFG2[2]} registers, to
mode has a higher probability of having soft errors. Hence wake the system periodically and optionally issue an inter-
for safety critical applications the MFGCFG.PWR- rupt by programming the bit {PM_TW_CFG2[3]}.
SYS.HIB.TR1[7] can be programmed to prevent hibernate
mode. When this bit is asserted, the command to enter 18.6.2 Fast Timewheel (FTW)
Hibernate will put the system into Sleep mode. This is The Fast Timewheel (FTW) is a 100 kHz, 5-bit counter
important in the case where there are chances of an acci- clocked by the ILO that can also be used to wake the sys-
dental entry into Hibernate and the Watchdog is disabled. tem. The FTW settings are programmable, using
PM_TW_CFG0 [4:0], and the counter automatically resets
18.5.1 Entering Hibernate Mode when the terminal count is reached. The FTW enables flexi-
Hibernate mode is entered by a write into PM_MODE_CSR ble, periodic wakeups of the CPU at a higher rate than the
[2:0]. Firmware must ensure the SPC Idle bit in the rate allowed using the CTW. To wake up on the FTW, the
SPC_SR[1] register is '1' prior to writing to the user must write into register PM_TW_CFG0 [0]. If the asso-
PM_MODE_CSR [2:0] register to ensure any SPC com- ciated FTW interrupt is enabled using PM_TW_CFG0 [1], an
mands have completed. The extremely low current hiber- interrupt is generated each time the terminal count is
nate regulator requires at least 1 ms to start up after a reset. reached.
During this time, the system ignores requests to enter Hiber-
nate mode.

18.5.2 Exiting Hibernate Mode

Return from Hibernate mode can occur only in response to a
PICU, comparator, or reset event. The digital, analog, and
sleep regulators are disabled in Hibernate mode. Upon
wakeup, the system activates all previously available
domains, unless the {PM_MODE_CFG1 [2]} field is set.

172 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Low Power Modes

18.7 Register List

Table 18-2. Low Power Modes Register List
Register Name Description

General Registers
PM_ACT_CFGx Active mode template
PM_STBY_CFGx Alternate Active mode template
PM_AVAIL_CRx Available settings for limited Active mode transition
PM_AVAIL_SRx Availability Status register
PM_MODE_CFG0 Not used
PM_MODE_CFG1 Interrupt and settings for low power modes
PM_MODE_CSR Power Mode Control and Status register
PM_INT_SR Power Mode Interrupt Status register
PM_TW_CFG0 Fast Timewheel (FTW) Configuration register
PM_TW_CFG1 Central Timewheel (CTW) Configuration register
PM_TW_CFG2 Configuration settings for CTW and FTW

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 173

Low Power Modes

174 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 19. Watchdog Timer

The Watchdog Timer (WDT) circuit automatically reboots the system in the event of an unexpected execution path. This timer
must be serviced periodically. If not, the CPU resets after a specified period of time. Once the WDT is enabled it cannot be
disabled except during a reset event. This is done to prevent any errant code from disabling the WDT reset function. To use
the WDT function, the user is required to enable the WDT function during their startup code.

19.1 Features
The WDT has the following features:
■ Protection settings to prevent accidental corruption of the WDT
■ Optionally-protected servicing (feeding) of the WDT
■ A configurable low power mode to reduce servicing requirements during sleep mode
■ A status bit for the watchdog event that shows the status even after a watchdog reset

19.2 Block Diagram

Figure 19-1 is a block diagram of the WDT circuit.

Figure 19-1. Watchdog Timer Circuit

2.048 sec - 3.072 sec

1024 Ticks

256 ms – 384 ms

128 Ticks
Watchdog Watchdog Reset
Counter
32 ms – 48 ms (3 Counts)

16 Ticks

4 ms – 6 ms PM_WDT_CFG [1:0]

ILO 2 Ticks
Clear Enable
1 kHz
Central Timewheel
PM_WDT_CR PM_WDT_CFG[4]

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 175

Watchdog Timer

19.3 How It Works accomplished by writing any value to the PM_WDT_CR

field. It is a good idea to service the WDT in a firmware main
The WDT circuit asserts a hardware reset to the device after loop, that is, not in an interrupt handler. If the WDT is ser-
a pre-programmed interval, unless it is periodically serviced viced in an interrupt handler, and the main loop code goes
in firmware. If an unexpected execution path is taken astray, the WDT may never generate a reset because the
through the code and the pre-programmed interval times interrupt may still be active, causing the interrupt handler to
out, the system is restarted. It can also restart the system continue to service the WDT.
from the CPU halt state.

The WDT timeout is between two and three programmable 19.3.3 Operation in Low Power Modes
tap periods, based on the free-running Central Timewheel. A configurable low power mode of the WDT reduces servic-
See the PSoC® 3 Registers TRM (Technical Reference ing requirements during sleep mode. The register
Manual) and the PSoC® 5 Registers TRM (Technical Refer- PM_WDT_CFG[6:5] governs the low power mode for the
ence Manual). WDT.
Each time the central timewheel crosses the programmed If the Watchdog-Timer (WDT) is enabled, these two bits
tap point, the Watchdog counter increments. When the define how the WDT behaves when the part enters sleep/
counter reaches three, a Watchdog reset is asserted, and idle/hibtimers (low power) mode. By default its left to 01, the
the counter is reset. When the WDT is serviced in software, system will automatically use the longest WDT interval when
the counter is reset to zero. Sleep/Idle/Hibtimers mode is entered - so SW isn't burdened
The time between servicing and the first tap crossing is usu- with waking just to feed the WDT. This is true regardless of
ally less than the complete tap period; therefore, software the value programmed in the wdt_interval register. Upon
should be programmed to service the WDT within two tap wakeup, the interval will remain at the highest setting until
periods. Actual WDT timeouts may differ slightly from nomi- the WDT is fed the first time by the user. A feeding at this
nal, caused by inaccuracy of the frequency of the ILO. point will cause the interval to automatically return to the
normal setting (value in wdt_interval). If this field is set to
NOCHANGE ('00'), the system does not change the interval
19.3.1 Enabling and Disabling the WDT
and does not feed the WDT when entering Sleep/Idle/Hib-
The WDT is enabled by setting the PM_WDT_CFG [4] regis- timers mode. If DISABLED (wdt_lpmode=11), the WDT is
ter bit. After this bit has been set, it cannot be cleared again turned off when Sleep/Idle/Hibtimers mode is entered and
except by a power reset event. This is done so that errant remains disabled until the first feeding by the user after
code cannot accidentally disable the Watchdog. Active mode is reentered.
Users must either reenable the Watchdog function at startup
after a reset occurs or include code to reenable the function 19.3.4 Watchdog Protection Settings
should a reset occur, allowing a dynamic choice whether to By use of the registers MLOGIC_SEG_CR and
enable the Watchdog. MLOGIC_SEG_CFG0, Watchdog timer registers are pro-
A status bit (RESET_SR0[3]) becomes set on the occur- tected from accidental corruption as follows:
rence of a Watchdog reset. This bit remains set until cleared ■ Clear, low-power enable, and Watchdog enable registers
by the user, by reading or writing to the register, or until a are protected as segment 0 as one-time system settings.
POR reset. All other resets leave this bit untouched. ■ The servicing of WDT clear is protected in segment 1 as
a reconfigurable system setting.
19.3.2 Setting the WDT Time Period and
See 22.3 Configuration Segment Protection on page 206.
Clearing the WDT
The user can select a tap from the central timewheel using
the register PM_WDT_CFG[1:0]. Based on the tap selected,
the WDT is timed at various periods, shown in Figure 19-1
on page 175. The Watchdog Timer counts until reaching
three counts, based on the tap from the central timewheel. If
the firmware does not clear the WDT before this time, a
Watchdog reset is initiated.

To prevent an automatic reset, the WDT must be periodi-

cally serviced by firmware. In the default mode, this is

176 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Watchdog Timer

19.4 Register List

Table 19-1. Reset Register List
Register Name Comments
PM_WDT_CFG Configuration register for Watchdog
PM_WDT_CR Watchdog clear
RESET_SRO Persistent Status register for Watchdog reset

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 177

Watchdog Timer

178 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 20. Reset

PSoC® 3 and PSoC® 5 architectures support several types of resets that allow error-free operation during power up for any
voltage ramping profile, user-supplied external or software resets, and recovery from errant code operation.

20.1 Reset Sources or software to indicate that a watchdog timer event

occurred. See the Watchdog Timer chapter on page 175.
The following is a description of reset sources. For power up
The RESET_SR0 [3] status bit becomes set on the occur-
supply monitoring, PSoC 3 and PSoC 5 devices support
rence of a watchdog reset. This bit remains set until cleared
POR (power on reset). They also support WRES (watchdog
by the user or until a POR reset. All other resets leave this
reset) for recovery from errant code, and SRES and
bit untouched. Except for the status bit, the watchdog reset
XRES_N for user-supplied software and external resets,
functions as all other system resets.
respectively. When a reset is initiated, all registers are
restored to their default states with minor exceptions, such
as some of the persistent status registers. 20.1.3 Software Initiated Reset
Software Initiated Reset (SRES) is a mechanism that allows
20.1.1 Power-on Reset a software-driven reset. The RESET_CR2 register forces a
device reset when a 1 is written into bit 0. This setting can
Power on Reset (POR) is provided primarily for a system
be made by firmware or with a DMA.
reset at power up. The IPOR will hold the device in reset
until all four voltages; Vdda, Vcca, Vddd, Vccd, are to data- The RESET_SR0 [5] status bit becomes set on the occur-
sheet specification. The POR activates automatically at rence of a software reset. This bit remains set until cleared
power up and consists of: by the user or until a POR reset.
■ An imprecise POR (IPOR) – is used to keep the device
in reset during initial power up of the device until the 20.1.4 External Reset
POR can be activated
External Reset (XRES_N) is a user-supplied reset that
■ A precision POR (PRES) – derived from a circuit cali- causes immediate system reset when asserted. XRES_N is
brated for a very accurate location of the POR trip point. available on a dedicated pin on some devices, as well as a
The power on RESET clears all the reset status registers shared GPIO pin P1[2] on all devices. The shared pin is
explained in 20.1.5 Identifying Reset Sources on available through a customer-programmed NV Latch setting
page 180. and supports low pin count parts that don't have a dedicated
XRES_N pin. This path is typically configured during the
20.1.2 Watchdog Reset boot phase immediately after power up. See the Nonvolatile
Latch chapter on page 121 for more details.
Watchdog Reset (WRES) detects errant code by causing a
reset if the watchdog timer is not cleared within the user- Either the dedicated pin or the GPIO pin, if configured, holds
specified time limit. The user must always set the WRES ini- the part in reset while held active. When the pin is released,
tialization code. This was done to allow the user to dynami- the part goes through a normal boot sequence. The external
cally choose whether or not to enable the watchdog timer. reset is active low, so that a low voltage (near ground) on
the XRES_N pin causes a reset.
This feature is enabled by setting the PM_WDT_CFG [4]
register bit. After this bit has been set, it cannot be cleared The RESET_SR0 [4] status bit becomes set on the occur-
again except by a reset event. When a watchdog timer rence of an XRES_N. This bit remains set until cleared by
event occurs, device reset occurs normally, but the watch- the user or until a POR.
dog timer enable bit is not cleared. This scheme allows the
watchdog timer enable bit to be a flag available to firmware

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 179

Reset

20.1.5 Identifying Reset Sources These two registers have specific status bits allocated for
the various RESET sources, except POR. The bits are set
When the device comes out of reset, it is beneficial to know on the occurrence of the corresponding reset, and remain
the cause of the reset. This is achieved in the device set after the reset, until the tstrst_en bit (bit 4) is cleared in
through the registers RESET_SR0 and RESET_SR1. All the Test Controller TC_TST_CR2 and they are cleared by
types of resets mentioned above set corresponding status the user or a POR reset.
bits in the RESET_SR0/1 registers. These persistent status
bits are only available when the tstrst_en bit (bit 4) is set in Therefore, all of the other RESET sources can be identified
the Test Controller TC_TST_CR2. after the reset. In the case of POR or the entire register is
cleared, indicating a power on reset.

20.2 Reset Diagram

Figure 20-1 is a simplified logic diagram of the RESET module. Any active source of reset will make the System RESET.

Figure 20-1. Logic Diagram of the RESET Module

POR

Hibernate

System
RESET

WRES_ENA
WRES
Hibernate

SRES
Hibernate

XRES

180 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Reset

Figure 20-2 is a diagram showing the operation of various RESETs with the change in Vdd/Vcc. The diagram also shows the
functioning of RESETs in a normal power up.

Figure 20-2. Resets Resulting from Various Reset Sources

Reset held until XRES is released

CPU State

Vddd/
Vdda Pin
Core
Vccd/Vcca Trip
Level

POR

XRES

HRES

WRES

SRES

Legend
Reset
Boot
User Code Runs

20.3 Reset Summary

All Reset sources and their triggers/effects are described in Table 20-1.

Table 20-1. Reset Sources, Triggers, and Effects

POR WRES SRES XRES_N
WDT not written in External XRES_N
Trigger Vccd <1.6V RESET_CR2[0] set
time window pin active
Yes (nonvolatile latch
Enable by Default? Yes No No
setting)
Block Power 50 µA <1 µA 0 0
Sleep Mode
Buzzed Not in Hibernate No Yes
Operation

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 181

Reset

20.4 Boot Process and Timing PSoC 3 life cycle consists of reset, boot, and user phases.
Figure 20-3 gives a brief view of these phases.
The boot process trims and configures the silicon to its ideal
state before the first line of the user code is executed. The
Figure 20-3. Boot Process

Reset Boot User Mode

Holds the part in reset Configuration loaded
until the operating from reserved area in CPU active. Start running code from
conditions are stable. NV Flash. Address 0.
Latch configuration Debug port acquire Loads configuration based on PSoC
happens here happens here creator generated code.

The process from supply voltage stabilization to user code gling of the external pins P1_0 and P1_1 and the configura-
entry is shown in the Figure 20.4. After the voltage is high tion finishes, the system moves into the user mode. Toggling
enough, the NVL Data load is initiated. The NVL load takes of P1_0 and P1_1 would imply a debug port acquire is being
care of loading configuration data stored in the NV Latches. attempted which would have to trigger a debug port entry.
These are configuration data that control the reset behavior
The process from supply voltage stabilization to user code
of the device. The maximum time for this NVL load is 10 s
entry is shown in the Figure 20.4. After the voltage is high
from the time of initiation. This resets the I/Os to the NVL
enough, the NVL Data load is initiated. The NVL load takes
drive mode settings as well as setting the other Manufactur-
care of loading configuration data stored in the NV Latches.
ing Configuration data for the device. At this point the device
These are configuration data that control the reset behavior
enters the reset state. The two types of NVL loads that hap-
of the device. The maximum time for this NVL load is 10 s
pen here are explained in section 20.4.1 Manufacturing
from the time of initiation. This resets the I/Os to the NVL
Configuration NV Latch.
drive mode settings as well as setting the other Manufactur-
If the external reset pin (XRES_N) is asserted low, the ing Configuration data for the device. At this point the device
device stays in the reset state. If the external reset pin enters the reset state. The two types of NVL loads that hap-
(XRES_N) is not asserted and all the voltages are at their pen here are explained in 20.4.1 Manufacturing Configura-
correct operating values it triggers the reset hold off circuitry tion NV Latch.
to begin bringing the device out of the reset state.
If the external reset pin (XRES_N) is asserted low, the
The IMO clock is then started in a fast IMO (FIMO) mode device stays in the reset state. If the external reset pin
which is a faster start up version of the IMO. The reset hold (XRES_N) is not asserted and all the voltages are at their
off counter continues to hold the device in reset until the correct operating values it triggers the reset hold off circuitry
other systems like band-gap and precision resets stabilize. to begin bringing the device out of the reset state.
The length of the hold off is approximately 20 s to allow
The IMO clock is then started in a fast IMO (FIMO) mode
enough time for these circuits to stabilize. If the band-gap or
which is a faster start up version of the IMO. The reset hold
precision reset blocks are not ready or there is a problem
off counter continues to hold the device in reset until the
with any of these devices stabilizing by the end of the hold-
other systems like band-gap and precision resets stabilize.
off counter, a fresh reset cycle is initiated and the hold-off
The length of the hold off is approximately 20 s to allow
counter is restarted. If there are no problems and the hold-
enough time for these circuits to stabilize. If the band-gap or
off counter completes and the device is released from reset.
precision reset blocks are not ready or there is a problem
After releasing from reset the IMO is switched to either 12 or with any of these devices stabilizing by the end of the hold-
48 MHz, the system bus clock is started, and the boot cycle off counter, a fresh reset cycle is initiated and the hold-off
begins. Until now the bus clock was fed from the FIMO counter is restarted. If there are no problems and the hold-
which has lesser accuracy compared to the IMO. Once the off counter completes and the device is released from reset.
reset is released it moves into the IMO which is more pre-
After releasing from reset the IMO is switched to either 12 or
cise. The boot phase is explained in section 20.4.3 User
48 MHz, the system bus clock is started, and the boot cycle
Mode. During this boot configuration time, if there is no tog-
begins. Until now the bus clock was fed from the FIMO

182 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Reset

which has lesser accuracy compared to the IMO. Once the gling of the external pins P1_0 and P1_1 and the configura-
reset is released it moves into the IMO which is more pre- tion finishes, the system moves into the user mode. Toggling
cise. The boot phase is explained in section 20.4.3 User of P1_0 and P1_1 would imply a debug port acquire is being
Mode. During this boot configuration time, if there is no tog- attempted which would have to trigger a debug port entry.

Figure 20-4. Power Up Reset Boot User Mode Cycle

Internal Reset Boot User Mode

Vddd / Vdda Pins

Core Vccd / Vcca

XRES_N

IPORXA

NVL Data NV Manufacturing Configuration Valid

reset_holdoff_counter count = 0 counting Counter expired

FIMO IMO, Either 12MHz or 48MHz

IMO

~20us
BG + Precision RESET READY

System_resets

clk_bus

Boot Configuration Data Configuration reads Configuration writes

Checksum Done

Boot Window Open

In this phase two types of NV Latches are loaded to set 20.4.1.1 Device Configuration NV Latch
reset states and trims in the device. The two types of the
Device Configuration is similar to Manufacturing Configura-
configuration are explained below. Both the configuration
tion NV in that it occurs while the device is in reset; however,
explained in sections 20.4.1 Manufacturing Configuration
it differs in that customers are selecting optional configura-
NV Latch and 20.4.1.1 Device Configuration NV Latch occur
tion settings not trim values for circuits. Manufacturing con-
simultaneously in the reset phase.
figuration and device configuration occur in parallel. One
such example of a device configuration is the NV latches
20.4.1 Manufacturing Configuration NV that determine the I/O drive modes during reset which deter-
Latch mine the reset state of the drive mode registers.
There are some circuits that must receive part specific trim
values before the device comes out of reset. Manufacturing 20.4.2 Boot Phase
NV latches provides these trim values. Conceptually an
Though many settings for the device are done using NV
example of such a circuit is the power on reset. This circuit
latch setting during the preboot process, there are other trim
is responsible for holding the device in reset until a safe sup-
values that require to be written during the boot process.
ply voltage is reached. The POR circuit requires a trim value
These values are stored in reserved space in the Flash
which would be stored in an NV latch. NV latch's output is
memory (I/O System chapter on page 187) and the boot
stable at approximately 1 V while the lowest operating volt-
process takes care of moving this data to the corresponding
age in the PSoC 3 platform is 1.71 V.
blocks. This loading of the configuration happens using the
DMA and the PHUB. A DMA channel fetches the configura-
tion bytes from the flash and places them in the SRAM. The
check sum block does a check sum to determine integrity.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 183

Reset

Once the data is verified it is then transferred using the DMA

to the corresponding configuration register. If the check sum
fails it would trigger a system reset.

Note that some circuits have mode dependent trim values,

for example the IMO's trim value depends on the speed set-
ting of the IMO. For circuits with mode dependent trim val-
ues the boot process loads the trim value that matches the
default mode. When the user's firmware or configuration
changes the mode, the firmware also retrieves the correct
trim value corresponding to the modes from the tables
stored in flash and writes them to the appropriate register.

The CPU halts until boot completes, therefore, you cannot

use the CPU to complete the boot process. The PHUB,
DMA, and a special checksum block are used for boot to
move the manufacturing configuration data from the flash to
the appropriate registers. These three blocks work together
to accomplish these objectives:
■ Minimize boot time, giving you the quickest path to firm-
ware execution
■ Provide a data integrity check on the manufacturing con-
figuration data
■ Provide flexibility in the order and addresses manufac-
turing configuration data is written to

Once the boot process is complete the device enters the

user mode where the user code starts executing.

20.4.3 User Mode

Once the boot phase is complete the device enters the User
mode to enable firmware code execution. This is where
code execution starts for the startup/configuration code
developed by PSoC Creator. Only after executing this part of
the PSoC Creator generated code does the code execution
reach the main().

184 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Reset

20.5 Register List

Table 20-2. Reset Register List
Register Name Comments
RESET_CR2
RESET_SR0 Persistent status bits for WRES, SRES, XRES_N, and so on
RESET_SR1 Persistent status bits for Segment reset, PRES
RESET_SR2 Real-time Reset Status

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 185

Reset

186 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 21. I/O System

The I/O system provides the interface between the CPU core and peripheral components to the outside world. The flexibility
of PSoC® devices and the capability of its I/O to route any signal to any pin greatly simplifies circuit design and board layout.
There are two types of I/O pins on every device, general purpose I/O (GPIO) and special I/O (SIO); those with USB provide a
third type. Both GPIO and SIO provide similar digital functionality. The primary differences are their analog capability and
drive strength. Devices that include USB also provide two USBIO pins that support specific USB functionality as well as spe-
cialized general purpose capability.

All I/O pins are available for use as digital inputs and outputs for both the CPU and digital peripherals. In addition, all I/O pins
can generate an interrupt. All GPIO pins can be used for analog input, CapSense®, and LCD segment drive, while SIO pins
are used for voltages in excess of Vdda and for programmable output voltages and input thresholds.

21.1 Features
The PSoC I/O system has these features, depending on the pin type.

Supported by both GPIO and SIO pins:

■ User programmable I/O state and drive mode on device reset
■ Flexible drive modes
■ Support level and edge interrupts on pin basis
■ Slew rate control
■ Supports CMOS and low voltage TTL input thresholds
■ Separate port read and write registers
■ Separate I/O supplies and voltages for up to four groups of I/O

Provided only on the GPIO pins:

■ Supports LCD drive
■ Supports CapSense
■ Supports JTAG interface
■ Analog input and output capability
■ 8 mA sink and 4 mA source current
■ Ports can be configured to support EMIF address and data

Provided only on SIO pins:

■ Hot swap capability (5V tolerance at any operating Vdd)
■ Single enable and differential input with programmable threshold
■ Regulated output voltage level option
■ Overvoltage tolerance up to 5.5V
■ Higher drive strength than GPIO
■ 25 mA sink and 4 mA source current

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 187

I/O System

USBIO features:
■ USB 2.0 compliant I/O
■ 25 mA source/24 mA sink current

21.2 Block Diagrams

Figure 21-1, Figure 21-2 on page 189, and Figure 21-3 on page 190 are block diagrams of three main categories of I/Os:
GPIO, SIO, and USBIO, respectively. Each diagram emphasizes the main blocks that drive the system, as well as the signals
and register settings that control the main blocks.

Figure 21-1. GPIO Block Diagram

Digital Input Path Naming Convention
PRT[x]CTL ‘x’ = Port Number
PRT[x]DBL_SYNC_IN ‘y’ = Pin Number

Digital System Input 1 Sync

0
PRT[x]PS

PICU[x]INTTYPE[y]
PICU[x]INTSTAT PRT[x]INP_DIS
Interrupt
Pin Interrupt signal Logic
PICU[x]SNAP

Digital Output Path

PRT[x]SLW
PRT[x]BYP
PRT[x]DR 0
Output from DSI
0 In Vio Vio
1
Sync 1
Vio
PRT[x]SYNC_OUT

PRT[x]DM2 Drive
Logic Slew
PRT[x]DM1 PIN
Cntl
PRT[x]DM0

Output Enable from DSI

PRT[x]BIE OE

Analog
1 0

1 0
CapSense Global Control 1
PRT[x]_CAPS_SEL[y] Switches
PRT[x]AG
Analog Global Bus
PRT[x]AMUX
Analog Mux Bus

LCD

Display Data
PRT[x]LCD_COM_SEG Logic and
PRT[x]LCD_EN MUX

LCD Bias Bus 5

188 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 I/O System

Figure 21-2. SIO Block Diagram

Digital Input Path Naming Convention

‘x’ = Port Number
PRT[x]SIO_HYST_EN
‘y’ = Pin Number
PRT[x]DBL_SYNC_IN

Digital System Input 1 Sync

0
PRT[x]PS

Input Buffer Disable

PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Interrupt
Pin Interrupt signal Logic
PICU[x]SNAP

PRT[x]SIO_DIFF
Reference
PRT[x]SIO_CFG Generator

Digital Output Path

Driver
PRT[x]SLW Vhigh
PRT[x]BYP
PRT[x]DR 0
Output from DSI In
0
1
Sync 1

PRT[x]SYNC_OUT
PRT[x]DM2 Drive
Logic Slew
PRT[x]DM1 PIN
Cntl
PRT[x]DM0

Output Enable from DSI

PRT[x]BIE OE

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 189

I/O System

Figure 21-3. USBIO Block Diagram

Digital Input Path Naming Convention

‘x’ = Port Number
‘y’ = Pin Number
USB Receiver Circuitry

PRT[x]DBL_SYNC_IN

Digital System Input 1 Sync

0
USBIO_CR1[0,1]

PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Interrupt
Pin Interrupt Signal Logic
PICU[x]SNAP

Digital Output Path

D+ pin only
USBIO_CR1[7] USB or I/O
USB SIE Control for USB Mode Vio Vio 3.3V Vio

USBIO_CR1[4,5] 0
In
Digital System Output 1
Drive
PRT[x]BYP 5k 1.5k
Logic
PIN
USBIO_CR1[2] D+ 1.5k
USBIO_CR1[3] D+D- 5k
USBIO_CR1[6] Open Drain

21.3 How It Works

PSoC I/Os provide: The I/Os are arranged into ports, with up to eight pins per
■ Digital input sensing port. Some of the I/O pins are multiplexed with special func-
tions (USB, debug port, crystal oscillator). Special functions
■ Digital output drive
are enabled using control registers associated with the spe-
■ Pin interrupts cific functions. For example, the Crystal Oscillator control
■ Connectivity for analog inputs and outputs register enables the crystal oscillator function for the I/O pin
■ Connectivity for LCD segment drive and EMIF multiplexed with the crystal oscillator function.

■ Access to internal peripherals:

21.3.1 Usage Modes and Configuration
❐ Directly for defined ports
❐ Through the Universal Digital Blocks (UDB) via the Because of the variety of I/O capabilities, it is necessary to
Digital System Interconnect (DSI) understand the modes thoroughly and the configuration for
each function.

190 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 I/O System

21.3.2 I/O Drive Modes The I/O pin drive state is based on the port data register
value (DR) or on a DSI signal, if bypass mode is selected.
Each GPIO and SIO pin is individually configurable into one The actual I/O pin voltage is determined by a combination of
of the eight drive modes listed in Table 21-1 and shown in the DR value, the selected drive mode, and the load at the
Figure 21-4, which depicts a simplified pin view based on pin. The state of the pin can be read from the Port Status
each of the eight drive modes. register (PS) or routed to a DSI signal, or both. Three config-
uration bits are used for each pin (DM [2:0]) and set in the
PRTxDM [2:0] registers.

Table 21-1. I/O Drive Modes

Mode PRTxDM2 PRTxDM1 PRTxDM0
Drive Mode Data = 1 Data = 0
Number DM2 DM1 DM0
0 High Impedance Analog 0 0 0 High Z High Z
1 High Impedance Digital 0 0 1 High Z High Z
2 Resistive Pull Up 0 1 0 Res 1 (5k) Strong 0
3 Resistive Pull Down 0 1 1 Strong 1 Res 0 (5k)
4 Open Drain, Drives Low 1 0 0 High Z Strong 0
5 Open Drain, Drives High 1 0 1 Strong 1 High Z
6 Strong Drive 1 1 0 Strong 1 Strong 0
7 Resistive Pull Up and Down 1 1 1 Res 1 (5k) Res 0 (5k)

Figure 21-4. I/O Drive Mode Diagram

Vio Vio

DR DR DR DR
Pin Pin Pin Pin
PS PS PS PS

0. High Impedance 1. High Impedance 2. Resistive 3. Resistive

Analog Digital Pull Up Pull Down

Vio Vio Vio

DR DR DR DR
Pin Pin Pin Pin
PS PS PS PS

4. Open Drain, 5. Open Drain, 6. Strong Drive 7. Resistive

Drives Low Drives High Pull Up & Down

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 191

I/O System

21.3.2.1 Drive Mode on Reset Drive mode, a 0 must be written to that pin’s Data Register
bit.
The factory drive mode default is high impedance analog
mode, which is appropriate for most designs. The Drive 21.3.2.5 Open Drain, Drives High and Drives
Mode on Reset feature allows the user to change the factory
Low
default to any of the four listed drive modes if the application
requires faster configuration to low or high logic levels. The Open Drain modes provide high impedance in one of the
Reset drive mode is set at POR release. The Drive Mode on data states and strong drive in the other. Pins are used for
Reset setting is a port wide setting and is not set per pin. digital input and output in these modes. A common applica-
Each pin is individually configured during the device configu- tion for these modes is driving I2C bus signal lines.
ration step after POR release; this setting overwrites the
reset drive mode. The Resistive Pull Up Drive Mode on 21.3.2.6 Strong Drive
Reset also sets the Port Data Register to 0xFF to ensure the The Strong Drive mode is the standard digital output mode
port is pulled up; all other modes leave the Data Register for pins; it provides a strong CMOS output drive in both high
0x00. and low states. Strong drive mode pins must not be used as
■ High impedance analog inputs under normal circumstances. This mode is often used
■ High impedance digital to drive digital output signals or external FETs.
■ Resistive pull up
21.3.2.7 Resistive Pull Up and Pull Down
■ Resistive pull down
The Resistive Pull Up and Pull Down mode is a single mode
Refer to the Nonvolatile Latch chapter on page 121 for and is similar to the Resistive Pull Up and Resistive Pull
details. Down modes, except that, in the single mode, the pin is
always in series with a resistor. The high data state is pull up
21.3.2.2 High Impedance Analog while the low data state is pull down. This mode is used
High Impedance Analog mode is the default reset state; when the bus is driven by other signals that may cause
both output driver and digital input buffer are turned off. This shorts.
state prevents a floating voltage from causing a current to
flow into the I/O digital input buffer. This drive mode is rec- 21.3.3 Slew Rate Control
ommended for pins that are floating or that support an ana-
GPIO and SIO pins have fast and slow output slew rate
log voltage. High impedance analog pins cannot be used for
options for strong drive modes – not resistive drive modes.
digital inputs. Reading the pin state register returns a 0x00
The fast slew rate is for signals between 1 MHz and 33
regardless of the data register value.
MHz.
To achieve the lowest device current in sleep modes, all I/
Because it results in reduced EMI, the slow option is recom-
Os must either be configured to the high impedance analog
mended for signals that are not speed critical – generally
mode, or they must have their pins driven to a power supply
less than 1 MHz. Slew rate is individually configurable for
rail (ground) by the PSoC device or by external circuitry.
each pin and is set by the PRTxSLW registers.
21.3.2.3 High Impedance Digital
21.3.4 Digital I/O Controlled by Port
High Impedance Digital mode is the standard high imped-
Register
ance (High Z) state recommended for digital inputs. In this
state, the input buffer is enabled for digital signal input. The Port Control registers (see Table 21-2 on page 193)
have separate configuration bit for each port pins. In addi-
21.3.2.4 Resistive Pull Up or Resistive Pull tion to port control registers, the device also provides regis-
Down ter for port-wide and pin wise configuration.

Resistive modes provide a series resistance in one of the The port wide configuration register writes the same config-
data states and strong drive in the other. Pins can be used uration for all the port pins in a single write. This is useful to
for digital input and output in these modes. Interfacing to configure all the port pins to a specific configuration.
mechanical switches is a common application for these
The pin wise configuration register writes to all configuration
modes. If a pull up is needed with the Resistive Pull Up
bits for a specific I/O pin in a single write. This is useful to
Drive mode, a 1 must be written to that pin’s Data Register
configure individual port pins to a specific configuration.
bit. If a pull down is required with the Resistive Pull Down

192 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 I/O System

Outputs are driven from the CPU by writing to the port data 21.3.4.2 Pin Wise Configuration Register
registers (PRTx_DR) Digital inputs are read by the CPU Alias
through the pin state registers (PRTx_PS}).
The port pin configuration registers (PRTxPC0 through
21.3.4.1 Port Configuration Registers PRTxPC7) access several configuration or status bits of a
single I/O port pin at once, as shown in Figure 21-5 on
Table 21-2 lists port control registers. page 193.
Table 21-2. Functional Registers Accessed through Pin and Figure 21-5 shows an example of a read from
Port Configuration Registers {PRT*_PC[4]}. Bit four of the port control registers associ-
Address Description ated with the port configuration register is read and driven
A bit set in this register connects the corresponding
onto the data bus.
PRT[0..11]_BYP port pin to the Digital System Interconnect (DSI),
and disconnects it from the DR register.
Each bit controls the output edge rate of the corre-
PRT[0..11]_SLW sponding port pin – fast edge rate mode (Slew=0) or
slow edge rate mode (Slew=1)
Each bit set controls the bidirectional mode of the
corresponding port pin.
PRT[0..11]_BIE
0 = Output always enabled
1 = Output Enable controlled by DSI input
This register reads the logical pin state for the cor-
PRT[0..11]_PS
responding GPIO port.
The combined value of these registers –
PRTx_DM2, PRTx_DM1, and PRTx_DM0 – deter-
PRT[0..11]_DM[0..2]
mines the unique drive mode of each pin in a GPIO
port.
Data written to this register specifies the high
PRT[0..11]_DR (Data=1) or low (Data=0) state for the GPIO pin at
each bit location of the selected port.

Figure 21-5. Effect of a Read of the Pin Configuration Register {PRT*_PC[4]}

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Data Register Bypass – (Port 3 BYP) Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

Slow Slew Rate – (Port 3 SLW) Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

Bidirectional Enable – (Port 3 BIE) Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

Pin Input State – (Port 3 PS) Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

Drive Mode 2 – (Port 3 DM2) Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

Drive Mode 1 – (Port 3 DM1) Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

Drive Mode 0 – (Port 3 DM0) Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

Data Output – (Port 3 DR) Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

BYP SLW BIE PS DM2 DM1 DM0 DR

Port Pin Configuration – Port 3, Pin 2

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 193

I/O System

21.3.4.3 Port Wide Configuration Register access during normal operation, while the PHUB bus pro-
Alias vides full control to all I/O registers.

The Port Configuration Register accesses several available As shown in Table 21-3, SFR registers contain three regis-
configuration registers on a port-wide basis with a single bit ters for each I/O port.
write.
Table 21-3. SFR Registers
This register PRT*_PRT aliases a subset of the configura-
Addressa Description
tion registers, allowing the user to configure a complete port
Sets the output data state for port x with
in a single write. SFR_USER_GPIOx respect to setting in SFR_USER_GPIOx_SEL
register
Figure 21-6. {PRT*.PRT} Write Example
Sets output for each bit in port x register to
SFR_USER_GPIOx_SEL
corresponding pin in port x
Write
Data bus Read only register; contains pin state value of
SFR_USER_GPIRDx
port x
a. x is port number and includes ports 0-6, 12, and 15
write 8
PRT[x].PRT
bit [1] Table 21-4 shows three examples illustrating results from
1 setting selected bits in the SFR register.

PRT[x].DM0 7 0 Table 21-4. SFR Register Bit Examples

bit [2] Example Settings Result

1 For Port 0, SFR_USER_GPIO0_SEL, bit0=1;

Port0 [0] =1
Bit 0 SFR_USER_GPIO0, bit 0=1

PRT[x].DM1 7 0 For Port 0, SFR_USER_GPIO0_SEL, bit0=1;

Port0 [0] =0
Bit 0 SFR_USER_GPIO0, bit 0=0
bit [3]
For Port 0, SFR_USER_GPIO0_SEL, bit0=0; SFR does not set
1 Bit 0 SFR_USER_GPIO0, bit 0=1 corresponding GPIO

PRT[x].DM2 7 0 For more information, see the 8051 Core chapter on

bit [5] page 37.

1
21.3.6 Digital I/O Controlled Through DSI
PRT[x].BIE 7 0 GPIO, USBIO, and SIO pins are connected to the internal
bit [6] peripheral blocks through the UDB via the digital system
1 interconnect (DSI). Any peripheral connected to the UDB
can be connected to any I/O pin through the DSI.
PRT[x].SLW 7 0
Each port has 20 unique connections to the UDB through
bit [7]
DSI: eight inputs, eight outputs, and four output control sig-
1 nals.

PRT[x].BYP 7 0 21.3.6.1 DSI Output

The bypass register {PRTx_BYP} selects either the selected
DSI output signal or the data register (PRTx_DR) to drive
21.3.5 SFR to GPIO the port pin.
All I/Os allow 8051 Special Function Register (SFR) direct
Mapping of the DSI signal to the output pin is illustrated in
read/write access to the data register and read access to the
Figure 21-7 on page 195.
pin state register. This feature gives the user another
method to read from and write to the ports. Together, output select registers PRTx_OUT_SEL1 and
PRTx_OUT_SEL0 select the DSI output signal to drive the
I/O ports are linked to the CPU through the PHUB. In addi-
corresponding output port pin.
tion, all of the I/O ports are linked to the SFR bus. Each of
the I/O ports supports two interfaces: the SFR bus and the
PHUB bus. The SFR bus allows for the most efficient I/O

194 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 I/O System

Figure 21-7. Digital System Input to Pad Selection

PRT[x]_OUT_SEL1[0], PRT[x]_OUT_SEL0[0]

PRT[x]_OUT_SEL1[7], PRT[x]_OUT_SEL0[7]
PRT[x]_OUT_SEL1[1], PRT[x]_OUT_SEL0[1]

PRT[x]_OUT_SEL1[6], PRT[x]_OUT_SEL0[6]
PRT[x]_OUT_SEL1[2], PRT[x]_OUT_SEL0[2]

PRT[x]_OUT_SEL1[5], PRT[x]_OUT_SEL0[5]
PRT[x]_OUT_SEL1[3], PRT[x]_OUT_SEL0[3]

PRT[x].OUT_SEL1[4],PRT[x].OUT_SEL0[4]
Lower Upper
Nibble Nibble
DSI IN DSI IN

DSI[0]
DSI[1]
DSI[2]
DSI[3]

DSI[4]
DSI[5]
DSI[6]
DSI[7]
PRT[x]_DR[7:0]

Port Logic Control

PRT[x]_BYP[7:0]

in in in in in in in in
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO

Px[0] Px[1] Px[2] Px[3] Px[4] Px[5] Px[6] Px[7]

21.3.6.2 DSI Input Together, dynamic output enable select registers

PRTx_OE_SEL1 and PRTx_OE_SEL0 select the DSI con-
The port pin input is directly connected to the UDB array
trol signal for each port pin.
through DSI for routing the input to various internal periph-
eral blocks. The control for these port inputs are at the DSI
inputs. See the Universal Digital Blocks (UDBs) chapter on
page 213 for port-to-DSI connections.

21.3.6.3 DSI for Output Enable Control

High-speed bidirectional capability is provided through the
{PRT*_BIE} register. When this mode is enabled and the
auxiliary control signal is high, the I/O pin immediately goes
into a High Z output drive state with input buffer enabled.
When this signal is low (or returns low), the I/O pin assumes
the pin state configured through the {PRT*_DM[2]},
{PRT*_DM[1]}, and {PRT*_DM[0]} registers.This allows fast
turnaround of the I/O pin. Four DSI control signals are avail-
able for dynamic drive control of the pins. Mapping of the
DSI control signal to port pin output enable is shown in
Figure 21-8 on page 196.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 195

I/O System

Figure 21-8. Mapping of DSI Control Signal to Port Pin Output Enable

Dynamic
Output Control

PRT[x]_OE_SEL1[0], PRT[x]_OE_SEL0[0]
PRT[x]_OE_SEL1[1], PRT[x]_OE_SEL0[1]
PRT[x]_OE_SEL1[2], PRT[x]_OE_SEL0[2]

from UDB
PRT[x]_OE_SEL1[3], PRT[x]_OE_SEL0[3]
PRT[x]_OE_SEL1[4], PRT[x]_OE_SEL0[4]
PRT[x]_OE_SEL1[5], PRT[x]_OE_SEL0[5]
PRT[x]_OE_SEL1[6], PRT[x]_OE_SEL0[6]
PRT[x]_OE_SEL1[7], PRT[x]_OE_SEL0[7]

dsi_oe[0]
dsi_oe[1]
dsi_oe[2]
dsi_oe[3]
PORT LOGIC
CONTROL

PRT[x]_BIE[7:0]

oe oe oe oe oe oe oe oe
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO

Px[0] Px[1] Px[2] Px[3] Px[4] Px[5] Px[6] Px[7]

21.3.7 Analog I/O For analog I/O pins, the drive mode should be configured to
High Z Analog in most situations, which disables the input
The only way that analog signals can pass to and from the buffer. The input buffer can also be disabled using the port
PSoC core is through GPIO. input disable (PRTx_INP_DIS) register. The buffer should
To connect a pin to an internal analog resource through remain enabled to allow simultaneous use of the pin as a
analog global bus or analog mux line, each GPIO connects digital input and analog input or output.
to one of the analog global lines and to one of the analog
mux lines. The switches that connect the I/O pin to Analog 21.3.8 LCD Drive
global lines and analog mux line are configured by the
All GPIO pins can be configured for LCD drive capabilities.
{PRT*_AG} and {PRT*_AMUX} registers.
{PRT*_LCD_EN} registers are used to enable individual
Refer to the Analog Routing chapter on page 359 for a pins for LCD drive. {PRT*_LCD_COM_SEG} registers are
description of the analog global network configuration. used to select whether a pin is set as a common or segment
Selected pins provide direct connections to specific analog drive pin.
features, such as DACs or uncommitted opamps.

196 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 I/O System

In LCD mode, the GPIO pins are configured into a High Z Figure 21-9. SIO Configuration Diagram
output mode, allowing the LCD drivers to control the pin
SIO Pair
state.

21.3.9 CapSense SIO

All GPIO pins can be used to create CapSense buttons and PRT[x]SIO_DIFF
sliders. The primary analog bus for CapSense is the AMUX-
BUS, which has two nets (AMUXBUSL and AMUXBUSR) ANALOG Reference
Global Generator
for two simultaneous sensing operations. These can also be
shorted to form a single net that connects to all GPIOs. See
PRT[x]SIO_CFG
the CapSense® chapter on page 397 for more information.
SIO
21.3.10 External Memory Interface (EMIF)
The EMIF uses the port interface and the UDB to connect to
external memory. When in EMIF mode, the ports directly
21.3.11.2 Adjustable Input Level
pass to the pads the address and data out from the PHUB.
Data reads from the EMIF pass through the port to the SIO pins support a differential input mode with programma-
PHUB. See the EMIF chapter on page 133 for more infor- ble thresholds. The SIO pair input buffer voltage levels are
mation. set by the vref_sel and vtrip_sel bits of the
{PRT*_SIO_DIFF} register. See the following table.
21.3.11 SIO Functions and Features Table 21-6. SIO Differential Input Buffer Reference Voltage
GPIO and SIO provide similar digital functionality. The pri- Selection
mary differences are in their analog capability and drive vref_sel[y] vtrip_sel[y] Mode Description
strength. This section describes adjustable input and output 0 0 0.5 × vcc_io
level and hot swap features that are available only with SIO.
0 1 0.4 × vcc_io
1 0 0.5 × vohref
21.3.11.1 Regulated Output Level
1 1 vohref
SIO port pins support the ability to provide a regulated high
output level. This can be useful for interfacing to external
signals with voltages lower than the SIO Vddio. This regu-
lated output sets the Voh for the SIO pair. The SIO are
grouped into pairs. Each pair shares the same reference
generator, thus the regulated output level applies for both
pins.

Configuration is provided for each SIO pair through the

{PRT*_SIO_CFG} registers, as shown in the following table.

Table 21-5. SIO Input and Output Configuration

vreg_en[y] ibuf_sel[y] Mode Description
Single Ended Input Buffer
0 0
Non-Regulated Output Buffer
Differential Input Buffer
0 1
Non-Regulated Output Buffer
Single Ended Input Buffer
1 0
Regulated Output Buffer
Differential Input Buffer
1 1
Regulated Output Buffer

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 197

I/O System

Figure 21-10. SIO Reference Voltage

vcc_io vcc_io

vreg_en | (ibuf_sel*vref_sel) ibuf_sel *(vohref | vref_sel)

vohref
(From Analog Global)
voutref
5 (To Output Buffer)
R
0
R
R
1
4
R 0
R vtrip_sel
vinref
vgnd 1 (To Input Buffer)
0
vref_sel
1
vtrip_sel

21.3.11.3 Hot Swap System reset (XRES_N, active low, resistive pull up) func-
tionality is supported on either the dedicated XRES_N pin or
SIO pins support hot swap capability. It is possible to con-
the P1[2] GPIO (since the XRES_N pin is not bonded on the
nect to another system without loading the signals con-
48-pin package). The IEEE 1149.1 JTAG TAP five pin inter-
nected to the SIO pins and without applying power to the
face may be enabled on the P1[0:1,3:5] pins.
PSoC device.
Serial wire debug is supported over the USBIO pins
The unpowered PSoC device can maintain a high imped-
(P15[6:7]) or the same pins as TMS / TCK (P1[0:1]). Analog
ance load to the external device while preventing the PSoC
function fixed pin assignments include two pairs of VIDAC
device from being powered through a GPIO pin’s protection
outputs to support high-current mode, two VREF inputs, and
diode.
four sets of analog output buffer pins. The “left side” VIDAC
and analog buffer pins are assigned to port 0 and are avail-
21.3.12 Special Functionality able on all package options. The “right side” VIDAC and lin-
Special purpose capability may uniquely exist on some pins ear buffer pins are assigned to port 3 and are available on
such as: all package options except the 48-pin package.

■ 4 to 25 MHz crystal input and output

■ 32 kHz crystal input and output
■ Test modes
■ I2C
■ SPI
■ CAN
■ USB

Special functions and peripherals such as I2C, crystal oscil-

lators, USB, XRES_N, JTAG TAP, SWD, high-current DAC
outputs, VREF inputs, and high drive analog output buffers
have fixed pin assignments.

The I2C block supports three pin assignment options: SIO

pin pair P12[0:1], SIO pin pair P12[4:5], or any GPIO / SIO
pin pair routed via the DSI.

198 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 I/O System

Table 21-7. Fixed Pin Assignments

Pad
Function Signal Name Pad # Pad Type TQPF 100 QFN 68 SSOP 48 Comment
Name
SCL 4 P12[4] SIO 4 3 -
SIO pair on Vio2
SDA 5 P12[5] SIO 5 4 -
I2C
SCL 61 P12[0] SIO 53 38 42
SIO pair on Vio3
SDA 62 P12[1] SIO 54 39 43
Xo 49 P15[0] GPIO / Xtal 42 27 39
MHz ECO
Xi 50 P15[1] GPIO / Xtal 43 28 40
Xo 62 P15[2] GPIO / Xtal 55 40 44
32 kHz ECO
Xi 63 P15[3] GPIO / Xtal 56 41 45
D+ 39 P15[6] USBIO 35 22 34
FS USB
D- 40 P15[7] USBIO 36 23 35
XRES_
19 XRES_N 15 10 - Fixed function XRES_N / TSTRST_N pin
N
XRES_N XRES_N
XRES_N / TSTRST_N option for 48-pin pack-
26 P1[2] GPIO 22 13 27
age
TMS 24 P1[0] GPIO 20 11 25
TCK 25 P1[1] GPIO 21 12 26
IEEE 1149.1
TDO 26 P1[3] GPIO 23 14 28
JTAG TAP
TDI 28 P1[4] GPIO 24 15 29
nTRST 29 P1[5] GPIO 25 16 30
24 P1[0] GPIO 20 11 25 SWD on GPIO pins option
SWDIO
39 P15[6] USBIO 35 22 34 SWD on USB pins option
Serial Wire
25 P1[1] GPIO 21 12 26 SWD on GPIO pins option
Debug SWDCK
40 P15[7] USBIO 36 23 35 SWD on USB pins option
SWO 27 P1[3] GPIO 23 14 28
Abuffer0L 82 P0[6] GPIO 78 55 10

VIDAC High Cur- Abuffer1L 83 P0[7] GPIO 79 56 11

rent Output Abuffer0R 51 P3[0] GPIO 44 29 -
Abuffer1R 52 P3[1] GPIO 45 30 -
Extref0 78 P0[3] GPIO 74 51 6
External Vref
Extref1 53 P3[2] GPIO 46 31 -
Abuf0+ 77 P0[2] GPIO 73 50 5
Abuf0- 78 P0[3] GPIO 74 51 6
Abuf0out 76 P0[1] GPIO 72 49 4
Abuf1- 55 P3[4] GPIO 48 33 -
Abuf1+ 56 P3[5] GPIO 49 34 -

Analog Linear Abuf1out 58 P3[6] GPIO 51 36 -

Output Buffer Abuf2+ 80 P0[4] GPIO 76 53 8
Abuf2- 81 P0[5] GPIO 77 54 9
Abuf2out 75 P0[0] GPIO 71 48 3
Abuf3- 53 P3[2] GPIO 46 31 -
Abuf3+ 54 P3[3] GPIO 47 32 -
Abuf3out 59 P3[7] GPIO 52 37 -

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 199

I/O System

21.3.13 I/O Port Reconfiguration 21.3.15 Overvoltage Tolerance

Care must be taken not to lose the current configuration dur- All I/O pins provide an overvoltage (Vddio < Vin < Vdda) toler-
ing reconfiguration of pins when the device is connected ance feature at any operating voltage. Limitations include
directly to a digital peripheral. The I/O pins should hold their the following:
current configurations during a reconfiguration. If the ports ■ No current limitations for the SIO pins, because they
are driven by the data registers, configuration maintenance present a high impedance load to the external circuit.
is automatic.
■ GPIO pins must be limited to 100 µA, using a current
However, if the ports are bypassed and driven by the DSI, limiting resistor. Outside the current limitation, GPIO pins
the current value must be read and written to the data regis- clamp the pin voltage to approximately one diode above
ter ({PRT*_DR}) before initiating reconfiguration. Saving of the Vddio supply.
the current configuration occurs as follows:
A common application for this feature is connection to a bus
1. The software reads the GPIO / SIO pin state, such as I2C, where different devices are running from differ-
{PRT*_PS}. ent supply voltages. In the I2C case, the PSoC device is
2. The software writes this value into the data registers, configured into the Open Drain, Drives Low mode using an
{PRT*_DR}. SIO pin. This allows an external pull up to pull the I2C bus
3. I/O ports driven by the DSI must be driven by the data voltage above the pin’s Vddio supply. For example, the PSoC
register by de-asserting the bypass register value, device could operate at 1.8V, and an external device could
{PRT*_BYP}. run from 5V. The SIO pin’s VIH and VIL levels are deter-
At this point, it is safe to reconfigure the device. When mined by the associated Vddio supply pin.
reconfiguration is complete, the I/O sources can be driven The I/O pin must be configured into a High Impedance drive
by the DSI by setting the {PRT*_BYP} register value. mode, Open Drain Low mode, or Resistive Pull Down mode,
for overvoltage tolerance to work properly.
21.3.14 Power Up I/O Configuration
Absolute maximum ratings for the device must be observed
By default, all I/Os power up in a known state, either driving for all I/O pins.
a 0, driving a 1, or set to High Z. Input buffers are disabled
during power up. The value set in the nonvolatile (NV) 21.3.16 I/O Power Supply
latches determines the value driving each port.
The Vddio supply must be less than or equal to the voltage
A pair of NV latches is associated with each I/O port; these on the device’s Vdda pin. This feature allows users to pro-
latches serve two functions: vide different I/O interface levels for different pins on the
■ Latch values configure the pins on a port-wide basis dur- device. Refer to the datasheet to determine Vddio capability
ing power up. for a given device and pin.
■ Latch values load reset values for the drive mode and SIO port pins support an additional regulated high output
data registers to correctly configure the port, when capability, as discussed in 21.3.11.2 Adjustable Input Level.
IPOR_disabled is deasserted.

See the Nonvolatile Latch chapter on page 121 for more 21.3.17 Sleep Mode Behavior
information.
The GPIO/SIO pad will maintain the current pin state during
If the NVLs are set to 0x00 for the port, by default all I/Os sleep modes. Port pin interrupts remain active in all sleep
reset to the High Impedance Analog state but are repro- modes, allowing the PSoC device to wake from an exter-
grammable on a port-by-port basis. They can be reset as nally generated interrupt.
High Impedance Analog, Pull Down, or Pull Up, based on
the requirements of the application. 21.3.18 Low Power Behavior
In all low power modes, I/O pins retain their states until the
part is awakened and changed or reset. To awaken the part,
use a pin interrupt, because the port interrupt logic contin-
ues to function in all low power modes.

200 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 I/O System

21.4 Port Interrupt Controller Unit 21.4.2 Interrupt Controller Block Diagram
This section describes the functions of the port interrupt Figure 21-11 is a block diagram of the PICU showing the
controller unit (PICU) for PSoC I/O. function of control signal generation and data manipulation
blocks. These blocks send appropriate control signals to
interrupt-generating pin logic blocks, simultaneously record-
21.4.1 Features
ing these signals in status and snap registers.
The features of the PICU are as follows:
■ All eight pins in each port interface with their own PICU
and associated interrupt vector
■ Pin status bits provide easy determination of interrupt
source down to the pin level
■ Rising/falling/either edge interrupts are handled
■ Pin interrupts can be individually enabled or disabled
■ Interfaces to the PHUB for read and write into its regis-
ters
■ Sends out a single interrupt request (PIRQ) signal to the
interrupt controller
Figure 21-11. PICU Block Diagram

From GPIO Pin

Pin 0
Logic
From GPIO Pin Pin1
Logic
wakeup_in wakeup_out
From GPIO Pin
Pin 2
Logic
From GPIO Pin
Pin 3
Logic
PIRQ To Interrupt Controller Input
From GPIO Pin Logical OR
Pin 4
Logic
From GPIO Pin
Pin 5
Logic
From GPIO Pin
Pin 6
Logic
From GPIO Pin
Pin 7
Logic

Status
Register
PHUB PHUB Interface

Snap Shot
Register

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 201

I/O System

21.4.3 Function and Configuration 21.5 Register Summary

Each pin of the port can be configured independently to gen- Registers shown in Table 21-8 are associated with a single
erate interrupt on rising edge, falling edge, or either edge. I/O port and are specific to both the GPIO and SIO ports.
Level sensitive interrupts are not directly supported. UDB
provides this functionality to the system when needed. This Table 21-8. GPIO and SIO Port Registers
configuration is done by writing into the interrupt type regis- Address Description
ter corresponding to each pin. The sequence is as follows:
The Port Data Output register sets the data output
1. Depending on the configured mode for each pin, when- state for the corresponding GPIO port. It is aliased to
{PRT*_DR}
continuous address space in the PRT*_DR_ALIASED
ever the selected edge occurs on a pin, its correspond- registers.
ing status bit in the status register is set to ‘1’, and an
The Port Pin State register reads the logical pin state
interrupt request is sent to the interrupt controller. for the corresponding GPIO port. It is aliased to contin-
{PRT*_PS}
uous address space in the PRT*_PS_ALIASED regis-
2. Status bits that have ‘1’ are cleared upon a read of the ters.
status register. Other bits of the status register can still
The Port Drive Mode registers ({PRT*_DM[0]},
respond to incoming interrupt sources. {PRT*_DM*} {PRT*_DM[1]}, and (PRT*_DM[2]}) specify the drive
3. If an interrupt is pending, and the status register is being mode for I/O pins.

read, all of the incoming events on the same interrupt {PRT*_SLW}

The Port Slew Control register sets the slew rate for
pin outputs.
source (GPIO) are blocked until the read is complete.
However, all of the other interrupt sources that were not The Port Bypass register selects port output data from
{PRT*_BYP}
either the data output register or digital global input.
pending an interrupt in status register are not blocked.
The Port Bidirectional Enable register enables
4. Each PICU has a wakeup_in input and a wakeup_out (PRT*_BIE}
dynamic bidirectional mode at any pin.
output signal. The wakeup_in signal in a PICU is ORed The Port Input buffer disable allows the user to over-
together with other pin interrupts to generate a {PRT*_INP_DIS}
ride the input buffer default drive mode settings.
wakeup_out signal, as shown in Figure 21-11. Mask of which bits within the {PRT*_DR} and
5. All of the PICUs are daisy chained together to generate {PRT*_BIT_MSK} {PRT*_PS} are accessible via read / writes to
{PRT*_DR_ALIAS} and reads of {PRT*_PS_ALIAS}.
a final wakeup signal that goes to the power manager.
The Analog global control enable register selects on a
{PRT*_AG} pin-by-pin basis whether to connect the pin to the ana-
log global bus.
The Analog Global Multiplexer Register selects on a
{PRT*_AMUX} pin-by-pin basis whether to connect the pin to the ana-
log mux bus.
The Port Configuration Register allows configuration
of several configuration bits of the entire I/O port simul-
{PRT*_PRT}
taneously. This register aliases the port functional reg-
isters on a port-wide basis.
The Port Pin Configuration Registers ({PRT*_PC[0]
through {PRT*_PC[7]}) access several configuration or
{PRT*_PC*} status bits of a single I/O port pin simultaneously.
These registers alias the functional registers on a pin-
by-pin basis.
Aliased port data. Allows read / write access to
{PRT*_DR} if {PRT*_BIT_MSK} is set. Allows access
{PRT*_DR_ALIAS}
to all port data registers as a contiguous block simplify-
ing DMA access.
Aliased port data. Allows read access to {PRT*_PS} if
{PRT*_BIT_MSK} is set. Allows access to all port state
{PRT*_PS_ALIAS}
registers as a contiguous block simplifying DMA
access.

202 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 I/O System

Table 21-9 shows registers specific to a GPIO port.

Table 21-9. GPIO Registers

Address Description
Port-wide configuration register. This contains
{PRT*_CTL} the portEmifCfg[2:0] and port-wide vtrip_sel for
the corresponding GPIO register.
LCD com_seg setting. This selects common or
{PRT*_LCD_COM_SEG}
segment mode when the LCD is enabled.
LCD enable, allows port pins not connected to
{PRT*_LCD_EN}
LCD to be used for other functions.

Table 21-10 shows registers specific to an SIO port.

Table 21-10. SIO Port Registers

Address Description
Differential input buffer reference voltage
{PRT*_SIO_DIFF}
select, 2 bits per SIO pair.
Input buffer enable and Output buffer Configu-
{PRT*_SIO_CFG}
ration, 2 bits per SIO pair.
{PRT*_SIO_HYST_EN} Differential hysteresis enable.

Registers shown in Table 21-11 involve DSI bit selection.

These registers are associated with all I/O ports and are
located within the port logic.

Table 21-11. DSI Selection Registers

Address Description
Data output from UDB to Digital System Array
{PRT*_OUT_SEL*} Input Select registers. There are two select
lines per port pin.
UDB set dynamic Output Enable control select.
{PRT*_OE_SEL*}
There are two select lines per port pin.
The Port Double Sync In register enables syn-
chronization of the data in from the port before
{PRT*_DBL_SYNC_IN}
driving the digital system interconnect (DSI) sig-
nals to the UDB.
The Port Sync Out register enables synchroni-
zation of the data in from the UDB digital sys-
{PRT*_SYNC_OUT}
tem interconnect (DSI) using the existing
{PRT*_DR} register.

Table 21-12 shows the register associated with the PICU.

Table 21-12. PICU-Associated Registers

Address Description
This register defines the interrupt type to config-
{PICU*_INTTYPE*}
ure the pin interrupt – 1 register for each pin
Status register provides information on cur-
{PICU*_INTSTAT} rently posted interrupts – 1 register for each
PICU
The Port Snapshot register provides informa-
tion on the state of the input pins at the most
{PICU*_SNAP}
recent read to the status (INTSTAT) register – 1
register for each PICU

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 203

I/O System

204 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 22. Flash, Configuration Protection

PSoC® 3 and PSoC® 5 devices offer a host of Flash and configuration protection options and device security features that
can be leveraged to meet the security and protection requirements of an application. These requirements range from protect-
ing configuration settings or Flash data to locking the entire device from external access. The following section discusses in
detail these features together with their usage cases.

22.1 Flash Protection

The objective of Flash protection is to prevent access or modification to the Flash contents. The only nonvolatile (NV) storage
on a PSoC 3 or PSoC 5 device that has protection options is the Flash; there are no EEPROM and NV latch protection
options. Flash memory in PSoC 3 and PSoC 5 architectures is organized as Flash arrays. Depending on the Flash memory
size, there can be one or more than one Flash array. Each Flash array can have a maximum of 256 rows. Each Flash array
row has 256 bytes of data. PSoC 3 and PSoC 5 architectures offer customers the ability to assign one of four protection levels
to each row of Flash in a device. For each Flash array, Flash protection bits are stored in a hidden row in that array. In the hid-
den row, two protection bits per row are packed into a byte, so each byte in the hidden row has protection settings for four
Flash rows. The Flash rows are ordered so that the first two bits in the hidden row correspond to the protection settings of
Flash row 0 (see Figure 22-1). Refer to the Flash Program Memory chapter on page 129 to learn more about Flash memory
organization in PSoC 3 and PSoC 5 devices.

Figure 22-1. Flash Protection Bit Structure

Row 0 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7

Bits [0:1] Bits [2:3] Bits [4:5] Bits [6:7] Bits [0:1] Bits [2:3] Bits [4:5] Bits [6:7]

Byte 0 in Flash Hidden Row 0: Contains protection Byte 1 in Flash Hidden Row 0: Contains protection
bits for Flash rows 0 through 3 bits for Flash rows 4 through 7

Protection is cumulative in that modes have successively Table 22-1. Flash Protection Modes
higher protection levels and include the lower protection External
modes. Flash protection can only be set once. In order to Mode Description Reada Internal Writec
Writeb
change Flash protection settings after they have been set, 00 Unprotected Yes Yes Yes
the Flash contents must be completely erased and repro- 01 Read Protect No Yes Yes
grammed, then the protection levels can be set again. Refer
10 Disable External Write No No Yes
to the Nonvolatile Memory Programming chapter on
11 Disable Internal Write No No No
page 473 for erasing and programming Flash. Table 22-1
a. Applies to Test Controller and Read commands.
shows the protection modes. b. Test controller/3rd party programmers.
c. Boot loading or writes due to firmware execution.

When a read/write/erase operation is done for a row, the

corresponding protection bits are checked. The command is
executed only if allowed under the current protection mode.
If the command is not allowed, then the command fails.

As shown in Table 22-1, four Flash protection levels are

available for every row of Flash in a device. A customer may

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 205

Flash, Configuration Protection

choose any one of these protection levels independent of the key into the WO latch, program the Flash protection
the protection choice for all other rows in the Flash. data, and then reset the part to lock it.

The following list provides a few additional details on the Refer to the Nonvolatile Memory Programming chapter on
features and use cases for each of these protection levels. page 473 for information about writing to the Write Once
■ 00 – No Protection (WO) nonvolatile latch.

■ 01 – Read Protect
No external device can read a flash block that is read 22.3 Configuration Segment
protected. Protection
The SPC Read commands cannot be used to read a
block that is read protected. Part of the PSoC platform’s value to customers is its ability
Only the processor and the PHUB can access a block of to change the functionality of the device in real time. Chang-
Flash that is read protected. ing the functionality can be as simple as enabling an exter-
Offers only read protection. nal crystal or as dramatic as changing the functionality of
UDBs from timers to CRC generators. Based on the applica-
■ 10 – External Write Protection
tion needs, the customer may also want to protect certain
No external device can erase or write a row of Flash that Configuration registers.
is external write protected.
Includes all Read Protect restrictions. Not all configuration registers need the same level of secu-
rity and protection. Hence, the configuration registers are
Boot loaders work at this protection level.
grouped into four segments, with registers assigned to a
■ 11 – Fully Protected segment based on the presumed application use cases. The
The processor cannot erase or write a block of Flash following list defines the different segments. Refer to the
that is fully protected. PSoC® 3 Registers TRM (Technical Reference Manual)
Includes all protections from lower levels of Flash data and the PSoC® 5 Registers TRM (Technical Reference
protection. Manual), to find out the segment to which a particular config-
This level is used when a block of Flash should never be uration register is assigned.
modified by an internal process or external device.
Segment 0. One time system settings. This segment has
system registers that are configured only once during pro-
22.2 Device Security gram execution. The registers in this segment come under
The objective of device security is to prevent the PSoC 3 the following broad categories:
and PSoC 5 device in an application from being used as a ■ Power System
host to compromise the application. The device security fea- ■ Reset
ture is enabled by writing to the Write Once (WO) latch.
■ Watchdog
The WO latch is a type of nonvolatile latch. When the output ■ Internal low speed oscillator (ILO)
is ‘1’, the Write Once NVL locks the part out of Debug and
Test modes; it also permanently gates off the ability to erase Segment 1. Reconfigurable system settings. This segment
or alter the contents of the latch. has registers that can be reconfigured during program exe-
The user can write a correct 32-bit key (0x50536F43) into cution. The registers in this segment come under the follow-
the WO latch to disable the part from entering into Debug ing broad categories:
and Test modes. This precaution prevents anyone from ■ LVI Detect
erasing or altering the content of the internal memory. ■ Voltage regulators
If the device is protected with a WO latch setting, Cypress ■ Power Manager
cannot perform failure analysis and, therefore, cannot ■ Wakeup Sources
accept an RMA from customers. The WO latch is read out
■ Boost Converter
via serial wire debug (SWD) to electrically identify protected
parts. The user writes the key in the WO latch to lock out Segment 2. UDB array configuration registers.
external access only if no Flash protection is set. However,
■ All UDB array configuration registers, such as the clock
after setting the values in the WO latch, a user still has
selection and datapath input/output multiplexer selec-
access to the device until it is reset. The output of the WOL
tion, come under this segment.
is only sampled upon reset. Therefore, a user could write

206 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Flash, Configuration Protection

Segment 3. Analog interface (Registers related to analog If the segment protect bit is ‘0’, the segment’s lock bit can be
interface configuration). written as a ‘0’ or ‘1’ at anytime. If the protect bit is ‘1’, the
segment’s lock bit cannot be modified.
It must be noted that Segment 0 registers can be configured
either as the one time configurable or reconfigurable type. The segment protect (LOCK_PROTECT_x) bit is a write-to1
The same applies to Segment 1 and Segment 2 registers as once bit. It cannot change from a ‘1’ to a ‘0’ except as a
well. But as a best practice, it is advisable to set Segment 0 result of a hardware reset, such as a POR or XRES_N. For
registers as one time configurable. The settings for the rest one time configuration of a segment, it must be locked and
of the segments depend on application requirements. To protected after configuration.
find out the segment to which a register is allocated, see the
segment field for the register in the PSoC® 3 Registers TRM Lock Bit. The segment lock (LOCK_x) bit controls the write
(Technical Reference Manual) and the PSoC® 5 Registers access to the Configuration registers in the segment. Setting
TRM (Technical Reference Manual). the LOCK_x bit prevents write access to the Control regis-
ters; clearing the lock bit allows a write.
Write access to the Configuration registers in various seg-
ments is enabled using the Segment Configuration register For dynamic configuration of a segment, it must not be pro-
(MLOGIC_SEG_CFG0). Write access to the Segment Con- tected and can be locked after every configuration.
figuration register (MLOGIC_SEG_CFG0) is enabled using
Table 22-2 describes the behavior for different protect and
the Segment Control register (MLOGIC_SEG_CR).
lock bit settings.

22.3.1 Locking/Unlocking Segment Table 22-2. Protect and Lock Bit Settings
Configuration Register Protect/Lock Bits Description

The 8-bit Segment Control register (MLOGIC_SEG_CR) is The Configuration registers are not protected and
00b
not locked. They can be written at anytime.
used to control write access to the Segment Configuration
The Configuration registers are not protected but
register (MLOGIC_SEG_CFG0) bits. By default, write locked. This is used to temporarily lock the configu-
01b
access to the Segment Configuration register is disabled. ration and is used in the case of dynamic reconfig-
uration.
Attempted writes will appear to execute normally, but the
The Configuration register are protected and not
contents of the register will remain unchanged. 10b
locked. They can be written at anytime.

Segment configuration write access is enabled by writing The Configuration registers are protected and
11b
locked. This is used for one time configuration.
0xB5 to the Segment Control register and is disabled by
writing 0xB4 to the Segment Control register. Upon device
reset, the Segment Control register resets to the locked
state and disables write to the Segment Configuration regis-
ter.

When illegal values (values other then 0xB4 and 0xB5) are
written to the Segment Control register, it causes a device
reset and is indicated by the Segment reset (SEGRS) bit in
Reset Status (RESET_SR1) register. The segment reset bit
remains set until cleared by the user or POR.

22.3.2 Locking and Protecting Segments

The 8-bit Segment Configuration register
(MLOGIC_SEG_CFG0) holds a pair of bits for each seg-
ment (Segment 0 to Segment 3) that are used to regulate
access to the Configuration registers in that segment. The
pair consists of one protect bit and one lock bit; these bits
operate independently of each other.

Protect Bit. The segment protect (LOCK_PROTECT_x) bit

controls the ability to write the segment’s lock bit.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 207

Flash, Configuration Protection

Table 22-3. Segment 0: One Time System Settings Table 22-4. Segment 1: Reconfigurable System Settings
Category Register Names PHUB Address Category Register Names PHUB Address
RESET.CR3 0x46F7 RESET.CR0 0x46F4
RESET.CR4 0x46F8 LVI Detect RESET.CR1 0x46F5
RESET.CR5 0x47F9 RESET.CR2 0x46F6
RESET.TR 0x46FB
Reset
RESET.IPOR_CR0 0x46F0 Volt Regulators PWRSYS.CR1 0x4331
RESET.IPOR_CR1 0x46F1
RESET.IPOR_CR2 0x46F2 PM.TW_CFG0 0x4380
RESET.IPOR_CR3 0x46F3 PM.TW_CFG1 0x4381
PM.TW_CFG2 0x4382
MFGCFG.HIB_TR0 0x4680 Power Manager PM.WDT_CR 0x4384
MFGCFG.HIB_TR1 0x4681 PM.MODE_CFG0 0x4391
MFGCFG.I2C_TR 0x4682 PM.MODE_CFG1 0x4392
MFGCFG.SLP_TR 0x4683 PM.MODE_CSR 0x4393
MFGCFG.BUZZ_TR 0x4684
MFGCFG.WAKE_TR0 0x4685 PM.WAKEUP_CFG0 0x4398
Power System Wakeup Sources
MFGCFG.WAKE_TR1 0x4686 PM.WAKEUP_CFG1 0x4399
MFGCFG.BREF_TR 0x4687
MFGCFG.BG_TR 0x4688 BOOST.CR0 0x4320
MFGCFG.WAKE_TR2 0x4689 BOOST.CR1 0x4321
Boost
MFGCFG.WAKE_TR3 0x468a BOOST.CR2 0x4322
PWRSYS.CR0 0x4330 BOOST.CR3 0x4323

MFGCFG.ILO_TR0 0x4690 FASTCLK.* 0x4200-0x42FF

ILO MFGCFG.ILO_TR1 0x4691 Fast Clock MFGCFG.IMO.* 0x46A0-0x46A7
SLOWCLK.ILO.CR0 0x4300 MFGCFG.XMHZ.TR 0x46A8

Watchdog PM.WDT_CFG 0x4383 FLASH LPM CACHE.CR1 0x4801

Table 22-5. Segment 2: UDB Array

Category Register Names PHUB Address
0x10000-
UDB Config UCFG.*
0x150FF

Table 22-6. Segment 3: Analog Interface

Category Register Names PHUB Address
Analog IF ANAIF.* 0x5800-0x5FFF
MFGCFG.ANAIF.* 0x4600-0x467F

208 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Flash, Configuration Protection

22.3.3 Example
The device peripherals are enabled/disabled by the protect bit for this segment, MLOGIC_SEG_CFG0[3], is
PM_ACT_CFG* registers in Active mode. These registers not set. If the protect bit has been set by the user, the
are mapped in Segment1. The following steps explain the lock bit cannot be modified, other than by a device reset.
procedure to configure these registers and then lock the 3. Write to the Active Power Mode Template registers
configuration information so that runaway code does not (PM_ACT_CFG*) to enable/disable the required periph-
overwrite the values. erals.
1. Write 0xB5 to the Segment Control register 4. Set the lock bit (MLOGIC_SEG_CFG0[2]) and clear the
(MLOGIC_SEG_CR) to enable the write access to the protect bit (MLOGIC_SEG_CFG0[3]) for Segment 1 in
Segment Configuration register. the Segment Configuration register
(MLOGIC_SEG_CFG0).
2. Clear the lock bit for Segment 1 to get write access to
the Configuration registers in Segment 1. This is done by 5. Write 0xB4 to the Segment Control register to disable
clearing the lock bit corresponding to Segment 1, which the write access to the Segment Configuration register.
is MLOGIC_SEG_CFG0[2]. Here, it is assumed that the

22.4 Frequently Asked Questions About Best Practices for Flash

Protection and Device Security
Question 1. How do I decide on the Flash protection level needed for the application?

The protection settings for Flash memory must be set based on the following criteria:
■ If the application warrants the need for a field upgrade, then set the Disable External Write mode for the Flash rows that
are going to be updated in the field. This allows you to use the bootloader application to update the flash using communi-
cation interfaces such as I2C and USB.
■ If the application code must be protected from being copied or modified to protect IP, the Flash security level for the rows
containing the IP code must be set to Full Protection mode.

Question 2. Is it possible to modify the Flash protection settings that have already been set?

It is not possible to directly alter the Flash protection setting. The only way to change the Flash protection settings is to com-
pletely erase the entire Flash memory using the Erase All command, reprogram the Flash memory, and then set the new pro-
tection settings. Refer to the Nonvolatile Memory Programming chapter on page 473 to learn more about Flash erase/
program commands.

Question 3. Is it possible to reprogram a Flash memory that has been configured with Full Protection?

The only way to reprogram the fully protected rows is to erase the entire Flash memory using the Erase All command, repro-
gram the Flash memory, and then set the new protection settings as described in Question 2 above.

Question 4. Is it necessary to enable protection for the entire Flash memory, or only the for the region of Flash memory that
the application uses?

It is sufficient to configure Flash security for memory regions that are used by the application, leaving the unused locations
unprotected, provided that there is no possibility of the program execution going to the unprotected region. If there is a possi-
bility of code executing from the unprotected region (due to, for instance, function calls), malicious code can be written in the
unprotected region to read the Flash data in the fully protected region. Remember that internal read is permitted in all protec-
tion modes; therefore, it is always a good practice to set protection for the entire Flash memory.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 209

Flash, Configuration Protection

Question 5. Is it ever necessary to configure different protection settings for different memory regions?

Yes, depending on the application requirements. Different flash rows may need different protection settings. A typical exam-
ple would be the case of field upgrade using the bootloader component. The portion of Flash that needs to be upgraded in the
field with bootloadable code must be configured in External Write Protect mode. The remaining Flash memory (base code or
bootloader code, unused flash memory) can be set to Full Protection.

Question 6. Are Flash protection settings obeyed in Debug mode?

The Read Protection setting is not obeyed in Debug mode, which means the Flash memory can be read regardless of Flash
protection setting. The Write Protection setting is still intact. Setting Full Protection makes it impossible to write to the Flash
memory in Debug mode.

Because the Debug mode is used during the application development phase, there is no need to protect the Flash. After the
application development phase is over, and code has been finalized, the user can disable the debug feature.

Question 7. What is device security?

Device security is the feature in PSoC 3 and PSoC 5 architecture that prevents the device from entering Debug and Test
modes. To enable device security, write a 32-bit key (0x50536F43) into the Write Once (WO) latch. After writing this key, the
device cannot be reprogrammed by entering test mode. Entering debug mode while using JTAG boundary scan is also not
possible. This prevents external access to registers and nonvolatile memory. Refer to Device Security on page 206 of this
chapter to learn more about device security.

Question 8. What are the risks associated with enabling device security?

If the device is protected with a WO latch setting, Cypress cannot perform failure analysis and, therefore, cannot accept
RMAs from customers. The WO latch can be read via the SWD to electrically identify protected parts.

Question 9. Are device security and flash protection interrelated or independent?

The answer is both. While flash protection settings and device security are configured independently, enabling device security
does not allow external read or write of Flash memory, regardless of the flash protection settings. There is one important
exception. Even with device security enabled, it is still possible to update the Flash memory using a bootloader application,
provided the Flash memory is not fully protected.

Question 10. Is it possible to implement OTP (one time programmable) functionality such that Flash content can never be
altered after it is programmed?

The Full Protection setting for Flash memory, along with the device security feature can prevent the Flash from ever being
modified. This combination is the highest level of security setting available in PSoC 3 and PSoC 5 devices. The steps to do
this are given below
1. Erase the entire Flash memory using the Erase All command
2. Reprogram the Flash content.
3. Write a 32-bit key (0x50536F43) into the WO latch to enable device security.
4. Set Flash Protection setting to Full Protection.
5. Reset the part to lock it.

210 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Section E: Digital System

The digital subsystems of PSoC® 3 and PSoC® 5 architectures provide these devices their first half of unique configurability.
The subsystem connects a digital signal from any peripheral to any pin through the Digital System Interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low-power Universal Digital Blocks (UDBs).

PSoC Creator™ provides a library of pre-built and tested standard peripherals that are mapped onto the UDB array by the
tool (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on). Nonstandard peripherals are easily imple-
mented using a Hardware Description Language (HDL) such as Verilog. Each UDB contains Programmable Array Logic
(PAL) and Programmable Logic Device (PLD) functionality, together with a small state machine engine to support a wide vari-
ety of peripherals.

In addition to the flexibility of the UDB array, PSoC devices provide configurable digital blocks targeted at specific functions.
These blocks can include 16-bit timer/counter/PWM blocks, I2C slave/master/multi-master, Full Speed USB, and CAN 2.0b.
Refer to the device datasheet for a list of available specific function digital blocks.

This section encompasses the following chapters:

■ Universal Digital Blocks (UDBs) chapter on page 213
■ UDB Array and Digital System Interconnect chapter on page 255
■ Controller Area Network (CAN) chapter on page 263
■ USB chapter on page 279
■ Timer, Counter, and PWM chapter on page 295
■ I2C chapter on page 311
■ Digital Filter Block (DFB) chapter on page 327

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 211

 Section E: Digital System

Top Level Architecture

Digital System Block Diagram

System Bus

DIGITAL SYSTEM
Universal Digital Block Array (N x UDB)
8-Bit Timer Quadrature Decoder 16-Bit 16-Bit PRS
CAN I2C
PWM 2.0 Master/Slave

Usage Example for UDB

UDB UDB UDB
Sequencer UDB

8-Bit Timer
USB D+
UDB UDB UDB UDB
Nx FS PHY D-
I2C Slave
8-Bit SPI
Logic Timer USB 2.0
12-Bit SPI
Counter
UDB UDB UDB UDB
PWM
Logic
UDB UDB
UDB UDB
UART 12-Bit PWM

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 212

 23. Universal Digital Blocks (UDBs)

This chapter shows how the PSoC® 3 and PSoC® 5 Universal Digital Blocks (UDBs) enable the development of programma-
ble digital peripheral functions. The UDB architecture provides balance between configuration granularity and efficient imple-
mentation; UDBs consist of a combination of uncommitted logic similar to programmable logic devices (PLDs), structured
logic (datapaths), and a flexible routing scheme.

23.1 Features
■ For optimal flexibility, each UDB contains several components:
❐ ALU-based 8-bit datapath (DP) with an 8-word instruction store and multiple registers and FIFOs
❐ Two PLDs, each with 12 inputs, eight product terms and four macrocell outputs
❐ Control and status modules
❐ Clock and reset modules
■ A PSoC 3 or PSoC 5 device contains an array of up to 24 UDBs
■ Flexible routing through the UDB array
■ Portions of UDBs can be shared or chained to enable larger functions
■ Flexible implementations of multiple digital functions, including timers, counters, PWM (with dead band generator), UART,
I2C, SPI, and CRC generation/checking

23.2 Block Diagram

Figure 23-1 on page 214 illustrates the UDB as a construct containing a pair of basic PLD logic blocks, a datapath, and con-
trol, status, clock and reset functions.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 213

Universal Digital Blocks (UDBs)

Figure 23-1. UDB Block Diagram

PLD
Chaining
PLD PLD
Clock 12C4 12C4
and Reset (8 PTs) (8 PTs)
Control

Status and
Control
Datapath Datapath
Chaining

Routing Channel

23.3 How It Works 23.3.1 PLDs

The major components of a UDB are: There are two “12C4” PLDs in each UDB. PLD blocks,
shown in Figure 23-2 on page 215, can be used to imple-
■ PLDs (2) – These blocks take inputs from the routing
ment state machines, perform input or output data condition-
channel and form registered or combinational sum-of-
ing, and to create lookup tables (LUTs). PLDs may also be
products logic to implement state machines, control for
configured to perform arithmetic functions, sequence the
datapath operations, conditioning inputs, and driving
datapath, and generate status. General purpose RTL can be
outputs.
synthesized and mapped to the PLD blocks. This section
■ Datapath – This block contains a dynamically program- presents an overview of the PLD design.
mable ALU, four registers, two FIFOs, comparators, and
condition generation. A PLD has 12 inputs which feed across eight product terms
(PT) in the AND array. In a given product term, the true (T)
■ Control and Status – These modules provide a way for
or complement (C) of the input can be selected. The output
CPU firmware to interact and synchronize with UDB
of the PTs are inputs into the OR array. The 'C' in 12C4 indi-
operation. Control registers drive internal routing, and
cates that the OR terms are constant across all inputs, and
status registers read internal routing.
each OR input can programmatically access any or all of the
■ Reset and Clock Control – These modules provide PTs. This structure gives maximum flexibility and ensures
clock selection and enabling, and reset selection, for the that all inputs and outputs are permutable.
other blocks in the UDB.
■ Chaining Signals – The PLDs and datapath have
chaining signals that enable neighboring blocks to be
linked, to create higher precision functions.
■ Routing Channel – UDBs are connected to the routing
channel through a programmable switch matrix for con-
nections between blocks in one UDB, and to all other
UDBs in the array. Routing is covered in detail in the
UDB Array and Digital System Interconnect chapter on
page 255.
■ System Bus Interface – All registers and RAM in each
UDB are mapped into the system address space and are
accessible by the CPU and DMA as both 8-bit and 16-bit
data.

214 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

Figure 23-2. PLD 12C4 Structure

PT0

PT1

PT2

PT3

PT4

PT5

PT6

PT7
IN0 TC TC TC TC TC TC TC TC
IN1 TC TC TC TC TC TC TC TC
IN2 TC TC TC TC TC TC TC TC
IN3 TC TC TC TC TC TC TC TC
IN4 TC TC TC TC TC TC TC TC
IN5 TC TC TC TC TC TC TC TC AND
IN6 TC TC TC TC TC TC TC TC Array

IN7 TC TC TC TC TC TC TC TC
IN8 TC TC TC TC TC TC TC TC
IN9 TC TC TC TC TC TC TC TC
IN10 TC TC TC TC TC TC TC TC
IN11 TC TC TC TC TC TC TC TC
SELIN
(carry in)

OUT0 MC0 T T T T T T T T
OUT1 MC1 T T T T T T T T
OUT2 MC2 T T T T T T T T
OUT3 MC3 T T T T T T T T

SELOUT
(carry out)
OR
Array

23.3.1.1 PLD Macrocells

The macrocell architecture is shown in Figure 23-3 on
page 216. The output drives the routing array, and can be
registered or combinational. The registered modes are D
Flip-Flop with true or inverted input, and Toggle Flip-Flop on
input high or low. The output register can be set or reset for
purposes of initialization, or asynchronously during opera-
tion under control of a routed signal.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 215

Universal Digital Blocks (UDBs)

Figure 23-3. Macrocell Architecture

XOR Feedback
00: D FF
01: Arithmetic (Carry)
10: T FF on high
11: T FF on low
Set Select
(from previous macrocell) XORFB[1:0] 0: Set not used
SSEL
selin 1: Set from input

Special Product Term

3 1
2
Inputs 1 0
0 To macrocell
cpt1 1
CONST
read-only register
cpt0 0 Constant
0: D FF true in 1

1: D FF inverted in out
set 0
sum D Q

clk QB
res
pld_en
reset 1
Output Bypass
BYP
0 0: Registered
COEN
1: Combinational
Carry Out Enable RSEL Reset Select
0:Carry Out disabled 0: Set not used
1: Carry Out enabled 1: Set from input
selout
(to next macrocell)

PLD Macrocell Read Only Register

In addition to driving the routing array, the outputs of the macrocells from both PLDs are mapped into the address space as an
8-bit read only register, which can be accessed by the CPU or DMA.

Figure 23-4. PLD Macrocell Read Only Register

PLD1 PLD0

MC3 MC2 MC1 MC0 MC3 MC2 MC1 MC0

7 6 5 4 3 2 1 0

RD MC (Read Only)

System Bus

216 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

23.3.1.2 PLD Carry Chain of the PLDs, and then to the next UDB as the carry chain out
“selout”. To support the efficient mapping of arithmetic func-
PLDs are chained together in UDB address order. As shown
tions, special product terms are generated and used in the
in Figure 23-6 the carry chain input “selin” is routed from the
macrocell in conjunction with the carry chain.
previous UDB in the chain, through each macrocell in both
Figure 23-5. PLD Carry Chain and Special Product Term Inputs

{PT7,PT6} PLD1 PLD0

{PT5,PT4}

{PT3,PT2}

{PT1,PT0}

{PT7,PT6}

{PT5,PT4}

{PT3,PT2}

{PT1,PT0}
cpt1,cpt0 cpt1,cpt0 cpt1,cpt0 cpt1,cpt0 cpt1,cpt0 cpt1,cpt0 cpt1,cpt0 cpt1,cpt0

selout MC3 MC2 MC1 MC0 MC3 MC2 MC1 MC0 selin
To the next From previous
PLD block PLD block in
in the chain the chain

23.3.1.3 PLD Configuration 23.3.2 Datapath

Each PLD appears to the CPU or DMA as a 16-bit wide The datapath, shown in Figure 23-6 below, contains an 8-bit
RAM. The AND array has 12 X 8 X 2 bits, or 24 bytes, for single-cycle ALU, with associated compare and condition
programming, and the OR array has 4 x 8 bits, or 4 bytes, generation circuits. A datapath may be chained with
for programming. In addition, each macrocell has one con- datapaths in neighboring UDBs to achieve higher precision
figuration byte, resulting in 32 total configuration bytes per functions. The datapath includes a small RAM-based control
PLD. Since each UDB contains two PLDs, there are 64 total store, which can dynamically select the operation to perform
PLD configuration bytes per UDB. See UDB Configuration in a given cycle.
Address Space on page 252 for more information.
The datapath is optimized to implement typical embedded
functions such as timers, counters, PWMs, PRS, CRC, shift-
ers and dead band generators. The addition of add and sub-
tract functions allow support for digital delta-sigma
operations.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 217

Universal Digital Blocks (UDBs)

Figure 23-6. Datapath Top Level

PHUB System Bus

R/W Access to all

registers

F1

FIFOs

Datapath Control

2 Zero Detect, 2 Ones Detect

Input Output
F0
Control Store RAM

Muxes Muxes
A0
8 Word X 16 bit

Input from Output to

Overflow Detect
6

Conditions
6

2 Compares
Programmable A1 Programmable
Routing D0 Routing
D1
D1
Data Registers

D0
To/From To/From
Prev Chaining Next
Datapath Datapath
A1

Accumulators

A0

PI
Parallel Input/Output
(to/from Programmable
Routing)
PO

ALU
ALU

Shift

Mask

218 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

23.3.2.1 Overview FIFO), or an output buffer (datapath internals write to the

FIFO, the CPU or DMA reads from the FIFO). These FIFOs
The following sections present an overview description of
generate status that can be routed to interact with sequenc-
key datapath features:
ers, interrupt, or DMA requests.
Dynamic Configuration
Chaining
Dynamic configuration is the ability to change the datapath
The datapath can be configured to chain conditions and sig-
function and interconnect on a cycle-by-cycle basis, under
nals with neighboring datapaths. Shift, carry, capture, and
sequencer control. This is implemented using the configura-
other conditional signals can be chained to form higher pre-
tion RAM, which stores eight unique configurations. The
cision arithmetic, shift, and CRC/PRS functions.
address input to this RAM can be routed from any block
connected to the routing fabric, most typically PLD logic, I/O Time Multiplexing
pins, or other datapaths.
In applications that are oversampled, or do not need the
ALU highest clock rates, the single ALU block in the datapath can
be efficiently shared between two sets of registers and con-
The ALU can perform eight general-purpose functions:
dition generators. ALU and shift outputs are registered and
increment, decrement, add, subtract, AND, OR, XOR, and
can be used as inputs in subsequent cycles. Usage exam-
PASS. Function selection is controlled by the configuration
ples include support for 16-bit functions in one (8-bit) data-
RAM on a cycle-by-cycle basis. Independent shift (left, right,
path, or interleaving a CRC generation operation with a data
nibble swap) and masking operations are available at the
shift operation.
output of the ALU.
Datapath Inputs
Conditionals
The datapath has three types of inputs: configuration, con-
Each datapath has two comparators, with bit masking
trol, and serial and parallel data. The configuration inputs
options, which can be configured to select a variety of data-
select the control store RAM address. The control inputs
path register inputs for comparison. Other detectable condi-
load the data registers from the FIFOs and capture accumu-
tions include all zeros, all ones, and overflow. These
lator outputs into the FIFOs. Serial data inputs include shift
conditions form the primary datapath output selects to be
in and carry in. A parallel data input port allows up to eight
routed to the digital routing fabric or inputs to other func-
bits of data to be brought in from routing.
tions.
Datapath Outputs
Built in CRC/PRS
There are a total of 16 signals generated in the datapath.
The datapath has built-in support for single-cycle Cyclic
Some of these signals are conditional signals (for example,
Redundancy Check (CRC) computation and Pseudo Ran-
compares), some are status signals (for example, FIFO sta-
dom Sequence (PRS) generation of arbitrary width and arbi-
tus), and the rest are data signals (for example, shift out).
trary polynomial specification. To achieve longer than 8-bit
These 16 signals are multiplexed into the six datapath out-
CRC/PRS widths, signals may be chained between dat-
puts and then driven to the routing matrix. By default the
apaths. This feature is controlled dynamically, and therefore
outputs are single synchronized (pipelined). A combinational
can be interleaved with other functions.
output option is also available for these outputs.
Variable MSB
The most significant bit of an arithmetic and shift function
can be programmatically specified. This supports variable
width CRC/PRS functions and, in conjunction with ALU out-
put masking, can implement arbitrary width timers, counters,
and shift blocks.

Input/Output FIFOs
Each datapath contains two 4-byte FIFOs, which can be
individually configured for direction as an input buffer (CPU
or DMA writes to the FIFO, datapath internals read the

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Universal Digital Blocks (UDBs)

Datapath Working Registers Table 23-2. FIFO Modes and Configurations

Each datapath module has six 8-bit working registers. All The control to load the FIFO from the datapath source is
sampled on the currently selected datapath clock (normal)
registers are readable and writable by CPU or DMA: Normal/Fast or the bus clock (fast). This allows captures to occur at the
highest rate in the system (bus clock), independent of the
Table 23-1. Datapath Working Registers datapath clock.
When this mode is enabled, and the FIFO is in output
Type Name Description mode, a read by the CPU or DMA of the associated accu-
The accumulators may be both a source and a mulator (A0 for F0, A1 for F1) initiates a synchronous trans-
destination for the ALU. They may also be loaded Software fer of the accumulator value into the FIFO. The captured
from a Data register or a FIFO. The accumulators Capture value may then be immediately read from the FIFO. If
Accumulator A0, A1 typically contain the current value of a function, chaining is enabled, the operation follows the chain to the
such as a count, CRC, or shift. These registers MS block for atomic reads by datapaths of multi-byte val-
are nonretention; they lose their values in sleep ues.
and are reset to 0x00 on wakeup. When the datapath is being clocked asynchronously to the
The Data registers typically contain constant data bus clock, the FIFO status signals can be routed to the rest
for a function, such as a PWM compare value, Asynch of the datapath either directly, single sampled to the DP
Data D0, D1 clock, or double sampled in the case of an asynchronous
timer period, or CRC polynomial. These registers
retain their values across sleep intervals. DP clock

The two 4-byte FIFOs provide both a source and Independent Each FIFO has a control bit to invert polarity of the FIFO
a destination for buffered data. The FIFOs can be Clock Polarity clock with respect to the datapath clock.
configured as both input buffers, both output buf-
fers, or as one input buffer and one output buffer.
Status signals indicate the read and write status
FIFOs F0, F1 of these registers. Usage examples include buff- Figure 23-7 shows the possible FIFO configurations con-
ered TX and RX data in the SPI or UART and trolled by the input/output modes. The TX/RX mode has one
buffered PWM compare and buffered timer
period data. These registers are nonretention; FIFO in input mode and the other in output mode. The pri-
they lose their values in sleep and are reset to mary usage example of this configuration is SPI. The dual
0x00 on wakeup.
capture configuration provides independent capture of A0
and A1, or two separately controlled captures of either A0 or
23.3.2.2 Datapath FIFOs A1. Finally, the dual buffer mode can provide buffered peri-
ods and compares, or two independent periods/compares.
FIFO Modes and Configurations
Each FIFO has a variety of operation modes and configura-
tions available:

Table 23-2. FIFO Modes and Configurations

Mode Description
In input mode the CPU or DMA writes to the FIFO and the
data is read and consumed by the datapath internals. In
Input/Output
output mode the FIFO is written to by the datapath internals
and is read and consumed by the CPU or DMA
The FIFO operates as a single buffer with no status. Data
Single Buffer written to the FIFO is immediately available for reading, and
can be overwritten at anytime.
The control to load the FIFO from the datapath internals
Level/Edge
can be either level or edge triggered.

220 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

Figure 23-7. FIFO Configurations

System Bus System Bus

F0 F0 F1

D0/D1 D0 D1
A0/A1/ALU A0/A1/ALU A0/A1/ALU A0 A1

F1 F0 F1

System Bus System Bus

TX/RX Dual Capture Dual Buffer

Figure 23-8 shows a detailed view of the FIFO sources and sinks.

Figure 23-8. FIFO Sources and Sinks

ALU

ALU
A0
A1

A0
A1
UDB Local Data Bus

FIFO F0 FIFO F1

D0 D1

A0 A1

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 221

Universal Digital Blocks (UDBs)

When the FIFO is in input mode, the source is the system bus and the sinks are the Dx and Ax registers. When in output
mode, the sources include the Ax registers and the ALU, and the sink is the system bus. The multiplexer selection is statically
set in UDB configuration register CFG15 as shown in the following table for the F0_INSEL[1:0] or F1_INSEL[1:0]:

Table 23-3. FIFO Multiplexer Set in UDB Configuration Register

Fx_INSEL[1:0] Description
00 Input Mode - System bus writes the FIFO, FIFO output destination is Ax or Dx.
01 Output Mode - FIFO input source is A0, FIFO output destination is the system bus.
10 Output Mode - FIFO input source is A1, FIFO output destination is the system bus.
11 Output Mode - FIFO input source is the ALU output, FIFO output destination is the system bus.

FIFO Status
Each FIFO generates two status signals, “bus” and “block,” which are sent to the UDB routing through the datapath output
multiplexer. The “bus” status can be used to assert an interrupt or DMA request to read/write the FIFO. The “block” status is
primarily intended to provide the FIFO state to the UDB internals. The meanings of the status bits depend on the configured
direction (Fx_INSEL[1:0]) and the FIFO level bits. The FIFO level bits (Fx_LVL) are set in the Auxiliary Control Working regis-
ter in working register space. Options are shown in the following table:

Table 23-4. FIFO Status Options

Fx_INSEL[1:0] Fx_LVL Status Signal Description
Input 0 Not Full Bus Status Asserted when there is room for at least 1 byte in the FIFO.
Input 1 At Least Half Empty Bus Status Asserted when there is room for at least 2 bytes in the FIFO.
Asserted when there are no bytes left in the FIFO. When not empty, the datapath
Input NA Empty Block Status internals may consume bytes. When empty the datapath may idle or generate an
underrun condition.

Output 0 Not Empty Bus Status Asserted when there is at least 1 byte available to be read from the FIFO.
Output 1 At Least Half Full Bus Status Asserted when there are at least 2 bytes available to be read from the FIFO.
Asserted when the FIFO is full. When not full, the datapath internals may write
Output NA Full Block Status bytes to the FIFO. When full, the datapath may idle or generate an overrun condi-
tion.

FIFO Illustrated Operation

Figure 23-9 on page 223 illustrates a typical sequence of reads and writes and the associated status generation. Although the
figure shows reads and writes occurring at different times, a read and write could also occur simultaneously.

222 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

Figure 23-9. Detailed FIFO Operation Sinks

Reset Write 2 bytes Write 2 more bytes Read 3 bytes
Empty = 1 Empty = 0 Empty = 0 Empty = 0
At Least Half Empty = 1 At Least Half Empty = 1 At Least Half Empty = 0 At Least Half Empty = 1
Full = 0 Full = 0 Full = 1 Full = 0
At Least Half Full = 0 At Least Half Full = 1 At Least Half Full = 1 At Least Half Full = 0

WR_PTR WR_PTR WR_PTR

D0 D0 X
RD_PTR RD_PTR RD_PTR

D1 D1 X

WR_PTR
D2 X

RD_PTR
D3 D3

Write 2 bytes Read 2 bytes Read 1 bytes

Empty = 0 Empty = 0 Empty = 1
At Least Half Empty = 0 At Least Half Empty = 1 At Least Half Empty = 1
Full = 0 Full = 0 Full = 0
At Least Half Full = 1 At Least Half Full = 0 At Least Half Full = 0

D4 X X

RD_PTR
D5 D5 X

WR_PTR WR_PTR WR_PTR

X X X
RD_PTR
RD_PTR
D3 X X

FIFO Fast Mode (FIFO FAST)

When the FIFO is configured for output, the FIFO load operation normally uses the currently selected datapath clock for sam-
pling the write signal. As shown in Figure 23-10, with the FIFO fast mode set, the bus clock can be optionally selected for this
operation. Used in conjunction with edge sensitive mode, this operation reduces the latency of accumulator-to-FIFO transfer
from the resolution of the DP clock to the resolution of the bus clock, which can be much higher. This allows the CPU or DMA
to read the captured result in the FIFO with minimal latency.

As shown in Figure 23-10, the fast load operation is independent of the currently selected datapath clock, however, using the
bus clock may cause higher power consumption.
Figure 23-10. FIFO Fast Configuration Sinks

UDB DP
Clock Mux

digital DP clk
clocks DP Operation

bus clk

fx_ld Write

0 FIFO
(In Output Mode)
bus clk
1

FIFO Fast

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 223

Universal Digital Blocks (UDBs)

FIFO Edge/Level Write Mode form is arbitrary (however, it must be at least one datapath
clock cycle in width). An example of this mode is capturing
There are two modes for writing the FIFO from the datapath.
the value of the accumulator using an external pin input as a
In the first mode, data is synchronously transferred from the
trigger. The limitation of this mode is that the input control
accumulators to the FIFOs. The control for that write
must revert to '0' for at least one cycle before another posi-
(FX_LD) is typically generated from a state machine or con-
tive edge is detected.
dition that is synchronous to the datapath clock. The FIFO
will be written in any cycle where the input load control is a Figure 23-11 shows the edge detect option on the FX_LD
'1'. In the second mode, the FIFO is used to capture the control input. One bit for this option sets the mode for both
value of the accumulator in response to a positive edge of FIFOs in a UDB. Note that edge detection is sampled at the
the FX_LD signal. In this mode the duty cycle of the wave- rate of the selected FIFO clock.

Figure 23-11. Edge Detect Option for Internal FIFO Write Sinks

0
fx_write
fx_ld (from Routing) 1
FF

FIFO Edge
dp_clk 0

bus_clk 1

FIFO Fast

FIFO Software Capture Mode

A common and important requirement is to allow the CPU or DMA the ability to reliably read the contents of an accumulator
during normal operation. This is done with software capture and is enabled by setting the FIFO Cap configuration bit. This bit
applies to both FIFOs in a UDB, but is only operational when a FIFO is in output mode. When using software capture, F0
should be set to load from A0 and F1 from A1.

As shown in Figure 23-12, reading the accumulator triggers a write to the FIFO from that accumulator. This signal is chained
so that a read of a given byte simultaneously captures accumulators in all chained UDBs. This allows an 8-bit processor to
reliably read 16 bits or more simultaneously. The data returned in the read of the accumulator should be ignored; the captured
value may be read from the FIFOs immediately.

The routed FX_LD signal, which generates a FIFO load, is ORed with the software capture signal; the results could be unpre-
dictable when both hardware and software capture are used at the same time. As a general rule these functions should be
mutually exclusive, however, hardware and software capture can be used simultaneously with the following settings:
■ FIFO capture clocking mode is set to FIFO FAST
■ FIFO write mode is set to FIFO EDGE

With these settings, hardware and software capture work essentially the same and in any given bus clock cycle, either signal
asserted initiates a capture.

It is also recommended to clear the target FIFO in firmware (ACTL register) before initiating a software capture. This initializes
the FIFO read and write pointers to a known state.

224 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

Figure 23-12. Software Capture Configuration

Chain X

capxi (chaining in)

capx (chaining out)
read ax
FIFO Cap

0 fx_write

1
fx_ld
FIFO EDGE

bus clk
(FIFO FAST)

FIFO Control Bits and F1 is set for output mode, which is a typical configura-
tion for TX and RX registers.
There are four bits in the Auxiliary Control register that may
be used to control the FIFO during normal operation. On the TX side, the datapath state machine uses "empty" to
determine if there are any bytes available to consume.
The FIFO0 CLR and FIFO1 CLR bits are used to reset or
Empty is set synchronously to the DP state machine, but is
flush the FIFO. When a '1' is written to one of these bits, the
cleared asynchronously due to a bus write. When cleared,
associated FIFO is reset. The bit must be written back to '0'
the status is synchronized back to the DP state machine.
for FIFO operation to continue. If the bit is left asserted, the
given FIFO is disabled and operates as a one byte buffer On the RX side, the datapath state machine uses “full” to
without status. Data can be written to the FIFO; the data is determine whether there is a space left to write to the FIFO.
immediately available for reading and can be overwritten at Full is set synchronously to the DP state machine, but is
anytime. Data direction using the Fx INSEL[1:0] configura- cleared asynchronously due to a bus read. When cleared,
tion bits is still valid. the status is synchronized back to the DP state machine.

The FIFO0 LVL and FIFO1 LVL bits control the level at A single FIFO ASYNCH bit is used to enable this synchroni-
which the 4-byte FIFO asserts bus status (when the bus is zation method; when set it applies to both FIFOs. It is only
either reading or writing to the FIFO) to be asserted. The applied to the block status, as it is assumed that bus status
meaning of FIFO bus status depends on the configured is naturally synchronized by the interrupt process.
direction, as shown in the table below.
FIFO Overflow Operation
Table 23-5. FIFO Level Control Bits
Use FIFO status signaling to safely implement both internal
FIFOx Input Mode Output Mode (datapath) and external (CPU or DMA) reads and writes.
LVL (Bus is Writing FIFO) (Bus is Reading FIFO)
There is no built-in protection from underflow and overflow
Not Full Not Empty conditions. If the FIFO is full, and subsequent writes occur
0
At least 1 byte can be written At least 1 byte can be read
(overflow), the new data overwrites the front of the FIFO (the
At Least Half Empty At Least Half Full data currently being output, the next data to read). If the
1
At least 2 bytes can be written At least 2 bytes can be read
FIFO is empty, and subsequent reads occur (underflow), the
read value is undefined. FIFO pointers remain accurate
FIFO Asynchronous Operation regardless of underflow and overflow.
Figure 23-13 illustrates the concept of asynchronous FIFO
operation. As an example, assume F0 is set for input mode

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 225

Universal Digital Blocks (UDBs)

Figure 23-13. FIFO Asynchronous Operation

System Bus

async
F0 (TX)
blk_stat
empty empty Empty to
Asynchronously cleared 0
DP state
Synch to by bus write, 1 machine
DP sycnhyronously set by set
DP read d q

Datapath Process DP clk

(Asynch)

async
Synch to
DP
full full Full to
Asynchronously cleared 0
blk_stat DP state
by bus read, 1 machine
F1 (RX) sycnhyronously set by set
DP write d q

DP clk
System Bus

FIFO Clock Inversion Option polarity as the DP clock. When this bit is set, the FIFO oper-
ates at the opposite polarity as the DP clock. This provides
Each FIFO has a control bit called Fx CK INV that controls
support for “both clock edge” communication protocols,
the polarity of the FIFO clock, with respect to the polarity of
such as SPI.
the DP clock. By default the FIFO operates at the same

FIFO Dynamic Control

Normally, the FIFOs are configured statically in either input
or output mode. As an alternative, each FIFO can be config-
ured into a mode where the direction is controlled dynami-
cally, that is, by routed signals. One configuration bit per
FIFO (Fx DYN) enables the mode. Figure 23-14 on
page 227 shows the configurations available in dynamic
FIFO mode.

226 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

Figure 23-14. FIFO Dynamic Mode

ALU
A0
A1
UDB Local Data Bus

FIFO Fx FIFO Fx

UDB Local Data Bus

Ax

Internal Access External Access

In internal access mode, the datapath can read and write FIFO status signals have the following definitions (also
the FIFO. In this configuration, the Fx INSEL bits must be dependent on Fx LVL control):
configured to select the source for the FIFO writes. Fx
INSEL = 0 (CPU bus source) is invalid in this mode; they Table 23-6. FIFO Status
can only be 1, 2 or 3 (A0, A1, or ALU). Note that the only Status Signal Meaning Fx LVL = 0 Fx LVL = 1
read access is to the associated accumulator; the data reg- fx_blk_stat Write Status FIFO full FIFO full
ister destination is not available in this mode. fx_bus_stat Read Status FIFO not empty At least ½ full

In external access mode, the CPU or DMA can both read

and write the FIFO. Since the datapath and CPU may both write and read the
FIFO, these signals are no longer considered “block” and
The configuration between internal and external access is “bus” status. The blk_stat signal is used for write status, and
dynamically switchable using datapath routing signals. The the bus_stat signal is used for read status.
datapath input signals d0_load and d1_load are used for
this control. Note that in the dynamic control mode, d0_load 23.3.2.3 FIFO Status
and d1_load are not available for their normal use in loading
the D0/D1 registers from F0/F1. The dx_load signals can be There are four FIFO status signals, two for each FIFO:
driven by any routed signal, including constants. fifo0_bus_stat, fifo0_blk_stat, fifo1_bus_stat and
fifo1_blk_stat. The meaning of these signals depends on the
In one usage example, starting with external access direction of the given FIFO, which is determined by static
(dx_load == 1), the CPU or DMA can write one or more configuration. FIFO status is covered in detail in section
bytes of data to the FIFO. Then toggling to internal access 23.3.2.2 Datapath FIFOs on page 220.
(dx_load == 0), the datapath can perform operations on the
data. Then toggling back to external access, the CPU or 23.3.2.4 Datapath ALU
DMA can read the result of the computation.
The ALU core consists of three independent 8-bit program-
Since the Fx INSEL must always be set to 01, 10 or 11 (A0, mable functions, which include an arithmetic/logic unit, a
A1, or ALU), which is “output mode” in normal operation, the shifter unit, and a mask unit.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 227

Universal Digital Blocks (UDBs)

Arithmetic and Logic Operation When a routed carry is used, the meaning with respect to
each arithmetic function is shown in Table 23-10. Note that
The ALU functions, which are configured dynamically by the
in the case of the decrement and subtract functions, the
RAM control store, are shown in the following table:
carry is active low (inverted).
Table 23-7. ALU Functions
Table 23-10. Routed Carry In Functions
Func[2:0] Function Operation
Carry In Carry In Carry In
000 PASS srca Function
Polarity Active Inactive
001 INC ++srca
INC True ++srca srca
010 DEC --srca
DEC Inverted --srca srca
011 ADD srca + srcb
ADD True (srca + srcb) + 1 srca + srcb
100 SUB srca - srcb
SUB Inverted (srca - srcb) - 1 (srca - srcb)
101 XOR srca ^ srcb
110 AND srca & srcb Carry Out
111 OR srca | srcb
The carry out is a selectable datapath output and is derived
from the currently defined MSB position, which is statically
Carry In
programmable. This value is also chained to the next most
The carry in is used in arithmetic operations. There is a significant block as an optional carry in. Note that in the
default carry in value for certain functions as shown in case of decrement and subtract functions, the carry out is
Table 23-8. inverted.

Table 23-8. Carry In Functions Table 23-11. Carry Out Functions

Function Operation Default Carry In Implementation Carry Out Carry Out Carry Out
Function
INC ++srca srca + 00h + ci, where ci is forced to 1 Polarity Active Inactive

DEC --srca srca + ffh + ci, where ci is forced to 0 INC True ++srca == 0 srca

ADD srca + srcb srca + srcb + ci, where ci is forced to 0 DEC Inverted --srca == -1 srca

SUB srca - srcb srca + ~srcb + ci, where ci is forced to 1 ADD True srca + srcb > 255 srca + srcb
SUB Inverted srca - srcb < 0 (srca - srcb)
In addition to this default arithmetic mode for carry opera-
tion, there are three additional carry options. The CI SELA Carry Structure
and CI SELB configuration bits determine the carry in for a
Options for carry in, and for MSB selection for carry out gen-
given cycle. Dynamic configuration RAM selects either the A
eration, are shown in Figure 23-15 on page 229. The regis-
or B configuration on a cycle-by-cycle basis. The options are
tered carry out value may be selected as the carry in for a
defined in Table 23-9.
subsequent arithmetic operation. This feature can be used
Table 23-9. Additional Carry In Functions to implement higher precision functions in multiple cycles.

CI SEL A
Carry Mode Description
CI SEL B
Default arithmetic mode as described
00 Default
in Table 23-8.
Carry Flag, result of the carry from
the previous cycle. This mode is used
to implement add with carry and sub-
01 Registered
tract with borrow operations. It can be
used in successive cycles to emulate
a double precision operation.
Carry is generated elsewhere and
routed to this input. This mode can
10 Routed
be used to implement controllable
counters.
Carry is chained from the previous
datapath. This mode can be used to
11 Chained implement single cycle operations of
higher precision involving two or
more datapaths.

228 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

Figure 23-15. Carry Operation

Selected MSB
Arithmetic ALU Function
(inc, dec, add, sub)
Default function value
ci Chained (from prev datapath)
ALU ALU ALU ALU ALU ALU ALU ALU
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Registered (from co_msb_reg)
Routed (from interconnect)
co_msb
(to DP output mux)

co_msb_reg

Shift Operation Table 23-13. Shift In Functions

The shift operation occurs independently of the ALU opera- SI SEL A

Shift In Source Description
tion, according to Table 23-12 SI SEL B
The default input is the value of the
Table 23-12. Shift Operation Functions DEF SI configuration bit (fixed 1 or
00 Default/Arithmetic 0). However, if the MSB SI bit is set,
Shift[1:0] Function then the default input is the currently
defined MSB (for right shift only).
00 Pass
The shift in value is driven by the cur-
01 Shift Left rent registered shift out value (from
the previous cycle). The shift left
10 Shift Right 01 Registered
operation uses the last shift out left
11 Nibble Swap value. The shift right operation uses
the last shift out right value.
Shift in is selected from the routing
A shift out value is available as a datapath output. Both shift 10 Routed
channel (the SI input).
out right (sor) and shift out left (sol_msb) share that output Shift in left is routed from the right
selection. A static configuration bit (SHIFT SEL in register 11 Chained
datapath neighbor and shift in right is
routed from the left datapath neigh-
CFG15) determines which shift output is used as a datapath bor.
output. When no shift is occurring, the sor and sol_msb sig-
nal is defined as the LSB or MSB of the ALU function, The shift out left data comes from the currently defined MSB
respectively. position, and the data that is shifted in from the left (in a shift
right operation) goes into the currently defined MSB posi-
The SI SELA and SI SELB configuration bits determine the
tion. Both shift out data (left or right) are registered and can
shift in data for a given operation. Dynamic configuration
be used in a subsequent cycle. This feature can be used to
RAM selects the A or B configuration on a cycle-by-cycle
implement a higher precision shift in multiple cycles.
basis. Shift in data is only valid for left and right shift; it is not
used for pass and nibble swap. The selections and usage
apply to both left and right shift directions and are shown in
Table 23-13.
Figure 23-16. Shift Operation
S e le c t d e fa u lt v a lu e o r
a r ith m e tic s h ift

D e fa u lt ( tie v a lu e )

s h ift in le ft ( s il) s o r_ re g
R e g is te r e d (s o r _ r e g )
R o u te d (fr o m in te r c o n n e c t) S e le c te d M S B
C h a in e d (fr o m n e x t D a ta p a th ) S h ift r ig h t o r s h ift le ft s h ift o u t r ig h t ( s o r )
(to D P o u tp u t m u x )

s il 7 6 5 4 3 2 1 0

D e fa u lt ( tie v a lu e )

s h ift o u t le ft ( s o l_ m s b ) R e g is te r e d ( fr o m s o l_ m s b _ r e g )
(to D P o u tp u t m u x ) s h ift in r ig h t (s ir ) R o u te d ( fr o m in te r c o n n e c t)
s o l_ m s b _ r e g C h a in e d (fr o m p r e v D a ta p a th )

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 229

Universal Digital Blocks (UDBs)

Note that the bits that are isolated by the MSB selection are
still shifted. In the example shown, bit 7 still shifts in the sil Table 23-14. Datapath Inputs
value on a right shift and bit 5 shifts in bit 4 on a left shift. Input Description
The shift out either right or left from the isolated bits is lost. Asynchronous dynamic configuration RAM address. There are
RAD2 eight 16-bit words, which are user programmable. Each word
RAD1 contains the datapath control bits for the current cycle.
ALU Masking Operation RAD0 Sequences of instructions can be controlled by these address
inputs.
An 8-bit mask register in the UDB static configuration regis-
When asserted in a given cycle, the selected FIFO is loaded
ter space defines the masking operation. In this operation, with data from one of the A0 or A1 accumulators or from the
the output of the ALU is masked (ANDed) with the value in F0 LD output of the ALU. The source is selected by the Fx
F1 LD INSEL[1:0] configuration bits. This input is edge sensitive. It is
the mask register. A typical use for the ALU mask function is sampled at the datapath clock; when a '0' to '1' transition is
to implement free-running timers and counters in power of detected, a load occurs at the subsequent clock edge.
two resolutions. When asserted in a given cycle, the Dx register is loaded from
D0 LD associated FIFO Fx. This input is edge sensitive. It is sampled
D1 LD at the datapath clock; when a '0' to '1' transition is detected, a
23.3.2.5 Datapath Inputs and Multiplexing load occurs at the subsequent clock edge.
This is a data input value that can be used for either shift in left
The datapath has a total of nine inputs as shown in Table SI
or shift in right.
24-16, including six inputs from the channel routing. These
This is the carry in value used when the carry in select control
consist of the configuration RAM address, FIFO and data CI
is set to "routed carry."
register load control signals, and the data inputs shift in and
carry in. As shown in Figure 23-17, each input has a 6-to-1 multi-
plexer, therefore, all inputs are permutable. Inputs are han-
dled in one of two ways, either level sensitive or edge
sensitive. RAM address, shift in and data in values are level
sensitive; FIFO and data register load signals are edge sen-
sitive.

Figure 23-17. Datapath Input Select

{0, dp_in[5:0], 0} rad0

(similar for rad1, rad2, si, ci)

CFGx
RAD0 MUX[2:0]
These inputs are
edge sensitive
{0, dp_in[5:0], 0} f0_ld
(similar for f1_ld, d0_ld, d1_ld)

CFGx
F0 LD MUX[2:0]

23.3.2.6 CRC/PRS Support Figure 23-18 shows the structural configuration for the CRC
operation. The PRS configuration is identical except that the
The datapath can support Cyclic Redundancy Checking
shift in (SI) is tied to '0'. In the PRS configuration, D0 or D1
(CRC) and Pseudo Random Sequence (PRS) generation.
contain the polynomial value, while A0 or A1 contain the ini-
Chaining signals are routed between datapath blocks to
tial (seed) value and the CRC residual value at the end of
support CRC/PRS bit lengths of longer than 8 bits.
the computation.
The most significant bit (MSB) of the most significant block
To enable CRC operation, the CFB_EN bit in the dynamic
in the CRC/PRS computation is selected and routed (and
configuration RAM must be set to '1'. This enables the AND
chained across blocks) to the least significant block. The
of SRCB ALU input with the CRC feedback signal. When set
MSB is then XORed with the data input (SI data) to provide
to zero, the feedback signal is driven to '1', which allows for
the feedback (FB) signal. The FB signal is then routed (and
normal arithmetic operation. Dynamic control of this bit on a
chained across blocks) to the most significant block. This
cycle-by-cycle basis gives the capability to interleave a
feedback value is used in all blocks to gate the XOR of the
CRC/PRS operation with other arithmetic operations.
polynomial (from the Data0 or Data1 register) with the cur-
rent accumulator value.

230 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

Figure 23-18. CRC Functional Structure

D0/D1
(POLY)

A0/A1
(CRC)

MSB
(most significant bit) FB SI
(feedback) (shift in)
srcb srca Tie input to
zero for PRS
ALU operation
(XOR)

SHIFTER
(LEFT)

CRC/PRS Chaining
Figure 23-19 illustrates an example of CRC/PRS chaining across three UDBs. This scenario can support a 17- to 24-bit oper-
ation. The chaining control bits are set according to the position of the datapath in the chain as shown.

Figure 23-19. CRC/PRS Chaining Configuration

Set msb_sel CHAIN MSB = 1 CHAIN MSB = 1

CHAIN FB = 1 CHAIN FB = 1

cmsbi cmsbo cmsbi cmsbo cmsbi cmsbo

UDB 2 UDB 1 UDB 0 sir CRC data in
cfbo cfbi cfbo cfbi cfbo cfbi

How the CRC/PRS feedback signal (cfbo, cfbi) is chained: CRC/PRS Polynomial Specification
■ If a given block is the least significant block, then the As an example of how to configure the polynomial for pro-
feedback signal is generated in that block from the built- gramming into the associated D0/D1 register, consider the
in logic that takes the shift in from the right (sir) and CCITT CRC-16 polynomial, which is defined as x16 + x12
XORs it with the MSB signal. (For PRS, the "sir" signal is +x5 + 1. The method for deriving the data format from the
tied to '0'.) polynomial is shown in Figure 23-20.
■ If a given block is not the least significant block, the
The X0 term is inherently always '1' and therefore does not
CHAIN FB configuration bit must be set and the feed-
need to be programmed. For each of the remaining terms in
back is chained from the previous block in the chain.
the polynomial, a '1' is set in the appropriate position in the
How the CRC/PRS MSB signal (cmsbo, cmsbi) is chained: alignment shown.
■ If a given block is the most significant block, the MSB bit Note This polynomial format is slightly different from the
(according to the polynomial selected) is configured format normally specified in HEX. For example, the CCITT
using the MSB_SEL configuration bits. CRC16 polynomial is typically denoted as 1021H. To con-
■ If a given block is not the most significant block, the vert to the format required for datapath operation, shift right
CHAIN MSB configuration bit must be set and the MSB by one and add a '1' in the MSB bit. In this case, the correct
signal is chained from the next block in the chain. polynomial value to load into the D0 or D1 register is 8810H

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 231

Universal Digital Blocks (UDBs)

Figure 23-20. CCITT CRC16 Polynomial Format

X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0

X16 + X12 + X5 + 1

1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0

CCITT 16-Bit Polynomial is 0x8810

Example CRC/PRS Configuration used, but this feature gives the capability for more elaborate
configurations, such as up to a 16-bit CRC/PRS function in
The following is a summary of CRC/PRS configuration
one UDB using time division multiplexing.
requirements, assuming that D0 is the polynomial and the
CRC/PRS is computed in A0: In this mode, the dynamic configuration RAM bit CFB_EN
1. Select a suitable polynomial (example above) and write still controls whether the CRC feedback signal is ANDed
it into D0. with the SRCB ALU input. Therefore, as with the built-in
2. Select a suitable seed value (for example, all zeros for CRC/PRS operation, the function can be interleaved with
CRC, all ones for PRS) and write it into A0. other functions if desired.
3. Configure chaining if necessary as described above.
4. Select the MSB position as defined in the polynomial
from the MSB_SEL static configuration register bits and
set the MSB_EN register bit.
5. Configure the dynamic configuration RAM word fields:
a. Select D0 as the ALU "SRCB" (ALU B Input Source)
b. Select A0 as the ALU "SRCA" (ALU A Input Source)
c. Select "XOR" for the ALU function
d. Select "SHIFT LEFT" for the SHIFT function
e. Select "CFB_EN" to enable the support for CRC/
PRS
f. Select ALU as the A0 write source
If a CRC operation, configure "shift in right" for input data
from routing and supply input on each clock. If a PRS opera-
tion, tie "shift in right" to '0'.

Clocking the UDB with this configuration generates the

required CRC or outputs the MSB, which may be output to
the routing for the PRS sequence.

External CRC/PRS Mode

A static configuration bit may be set (EXT CRCPRS) to
enable support for external computation of a CRC or PRS.
As shown in Figure 23-21, computation of the CRC feed-
back is done in a PLD block. When the bit is set, the CRC
feedback signal is driven directly from the CI (Carry In) data-
path input selection mux, bypassing the internal computa-
tion. The figure shows a simple configuration that supports
up to an 8-bit CRC or PRS. Normally the built-in circuitry is

232 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

Figure 23-21. External CRC/PRS Mode

PLD

Tie shift in to
SI
zero for PRS
(shift in)
operation

Routing Routing

D0/D1
(POLY)
When the
A0/A1 EXT_CRCPRS bit is
(CRC) set, the CI selection
drives the CRC
feedback line.
MSB FB
(Most Significant Bit)

DP Inputs
(feedback)
CI Mux
srcb srca

ALU
(XOR)

SHIFTER
(LEFT) SI Mux

23.3.2.7 Datapath Outputs and Multiplexing There are a total of six datapath outputs. As shown in
Figure 23-22, each output has a 16-1 multiplexer that allows
Conditions are generated from the registered accumulator
any of these 16 signals to be routed to any of the datapath
values, ALU outputs, and FIFO status. These conditions can
outputs.
be driven to the digital routing for use in other UDB blocks,
for use as interrupts or DMA requests, or to I/O pins. The 16 Figure 23-22. Output Mux Connections
possible conditions are shown in the table below:
Output Mux
Table 23-15. Datapath Condition Generation
Name Condition Chain? Description
ce0
ce0 Compare Equal Y A0 == D0 0
cl0
1
cl0 Compare Less Than Y A0 < D0
z0
2

z0 Zero Detect Y A0 == 00h

ff0 Ones Detect Y A0 = FFh ff0
3

A1 or A0 == D1 or A0 ce1
4

ce1 Compare Equal Y

Output Mux (6 - 16 to 1)

(dynamic selection)
cl1
5

A1 or A0 < D1 or A0
cl1 Compare Less Than Y
(dynamic selection) z1
6

z1 Zero Detect Y A1 == 00h

6
ff1 dp_out[5:0]
7

ff1 Ones Detect Y A1 == FFh

ov_msb
8

ov_msb Overflow N Carry(msb) ^ Carry(msb-1)

co_msb
14 13 12 11 10 9

Carry out of MSB defined

co_msb Carry Out Y
bit cmsb
sor
cmsb CRC MSB Y MSB of CRC/PRS function
so Shift Out Y Selection of shift output sol_msb
f0_blk_stat
Definition depends on FIFO
f0_blk_stat FIFO0 Block Status N
configuration f1_blk_stat

Definition depends on FIFO f0_bus_stat

f1_blk_stat FIFO1 Block Status N
configuration
15

f1_bus_stat
Definition depends on FIFO
f0_bus_stat FIFO0 Bus Status N
configuration
Definition depends on FIFO
f1_bus_stat FIFO1 Bus Status N
configuration

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 233

Universal Digital Blocks (UDBs)

Compares dynamic RAM bit selects one of the A or B configurations on

a cycle-by-cycle basis.
There are two compares, one of which has fixed sources
(Compare 0) and the other has dynamically selectable Table 23-16. Compare Configuration
sources (Compare 1). Each compare has an 8-bit statically
CMP SEL A
programmed mask register, which enables the compare to Comparator 1 Compare Configuration
CMP SEL B
occur in a specified bit field. By default, the masking is off
00 A1 Compare to D1
(all bits are compared) and must be enabled.
01 A1 Compare to A0
Comparator 1 inputs are dynamically configurable. As 10 A0 Compare to D1
shown in the table below, there are four options for Compar- 11 A0 Compare to A0
ator 1, which applies to both the "less than" and the "equal"
conditions. The CMP SELA and CMP SELB configuration Compare 0 and Compare 1 are independently chainable to
bits determine the possible compare configurations. A the conditions generated in the previous datapath (in
addressing order). Whether to chain compares or not is stat-
ically specified in UDB configuration registers. Figure 23-23
illustrates compare equal chaining, which is just an ANDing
of the compare equal in this block with the chained input
from the previous block.

Figure 23-23. Compare Equal Chaining

CFGx
CCHAIN0

ce0
(to routing ce0i
and chaining) (from chaining)

Compare Equal

Figure 23-24 illustrates compare less than chaining. In this case, the “less than” is formed by the compare less than output in
this block, which is unconditional. This is ORed with the condition where this block is equal, and the chained input from the
previous block is asserted as less than.

Figure 23-24. Compare Less Than Chaining

CFGx
CCHAIN0

cl0 cl0i
(to routing (from chaining)
and chaining)

Compare Compare
Less Than Equal

234 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

All Zeros and All Ones Detect the currently defined MSB as specified by the MSB_SEL
bits. This condition is not chainable, however the computa-
Each accumulator has dedicated all zeros detect and all
tion is valid when done in the most significant datapath of a
ones detect. These conditions are statically chainable as
multi-precision function as long as the carry is chained
specified in UDB configuration registers. Whether to chain
between blocks.
these conditions is statically specified in UDB configuration
registers. Chaining of zero detect is the same concept as
23.3.2.8 Datapath Parallel Inputs and Outputs
the compare equal. Successive chained data is ANDed if
the chaining is enabled. As shown in Figure 23-25, the datapath Parallel In (PI) and
Parallel Out (PO) signals give limited capability to bring
Overflow routed data into and out of the Datapath. Parallel Out signals
are always available for routing as the ALU asrc selection
Overflow is defined as the XOR of the carry into the MSB
between A0 and A1.
and the carry out of the MSB. The computation is done on
Figure 23-25. Datapath Parallel In/Out

PI[7:0] A0[7:0] A1[7:0]

CFB_EN

PI DYN 1 0
(static config bit)
ASRC[7:0]
PI SEL
(static config bit)
Alu

PO[7:0]

Parallel In needs to be selected for input to the ALU. There 23.3.2.9 Datapath Chaining
are two options, static operation or dynamic operation. For
Each datapath block contains an 8-bit ALU, which is
static operation, the PI SEL bit forces the ALU asrc to be PI.
designed to chain carries, shifted data, capture triggers, and
The PI DYN bit is used to enable the PI dynamic operation.
conditional signals to the nearest neighbor datapaths, to
When it is enabled, and assuming the PI SEL is 0, the PI
create higher precision arithmetic functions and shifters.
multiplexer may then be controlled by the CFB_EN dynamic
These chaining signals, which are dedicated signals, allow
control bit. The primary function of the CFB_EN bit is to
single-cycle 16-, 24- and 32-bit functions to be efficiently
enable PRS/CRC functionality.
implemented without the timing uncertainty of channel rout-
ing resources. In addition, the capture chaining supports the
ability to perform an atomic read of the accumulators in
chained blocks. As shown in Figure 23-21, all generated
conditional and capture signals chain in the direction of least
significant to most significant blocks. Shift left also chains
from least to most significant. Shift right chains from most to
least significant. The CRC/PRS chaining signal for feedback
chains least to most significant; the MSB output chains from
most to least significant.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 235

Universal Digital Blocks (UDBs)

Figure 23-26. Datapath Chaining Flow

CE0 CE0i CE0 CE0i CE0 CE0i 0

CL0 CL0i CL0 CL0i CL0 CL0i 0
CE1 CE1i CE1 CE1i CE1 CE1i 0
CL1 CL1i CL1 CL1i CL1 CL1i 0
Z0 Z0i Z0 Z0i Z0 Z0i 0
Z1 Z1i Z1 Z1i Z1 Z1i 0
FF0 FF0i FF0 FF0i FF0 FF0i 0
FF1 UDB2 FF1i FF1 UDB1 FF1i FF1 UDB0 FF1i 0
CAP0 CAP0i CAP0 CAP0i CAP0 CAP0i 0
CAP1 CAP1i CAP1 CAP1i CAP1 CAP1i 0
CO_MSB CI CO_MSB CI CO_MSB CI 0
SOL_MSB SIR SOL_MSB SIR SOL_MSB SIR 0
CFBO CFBI CFBO CFBI CFBO CFBI 0
0 SIL SOR SIL SOR SIL SOR
0 CMSBI CMSBO CMSBI CMSBO CMSBI CMSBO

23.3.2.10 Dynamic Configuration RAM An additional asynchronous read port is provided as a fast
path to output these 16-bit words as control bits to the data-
Each datapath contains a 16 bit-by-8 word dynamic configu-
path. The asynchronous address inputs are selected from
ration RAM, which is shown in Figure 23-27. The purpose of
datapath inputs and can be generated from any of the possi-
this RAM is to control the datapath configuration bits on a
ble signals on the channel routing, including I/O pins, PLD
cycle-by-cycle basis, based on the clock selected for that
outputs, control block outputs, or other datapath outputs.
datapath. This RAM has synchronous read and write ports
The primary purpose of the asynchronous read path is to
for purposes of loading the configuration via the system bus.
provide a fast single-cycle decode of datapath control bits.

Figure 23-27. Configuration RAM I/O

16

Datapath Control
Read/Write

Inputs
Decoder
Address

bus_addr
Address Decoder

UDBLocal Bus
[2:0] bus_data[15:0]
Read Only

16 Bit-by-8 Word RAM

rad[2:0] Array
Wr Ctrl

wrl
RO R/W wrh
Read Read
16 16

Config RAM
dyn_cfg_ram rd
[15:0] dpram

The fields of this dynamic configuration RAM word are shown in the following tables. A description of the usage of each field
follows.

Register Address 15 14 13 12 11 10 9 8
61h - 6Fh
CFGRAM FUNC[2:0] SRCA SRCB[1:0] SHIFT[1:0]
(Odd)

Register Address 7 6 5 4 3 2 1 0
60h - 6Eh
CFGRAM A0 WRSRC[1:0] A1 WRSRC[1:0] CFB EN CI SEL SI SEL CMPSEL
(Even)

236 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

Table 23-17. Dynamic Configuration Quick Reference

Field Bits Parameter Values
000 PASS
001 INC SRCA
010 DEC SRCA
011 ADD
FUNC[2:0] 3 ALU Function
100 SUB
101 XOR
110 AND
111 OR
0 A0
SRCA 1 ALU A Input Source
1 A1
00 D0
01 D1
SRCB 2 ALU B Input Source
10 A0
11 A1
00 PASS
01 Left Shift
SHIFT[1:0] 2 SHIFT Function
10 Right Shift
11 Nibble Swap
00 None
A0 WR 01 ALU
2 A0 Write Source
SRC[1:0] 10 D0
11 F0
00 None
A1 WR 01 ALU
2 A1 Write Source
SRC[1:0] 10 D1
11 F1
0 Enable
CFB EN 1 CRC Feedback Enable
1 Disable
0 ConfigA
CI SEL 1 Carry In Configuration Select
1 ConfigBa
0 ConfigA
SI SEL 1 Shift In Configuration Select
1 ConfigBa
0 ConfigA
CMP SEL 1 Compare Configuration Select
1 ConfigBa
a. For CI, SI, and CMP, the RAM fields select between two predefined static settings. See Static Register Configuration.

23.3.3 Status and Control Module

A high level view of the Status and Control module is shown in Figure 23-28. The Control register drives into the routing to
provide firmware control inputs to UDB operation. The Status register read from routing provides firmware a method of moni-
toring the state of UDB operation.

Figure 23-28. Status and Control Registers

System Bus

8-Bit Status Register 8-Bit Control Register

(Read Only) (Write/Read)

Routing Channel

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 237

Universal Digital Blocks (UDBs)

A more detailed view of the Status and Control module is shown in Figure 23-29. The primary purpose of this block is to coor-
dinate CPU firmware interaction with internal UDB operation. However, due to its rich connectivity to the routing matrix, this
block may be configured to perform other functions.

Figure 23-29. Status and Control Module

Status and Control Module

7-Bit 7-Bit
Period Register Mask Register
(same as Mask) Interrupt (same as Period)
EN/LD CTL Gen
From 8-Bit 7-Bit 8-Bit To
Datapath Control Register Down Count Status Register Datapath
Parallel TC CNT INT Parallel
Output 7 8 Input
8
(po[7:0]) 8 (pi[7:0])
8 8 4
sc_in[3:0]

4-Bit Sync
8
CFGx
3
SC OUT
CTL[1:0]

CFGx
8 INT MD
CFGx
SYNC MD 8

sc_out[7:0] sc_io_out[3] sc_io_out[2:0] {sc_io_in[3:0],sc_in[3:0]}

Horizontal Channel Routing

Modes of operation include:

■ Status Input – The state of routing signals can be input
and captured as status and read by the CPU or DMA.
■ Control Output – The CPU or DMA can write to the
control register to drive the state of the routing.
■ Parallel Input – To datapath parallel input.
■ Parallel Output – From datapath parallel output.
■ Counter Mode – In this mode, the control register oper-
ates as a 7-bit down counter with programmable period
and automatic reload. Routing inputs can be configured
to control both the enable and reload of the counter.
When this mode is enabled, control register operation is
not available.
■ Sync Mode – In this mode, the status register operates
as a 4-bit double synchronizer. When this mode is
enabled, status register operation is not available.

23.3.3.1 Status and Control Mode

When operating in status and control mode, this module
functions as a status register, interrupt mask register, and
control register in the configuration shown in Figure 23-30
on page 239.

238 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

Figure 23-30. Status and Control Operation

00: Read Transparently

01: Sticky, Clear on Read

CFGx
STAT MD[7:0]

System Bus

Read Read Read

Write Only Write

Reset 8-Bit Control 8-Bit Status 7 7 7-Bit Mask

(Routed Reset Register Register Register
from Reset and Clock
Control Block
7

ACTL
CFGx INT EN
SC OUT
CTL[1:0]
INT
SC OUT CTL bits must
be set to select Control CFGx
register bits for output 8 INT MD
8

sc_out[7:0] {sc_io_in[3:0],sc_in[3:0] sc_io_out[3]

Status Register Operation Sticky Status, with Clear on Read

One 8-bit, read only status register is available for each In this mode, the status register inputs are sampled on each
UDB. Inputs to this register come from any signal in the digi- cycle of the status and control clock. If the signal is high in a
tal routing fabric. The Status register is nonretention; it loses given sample, it is captured in the status bit and remains
its state across sleep intervals and is reset to 0x00 on high, regardless of the subsequent state of the input. When
wakeup. Each bit can be independently programmed to the CPU or DMA reads the status register the bit is cleared.
operate in one of two ways, as shown below: The status register clearing is independent of mode and
occurs even if the UDB clock is disabled; it is based on the
Table 23-18. Status Register bus clock and occurs as part of the read operation.
STAT MD Description
Transparent read. A read returns the current value of the Status Latching During Read
0
routed signal.
Figure 23-31 on page 240 shows the structure of the status
Sticky, clear on read. A high on the input is sampled and cap-
1
tured. It is cleared when the register is read. read logic. The sticky status register is followed by a latch,
which latches the status register data and holds it stable dur-
An important feature of the status register clearing operation ing the duration of the read cycle, regardless of the number
is to note that the clear of status is only applied to the bits of wait states in a given read.
that are set. This allows other bits that are not set to con-
tinue to capture status, so that a coherent view of the pro-
cess can be maintained.

Transparent Status Read

By default, a CPU read of this register transparently reads
the state of the associated routing net. This mode can be
used for a transient state that is computed and registered
internally in the UDB.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 239

Universal Digital Blocks (UDBs)

Figure 23-31. Status Read Logic

Sticky Status Register Bit
Status Latch

UDB Local Bus

from Routing

UDB Status Read

sc_clk

force_lat_open
UDB Status Read

Interrupt Generation output of the control register is driven directly to the routing
on that write cycle.
In most functions, interrupt generation is tied to the setting of
status bits. As shown in Figure 23-31, this feature is built Figure 23-32. Control Register Direct Mode
into the status register logic as the masking and OR reduc-
tion of status. Only the lower 7 bits of status input can be To
Data Bus
used with the built-in interrupt generation circuitry. The most Routing
significant bit is typically used as the interrupt output and
may be routed to the interrupt controller through the digital
routing. In this configuration, the MSB of the status register
Bus
is read as the state of the interrupt bit. Write
Clock
23.3.3.2 Control Register Operation
One 8-bit control register is available for each UDB. This Control Register Sync Mode
operates as a standard read/write register on the system
bus, where the output of these register bits are selectable as In Sync mode, as shown in Figure 23-33, the control register
drivers into the digital routing fabric. output is driven by a re-sampling register clocked by the cur-
rently selected Status and Control (SC) clock. This allows
The Control register is nonretention; it loses its contents the timing of the output to be controlled by the selected SC
across sleep intervals and is reset to 0x00 on wakeup. clock, rather than the bus clock.

Control Register Operating Modes Figure 23-33. Control Register Sync Mode

There are three available modes that may be configured on To

Data Bus
a bit-by-bit basis. The configuration is controlled by the con- Routing
catenation of the bits of the two 8-bit registers
CTL_MD1[7:0] and CTL_MD0[7:0]. For example
{CTL_MD1[0],CTL_MD0[0]} controls the mode for Control Bus
Register bit 0, as shown in Figure 23-19. Write SC CLK
Clock
Table 23-19. Mode for Control Register Bit 0
CTL MD Description Control Register Pulse Mode
00 Direct mode
Pulse mode is similar to Sync mode in that the control bit is
01 Sync mode
re-sampled by the SC clock; the pulse starts on the first SC
10 (reserved)
clock cycle following the bus write cycle. The output of the
11 Pulse mode control bit is asserted for one full SC clock cycle. At the end
of this clock cycle, the control bit is automatically reset.
Control Register Direct Mode
With this mode of operation, firmware can write a 1 to a con-
The default mode is Direct mode. As shown in Figure 23-32, trol register bit to generate a pulse. After it is written as a 1 it
when the Control Register is written by the CPU or DMA the

240 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

will be read back by firmware as a 1 until the completion of Control Register Reset
the pulse, after which it will be read back as a 0. The firm-
The control register has two reset modes, controlled by the
ware can then write another 1 to start another pulse. A new
EXT RES configuration bit, as shown in Figure 23-34. When
pulse cannot be generated until the previous one has been
EXT RES is 0 (the default) then in sync or pulse mode the
completed. Therefore the maximum frequency of pulse gen-
routed reset input resets the synced output but not the
eration is every other SC clock cycle.
actual control bit. When EXT RES is 1 then the routed reset
input resets both the control bit and the synced output.

Figure 23-34. Control Register Reset

Routed Reset

0 To
EXT RES
Routing
1
Static configuration Data Bus res res
bit
Bit by Bit
CFG

Bus
Write SC CLK
Clock

23.3.3.3 Parallel Input/Output Mode datapath parallel out. The parallel input connection is always
available, but these routing connections are shared with the
In this mode, the status and control routing is connected to
status register inputs, counter control inputs, and the inter-
the datapath parallel in and parallel out signals. To enable
rupt output.
this mode, the SC OUT configuration bits are set to select
Figure 23-35. Parallel Input/Output Mode

Datapath

po[7:0] pi[7:0]
Datapath Datapath
Parallel Out Parallel In
SC OUT CTL bits must
be set to select
8 8 The INT MD and SYNC
datapath parallel out bits
MD control bits should
for output to routing.
be cleared to enable
SC_IO bits to input mode.

sc_out[7:0] {sc_io_in[3:0], sc_in[3:0]}

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 241

Universal Digital Blocks (UDBs)

23.3.3.4 Counter Mode ■ In default mode the terminal count is registered. In alter-
nate mode the terminal count is combinational.
As shown in Figure 23-36, when the block is in counter
■ In default mode, the routed enable, if used, must be
mode, a 7-bit down counter is exposed for use by UDB inter-
nal operation or firmware applications. This counter has the asserted for routed load to operate. In alternate mode
following features: the routed enable and routed load signals operate inde-
pendently.
■ A 7-bit read/write period register.
■ A 7-bit read/write count register. It can be accessed only To enable the counter mode, the SC_OUT_CTl[1:0] bits
when the counter is disabled. must be set to counter output. In this mode the normal oper-
ation of the control register is not available. The status regis-
■ Automatic reload of the period to the count register on
ter can still be used for read operations, but should not be
terminal count (0).
used to generate an interrupt because the mask register is
■ A firmware control bit in the Auxiliary Control Working reused as the counter period register. The Period register is
register called CNT START, to start and stop the counter. retention and will maintain its state across sleep intervals.
(This is an overriding enable and must be set for optional For a period of N clocks, the period value of N-1 should be
routed enable to be operational.) loaded. N = 1 (period of 0) is not supported as a clock divide
■ Selectable bits from the routing for optional dynamic value, and will result in the terminal count output of a con-
control of the counter enable and load functions: stant 1.The use of SYNC mode depends on whether or not
❐ EN, routed enable to start or stop counting. the dynamic control inputs (LD/EN) are used. If they are not
used, SYNC mode is unaffected. If they are used, SYNC
❐ LD, routed load signal to force the reload of period.
mode is unavailable.
When this signal is asserted, it overrides a pending
terminal count. It is level sensitive and continues to
load the period while asserted.
■ The 7-bit count may be driven to the routing fabric as
sc_out[6:0].
■ The terminal count may be driven to the routing fabric as
sc_out[7].

Figure 23-36. Counter Mode

P3B Bus System Bus

Read Read
Only* Write
*Current count value is
only readable when 7-Bit Period
not enabled.
Register

0: Reload is only controlled by terminal count

1: Reload is also controlled by routing
Routed Reset from CFGx
Reset and Clock RES LD ROUTE LD
Control Block 7-Bit Counter CFGx
EN ROUTE EN
0: Enable is only controlled by firmware
ACTL 1: Enable is also controlled by routing
Zero CNT START
Detect

Terminal
Count CFGx CFGx
(TC) EN SEL[1:0] LD SEL[1:0]

SC OUT CTL bits must be set 7 The INT MD and SYNC 4 4

to select the counter output MD bits should be
as the selected output to [7:4] [3:0]
cleared to configure the
routing. SC_IO bits to input mode.
sc_out[7] sc_out[6:0]
8

{sc_io_in[3:0], sc_in[3:0]}

242 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

23.3.3.5 Sync Mode 23.3.3.7 Auxiliary Control Register

As shown in Figure 23-37, the status register can operate as The read-write Auxiliary Control register is a special register
a 4-bit double synchronizer, clocked by the current SC_CLK, that controls fixed function hardware in the UDB. This regis-
when the SYNC MD bit is set. This mode may be used to ter allows CPU or DMA to dynamically control the interrupt,
implement local synchronization of asynchronous signals, FIFO, and counter operation. The register bits and descrip-
such as GPIO inputs. When enabled, the signals to be syn- tions are:
chronized are selected from SC_IN[3:0], the outputs are
driven to the SC_IO_OUT[3:0] pins, and SYNC MD auto- Auxiliary Control Register
matically puts the SC_IO pins into output mode. When in 7 6 5 4 3 2 1 0

this mode, the normal operation of the status register is not CNT FIFO1 FIFO0 FIFO1 FIFO0
INT EN
START LVL LVL CLR CLR
available, and the status sticky bit mode is forced off,
regardless of the control settings for this mode. The control
register is not affected by the mode. The counter can still be FIFO0 Clear, FIFO1 Clear
used with limitations. No dynamic inputs (LD/EN) to the
The FIFO0 CLR and FIFO1 CLR bits are used to reset the
counter can be enabled in this mode.
state of the associated FIFO. When a '1' is written to these
Figure 23-37. Sync Mode bits, the state of the associated FIFO is cleared. These bits
must be written back to '0' to allow FIFO operation to con-
Sync Module (Status Register) tinue. When these bits are left asserted, the FIFOs operate
as simple one-byte buffers, without status.

FIFO0 Level, FIFO1 Level

The FIFO0 LVL and FIFO1 LVL bits control the level at
7 6 5 4 3 2 1 0 which the 4-byte FIFO asserts bus status (when the bus is
either reading or writing to the FIFO) to be asserted. The
meaning of FIFO bus status depends on the configured
direction, as shown in the table below.

4 4 Table 23-20. FIFO Level Control Bits

CFGx FIFOx Input Mode Output Mode
SYNC MD LVL (Bus is Writing FIFO) (Bus is Reading FIFO)
sc_io_out[3:0] sc_in[3:0] Not Full Not Empty
0
At least 1 byte can be written At least 1 byte can be read
Digital Routing
At Least Half Empty At Least Half Full
1
At least 2 bytes can be written At least 2 bytes can be read

23.3.3.6 Status and Control Clocking

Interrupt Enable
The status and control registers require a clock selection for
any of the following operating modes: When the status register’s generation logic is enabled, the
■ Status register with any bit set to sticky, clear on read INT EN bit gates the resulting interrupt signal.
mode.
Count Start
■ Control register in counter mode.
The CNT START bit may be used to enable and disable the
■ Sync mode.
counter (only valid when the SC_OUT_CTL[1:0] bits are
The clock for this is allocated in the reset and clock control configured for counter output mode).
module. See 23.3.4 Reset and Clock Control Module on
page 244.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 243

Universal Digital Blocks (UDBs)

23.3.3.8 Status and Control Register

Summary
The table below summarizes the function of the status and
control registers. Note that the control and mask registers
are shared with the count and period registers and the
meaning of these registers is mode dependent.

Table 23-21. Status, Control Register Function Summary

Mode Control/Count Status/SYNC Mask/Period
Control Control Out Status Mask
Status In or SYNC
Count Count Out Count Perioda
Status Status In Status Mask
Control Out or Count Out
SYNC SYNC NAb
a. Note that in counter mode, the mask register is operating as a period
register and cannot function as a mask register. Therefore, interrupt out-
put is not available when counter mode is enabled.
b. Note that in SYNC mode, the status register function is not available, and
therefore, the mask register is unusable. However, it can be used as a
period register for count mode.

23.3.4 Reset and Clock Control Module

The primary function of the reset and clock block is to select
a clock from the available global system clocks or bus clock
for each of the PLDs, the datapath, and the status and con-
trol block. It also supplies dynamic and firmware-based
resets to the UDB blocks. As shown in Figure 23-38, there
are four clock control blocks, and one reset block. Four
inputs are available for use from the routing matrix
(RC_IN[3:0]). Each clock control block can select a clock
enable source from these routing inputs, and there is also a
multiplexer to select one of the routing inputs to be used as
an external clock source. As shown, the external clock
source selection can be optionally synchronized. There are
a total of 10 clocks that can be selected for each UDB com-
ponent: 8 global digital clocks, bus clock, and the selected
external clock (ext clk). Any of the routed input signals
(rc_in) can be used as either a level sensitive or edge sensi-
tive enable. The reset function of this block provides a
routed reset for the PLD blocks and SC counter, and a firm-
ware reset capability to each block to support reconfigura-
tion.

The bus clock input to the reset and clock control is distinct
from the system bus clock. This clock is called
“bus_clk_app” because it is gated just like the other global
digital clocks and used for UDB applications. The system
bus clock is only used for I/O access and is automatically
gated, per access. The datapath clock generator produces
three clocks: one for the datapath in general, and one for
each of the FIFOs.

244 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

Figure 23-38. Reset and Clock Control

global_enable

From channel routing bus_clk_app, gclks[7:0]

PLD0
rc_in_gated[3:0] Clock
rc_in[3:0] pld0_clk (to PLD0)
Select/Enable

ext_clk

2
bus_clk PLD1
CFGx CFGx Clock pld1_clk (to PLD1)
EXT CLK SEL[1:0] EXT SYNC Select/Enable

dp_clk (to Datapath)

DP
Clock f0_clk (to FIFO0)
Select/Enable
f1_clk (to FIFO1)

SC
Clock sc_clk (to Status and Control)
Select/Enable

mf
rc_in_gated[3:0]
cnt_routed_ reset (to SC counter)
sysreset Reset
pld0_reset (firmware/system reset)
Select/Enable
pld1_reset (firmware/system reset)
sc_reset (firmware/system reset)
dp_reset (firmware/system reset)

23.3.4.1 Clock Control

Figure 23-39 illustrates one instance of the clock selection and enable circuit. There are four of these circuits in each UDB:
one for each of the PLD blocks, one for the datapath, and one for the status and control block. The main components of this
circuit are a global clock selection multiplexer, clock inversion, clock enable selection multiplexer, clock enable inversion, and
edge detect logic.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 245

Universal Digital Blocks (UDBs)

Figure 23-39. Clock Select/Enable Control

3
1 2 Latch clk
rc_in_gated[3:0] 0 FF 1 1
0 0

2 2 2

CFGx CFGx CFGx

EN SEL[1:0] EN INV EN MODE[1:0]
Enable Select Enable Invert Enable Mode
00: rc_in[0] 0: true 00: off
01: rc_in[1] 1: inverted 01: on
10: rc_in[2] 10: positive edge
11: rc_in[3] 11: level

{bus_clk_app,ext_clk, gclk[7:0]} 0

Clock Select 4 2
0000: gclk[0] 0100: gclk[4] Clock Invert
CFGx CFGx 0: true
0001: gclk[1] 0101: gclk[5]
CK SEL[3:0] CK INV
0010: gclk[2] 0110: gclk[6] 1: inverted
0011: gclk[3] 0111: gclk[7]
1000: ext_clk
1001: bus_clk_app

Clock Selection Clock Enable Inversion

There are eight global digital clocks routed to all UDBs; any The clock enable signal may be optionally inverted. This
of these clocks may be selected. Global digital clocks are feature allows the clock enable to be generated in any
the output of user selectable clock dividers. See the Clock- polarity.
ing System chapter on page 147. Another selection is bus
clock, which is the highest frequency in the system. Called Clock Enable Mode
“bus_clk_app,” this signal is routed separately from the sys- By default, the clock enable is OFF. After configuring the tar-
tem bus clock. In addition, an external routing signal can be get block operation, software can set the mode to one of the
selected as a clock input to support direct-clocked functions following using the CFGxEN MODE[1:0] register shown in
such as SPI. Since application functions are mapped to arbi- Figure 23-39.
trary boundaries across UDBs, individual clock selection for
each UDB subcomponent block supports a fine granularity Table 23-22. Clock Enable Mode
of programming.
Clock Enable
Description
Mode
Clock Inversion OFF Clock is OFF.

The selected clock may be optionally inverted. This limits ON Clock is ON. The selected global clock is free running.
the maximum frequency of operation due to the existence of A gated clock is generated on each positive edge detect of
Positive Edge the clock enable input. Maximum frequency of enable
one half cycle timing paths. Simultaneous bus writes and input is the selected global clock divided by two.
internal writes (for example writing a new count value while
Clocks are generated while the clock enable input is high
a counter is counting) are not supported when the internal Level
('1').
clock is inverted and the same frequency as bus clock. This
limitation affects A0, A1, D0, D1, and the Control register in Clock Enable Usage
counter mode.
There are two general usage scenarios for the clock enable.
Clock Enable Selection Firmware Enable – It is assumed that most functions
The clock enable signal may be routed to any synchronous require a firmware clock enable to start and stop the func-
signal and can be selected from any of the four inputs from tion. Since the boundary of a function mapped into the UDB
the routing matrix that are available to this block. array is arbitrary, i.e., it may span multiple UDBs and/or por-
tions of UDBs, there must be a way to enable a given func-
tion atomically. This is typically implemented from a bit in a

246 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

control register routed to one or more clock enable inputs. ■ Each FIFO clock can be inverted with respect to the
This scenario also supports the case where applications selected datapath clock polarity.
require multiple, unrelated blocks to be enabled simultane- ■ When FIFO FAST mode is set, the bus clock overrides
ously. the datapath clock selection normally in use by the FIFO.
Emulated Local Clock Generation – This feature allows
local clocks to be generated by UDBs, and distributed to 23.3.4.2 Reset Control
other UDBs in the array by using a synchronous clock There are two modes of reset control: legacy mode and
enable implementation scheme, rather than directly clocking standard mode. The modes are controlled by the ALT RES
from one UDB to another. Using the positive edge feature of bit in each UDB configuration register CFG31. The default
the clock enable mode eliminates restrictions on the duty for this bit is 0 (legacy mode); it is recommended that it be
cycle of the clock enable waveform. set to 1 for standard mode. Standard mode has greater
granularity - routed resets can be used by individual blocks
Special FIFO Clocking within the UDB. Contact Cypress for information on legacy
The datapath FIFOs have special clocking considerations. mode reset.
By default, the FIFO clocks follow the same configuration as
the datapath clock. However, the FIFOs have special control PLD Reset Control
bits that alter the clock configuration: Figure 23-40 shows the PLD reset system.

Figure 23-40. PLD Reset Structure

PLD0
pld_routed_reset
rc_in[3:0] M
C
sysreset
2 M SSEL
C routed
CFGx CFGx reset
PLD0 RES SEL[1:0] PLD0 RES POL 1
Reset Select Reset Invert M 0
00: rc_in[0] 0: true C
SSEL
01: rc_in[1] 1: inverted set
D Q
10: rc_in[2] M
11: rc_in[3] C QB
res
1
0

PLD1 System RSEL

Reset
M
C PLD
Macrocell
M
C

M
C

M
C

Datapath Reset Control

Figure 23-41 shows the datapath reset system. The routed reset is applied to all datapath registers and states except the
data registers D0 and D1. The data registers are retention registers. The FIFO data is unknown after reset because it is RAM
based.

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Universal Digital Blocks (UDBs)

Figure 23-41. Datapath Reset Structure

sysreset_ret RES Accumulator

Data Registers

RES Accumulator
Accumulators
Output
Sync
Registers
RES Carry Out
Register
sysrese
t
RES
RES Shift Out
Left
Register

rc_in[3:0]
RES Shift Out
2 Right Register

CFGx CFGx CFGx

DP RES SEL[1:0] DP RES POL EN RES DP
Reset Select Reset Invert ACTL RES
00: rc_in[0] 0: true F0 CLR FIFO0 Status
01: rc_in[1] 1: inverted
10: rc_in[2]
11: rc_in[3]

ACTL RES
F1 CLR FIFO1 Status

248 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

Status and Control Reset Control

Figure 23-42 shows the status and control block reset system. The status and control/count registers share the routed reset,
however they are individually enabled. The mask/period and auxiliary control registers are retention registers.

Figure 23-42. Status and Control Reset Control

sysreset_ret RES Accumulator

Data Registers
All elements of the Datapath are reset by the
selected DP routed reset signal, EXCEPT the
Data Registers
RES Accumulator
Accumulators
Output
Sync
Registers
RES Carry Out
Register
sysreset
Shift Out RES
RES
Left
Register

rc_in[3:0]
RES Shift Out
Right
2 Register
CFGx CFGx CFGx
DP RES SEL[1:0] DP RES POL EN RES DP
Reset Select Reset Invert ACTL RES
00: rc_in[0] 0: true F0 CLR FIFO0 Status
01: rc_in[1] 1: inverted
10: rc_in[2]
11: rc_in[3]
ACTL RES
F1 CLR FIFO1 Status

23.3.4.3 UDB POR Initialization As a result of this initialization, conflicting drive states on the
routing are avoided and initial configuration occurs in an
Register and State Initialization order-independent sequence.

Table 23-23. UDB POR State Initialization

State Element State Element POR State
Configuration Latches CFG 0 - 31 0
Accumulators, data registers,
Ax, Dx, CTL, ACTL, MSK auxiliary control register, 0
mask register
Status and macrocell read
ST, MC 0
only registers
Datapath configuration RAM
DP CFG RAM & Fx (FIFOs) Unknown
and FIFO RAM
PLD RAM PLD configuration RAM Unknown

Routing Initialization
On POR, the state of input and output routing is as follows:
■ All outputs from the UDB that drive into the routing
matrix are held at '0'.
■ All drivers out of the routing and into UDB inputs are ini-
tially gated to '0'.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 249

Universal Digital Blocks (UDBs)

23.3.5 UDB Addressing

There are three unique address spaces in a UDB pair: due to the even address alignment. The upper 4 bits is still
■ 8-Bit Working Registers – A bus master that can only the register number.
access 8 bits of data per bus cycle, such as the PSoC 3 Figure 23-43. UDB Working Registers
8051, can use this address space to read or write any
UDB working register. These are the registers with which 8-Bit 16-Bit
Addresses Addresses
the CPU and DMA interact during normal operation.
UDB Working Base +
■ 16-Bit Working Registers – A bus master with 16-bit
0xh A0 0xh
capability, such as the DMA or the PSoC 5 Cortex-M3,
1xh A1 2xh
can access 16 bits per bus cycle to facilitate the data
2xh 4xh
transfer of functions that are inherently 16 bits or greater. D0
Although this address space is mapped into a different 3xh D1 6xh
area than the 8-bit space, the same registers are 4xh F0 8xh
accessed, two registers at a time. 5xh Axh
F1
■ 8- or 16-Bit Configuration Registers – These registers 6xh Cxh
ST
configure the UDB to perform a function. Once config- 7xh Exh
CTL/CNT
ured, they are normally left in a static state during opera-
8xh MSK/PER 10xh
tion. These registers maintain their state through sleep.
9xh ACTL 12xh

23.3.5.1 Working Register Address Space Axh MC 14xh

Bxh 16xh
Working registers are accessed during normal operation
and include accumulators, data registers, FIFOs, status and
control registers, mask register, and the auxiliary control 8-Bit Working Register Access
register.
In this mode, all UDB registers are accessed on byte-
Figure 23-43 shows the register map for one UDB. aligned addresses. In 8-bit register access mode, as shown
in Figure 23-44, all data bytes written to the UDBs are
On the right in Figure 23-43 is the 16-bit address, which is
aligned with the low byte of the 16-bit UDB bus.
always even aligned. The UDB number is 5 bits instead of 4,
Only one byte at a time can be accessed in this mode.

Figure 23-44. 8-Bit Working Register Access

UDB 2 UDB 1 UDB 0

A0 A0 A0
A1 A1 A1

Low byte Low byte Low byte

16-Bit UDB Array Data Bus

250 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

16-Bit Working Register Address Space

The 16-bit address space is designed for efficient DMA access and to provide support for CPU firmware access in processors
that can support it, such as the Cortex-M3 in PSoC 5. There are two modes of 16-bit register access, the “default” mode and
the “concat” mode. As shown in Figure 23-45, the default mode accesses a given register in UDB 'i' in the lower byte and the
same register in UDB 'i+1' in the upper byte. This makes 16-bit data handling efficient in neighboring UDBs (address order)
that are configured as a 16-bit function.

Figure 23-45. 16-Bit Working Register Default Access Mode

UDB 2 UDB 1 UDB 0

A0 A0 A0
A1 A1 A1

Low byte High byte Low byte High byte Low byte
16 bits at 16 bits at 16 bits at
UDB 2 UDB 1 UDB 0

16-Bit UDB Array Data Bus

In concat mode, the registers of a single UDB are concate- There is a limitation in the use of DMA with respect to the
nated to form 16-bit registers as shown in Figure 23-46. In 16-bit working register address space. It is inefficient for use
this mode, the 16-bit UDB array data bus has access to when the function is greater than 16 bits. This is because
pairs of registers in the UDB in the format shown in the fig- the addressing overlaps, as shown in Table 23-24.
ure. For example, an access at A0 accesses A0 in the low
byte and A1 in the high byte. Table 23-24. Optimized Address Space for 16-Bit UDB
Function
Figure 23-46. 16-Bit Working Register Concat Access
Address Upper Byte Goes Lower Byte Goes
Mode
0 UDB1 UDB0
UDB i 2 UDB2 UDB1
4 UDB3 UDB2
A1 A0
D1 D0
When the DMA transfers 16 bits to address 0, the lower and
F1 F0 upper bytes are written to UDB0 and UDB1, respectively. On
CTL/CNT ST the next 16 bit DMA transfer at address 2, you overwrite the
ACTL MSK/PER value in UDB1 with the lower byte of that transfer.
00h MC To avoid having to provide redundant data organization in
memory buffers to support this addressing, it is recom-
16 bits at
UDB i
mended that 8-bit DMA transfers in the 8-bit working space
High byte Low byte
be used for functions over 16 bits.

16-Bit UDB Array Data Bus

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 251

Universal Digital Blocks (UDBs)

23.3.5.2 Configuration Register Address 23.3.5.4 Routing Configuration Address

Space Space
Configuration is done at the UDB pair level. A UDB pair con- UDB routing configuration consists of embedded RAM bits
sists of two UDBs and an associated routing channel, as to control the state of transmission gate switches, segmen-
shown in Figure 23-47. tation, and input/output buffers. For more information, see
the UDB Array and Digital System Interconnect chapter on
Figure 23-47. UDB Pair Configuration Address Map
page 255.
UDB Pair k Base + 0
UDB i
128 bytes
80h
UDB i+1
128 bytes
UDB Pair k
100h
512 bytes

UDB Pair k Routing

256 bytes

200h

23.3.5.3 UDB Configuration Address Space

Figure 23-48 shows the address map for configuration of a
given UDB. As shown, this UDB configuration space is repli-
cated for the two UDBs in the UDB pair. There are 128 bytes
(7 bits of address) reserved for each UDB configuration,
which is organized in 16-bit width. There are individual byte
write enables for this address space to support both 16- and
8-bit access. Note that 16-bit access on odd boundaries is
not supported. Reads always return 16 bits in configuration
space, and the byte not required can be ignored.

Figure 23-48. UDB Configuration Address Space

Write Write
High Byte Low Byte

00h

PLD0/PLD1
64 bytes
(32 words x 16 bits)

40h
128
UDB Config Registers
bytes
(32 bytes)
(16 words x 16 bits)

60h
Dynamic Configuration RAM
(16 bytes)
(8 words x 16 bits)
70h
Reserved
(16 bytes)

80h (MS Byte) (LS byte)

Read Word
(16 bits)

252 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Universal Digital Blocks (UDBs)

23.3.6 System Bus Access Coherency

UDB registers have dual access modes:
■ System bus access, where the CPU or DMA is reading or writing a UDB register.
■ UDB internal access, where the UDB function is updating or using the contents of a register.

23.3.6.1 Simultaneous System Bus Access

The following table lists the possible simultaneous access events and required behavior:

Table 23-25. Simultaneous System Bus Access

UDB Write UDB Write UDB Read UDB Read
Register
Bus Write Bus Read Bus Write Bus Read
Ax Current value is read
Undefined result Not allowed directlya, b UDB reads previous value
by both
Dx
Not supported (UDB
Not supported (UDB and bus must be If FIFO status flags are used, no simultaneous read/write at the same location is
Fx and bus must be
opposite access) possible
opposite access)
ST NA, bus does not write Bus reads previous value NA, UDB does not read
CTL NA, UDB does not write
CNT Undefined result Not allowed directlyc
ACTL UDB reads previous value Current value is read
MSK NA, UDB does not write by both

PER
MC (RO) NA, bus does not write Not allowed directlyd NA, bus does not write
a. The Ax registers can be safely read by using software capture feature of the FIFOs.
b. The Dx registers can only be written to dynamically by the FIFOs. When this mode is programmed, direct read of the Dx registers is not allowed.
c. The CNT register can only be safely read when it is disabled. An alternative for dynamically reading the CNT value is to route the output to the SC register
(in transparent mode).
d. MC register bits can also be routed to the status register (in transparent mode) inputs for safe reading.

23.3.6.2 Coherent Accumulator Access

(Atomic Reads and Writes)
The UDB accumulators are the primary target of data com-
putation. Therefore, reading these registers directly during
normal operation gives an undefined result, as indicated in
the table above). However, there is built-in support for
atomic reads in the form of software capture, which is imple-
mented across chained blocks. In this usage model, a read
of the least significant accumulator transfers the data from
all chained blocks to their associated FIFOs. This operation
is explained in FIFO Software Capture Mode on page 224.
Atomic writes to the accumulator can be implemented pro-
grammatically. Individual writes can be performed to the
input FIFOs, and then the status signal of the last FIFO writ-
ten can be routed to all associated blocks and simultane-
ously transfer the FIFO data into the Dx or Ax registers.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 253

Universal Digital Blocks (UDBs)

23.4 UDB Working Register Reference

All registers except the FIFO are cleared upon any system reset. The FIFO status is cleared, but FIFO data is random. These
registers are not retention registers so they must be reset upon wakeup from a power cut-off sequence.

8-Bit 16-Bit
Register 7 6 5 4 3 2 1 0
Address Address
Datapath Registers
A0[7:0]
A0 0xh 00xh
(Accumulator 0 Value)
A1[7:0]
A1 1xh 02xh
(Accumulator 1 Value)
D0[7:0]
D0 2xh 04xh
(Data Register 0)
D1[7:0]
D1 3xh 06xh
(Data Register 1)
F0[7:0]
F0 4xh 08xh
(FIFO 0)
F1[7:0]
F1 5xh 0Axh
(FIFO 1)
Status and Control Registers
ST[7:0]
ST 6xh 0Cxh
(Status Register)
CTL[7:0] / CNT[6:0]
CTL/CNT 7xh 0Exh
(Control / Count Register)
MSK[6:0] / PER[6:0]
MSK/PER 8xh 10xh
(Interrupt Mask / Period Register)
Auxiliary Control Register
ACTL 9xh 12xh CNT START INT EN FIFO1 LVL FIFO0 LVL FIFO1 CLR FIFO0 CLR
PLD Macrocell Register
MC Axh 14xh PLD1 MC[3:0] PLD0 MC[3:0]

254 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 24. UDB Array and Digital System Interconnect

This chapter describes the structure of the UDB Array and Digital System Interconnect (DSI). Universal Digital Blocks (UDBs)
are organized in the form of a two-dimensional array with programmable interconnect provided by the DSI. In addition to con-
necting UDB components, the DSI routing also provides connection between other hardware resources on the device, such
as I/O pins, interrupts, and fixed function blocks.

24.1 Features
■ Offers a homogeneous array of UDBs which provide flexible function mapping
■ Provides array level interconnect routing between the components of the UDB hardware
■ Provides device level interconnect routing between UDBs, device peripherals, and I/O pins

24.2 Block Diagram

Figure 24-1 illustrates the programmable digital architecture for PSoC 3 and PSoC 5.
Figure 24-1. Programmable Digital Architecture

Digital Core System

and Fixed Function Peripherals

INT/DMA INT/DMA
Routing Controller
IO Port

IO Port

DSI Routing Interface

UDB UDB UDB UDB

UDB Array

UDB Array

UDB UDB UDB UDB

UDB UDB UDB UDB

UDB UDB UDB UDB

DSI Routing Interface

IO Port

IO Port

Digital Core System

and Fixed Function Peripherals

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 255

UDB Array and Digital System Interconnect

The main components of this system are: system blocks that require connectivity are routed to this
■ UDB Array:- UDB blocks are arrayed within a matrix of interface at the UDB array, which allows connections into
programmable interconnect. UDB pairs consisting of 2 the core of the array or directly between device peripherals.
UDBs are the basic building blocks of the UDB array. Signals in this category include:
UDB pairs are tiled to create an array. UDB pairs can
■ Interrupt requests from all digital peripherals in the sys-
connect with neighboring UDB pairs in seamless fashion
tem
■ DSI- Routing interface tiled at top and bottom of UDB
■ DMA requests from all digital peripherals in the system
array core. Provides general purpose programmable
routing between device peripherals, including UDBs, I/ ■ Digital peripheral data signals that need flexible routing
Os and fixed function blocks. to I/Os

■ System Interface (not shown)- Built in 8/16-bit bus inter- ■ Digital peripheral data signals that need connections to
face with parallel access to all registers to support fast UDBs
configuration. Also provides clock distribution and clock ■ Connections to the interrupt and DMA controllers
gating functionality. ■ Connection to I/O pins
The following section explain in detail the DSI routing and ■ Connection to analog system digital signals
System Interface.
Figure 24-2 and Figure 24-4 show some examples of the
device peripherals that are connected to this interface,
24.3 How It Works including UDBs, I/Os, analog peripherals, interrupts, DMA,
and fixed function peripherals.
The purpose of the DSI is to provide general purpose pro-
grammable connectivity across the device. Peripherals and
Figure 24-2. DSI Example Connections to the Interrupt and DMA Controller

DMA Interrupt CAN Interrupt

request CAN USB
Controller Controller
REQ REQ
USB DMA
request

DSI Routing Interface

UDB DMA Request

UDB UDB UDB

UDB Interrupt
Request

UDB UDB UDB

256 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 UDB Array and Digital System Interconnect

Figure 24-3. DSI Example Connections between Peripherals, I/O Pins, and UDBs

I2C Timer
I/O I/O I/O
Pin Pin SDA SDA SDA SDA Pin EN TC
IN OUT IN OUT

DSI Routing Interface

UDB UDB UDB

UDB UDB UDB

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 257

UDB Array and Digital System Interconnect

24.4 UDB Array System Interface There are eight digital global clocks, plus the application bus
clock, routed to each bank of UDBs. The UDB local interface
The system interface consists of infrastructure blocks that blocks contain clock gating control registers, which must be
distribute and interface the device system bus to the UDB set by configuration firmware to enable clock distribution.
array bus and to the UDB blocks, the DSI channel routing, There are four registers in each block:
and the UDB pair channel routing. Depending on the config- ■ 8-Bit MDCLK_EN (Master Digital Clock Enable) – This
uration of the array, there is one or more AHB interfaces that register individually enables the digital global clocks at
connect to PHUB spokes providing an interface to the UDB the input to the UDB array.
array system bus. Both 8-bit and 16-bit bus access is sup-
■ 1-Bit MBCLK_EN (Master Bus Clock Enable) – This
ported. The system interface also provides support for clock
register individually enables the application bus clock at
distribution and gating for the digital global clocks and bus
the input to the UDB array.
clock. A gated clock tree distribution is implemented to allow
only those clocks that are in use to be activated. ■ 8-Bit DCLK_ENx (Quadrant Digital Clock Enable) – This
register individually enables the digital global clocks to
Following are the system interface components: the associated quadrant (4 UDBs) of the UDB array.
■ AHB Interface – Connects to a standard PHUB spoke ■ 1-Bit BCLK_ENx (Quadrant Bus Clock Enable) – This
and provides support for up to 1 bank of UDBs (16). register individually enables the bus clock to the associ-
Controls array wait states and translates AHB signaling ated quadrant (4 UDBs) of the UDB array. It also con-
into array register and routing configuration access con- tains bits to put the associated routing channel RAM into
trol. global write mode.
■ DSI Channel IF – Interfaces the UDB array bus to the
DSI routing channel for writing and reading configura- 24.4.1 UDB Array POR Initialization
tion.
The key aspects of POR initialization are summarized as fol-
■ UDB Local IF – Interfaces the UDB array bus to the
lows.
UDB blocks for registers and RAM access, and provides
local clock gating. ■ All UDB clocks are gated off. There are three levels of
clock gating configuration: one at the UDB level for each
■ UDB Pair Channel – Interfaces the UDB array bus to
individual block clock control and a set of registers at the
the pair routing channel for writing and reading configu-
array level that controls master and quadrant clock gat-
ration.
ing.
■ Bank IF – Contains the master clock gating and bank
■ The state of all drivers into the routing matrix is gated to
wide configuration interface signals.
‘0’ with a global routing enable control. This includes
■ 8-Bit WAIT_CFG Register – Sets the read and write UDB block outputs, DSI inputs, and segmentation buf-
wait states for working and configuration registers. fers. Since the routing is initialized to a random state, the
■ 4-Bit BANK_CTL Register – Contains global bank con- state of routing nets will be either ‘0’ or ‘Z’.
trol bits. ■ The inputs of all routing output buffers, including seg-
❐ One bit to globally enable all DSI inputs. On POR, all mentation buffers, are gated to ‘0’ with a global routing
DSI inputs are gated off until the DSI channel is con- enable control. This prevents floating routes from caus-
figured. This bit globally enables DSI inputs to drive ing high power states. This also drives the buffer outputs
the routing. to ‘0’ and that is the state for all DSI outputs.
❐ One to disable all UDB status register clear-on-read ■ Configuration can occur in an order-independent way.
function for debug support.
When configuration is complete, each bank of UDBs has
❐ One to put the embedded DP RAM into test mode for a global routing enable which is asserted to activate the
DFT support. connections (forced gating is disabled).
❐ One to put the bank into global write mode, also for
■ After routing is enabled, a global clock enable bit (bank
DFT support.
enable) can be set (residing in the power manager)
which then enables clocking in the array. The bank
enable bit prevents any spurious operation until the
array is completely configured.

258 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 UDB Array and Digital System Interconnect

24.4.2 UDB POR Configuration Sequence

The previous section documented the POR state for the UDB array. From this initial state, configuration will proceed in the
order shown in Figure 24-4.

Figure 24-4. POR Configuration Sequence

Routing configuration is random,

but due to the fact that routing
Step 1 and clocking is disabled, array is
POR in a benign state.

Configure routing, PLD RAM, Datapath

RAM, and Datapath CFG registers in
Step 2 the UDB blocks. Also can configure
Configure Array working registers if desired.
Configuration is order independent.

Now that routing and UDB block

Step 3 configuration is done, you can enable
Enable Clock
Configuration Engine Performs These Steps

clock configuration input to use the

Configuration to routed enable for the clock. The clock
Input Routed Clock trees are still gated off.
Enable

The set of clocks to enable is

Step 4 determined by how clocks are allocated
Enable Quadrant in the array. Enabling only clocks that
Clock Enables and are used reduces the UDB array power.
Then Global Clock This does not actually enable the
Enables clocks. There is a global clock enable
for the UDB array in the power
manager block (Step 6).

Step 5 Routing between blocks and initial DSI

Enable Routing outputs are enabled.

There is one bit per bank (in one

Step 6 register) in the Power Manager register
Enable the UDB set. This allows for a global atomic
Bank Enable Bit in clock enable for the entire UDB array.
the Power Manager

Need to start from the sources and

work forward to avoid temporary high
Step 7 - Done. current states. Need to include a
User Can Write to routed enable to implement an atomic
Firmware Enable firmware enable.
Bits in Control
Register to Start
Functions

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 259

UDB Array and Digital System Interconnect

24.4.2.1 Quadrant Route Disable 24.4.4 UDB Register References and

To support fast bring up of initial functionality, the Quadrant Address Mapping
Bus Clock Enable register contains a bit called Route Dis- UDB registers are classified as shown in the Figure 24-5.
able to disable the routing for the associated UDB quadrant There are five address spaces: one for 8-bit working regis-
(2 UDB pairs). By default, this bit is cleared and is not dis- ters (registers that are accessed during normal operation),
abling the routing. If this bit is set to ‘1’ during initial configu- one for 16-bit working registers, and three for configuration.
ration, the associated channel routing RAM does not need
to be configured. The global route enable bit can be set and Each bank of UDBs is on a separate spoke, so a total of 6
this routing will remain in a benign state. Routing configura- select lines are generated from the PHUB to support the
tion for this quadrant can occur at a future time when this bit UDB array. The working registers are on the main 64K page
can be cleared to ‘0’ to enable the routing (assuming that (Page 0). The configuration registers have their own page
the global route enable bit is set). (Page 1). Details of these registers are located in the
PSoC® 3 Registers TRM (Technical Reference Manual)
and the PSoC® 5 Registers TRM (Technical Reference
24.4.3 UDB Sleep and Power Control
Manual).
The UDB array has support for low power operation in the
form of a sleep control input and power switch control
inputs. All static configurations are on the “keep-alive”
domain which retains state during a sleep/power down
period. However, all application level working registers,
including the accumulators, the data registers, the FIFO,
control and status registers, etc., lose their state and must
be reinitialized on power up. Nonretention registers and
FIFO state are reset after a sleep period to insure a good ini-
tial state.

Figure 24-5. UDB Register Mapping

UDB Registers

Working Configuration
Registers Registers

DSI Interface
8-Bit Working 16-Bit Working UDB Bank Array Bank Control
Configuration

UDB Pair
Concatinated
Configuration

UDB Channel
Default Access Interface
Configuration

260 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 UDB Array and Digital System Interconnect

Figure 24-6 shows the register mapping for working and configuration registers of UDB and DSI.

Figure 24-6. UDB Array Base Addresses

Address Page 0 Address Page 1

6400h Bank 0 0000h

8-Bit
Bank 0
Working Registers 512 Array Configuration
6500h Bank 1 Bytes
8-Bit 8-Bit
Working 1000h 8K Bytes
Working Registers
Register 6600h
Address Bank 1
Space Reserved UDB Array Array Configuration
Configuration
6700h Space 2000h
Reserved (maximum used:
13K)
6800h Reserved

Bank 0
16-Bit 3000h
Working Registers
Reserved
6A00h 1K Bytes
4000h
Bank 1 DSI
16-Bit Configuration Space DSI Configuration 3K Bytes
16-Bit Working Registers (maximum used: 4800h
Working 4K)
Reserved
Register 6C00h 5000h
Address Bank 0 Control
Bank 5010h 32 Bytes
Space Bank 1 Control
Configuration 5020h
Reserved Space Reserved
Reserved

6E00h Reserved

Reserved Interrupt 5100h

INT/DMA 256
and DMA
Configuration Bytes
Configuration
5200h
7000h

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 261

UDB Array and Digital System Interconnect

262 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 25. Controller Area Network (CAN)

The CAN peripheral is a fully functional Controller Area Network (CAN) supporting communication baud rates up to 1 Mbps.
The CAN controller is CAN2.0A and CAN2.0B compliant per the ISO-11898 specification. The CAN protocol was originally
designed for automotive applications with a focus on a high level of fault detection and recovery. This ensures high communi-
cation reliability at a low cost. Because of its success in automotive applications, CAN is used as a standard communication
protocol for motion oriented embedded control applications (CANOpen) and factory automation applications (DeviceNet). The
CAN features allow the efficient implementation of higher level protocols without affecting the performance of the microcon-
troller CPU.

Figure 25-1. CAN Bus System Implementation

CAN Node 1 CAN Node 2 CAN Node n

PSOC

CAN Drivers

CAN Controller
EN

RX
TX

CAN Transceiver

CAN_H CAN_L CAN_H CAN_L CAN_H CAN_L

CAN Bus

25.1 Features
■ Compliant with CAN2.0A/B protocol specification:
❐ Standard and extended frames
❐ Remote Transmission Request (RTR) support
❐ Programmable bit rate up to 1 Mbps
■ Receive path:
❐ 16 receive message buffers
❐ 16 acceptance filters and acceptance masks
❐ DeviceNet addressing support
❐ Option to link multiple receive buffers to form a hardware FIFO
■ Transmit path:
❐ Eight transmit message buffers
❐ Programmable priority for each transmit message buffer
■ CAN Transmit (Tx), Receive (Rx), and EN can be routed to any I/O
■ Listen Only mode for auto baud detection
■ Ability to wake up the device from Sleep mode on bus activity

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 263

Controller Area Network (CAN)

25.2 Block Diagram

To transmit a message, the host controller stores a message in the transmit message buffer and informs the transmit mes-
sage handler which transmits the message. When a message is received, it is stored in the memory buffer and the host con-
troller can process it on demand. The transmission and reception are mainly governed by the status and configuration
registers. The various interrupts of the CAN module are handled by the interrupt controller unit. Figure 25-2 illustrates this
process.

Figure 25-2. CAN Block Diagram

Memory
Buffer
(SRAM)
CAN Module

Memory
Arbiter

Receive
Message
Handler
CAN
Transmit
Bus
TO Message
Advanced
CPU/PHUB Handler
Peripheral
Bus
CAN
(APB)
Coupler
Framer
Interrupt
Controller

Status and
Configuration

Control and
Command

25.3 CAN Message Frames 25.3.1.1 Standard Data Frame

In CAN the transmission and reception of messages are The standard data frame for CAN is illustrated in
governed by four main frame types: Figure 25-3 on page 265.

■ Data frames
■ Remote frame
■ Error frame
■ Overload frame

25.3.1 Data Frames

Data frames are mainly used to transfer data between trans-
mitter and receiver. CAN supports mainly two types of data
frames: Standard Data Frame and Extended Data Frame.
For a CAN frame, '0' is referred to as the dominant bit and '1'
as a recessive bit.

264 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Controller Area Network (CAN)

Figure 25-3. Standard Data Frame

Arbitration Field

Interframe Interframe
Space Start of Identifier DLC Data CRC ACK End of Space
RTR IDE R0 (Maximum 8
Frame (11 Bits) (4 Bits) Field Field Frame
Bytes)

Control Field

Start of frame. The beginning of a data frame is indicated Data Length Code (DLC). These 4 bits indicate the num-
by the start of frame bit. It is a single dominant bit. ber of data bytes in the data field. The IDE, R0, and DLC
bits constitute the Control Field.
Identifier. For a basic CAN data frame, the identifier is 11
bits long. It is mainly used to filter the data at the receiver Data Field. This field contains the message data. It is of
side. variable length and can have a maximum of 8 bytes.

Remote Transmission Request Bit (RTR). Set the RTR Cyclic Redundancy Check (CRC). Frame checking is car-
bit '0' (dominant) for a data frame and set to '1' (recessive) ried out by the method of cyclic redundancy check (CRC).
for a remote frame. The identifier and RTR bit are known as The field consists of a 15-bit CRC code followed by a CRC
the Arbitration Field. delimiter.

Extended Identifier Bit (IDE). This bit must be a ‘0’ (domi- Acknowledgement Field (ACK). The ACK field is two bits
nant for a standard data frame and a ‘1’ (recessive) for long and recessive by default. When a receiver receives a
extended CAN data frame. message correctly, it overwrites the ACK field with a domi-
nant bit.
R0. Reserved bit.
End of Frame. The end of every frame is indicated by End
of Frame field and it consists of seven recessive bits.

25.3.1.2 Extended Data Frame

The extended CAN frame format is illustrated in Figure 25-4. The extended CAN has a 29-bit identifier. It is arranged as an
11-bit identifier field and an 18-bit identifier field separated by a Substitute Remote Request (SRR) bit and an IDE bit. The
SRR bit is in the same position as the RTR bit in the standard frame, and is recessive. The IDE bit is set for extended frames.
The Control Field of the extended data frame has an additional reserve bit ‘R1’ compared to the standard data frame.

Figure 25-4. Extended Data Frame

Arbitration Field

Interframe Interframe
Space Start of Identifier Identifier DLC Data CRC ACK End of Space
(11 Bits)
SRR IDE
(18 Bits)
RTR R1 R0 (4 Bits) (Maximum Field Field Frame
Frame
8 Bytes)

Control Field

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 265

Controller Area Network (CAN)

25.3.2 Remote Frame thereby forcing all other nodes to send out error flags result-
ing in a series of six to twelve dominant bits on the bus.
The CAN bus allows a destination node to request data from
the source by sending a Remote Frame. There are two dif- Error Passive Flag. An error passive flag consists of six
ferences between a Data Frame and a Remote Frame. recessive bits. When an error passive station detects an
First, the RTR bit is transmitted as a recessive bit in the error it sends a passive error flag. A passive error does not
remote Frame. Second, there is no Data Field in the Remote affect any other nodes and the error is detected only if the
Frame. transmitting node detects a bus error. The Error Delimiter
For extended remote frame, the SRR bit is also transmitted consists of eight recessive bits.
as a recessive bit.
25.3.4 Overload Frame
Interframe Space. Interframe space separates the data
The overload frame (EOF) consists of an overload flag and
frames and remote frames from the preceding frames.
an overload delimiter. CAN supports reactive overload
frame which is activated when the following conditions
25.3.3 Error Frame occur:
The Error frame is generated by a node when it detects any ■ Detection of a dominant bit during first two bits of inter-
bus error. The error frame consists of an error flag and error mission
delimiter. The error flag are classified into two types: error ■ Detection of a dominant bit in the last bit of EOF by a
active flag and error passive flag. receiver
■ Detection of a dominant bit by any node at the last bit of
Error Active Flag. When an error active station detects an
error it sends six dominant bits as an active error flag. The error delimiter or overload delimiter
format of the error flag thus violates the rule of bit stuffing

25.4 Transmitting Messages in CAN

The CAN module supports eight transmit message holding buffers. An internal priority arbiter selects the message according
to the chosen arbitration scheme. The arbitration scheme is either a round robin or fixed priority scheme. When a message is
transmitted or when there is a message arbitration loss, the priority arbiter re-evaluates the message priority of the next mes-
sage. The receive message buffers can also transmit remote transmit requests, which are explained later in this chapter.

266 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Controller Area Network (CAN)

Figure 25-5. Transmit (Tx) Block Diagram

TxREQ CAN Module

TxMESSAGE0

TxREQ
TxMESSAGE1

CAN
To Bus
TxREQ CAN
CPU/PHUB TxMESSAGE7
ABP Framer
Priority
Bus Arbiter
Coupler RTR REQ
RxMESSAGE0

RTR REQ
RxMESSAGE1

RTR REQ
RxMESSAGE15

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 267

Controller Area Network (CAN)

25.4.1 Message Arbitration The main steps in transmitting a standard data frame are:
1. Write the message into an empty transmit message
The priority arbiter supports a round robin and fixed priority
holding buffer. An empty buffer is indicated by TxREQ
arbitration. The arbitration mode is selected using the con-
flag equal to zero.
figuration register.
a. For standard data frame, write '0' (dominant) to the
RTR and IDE bit.
Round Robin. In a round robin scheme, Buffer 0 is
selected first, then Buffer 1 and so on till Buffer 7, and it con- b. Write the DLC bits appropriately to specify the num-
tinues again with Buffer 0 thus forming a cycle. A particular ber of data bytes to be transferred. The maximum
number of data bytes is limited to eight. Data bytes
buffer is only selected if its TxREQ flag is set. This scheme
with MSb (most significant bit) first in each byte are
guarantees that all buffers receive the same probability to
written in D0, D1…D7 locations.
send a message.
c. The 11-bit message identifiers are written to the
ID[31:21] bit field.
Fixed Priority. Buffer 0 has the highest priority. Designate
Buffer 0 as the buffer for critical messages to guarantee that 2. Choose an appropriate priority arbitration scheme. The
message is sent first. Priority arbitration is selected using internal message priority arbiter selects the message
according to the chosen arbitration scheme.
the CFG_ARBITER bit in the Configuration register
(CAN_CSR_CFG[12]). 3. Request transmission by setting the respective TxREQ
flag to ‘1’.
Note RTR message requests are served before TxMes- 4. The TxREQ flag remains set as long as the message
sage buffers are handled. For example, RTRreq0, transmit request is pending. The content of the message
RTRreq15, TxMessage0, TxMessage1, and TxMessage7. buffer must not be changed while the TxREQ flag is set.
Once the message is transmitted, the TxREQ flag is cleared
25.4.2 Message Transmit Process and the TX_MSG interrupt status bit
Figure 25-6 shows the registers associated with a message [CAN_CSR_INT_SR[11] in the interrupt status register
that is transmitted. CAN_CSR_INT_SR is asserted. The interrupt status bit is
only asserted if the TxINT ENBL (CAN_TX [n]_CMD[2]) is
set to ‘1’.

Figure 25-6. Transmit (Tx) Message Registers

REGISTERS

COMMAND REGISTER Reserved WPN2 Reserved 1 RTR IDE DLC Reserved WPN1 Tx INT Tx Tx
(CAN_Txn_CMD) [31:24] [23] [22] [21] [20] [19:16] [15:4] [3] ENBL ABORT REQ
[2] [1] [0]

IDENTIFIER ID
(CAN_Txn_ID) [31:3] Reserved [2:0]

DATA REGISTER High D0 D1 D2 D3

(CAN_Txn_DH) [63:56] [55:48] [47:40] [39:32]

DATA REGISTER Low D4 D5 D6 D7

(CAN_Txn_DL) [31:24] [23:16] [15:8] [7:0]

n = 0,1,…,7

268 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Controller Area Network (CAN)

25.4.3 Message Abort Note 4. Using the WPN flags(wpn1 and wpn2) enables sim-
ple retransmission of the same message by only having to
A message is aborted by setting the TxABORT flag set the TxREQ flag without taking care of the special flags
(CAN_TX [n]_CMD[1]) in the CAN_TX [n]_CMD register. (RTR,IDE,DLC and TxINTENBL).
This bit is automatically cleared by the hardware when the
message is aborted.
25.4.4 Transmitting Extended Data
Note 1. The CAN Buffer register (CAN_CSR_BUF_SR) is Frames
used to read whether any transmission requests are pend- For transmitting an extended data frame certain register set-
ing. tings must change compared to that of a standard data
frame. These changes are as follows.
Note 2. If the write protect bit wpn2 (CAN_TX [n]_CMD[23])
■ For extended date frame, write '1' (recessive) to the IDE
is ‘0’, then the bits [21:16] of the Command register cannot
bit.
be modified because they are protected and provides an
undefined value on read back. ■ The message identifiers are written to the ID[31:3] bit
field.
Note 3. If the write protect bit wpn1 (CAN_TX [n]_CMD[3])
is ‘0’, then the bit [2] of the Command register cannot be
modified. This bit gives a ‘0’ upon read back.

25.5 Receiving Messages in CAN

The CAN module has 16 receive message buffers as illustrated in Figure 25-7. Each message buffer has a dedicated accep-
tance filter. The CAN message is received by the CAN framer and then the received message is simultaneously compared
with all the acceptance filters and the accepted message is stored in the respective receive message buffer. The message
available (MSG AV) bit in the message buffer is set to indicate the availability of the new message. Message receipt must be
acknowledged by clearing the MSG AV flag to allow receipt of another message.

The acceptance filter is configured by the Acceptance Mask Register (AMR) and the Acceptance Code Register (ACR).

Figure 25-7. Receive (Rx) Block Diagram

CAN Module
RxMESSAGE0 Acceptance Filter 0
1
RxMESSAGE1 Acceptance Filter 1 2 CAN
3 RxMESSAGE CAN Bus
RxMESSAGE2 Acceptance Filter 2
Handler Framer
16

RxMESSAGE15 Acceptance Filter 15

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 269

Controller Area Network (CAN)

25.5.1 Message Receive Process

Figure 25-8 shows the registers associated with a received message.

Figure 25-8. Receive (Rx) Message Registers

REGISTERS

COMMAND REGISTER Reserved WPN2 Reserved1 RTR IDE DLC Reserved WPNL LINK Rx INT RTR BUFF RTR RTR REPLY MSG AV
(CAN_Rxn_CMD) [31:24] [23] [22] [21] [20] [19:16] [15:8] [7] FLAG ENBL REPLY ENBL ABORT PNDG [0]
[6] [5] [4] [3] [2] [1]

IDENTIFIER ID Reserved
(CAN_Rxn_ID) [31:3] [2:0]

DATA REGISTER High D0 D1 D2 D3

(CAN_Rxn_DH) [63:56] [55:48] [47:40] [39:32]

DATA REGISTER Low D4 D5 D6 D7

(CAN_Rxn_DL) [31:24] [23:16] [15:8] [7:0]

n = 0,1,…,15

The main steps in receiving a message are: Following message fields are covered:
1. After receipt of a new message, the RxMessageHandler ■ Identifier
hardware (as seen in Figure 25-7) searches all receive ■ IDE
buffer starting from RxMessage0 until it finds a valid buf-
fer. A valid buffer is indicated by: ■ RTR
a. Receive buffer is enabled indicated by BUFF ENBL = ■ Data byte 1 and data byte 2
‘1’ (CAN_RX[n]_CMD[3]). For a standard CAN message when IDE=0, the 11 bit
b. Acceptance filter of the receive buffer matches identifier are the bits [31:21] of AMR and ACR.
incoming message.
2. If the RxMessageHandler finds a valid buffer that is
25.5.2.1 Example
empty, then the message is stored and the MSG AV flag A message and the acceptance filter settings to accept that
of this buffer is set to ‘1’. message are shown in Figure 25-9 on page 271.
3. If the Rx INT ENBL flag is set, then the RX_MSG flag
(CAN_CSR_INT_SR[12]) of the interrupt controller is
asserted.
4. If the receive buffer already contains a message indi-
cated by MSG AV = ‘1’ and the Link Flag is not set, then
the RX_MSG_LOSS interrupt flag
(CAN_CSR_INT_SR[10]) is asserted. The existing mes-
sage is overwritten with the new received message.
Note The CAN Buffer register (CAN_CSR_BUF_SR) deter-
mines if any receive message buffer is available.

25.5.2 Acceptance Filter

Each receive buffer has its own acceptance filter that is
used to filter incoming messages. An acceptance filter is
configured by the Acceptance Mask register (AMR) and the
Acceptance Code register (ACR).

AMR: ‘0’. The incoming bit is checked against the respec-

tive ACR bit. The message is not accepted when the incom-
ing bit does not match respective ACR bit.

AMR: ‘1’. The incoming bit is Do Not Care.

270 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Controller Area Network (CAN)

Figure 25-9. Acceptance Filter

M e s s a g e F ra m e

Id e n tifie r

S ta rt RTR ID E
of DLC
F ra m e 0 X X 0 0 1 1 0 0 1 0 0 0

YES
ACCEPT MESSAGE

=
NO
R EJEC T M ESSA G E

ID E RTR R
Do Not S
ACR 0 X X 0 0 1 1 0 0 1 0 C a re 0 0 V 0
D

31 30 29 28 27 26 25 24 23 22 21 20 3 2 1 0

ID E RTR R
S
AMR 0 1 1 0 0 0 0 0 0 0 0 A ll O n e s 0 0 V
D

31 30 29 28 27 26 25 24 23 22 21 20 3 2 1 0

M asked

As seen in the Figure 25-9, the shaded areas are masked AMR Settings:
bits. When a bit is set to ‘1’ in the AMR register, the corre-
ID[28:21],ID[31] = 0
sponding bit in the ACR register is not checked against the
ID[30],ID[29]= 1
received message frame. In the example, bits 30, 29, and
ID[20:3] = All Ones
bits from 3 to 20 are set to ‘1’ and are masked. Since other
IDE = 0
bits in the AMR register are written as ‘0’, the respective bits
RTR = 0
in the ACR register are compared with message bits as
shown in Figure 25-9. If the corresponding bits in ACR ACR Settings:
match with that of the message, the message is then stored
ID[31:21] = 182h
in the receive message buffer. If the corresponding bits in
ID[20:3] = Do Not Care
ACR do not match with the message, the incoming mes-
IDE = 0
sage is rejected.
RTR = 0

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 271

Controller Area Network (CAN)

25.5.3 DeviceNet Filtering

For some CAN high level protocols such as DeviceNet, additional protocol related information is contained in the first and
second data bytes. The acceptance filters provide additional coverage of these two bytes for a more efficient implementation
of the protocol. The data bits of the first two bytes of the incoming message are compared with the ACRD register (CAN_RX
[n]_ACRD) and the respective bits that are compared are specified using AMRD register (CAN_RX [n]_AMRD). Using the
Example on page 270, DeviceNet filtering is illustrated in Figure 25-10.

Figure 25-10. DeviceNet Filter

Message Frame Identifier Data

Start of RTR IDE DLC

Do Not
Frame 0 X X 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 Care

Yes
Accept Message

=
No
Reject Message

R
Do Not S
0 X X 0 0 1 1 0 0 1 0 0 0 Do Not
ACR Care 0
V
ACRD 0 0 0 0 0 X X 1 1 0 Care
D

31 30 29 28 27 26 25 24 23 22 21 20 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 0

IDE RTR All

R
S AMRD 0 0 0 0 0 1 1 0 0 0 Ones
AMR 0 1 1 0 0 0 0 0 0 0 0 All Ones 0 0 V
D
15 14 13 12 11 10 9 8 7 6 5 0
31 30 29 28 27 26 25 24 23 22 21 20 3 2 1 0

Masked

In Figure 25-10 the data field of the message frame is com- ACR Settings:
pared with those bits of the ACRD register, which are not
ID[31:21] = 182h
masked by the AMRD register.
ID[20:3] = Do Not Care
To accept this message, the acceptance filter settings are IDE = 0
as follows. RTR = 0
ACRD [15:6] = 06h
AMR Settings:
ACRD [5:0] = Do Not Care
ID[28:21],ID[31] = 0
The example in Figure 25-10 shows the filtering using 10
ID[30],ID[29] = 1
data bits. Using AMRD, up to 16 data bits, can be used for
ID[20:3] = All Ones
filtering.
IDE = 0
RTR = 0
AMRD [15:11], AMRD[8:6] = 0 25.5.4 Filtering of Extended Data Frames
AMRD[10:9], AMRD [5:0] = All Ones Filtering the extended data frame is very similar to the stan-
dard date frame with the following exception.
■ IDE bit in AMR and ACR registers must be set to check
for extended data frame.

272 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Controller Area Network (CAN)

25.5.5 Receiver Message Buffer Linking 25.6 Remote Frames

Several receive buffers can link together to form a receive Remote frames are used for initiating transmission between
buffer array that acts almost like a receive FIFO. To accom- two nodes and the node acting as a receiver sends the
plish this, do the following: remote frame. A remote frame can use either standard for-
■ Set the Link flag CAN_RX[n]_CMD[6] for the buffers that mat or extended format. A remote frame is different from a
need to be linked. data frame in that the RTR bit is always equal to ‘1’ and the
■ Make sure that all buffers of the same array have the data field is absent, independent of the value of DLC field.
same message filter setting (AMR and ACR are identi- The flow of a remote transmit request is illustrated in
cal). Figure 25-11.

■ Do not set the Link flag of the last buffer of an array. As shown in Figure 25-11:

When a receive buffer already contains a message (MSG ■ The message buffer0 of node1 transmits a remote frame
AV=’1’) and a new message arrives for this buffer, then this into the CAN bus.
message is discarded (RX_MSG_LOSS Interrupt). To avoid ■ The RTR request is received by the RxMessageHandler
this situation, several receive buffers are linked together. of node 2 and sends it to the acceptance filters.
When the CAN controller receives a new message, the ■ The acceptance filter settings of the receive message
RxMessageHandler searches for a valid receive buffer. If buffer 15 matches with that of the message and then the
one is found that is already full (MSG AV = ‘1’) and the ‘Link message is moved to the receive message buffer 15.
Flag’ is set, the search for a valid receive buffer is continued.
■ If the RTR Auto Reply feature is enabled, the receive
If found, the message is transferred to that buffer thereby
message buffer 15 will transmit the message with the
forming an array. If no other buffer is found, then the
same identifier as it received (without CPU intervention).
RX_MSG_LOSS interrupt is set.

It is possible to build several message arrays. Each of these ■ The acceptance filter of the receive message buffer 1 of
arrays must use the same AMR and ACR. node1 has the same identifier settings as that of the
transmitted message node 1. Hence, the RTR message
will be stored in the receive message buffer 1 of node 1.

Figure 25-11. Remote Transmit Request

Node 1
Node 2

Receive Message
Message Buffers Acceptance Buffers
Node 1 Filters Node 2
RTR
REQ FILTER0 RxMESSAGE0
TxMESSAGE0
CAN Bus Rx FILTER1
TxMESSAGE1 Priority Message RxMESSAGE1
Arbiter Handler

TxMESSAGE7 FILTER15 RxMESSAGE15

Acceptance
Filters
RxMESSAGE0
FILTER0
RxMESSAGE1 FILTER1 Rx Priority
CAN Bus Arbiter
Message
Handler

RxMESSAGE15 FILTER15

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Controller Area Network (CAN)

25.6.1 Transmitting a Remote Frame by 25.7 Bit Time Configuration

the Requesting Node
The CAN module operates on a single clock input
The process to transmit a remote frame by a requesting CLK_BUS. This section explains how to configure the pro-
node (Node 1 as shown in Figure 25-11 on page 273) is as grammable bit-rate divider to achieve the desired bit rate
follows. and its relationship with CLK_BUS.
1. Write a message to an empty transmit buffer. An empty
buffer is indicated by Tx_REQ = ‘0’ 25.7.1 Allowable Bit Rates and System
(CAN_TX[n]_CMD[0]). Clock (CLK_BUS)
2. Set the RTR bit (CAN_TX [n]_CMD[21]) to ‘1’.
Across the industry, most implementations of CAN-Bus use
3. Choose an appropriate priority arbitration scheme.
one of 10 bit rates:
4. Set the transmit request flag to initiate transmission.
■ 1 Mbps
5. The Identifier transmitted in a message must be the
same as the identifier of receiving message. ■ 800 Kbps
■ 500 Kbps
25.6.2 Receiving a Remote Frame ■ 250 Kbps
The process to receive a remote frame is as follows. ■ 125 Kbps
1. The acceptance filter must be configured to receive the ■ 100 Kbps
desired message ID. ■ 50 Kbps
2. Enable the automatic RTR message handling by setting ■ 20 Kbps
bit ‘RTR REPLY’ to ‘1’.
■ 10 Kbps
a. If enabled, it will automatically transmit the remote
frame with the same identifier. ■ 5 Kbps
b. Else the remote frame must be transmitted following These bit rates are configurable if CLK_BUS is 8 MHz or a
the standard routine as that of a data frame. multiple. All except 800 Kb are configurable if CLK_BUS is
3. Set the requesting node that receives the replied RTR 10 MHz or a multiple. With a very few exceptions, all 10 bit
message to receive a normal message. Do not set the rates are not possible if CLK_BUS is not evenly divisible by
RTR Reply bit. 1,000,000 Hz. From a bit rate generation point of view, the
accuracy for CLK_BUS must be at least 1.58% for 125 Kbps
25.6.3 RTR Auto Reply and slower bit rates, and 0.5% or better for bit rates faster
The CAN module supports automatic answering of RTR than 125 Kbps. Figure 25-12 on page 275 shows a table of
message requests. All 16 receive buffers support this fea- the 10 bit rates that are supported for any given fclk fre-
ture. If an RTR message is accepted in a receive buffer quency from 8 MHz to 100 MHz. Note that maximum possi-
where the RTR REPLY FLAG is set, then this buffer auto- ble frequency for PSoC3 is 67MHz and PSoC5 is 80MHz.
matically replies to this message with the content of the
receive buffer. The ‘RTR REPLY PNDG FLAG’ is set when
the RTR message request is received. It is reset when the
message is sent or when the message buffer is disabled. To
abort a pending RTRreply message, use the RTR ABORT-
command.

25.6.4 Remote Frames in Extended

Format
The transmission and reception of remote frames in
extended format is similar to standard format except for the
following.
■ The IDE bit (CAN_TX [n]_CMD[20]) is set to ‘1’ to make
it an extended data frame.
■ The identifier is 29 bits long compared to the 11 bits of a
standard data frame.

274 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Controller Area Network (CAN)

Figure 25-12. Bit Rate Versus CLK_BUS

clk_bus clk_bus clk_bus

1 800 500 250 125 100 50 20 10 5 1 800 500 250 125 100 50 20 10 5 1 800 500 250 125 100 50 20 10 5
Freq Freq Freq
Mb Kb Kb Kb Kb Kb Kb Kb Kb Kb Mb Kb Kb Kb Kb Kb Kb Kb Kb Kb Mb Kb Kb Kb Kb Kb Kb Kb Kb Kb
(MHz) (MHz) (MHz)

8 39 70
9 40 71
10 41 72
11 42 73
12 43 74
13 44 75
14 45 76
15 46 77
16 47 78
17 48 79
18 49 80
19 50 81
20 51 82
21 52 83
22 53 84
23 54 85
24 55 86
25 56 87
26 57 88
27 58 89
28 59 90
29 60 91
30 61 92
31 62 93
32 63 94
33 64 95
34 65 96
35 66 97
36 67 98
37 68 99
38 69 100

Configurable Bit Rates

Non Configurable Bit Rates

25.7.2 Setting Bit Rate TSEG1 and BRP + 1

TQ = --------------------- Equation 2
TSEG2 clk_bus
The bit rate is defined as the number of bits transmitted on a Note Bit rate pre scaler is a register that performs a pre
CAN bus per second. Bit time is the reciprocal of bit rate. Bit scaling function on CLK_BUS to generate the clock for CAN
time is divided into three segments as shown in module. See Figure 25-14.
Figure 25-13. Each segment is represented in terms of fixed
units of time called Time Quanta (TQ) which is derived from Synchronization Segment. This is the first segment with 1
the oscillator clock. TQ length and is mainly used for synchronization. An edge
is expected to fall within this segment.
Figure 25-13. Bit Time
Nominal Bit Time = 8...25 TQ (Time Quanta)
Tseg1, Tseg2. These segments compensate for the edge
SJW: 1...4TQ phase shift errors. The tseg1 also takes in the propagation
time which includes any delays in the network. The length of
Tseg1 Tseg2 the segments is increased or decreased to compensate for
prop_seg + phase_seg1 phase_seg2 the error due to phase shift of edges which is known as
resynchronization.

Synchronization
Sample Point Sample Point. This is the point at which the state of the
Segment bus is read and the bit is interpreted. It is located at the end
1 or 3 Sample Mode
of tseg1.

BitTime =  1 +  tseg1 + 1  +  tseg2 + 1    TQ Synchronization Jump Width. By resynchronization, the

Equation 1 tseg1 is lengthened or tseg2 is shortened. Synchronization
jump width puts a limit to this resynchronization. The length

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 275

Controller Area Network (CAN)

of tseg2 must be greater than the synchronization jump Note 1. Sampling_mode bit in the Configuration register
width. (CAN_CSR_CFG) specifies whether or not one sampling
point is used in the receiver path or three sampling points
The Configuration register CAN_CSR_CFG is used for set-
with majority decision are used.
ting the bit rate prescaler (BRP), tseg1, tseg2, and the syn-
chronization jump width. CAN peripheral clock (CAN_CLK)
Note 2. Edge_mode bit in the Configuration register
is generated by dividing the system clock (CLK_BUS) by
(CAN_CSR_CFG) specifies whether or not the high to low
(BRP+1). See the Clocking section for detailed information
edge is used for synchronization or both edges are used.
on available options to generate the system clock. For N
time quanta in a bit time, the CAN peripheral clock fre-
quency must be configured to N time the CAN bus bit rate. 25.8 Error Handling and
Figure 25-14. Bit Timing Block Diagram Interrupts in CAN
clk_bus can_clk According to the CAN protocol specification, there are five
Divider different types of errors. Each CAN node in the bus tries to
detect an error, and when it does, it sends out an error
frame. The different types of errors and the process of error
BRP (CAN_CSR_CFG[14:0]) handling are explained in the following sections.

25.8.1 Types of Errors

25.7.2.1 Example
An example to achieve 1 Mbps speed with 40 MHz is 25.8.1.1 BIT Error
described as follows. A CAN unit sending a bit on the bus also monitors the bus.
1. Since the speed is 1 MHz, the bit time is 1 µs. When the bit value that is monitored is different from the bit
2. Choosing a minimum value of 8 TQ in the bit time, 1TQ = value that is sent, a BIT error is detected. An exception is
0.125 µs. the sending of a ‘recessive’ bit during the stuffed bit stream
3. BRP = ((time quanta * clk_bus) – 1) = 4. of the Arbitration Field or during the ACK Slot. A Transmitter
sending a Passive Error Flag and detecting a ‘dominant’ bit
4. Therefore write a value of ‘4’ into the CFG_BITRATE bits
does not interpret this as a BIT error.
in the configuration register.
5. Choose the sampling point to be 60% of the bit time, 25.8.1.2 FORM Error
which is approximately equal to 5TQ. Since the sampling
point is at the end of tseg1, this implies that (tseg2+1) = A FORM error is detected when there is an error in the CAN
3TQ or tseg2 = 2TQ. message format. The fixed format fields in the message
6. To fix the sampling point synchronization jump width, frame such as End of Frame, Interframe Space, etc., con-
use a value ‘1’ by writing to the bits CFG_SJW = ‘1’. tains illegal bits.
7. Write to the bits cfg_tseg2 a value of ‘2’ to set the value
of tseg2 to 2TQ. 25.8.1.3 ACKNOWLEDGE Error
8. Now tseg1 is calculated using the following equation: A transmitter sending a recessive bit during the ACK slot
tseg1 = ((BitTime - (1TQ + tseg2 + 1TQ)) - 1TQ) monitors the ACK slot for a dominant bit. If a receiver
...which is tseg1 = 3TQ. receives a message correctly, a dominant bit is written in the
9. Therefore, write a value of ‘3’ into the bits cfg_tseg1 in ACK slot. Therefore, if the transmitter does not find a domi-
the configuration register. nant bit in the ACK slot after transmission, then an
ACKNOWLEDGE error is detected.
This procedure above is applied to achieve the standard bit
rates using the clock frequencies as specified in the table in 25.8.1.4 CRC Error
Figure 25-12 on page 275.
A transmitting node performs certain calculations to gener-
Observe the following conditions for setting tseg1 and tseg2: ate a CRC code and transmits it in the CRC field. A receiv-
■ tseg1 = 0 or tseg1 = 1 are not allowed. ing node also performs the same calculations to generate a
■ tseg2 = 0 is not allowed; tseg2 = 1 is only allowed in CRC code. If the code generated by the receiver does not
direct sampling mode. match the code transmitted then a CRC error is detected.

276 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Controller Area Network (CAN)

25.8.1.5 STUFF Error that indicate if the Transmit Error Counter and Receive Error
Counter, respectively, are greater than or equal to 96 deci-
When there are six consecutive equal bit levels in a mes-
mal. This is a feature. It serves as an error warning because
sage field that is coded by the message of bit stuffing, a
an error count value greater than and around 96 indicates a
STUFF error is detected during the bit time of the sixth con-
heavily disturbed bus.
secutive bit level.

25.8.3 Interrupt Sources in CAN

25.8.2 Error States in CAN
The interrupt controller governs the various interrupt
There are three main error states in CAN:
sources in CAN.

Error Active. An error active node can take part in normal The interrupt controller contains an interrupt status and an
bus communication. When it detects an error it sends out an interrupt enable register. The interrupt status register
ERROR ACTIVE FLAG. (CAN_CSR_INT_SR) stores internal interrupt events. Once
a bit is set, it remains set until it is cleared by writing a '1' to
Error Passive. An error passive node takes part in bus it. The interrupt enable register has no effect on the interrupt
communication. When it detects an error it sends out an status register.
ERROR PASSIVE FLAG. After sending out the ERROR
The interrupt enable register (CAN_CSR_INT_EN) controls
PASSIVE FLAG, it waits before proceeding with further
which particular bits from the interrupt status register are
transmission. An error passive node sends additional 8
used to assert the interrupt output INT_N. INT_N is asserted
recessive bits during the interframe space. This period is
if a particular interrupt status bit and the respective enable
also known as suspend transmission since no transmission
bit are set.
takes place.
The various interrupt sources in CAN are as follows:
Bus Off. A node that is in Bus Off does not take part in any
bus communication. It has no effect on the bus. rx_msg. Indicates a message received.
The error status in CAN is indicated by the error status reg-
tx_msg. Indicates a message sent.
ister CAN_CSR_ERR_SR. The bits ERR_STATE
(CAN_CSR_ERR_SR[17:16]) indicate which error state the
rx_msg_loss. Is set when a new message arrives but the
CAN node is in. The error states in CAN are determined
RxMessage flag MSG AV is set.
according to the values of two counters:
■ Transmit Error Counter (CAN_CSR_ERR_SR[7:0]) bus_off. The CAN has reached the bus off state.
■ Receive Error Counter (CAN_CSR_ERR_SR[15:8])
crc_err. A CAN CRC error detected.
The error counters are modified according to the CAN 2.0B
Specification. form_err. A CAN message format error detected.
A node is in ‘error active’ state if the Transmit Error Counter
ack_err. A CAN message acknowledge error detected.
or the Receive Error Counter are less than or equal to 127
decimal. A node is in ‘error passive’ state if the Transmit or
stuff_err. A bit stuffing error detected.
Receive Error Counter value exceeds or equals 128 deci-
mal. A node is in ‘Bus Off’ state if the Transmit Error Counter
bit_err. A bit error detected.
exceeds or equals the value of 256 decimal.

An ‘error passive’ node becomes ‘error active’ again when ovr_load. An overload frame received.
both the Transmit Error Count and the Receive Error Count
are less than or equal to 127. arb_loss. The arbitration lost while sending a message.

A node which is in ‘Bus Off’ state becomes ‘error active’ with

its error counters both set to ‘0’ after 128 occurrences of 11
consecutive ‘recessive’ bits are monitored on the bus.

There are two bits in the error status register:

■ ‘txgte96’ (CAN_CSR_ERR_SR[18])
■ ‘rxgte96’ (CAN_CSR_ERR_SR[19])

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Controller Area Network (CAN)

25.9 Operating Modes in CAN

The CAN module operates mainly in three different modes.
The command register CAN_CSR_CMD is used to select
the operating modes by setting the corresponding bit for
each mode. The three operating modes are as follows:
■ SRAM Test Mode: CAN_CSR_CMD[2]
■ Listen Only Mode: CAN_CSR_CMD[1]
■ Run/Stop Mode: CAN_CSR_CMD[0]

25.9.1 Listen Only Mode

In Listen Only mode, the CAN controller only listens to the
CAN receive line without acknowledging the received mes-
sages on the bus. It does not send any messages in this
mode. However, the error flags are updated so that the bit
timing is adjusted until no error occurs.

The various steps involved in automatic baud rate detection

are as follows.
1. The CAN controller is initialized for acceptance of all
messages (i.e., the global/local mask is set to ‘0’).
2. The bit timing values of the first possible CANOpen bit
rate (10 Kbps) is loaded and the controller is switched
into “Listen Only” mode.
3. Assuming that there is traffic on the network and the bit
rate is correct, the message is accepted.
4. The error registers will not change and the flag for mes-
sage reception is set inside the CAN controller. This
means the correct bit rate is detected.
5. Assuming the bit rate is not correct, the error flags are
updated (stuff-, CRC, or form-error).
6. In this scenario, the CAN controller is switched off and
the next possible bit timing values are loaded from the
bit rate table.

25.9.2 Run/Stop Mode

The CAN controller is in Run mode when it is operating nor-
mally. The CAN controller is stopped while it is in the SRAM
Test mode.

278 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 26. USB

The PSoC® USB block acts as a USB device that communicates with a USB host. The USB block is available as a fixed func-
tion digital block in the PSoC device. It supports full speed communication (12 Mbps) and is designed to be compliant with the
USB Specification Revision.2.0. USB devices can be designed for plug and play applications with the host and also support
hot swapping. This chapter details the PSoC USB block and transfer modes. For details about the USB specification, see the
USB Implementers Forum web site.

26.1 Features
The PSoC USB has these features:
■ Complies with USB Specification 2.0
■ Supports full speed peripherals device operation with a signaling bit rate of 12 Mbps
■ Supports 8 data endpoints and 1 control endpoint
■ Supports four types of transfers – bulk, interrupt, isochronous, and control
■ Supports Plug and Play
■ Supports two types of logical transfer modes:
❐ Store and Forward mode
❐ Cut Through mode
■ Differential signal (D+ and D-) output
■ Supports maximum packet size of 64 bytes using the Store and Forward mode and maximum packet size of 1023 for Iso-
chronous transfer using the Cut through mode
■ Capable of supplying PS/2 and CMOS signals
■ Supports two Vccd voltage ranges, with a nominal voltage of 3.3 V

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 279

USB

26.2 Block Diagram

Figure 26-1 illustrates the architecture of the USB block. It consists of the Serial Interface Engine (SIE) and Arbiter.

Figure 26-1. USB Block Diagram

Frequency
Tuning
clk_usb
clk_bus data

USB Block

Arbiter
CPU
CPU
Interface
512 Bytes Memory
SRAM Interface
Arbiter
Logic

DMA
SIE Interface
Interface

SIE

Transceiver

D+ D-

280 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 USB

26.2.1 Serial Interface Engine (SIE) interrupt for an endpoint is obtained from the
USB_SIE_INT_SR register.
The Serial Interface Engine (SIE) is responsible for handling
the decoding and creating of data and control packets dur- The SIE registers CNT0 and CNT1 hold the count value for
ing transmit and receive. It decodes the USB bit streams each endpoint which reports the number of data bytes in a
into USB packets during receive and creates USB bit USB transfer. In the case of an OUT endpoint, the firmware
streams during transmit. The following are the features of programs the maximum number of bytes that can be
the SIE block: received for the endpoint. The SIE updates the register with
the number of bytes received. In the case of an IN endpoint,
■ Conforms to the USB 2.0 Specification
it holds the number of bytes that will be transmitted.
■ Supports 1 device address
The SIE Control register for each endpoint,
■ Supports 8 data endpoints and 1 control endpoint
USB_SIE_EPx_CR0, holds the mode value. The mode
■ Supports interrupt for each endpoint value determines the response of the USB block to the host.
■ Operates at Full Speed with a 48 MHz Clock (maximum Refer to Table 26-1 for the different mode values. The table
permitted tolerance is ±0.25%) describes the mode values corresponding to each type
■ Integrates an 8-byte buffer in the Control endpoint token: the SETUP, IN and OUT tokens.

The registers for this block are mainly used to configure the Transition error is also reported by the SIE. The bit
data endpoint operations and the Control Endpoint Data buf- “err_in_txn” in the USB_SIE_EPx_CR0 register indicates
fers. The register also controls the interrupt available for the occurrence of an error. When this bit is set and the USB
each endpoint. block is in Store and Forward mode, the hardware automati-
cally retransmits the same data when it receives another IN
The SIE generates an interrupt at the end of a transfer. The token from the host. In Cut Through mode, this bit can be
interrupt enabling and disabling for an endpoint can be done read by the firmware to determine if the data should be
using the USB_SIE_INT_EN register. The status of the retransmitted.

Table 26-1. Mode Values in the MODE bits of the SIE_EPx_CR0 Register
Mode Encoding SETUP IN OUT Comments
Disable 0000 Ignore Ignore Ignore Ignore all USB traffic to this endpoint
NAK IN/OUT 0001 Accept NAK NAK NAK IN and OUT token
When this mode is set, it accepts a SETUP token,
STALLs in case of IN token and ACKs with a zero
Status OUT Only 0010 Accept STALL Check
length packet in case of OUT token. Used for control
endpoint
When this mode is set, it accepts a SETUP token,
STALL IN/OUT 0011 Accept STALL STALL STALLs in case of IN and OUT token. Used for control
endpoint
Reserved 0100 Ignore Ignore Ignore
ISO OUT 0101 Ignore Ignore Always Isochronous OUT
When this mode is set, it accepts a SETUP token,
STALLs in case of OUT token and ACKs with a zero
Status IN only 0110 Accept TX 0 byte STATLL
length packet in case of IN token. Used for control end-
point
ISO IN 0111 Ignore TX Count Ignore Isochronous IN
NAK OUT 1000 Ignore Ignore NAK Send NAK handshake to OUT token
This mode is changed by the SIE to mode 1000 on issu-
ACK OUT (STALL = 0) 1001 Ignore Ignore ACK
ance of ACK handshake to an OUT
ACK OUT (STALL = 1) 1001 Ignore Ignore STALL STALL the OUT transfer
Reserved 1010 Ignore Ignore Ignore
ACK the OUT token or send zero length data packet for
ACK OUT – STATUS IN 1011 Accept TX0 byte ACK
IN token.
NAK IN 1100 Ignore NAK Ignore Send NAK handshake for IN token

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USB

Table 26-1. Mode Values in the MODE bits of the SIE_EPx_CR0 Register (continued)
Mode Encoding SETUP IN OUT Comments
This mode is changed by the SIE to mode 1100 after
ACK IN (STALL = 0) 1101 Ignore TX Count Ignore
receiving ACK handshake to an IN data
ACK IN (STALL = 1) 1101 Ignore STALL Ignore STALL the IN transfer
Reserved 1110 Ignore Ignore Ignore
ACK IN – Status OUT 1111 Accept TX Count Check Respond to IN data or Status OUT

26.2.2 Arbiter maximum memory size supported is 512 bytes organized as

256 x a 16-bit memory unit. This is a dedicated memory for
The Arbiter is the block which handles access of the SRAM the USB. All the control and data lines, including the Data In
memory by the endpoints. The SRAM memory can be lines, Data Out lines, Enable line, Address lines, and Direc-
accessed by the CPU or the SIE. The Arbiter handles the tion Control line between the USB and the memory unit, are
arbitration between the CPU and the SIE. The Arbiter con- handled by the memory interface. The memory access can
sists of the following blocks: be requested by the SIE or by the CPU. The SIE Interface
■ SIE Interface Module block and the CPU Interface block handle these requests.
■ CPU Interface Module
26.2.2.4 DMA Interface
■ Memory Interface
■ DMA Engine When Direct Memory Access (DMA) is configured, the DMA
interface is responsible for all transactions back and forth
■ Arbiter Logic
between the DMA and USB. The block supports the DMA
■ Synchronization Module request line for each data endpoint. The behavior of the
The Arbiter registers are used to handle the endpoint config- DMA depends on the type of logical transfer mode config-
urations, the Read address, and the Write address for the ured in the Configuration register. Note that DMA transfers
endpoints. It also configures the logical transfer type from UDBs to the USB block must first go through SRAM to
required for each endpoint. The types of logical transfers are ensure that proper timing is kept. An additional transaction
discussed below. Also, each endpoint supports interrupt. descriptor should be used to transfer from UDBs to SRAM,
The Arbiter has only one interrupt line for the Interrupt Con- and then from SRAM to USB. Other applicable DMA trans-
troller. The Arbiter registers handle the enabling/disabling of fers from sources besides UDBs are not constrained to this
the interrupts for the endpoints and hold the status of the path.
interrupts. The Arbiter is also responsible for the memory
management (i.e., sharing the available 512 bytes of SRAM 26.2.2.5 Arbiter Logic
among the data endpoints). This is the main block of the Arbiter. It is responsible for arbi-
trations for all the transactions that happen in the Arbiter. It
26.2.2.1 SIE Interface Module arbitrates the CPU, DMA, and SIE access to the memory
This module handles all the transactions with the SIE block. unit and the registers. This block also handles the memory
The SIE reads data from the SRAM memory and transmits management. The memory management is either “Manual”
to the host. Similarly, it writes the data received from the or “Automatic.” In the case of Manual Memory Management,
host to the SRAM memory. These requests are registered in the read and write address manipulations are done by the
the SIE Interface module and are handled by this block. firmware. In the case of Automatic management, all the
memory handling is done by this block itself. This block
26.2.2.2 CPU Interface Block takes care of the buffer size allocation, depending on the
programmed buffer size (using the USB_BUF_SIZE). It also
This module handles all the transactions with the CPU. The does the handling of common memory area.
CPU makes requests for the reads and writes to the SRAM
memory for each endpoint. These requests are registered in This block also handles the interrupt requests for each end-
the CPU Interface block and are handled by the block. point. Each endpoint can have interrupts due to:
■ DMA Grants
26.2.2.3 Memory Interface ■ IN Buffer Full
The memory interface is used to control the interface ■ Buffer Overflow
between the USB block and the SRAM memory unit. The
■ Buffer Underflow

282 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 USB

These arbiter interrupt requests are routed to only one inter- The USB needs a nominal voltage of 3.3V for its operation.
rupt line which acts as a signal to the interrupt controller. The block uses the regulated digital voltage Vccd. It sup-
ports an internal regulator which is used for voltage regula-
26.2.2.6 Synchronization Block tion. While in the Standard Voltage Range, the voltage is
regulated to 3.3V by the internal regulator. While in the
The USB block uses 2 clocks: the System Clock and the
Lower Voltage Range, the internal regulator should be
USB Clock. The System Clock is used by the Arbiter. The
bypassed. The “reg_enable” bit in the USB_USB_CR1 reg-
USB Clock is used by the SIE and the OsClock module.
ister is used to control the regulator usage.
Since these two are different clocks, synchronization is
required between the blocks. The handling of the synchroni- In all other voltage ranges (that is, 1.7V to 3.15V, 3.45V to
zation is done by this block. 4.35V, and 5.25V to 5.5V, the “suspend,” “pull up,” and “high
impedance drive” modes will work properly because the cur-
rent specification is met. The Drive modes can be selected
26.3 How it Works using the registers USB_USBIO_CR1 and
The USB Block operates at a certain frequency and voltage USB_USBIO_CR2.
range. For proper operation of the USB block, the user must
ensure that the operating ranges are within tolerances. The 26.3.3 Transceiver
following sections discuss the operating ranges required for
The USB block includes the transmitter and the receiver.
the PSoC USB.
The signal between the USB device and the host is a differ-
ential signal. The receiver receives the differential signal
26.3.1 Operating Frequency and converts it to a single ended signal. The single ended
The USB block needs two different clocks to work: the Sys- input is given to the USB block at a nominal voltage range of
tem Clock which controls the Arbiter, memory and the regis- 1.55V to 1.95V. The transmitter converts the single ended
ter block, and the USB clock which controls the SIE and the signal to the differential signal and transmits it to the host.
OsClock. The differential signal is given to the upstream devices at a
nominal voltage range of 0V to 3.3V.
■ Minimum system clock – 24 MHz
■ USB Clock for Full Speed operation – 48 MHz (+0.25% The transceiver also supports the PS/2 signals. It can
tolerance) receive and transmit PS/2 signals at a nominal voltage of 0V
to 5V. The transceiver has the pull up resistors to support
The USB needs a 48 MHz clock to function. The clock to the the PS/2 signals.
USB is called the clk_usb. The clk_usb can be derived from
either IMOCLK, doubler clock (IMOCLK * 2), PLL, or the DSI Apart from the PS/2 signals, the transceiver also supports
clock. For further details on the clock for this block, refer to the CMOS signal levels. The PS/2 and the CMOS modes
the Clocking System chapter on page 147. The OsClock can be selected using the registers USB_USBIO_CR1 and
block of the USB trims the USB clock to lock to the fre- USB_USBIO_CR2.
quency of the USB packets. The USB clock is clocked to the The Transmitter can be manually forced to transmit signals.
USB token as per the USB 2.0 Specification. When the fre- The register USB_USBIO_CR0 is used to manually transmit
quency is locked with other USB bit streams, the block will the signals. Examples are as follows:
locate a particular edge in the USB packet. The number of
■ When the manual transmission is enabled, the register
clock periods between these edges is measured to lock the
can be configured to transmit Single Ended Zero signal
internal oscillator frequency with the frequency of the USB
(that is, D+ and D- are low).
packet. The frequency tuning value is sent to the Clocking
system by the USB Block to lock the frequency. The locking ■ Configurable to transmit the USB signals. The USB sig-
of the frequency is done by the hardware and needs no user nals can be two types:
intervention. The Synchronization Block of the Arbiter han- ❐ D+ low and D- high = J
dles the synchronization of the USB Clock and System ❐ D+ high and D- low = K
Clock.
■ The register also has a bit which is used to read the
received signal levels. The bit can show if D+ < D- or D+
26.3.2 Operating Voltage > D-.
The USB block can operate in two voltage ranges:
■ Standard voltage range – 4.35V to 5.25V
■ Lower voltage range – 3.15V to 3.45V

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USB

26.3.4 Endpoints ❐ Automatic for acknowledged transfer

❐ Can be enabled for non-acknowledged transfer
The SIE and Arbiter support 8 data endpoints (EP1 to EP8)
■ The register USB_SIE_EP_INT_EN is used to enable
and one control endpoint (EP0). The data endpoints share
the SRAM memory area of 512 bytes. The endpoint memory the SIE interrupt for each endpoint. Each bit in the regis-
management can be either “Manual” or “Automatic.” The ter corresponds to each endpoint.
endpoints are configured for direction and other configura- ■ The status of the SIE interrupt can be read using the
tion using the SIE and arbiter registers. The endpoint “read USB_SIE_EP_INT_SR register. These bits are sticky
address” and “write address” registers are accessed bits and need firmware to clear the status.
through the Arbiter. Each endpoint supports a set of inter- ■ Separate interrupt line for each data endpoint and con-
rupts. The interrupts can be enabled or disabled for an indi- trol endpoint.
vidual endpoint. The interrupts for each endpoint can also
■ The register SIE_EP_INT_EN and SIE_EP_INT_SR
be collectively enabled or disabled.
control/ show the status of both the SIE and the Data
The endpoints can be individually made active. In the Auto Endpoint interrupts.
Management mode, the register USB_EP_ACTIVE is writ-
ten to control the active state of the endpoint. The endpoint Arbiter Interrupt Line
activation cannot be dynamically changed during runtime. In The arbiter generates interrupts for the endpoints during
Manual Memory Management mode the firmware decides these events:
the memory allocation, so it is not required to specify the
■ Buffer overflow
active endpoints. The EP_ACTIVE register is ignored during
the manual memory management mode. The ■ Buffer underflow
USB_EP_TYPE register is used to control the transfer direc- ■ DMA grant
tion (IN, OUT) for the endpoints. The control endpoint has a ■ IN endpoint local buffer full
separate 8 bytes for its data.
This information applies to the arbiter interrupts.
26.3.5 Transfer Types ■ These interrupts can be generated by every endpoint.
The register USB_ARB_EPx_INT_EN (where x = 1 to 8
The PSoC USB supports Full Speed transfers and is compli- for each endpoint) is used to enable or disable each
ant with the USB 2.0 Specification. It supports four types of interrupt for the endpoint.
transfers:
■ The Status of each interrupt for every endpoint can be
■ Interrupt Transfer read using the USB_ARB_EPx_INT_SR (where x = 1 to
■ Bulk Transfer 8 for each endpoint) register.
■ Isonchronous Transfer ■ The interrupt for an endpoint can be collectively enabled
■ Control Transfer or disabled using the USB_ARB_INT_EN register_ Each
bit in this register corresponds to each endpoint.
For further details about these transfers, refer to the USB
■ The status of the Arbiter interrupt for an endpoint can be
Specification 2.0.
read using the USB_ARB_INT_SR register.

26.3.6 Interrupts There is only one arbiter line common for all the endpoints.

The interrupts are generated by the SIE and the Arbiter. The SIE Interrupt for SOF
following interrupt lines are available for the interrupt con-
■ Generated whenever the SOF is received.
troller:
■ Nine SIE interrupt lines (one for each endpoint and con- SIE Data Interrupt
trol endpoint)
■ Interrupt generated for the data valid or error in transac-
■ Arbiter interrupt line
tion.
■ SIE interrupt line for SOF
■ One interrupt line common for all endpoints.
■ SIE data endpoints interrupt line
■ The sticky bit “data_valid,” in the USB_SIE_EPx_CNT0
■ Reset interrupt line register, indicates the data valid state.
■ The sticky bit “err_in_txn” in the USB_SIE_EPx_CR0
Nine SIE Interrupts
register indicates the error in transaction state.
■ Generated after the completion of packet transmission.

284 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 USB

26.4 Logical Transfer Modes The logical transfer mode is a combination of memory man-
agement and DMA configurations. The Logical Transfer
The USB block in PSoC devices supports two types of logi- modes are related to the data transfer within the USB block
cal transfers. The logical transfers can be configured using (i.e., to/ from the SRAM memory unit for each endpoint). It
the register setting for each endpoint. Any of the logical does not represent the transfer methods between the device
transfer methods can be adapted to support the three types and the host (i.e., the transfer types specified in the USB 2.0
of data transfers (Interrupt, Bulk, and Isochronous) men- Specification).
tioned in the USB 2.0 Specification. The Control transfer is
The USB block supports two basic types of transfer modes
mandatory in any USB device.
and are detailed in Table 26-2 on page 285.
■ Store and Forward mode
■ Cut Through mode

Table 26-2. USB Transfer Modes

Feature Store and Forward Mode Cut Through Mode
SRAM Memory Usage Requires more memory Requires less memory
SRAM Memory Management Manual Auto
Each endpoint is allocated less share of memory automatically by
512 bytes of SRAM shared between endpoints. Sharing
SRAM Memory Sharing the block. Rest of memory is available as “Common Area.” This
is done by firmware.
Common Area is used during the transfer.
Memory filled with data only when SRAM IN command is received.
Entire packet present in SRAM memory before the IN
IN Command Data is given to host when enough data is available (based on DMA
command is received.
configuration). Does not wait for the entire data to be filled.
Entire packet is written to SRAM memory on OUT com- Waits only for enough bytes (depends on DMA configuration) to be
OUT Command mand. After entire data is available, it is copied from written in SRAM memory. Once enough bytes are present, it is
SRAM memory to the USB device. immediately copied from SRAM memory to the USB device.
Data is transferred when all bytes have been written to Data is transferred when enough bytes are available. It does not wait
Transfer of Data
the memory. for the entire data to be filled.
No DMA mode
Types Based on DMA Only Auto DMA mode
Manual DMA mode
Supported Transfer Types Best suited for Interrupt and Bulk transfers Best suited for Isochronous transfer

Every endpoint has a set of registers that need to be handled during the modes of operation, as detailed in Table 26-3.

Table 26-3. Endpoint Registers

Register Comment Content Usage
This register indicates the SRAM location to which the data in the
ARB_RWx_WA Endpoint Write Address register Address of the SRAM
Data register is to be written.
This register indicates the SRAM location from which the data must
ARB_RWx_RA Endpoint Read Address register Address of the SRAM
be read and stored to the Data register.
Data register is read/ written to perform any transaction.
IN command: Data written to the Data register is copied to the
SRAM location specified by the WA register. After write, the WA
value is automatically incremented to point to the next memory loca-
ARB_RWx_DR Endpoint Data Register 8-Bit Data tion.
OUT command: Data available in the SRAM location pointed by the
RA register is read and stored to the DR. Once the DR is read, the
value of RA is automatically incremented to point to the next SRAM
memory location that must be read.
Holds the number of bytes that can be transferred.
IN command: Holds the number of bytes to be transferred to host.
SIE_EPx_CNT0 and OUT command: Holds the maximum number of bytes that can be
Endpoint Byte Count Register Number of Bytes
SIE_EPx_CNT1 received. The firmware programs the maximum number of bytes that
can be received for that endpoint. The SIE updates the register with
the number of bytes received for the endpoint.
Controls how the USB device responds to the USB traffic and the
“Mode” bits in SIE_EPx_CR0 Mode Values Response to the Host USB host. Some examples of mode include ACK, NAK, STALL, etc.
Refer to Table 26-1 on page 281 for additional details.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 285

USB

In the Manual Memory Management case, the endpoint Figure 26-2. No DMA Access IN Transaction
read and endpoint write address registers are updated by
Write WA register (based on
the firmware. So the memory allocation can be done as required memory allocation)
required by the user and the memory allocation decides
which endpoints are active. (i.e., the user can decide to
share the 512 bytes for all the 8 endpoints or a lesser num- Write packet size to
Byte Count register
ber of endpoints).
Value automatically
In the Automatic memory management case, the endpoint written to the SRAM
read and endpoint write address registers are updated by Write data to Data specified by WA
register location. WA++
the USB block. The block assigns memory to the endpoints
which have been activated using the EP_ACTIVE register. No
The size of memory allocated depends on the value in the
Is all
BUF_SIZE register. The rest of the memory, after allocation, data written to
is called the “Common Area” memory and used for the SRAM?

transfer of data.
Yes
In the following text, the algorithm for the IN and OUT trans-
action for each mode is discussed. An IN transaction is Write the RA
when the data is read by the USB host (for example, PC). register (same as
initial WA register)
An OUT transaction is when the data is written by the USB
host to the USB device (in this case, PSoC 3 or PSoC 5).
The choice of using the DMA and memory management can Set mode value in
CR0 register
be configured using the USB_ARB_CFG register and the
mode is common to all endpoints.

26.4.1 Store and Forward Mode Wait

Is IN
command
received? Responds
26.4.1.1 No DMA Access No automatically
with ACK
This is the Manual Memory Management mode with no (configured as
Yes Mode value)
DMA access.
USB Block reads
value from RA and
IN Transaction (CPU Write, SIE Read). The steps for an transmits to host.
IN transaction on an IN endpoint are shown in Figure 26-2. RA++

No

Is all data
transmitted?

Yes Interrupt
Generated
Set the mode as NAK for the
last byte in transfer. Status
bits set by the block

OUT Transaction (CPU Read, SIE Write). The steps for

an OUT transaction on an OUT endpoint are shown in
Figure 26-3.

286 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 USB

Figure 26-3. No DMA Access OUT Transaction 26.4.1.2 Manual DMA Access
Write WA register (based on This is the Manual Memory Management mode with Manual
required memory allocation) DMA Access. This mode requires the configuration of the
DMA controller. See DMA Interface on page 282 for details
To inhibit CRC
and constraints regarding DMA transfers to the USB block.
set the “crc_bypass” bit Write maximum packet size to
in the ARB_EPx_CFG Byte Count register
This mode is similar to the No DMA Access except that the
register
write/read of packets is performed by DMA. A DMA request
for an endpoint is generated by setting the DMA_CFG bit in
Set mode value in
CR0 register the ARB_EPx_CFG register. When the DMA service is
granted and is done (DMA_GNT), an arbiter interrupt can be
programmed to occur. The transfer is done using a single
Wait DMA cycle or multiple DMA cycles. After completion of
Is OUT every DMA cycle the arbiter interrupt (DMA_GNT) is gener-
No command ated. Similarly, when all the bytes of data (programmed in
received?
Responds the byte count) have been written to the memory, the arbiter
automatically
with ACK interrupt occurs and the IN_BUF_FULL bit is set.
Yes (configured as
mode value)
IN Transaction (CPU Write, SIE Read). The steps for an
Data received from IN transaction on an IN endpoint are shown in Figure 26-4.
host written to SRAM
location WA
WA++
No

Is all
data written to
SRAM?

Yes

SIE sets mode to NAK. Updates Byte

Count with actual number of data
received and sets the data valid bit

SIE Data
Interrupt
Write the RA value
(same as initial Generated
WA)

Data in Data
register is read USB Block reads the data at
by CPU and location RA and writes to Data
given to device. register
RA++ is done
automatically.
No
Is all
data read from
SRAM?

Yes

End

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 287

USB

Figure 26-4. Manual DMA IN Transaction Figure 26-5. Manual DMA OUT Transaction
Write WA register (based on required memory allocation)
Write WA register (based on
required memory allocation)
Write Packet size to Byte Count register

To inhibit CRC set

Set the DMA request
the “crc_bypass” Write maximum packet size to
Value bit in the Byte Count register
DMA writes data to Data register automatically ARB_EPx_CFG
written to the
register.
SRAM specified
No Is all by WA location.
data written to WA++ Set mode value in
DMA_GNT interrupt generated SRAM? CR0 register
for every DMA cycle.
IN_BUF_FULL interrupt
Yes
generated after full data write.
Wait
Write the RA register (same as initial WA register)
Is OUT
No command
Set Mode value in CR0 register received?
Responds
automatically
Wait with ACK
Is IN Yes (configured as
No command Mode value)
Responds
received?
automatically
with ACK Data received from
(configured as host written to
Yes Mode value)
SRAM location WA

USB Block reads value from RA and WA++

transmits to host. RA++ No

Is all
data written to
Is all data SRAM?
No
transmitted?
Interrupt
Generated Yes
Yes

Set the mode as NACK for the last byte in

SIE sets mode to NACK. Updates Byte
transfer. Status bits set by the block.
Count with actual number of data
received and sets the data valid bit

SIE Data
Interrupt
Write the RA value
(same as initial Generated
WA)

OUT Transaction (CPU Read, SIE Write). The steps for Configure the
Data in Data DMA request
an OUT transaction on an OUT endpoint are shown in register is
Figure 26-5. read by DMA
and given to USB block reads the data at
device. location RA and writes to Data
RA++ register

No
Is all
data read from
SRAM?
At the end of
every DMA cycle,
Yes DMA_GNT
interrupt is
End generated.

288 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 USB

26.4.2 Cut Through Mode

This is the Auto Memory Management mode with Auto DMA
Access. The CPU programs the initial buffer size require-
ment for IN/OUT packets and informs the Arbiter block of
the endpoint configuration details for the particular applica-
tion being considered. The block then controls memory par-
titioning and handling of all memory pointers. During the
memory allocation, each active IN endpoint (set by the
EP_ACTIVE and EP_TYPE registers) is allocated a small
amount of memory configured using the BUF_SIZE register.
The remaining memory is left as “Common Area” and is
common for all endpoints.

In this mode, the memory requirement is less and it is suit-

able for the Full Speed “Isochronous Transfer” up to 1023
bytes.

When an IN command is sent by the host, the device

responds with the data present in the dedicated memory
area for that endpoint. It simultaneously issues a DMA
request for more data for that EP. This data fills up in the
Common Area. The device does not wait for the entire pack-
ets of data to be available. It only waits for the
(USB_DMA_THRES_MSB, USB_DMA_THRES) number of
data available in the SRAM memory and begins the transfer
from the common area. See DMA Interface on page 282 for
details and constraints regarding DMA transfers to the USB
block.

Similarly, when an OUT command is received, the data for

the OUT endpoint is written to the common area. Once
some data (data greater than (USB_DMA_THRES_MSB,
USB_DMA_THRES)) is available in the common area, the
Arbiter block initiates a DMA request to the PHUB and the
data is immediately written to the device. The device does
not wait for the common area to be filled.

This mode requires the configuration of the DMA_THRES

and DMA_THRES_MSB registers to hold the number of
bytes that can be transferred in one DMA transfer. Similarly,
the PHUB register must be configured for the BURSTCNT
values. The BURSTCNT value must always be equal to the
value set in the DMA_THRES registers. The block sends
the Termin signal to the PHUB along with the last data byte
of the packet. Apart from the DMA registers, this mode also
needs the configuration of the BUF_SIZE for the IN and the
OUT buffers and the EP_ACTIVE and the EP_TYPE regis-
ters.

IN Transaction (CPU Write, SIE Read). The steps for an

IN transaction on an IN endpoint are shown in Figure 26-6
on page 290.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 289

USB

Figure 26-6. Cut Through Mode IN Transaction

Write packet size of the endpoint
to Byte Count register

Set IN_DATA_RDY for the endpoint

in ARB_EP1_CFG register

Block automatically raises interrupt

for DMA
This memory location is very limited. The
Data automatically read
memory location is filled initially to make sure
and written to SRAM
the host does not stall when an IN command
pointed by WA. WA++
is sent. When an IN command is received the DMA writes to Data register.
PHUB initiates the copy of data from device
to common area. This initialization would take
some time. The data in the end point buffer is
transmitted until the data is copied to the No
common area. Is the endpoint
IN_BUF_FULL Interrupt
buffer filled?
generated

Yes

Update Mode value in

the Mode register

Wait

Is IN command
No
received
Block automatically sends
the ACK. (Configured as
Yes Mode value)

Is the complete
Yes data available No
in the memory

SIE reads data from SRAM

(specified by location RA) and Raise a DMA request
transmits to host

RA++
No
SIE reads data from SRAM In the mean time, the PHUB
Is all data in buffer (specified by location RA) and initiates the transaction. The
transmitted? transmits to host data from the device is copied
to the common area. The data
RA++
No from the USB is written to the
SRAM by the DMA.
Set the data valid bits Is all data in buffer
transmitted?

End Yes
Wait

Is data in Common Area >

No
{DMA_THRES, DMA_THRES_MSB)

Yes
The process is continued
till all the data is transferred Initiate PHUB
transfer.

Block transfer data

available in Common
Area

Set the data valid bits

End

290 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 USB

OUT Transaction (CPU Read, SIE Write). The steps for Figure 26-8. IN Transaction
an OUT transaction on an OUT endpoint are shown in
Set the mode bits to
Figure 26-7. ACK the IN token

Figure 26-7. Cut Through Mode OUT Transaction No

Write maximum bytes to Byte Count register Is SETUP

token received

Yes
Program the Mode register for the endpoint

The block ACKs it

Wait
Is the
No OUT command received Generates Interrupt and sets the bit to
from host? indicate that IN token is received.

Yes
Read the status bit and the
Data valid bit
The DMA writes the received
data to the SRAM in location
specified by WA

WA++ Is Data Valid?

No

Is data in Yes
SRAM > (DMA_THRES,
DMA_THRES_MSB)? Read the EP0_DRx register to find the
type of request

Yes
Copy the required data to the
The process DMA request is EP0_DRx registers
is continued raised
till all the data Data in the Data
is transferred
USB Block writes register is read and
the data from Set the data valid bit and the mode bits.
given to the USB
SRAM to the Data Also update the byte count value
device by the DMA.
register
No RA is incremented
automatically. No

Is all the Is IN token

data from SRAM copied received?
to device?
No
No Yes
Yes

The block transmits the data from

Set the data valid bits the EP0_DRx registers

End The block sets the mode value to

NAK all further IN tokens.

26.4.3 Control Endpoint Logical Transfer Blocks generates interrupt on receiving ACK from
host and sets the IN byte received bit.
The control endpoint has a special logical transfer mode. It
doesn’t share the 512 bytes of memory. Instead it has dedi-
cated 8 byte register buffer. The IN and OUT transaction for Are all bytes
transferred?
the control endpoint is detailed below:

Yes

End

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 291

USB

Figure 26-9. OUT Transaction 26.5 PS/2 and CMOS I/O Modes
Program the mode
bits for ACK_OUT The USB transceiver is designed in such a way that, apart
No from the USB signals, it can also transmit other signal lev-
els. The pull up resistors are available at the transmitter end,
Is the SETUP token which enables additional signal levels. The registers
received?
USB_USBIO_CR1 and USB_USBIO_CR2 must be config-
Yes ured to get different signal levels.
The block ACKs The “test_res” bit in the USBIO_CR2 register puts the trans-
the SETUP token
mitter in pull up mode where the pull up resistors are con-
nected.
Generates Interrupt and sets a bit in
EP0_CR register to indicate that The I/O mode bit in the USBIO_CR1 register puts the USB
SETUP token was received. in either USB mode or Drive mode. When put in Drive mode,
the USB signals are disabled and the bits DMI and DPI are
Read the Data valid bit in EP0_CNT used to drive D- and D+, respectively. There are two differ-
ent drive modes. In CMOS Drive mode, D+ follows the DPI
and D- follows the DMI. In the case of Open Drain mode, the
Is data valid? pull up resistors play a role. In this state, when the DPI and
DMI bits are set to high, D+ and D- are high impedance.
Yes
The pull up resistors can be connected between Vdd and
Read EP0_DRx to read the type of request
D+ and D-, independent of the Drive modes. The bit
“p2puen” is used for this.

Update the mode bits to ACK an An internal pull up of 1.5 k is also supported and can be
OUT token
enabled using the register USBIO_CR1. The USBIO_CR1
No register is also used to poll the state of the D+ and D- pins.
Is OUT token
received?

Yes

The block stores the received byte to the

EP0_DRx register and ACK the received byte.

Interrupt generated. No

No

Read the status and data valid bits

Is data valid? No

Yes

Set the mode bit to NAK all OUT tokens till

all bytes have been received.

Are all bytes

received?

Yes

End

292 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 USB

26.6 Register List

Table 26-4. USB Register List
Register Name Comments Features

General Registers

USB_CR0 USB Control register 0 To enable the USB and store the USB Device address

USB_CR1 USB Control register 1 To monitor the bus activity and control the regulator operation

USBIO_CR0 USB I/O Control register 0 To control the operation on D+ and D- signals

USBIO_CR1 USB I/O Control register 1 To configure the pull up registers

USBIO_CR2 USB I/O Control register 2 To control in test modes

USB_BUF_SIZE Dedicated endpoint buffer size register Stores the dedicated buffer size for each endpoint

USB_EP_ACTIVE Endpoint active register Stores the status of active endpoints

USB_EP_TYPE Endpoint Type register Stores the type of endpoint either IN/OUT
USB_EP0_DRx
Control endpoint Data register The endpoint 0 is the control endpoint
x= 0 -7
USB_EP0_CR Endpoint 0 Control register

USB_EP0_CNT Endpoint 0 Count register

SIE Registers

USB_SIE_EP_INT_EN Interrupt enable register To enable the interrupts for each endpoint

USB_SIE_EP_INT_SR Interrupt status register To find the status of interrupt for each endpoint
USB_SIE_EPx_CNT0
Non control endpoint Count register Handles the Data toggle state and MSB of the 11 bit counter
x= 1- 8
USB_SIE_EPx_CNT0
Non control endpoint Count register LSB of the 11 bit counter
x= 1- 8
USB_SIE_EPx_CR0 Controls the mode for the endpoint and stores the state of error, ACK
Non control endpoint Control register
x=1-8 and NACK for the endpoint.
OsClock Registers

OSCLK_DR0 OsClock Lock register 0 The LSB of the Oscillator locking circuit output

OSCLK_DR1 OsClock Lock register 1 The MSB of the Oscillator locking circuit output

Arbiter Registers
USB_ARB_EPx_CFG Stores the configuration for the transfer modes, reset of pointers and
Endpoint configuration register
x=1–8 CRC
USB_ARB_Epx_INT_EN
Endpoint Interrupt enable register To enable the required interrupts
x=1–8
USB_ARB_Epx_SR To indicate status like overflow, underflow, DMA grant and Local buffer
Endpoint status register
x = 1- 8 full
USB_ARB_RWx_WA
Endpoint Write address register Stores the LSB 8 bits of the Write address pointer
x=1–8
USB_ARB_RWx_WA_MSB
Endpoint Write address register Stores the MSB 1 bit of the Write address pointer
x=1–8
USB_ARB_RWx_RA
Endpoint Read address register Stores the LSB 8 bits of the Read address pointer
x=1–8
USB_ARB_RWx_RA_MSB
Endpoint Read address register Stores the MSB 1 bit of the Read address pointer
x=1–8
USB_ARB_CFG Arbiter Configuration register

USB_ARB_INT_EN Arbiter Interrupt Enable register To enable the interrupt for each endpoint

USB_ARB_INT_SR Arbiter Interrupt Status register To store the interrupt status for each endpoint

USB_CWA Common Area Write Address register The LSB 8 bits of the Write address pointer

USB_CWA_MSB Common Area Write Address register The MSB 1 bit of the Write address pointer

USB_DMA_THRES DMA Threshold Count register The LSB 8 bits of the DMA threshold count register

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 293

USB

Table 26-4. USB Register List (continued)

Register Name Comments Features

USB_DMA_THRES_MSB DMA Threshold Count register The MSB 1 bit of the DMA threshold count register

USB_SOF0 Start of Frame register 0 LSB 8 bits of the Start of Frame counter

USB_SOF1 Start of Frame register 1 MSB 3 bits of the Start of Frame counter

USB_BUS_RST_CNT Bus reset count register The reset counter for the USB

294 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 27. Timer, Counter, and PWM

Timer blocks in PSoC® devices are 8/16 bits and configurable to act as Timer, Counter, or Pulse Width Modulator (PWM)
blocks that play important roles in embedded systems. PSoC devices give a maximum of four instances of the block. If addi-
tional blocks are required, they can be configured in the UDBs using PSoC Creator™. Timer blocks have various clock
sources and are connected to the General Purpose Input/Output (GPIO) though the Digital System Interconnect (DSI).

27.1 Features
■ 8/16-bit timer/counter/PWM that acts as a down counter
■ Supports the following modes:
❐ Timer
❐ Gated Timer
❐ Pulse-width Modulator (PWM)
❐ One Shot
■ Supports interrupts upon:
❐ Terminal count – the final value in the Count register is reached
❐ Compare true – the timer value matches with the Compare register
❐ Capture – capture of timer value on edge detection in the Capture signal
■ Counts when Enable signal is asserted
■ Supports the free running timer
■ Period reload on start, reset, and terminal count
■ Selectable clock source
■ Supports kill and dead band features

27.2 Block Diagram

Figure 27-1 on page 296 shows one timer block.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 295

Timer, Counter, and PWM

Figure 27-1. Timer Block Diagram

Clock
Timer Block
DSI
Configuration registers
DSI CFG0 and CFG1
Terminal Count Terminal Count
Output signal Output pin
Capture Period PER1 PER0
signal registers (MSB) (LSB)
Compare Compare
Output signal Output pin
Capture CAP1 CAP0
registers (MSB) (LSB)
Timer Reset pin Timer
Enable
Terminal Count
signal Count
Enable pin Interrupt signal
registers CNT_CMP1 CNT_CMP0
(MSB) (LSB) Capture/Compare Interrupt signal
Kill pin Compare Interrupt signal to
registers Interrupt Controller
Capture pin Kill Timer Stop
signal Interrupt signal
External Route Registers Timer Enable
RT0 and RT1 Interrupt signal

Timer Status Register SR0

Reset
signal

27.3 How It Works

The block receives a clock signal that is selectable from dif- 27.3.1 Clock Selection
ferent sources. The block in PSoC devices is a down coun-
ter and counts for every rising edge of the input clock. It The block supports the flexibility to select the required clock
counts down from the period value to zero. When it reaches source. As shown in Figure 27-2 on page 297, the block
zero (terminal count) the period value is reloaded into the uses the CLK_BUS frequency, or it is routed through one of
count register, and the timer continues to count. If the timer the eight selectable clock lines CLK_BUS_EN 0…7, which
is configured for One Shot mode, the timer stops when it are synchronous to the clock bus.
reaches the terminal count. Clock selection is done through the Configuration register
The timer block can act in various modes, depending on CFG1. If the CLK_BUS bit in register CFG1 is set, the block
appropriate configuration of the registers: uses the CLK_BUS frequency, instead of the eight select-
able digital clock lines.
■ Timer
❐ Free Run If the CLK_BUS bit is set to 0, one of the eight selectable
lines is used for the clock. The bits CLK_BUS_EN_SEL in
❐ Gated Timer
Configuration register CFG1 are set to choose one of eight
– Pulse Width selectable digital clock lines. The clock for the digital clock
lines can be derived from the CLK_BUS or it can be another
– Period
UDB signal or external clock signal.
– Stop on Interrupt
■ PWM
■ One Shot

The block can be used as a timer to capture time of external

event, to measure period and pulse width of the input signal,
and to find the time of occurrence of interrupt and as a PWM
generation unit.

296 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Timer, Counter, and PWM

Figure 27-2. Clock Selection

CLK_BUS_EN_SEL[2:0] CFG1

Clock Select CLK BUS

Clock Bus Enable 0

Clock Bus Enable 1
Clock Bus Enable 2
Latch
Clock Bus Enable 3
D Q Clock
Clock Bus Enable 4
Signal
Clock Bus Enable 5
CLK
Clock Bus Enable 6
Clock Bus Enable 7

CLK BUS

27.3.2 Enabling and Disabling Block 27.3.3 Input Signal Characteristics

The block is enabled or disabled by setting the Enable bit The block has four input signals separate from the clock sig-
EN in Configuration register TMRx_CFG0. All the required nal:
configurations for the block must be done before it is ■ Enable
enabled. When the block is enabled, it functions in the con-
■ Capture
figured mode (Timer or PWM). Enabling a block updates the
registers with the new configured value. Disabling a block ■ Timer Reset
retains the values in the registers until it is enabled again. ■ Kill
■ When the EN bit is set, the previous state is cleared and Input signals are connected to the GPIO through the Digital
the count register is loaded with the reload value from System Interconnects (DSI). The user maps the input pins
the period register. The block starts to count. to the DSI routing through External Routing register RT0.
■ When Configuration and Period registers are modified DSI 1 through DSI 4 within any block can be routed to as
with the EN bit set to ‘1’, the changes go into effect only any of the above input signals, depending on user mapping.
after the completion of the current running period (at the Mapping between DSI routing and the input pins is not fixed.
terminal count). See Figure 27-1 on page 296.
■ When Configuration and Period registers are modified The block has two outputs, terminal count and compare out-
with the EN bit set to ‘0’, the changes go into effect put. They are synchronized to the clock signal. This is done
immediately after the EN bit is set to ‘1’. by setting the bits in the external routing register RT1. When
■ When the block is enabled, the count value is loaded the pins are set as asynchronous, the changes go into effect
with the new reload value, regardless of the state of the immediately. If synchronous, the changes go into effect dur-
register before setting EN = ‘0’. ing the next clock cycle.

When the register values are changed after setting EN = ‘0’,

the changes go into effect immediately. This is useful during
the PWM mode, where the user can change the PWM
period or duty cycle immediately.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 297

Timer, Counter, and PWM

27.3.3.1 Enable Signal 27.3.3.2 Capture Signal

The effect of the enable signal is explained in the timing dia- The capture signal is useful to find the time when an event
gram for each mode. The following characteristics apply: occurs. The capture signal is usually combined with the free
■ Gated timer pulse width mode and period mode take the run timer mode. For the timer block to respond to the cap-
Enable signal as input. ture signal, the enable signal must be asserted before
asserting the capture signal. The following describes the
■ Gated timer stop at interrupt mode and PWM mode need
process:
an asserted Enable signal to function properly.
■ The time value is captured in the capture register by
■ Free run mode is independent of the enable signal.
assertion of the Capture signal for the block.
■ Enable signal polarity is reversed by setting the bit INV
■ Whenever the rising edge of the Capture signal is
in configuration register CFG0.
detected, the count value is captured in the Capture reg-
■ Use of the capture signal to capture a time instance is ister.
valid only when the enable signal is asserted.
■ The capture register is read to find the time when the
assertion of Capture signal occurred.
■ With every assertion of the Capture signal, a new value
is captured to the Capture register.
■ An interrupt can be configured to occur at the assertion
of the Capture signal. The interrupt bit in the Status reg-
ister should be unmasked for the capture interrupt to
occur. The Capture register value can be read in the
capture ISR.
■ When using a fixed function timer with interrupt on cap-
ture enabled, read the capture register twice. The first
reading yields an incorrect value (0xff)”

Figure 27-3 shows the effect of the capture signal (period

register = 0xFFFF).

298 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Timer, Counter, and PWM

Figure 27-3. Capture Mode Timing Diagram

Clock

EN Bit

Enable
0xFFFF 0xFFFF
0xFFFE 0xFFFE
0xFFFD 0xFFFD

0x1000

0x1 0x1
Count Value 0x0
0x0

Capture
Input Pin

Capture
0xFFFD 0x1000
Register
Capture
Interrupt

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 299

Timer, Counter, and PWM

27.3.3.3 Timer Reset Signal

When the timer reset pin is asserted, the count value in the Count register (TMRx_CNT) is set to 0x00. When the timer reset
pin is deasserted, the TMRx_CNT register is reloaded with the period value, and it functions in the configured mode. This sig-
nal stops the block operation for the time during which the timer reset signal is high and then restarts the operation from the
beginning.

Figure 27-4 is a timing diagram for the timer reset signal (Period register = 0xFFFF).

Figure 27-4. Timer Reset Signal Timing Diagram

Clock

EN Bit

Enable

Timer
Reset

0xFFFF 0xFFFF
0xFFFE 0xFFFE
0xFFFD 0xFFFD

0x0100 0x0100
0x00FF 0x00FF

Count Value
0x1
0x0000 0x0

27.3.3.4 Kill Signal

The Kill signal is valid only during PWM mode. The effect of
the kill signal is explained in PWM mode in the sections
ahead.

300 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Timer, Counter, and PWM

27.3.4 Operating Modes

27.3.4.1 Timer Mode – Free Run Mode ❐ An interrupt at the terminal count – To initiate an
interrupt, the terminal count interrupt in the Status
The register configuration for Timer mode is: register must be unmasked.
■ Registers to set – TMTx_CFG0, TMRx_CFG1 ■ The current timer value is read from the 8-bit Count reg-
■ Bit MODE in TMRx_CFG0 = 0 – Timer mode isters CNT0 and CNT1. In the case of the 32-bit control-
■ Bits MODE_CFG in TMRx_CFG1 = 0 – Timer runs in ler, a 16-bit read of the Capture register can be done.
continuous mode ■ In the case of the 8-bit controller, the 8-bit read is done.
When an 8-bit read is done for the CNT0 register (LSB)
The Free Run mode is mainly used to obtain the current
the values of LSB and MSB are automatically captured
system time. Timer operation, automatically forced into the
in the Capture registers. The user can read the Capture
Free Run mode, occurs independent of the state of the
register to obtain the 16-bit time value.
Enable pin. This mode is called Free Run because the timer
runs even if the state of the Enable pin is low. Figure 27-5 shows the terminal count output signal and the
terminal count interrupt behavior in the Free Run mode
The following describes the process:
(Period register value = 0xFFFF) and illustrates the following
■ The timer is a down counter, and the current time value behavior.
is stored in the TMRx_CNT registers.
■ Independence of the Timer from the Enable signal for
■ The reload value for the timer is stored in the Period reg- the block
isters TMRx_PER0 and TMRx_PER1.
■ The effect of changing the Period register with both EN =
■ After the count reaches zero (terminal count), the period ‘1’ and EN = ‘0’
value is reloaded automatically to the Count registers for
❐ When the Period register is changed without setting
the timer to count. The reload value determines the EN = 1, the effect takes place only after the terminal
period for the timer. Two types of output result when the count.
terminal count is reached:
❐ When the Period register is changed with EN = 0, the
❐ A terminal count output signal that generates a pulse effect takes place immediately after setting EN = 1.
at the terminal count – The terminal count output sig-
nal can be routed to any GPIO through the DSI.
Figure 27-5. Free Run Mode Timing Diagram

Clock

EN Bit
Period changed Period changed
without changing EN after EN = 0
Period
0xFFFF 0x00FF 0xE000
Value
Automatic reload Immediate effect
of period after EN = 1
0xFFFF 0xFFFF 0x00FF 0xE000 0xE000
0xFFFE 0xFFFE 0x00FE 0xDFFF 0xDFFF
0xFFFD 0xFFFD 0xDFFE 0xDFFE
0x00FD

0x1 0x1 0x1 0x1

Count Value
0x0 0x0 0x0 0x0

Terminal Count
Output Pin

Terminal
Count
Interrupt

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Timer, Counter, and PWM

27.3.4.2 Gated Timer Mode

In the Gated Timer mode, the timer does not run continu- The following describes the process:
ously; it starts and stops, based on certain criteria. The ■ When the EN bit is set to ‘1’, the Count register is loaded
Gated Timer mode measures some parameters of the input with the period value from the Period register.
signal, including the period of the input signal, the pulse
■ The timer begins counting whenever a rising edge
width of the input signal, and the time after which an inter-
occurs in the enable input. The Count register counts for
rupt occurs. Depending on the configuration of the register,
every clock cycle.
the following modes are supported:
■ When the next edge is reached (falling edge in the case
■ Pulse Width
of a Pulse Width count and the next rising edge in the
■ Period case of a Period count), the timer stops to count.
■ Stop on Interrupt ■ On reaching the terminal count, the TMRx_CNT register
The register configuration for the Counter mode is: is automatically reloaded with the period value. The
timer stop interrupt can be configured to occur when the
■ Registers to set – TMRx_CFG0, TMRx_CFG1
timer stops to count. The timer stop interrupt enable bit
■ Bit MODE in TMRx_CFG0 = 0 – block acts in gated should be unmasked for the interrupt to occur.
timer mode
■ The state of the timer is obtained from the TSTOP bit in
■ Three bits MODE_CFG in TMRx_CFG1 – gated timer the Status register. This sticky bit shows whether the
runs in various modes timer has stopped counting; the user must clear the bit.
The modes are achieved by setting the MODE_CFG bit
appropriately, as shown in Table 27-1.

Table 27-1. MODE_CFG Bit Settings in Gated Timer Mode

MODE_CGF Comments
Pulse width count – counts from positive edge to negative
001
edge
Period count – counts from one positive edge to the next
010
positive edge
011 Counts from enabled to IRQ

The signal for which the pulse or period is measured is

given to the Enable pin.

302 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Timer, Counter, and PWM

Pulse Width Mode The count value is read using 16-bit read in case of a 32-bit
controller and 8-bit read in case of a 8-bit controller. During
The input signal is given to the Enable pin. The timer begins
16-bit read, the count values are read as one 16-bit value
counting at the rising edge of the Enable signal and stops
and the value is captured in the Capture register. During the
counting at the falling edge of the Enable signal. There is a
8-bit read, a read of the CNT0 (LSB value) captures the LSB
latency of one clock cycle for the block to detect the edges.
and MSB in the Capture register. The user can read the
The difference in the count value before and after the count Capture register to obtain the time value.
is equal to the pulse width of the input signal in terms of
Figure 27-6 shows the Gated Timer in Pulse Width mode. In
counts.
this figure, the One Shot mode is disabled, so the timer will
start to count when the next rising edge is encountered.
When the One Shot mode is enabled, the timer stops after
the falling edge and should be enabled again.

Figure 27-6. Gated Timer in Pulse Width Mode

Clock

EN Bit

Enable Pin

0xFFFF
0xFFFE
0xFFFD

0x1001
0x1000 0x1000
0x0FFF
0x0FFE
Count Value

0x0100
0x00FF

Final CNT.reg
Value 0x1000 0x00FF

Timer Stop
Interrupt

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Timer, Counter, and PWM

Period Mode The count value is read, using a 16-bit read in the case of a
32-bit controller and an 8-bit read in case of an 8-bit control-
The input signal is given to the Enable pin. In this mode, the
ler. During a 16-bit read, the count values are read as one
timer begins counting at the rising edge of the Enable signal
16-bit value, and the value is captured in the Capture regis-
and stops counting at the next rising edge. There is a
ter. During the 8-bit read, a read of the CNT0 register (LSB
latency of one clock cycle for the block to detect the edges.
value) captures the LSB and MSB in the Capture register.
The difference in the count value between the start and the The user can read the Capture register to obtain the time
end of the count is equal to the period (in counts) of the value.
input signal.
Figure 27-7 shows the Gated Timer in Period mode. In this
figure, the One Shot mode is disabled; the timer starts to
count when encountering the next rising edge after the
period calculation. When the One Shot mode is enabled, the
timer stops after the second rising edge and should be
enabled again.

Figure 27-7. Gated Timer in Period Mode

Clock

EN Bit

Enable Pin

0xFFFF
0xFFFE
0xFFFD

0x1001
0x1000 0x1000
0x0FFF
0x0FFE
Count Value

0x0100
0x00FF

Final CNT.reg
Value 0x1000 0x00FF

Timer Stop
Interrupt

304 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Timer, Counter, and PWM

Stop on Interrupt Mode

The Stop on Interrupt mode is useful to stop the timer on The timer begins to run only after it is disabled and enabled
occurrence of a specific event for the block. In this mode, again. The count value is read using a 16-bit read in case of
the timer starts counting when the EN bit is set to ‘1’ and 32-bit controller and an 8-bit read in case of 8-bit controller.
stops counting when an Interrupt Request (IRQ) is received. During a 16-bit read, the count values are read as one value
The IRQ is any configured interrupt (Terminal Count/Cap- and the value is also captured in the Capture register. Dur-
ture, Compare/Timer Stop) of the block. When the IRQ is ing the 8-bit read, a read of the CNT0 register (LSB value)
received, the timer is automatically disabled. The timer captures the LSB and MSB in the Capture register. The user
should be enabled (EN = ‘1’) to start the timer again. can read the Capture register to obtain the time value.

Figure 27-8 shows the Gated Timer in IRQ mode.

Figure 27-8. Gated Timer in IRQ Mode

Clock

EN Bit

IRQ Pin

0xFFFF
0xFFFE
0xFFFD

0x1001
0x1000

Count Value

Final CNT.reg
0x1000
Value

Timer Stop
Interrupt

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Timer, Counter, and PWM

27.3.4.3 Pulse-width Modulator Mode During the Comparator mode alone, the terminal count out-
put pin acts as the complement to the compare output pin.
The Pulse-width Modulator (PWM) mode is also called the
To use this feature, enable the dead band mode (see Dead
Comparator mode, because the comparison output is a
Band Feature on page 308). Enable the dead band feature
PWM output with a varying duty cycle and a varying period.
by setting ‘1’ in the DB bit of CFG0. In the Comparator
The duty cycle depends on the compare type and compare
mode, the CNT register cannot be read.
value. The period depends on the Period register. For exam-
ple, consider a 16-bit PWM block with a clock of 48 MHz. Compare Types
The period value is set to 0x8000 (32768 in decimal). This
block gives a PWM period as follows: The following is a description of various compare types.

PWM Period = (Period Value * 1/Clock frequency) MODE_CFG = 000

PWM period for this example = (32768 * 1/48MHz) = 682.7 The compare output pin generates a pulse when the timer
microsecond value = the comparator value. In this case, the width of the
pulse = one clock cycle. The compare output interrupt signal
The register configuration for the Comparator mode is: occurs when the compare value = Timer Value.
■ Registers to set – TMRx_CFG0, TMRx_CFG1
MODE_CFG = 001
■ Bit MODE in TMRx_CFG0 = 1 – block acts as Compara-
tor The compare output pin generates a pulse when the timer
value is less than the comparator value. The following
■ Three Bits MODE_CFG in TMRx_CFG1 – Comparator
describes the event:
runs in various compare modes
■ The width of the pulse = one clock cycle x Comparator
The following table lists appropriate register settings. value.
Table 27-2. Register Settings for Compare Type ■ The rising edge occurs when the timer value becomes
less than the comparator value, such as when the less
MODE_CGF Comments
than condition is met.
000 Timer Value == Comparator Value
■ The falling edge of the pulse occurs when the terminal
001 Timer Value < Comparator Value count is reached, such as when the condition changes to
010 Timer Value <=Comparator Value false.
011 Timer Value > Comparator Value ■ When the comparator is disabled (EN = ‘0’) before the
100 Timer Value >= Comparator Value terminal count, the output remains high.
■ The Compare output interrupt signal occurs when the
The Comparator mode compares the timer value and the timer value is less than the Compare value.
Compare register value, using either “==”, “<”, “<=”, “>” or
MODE_CFG = 010
“>=” depending on the mode configuration in the CFG1 reg-
ister. The compare output pin generates a pulse when the timer
value is less than or equal to the comparator value. The fol-
The following describes the compare process:
lowing describes the event:
1. The timer value begins to count when EN = ‘1’.
■ The width of the pulse = one clock cycle x (Comparator
2. When the compare is true, the compare output signal is value + 1).
asserted or the compare interrupt signal is asserted. The
■ The rising edge occurs when the timer value becomes
block continues to count.
equal to the comparator value, such as when the less
3. The CNT register is reloaded with the period value when
than or equal to condition is met.
the terminal count is reached and begins to count com-
pare again. ■ The falling edge of the pulse occurs when the terminal
4. The output of the compare is either the compare output count is reached, such as when the condition changes to
signal or interrupt at the compare. false.
5. The interrupt occurs when the compare interrupt enable ■ When the comparator is disabled (EN = ‘0’) before the
bit is unmasked in the Status register. terminal count, the output remains high.
6. The compare output signal is routed to the GPIO pin ■ The Compare output interrupt signal occurs when the
using the DSI. timer value = Compare value.

306 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Timer, Counter, and PWM

MODE_CFG = 011 MODE_CFG = 100

The compare output pin generates a pulse when the timer The compare output pin generates a pulse when the timer
value is greater than the comparator value. The following value is greater than or equal to the comparator value. The
describes the event: following describes the event:
■ The width of the pulse = one clock cycle x (Period – ■ The width of the pulse = one clock cycle x (Period –
Comparator value). Comparator value + 1).
■ The rising edge occurs when the Count register is ■ The rising edge occurs when the Count register is
reloaded with the period value, such as when the greater reloaded with the period value, such as when the greater
than condition is met. than or equal to condition is met.
■ The falling edge of the pulse occurs at the end of count ■ The falling edge of the pulse occurs at the end of count
value = (Comparator value + 1), such as when the condi- value = Comparator value, such as when the condition
tion changes to false. changes to false.
■ When the comparator is disabled (EN = ‘0’) before the ■ When the comparator is disabled (EN = ‘0’) before the
condition changes to false, the output remains high. condition changes to false, the output remains high.
■ The Compare output interrupt signal occurs after the ■ The Compare output interrupt signal occurs after the
reload of the period value. reload of the period value.

Figure 27-9 shows the compare output for various Compare

types. The Period register is loaded with 0xFFFF, and the
Compare register is loaded with 0x1000.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 307

Timer, Counter, and PWM

Figure 27-9. Compare Output for Various Compare Types

Clock

EN Bit

Enable

Compare 0x0100
Register

0xFFFF 0xFFFF
0xFFFE 0xFFFE
0xFFFD 0xFFFD

0x0100 0x0100
0x00FF 0x00FF

Count Value
0x1 0x1

0x0 0x0
Compare Timer =
Output Pin Compare

Timer <
Compare

Timer <=
Compare

Timer >
Compare

Timer >=
Compare

On the Fly Duty Cycle Update Dead Band Feature

Support for multiple comparisons depends on the bit The dead band feature is used only in Comparator mode. To
CMP_BUFF in Configuration register CFG0. The following enable the dead band feature, set the DB bit in Configura-
describes the process: tion register TMRx_CFG0 to ‘1’. In the dead band mode, the
■ When the CMP_BUFF is set to ‘1’; the updated compar- terminal count output pin complements the comparator out-
ator value takes effect only after completion of the cur- put pin.
rently running period. After the terminal count, the new During the dead band period, both compare output and
compare value is taken for further comparison. When complement compare output are low for a period, deter-
this mode is used, the PWM block detects only one com- mined by the DEADBAND_PERIOD bits in the TMRx_CFG0
pare during a period. register. The dead band feature allows generation of two
■ When the CMP_BUFF is set to ‘0’; the updated compar- PWM pulses with non-overlapping outputs. The dead band
ator value takes effect immediately even before the com- feature uses a counter. The following describes the process:
pletion of the current running period. This may result in ■ When the comparator asserts the comparator output, it
another toggling of the pin even before the completion of negates the asserted output for the dead band period.
current period, thus supporting multiple comparisons.
■ The dead band period is loaded and counted for the
period configured in the DEADBAND_PERIOD bits.
■ When the dead band period has completed, the signal is
asserted, and the complement is negated.

308 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Timer, Counter, and PWM

■ A dead band period of zero has no effect. The following table shows end criteria (where the block
■ When the rate of change in the compare output is less would stop) for each mode. When an end criterion is met,
than the dead band period, the immediate change is the block stops running and the EN bit is cleared. If the user
ignored. Transitions in the compare and complement wants to run the block again, then the block must be
compare output occur only for the next change in the enabled (EN = ‘1’):
compare output.
Table 27-3. Block Stops
■ When the rate of change in the compare output is more
than the dead band period, the transitions occur at both Modes Sub-Types Criteria

compare output changes. Free Run Mode Terminal Count

Timer
Capture Mode Terminal Count
Kill Feature Pulse Width Mode Negative Edge
The Kill signal is mainly used to deactivate the PWM signal Counter Period Mode Second Positive Edge
in case of fault. Used only in Comparator mode, this signal IRQ Mode IRQ
places the output signals of the block in an unasserted state. MODE_CFG = 000 Terminal Count
MODE_CFG = 001 Terminal Count
The following describes the process:
PWM MODE_CFG = 010 Terminal Count
■ When the Kill signal is asserted, the compare output and
MODE_CFG = 011 Terminal Count
the complement of the compare output (if it exists) go to
MODE_CFG = 100 Terminal Count
its unasserted state. The terminal count output acts as
the complement of the compare output when the dead
band feature is enabled. 27.3.5 Interrupt Enabling
■ When the Kill signal is reasserted, the output signal is The block supports four types of interrupt:
restored to its default state. Kill signal duration should be
■ Terminal Count
at least one full clock cycle for proper stopping and res-
■ Capture/Compare
toration of the output signal. There is a latency of two
clock cycles before the output signal is restored. ■ Timer Enable
■ When the Kill signal is asserted, any change in the com- ■ Timer Stop
pare output is ignored, and the deassertion of the Kill
These interrupts are enabled by setting the corresponding
signal results only in the previous default state.
bits in the Status register; occurrences are stored in the Sta-
tus registers. Because these Status register bits are sticky,
27.3.4.4 One Shot Mode the interrupt request bits must be cleared explicitly by the
The One Shot mode works in combination with all of the software on occurrence of the interrupt. See Figure 27-1 on
modes specified above. The only difference is that the auto- page 296. The process is described as follows:
matic reload of the Count register with the period does not ■ Interrupt signals are sent to the Interrupt controller block,
occur. The block stops working when the required criteria where execution is decided and processed.
are reached; there is no further reload and running of the
■ The blocks are configured to support any combination of
block.
the four interrupts; only one interrupt is supported at a
The register configuration for the One Shot mode is: time.
■ Bit ONESHOT in Configuration register TMRx_CFG0 = ■ When another interrupt signal comes during the execu-
1 – enabled One Shot mode tion of one interrupt, the new interrupt request is held
pending until the previous interrupt execution is com-
pleted.
■ After the completion of the previous interrupt the new
interrupt begins the execution.

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Timer, Counter, and PWM

Interrupt signals can be of two types: 27.3.6 Sleep Mode Behavior

■ Raw Interrupt – Sent whenever the interrupt occurs.
The block supports the following two power saving features:
These interrupt signals do not wait for the execution of
■ When the timer blocks are not accessed by the PHUB,
the previous interrupt request; they are continuously
sent whenever the interrupt occurs. This type of interrupt the clock to the AHB interface is gated off, preventing all
signal is called "pulse input" because for every interrupt registers in the block from accessing the clock.
occurrence, a pulse is sent on the interrupt signal and ■ When the EN bit for a block is not asserted, the clock for
does not wait for acknowledgement from the CPU. that particular block is gated off.
■ Status Interrupt – Sent depending on the status bits in The block retains the values of the Period, Configuration,
the Status register. When the status bit is set to ‘1’, the and Compare registers during the sleep and hibernate
interrupt signal is sent. The next interrupt signal is sent states. The Count register value is not retained during the
only after the status bit is cleared. The clearing of the sleep and hibernate states.
status bit is handled by the software inside the interrupt
service routine. The interrupt signal is not sent for every
interrupt occurrence, but for every new setting of the sta- 27.4 Register Listing
tus bit in the Status register. These types of interrupt
The following table lists the registers.
allow the user control over the execution of the interrupt.
This type of interrupt signal is called "level input" Table 27-4. Registers
because the signal is asserted and remains asserted
Register Names Comments Features
until the bit is cleared by the software. The selection of
Configures Enable of block,
the interrupt signal type is decided using the bit Configuration Reg- One Shot mode, mode of block,
TMRx_CFG0
IRQ_SEL, available in the configuration register ister Enable pin inversion and dead
band features
TMRx_CFG1.
Configures Clock, mode config-
Configuration Reg-
TMRx_CFG1 uration for each mode and type
ister
of interrupt
TMRx_PER0,
Period Register Retains the reload value
TMRx_PER1
In the Comparator mode, the
Count register cannot be read.
TMRx_CNT_CMP0, Count/Comparator
So the Compare and Count
TMRx_CNT_CMP1 Registers
register share the same
address space.
TMRx_CAP0,
Capture Register
TMRx_CAP1
Hold the status of interrupts and
TMRx_SR0 Status Register
controls the interrupt masking
Controls synchronization of the
TMRx_RT0, External Routing
signals and routing of the sig-
TMRx_RT1 Registers
nals to the DSI

310 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 28. I2C

PSoC® 3 and PSoC® 5 devices include a fixed block I2C peripheral designed to interface the PSoC device with an I2C com-
munications bus. Additional I2C interfaces can be created using Universal Digital Blocks (UDBs) and PSoC Creator™. This
chapter describes the fixed block I2C interface. For details on the UDB-based interface, see the component datasheet in
PSoC Creator. Users not familiar with the I2C interface and the basics of an I2C transaction should refer to 28.3 Background
Information.

28.1 Features
The I2C communication block is a serial to parallel processor, designed to connect the PSoC device to a two wire I2C serial
communications bus. To eliminate the need for excessive CPU intervention and overhead, this block gives I2C specific sup-
port for status detection and framing bit generation.

This block operates as a slave, a master, both, or a multimaster. When active in slave mode, the unit listens for a start condi-
tion, or sends or receives data. The master modes works in conjunction with slave mode. The master has the ability to gener-
ate a START and STOP condition and determine whether or not other masters are on the bus. For multimaster mode lock
synchronization is supported.

Basic I2C features include:

■ Slave/master/multimaster, transmitter and receiver operation
■ Byte processing for low CPU overhead
■ Provides support for bus status detection and generation of framing bits
■ Generates interrupts for a variety of bus events
■ Interrupt or polling CPU interface
■ Supports bus stalling
■ Support for clock rates of up to 1MHz(Fast-mode plus)
■ 7 or 10-bit addressing (10-bit addressing requires firmware support)
■ SMBus operation (through firmware support - NO SMBus timeout protocol HW support)
■ Routes SDA and SCL connection directly to one of two pairs of assigned pins on the SIO port, or through the DSI to any
pair of GPIO or SIO pins
■ Provides HW address compare, and wake from sleep on address match
■ Provides 50 ns glitch filtering

28.2 Block Diagram

Figure 28-1 is a block diagram of the PSoC I2C interface.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 311

I2C

Figure 28-1. Block Diagram of the PSoC I2C Interface

I2C Registers

Master Mode
PHUB Interface Slave Mode Logic
Logic

IRQ

Serial
Interface

312 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 I2C

28.3 Background Information ■ Multiple masters are supported, using collision detection
and arbitration if two or more masters simultaneously ini-
The following information is provided to familiarize the user tiate data transfer.
with the I2C bus and the way it transfers data.
For more information, see the I2C-Bus Specification, and
User Manual, Version 03 at http://www.nxp.com/
28.3.1 I2C Bus Description acrobat_download/usermanuals/UM10204_3.pdf.
The Inter IC, or I2C, bus was developed by Philips Semicon-
ductors (now NXP) to provide a simple means to allow multi- 28.3.2 Typical I2C Data Transfer
ple ICs to communicate directly with each other over a
In a typical I2C transaction, the following sequence takes
common bus. Features of the I2C bus include:
place:
■ Only two bus lines are required: (1) serial data (SDA)
1. A master device controls the SCL line and generates a
and (2) serial clock (SCL).
Start condition followed by a data byte. The data byte
■ Serial, 8-bit, bi-directional data transfers can be made at contains a 7-bit slave address and a Read / Write (RW)
up to 100 kbps in the standard mode, up to 400 kbps in bit. The bit sets the direction of the data transfer, relative
the fast mode and up to 1 Mbps in the fast mode plus. to the master. It is high for read and low for write.
See Figure 28-2 for bus states. 2. The slave device recognizes its address and acknowl-
■ Devices are connected to the bus using open collector or edges (ACK) the byte by pulling the data line low during
open-drain output stages, with pull up resistors, for wired the ninth bit time.
AND functions. If the slave does not respond to the first data byte with
■ Each slave device connected to the bus is software an ACK, a Stop condition is generated by the master to
addressable by a unique address. terminate the transfer. A Repeated Start condition may
also be generated for a retry attempt.
■ Simple master/slave relationships exist; masters and
slaves can operate as either transmitters or receivers. 3. The master transmits or receives an indeterminate num-
ber of bytes, depending on the RW direction.
4. When the transfer is complete, the master generates a
Stop condition.

Figure 28-2. I2C Transfer of a Single Data Byte, With Clock Stretching by a Non-PSoC Slave

P
SDA
MSB Acknowledgement Acknowledgement SR
signal from Slave signal from Receiver
Byte complete, Clock line held low while
interrupt within Slave interrupts are serviced.
SCL S or 1 2 7 8 9 1 2 3-8 9 SR
SR or P
ACK ACK

START or STOP or
Repeated Repeated
START START
condition condition

28.4 How It Works ■ Master – The interface generates the Start and Stop
conditions and initiates data transfers by transmitting a
The PSoC 3 and PSoC 5 I2C interface provides support for slave address.
bus status detection and generation of framing bits. It can ■ Multi-Master – The interface provides clock synchroniza-
operate at up to fast mode plus speeds, in these modes: tion and arbitration to allow multiple masters on the
■ Slave – The interface listens for Start and Stop condi- same bus. Slave mode can be enabled at the same time
tions to begin and end data transfers. as master mode.

For details about the operation of these three modes, see

28.4.6 Operating the I2C Interface on page 315 and sec-

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I2C

tions 28.7 Slave Mode Transfer Examples on page 319, 28.4.2 System Management Bus
28.8 Master Mode Transfer Examples on page 322, and
28.9 Multi-Master Mode Transfer Examples on page 324. The System Management Bus (SMBus) is a bus definition
based on the I2C bus. It is similar to, and generally a subset
The I2C interface supports either 7-bit or 10-bit addressing. of, the I2C bus. For more information, see the SMBus Spec-
The hardware supports 7-bit address compare. In slave ification, Version 1.1. The I2C interface generally supports
mode, 7-bit address detection is done by using either a SMBus, although additional firmware support may be
hardware address compare or by the CPU in firmware. A required.
10-bit address detection must be done by the CPU in firm-
ware. In master mode, 10-bit address generation must be 28.4.3 Pin Connections
done by the CPU in firmware.
The I2C block controls the data (SDA) and the clock (SCL)
28.4.1 Bus Stalling (Clock Stretching) to the external I2C interface, through direction connections
to the GPIO/SIO pins. When I2C is enabled, these GPIO/
After a byte is transferred on the I2C bus, a slave device SIO pins are not available for general purpose use.The SDA
may need time to store the received byte or to prepare and SCL connections of the I2C interface can be directly
another byte to be transmitted. In that case, the slave can routed to one of two pairs of assigned pins on the SIO port.
hold the SCL line low before or after acknowledgment of a The connections can also be routed through the DSI to any
byte, which forces the master into a wait state until the slave other pair of GPIO or SIO pins. In all cases, the GPIO or SIO
is ready. This operation is known as stalling the I2C bus. pins must be configured for “Open Drain, Drives Low” mode
Some devices in master mode may not support bus stalling; (see 21.3.2.5 Open Drain, Drives High and Drives Low on
the system design should be checked before using bus stall- page 192).
ing in slave mode.
The I2C must be routed to the SIO pins in order to use the
The I2C interface can stall the bus on every received block in sleep.
address and on every completed byte transfer. After a byte
is transferred, the CPU has half of the SCL clock cycle
period to write/read the next byte before stalling begins.
28.4.4 I2C Interrupts
SCL is released when the next byte is written/read, and the The I2C interface generates interrupts for these conditions:
next byte transfer begins. ■ Byte transfer (receive or transmit) complete
■ I2C bus Stop condition detected
■ I2C bus error detected

The I2C interface cannot generate DMA requests.

28.4.5 Control by Registers

The I 2C interface is controlled by reading and writing a set of
configuration, control, and status registers listed in the fol-
lowing table. These 8-bit wide registers are used to turn the
I2C interface on or off, connect to I/O pins, set the baud rate,
provide status and control for the data transfer processes,
and monitor for exceptions.

Table 28-1. I2C Registers

Register Usage
Configuration – basic operating modes, oversample rate,
I2C_CFG
and selection of interrupts.
I2C_XCFG Configuration – configures enhanced features.
I2C_CLK_DIV1 Clock Divide – sets baud rate (along with oversample
I2C.CLK_DIV2 rate in I2C_CFG).

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 I2C

Table 28-1. I2C Registers (continued) 2. To route the SDA and SCL to the desired pin pair, set up
I2C_CFG as described in Table 28-2.
Register Usage
3. Select the baud rate (SCL clock frequency) by setting
Control / Status – used to control the flow of data bytes
I2C_CSR
and to keep track of the bus state during a transfer. the I2C_CFG register, bit 2and the I2C_CLK_DIV1 and
I2C.CLK_DIV2 registers as shown in Table 28-3. The
Master Mode Control / Status – implements I2C framing
I2C_MCSR
controls and provides bus status.
formula to determine the baud rate is:
Slave Address – for slave address recognition in hard- Baud Rate = Bus clock frequency / (Clock Division Fac-
I2C_ADR
ware, holds the 7-bit slave address. tor * Oversample Rate)
Data – provides read / write access to the data shift 4. Enable the desired mode of operation, following the
I2C_D
register.
instructions in 28.4.6.1 Slave Mode on page 316,
28.4.6.2 Master Mode on page 317, or 28.4.6.3 Multi-
28.4.6 Operating the I2C Interface Master Mode on page 318.
Operate the I2C interface in this manner:
1. Turn on the I2C interface by setting the I2C_XCFG bit 7,
csr_clk_en.

Table 28-2. Configuration of the I2C_CFG Register, Bit 7

Pin Pair Port Pinsa Register Settings

I2C0 P12[4,5] I2C_CFG[6] = 1, I2C_CFG[7] = 0

I2C1 P12[0,1] I2C_CFG[6] = 1, I2C_CFG[7] = 1
Any other GPIO / SIO
Selectable I2C_CFG[6] = 0, other DSI and GPIO registers according to pin pair selected
pin pair
a. The port pins used must be configured to “Open drain, Drives Low” mode (mode 4). The SIO pins are more suited for this purpose than the GPIO pins as
the SIO pins have higher current sink capability and over voltage tolerance.

Table 28-3. Configuration For I2C Baud Ratea

IMO Bus Clock Divide Factor

I2C Mode Oversample Rate SCL (kHz)
(MHz) I2C_CLK_DIV2[1:0] I2C.CLK_DIV1[7:0]
3 Standard 16 (0)2'b00 (2)8'b00000010 93.75
6 Standard 32 (0)2'b01 (2)8'b00000010 93.75
6 Fast 16 (0)2'b02 (1)8b'00000001 375
12 Standard 32 (0)2'b03 (4)8'b00000100 93.75
12 Fast 16 (0)2'b04 (2)8'b00000010 375
24 Standard 32 (0)2'b05 (8)8b'00001000 93.75
24 Fast 16 (0)2'b06 (4)8'b00000100 375
48 Standard 32 (0)2'b07 (16)8b'00010000 93.75
48 Fast 16 (0)2'b08 (8)8b'00001000 375
48 Fast plus 16 (0)2'b09 (3)8b'00000011 1000
67 Standard 32 (0)2'b10 (21)8b'00010101 99.7
67 Fast 16 (0)2'b11 (11)8b'00001011 381
67 Fast plus 16 (0)2'b12 (4)8'b00000100 1046
80 Standard 32 (0)2'b13 (25)8b'00011001 100
80 Fast 16 (0)2'b14 (13)8b'00001101 385
80 Fast plus 16 (0)2'b15 (5)8b'00000101 1000
a. Other values of bus clock, oversample rate and clock divider cause the baud rate to be scaled accordingly.

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I2C

28.4.6.1 Slave Mode

To enable slave mode operation, set I2C_CFG bit 0, Enable Slave. See Figure 28-3.

Figure 28-3. Slave Mode Operation

Master transmits
another byte

CPU writes CPU issues ACK/ ACK = Slave OK to

(ACK) to An interrupt is SCL line is NACK command receive more.
Successful Slave Transmitter/Reciever generated on byte
I2C_SCR held low. with a write to the Master may send
register. complete. I2C_CSR register. more or issue stop.

8-Bit Data STOP

ACK
ACK/
NACK

A byte interrupt is SCL line is Write (RX) NACK = Slave

generated. held low. 1 7 8 9 says no more

START 7-Bit Address R/W

CPU reads the
received byte from the CPU reads the
I2C_D register and received byte from
checks for “Own the I2C_D register.
1 7 8 Address” and R/W.
Read (TX)

CPU writes the CPU writes

byte to transmit (ACK | TRANSMIT) to An interrupt is generated
to the I2C_D I2C_CSR register. SCL line is
on a complete byte +
register. held low.
ACK/NACK.

8-Bit Data STOP

ACK NACK = Master
ACK/ says end-of-data
NACK

9 1 7 8 9

ACK = Master
wants to read
another byte.

CPU writes a new byte to the

I2C_D register and then writes a
TRANSMIT command to
I2C_CSR to release the bus.

In slave mode, the I2C interface continually monitors the bus NACK or a Stop condition is a signal that the master
for a Start condition. When a Start condition is detected, the doesn’t want any more bytes – the CPU should let the
following ensues. I2C interface go to an idle state.
1. The first byte, which is the Address / RW byte, starts to 5. When receiving bytes, the slave ACKs / NACKs each
be shifted in. When all eight bits have been received, a byte received from the master.
Byte Complete status is generated. ACK is a signal that the slave can accept another byte.
2. On the following low of the clock, the bus is stalled by NACK is a signal that no more bytes can be accepted –
holding SCL low, until the address byte is read and com-
after generating a NACK the CPU should then let the I2C
pared. An ACK or NACK is then issued, based on that
interface go to an idle state.
comparison.
3. If there is an address match, the RW bit determines the 6. Data transfer is complete when the master generates a
direction of the data transfer, as shown in the two Stop condition.
branches of Figure 28-3. After each byte is received, or 7. At anytime when a Stop condition or Bus Error is
when a new byte can be transmitted, a Byte Complete detected, the I2C interface is automatically reset to an
status is generated, and SCL is held low to stall the bus idle state.
until the CPU handles the interrupt and transfers the
next byte.
4. When transmitting bytes, the slave receives an ACK /
NACK from the master for each byte sent.
ACK is a signal that the master wants another byte.

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Slave Address Recognition When hardware address recognition is enabled, the address
portion of the first byte received after a bus Start condition is
The slave address recognition feature can be enabled in
compared to the value in I2C_ADR.
hardware to reduce CPU usage. To enable hardware
■ If no match is detected, the byte is automatically NAKed.
address recognition:
■ If a match is detected, the byte is automatically ACKed,
1. Set the 7-bit slave address in I2C_ADR, bits 0 to 6.
a byte complete interrupt is generated, and the remain-
2. Set I2C_XCFG, bit 0, HW Addr En. der of the transfer is performed as described above.

28.4.6.2 Master Mode

To enable master mode operation, set the I2C_CFG bit 1, Enable Master. See Figure 28-4.

Figure 28-4. Master Mode Operations

Successful Master Transmitter/

Receiver An interrupt is The SCL line CPU issues ACK/
generated on byte is held low. NACK command to ACK =Master
complete. the I2C_CSR wants more
register.

CPU issues a 8-Bit Data STOP

CPU issues command to the ACK/
Generate I2C_CSR register to NACK
START release SCL
A Start/Address compete
command to The SCL line
interrupt is generated. 1 7 8 9
I2C_MCR. is held low. NACK = Master
indicates end-of-
Read (RX)

data
CPU reads the
START 7-Bit Address R/W received byte from
I2C_D register.
ACK
CPU checks Read/
Write Bit
1 7 8 9
Write (TX)

CPU writes address

byte to the I2C_D CPU issues TRANSMIT An interrupt is generated
register. The SCL line CPU issues STOP
command to the on completion of the byte is held low. command
I2C_CSR register. + ACK/NACK.

CPU writes a byte to

transmit I2C_D NACK =
8-Bit Data Slave says no STOP
register.
ACK/ more.
NACK

1 7 8 9

ACK = Slave
says OK to
receive more.
Master can
send more or
Stop
Master wants to
send more bytes.

If Enable Slave is not set, the I2C interface is in Master Only 2. When transmitting bytes, the master receives an ACK/
mode and ignores all externally generated Start conditions. NACK from the slave for each byte sent.
ACK is a signal that the slave can accept another byte.
Operation in master mode is as follows:
NACK is a signal that no more bytes can be accepted.
1. To start a transfer, the CPU writes the slave address/
direction byte to I2C_D and sets I2C_MCSR bit 0, Start
Gen (or bit 1, Restart Gen).
In a single-master environment the Start condition is
successfully generated, the byte is transmitted, and a
Byte Complete is generated. If the byte is ACKed by the
slave, data bytes can be sent or received as shown in
the two branches of Figure 28-4.

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I2C

3. When receiving bytes, the master ACKs/NACKs each Lost Arb bit is set. The hardware waits for a com-
byte received from the slave. mand from the CPU, stalling the bus if necessary.
ACK is a signal that the master wants another byte. The master clears I2C_CSR to release the bus and
allow the transfer to continue, and the I2C interface
NACK is a signal that the master is done accepting
goes back to idle mode. The firmware can then retry
bytes.
the transfer when the bus becomes free again.
4. When data transfer is complete, the CPU issues a Stop
command. The I2C interface generates a Stop condition
and goes to an idle state. 28.5 Hardware Address Compare
Instead of a Stop condition, the CPU can issue a Restart The hardware has the ability to compare the seven address
command, and another transfer is immediately started. bits received on the SDA line with that configured in the
I2C.ADR register. On a true compare, the address is auto-
28.4.6.3 Multi-Master Mode matically ACKed, the SCL line held low, and a byte complete
Multi-master mode becomes enabled when Master mode is interrupt is issued. On reception of the byte complete inter-
enabled by setting the I2C_CFG bit 1, Enable Master. rupt from the hardware, the firmware needs to read bit [0] of
the data register to determine Read/Write direction for the
In Multi-master mode, the CPU starts the transfer in the transfer. The firmware must then set the transmit bit in the
same manner as in a single-master environment. However, I2C.CSR register to release the SCL. On an mismatch the
before generating a Start condition, the master must monitor address is automatically NAKed and the hardware revert to
the Bus Free bit in I2C_MCSR, and wait until the I2C bus is an idle state waiting for the new Start detection.
free.

After a Start condition is generated other outcomes may 28.6 Wake from Sleep
result, causing the CPU to delay or abort the transfer:
■ Another master in a multimaster environment has gener- When the HW address compare is enabled and the device
ated a valid Start, and the bus is now busy. The Start is put to sleep, the slave can be used to wake the device on
condition is not generated. The resulting behavior an I2C HW address match (only when either of the SIO pairs
depends upon whether Slave mode is enabled. are used as I2C pins). While in sleep, the master clock is
disabled. The incoming SCL clock is used to latch the
❐ Slave mode is enabled – A Byte Complete interrupt
address into the block. Once the address matches, the
is generated. When reading I2C_MCSR, the master
sees that the Start Gen bit is still set and that wakeup interrupt is asserted to wake the system up, and the
I2C_CSR has the Address bit set, indicating that the SCL is pulled low until the master clock is operational. After
block has been addressed as a slave. The firmware the system wakes, the I2C block is switched back to normal
may then ACK the address to continue the transfer operation, and all other transaction proceed.
as a slave, or NACK the address.
The I2C Block only responds to transactions during sleep if
❐ Slave mode is not enabled – The Start Gen bit and only if:
remains set, and the transfer is delayed until the bus
becomes free. A Byte Complete is generated when ■ The I2C block is enabled in slave mode and slave mode
the Start condition has been generated and the only
address byte has been transmitted. ■ Hardware address compare is enabled
■ The Start condition is generated, but the master loses ■ There is an address value written in the I2C.ADR
arbitration to another master. The resulting behavior
■ The I2C_ON bit in I2C.XCFG is set to 1'b1
depends upon whether Slave mode is enabled.
❐ Slave mode is enabled – A byte complete interrupt is Follow this procedure before putting the part to sleep, to
generated. When reading I2C_MCSR, the master ensure proper sleep mode I2C operation.
sees that the Start Gen bit is clear, indicating that the 1. The CPU must set the Force NACK bit of the I2C.XCFG
Start condition was generated. However, the Lost register when it wants to put the part into sleep.
Arb bit is set in I2C_CSR. The Address status is also
2. The FW must poll the Ready_To_Sleep bit in the
set, indicating that the block has been addressed as
I2C.XCFG bit. One the bit is high, FW can put the part to
a slave. The firmware may then ACK the address to
sleep.
continue the transfer as a slave, or NACK the
address.
❐ Slave mode is not enabled – A Byte Complete inter-
rupt is generated. The Start Gen bit is clear and the

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28.7 Slave Mode Transfer Examples

Slave mode receives or transmits data, as described in this section.

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28.7.1 Slave Receive

A slave receive operation is accomplished as shown in Figure 28-5.

Figure 28-5. Slave Receive Operation Sequence

Start

Write ‘1’ to I2C_XCFG[7], csr_clk_en, NO Byte Complete, I2C_CSR[0] == 1, ERROR

E
to start up the I2C interface hardware. or Error, (I2C_CSR & 0xA0) != 0?

YES
Write ‘0’ to I2C.CSR to clear all bits.

NO
I2C_CSR[3] == 1, E
Address?
Set I2C_CFG[3:2], Clock Rate,
and I2C_CLK_DIV
to set the SCL frequency. YES

Write ‘0’ to I2C_CSR[3] to reset address.

Set I2C_CFG[7:6], SIO Select and PSelect,

to connect SDA and SCL to the
appropriate pins.

Write ‘0’ to I2C_CSR[4 NO

I2C_D[7:1] == MyAddr?
to NACK

Set I2C_CFG[0], Enable Slave,

to start Slave mode. YES

Write ‘1’ to I2C_CSR[4] to ACK.

YES I2C_D[0] = 0, NO
Go do slave transmit functions.
I2C Write?

Write ‘0’ to I2C_CSR[2]

to set Receive mode

Write ‘0’ to I2C_CSR[4] to NACK

ERROR
Byte Complete, I2C_CSR[0] == 1, NO
E or Error, I2C_CSR[7] != 0, or
Stop, I2C_CSR[5] != 0?

STOP
NO ERROR
YES Stop Status, I2C_CSR[5] == 1, E
or Error, I2C_CSR[7] != 0?
Copy I2C_D to receive data buffer.

YES

NO Write ‘1’ to I2C_CSR[4]

Done?
to ACK
E Report a successful transfer.
YES

Report and handle error. End

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 I2C

28.7.2 Slave Transmit

A slave transmit operation is accomplished is accomplished as shown in Figure 28-6.

Figure 28-6. Slave Transmit Operation Sequence

Flow Chart for Slave Transmit

Start

Write ‘1’ to I2C_XCFG[7], Clk Gate En, NO Byte Complete, I2C_CSR[0] == 1, ERROR
E
to start up the I2C interface hardware. or Error, (I2C_CSR & 0xA0) != 0?

YES
Write ‘0’ to I2C_CSR to clear all bits

NO
I2C_CSR[3] == 1, E
Address?
Set I2C_CFG[3:2], Clock Rate,
and I2C_CLK_DIV
to set the SCL frequency. YES

Write ‘0’ to I2C_CSR[3] to reset address.

Set I2C_CFG[7:6], SIO Select and PSelect,

to connect SDA and SCL to the
appropriate pins.

Write ‘0’ to I2C_CSR[4] NO

I2C_D[7:1] == MyAddr?
to NACK.

Set I2C_CFG[0], Enable Slave,

to start slave mode. YES

Write ‘1’ to I2C_CSR[4] to ACK.

NO I2C_D[0] = 0, YES
Go do slave receive functions.
I2C Write?

Copy first/next byte from transmit data buffer to I2C_D.

Write ‘1’ to I2C_CSR[2] to start transmitting byte.

NO ERROR
Stop Status, I2C_CSR[5] == 1, E
ERROR
NO or Error, I2C_CSR[7] != 0?
Byte Complete, I2C_CSR[0] == 1,
E
or Error, (I2C_CSR & 0xA8) != 0?

YES

YES
Report a successful transfer.

ACK
Byte ACK’ed or NACK’ed?
I2C_CSR[1]
End
E
NACK

Report and handle error.

Note that, instead of waiting for Byte Complete or Error, an interrupt can be generated for each of these conditions, as well as
for the I2C Stop condition. The interrupt handler can then do some or all of the functions shown.

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I2C

28.8 Master Mode Transfer Examples

Master mode receives or transmits data, as described in this section.

28.8.1 Single Master Receive

A master receive operation in a single-master system is accomplished as shown in Figure 28-7.

Figure 28-7. Single Master Mode Receive Operation

Flow Chart for Single Master Receive

Write ‘1’ to I2C_MCSR[0], Start Gen,
Start to start the transfer.

Write ‘1’ to I2C_XCFG[7], Clk Gate En,

to start up the I2C interface hardware.

NO Byte Complete, I2C_CSR[0] == 1, ERROR

E
or Error, (I2C_CSR & 0xA0) != 0 or
Write ‘0’ to I2C_CSR to clear all bits. I2C_MCSR[2] != 1?

YES
Set I2C_CFG[3:2], Clock Rate,
and I2C_CLK_DIV
NACK
to set the SCL frequency.
Byte ACK’ed or NACK’ed?
* If address byte is NACK’ed, I2C_CSR[1]
instead of retry, an error can
be reported.
ACK
Set I2C_CFG[7:6], SIO Select and PSelect,
to connect SDA and SCL to the
appropriate pins. Write ‘0’ to I2C_CSR[2] to set Receive mode.

Set I2C_CFG[1], Enable Master,

to start master mode.

Set I2C_D = Slave Addr/Read

Write ‘0’ to I2C_CSR[4] to NACK.

ERROR
Byte Complete, I2C_CSR[0] == 1, NO
E
or Error, (I2C_CSR & 0xA0) != 0 or
I2C_MCSR[2] != 1?

NO ERROR
YES Stop Status, I2C_CSR[5] == 1, E
or Error, I2C_CSR[7] != 0?
Copy I2C_D to receive data buffer.

YES

E NO Write ‘1’ to I2C_CSR[4] Report a successful transfer.

Done?
to ACK.

YES
Report and handle error. End

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 I2C

28.8.2 Single Master Transmit

Figure 28-8 illustrates the process by which you generate a master transmit operation in a single master system.

Figure 28-8. Single Master Mode Transmit Operation

Flow Chart for Single Master Transmit

Write ‘1’ to I2C_MCSR[0], Start Gen,
Start to start the transfer.

Write ‘1’ to I2C_XCFG[7], Clk Gate En,

to start up the I2C interface hardware.

NO Byte Complete, I2C_CSR[0] == 1, ERROR

E
or Error, (I2C_CSR & 0xA0) != 0 or
Write ‘0’ to I2C_CSR to clear all bits. I2C_MCSR[2] != 1?

YES
Set I2C_CFG[3:2], Clock Rate,
and I2C_CLK_DIV
NACK
to set the SCL frequency.
Byte ACK’ed or NACK’ed?
* If address byte is NACK’ed, I2C_CSR[1]
instead of retry, an error can
be reported.
ACK
Set I2C_CFG[7:6], SIO Select and PSelect,
to connect SDA and SCL to the
appropriate pins. Write ‘1’ to I2C_CSR[2] to set transmit mode.

Set I2C_CFG[1], Enable Master,

to start master mode.

Set I2C_D = Slave Addr/Write.

NO
Done?

YES

Copy first/next byte from transmit data buffer to I2C_D. Write ‘0’ to I2C_CSR[2]
Write ‘1’ to I2C_CSR[2] to start transmitting byte. to generate a Stop condition.

ERROR NO
Byte Complete, I2C_CSR[0] == 1, NO Stop Status, I2C_CSR[5] == 1, ERROR
E E
or Error, (I2C_CSR & 0xA0) != 0 or or Error, I2C_CSR[7] != 0?
I2C_MCSR[2] != 1?

YES YES

Report a successful transfer.

ACK
Byte ACK’ed or NACK’ed?
I2C_CSR[1]

NACK End
E
Write to I2C_CSR[4]. A Stop
condition is automatically
generated by the hardware,
regardless of the value written. Report and handle error.

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I2C

Defining single master operations allows the following ■ There is no need to Enable Slave (I2C_CFG[0]) when
assumptions to be made: enabling the master mode, as the interface will never be
■ There is no need to check for bus busy (I2C_MCSR[3]) forced into slave mode due to bus busy or lost arbitra-
or Lost Arb (I2C_CSR[6]). tion.

28.9 Multi-Master Mode Transfer Examples

In multi-master mode, data transfer can be achieved with the slave mode not enabled or with the slave mode enabled.

28.9.1 Multi-Master, Slave Not Enabled

A master data transfer operation in a multi-master system, where the slave mode is not enabled is accomplished as shown in
Figure 28-9.
Figure 28-9. Multi-Master Mode, Slave Not Enabled Sequence

Flow Chart for Multi-Master, Slave Not Enabled

Start

Write ‘1’ to I2C_XCFG[7], Clk Gate En,

to start up the I2C interface hardware. Bus Busy? YES
I2C_MCSR[3]

NO

Write ‘0’ to I2C_CSR to clear all bits. Write ‘1’ to I2C_MCSR[0], Start Gen,
to start the transfer.

Set I2C_CFG[3:2], Clock Rate,

and I2C_CLK_DIV
to set the SCL frequency.

Start condition? NO
I2C_MCSR[0] == 0 Bus became
busy.
Set I2C_CFG[7:6], SIO Select and PSelect,
to connect SDA and SCL to the YES
appropriate pins.

Set I2C_CFG[1], Enable Master,

to start Master mode ERROR Byte Complete, I2C_CSR[0] == 1, NO
with slave not enabled. or Error, I2C_CSR[7] != 0 or
I2C_MCSR[2] != 1?

YES
Set I2C_D = Slave Addr/Read or Write

Lost arbitration? YES

I2C_CSR[6] == 1 Lost arbitration,
restart transfer.
NO

Continue with data transfer

Report and handle error.
as in single master.

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 I2C

28.9.2 Multi-Master, Slave Enabled

A master data transfer operation in a multi-master system, where the slave mode is enabled is accomplished as shown in
Figure 28-10.

Figure 28-10. Multi-Master Mode, Slave Enabled Sequence

Flow Chart for Multi-Master, Slave Enabled

Start

Write ‘1' to I2C_XCFG[7], Clk Gate En,

to start up the I2C interface hardware. Bus Busy? YES
I2C_MCSR[3]

NO
Write ‘0’ to I2C_CSR to clear all bits.

Write ‘1’ to I2C_MCSR[0], Start Gen,

to start the transfer.

Set I2C_CFG[3:2], Clock Rate,

and I2C_CLK_DIV
to set the SCL frequency.

Set I2C_CFG[7:6], SIO Select and PSelect, ERROR NO

Byte Complete, I2C_CSR[0] == 1,
to connect SDA and SCL to the or Error, I2C_CSR[7] != 0?
appropriate pins.

YES
Set I2C_CFG[1], Enable Master,
and I2C_CFG[0], Enable Slave,
to start both modes.
Bus became busy,
YES or lost arbitration?
I2C_MCSR[0] == 1 and
I2C_CSR[3] == 1
Set I2C_D = Slave Addr/Read or Write.

NO

Report and handle error. Continue with address Continue with data transfer
recognition as a slave. as in single master.

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 29. Digital Filter Block (DFB)

Some PSoC® devices have a dedicated hardware Digital Filter Block (DFB) used to filter applications. The heart of DFB is a
multiply and accumulate unit (MAC), which can do 24 bit * 24 bit multiply and 48 bit accumulate in one system clock cycle. In
addition, there are data RAMs to store data and coefficients of digital filters.

29.1 Features
■ Two 24-bit wide streaming data channels
■ Two sets of data RAMs each that can store 128 words of 24-bit width each
■ One interrupt and two DMA request channels
■ Three Semaphore bits to interact with system software
■ Data alignment and coherency protection support options for input and output samples

29.2 Block Diagram

The Digital Filter Block (DFB) is a 24-bit fixed point, programmable limited scope DSP engine. The DFB is made up of four pri-
mary subfunctions as shown in the DFB Basic Block diagram in Figure 29-1.
■ Controller
■ Datapath
■ Address Calculation Units (ACUs)
■ Bus Interface

The Controller consists of a small amount of digital logic and memories. The memories in the controller are filled with assem-
bled code that make up the data transform function the DFB is intended to perform.

The Datapath subblock is a 24-bit fixed point, numerical processor containing a Multiply and Accumulator (MAC), a multi-
function Arithmetic Logic Unit (ALU), sample and coefficient and data RAM (data RAM is shown in Figure 29-1) as well as
data routing, shifting, holding, and rounding functions. The datapath block is the calculation unit inside the DFB.

The addressing of the two data RAMs in the datapath block are controlled by the Address Calculation Units (ACUs). There
are two (identical) ACUs, one for each RAM.

These three subfunctions make up the core of the DFB block and are wrapped with a 32-bit DMA-capable AHB-Lite Bus Inter-
face with Control/Status registers. Each of these four subfunctions are discussed in the following sections.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 327

Digital Filter Block (DFB)

Figure 29-1. Digital Filter Block Diagram

D a ta p a th

MAC S ta g e S ta g e
In p u t fr o m
ALU R e g is te r R e g is te r CPU/ DMA
S h ift A B
H o ld
Bus
Round In te r fa c e

D a ta D a ta H o ld H o ld
O u tp u t to
RAM A RAM B R e g is te r R e g is te r CPU/ DMA
A B

C o n tr o l

d fb _ in tr
C o n tr o lle r
ACU A ACU B d fb _ d m a r e q 1
d fb _ d m a r e q 2

A d d r e s s C a lc u la tio n U n it
d fb _ g lo b a li1 & 2 d fb _ g lo b a lo 1 & 2

D S I s ig n a ls

F ig u re 3 0 - 1 . D ig ita l F ilte r B lo c k D ia g r a m

29.3 How It Works

29.3.1 Controller
The controller consists of a RAM-based state machine, a
RAM-based control store, program counters, and next state
control logic (see Figure 29-2 on page 329). Its function is to
control the address calculation units and the datapath, and
to communicate with the bus interface to move data in and
out of the datapath.

328 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Digital Filter Block (DFB)

Figure 29-2. Controller Block Diagram

Fjump addr
Fjump limit
Jump addr
FSM RAM Loop

PC PC

fsm_addr[4:0]

nstate[4:0]

fstate[4:0]
A B

loop
csa_addr[5:0] csb_addr[5:0]

Control Store Control Store

RAM A RAM B

Next State
Conditions
Logic
RAM Selection

To Datapath,
eob
ACU, and
Bus Interface

The contents of FSM RAM, the two control store RAMs, the correct CS RAM output. Opcode execution then switches to
ACU RAM, and potentially the two datapath RAM (if initial and stays with the CS RAM until the next jump condition.
conditions are required) must be loaded by the system
before use. The contents of the DFB RAMs are stored in 29.3.1.1 FSM RAM
flash memory from where they are written into the RAM
FSM RAM is 64x32 RAM. It is used as ROM. The FSM RAM
before the DFB operation is enabled.
is filled with control flow information implementing the
The next state decode logic and the FSM RAM comprise the desired function of the DFB prior to use. This RAM is loaded
main DFB branch control. The next state decoder generates typically at system boot time, but is not restricted to any par-
the FSM RAM’s address and the RAM produces next state ticular time as long as the DFB is not running (run is deas-
information as well as branch flag masks. These masks serted in DFB_CR[0]). The code in this and the Control
enable the use of flags as jump conditions for conditional Store RAMs can be altered at anytime to change the func-
branching. This state machine controls the program counter tion performed by the DFB. In fact, some applications have
to produce the address for the Control Store RAMs. the algorithm loaded routinely and swapped out when sev-
eral channels of data need processing or when one channel
There are two identical Control Store (CS) RAMs and an
needs multiple transforms – when the code is too large to fit
associated Program Counter to allow an interleaving meth-
in the available space.
odology for CS opcode fetches. The CS RAMs are 64x32
each. The FSM RAM is addressed as two banks of 32x32. The
Bank selection is achieved using the CSR bit (DFB_CR[1]).
Both CS RAMs are sometimes filled with identical data. It is
The primary use of the two banks is to allow two separate
possible to effectively double the control store instruction
code stores to load and jump between without incurring the
space by using different contents in each RAM. It is during
reload penalty of the FSM RAM.
branch conditions that next state address calculations hap-
pen. Hence, the two possible branch addresses are sup-
plied – one to each RAM. When the branch condition is
determined, late in the cycle, the controller simply picks the

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 329

Digital Filter Block (DFB)

Table 29-1 shows the bit fields used for the controller by the 32-bit FSM RAM.

Table 29-1. FSM RAM Bit Field Mapping

False Jump
Name Enables Loop Jump Address False Jump Limit Next State
Address
Signal enables loop jaddr fjlim fjaddr nstate
Bits 31:24 23 22:17 16:11 10:5 4:0
Enables for the top 8
Jump address for CS Jump address for CS Next state address
Description input branching con- Signifies a code loop Address loop limit
RAMs on TRUE RAMs on FALSE* for FSM
ditions
* This false jump address is for use only in a loop state, where the controller moves back to the start of the loop on a false condition.
If the state is not a loop state, then this address is used for the next state on false value.

29.3.1.2 Program Counter

The primary purpose of the program counter (PC) is to supply correct addresses to the Control Store (CS) RAMs. This is not
as simple as providing a direct address from the FSM RAM because jump addresses must be determined and held in the PC
before branches are taken. The PC also controls the incrementing and wrapping of addresses for loops, allowing the FSM to
sit in one state during looping processes. For this reason the FSM RAM sends out the jump address and loop conditions to
the PC

29.3.1.3 Control Store

The term Control Store (CS) refers to a bank of two interleaved RAMs used to hold control opcodes for the ACUs and the Dat-
apath unit. These RAMs are addressed by the FSM RAM indirectly through the Program Counters and set the per-cycle oper-
ation state of the DP and ACUs.

The outputs of these two 32-bit wide RAMs are muxed to one control bus (based upon which is presently the active RAM
denoted by DFB_SR[0]) and provide the following bit-fields to the ACUs and Datapath unit listed in Table 29-2.

Table 29-2. Control Store RAM Bit Field Mapping

Name DP CTRL Bus WR ACU-A Opcode ACU-B Opcode ACU Addr End of Block
Signal dp_ctrl buswr acua_op acub_op acu_addr eob
Bits 31:14 13 12:9 8:5 4:1 0
Signifies a data out-
Control bus to the
Description put condition to the ACU A’s opcode ACU B’s opcode ACU RAM’s address End of Block marker
Datapath Unit
bus

29.3.1.4 Next State Decoder 2. Datapath status inputs such as sign, threshold, and
equal.
The Next State Decoder is combination logic that controls
❐ Dpsign – A jump based on the MSB of the ALU out-
the state transitions in the FSM RAM. The next state
put. If ALU output goes negative, assert.
decoder is the logic that gives the address (state address) to
❐ Dpthresh – Datapath Threshold – Asserted when the
the FSM. The result of the next state decoder is governed
ALU detects a sign change, such as a zero crossing
by the branching signal conditions. You get a state transition
detection.
when one of these two conditions exist:
❐ Dpeq – Datapath Equity – Asserted when the ALU
■ EOB is high and the signal condition goes high. This is hardware detects an output value of zero.
the jump on true branch.
3. Acueq – ACU A or B REG is equal to MREG or LREG, if
■ Loop (cfsmram[23]) is low meaning no loop, EOB is modflag is set. ACU A or B REG is equal to 127 or 0, if
high, and condition is low. This is the flow through condi- modflag is cleared. This means that the pointer to the
tion for a false condition. DP Data registers has reached its upper/lower limit.
Refer to 29.3.2 Datapath on page 331 for clarity.
The branching conditions are:
1. End of block is encountered for a control store block – a
condition for a jump because a jump instruction signifies
the end of the block.

330 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Digital Filter Block (DFB)

4. IN1 or IN2 – When new data is available in one of the 29.3.2 Datapath
staging registers A or B. Signals a new input cycle and is
available for consumption. Remains asserted until Datapath (DP) is the name used to refer to the numerical
cleared by a bus read command. calculation unit of the DFB. The datapath subblock is a 24-
5. globali1 – Branch control input from DSI port. bit fixed-point numerical processor containing a 48-bit MAC,
a multi-function ALU, sample and coefficient data RAMs as
6. globali2 – Branch control input from DSI port.
well as data routing, shifting, holding and rounding func-
7. The sat_det flag (Saturation) from ALU – This flag is set
tions.
when saturation occurs in MAC, ALU, or Shifter.
8. Any of the semaphores (refer to the PHUB and The DP architecture makes use of two 128x24 single-port
DMAC chapter on page 91). RAMs (RAM A and RAM B). The RAMs can be loaded from
the bus or from the datapath output (feedback). These
For branching, the branching conditions must be enabled.
RAMs hold data and coefficients with size and location
The ENGLOBALS, ENSATRND, ENSEM, SETSEM, and
under full DFB controller control.
CLEARSEM commands are used.
The heart of the DP unit is a 48-bit Multiply and Accumulator
If the ALU command is ENSEM, then the data on
(MAC). Two 24-bit values can be multiplied and the result
acu_addr[2:0] is written to the register sem_en for enabling
added to the 48-bit accumulator in each clock cycle. This
semaphores to be branching conditions. The acu_addr[2:0]
accumulator or any memory value can be routed to the ALU.
is converted bitwise to enable each of the three sema-
Results from the ALU can then be stored in either Data
phores.
RAM. The MAC is the only portion of the DP that is wider
The SETSEM and CLEARSEM are used to set or clear the than 24 bits. All results from the MAC are passed on to the
semaphores based on the semaphore selected in ALU as 24-bit values representing the high-order 24 bits in
acu_addr[2:0]. the accumulator shifted by one (bits 46:23). The MAC
assumes an implied binary point after the MSB which shifts
Acu_addr[2] -> semaphore2
the result down a bit in the output of the MAC. For this rea-
Acu_addr[1] -> semaphore1
son, bits 46:23 are used instead of 47:24.
Acu_addr[0] -> semaphore0
The DP unit also contains an optimized ALU that supports
The ENGLOBALS command is used to enable the use of
add, subtract, comparison, threshold, absolute value,
external dsi inputs and datapath saturation flags as branch-
squelch, saturation, and other functions.
ing conditions. ENGLOBALS shares an ALU opcode with
ENSATRND. They are differentiated by the acu_addr[3] bit With the exception of the DP RAM addresses, the DP unit is
as shown in Table 29-3. completely controlled by seven control fields totaling 18 bits
coming from the DFB Controller as the DP_CTRL control
Table 29-3. ENGLOBALS and ENSATRND Commands bus (Table 29-2 on page 330). These 18 bits of control are
Acu_addr[0]: enables globali1 listed in Table 29-4.
Englobals Acu_addr[3]=0 Acu_addr[1]: enables globali2
Acu_addr[2]: enables sat_det
Acu_addr[0]: writes to rnd_flag
Acu_addr[1]: writes to sat_flag
Ensatrnd Acu_addr[3]=1
Acu_addr[2]: creates strobe to clear satura-
tion flag

Table 29-4. Datapath Opcode Bit Field Mapping

Name B Mux Ctrl A Mux Ctrl MAC Opcode ALU Opcode Shift Opcode RAM A WR RAM B WR
Signal muxb*_ctrl muxa*_ctrl mac_op alu_op shift dpa_r_wb dpa_r_wb
Width 3 3 2 5 3 1 1
mux1b mux2b mux1a mux2a DP output shifter Write signal to Write signal to
Description MAC opcode ALU opcode
mux3b mux3a opcode RAM A RAM B

Note how the different signals from Table 29-4 affect the functioning of the different elements in the datapath.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 331

Digital Filter Block (DFB)

Figure 29-3. Datapath

mux1a mux2a
mux3a

mux2a
alu_op[4:0]
mux1a

RAM A
128 x 24

mux3a
shift_op[2:0]
mac_op[1:0]

dp_out
A

Pass Mux
AHB Round AHB
MAC Hold Shift
Bus or Pass
Bus
B

mux3b
Round Flag
mux1b

RAM B
128 x 24
mux2b

mux3b

mux1b mux2b

Round Mode – If DP is in Round mode, any result passing out of the DP unit is being rounded to a 16-bit value. This feature
status is shown in the register setting, DFB_SR [2].

Saturation Mode – If DP is in Saturation mode, any mathematical operation that produces a number outside the range of a
24-bit 2’s complement number is clamped to the maximum positive or negative number. Enabling and disabling saturation
and rounding is under the control of DFB controller. See the ALU instruction set. The status is visible at DFB_SR [1].

29.3.2.1 MAC instead of 47:24. The instruction set for the MAC, ALU and
Shifter is listed in Table 29-7 on page 339, Table 29-6 on
The multiply add function takes two 24-bit signed numbers
page 339, and Table 29-8 on page 340.
and calculates a 48-bit signed result, then adds a signed 48-
bit value ((a*b)+c). 29.3.2.2 ALU
The accumulator consists of a 48-bit register and the multi- The ALU provides data control on the output end of the data
ply adder. path. ALU supports add, subtract comparison, threshold,
Together these two functions, along with some control logic, absolute value, squelch, saturation, and other functions.
make up the MAC. Based on the opcode (mac_op) coming See Table 29-6 for various instructions supported by ALU.
from the DFB controller it can do one of the following opera- The ALU commands as well as inputs are pipelined. This
tion: pipelining can be made use for data movement in some fil-
■ Multiply and accumulate with previous Values tering applications. This pipelining causes a delay of two
■ Clear Accumulator and load with current product. clock cycles for the ALU input to reach the output.
■ Hold accumulator, no multiply (no power in mult)
29.3.2.3 Shifter and Rounder
■ Add ALU value to product and start new accumulation
The shifter at the ALU output can be used to shift the ALU
The output of MAC is higher order 24 bits of multiply accu- results as required. See Table 29-8 for various shifter com-
mulate operation. The MAC assumes an implied binary mands. Rounder rounds the results to a 16 bit value when
point after the MSB, which shifts the result down a bit in the the data path is operating in round mode.
output of the MAC. For this reason, bits 46:23 are used

332 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Digital Filter Block (DFB)

29.3.3 Address Calculation Unit dence requires the same value on the ACU_addr for all
commands involved.
The Address Calculation Units (ACUs) generate addresses
for each DP RAM. There are two address calculation unit for
supporting sophisticated branching operations.
29.3.4 Bus Interface and Register
Descriptions
The ACU is capable of saving and restoring address, incre-
menting or decrementing address by 1 or n (n is a constant The DFB block is wrapped with a 32-bit AHB-Lite Slave bus
value stored in FREG), flagging a programmable terminal interface. A 32-bit bus was chosen to accommodate the fact
count, and a number of other functions. that the RAMs in the DFB are all 24 bits and most of the bus
transfers to the DFB are 24 bits.
REG – Stores the current value that the ACU is operating on
and outputs it on every cycle, unless a command specifies The DFB has a set of expanded Control and Status Regis-
otherwise. ters (CSR) that are accessible through the system bus at all
times. The registers containing CSR bit information are
FREG – Loads with a value to increment or decrement by, address mapped as 32-bit registers with active bits only in
when using the ADDF and SUBF commands. For example, the low byte. This arrangement works well for both 8-bit and
load two into FREG and then it is possible to increment 32-bit MCUs.
through the data RAMs by two.
The CSRs that hold sample data are 24-bits wide (Staging
MREG – Stores the maximum value before a wraparound if and Hold register) and coherency interlocking HW is
modulo arithmetic is turned on. When the address calcu- included to allow 8-bit and 16-bit accesses.
lated by the ACU exceeds MREG value, it will wraparound
to LREG value, if modulo arithmetic is turned on. In normal mode of operation, the DFB RAMs (except the
input staging and output holding registers) is controlled by
LREG – Stores the minimum value before a wraparound to the DFB controller and is not accessible to CPU/DMA. If
the MREG value when modulus arithmetic is turned on. CPU/DMA needs control of this DFB RAM memory it should
Modulus arithmetic is enabled using the SETMODE ACU make use of DFB_RAM_DIR control bits (one per RAM) to
command and disabled using the UNSETMOD command. give the RAM control to system bus.
Modulus arithmetic prevents the ACU from incrementing
past the value of MREG and from decrementing below the
29.3.4.1 Streaming Mode
value of LREG. Make sure the REG value is within the In streaming mode the filter coefficients and historic data are
LREG:MREG range at the time modulus arithmetic is turned loaded into DFB before starting the DFB operations. Run-
on to avoid unexpected results. time data movement is through the staging and holding reg-
isters.
The ACU (including the ACU RAM) is initialized whenever a
hard reset event occurs or when the RUN bit in the The DFB has:
DEC_CR register is ‘0’. Initialization is as follows: ■ Two 24-bit input staging registers
ACU RAM Contents=0, MREG=127, LREG=0, FREG=2. ■ Two 24-bit output holding registers
The current address and state of the register of both ACUs These registers can be accessed by both DFB as well as
can be stored or retrieved from memory with assembly AHB Bus (CPU/DMA). In reality, these registers are double
instructions. This is used in context switching. A 16x14 ACU buffered, but to the DFB controller and the system bus, they
RAM is used for this purpose. The 16x14 RAM is used by appear as single registers. In streaming mode data to be fil-
both ACUs. The upper seven bits are for ACU B and the tered is streamed in to staging registers. Filter output is
lower seven bits are for ACU A. Thus, each ACU can store streamed out through DFB holding registers.
16 addresses or state elements.
The two sets of input and output registers aid stereo data
The ACU instructions perform incrementing/decrementing of processing applications. Applications requiring more than
the data RAM addresses by one or the value in FREG. two concurrent channels must use block mode.
Apart from this, the modulus arithmetic is used to enable a
wrap around at user defined limits.

Note Apart from addressing the ACU RAM, the ACU_addr

is also used as an argument for other ALU and branching
commands. The single ACU_addr value can be used simul-
taneously for different commands (ACU, ALU...) if coinci-

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 333

Digital Filter Block (DFB)

Figure 29-4. Streaming Mode Transfer

Holding Holding
Reg A2 Reg A1
24 Bit 24 Bit
Staging 128 X 24 RAM A A
Reg A
MAC,
ALU,
Shift,
etc.
Staging 128 X 24 RAM B B
Reg B Holding Holding
Reg B2 Reg B1
24 Bit 24 Bit
Input
Select

In input Streaming mode, the sample rate is determined by ters with the low order ACU RAM address bit (acu_addr[0]).
the ADC or other sampling resources providing the input If the address bit is low, Staging register A is read; if the
samples. By definition the DFB must be running (process- address bit is high, B is read. When read, the associated
ing) samples faster than or at the exact same rate as the Stage Valid signal is automatically cleared by the hardware.
sample source to function properly. Therefore, the DFB
Apart from this, the Staging register also has a key coher-
knows how to stall and wait for subsequent input data or
ence byte setting. This setting is available to reduce errors
postpone operation on that channel and switch to another
due to bus access being less wide as compared to the regis-
channel (if in use).
ter width. The staging registers are protected on writes, so
When the calculation engine is finished processing a sam- the underlying hardware does not incorrectly use the field
ple, a bus read instruction can be issued. At this point, the when it is partially updated by the system software. If the
next staged sample is read or, if not present yet, the DFB system software is in the middle of reading from the holding
controller stalls while waiting for the next input sample. If two registers, the DFB will not update the holding registers until
streaming channels are being processed, the DFB control- the coherency key byte is read. The Key Coherency byte is
ler, upon completion of a calculation, can jump to the other basically the user (software) telling the hardware which byte
channel. of the field is written or read last when an update to the field
is desired. In the Staging register the new value availability
The full or empty status of the two Staging registers is visi-
is flagged only when the key coherency byte is written to.
ble to the DFB controller and it can branch based on the sta-
tus information, allowing it control of which channel it is
29.3.4.2 Block Transfer Modes
working on.
Block mode is defined by the system software moving sets
When the bus read instruction is issued by the DFB control-
of samples or coefficient data in and out of the DFB data
ler, it does not request the bus, generate an interrupt, or
RAMs in blocks. This method of using the DFB supports
DMA request. It simply tells the DFB bus interface that it
such features as multi-channel processing and deeper filters
wants the next sample and will wait until it arrives. In this
than the embedded data RAMs will support. It can also be
state, the DFB controller waits until the bus interface signals
used to initialize the DFB RAMs for streaming mode opera-
that the sample has arrived. A one 24-bit word Staging reg-
tion.
ister is used for a sample rate at or below 1 Msps and guar-
anteed bus latency lower than the sample period. There are The DFB datapath block has two 128x24 embedded data
two Staging registers: one for each supported channel. RAMs. These hold the data (signal or coefficients) used in
the calculation of numerical processes. These two RAMs
In streaming mode new samples arrive in the staging regis-
are completely separate memories from the bus’ point of
ters. The DFB controller checks for new data write to staging
view. The DFB views these two RAMs as a working set, as
registers and branch to process data depending on the
shown in Figure 29-5 on page 335.
CFSM code.

The input staging registers are read by the DFB controller by

asserting the bus read signal and addressing the two regis-

334 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Digital Filter Block (DFB)

Figure 29-5. Block Mode Transfer

128 X 24 RAM A A
MAC
Bus Control ALU
Logic Shift
etc
128 X 24 RAM B B

RAM Control from CSR

The primary concept of Block mode is to allow the system Typically, results of DFB applications are streaming in
software full control of what is in the data RAM for each cal- nature. However, in cases where results are created as data
culation cycle of the DFB. In general, this extends the func- sets, Block mode can be used to move the resultant data
tionality of the DFB by trading performance for fundamental sets out of the DFB data RAMs.
features such as the ability to implement filters with more
taps than 128 or to time division multiplex the processing of 29.3.4.3 Result Handling
more than two low sample rate channels. The system soft-
Frequently DFB block output results are generated at peri-
ware burden of Block mode is in the management of the
odic intervals after a series of mathematical calculations.
RAM’s contents. Both system and DFB performance is lost
This also happens after a wait for the input sample stream.
due to software servicing of the DFB and because the DFB
The generation rate of these result elements will vary radi-
must stall while the system software reads/writes the data
cally based on the function being programmed and run on
RAMs. Block mode also creates more bus traffic on the sys-
the DFB.
tem bus for a given sample rate.
To assist system software with the handling of resultant
The system software takes control of memory by putting it
data, the DFB implements two Holding registers, 24 bits
on the system bus with the use of (DFB_RAM_DIR) control
wide, for output results. In reality, these two Holding regis-
bits (one per RAM). It then reads/writes the data and
ters are double buffered, but to the DFB controller and the
“passes” the memory back to the DFB by toggling the con-
system bus, they appear as a single register. They are
trol bit back. While this is happening, the DFB must stall,
referred to as a single register hereafter, but keep in mind
unless it is performing some function that only requires one
there are really two registers to deal with bus latency issues.
of the two data RAMs. The two data RAMs are individually
The fact they are double buffered is transparent to both the
controlled by the system software as to which resource has
bus and the DFB controller. Hardware automatically man-
control of them – the bus or the DFB.
ages the fact that they are double buffered.
Any number of data channels can be supported with Block
The intent of having two fully addressed Holding registers is
mode (within reason). With each added data channel, the
primarily to allow the controller and system software to map
system software has the additional burden of tracking and
filter channels so that DMA requests are much easier to
managing and sample rates supported reduces consider-
support. The two Holding registers are addressed with the
ably since the DFB must be stalled for data movement oper-
low-order ACU address bit out of the Control Store.
ations.
When bus write is asserted in the CS word and the low-
The DFB controller provides a semaphore methodology to
order ACU address bit (acu_addr[0]) is low, Holding register
communicate with the system software as to the status of
A is written and Holding register B is written when the low-
the data RAMs when being passed back and forth for block
order address bit is high.
transfers. Optional interrupt support can be associated with
the setting and clearing of semaphores. There are a couple of methods provided to read the Holding
registers on the system bus. These registers are generic

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 335

Digital Filter Block (DFB)

read only CSRs. They can be read manually by software ware which byte of the field is read last. The Holding
running on the MCU under poled or interrupt control registers are considered read once the key coherency byte
(DFB_INTR_CTRL), or each can be associated with a DMA is read.
request signal and read by the system DMA controller
Note 1 In Block mode, when more than two channels are
(DFB_DMA_CTRL). Pending interrupts from the Holding
being processed, management of the output results is more
register update is monitored from the DFB_SR register.
burdensome to the system software as it can no longer be
Operations on the Holding registers are protected. The constantly mapped one-to-one with a Holding register or
nature of the protection is set by the coherence bits DMA request.
(DFB_COHER). The Holding registers are protected on
Note 2 In 8-bit devices, reading the Holding registers man-
reads so that the underlying HW doesn’t update it when par-
ually results in a multi-cycle operation.
tially read by the System SW or DMA. The key coherency
byte is selected in the Coherency register. The Key Coher- Figure 29-6 explains DFB control signals can be used for
ency byte is basically the user (software) telling the hard- data streaming and result handling.

Figure 29-6. Control Signals for Data Streaming and result handling

Dfb_intr
INTR_CTRL [0]
Stage A
Valid, in1
Dfb_dmareq1
Stage A DMA_CTRL [1:0]
Coherency Key
DFB_COHER[1:0]
Data Write Strobe Hold A
Stage A Stage A Stage A 128 X 24
A
LOW MED HIGH RAM A
[8 Bits] [8 Bits] [8 Bits] MAC,
DMA ALU, DMA
Shift,
CPU etc. CPU
Stage B Stage B Stage B 128 X 24
LOW MED HIGH B
RAM B
[8 Bits] [8 Bits] [8 Bits] Hold B
Data Write Strobe
Input
Stage B
Select Dfb_intr
Coherency Key
DFB_COHER[3:2] INTR_CTRL [1]
Stage B
Valid, in2
Dfb_dmareq2
DMA_CTRL [3:2]

336 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Digital Filter Block (DFB)

29.3.4.4 Data Alignment To set and clear semaphores bits, two DP ALU commands
are available: SEM_SET and SEM_CLR. For each active
The hardware provides a data alignment feature in the input
high bit of the ACU address, the corresponding semaphore
Staging registers and in the output Holding registers for sys-
bit is either set or cleared.
tem software convenience.
For system software to write into a semaphore bit the regis-
Both staging and holding registers support byte accesses
ter DFB_SEMA is used. The mask bit is set when the corre-
that addresses alignment issues for input and output sam-
sponding semaphore bit in the register is updated.
ples of 8 bits or less. Also, all four of these registers are
mapped as 32-bit registers (only three of the four bytes are Any of the semaphore bits can be optionally (programma-
used) so there are no alignment issues for samples between ble) associated with the system interrupt signal
17 and 24 bits. However, for sample sizes between 9 and (DFB_INTR_CTRL) or either of the DMAREQ
16, it is convenient to read and write these samples on bus (DFB_DMA_CTRL) outputs leaving the DFB, and/or either
bits 15:0, while they source and sink on bits 23:8 of the of the outgoing Global signal. Pending semaphore interrupts
Holding and Staging registers. are monitored from the DFB_SR register.

The CSR DALIGN provides bits that enable an alignment 29.3.4.6 DSI Routed Inputs and Outputs
feature which allows bus bits 15:0 to either be sourced from
Holding register bits 23:8 or sink to Staging register bits The DFB has the option to take two DSI global inputs
23:8. Each Staging and Holding register can be configured (globali1 and globali2) and two DSI global outputs (globalo1
individually with a bit in the DALIGN register. If the bit is set and globalo2).
high, the effective byte shift occurs. For example, if an out- Use of the global outputs is optional. If needed, they can be
put sample from the Decimator is 12 bits wide, aligned to bit programmed to carry one of four different DFB internal sta-
23 of the Decimator Output Sample register, and is desired tus/control signals. These can be routed to the DSI and
to stream this value to the DFB, the similar data alignment used as inputs to other circuits. The global outputs can be
feature of the Decimator can be enabled, allowing the 16 configured to carry semaphore, an interrupt, or DP status
bits of the Decimator Output Sample register to be read on signals as listed in Table 29-5 on page 338. This is done
bus bits 15:0. Setting the alignment feature in the DFB for using the DFB_DSI_CTRL register.
the Staging A input register, these 16 bits can be written on
bus bits 15:0 and will be written into bits 23:8 of the Staging The DSI inputs into the DFB to control operations of the
A register when required. FSM are optionally used as branching inputs to the Control-
ler's next state decoder. See the section on 29.3.1.4 Next
29.3.4.5 DMA and Semaphores State Decoder on page 330 for more details.

The DFB bus interface supports two DMA request signals.

These can be associated with the two Holding registers
(optional) or associated with the semaphore bits (see regis-
ter DFB_DMA_CTRL).

The DFB provides three generic semaphore register bits

that the system software and the DFB controller can use to
communicate. The intent of these three semaphores is to
allow the system software and the DFB controller to commu-
nicate the status of data movement in and out of the DFB
and, in particular, the handling of block data transfers. The
definition of these three bits is left to the system and control-
ler software architects.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 337

Digital Filter Block (DFB)

29.4 DFB Instruction Set

Each control word for the DFB is 32 bits long. The fields in the control word are as follows:
■ Datapath Mux Control – 6 bits
■ Data RAM R/W – 2 bits
■ Bus R/W – 1 bit
■ ALU Control – 5 bits
■ MAC Control – 2 bits
■ Shifter Control – 3 bits
■ ACU Control – 8 bits
■ ACURAM Address – 4 bits
■ End of Code Block – 1 bit

The mux control bits are split equally between the A and B paths each having 3 bits. Three bits are allocated and encode the
control of the mux1, mux2, and mux3 functions as shown in Table 29-5.

Table 29-5. Mux Functions

Assembly Function Function Function
Code Function
Name MUX1 MUX2 MUX3
0 BA mux1 = AHB Bus mux2 = mux1 mux3 = mux2 AHB ->ALU
1 SA mux1 = dp_out mux2 = mux1 mux3 = mux2 dp_out->ALU
AHB->RAM
2 BRA mux1 = AHB Bus mux2 = RAM out mux3 = mux2
AHB->ALU
dp_out->RAM
3 SRA mux1 = dp_out mux2 = RAM out mux3 = mux2
dp_out ->ALU
4 BM mux1 = AHB Bus mux2 = mux1 mux3 = MAC AHB->MAC->ALU
5 SM mux1 = dp_out mux2 = mux1 mux3 = MAC dp_out->MAC->ALU
AHB->MAC->ALU
6 BRM mux1 = AHB Bus mux2 = RAM out mux3 = MAC
AHB->RAM
dp_out->MAC->ALU
7 SRM mux1 = dp_out mux2 = RAM out mux3 = MAC
dp_out->RAM

338 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Digital Filter Block (DFB)

ALU functions are programmed as shown in Table 29-6 and are encoded in 5 bits.

Table 29-6. ALU Functions

Code Assembly Name Function
0 SET0 Set ALU output to 0
1 SET1 Set ALU output to 1
2 SETA PASS A to ALU output
3 SETB PASS B to ALU output
4 NEGA Set ALU output to –A
5 NEGB Set ALU output to –B
6 PASSRAMA Pass RAM A output directly to ALU output
7 PASSRAMB Pass RAM B output directly to ALU output
8 ADD Add A and B and put result on the ALU output
9 TDECA Put A-1 on the ALU output, set threshold detection
10 SUBA Put B-A on the ALU output
11 SUBB Put A-B on the ALU output
12 ABSA Put |A| on the ALU output
13 ABSB Put |B| on the ALU output
14 ADDABSA Put |A| + B on the ALU output
15 ADDABSB Put A + |B| on the ALU output
16 HOLD Hold ALU output from previous cycle
17 ENGLOBALS, - Enables global and saturation jump conditions using a 3-bit field to specify which events are active jump conditions
17 ENSATRND, - Writes to the saturation and rounding enable register using a 3-bit field to enable and disable them
18 ENSEM, --- Enables semaphores as jump conditions using a 3-bit field to specify which are active
19 SETSEM, --- Set the semaphores high using the 3-bit mask
20 CLEARSEM, --- Set the semaphores low using mask, addr[2:0]
21 TSUBA Put B-A on the ALU output, set threshold detection
22 TSUBB Put A-B on the ALU output, set threshold detection
23 TADDABSA Put |A| + B on the ALU output, set threshold detection
24 TADDABSB Put A + |B| on the ALU output, set threshold detection
25 SQLCMP Load squelch comparison register with a value from side A, Pass Side B
26 SQLCNT Load squelch count register with value from side A, Pass Side B
Squelch side A: If value is above threshold pass it. If value is below threshold and the squelch count register is zero, pass.
27 SQA
zero. Otherwise pass A
Squelch side B: If value is above threshold pass it. If value is below threshold and the squelch count register is zero, pass.
28 SQB
zero. Otherwise pass B
29-31 UNDEFINED Undefined Opcodes

MAC functions are programmed as shown in Table 29-7 and are encoded in 2 bits.

Table 29-7. MAC Functions

Code Assembly Name Function
0 LOADALU Add ALU value to product and start new accumulation
1 CLRA Load accumulator with product but a 0 sum
2 HOLD Hold accumulator, no multiply (no power in mult)
3 MACC Default – just accumulate

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 339

Digital Filter Block (DFB)

Shifter functions are programmed as shown in Table 29-8 and are encoded in 3 bits. If deeper shifts are required, data can be
passed through the ALU on multiple cycles.

Table 29-8. Shifter Functions

Code Assembly Name Function
0 <default> No shift
1 shift(right,1) Shift right 1 (divide by 2)
2 shift(right,2) Shift right 2 (divide by 4)
3 shift(right,3) Shift right 3
4 shift(right,4) Shift right 4
5 shift(right,8) Shift right 8
6 shift(left,1) Shift left 1 (multiply by 2)
7 shift(left,2) Shift left 2 (multiply by 4)

Two ACUs are supplied. There are 16 functions per ACU as shown in Table 29-9 and are encoded in 4 bits. This RAM is use-
ful when parallel filters or algorithms are implemented and control flow needs to shift from one to the other, while still maintain-
ing the relative addresses for each filter.

Table 29-9. ACU Functions

Code Assembly Name Function
0 HOLD Put REG on output, hold REG in REG
If (modflag && REG = MREG
1 INCR Put LREG on output, write to REG else If (!modflag && REG = 127)
Put 0 on output, write to REG else Put REG+1 on the output, write to REG
If (modflag && REG = LREG)
Put MREG on output, write to REG
else If (!modflag && REG = 0)
2 DECR
Put 127 on output, write to REG
else
Put REG-1 on the output, write to REG
Read ACU RAM and put value on output
3 READ
Write to REG
Put REG on output, write output to RAM
4 WRITE
Hold REG in REG
5 LOADF Load FREG from ACU RAM, put REG on output
6 LOADL Load LREG from ACU RAM, put REG on output
7 LOADM Load MREG from ACU RAM, put REG on output
Put LREG on output, assert RAM write enable
8 WRITEL
Hold REG in REG
Set modflag true, put REG on output
9 SETMOD
Hold REG in REG
Set modflag false, put REG on output
10 UNSETMOD
Hold REG in REG
If (modflag)
Put LREG on output, write to REG
11 CLEAR
else
Put 0 on output, write to REG

340 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Digital Filter Block (DFB)

Table 29-9. ACU Functions (continued)

Code Assembly Name Function
If (modflag && REG+FREG>MREG) Put ((((REG+FREG)-MREG)-1)+LREG) on output else If (!modflag &&
12 ADDF
REG+FREG>127) Put (((REG+FREG)-127)-1) on output else Put REG+FREG on output, write to REG

If (modflag && REG-FREG<LREG)

Put MREG-((FREG-(REG-LREG))-1) on output
else If (!modflag && REG-FREG<0)
13 SUBF
Put 127-((FREG-REG)-1) on output
else
Put REG-FREG on output, write to REG

Put MREG on output, assert RAM write enable

14 WRITEM
Hold REG in REG
Put FREG on output, assert RAM write enable
15 WRITEF
Hold REG in REG

29.5 Usage Model

The instruction set is programmed into the controller based
on dual control stores and a control finite state machine.

The control store contains sequential blocks of instructions

to execute an algorithm. In the simplest programming
model, all of the statements will appear in line and the pro-
gram counter will step from zero to the end of the last
instruction.

In this architecture it is more efficient to reuse blocks of code

(such as implementing a biquad IIR section). In this specific
case, a block of 12 instructions are looped through with off-
sets in the ACU adjusted so that the correct coefficients and
data are used. To control the use of this subroutine, a
branching controller is needed. This is the Control Finite
State Machine (CFSM) in the controller.

The CFSM contains information on branching. At the end of

each clock cycle, the various datapath flags, ACU flags, and
globals are evaluated to determine if a jump condition is
met. A jump is only allowed at the end of a CS block, which
is indicated when the EOB (end of block) bit in the control
store word is set to ‘1’. The CFSM RAM stores information
about the current state, bits to control which of the input
flags are active, and the jump address.

Loop counters are often found in architectures supporting a

single instruction MAC for FIR filtering. The loop counter
function can be achieved more generally in this architecture
through the use of the ACU. The equal flag in the ACU gets
set when the address is equal to the mask in the MREG and
when the end of the ram is reached or zero. Thus a branch
is triggered when the address reaches a certain address.
This is how a single instruction, zero instruction overhead
branch loop for FIR filtering can be implemented.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 341

Digital Filter Block (DFB)

342 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Section F: Analog System

The PSoC® analog subsystem provides the device the second half of its unique configurability. All analog performance is
based on a highly accurate absolute voltage reference with less than 0.2% error over temperature and voltage. The configu-
rable analog subsystem includes analog muxes, comparators, mixers, voltage references, analog-to-digital converters (ADC),
digital-to-analog converters (DAC), and digital filter bocks (DFB). All GPIO pins can route analog signals into and out of the
device, using the internal analog bus. This feature allows the device to interface up to 62 discrete analog signals.

This section encompasses the following chapters:

■ Switched Capacitor/Continuous Time chapter on page 345
■ Analog Routing chapter on page 359
■ Comparators chapter on page 375
■ Opamp chapter on page 379
■ LCD Direct Drive chapter on page 383
■ CapSense® chapter on page 397
■ Temperature Sensor chapter on page 403
■ Digital-to-Analog Converter chapter on page 409
■ Precision Reference chapter on page 413
■ Delta Sigma Converter chapter on page 417
■ Successive Approximation Register ADC chapter on page 437

Top Level Architecture

Analog System Block Diagram

System Bus

Digital
ANALOG SYSTEM
LCD Direct
Filter +
Drive
Block Nx
ADCs Opamp
N x SAR
ADC
N x SC/CT Blocks
(TIA, PGA, Mixer, etc.)
SPC ADC

Temperature +
Sensor Nx Nx
N x DAC Del Sig CMP
ADC
CapSense

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 343

 Section F: Analog System

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 344

 30. Switched Capacitor/Continuous Time

The PSoC® 3 and PSoC® 5 Switched Capacitor (SC) – Continuous Time (CT) block is a general purpose block constructed of
a rail-to-rail amplifier with arrays of switches, capacitors, and resistors. Register configurations select the block functional
topology, power level, and bandwidth.

30.1 Features
The PSoC SC/CT block has these features:
■ Multiple configurations:
❐ Naked Opamp
❐ Continuous Time Unity Gain Buffer
❐ Track and Hold Amplifier
❐ Continuous Time Programmable Gain Amplifier
❐ Continuous Time Trans Impedance Amplifier
❐ Continuous Time Mixer
❐ Sampled Mixer (non return-to-zero sample and hold -- NRZ S/H)
❐ Delta Sigma Modulator
■ Routability to GPIO
■ Routable reference selection
■ Programmable power and bandwidth
■ Sample and hold configuration

30.2 Block Diagram

The overall block diagram of the block is shown in Figure 30-1 on page 346. Individual block diagrams for the possible imple-
mentations are shown in separate sections.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 345

Switched Capacitor/Continuous Time

Figure 30-1. Switched Capacitor and Continuous Time Block Diagram

Mod, CT, TIA :1. 275 pF

20 k or 40 k Mod, CT, TIA : 850 fF

10k G48/G50
Vin
20 k to 980 k
V ref

Vin
Mod Gain 0 : 850 fF
V out Mod Gain1 : 425fF
SC: 850 fF comp<1:0>
TIA : 850 fF 1. 25 fF – 5 pF

Vout

V out TIA : 850 fF

Mod Gain 0 : 425 fF
V ref Mod Gain 1 : 850 fF Vref
Vgnd

V ref

Vin
CT, TIA : 850 fF
SC: 850 fF
Trk Hld : 4.0 pF

346 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Switched Capacitor/Continuous Time

30.3 How it Works V

I load = C load ------- Equation 1
t
Each instance of the SC/CT block is able to implement any
of the available configurations. Selection of the mode bits ...where Cload includes the total internal capacitance at the
configures most of the resources required to implement output node of the amplifier plus any external capacitive
these configurations. loads. A value of 10 pF should be used for the internal load
from analog bus routing. Set the drive controls,
SC_DRIVE[1:0], according to the slew requirements at the
30.3.1 Operational Mode of Block is Set
output in SC[0..3]_CR1[1:0] register bits.
The operational mode of the SC/CT block is selected by set-
ting the MODE[2:0] bits in the SC[0..3]_CR1 register, bits Table 30-2. Output Load Current by Drive Setting
[3:1]. SC_DRIVE[1:0] I_load (µA)
2'b00 175
Table 30-1. SC/CT Block Operational Mode Settings
2'b01 250
SC_MODE[2:0] Operational Mode 2'b10 330
[000] Naked Opamp Mode 2'b11 400
[001] Trans Impedance Amplifier
[010] Continuous Time Mixer Figure 30-3. Naked Opamp Drive Control I_LOAD
90
[011] Discrete Time Mixer -- NRZ S/H
80
[100] Unity Gain Buffer
70
[101] First-Order Modulator
60
[110] Programmable Gain Amplifier 50

[111] Track and Hold Amplifier 40

dB
30

20
30.4 Naked Opamp 10
175 uA
250 uA
0 330 uA
The naked opamp mode provides direct access to the input -10
400 uA

and output terminals of the opamp. All of the other circuitry -20
(resistors and capacitors) is disconnected in this mode. This 0.001 0.01 0.1 1 10 100 1000 10000

mode is used for applications that require a general purpose

opamp with external components.
30.4.1 Bandwidth/Stability Control
Figure 30-2. Naked Opamp Configuration
This block has three control options for modifying closed
loop bandwidth and stability that apply to all configurations:
V IN + current through the first stage of the amplifier
V OUT (BIAS_CONTROL), Miller capacitance between the ampli-
fier input and the output stage (SC_COMP[1:0]), and feed-
V IN -
back capacitance between the output stage and the
negative input terminal (SC_REDC[1:0]).

The naked opamp is selected by setting the MODE[2:0] bits 30.4.1.1 BIAS_CONTROL
in the SC[0...3]_CR0 to 000. The opamp is a two stage The bias control option doubles the current through the
design with a rail-to-rail input folded cascade first stage and amplifier stage. AC open loop stability analysis for all contin-
a class A second stage. The opamp is internally compen- uous time modes shows that leaving this option set to ‘1’
sated. To accommodate varying load conditions, the com- and then controlling the bandwidth/stability using the capac-
pensation capacitor and output stage drive strength is itor options results in a greater overall bandwidth once the
programmable. circuit is stabilized than using the option of less current in
The setting to apply is determined from the minimum the first stage. The bias current is doubled by setting the
required slew rate determined from the signal swing and SC[0..3]_CR2[0] register bit.
time, and load capacitance. This is primarily a consideration
for the stability reasons.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 347

Switched Capacitor/Continuous Time

30.4.1.2 SC_COMP[1:0] 30.4.1.3 SC_REDC[1:0]

SC_COMP bits set the amount of compensation capaci- The capacitance option between the output driver and the
tance used in the amplifier. This directly affects the gain negative input terminal is another stability control option.
bandwidth of the amplifier and is an important tool in tuning Depending on the continuous time configuration, this capac-
the circuit stability. Follow the recommendations in the itor option generally contributes to a higher frequency zero
upcoming tables for this setting. The Miller capacitance is and a lower frequency pole, thus reducing the overall band-
set to one of the four values in the SC[0..3]_CR1[3:2] regis- width and gaining some phase margin at the unity gain fre-
ter bits. quency. This capacitance is set to one of the four values in
SC[0..3]_CR2[3:2] register bits.
Table 30-3. Miller Capacitance between Amplifier Output
and Output Driver Table 30-4. CFB in CT Mix, PGA, Opamp, Unity Gain Buffer,
SC_COMP[1:0] CMiller (pF) and T/H Modes
00 1.30 SC_REDC[1:0] CFB (pF)
01 2.60 00 0.00
10 3.90 01 1.30
11 5.20 10 0.85
11 2.15

Recommended Settings by Mode

Stability settings for each mode are listed in Table 30-5 on
page 348. These are the settings that were used to simulate
each mode.

For the transimpedance amplifier (TIA) mode, the analog

global load was modeled at the input as 10 pF between two
150  switch impedances with an additional 40 pF added to
the input to model the input diode capacitance.

For all continuous time modes, the output was modeled with
two 150 switches with an 8 pF load in between, then fol-
lowed b ya 300 impedance and a 50 pF external load.

The modulator mode was simulated with a 0.5 pF load at the

output.

Table 30-5. Recommended Stability Settings by Mode

SC_MODE[2:0] Operational Mode BIAS_CONTROL SC_COMP[1:0] SC_REDC[1:0]
[001] Trans Impedance Amplifier 1 3 3
[010] Continuous Time Mixer 1 2 1
[011] Discrete Time Mixer -- NRZ S/H 1 2 0
[100] Unity Gain Buffer 1 2 0
[101] First-Order Modulator 1 1 0
[110] Programmable Gain Amplifier See Table 30-7 on page 350
[111] Track and Hold Amplifier 1 2 0

348 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Switched Capacitor/Continuous Time

30.5 Continuous Time Unity Gain Buffer

The Continuous Time Unity Gain Buffer is a naked opamp with the inverting input locally connected to the output. Use of rout-
ing features external to the block is not required to implement this function.

Figure 30-4. Unity Gain Buffer Configuration

V IN
V OUT

The unity gain buffer is used when an internally generated signal with high output impedance, such as a voltage DAC output,
is required to drive a load; or when an external source with a high impedance is required to drive a significant on-chip load,
such as the Continuous Time Mixer.

30.6 Continuous Time Programmable Gain Amplifier

The Programmable Gain Amplifier (PGA) is a continuous time opamp with selectable taps for input and feedback resistances.
The PGA is selected by setting the MODE[2:0] bits in the SC[0...3]_CR0 register to ‘110’.

Figure 30-5. PGA Configuration

Rfb = 20 k to 1 Mohm

rval [000]:rval[101]

R in =20k or 40k
rval< 110 > : rval< 111>
R in = 9.6k or 19.6k
V in 0

1
V out
1

V ref 0
0.3k
pga _ rlad

sc_pga_ gndVref

sc _ gain

The PGA can be implemented as either a positive gain or The positive gain (non-inverting) topology is shown in
negative gain topology, or as half of a differential amplifier. Figure 30-6.
The specific gain configuration is selected by the SC_GAIN
bit [5] in register SCL[0..3]_CR1. Any added input resistance
from analog routing affects the PGA gain.

Table 30-6. PGA Gain Configuration

SC_GAIN Gain
0 Inverting (-RFB/RIN)

1 Non-inverting (1+ RFB/RIN)

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 349

Switched Capacitor/Continuous Time

Figure 30-6. PGA Positive Gain (Noninverting) Topology RLAD is at very high impedance to minimize gain errors. The
output of the differential amplifier is
VIN VOUT+ - VOUT- = Gain*(VIN+ - VIN-). Equation 2
VOUT
The common mode voltage of the output remains at the
common mode voltage of the input.

VCM = (VIN+ + VIN-)/2. Equation 3

VREF Because of capacitive loading, each gain step has a differ-
RIN RFB ent requirement for compensation capacitors.

Table 30-7. PGA Stability Settings by Gain

Figure 30-7. PGA Negative Gain (Inverting) Topology SC_RVA
Non-
R20_40B Inverting BIAS_ SC_COMP SC_REDC
L[2:0]
Gain (AC) CONTROL [1:0] [1:0]
RFB
Bin Bin Lin
0 0 1 1 2 0
0 1 1 1 2 0
VIN 1 0 2 1 2 1
RIN 1 1 2 1 2 1
10 0 4 1 0 1
VREF
10 1 4 1 0 1
11 0 8 1 0 1
11 1 8 1 0 1

Figure 30-8. PGA Differential Amplifier Topology 100 0 16 1 1 1

100 1 16 1 1 1
VIN+ 101 0 24 1 1 3

VOUT+ 101 1 32 1 1 3
110 0 24 1 0 2
110 1 48 1 1 0
111 0 25 1 0 2
111 1 50 1 1 0

RIN RFB
RLAD The negative gain (inverting) topology is shown in
Figure 30-7.

RLAD
RIN RFB 30.7 Continuous Time
Transimpedance Amplifier
The Transimpedance Amplifier (TIA) is a continuous time
opamp with dedicated and selectable feedback resistor. The
VOUT- TIA is selected by setting the MODE[2:0] bits in the
VIN- SC[0..3]_CR0 register to ‘001’.

The differential amplifier two PGAs in parallel. The connec-

tion (RLAD) is external to the SC blocks and has very low
impedance to reduce gain error. When not in differential
mode, RIN is connected to the analog or global routing and

350 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Switched Capacitor/Continuous Time

Figure 30-9. Transimpedance Amplifier Configuration The CFB options for TIA mode are larger than for the other
continuous time modes, as shown in Table 30-9. The feed-
C FB
back capacitance is set in bits [3:2] of the SCL[0..3]_CR2
register.

R FB Table 30-9. Feedback Capacitance Settings

SC_REDC[1:0] CFB (pF)

00 0.00
V IN
01 1.30
10 3.30
V REF 11 4.60

A large source capacitance causes instability in the TIA with

the small feedback resistor settings. Therefore, in applica-
The output of the transimpedance amplifier is a voltage that
tions where the internal capacitance is not sufficient to stabi-
is proportional to input current; the conversion gain is a
lize the TIA, an external capacitance is necessary. This is
resistor value, where:
connected using the analog global routing.
V OUT = V REF –  I IN  R FB  Equation 4

The output voltage is referenced to VREF, which is routable

to the analog globals or through local analog routing to any
selected reference.

The feedback resistor can be programmed from 20 k to

1.0 M in eight steps, selected in bits [6:4] of the
SCL[0..3]_CR2 register.

Table 30-8. Feedback Resistor Settings

SC_RVAL[2:0] Nominal RFB (k)

000 20
001 30
010 40
011 80
100 120
101 250
110 500
111 1000

The feedback resistor is untrimmed polysilicon, so the abso-

lute resistance value varies largely with process and tem-
perature. Calibration of the TIA gain is expected to be done
by the user using the precise outputs of the current output
DAC combined with measurements in the ADC.

Stability of this opamp topology in general is affected by

shunt capacitance on the inverting input. This capacitance is
determined largely by parasitic capacitances in the analog
global routing and at the input pin. An internal shunt feed-
back capacitor is used to maintain stability. Because the
input capacitance is larger in the TIA than in other modes,
the stability capacitance is somewhat larger.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 351

Switched Capacitor/Continuous Time

30.8 Continuous Time Mixer

The Continuous Time Mixer uses input switches to toggle a The output spectrum of the mixer includes terms at 455 kHz,
PGA between an inverting PGA gain of -1 and a noninvert- 55 kHz, at 3*fCARRIER ± fSIGNAL, 5*fCARRIER ± fSIGNAL,
ing PGA gain of +1. The maximum toggle frequency is 1 7*fCARRIER ± fSIGNAL, etc. The up conversion is ultimately
MHz. The continuous time mixer is selected by setting the achieved by filtering out the desired harmonic of the mixed
MODE[2:0] bits in the SC[0..3]_CR0 register to ‘010’. product of the input frequency and modulating frequency
using gain toggling.
The continuous time mode was chosen to achieve up con-
version because it provides higher conversion gain relative Usage options for the continuous time mixer mode include
to the sampled mixer. In the CT mixer the magnitude of the controlling the sampling function and setting the value of the
FCLK+FIN and FCLK-FIN are equal, while in the sampled resistor in the inverting gain configuration. The continuous
case, there is attenuation between the two configurations. time mixer configuration can be seen in Figure 30-11.

Example waveforms where the input is at 200 kHz and the

carrier is at 255 kHz are shown in Figure 30-10.

Figure 30-10. Continuous Time Mixer Waveforms

Signal
Ca rr ier
Mult
0 10 20 30 40

Figure 30-11. Continuous Time Mixer Configuration

R mix = 20 k or 40k

sc_clock

!sc_clock
Rmix = 20 k or40k
V in
V out
1
0
V ref

sc_clock

Table 30-11. Input Resistor Settings for CT Mixer Inverting

Mode
Table 30-10. Sampling Configurations for CT Mixer
R20_40B RMIX
SC_DYN_CNTRL Configuration
0 40 k
0 Inverting Amplifier with Gain of 1
1 20 k
1 Unity Gain Buffer

352 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Switched Capacitor/Continuous Time

30.9 Sampled Mixer In this example, we have a 500 kHz down-converted signal,
but we are sampling it at 2 MHz. Since the ADC and the
The Sampled Mixer is a nonreturn-to-zero (NRZ) sample switched capacitor block can both run at the same 2 MHz
and hold circuit with very fast response. The mixer is sample rate, there is no need to low pass filter the output of
selected by setting the MODE[2:0] bits in the SC[0..3]_CR0 the switched capacitor block. Its output can be fed directly
register to ‘011’. The discrete time mode has a maximum into the ADC input.
FCLK of 4 MHz. The maximum input frequency in discrete
A few examples illustrate the frequency shifting capabilities
time mode is 14 MHz. The mixer output is designed to either
of the mixer. For a signal frequency at 1.36 MHz, and a car-
drive an off-chip ceramic filter (i.e., 455 kHz Murata Cerafil)
rier at 1.28 MHz, the output frequency is the difference
or the internal ADC through the on-chip analog routing. In
between the two frequencies, as shown in Figure 30-12.
order for the ADC to correctly sample the mixer output, the
sample clock for the ADC and mixer must be the same. Figure 30-12. Sampled Mixer N = 1
The sample and hold mixer is primarily used for down-con-
version mixing. The down conversion is achieved by filtering
the desired harmonics of the mixed product of the input fre-
quency and sample clock frequency. Correct frequency
planning is required to achieve the desired results. For a
given input carrier frequency, FIN, a sample clock frequency,
FCLK, can be chosen to provide the desired IF frequency,
FIF, for the system.
Signal
Provided that FCLK is less than 4 MHz, and FIN is less than
Carrier
14 MHz:
Dif f

If 0 5 10 15 20 25 30 35

2N – 1-
--------------- F CLK  F IN  N  F CLK Equation 5
2 For a higher frequency signal at 13.6 MHz, and the carrier at
then 3.2 MHz, the output is at the same frequency, but longer
separation between the samples, as shown in Figure 30-13.
F IF = N  F CLK – F IN Equation 6 Figure 30-13. Sampled Mixer N = 3
If

2N + 1
N  F CLK  F IN  ---------------- F CLK Equation 7
2
then

F IF = F IN –  N  F CLK  Equation 8

Equation 1 and Equation 2 can be summarized as: Signal

Carrier
F IF = abs  N  F CLK – F IN  Equation 9 Dif f
0 0.5 1 1.5 2 2.5 3 3.5
Consider an example using an input carrier frequency of
13.5 MHz and a desired IF frequency of 500 kHz. We set the
sample clock frequency and the ADC sample frequency to
be 2 MHz. There is no increase in harmonic distortion, only an increase
in the level of the sampling aliases. When the mixer output
From the down conversion equations above, we can calcu-
is sampled at the same rate as the carrier frequency, the
late the IF frequency with N = 7.
aliases are suppressed.
F IF = 7  F CLK – F IN = 500kHz Equation 10 The discrete time mixer configuration (NRZ S+H) is shown
in Figure 30-14 on page 354. The options specific to this

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 353

Switched Capacitor/Continuous Time

configuration are the reference option and the clock division of the input clock. This is achieved by resetting the
option. SC[0..3]_CR1[4] bit.

Figure 30-14. Switched Capacitor Discrete Time Mixer Table 30-13. Clock Division Option for Sample and Hold
Configuration
C1 1 Mixer
Vin
SC_DIV SC_CLOCK Requirements
SC_CLOCK should be set to half the desired sample
1&!sc_gndVref 2 0
frequency
Vref SC_CLOCK should be set to the desired sample
1&sc_gndVref 1
frequency

sc_gndVref
V out
!sc_gndVref
Vref
2&!sc_gndVref
Vref
2&sc_gndVref
1

C4 Vin
2

The option exists to either use an external reference voltage

or to have the reference grounded internally. This option is
controlled by the SC_GNDVREF SC[0..3]_CR2 signal as
described in Table 30-12.

Table 30-12. External Reference Option for Sample and

Hold Mixer
SC_GNDVREF Amplifier/Capacitor Reference
0 External Voltage
1 Internal Ground

The use of the internal ground can cause different step sizes
up versus down because the amplifier does not respond
identically when the negative terminal jumps below ground.
To avoid this distortion, use the external reference option
and set it to 500 mV or greater.

The architecture of the discrete mixer is such that the output

changes with a new hold value on both the rising and falling
edge of the input clock. The SC_DIV control signal can be
used to designate that output only change on the rising edge

354 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Switched Capacitor/Continuous Time

30.10 Delta Sigma Modulator

The SC/CT block can be programmed to function as a switched capacitor integrator to use in a first-order modulator loop at
high oversampling ratios.

The Delta Sigma Modulator is selected by setting the MODE[2:0] bits in the SC[0..3]_CR0 register to ‘101’. The integrator out-
put is compared to a reference level and fed back to the input in a feedback loop. The modulator output is clocked at the high
sampling rate, and needs to be decimated down to the signal band of interest using a decimation filter.

Figure 30-15. Discrete Time Delta Sigma Modulator Block Diagram

+
Out
Sample / Hold Integrator Comparator

Input

The modulator can also be used as an incremental modulator by using a reset switch that is placed across the integrating
capacitor. The accuracy of the sampled data from the first-order modulator is determined from several factors: the maximum
input signal bandwidth, oversampling ratio, and the sampling clock jitter. The oversampling clock is limited to a maximum of
4 MHz. Oversampling below x64 does not produce a stable output. Table 30-14 below shows the expected performance from
a system simulation.

Table 30-14. Incremental Modulator Expected Performance from System Simulation

Signal-to-Noise Ratio After
Oversampling Rate OSR
Maximum Input Signal Frequency Sampling Clock Frequency (MHz) Decimation by OSR
(fsamp/fsig/2)
(at Maximum Input Signal)
16 kHz 64 2.048 54 dB
8 kHz 128 2.048 64 dB
32 kHz 64 4.096 54 dB
16 kHz 128 4.096 64 dB

The Signal-to-Noise Ratio (SNR) values include the effects of limit cycle oscillations.

The configuration diagram of the discrete time first-order modulator is shown in Figure 30-16 on page 356. There are two
mode-specific usage options: a reset switch placed across the integrating capacitor and a gain setting to adjust the allowable
input amplitude range.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 355

Switched Capacitor/Continuous Time

Figure 30-16. Switched Capacitor First-Order Modulator Configuration

Sampling Phase
C 5 = 1.7pF

C 4 = 850fF
Gain 0: C 1 = 850F
Gain 1: C 1 = 425F C 2 = 850fF
V in
sc_dyn_cntrl

V ref

Vout_mod = 0 V ref V out

Vout_mod = 1
Gain 0: C3 = 425fF Comparator Vout _mod
Gain 1: C3 = 850fF V ref

Integrating Phase

C 5 = 1.7pF

C 4 = 850fF

Gain 0: C1 = 850F Gain 0: C3 = 425fF

Gain 1: C1 = 425F C 2 = 850fF
Gain 1: C3 = 850fF
V ref
sc_dyn_cntrl

Vout_mod = 0 V out
Vout_mod = 1
V ref

Comparator Vout _mod

V re f

V ref

30.10.1 First-Order Modulator, Incremental The range of the allowed input amplitude can be set using
Mode the SC_GAIN SC[0..3]_CR1[5] control signal as shown in
Table 30-16.
The dynamic control input SC[0..3]_CR1[5] can be used to
reset the integrating capacitor if to perform an incremental Table 30-16. First-Order Modulator, Input Amplitude
conversion: SC_GAIN Maximum Input Amplitude
0 ± half VREF
Table 30-15. First-Order Modulator, Integrating/Incremental
Mode 1 ± 2 VREF

SC_DYN_CNTRL State
0 Integrating
Reset. VOUT is connected to amplifier negative
1
terminal.

356 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Switched Capacitor/Continuous Time

30.11 Track and Hold Amplifier

Track and hold amplifier mode is derived using the unity
gain buffer amplifier. Implementation is shown in
Figure 30-17.

Figure 30-17. Track and Hold Block Diagram

!sc_dyn_cntrl VOUT
VIN
Ctrk_hld = 12.0 pF
(pfet gate cap)

Track and hold mode tracks to 1 percent of a 5.5V input step

in less than 1 µs. The charge injection error from the sample
switch is < 1.1 mV. The hold loss is < 0.2 mV.

The control of the amplifier between track and hold is done

using the SC_DYN_CNTRL input as shown in Table 30-17.

This feature is enabled by setting the register bit value

SC[0..3]_CLK[5].

Table 30-17. Track and Hold Amplifier Control

SC_DYN_CNTRL Output
0 Track VIN

1 Hold sampled value

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 357

Switched Capacitor/Continuous Time

358 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 31. Analog Routing

PSoC® 3 and PSoC® 5 have a flexible analog routing architecture to route signals between GPIOs and analog resource
blocks such as the ADC, Switched Capacitor, DAC, etc. One of the strong points of this flexible routing architecture is that it
allows dynamic configuration of input/output connections to the different analog blocks. For example, the comparator input
could be switched between two GPIOs, on the fly, by DSI control signals and register settings. Knowing and understanding
the architecture enables efficient and optimal utilization of the device analog routing resources.

31.1 Features
PSoC® analog routing has the following features:
■ Flexible, configurable analog routing architecture
■ Dedicated routing options for LCD drive capability
■ Eight analog globals (AGs) and one analog multiplexer bus (AMUXBUS) for GPIOs on each side
■ Flexible routing options within the analog core to interconnect analog resource blocks using analog local bus (abus)

31.2 Block Diagram

The PSoC 3 and PSoC 5 analog system block diagram is shown in Figure 31-1 on page 360. In Figure 31-1, the CapSense®
system is limited to the GPIO controls, there are no separate blocks. Figure 31-2 on page 361 shows detailed analog routing
architecture. All the figures used to explain analog routing in this chapter are derived from Figure 31-2.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 359

Analog Routing

Figure 31-1. Analog System Block Diagram

ANALOG SYSTEM

Left Side Right Side

Left Side Right Side
Analog Globals Analog Globals
ARBs ARBs
and Muxes and Muxes

Delta Sigma
LCD
Channel (1x)

LPF LPF

Right Side GPIO

Left Side GPIO

Switched Switched
Capacitor (2x) Capacitor (2x)

DAC (2x) DAC (2x)

Opamp (2x) Opamp (2x)

Comparator (2x) Comparator (2x)

CapSense CapSense
Refbuf Refbuf

SAR0 SAR1

5 8 4 CY8C55 only
4 8 5

Analog Analog Analog Analog Analog Analog LCD

Precision
LCD Mux Global Local
Reference
Local Global Mux
Bus Bus Bus Bus Bus Bus

Analog Interface

360 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Analog Routing

Figure 31-2. Analog Interconnect

Vssio
Vdab

Vdda

Vsab
Vssa

Vcca

Vssd
* * * *
Upper Left Quadrant Upper Right Quadrant

P15[3]

P15[2]

P12[1]

P12[0]
P12[3]

P12[2]

GPIO

GPIO

GPIO

GPIO
GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

P3[7]

P3[6]
P0[3]

P0[2]

P0[1]

P0[0]

P4[1]

P4[0]
Vio0

Vio3
SIO

SIO
SIO

SIO
* * * * * * * *
AMUXBUSL AMUXBUSR
* *
AGL[4] AGR[4]
AGL[5] AGR[5]
AGL[6] AGR[6]
AMUXBUSL

AGL[7] AGR[7]
AGL[4]
AGL[5]
AGL[6]
AGL[7]

ExVrefL ExVrefL2 44
ExVrefL1
opamp0 opamp2
opamp3 opamp1 GPIO
01 23456 7 0123 3210 76543210 P3[5]
GPIO
GPIO
*

P0[4]
GPIO P3[4]
GPIO
*

P0[5]
GPIO P3[3]
i0 1.024V in0 LPF in1 GPIO
P0[6] *
1.024V
out0 5 out1 ExVrefR
GPIO P3[2]
i2 GPIO
P0[7] * + comp0
-
comp1 +
- i3 P3[1]
1.024V COMPARATOR 1.024V
GPIO
i1 P3[0]
GPIO + comp2 comp3 +
0.256V - 90 - GPXT
P4[2] *P15[1]
GPIO vda, vda/2
GPXT
P4[3] 1.024V out CAPSENSE out 1.024V
*P15[0]
ref ref
GPIO 1.2V
in refbufl refbufr in
1.2V

P4[4]

AGR[7]
AGR[6]
AGR[5]
AGR[4]
AMUXBUSR
GPIO Vssa sc0 sc1 Vssa
*
P4[5] Vin Vin
Vccd
GPIO Vref Vref
1.024V out out 1.024V
P4[6] SC/CT Vssio
GPIO Vin Vin
Vref Vref *
P4[7] Vssd
* out out
Vccd sc2 104 sc3 *
* Vddd
Vssd ABUSL0 ABUSR0
ABUSL1 ABUSR1 Vusb
ABUSL2 ABUSR2
Vssio ABUSL3 ABUSR3
*
Vddd v0 USB IO
v1
GPIO i0
VIDAC i1 * P15[7]
P6[0] v2 36
USB IO
GPIO i2
v3
i3
* P15[6]
P6[1] 0.256V
GPIO
GPIO P5[7]
P6[2] + dsm0 GPIO
GPIO
- DSM P5[6]
vpwra, qtz_ref 28
P6[3] 0.8V vpwra/2 Vssa GPIO
GPIO refs P5[5]
0.7V
P15[4] 1.2V
GPIO
vda,
GPIO 1.024V vda/4 ExVrefL ExVrefR P5[4]
P15[5] CY8C55 only SIO
Vp (+) (+) Vp
GPIO P12[7]
Vn (-) SAR0 SAR1 (-) Vn
P2[0] Vrefhi_out Vrefhi_out SIO
GPIO refs refs P12[6]
P2[1]
1.2V
1.024V vda,
vda/2
SAR ADC vda,
vda/2
1.2V
1.024V GPIO
GPIO CY8C55 only ExVrefL1 ExVrefL2 CY8C55 only
*P1[7]
P2[2] GPIO
GPIO AMUXBUSL 01234567 0123 3210 76543210 AMUXBUSR *P1[6]
P2[3] * ANALOG ANALOG
GLOBALS
ANALOG ANALOG
BUS BUS GLOBALS
GPIO
AMUXBUSR
AGR[0]
AGR[3]
AGR[2]
AGR[1]

P2[4] * TS
VBE
:
AMUXBUSL

* VSS ref
Vio2 ADC
AGL[1]
AGL[2]
AGL[3]
AGL[0]

LPF

AGL[3] AGR[3]
AGL[2] AGR[2]
AGL[1] AGR[1]
AGL[0] AGR[0]
AMUXBUSL AMUXBUSR
13 * * * * *
*
*

Mux Group * * *
P12[4]

P12[5]

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO
GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

P5[0]

P5[1]

P5[2]

P5[3]

P1[0]

P1[1]

P1[2]

P1[3]

P1[4]

P1[5]
P2[5]

P2[6]

P2[7]

P6[4]

P6[5]

P6[6]

P6[7]

Vio1

Switch Group
SIO

SIO

Connection

* * * * *
Lower Left Quadrant Notes: Lower Right Quadrant
XRES_N
Vssio
Vssb

Vssd

# Size
Vbat

Other: * Denotes pins on all packages

Ind

Vb

DFT 24 Small
266 Small (higher z) LCD signals are not shown.
LCD 15 Small Rev. #44
93/122 Large (lower z) June 22, 2009

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 361

Analog Routing

31.3 How it Works ■ In the lower right half, Px[3:0] maps to AGR[3:0] and
Px[7:4] maps to AGR[3:0]
Analog routing resources in PSoC 3 and PSoC 5 devices ■ In the upper right half, Px[3:0] maps to AGR[7:4] and
include analog globals (AGs), analog mux bus (AMUXBUS), Px[7:4] maps to AGR[7:4]
liquid crystal display bias bus (LCDBUS), and local analog
buses (abus). The analog globals and AMUXBUS go to the This means that two pins on each port are connectable to
GPIOs and provide a way to route signals between the the same global as shown in the diagram. The analog global
GPIOs and the analog resource blocks (ARBs). The LCD- bus connects to inputs and/or outputs of the following ARBs:
BUS is used for LCD bias signal routing. DAC, comparator, output buffer, switched capacitor, Delta
Sigma ADC, and CapSense (which is a virtual block). These
Analog resource blocks include the following: DACs, com- connections are made through switches and muxes.
parators, CapSense, switched capacitors, Delta Sigma PRT[x]_AG registers are used to configure the analog glo-
ADC, and opamps. The analog local buses (abus) are local bals (AGs) for each GPIO port pin. Refer to 31.6 Analog
buses used for connections between ARBs. Routing Register Summary on page 373 for register details.
In addition, there is a VREF bus as shown in Figure 31-2 on Port 12 contains the Special Input/Output (SIO) pins. These
page 361. This VREF bus carries the reference voltages for pins are grouped in pairs for each quadrant of the device
different analog blocks that are generated by the precision (lower right: P12[6] and P12[7], lower left: P12[4] and
reference block. Refer to the Precision Reference chapter P12[5], upper left: P12[2] and P12[3], upper right: P12[0]
on page 413 for details on these reference voltages. and P12[1]), with each pair sharing a reference generation
Analog switches and muxes establish connections between (REFGEN) block. The SIO REFGEN block can select from
the above mentioned analog routing buses and the ARBs. one of two analog globals routed to the pair shown in
Figure 31-2 on page 361. The mux selection is controlled by
All these analog routing resources are explained in detail in the {PRT12_AG} register. Refer to the I/O System chapter
the following sections. on page 187 for details about SIO operation.
Figure 31-4 on page 364 illustrates the difference between
switches and muxes. 31.3.2 Analog Mux Bus (AMUXBUS)
There are two AMUXBUS routes in PSoC 3 and PSoC 5
31.3.1 Analog Globals (AGs) devices. The device can be divided into two halves (left and
The PSoC 3 and PSoC 5 die is divided into four quadrants right), with each half having one AMUXBUS (AMUXBUSR,
as shown in Figure 31-2 on page 361 and Figure 31-3 on AMUXBUSL). The left and right AMUXBUS may be shorted
page 363. The analog global bus has eight routes on each together with an analog switch. Every GPIO has the provi-
side, AGL[7:0] on the left, and AGR[7:0] on the right. Within sion to connect to an AMUXBUS through an analog switch.
each side, the bus is divided into two groups, AGR[3:0] and CapSense applications use the AMUXBUS for their opera-
AGR[7:4] for the right side, and AGL[3:0] and AGL[7:4] for tion. Refer to the CapSense® chapter on page 397 for
the left side. The lower four globals on each side are routed details on using this bus for CapSense applications.
to the GPIO in the lower half of the die and the upper four PRT[x]_AMUX registers are used to configure the AMUX-
globals on each side are routed to the GPIO in the upper BUS routing for each GPIO port pin. Refer to 31.6 Analog
half of the die. All eight analog globals on each side get Routing Register Summary on page 373 for register details.
routed to ARBs on the same side. Analog globals can be
used as single ended or differential signal paths. The left 31.3.3 Liquid Crystal Display Bias Bus
and right half globals may operate independently or they (LCDBUS)
may be joined through the switches that are shown at the
top and bottom of Figure 31-3 on page 363. The LCD bias bus contains five routes that connect to every
GPIO. These routes are continuous around the device
Each GPIO may be connected to an analog global through a periphery and are not separated by switches at the midline
switch in the following manner: as are the analog globals and AMUXBUS. Each LCD route
■ In the lower left half, Px[3:0] maps to AGL[3:0] and is individually configurable so that they are driven by the
Px[7:4] maps to AGL[3:0] analog local bus or LCD bias voltage to the LCD driver buf-
■ In the upper left half, Px[3:0] maps to AGL[7:4] and fer located in the GPIO. Connecting to an analog bus allows
Px[7:4] maps to AGL[7:4] low frequency analog signals to drive off-chip through the
LCD driver buffers.

362 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Analog Routing

The LCDBUS mux selections are given in the following table. Refer to the LCD Direct Drive chapter on page 383 for LCD
operation and biasing. Refer to 31.6 Analog Routing Register Summary on page 373 for register details.

Table 31-1. LCD Bias Bus Mux Selections

Output Mux Selections
LCD_BIAS_BUS[0] {0=LCDDAC_V0,1=abusr[0],2=abusl[0],3=NA}
LCD_BIAS_BUS[1] {0=LCDDAC_V1,1=abusr[1],2=abusl[1],3=NA}
LCD_BIAS_BUS[2] {0=LCDDAC_V2,1=abusr[2],2=abusl[2],3=NA}
LCD_BIAS_BUS[3] {0=LCDDAC_V3,1=abusr[3],2=abusl[3],3=NA}
LCD_BIAS_BUS[4] {0=LCDDAC_V4,1=AMUXBUSR,2=AMUXBUSL,3=NA}

Figure 31-3. Analog Globals, AMUXBUS, and LCDBUS Routing

AG[4]L AG[4]R
AG[5]L AG[5]R
AG[6]L AG[6]R
AG[7]L AG[7]R

5 LCD Bias Bus

AMUXBUSL AMUXBUSR
GPIO GPIO
Px[0] Px[0]
GPIO GPIO
Px[1] 7 6 5 43 2 1 0 Px[1]
GPIO 01 2 3 4 56 7 GPIO
Px[2] Px[2]
GPIO GPIO
Px[3] Px[3]
GPIO GPIO
Px[4] Px[4]
GPIO GPIO
Px[5] Px[5]
GPIO GPIO
Px[6] Upper Left Quadrant Upper Right Quadrant Px[6]
GPIO GPIO
Px[7] Px[7]

GPIO GPIO
Px[0] Px[0]
GPIO GPIO
Px[1] Px[1]
GPIO Lower Left Quadrant Lower Right Quadrant
GPIO
AMUXBUSL

Px[2] Px[2]
GPIO
AMUXBUSR

GPIO
Px[3] Px[3]
GPIO GPIO
Px[4] Px[4]
GPIO GPIO
Px[5] Px[5]
GPIO GPIO
Px[6] 01 2 3 4 56 7 Px[6]
GPIO 7 6 5 43 2 1 0
GPIO
Px[7] Px[7]

AG[3]L AG[3]R
AG[2]L AG[2]R
AG[1]L AG[1]R
AG[0]L AG[0]R

Switch
Connection

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 363

Analog Routing

31.3.4 Analog Local Bus (abus) Figure 31-4. Difference Between Analog Switches and
Muxes
There are eight analog local bus (abus) routes in PSoC 3

AMUXBUS (1 of 2)
LCDBUS (1 of 5)

abus (1 of 8)
Analog Global (1 of 16)
and PSoC 5 devices, four in the left half (abusl[0:3]) and four
in the right half (abusr[0:3] as shown in Figure 31-2 on
page 361. These are local routes located in the analog sub-
system and are for interconnecting ARBs, which reduces ARB Mux
the usage of AGs. They do not route directly out into GPIOs.
It is possible to short the left and right abus’ together with LCD MUX
IN
four analog switches. ARBs may connect to each other
through analog globals (AG) or the analog local bus (abus).
ARB1
For example, in Figure 31-2 on page 361, a DAC output GPIO
(V1, for example) may be used as a reference for a compar-
ator negative input (COMP1, for example). Using an analog ARB2
GPIO Switch OUT
switch, the DAC output could be placed on AGR0 and the
comparator input switch could also be set to AGR0. Since IN
there are a limited number of available analog globals (eight ARB Switch ARB3
per side), some block to block connections can be made OUT
through analog local bus for direct connections between
blocks. For above example, the DAC output (V1) can be
routed directly to the analog local bus (abusr3) that goes to
the negative input of the comparator (COMP1). This saves
the GPIO routing resource from being used for interconnect-
ing two ARBs. 31.3.5.1 Control of Analog Switches
Analog globals (AGs), analog mux bus (AMUXBUS) and the
31.3.5 Switches and Multiplexers analog local bus (abus) all use analog switches to establish
connections. As stated earlier, analog switches can be
Switches and multiplexers are used to establish connections
grouped together to form multiplexers or switches.
using different analog routing buses. They are placed on the
various buses to direct signals into and out of the GPIOs Each GPIO has two analog switches, one to connect the pin
and ARBs. to the analog global and the other to connect the pin to the
AMUXBUS. The open/close control signals for these analog
In a switch with ‘n’ inputs and one output, zero through ‘n’
switches can be generated by either one of the following two
switches may be on at a time, whereas in a multiplexer
ways:
(mux) with ‘n’ inputs and one output, only one switch may be
on at a time. Note that a group of eight analog switches 1. The registers corresponding to the GPIO pin,
requires eight bits for configuration, whereas, a mux with PRT[x]_AMUX and PRT[x]_AG, can be used to control
the open/close state of the analog switches. This is the
eight analog switches requires only three bits. Figure 31-4
default option.
illustrates the difference between switches and muxes, in
switch and mux symbols. 2. In addition, there is a provision to dynamically control
these switches by means of the DSI control signal that is
For example, in Figure 31-4, there are two muxes (ARB, connected to the input of the port pin logic block. This
LCD). In both these muxes, only one of the analog switches option is enabled by setting the bit in the Port Bidirection
can be selected for routing. In the same figure, there are two Enable register (PRT[x]_BIE). For example, to control
switches (GPIO, ARB). For these switches, more than one pin 3 of port 0, a value of 0x08 is written to PRT[0]_BIE.
analog switch can be selected for routing. Note that both The switch control signal is the logical AND of the regis-
ter setting, as in the first case, and the DSI control sig-
muxes and switches are formed using analog switches.
nal, as shown in Figure 31-5.
Each GPIO is connected through two analog switches to an
analog global and an AMUXBUS. The ARBs use ARB
switches and ARB muxes for input/output routing options.

364 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Analog Routing

Figure 31-5. GPIO Pin Input/Output Block Diagram

Digital Input Path Naming Convention
PRT[x]CTL ‘x’ = Port Number
PRT[x]DBL_SYNC_ IN ‘y’ = Pin Number

Digital System Input 1 Sync

0
PRT[x]PS

PICU[x]INTTYPE[y]
PICU[x]INTSTAT Input Buffer Disable
Pin Interrupt Signal Interrupt
Logic
PICU[x]SNAP

Digital Output Path

PRT[x] SLW
PRT[x] BYP
PRT[x]DR 0
Output from DSI In
0 Vio Vio
1
Sync 1
Vio
PRT[x] SYNC_ OUT

PRT[x] DM2 Drive

Logic Slew
PRT[x] DM1 PIN
Cntl
PRT[x] DM0

Output Enable from DSI

PRT[x] BIE OE

Analog
1 0

1 0
CapSense Global Control 1
PRT[x]_CAPS_SEL[y] Switches
PRT[x]AG
Analog Global Bus
PRT[x] AMUX
Analog Mux Bus

LCD

Display Data
PRT[x] LCD_ COM_ SEG
Logic and
PRT[x] LCD_EN MUX
LCD Bias Bus 5

In addition, there are control signals that are dedicated for For example, to switch comparator input between two
CapSense applications as shown in Figure 31-5 above. GPIOs that are connected to the same analog global, the
Refer to the CapSense® chapter on page 397 for the usage register settings for the input select of the comparator are
of these control signals. configured to select the analog global to which the GPIOs
are connected. The DSI control signal can dynamically
The analog switches corresponding to the analog resource
select between the two GPIOs after the corresponding
blocks can be controlled only by the register settings of the
PRT[x]_BIE register has been configured.
respective ARBs.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 365

Analog Routing

31.4 Analog Resource Blocks –

Routing and Interface
The Analog Interface (ANAIF) is the interface between the
analog blocks and other PSoC systems (UDB, DSI, clock,
and decimator). The analog interface has 2 kilobytes of
memory, which stores the configuration settings of all analog
resource blocks. The configuration space is written to and
read by the PHUB. The analog interface also interfaces
clock distribution to the various analog resource blocks. For
ARBs that deal with both analog and digital signals, like the
ADC, DAC, and comparator, the analog interface connects
the digital and analog portions. For example, the comparator
output is routed to the Digital Systems Interconnect (DSI)
through the analog interface. The modulator output (digital)
is routed to the decimator through the analog interface. Sim-
ilarly, the strobe and other digital signals for the DAC are
routed through the analog interface. More details about how
the interfaces are provided by the ANAIF are given in the
individual chapters in Section F: Analog System on
page 343. The following figure shows the top level diagram
of the analog interface.

Figure 31-6. Analog Interface System Diagram

Analog
System
Block
Port
Control

ANAIF
CLK_A_DIG[3:0]
CLK_A[3:0]

AHB

All
Clocks
CLKDIST
UDB
Array Decimator PHUB

366 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Analog Routing

31.4.1 Digital-to-Analog Converter (DAC)

The DAC routing options and connections to other PSoC subsystems through the analog interface are shown in Figure 31-7.
The output for each DAC is selected by control registers that are connected to multiplexer select lines. The DAC receives
input data and control signals from the analog interface. The control signals include the strobe signal for the DAC, the reset
signal, the DAC current-off signal, and output current direction. These control signals come from UDBs or control registers.
Refer to the Digital-to-Analog Converter chapter on page 409 to learn more about DAC control and operation.

Figure 31-7. DAC Routing, Interface

Reg DAC1.SW*
Reg DAC0.SW*

AGL0 ANAIF AGR0

AGL1 AGR1
AMUXBUSL AMUXBUSR
abusl1 dac_data abusr1
dac_data
abusl3 V 8 8 V abusr3
DAC0 DAC1
P0[6] P3[0]
I dac0_cr dac1_cr I
AMUXBUSL 4 AMUXBUSR
AGL0 4 AGR0
AGL1 AGR1

Reg DAC0.SW* Reg DAC1.SW*

Reg DAC3.SW*
Reg DAC2.SW*

AGL4 AGR4
AGL5 AGR5
AMUXBUSL AMUXBUSR
abusl0 dac_data abusr0
abusl2 V 8
dac_data
8 V abusr2
DAC2 DAC3
P0[7] I P3[1]
I dac2_cr dac3_cr
AMUXBUSR
AMUXBUSL 4 4
AGL4 AGR4
AGL5 AGR5
8 4 4 4 4
dac_data_udb
Reg DAC2.SW* dac0_cr_udb dac3_cr_udb Reg DAC3.SW*
dac1_cr_udb dac2_cr_udb
dacn_cr includes strobe, reset, ioff, idir
signals
UDB

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 367

Analog Routing

31.4.2 Comparator
The comparator routing options and connections to other PSoC subsystems through the analog interface are shown in
Figure 31-8. The input for each comparator is selected by control registers, which are connected to the multiplexer select
lines.The outputs of the comparators are routed to the ANAIF for further processing (see the following figure). The analog
interface contains lookup tables (LUTs) that are used to implement logic functions on comparator outputs. The LUT outputs
(LUTN_OUT) are routed to the UDB block through the Digital System Interconnect (DSI). In addition, LUT outputs can gener-
ate interrupts (LUT_IRQ) to the device. Refer to the Comparators chapter on page 375 to learn more about comparator con-
trol and operation.

Figure 31-8. Comparator Routing, Interface

AG L0 AG R 0
AG L1 AG R 1
AG L2 AG R 2
AG L3 AG R 3
AG L4 AG R 4
AG L5 AG R 5
AG L6 AG R 6
AG L7 AG R 7
AM U XBU SL AM U XBUSR
abusl0 ANAIF abusr0
abusl1
refbufl + abusr1
refbufr
R eg C M P0.SW *, C M P0.SW * com p0 + R eg C M P1.SW *, C M P1.SW *
AG L0
AG L2 _ com p1
AG R 0
AG R 2
AG L4
AG L 6
AM U XBUSL
_ AG R 4
AG R 6
AM U XBU SR
abusl2 abusr2
abusl3 abusr3
VR EF 0 VR EF0
VR EF1 VR EF1
Reg C M P0.SW *, C M P0.SW * R eg C M P1.SW *, C M P1.SW *

AG L0 AG R0
AG L1 AG R1
AG L2 AG R 2
AG L3 AG R 3
AG L4 AG R4
AG L5 AG R5
AG R 6
AG L6
AG L 7
AM UXBU SL
+ AG R 7
AM U XBUSR
abusl0 com p3 abusr0
abusl1
refbufl + _ abusr1
refbufr
R eg C M P2.SW *, C M P2.SW *
com p2 Reg C M P3.SW *, C M P3.SW *
AG L1
AG L3
AG L5
_ AG R 1
AG R 3
AG R 5
AG L7 AG R 7
AM U XBUSL AM U XBU SR
abusl2 4 4 4 4 4 4 4 4 abusr2
abusl3 abusr3
VR EF0 VREF0
VR EF1 VR EF 1
R eg C M P 2.SW *, CM P2.SW * R eg C M P3.SW *, C M P3.SW *
LUT0 LUT1 LUT2 LUT3

U DB

368 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Analog Routing

31.4.3 Delta Sigma Modulator (DSM)

The Delta Sigma modulator (DSM) is part of the Delta Sigma ADC and consists of various blocks that are mentioned in the
Delta Sigma Converter chapter on page 417. The DSM can select its clock from any of the four analog clocks. The decimator
block and the synchronization circuit in the ANAIF use the clock, CLK_DEC, which is selected from the corresponding digitally
aligned analog clocks. The DSM output DSM0_DOUT and the overload detect status bits are routed to the ANAIF block for
post processing. DSM also receives the reset signals and modulation signal from the analog interface. These control signals
may originate from UDBs and or from control registers. Refer to the Delta Sigma Converter chapter on page 417 to learn
more about the control and operation of this block.

Figure 31-9. DSM Routing, Interface

AGL0 dsm0_startup_reset_udb
AGL1
AGL2 dsm0_startup_reset
dsm0_modbitin_udb
AGL3
AGL4
dsm0_extclk_cp_udb
AGL5
AGL6
8 dsm0_dout_udb
AGL7
abusl0
dsm0_dout
abusl2 8
VSSA dec_irq
dsm0_overload
Reg DSM0.SW* DSM _one
ANAIF dsm0_dout2scomp 4
UDB
AG1L
dsm0_overload Decimator dec_start
AG3L
AG5L
_zero
AG7L
AMUXBUSL
dec_clk
abusl1
abusl3
dsm0_clk
VREF dsm0_reset_dec
VSSA dsm0_modbitin

dsm0_extclk_cp_udb
Reg DSM0.SW*

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 369

Analog Routing

31.4.4 Switched Capacitor

The switched capacitor block provides various analog functions. It has a modulator output SCN_MODOUT, which is routed to
a register and is also routed to the UDB array as SCN_MODOUT_SYNC (Figure 31-10). The four analog clocks and the cor-
responding digitally aligned clocks, as well as the UDB generated clock, are selectable for each switched capacitor block
instance. The interrupt signal corresponding to the switched capacitor blocks (SC_IRQ) is also routed to the UDB array. The
polarity of the dynamic control input, SC_DYN_CNTRL, switches the amplifier between the inverting and non-inverting config-
uration. Refer to the Switched Capacitor/Continuous Time chapter on page 345 to learn more about SC/CT.

Figure 31-10. Switched Capacitor Routing, Interface

AGL1 AGR1
AGL3 AGR3
AGL5 AGR5
AGL7 AGR7
abusl1 abusr1
abusl3 abusr3
SC1O Reg SC1.SW*
Reg SC0.SW*
SC0O
AGL0 AGR0
AGL2
AGL4
ANAIF AGR2
AGR4
AGL6 SC0 SC1 AGR6
VREF VREF
abusl0 abusr0
SC1O SC0O
Reg SC0.SW* Reg SC1.SW*

AGL0 AGR0
AGL1 AGR1
AGL2
sc0_modout sc1_modout AGR2
AGL3 AGR3
AGL4 sc0_dyn_cntl sc1_dyn_cntl AGR4
AGL5 AGR5
AGL6 sc0_clk sc1_clk AGR6
AGL7 AGR7
AMUXBUSL AMUXBUSR
abusl0 abusr0
abusl2 abusr2
abusl3 abusr3
VREF VREF
SC1O SC0O
Reg SC0.SW*
Reg SC1.SW*
AGL0
AGR0
AGL2
AGR2
AGL4
AGR4
AGL6
AGR6
abusl0 SC2O SC3O abusr0
abusl2
abusr2
Reg SC3.SW*
AGL1
Reg SC2.SW*
SC2 SC3 AGR1
AGL3 AGR3
AGL5 AGR5
AGL7 AGR7
VREF VREF
abusl1 abusr1
SC3O sc2_modout sc3_modout SC2O
Reg SC2.SW* Reg SC3.SW*
sc2_dyn_cntl sc3_dyn_cntl AG0R
AG0L
AG1L sc2_clk AG1R
sc3_clk AG2R
AG2L
AG3L AG3R
AG4L AG4R
AG5L AG5R
AG6L AG6R
AG7L AG7R
AMUXBUSL AMUXBUSR
abusl1 abusr1
abusl2 abusr2
abusl3 abusr3
VREF VREF
SC3O SC2O
Reg SC2.SW* 4 Reg SC3.SW*
sc_irq 4
sc_dyn_cntl sc_clk_udb sc_modout_sync

UDB

370 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Analog Routing

31.4.5 Opamp
The input and output routing options for the output buffer (opamp) are shown in Figure 31-11. Refer to the Opamp chapter on
page 379 for details on configuration and operation of this block.

Figure 31-11. Opamp Input/Output Routing

Reg ABUF0.SW* Reg ABUF1.SW*

Reg ABUF0.SW* Reg ABUF1.SW*

P0[3] P3[4]

AGL4 AGR4
AGL6 AGR6
Reg ABUF0.MX* Reg ABUF1.MX*

AGL4 Opamp0 Opamp1 AGR4

AGL5 AGR5
AGL6 AGR6
AGL7 AGR7
VREF VREF
abusl0 P0[1] P3[6] abusr0
abusl1 abusr1
abusl2 Reg ABUF0.SW* Reg ABUF1.SW* abusr2
abusl3 abusr3
Reg ABUF0.MX* Reg ABUF1.MX*
Reg ABUF0.SW* Reg ABUF1.SW*
P0[2] P3[5]

Reg ABUF2.SW* Reg ABUF3.SW*

Reg ABUF2.SW* Reg ABUF3.SW*

P0[5] P3[2]

AG5L AGR5
AG7L AGR7
Reg ABUF2.MX* Reg ABUF3.MX*

AGL4 Opamp2 Opamp3 AGR4

AGL5 AGR5
AGL6 AGR6
AGL7 AGR7
VREF VREF
abusl0 P0[0] P3[7] abusr0
abusl1 abusr1
Reg ABUF2.SW* Reg ABUF3.SW* abusr2
abusl2
abusl3 abusr3
Reg ABUF2.MX* Reg ABUF3MX*
Reg ABUF2.SW* Reg ABUF3.SW*
P0[4] P3[3]
= Analog Switch

31.4.6 Low Pass Filter (LPF)

Two tunable low pass filter blocks are available. The inputs are selectable in a 2:1 mux for each LPF as shown in
Figure 31-12. On the left side, the LPF inputs are AMUXBUSL and AGL0. On the right side, the inputs are AMUXBUSR and
AGR0. The outputs are connected through switches to abusL0 and abusR0, respectively. The tunability of the LPF allows the
user to select an R of either 1 M or 200 k, and a C of either 5 pF or 10 pF. The LPF control registers are LPF0_CR0 and
LPF1_CR0.

Figure 31-12. LPF Routing

AMUXBUSL AMUXBUSR
ABUSL0 ABUSR0
IN0 OUT0 OUT1 IN1 AGR0
AGL0
LPF0 LPF1

LPF0.CR0 LPF1.CR0

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 371

Analog Routing

31.5 Low Power Analog Routing For example, assume we want to connect P3.5 to P3.4 in a
simple pass-through configuration. This is illustrated
Considerations Figure 31-12. This illustration is taken from the full chip dia-
Figure 31-2 illustrates the analog global routing network, gram shown in Figure 31-2. P3.5 enters the chip on analog
overlaid on top of the ARBs. Each ARB has a set of muxes global AG5. P3.4 enters the chip on analog global AG4. To
and switches that it uses to connect to the global analog connect these two pins together we need to Track Jump
routing. By connecting to one of the analog routing channels between AG4 and AG5. To do this we can use the Compar-
virtually any ARB can be connected to any other ARB or pin ator ARBs comp1 positive input switches (assuming the rest
on the chip. of our project isn't using these switches). The switch for AG4
and AG5 on the Comparator comp1 positive input is closed,
Not all pins or ARBs are connected to every analog global while the rest of the switches remain open. The inputs to the
routing channel. To get a signal from a particular ARB out to Comparator ARB itself are isolated from the switch group via
a specific pin, the PSoC Creator analog routing algorithm a transmission gate.
implements a technique known as “Track Jumping”. Track
jumping connects two analog globals together via one of the Once this configuration is programmed into the device, any
ARBs analog global switching structures, without connecting signal seen on P3.5 will show up on P3.4.
to that particular ARB resource.
Figure 31-13. Simplified diagram of routing P3.5 to P3.4 Using Track Jumping on the Positive Input of Comparator 1.

P3.5
COMPARATOR
P3.4

com p1

input offs et
cancelation
AG 7

AG 6

AG 5
AG4

31.5.1 Mitigating Analog Routes with chosen by using the manual routing components in PSoC
Degraded Low Power Signal Creator, the designer must make certain to avoid routing
which uses the SC/CT block for track jumping purposes if
Integrity the SC/CT is not enabled in Hibernate/Sleep modes.
The analog router in PSoC Creator uses track jumping to
If a design utilizes SC/CT analog switches to realize a
connect analog globals together. Track jumping is done on
design, in Sleep/Hibernate modes but has this block pow-
the muxes/switches of unused ARBs. The auto-router in
ered down, significant degradation in signal integrity may be
PSoC Creator will always choose routes which ensure sig-
experienced. Explicitly Start() components derived from the
nal integrity in all power modes.
SC/CT block and leave on in Hibernate/Sleep if it is neces-
If the auto-router is not sufficient and the designer needs to sary to still use these switches to route the design. Not start-
resort to manual routing techniques to realize a design, then ing the ST/CT block is equivalent to stopping it. By starting
special care should be taken. For performance reasons, the this block its routing resources become available for routing.
SC/CT ARB controls the availability of all of its associated See the PSoC Creator Data Sheet associated with Manual
analog switches. Routing for more details on how to use the MARS tool.

A designer can modify which analog routes are chosen by

using the Manual Analog Routing (MARS) tool to force the
routes. If the designer modifies which analog routes are

372 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Analog Routing

31.6 Analog Routing Register Summary

Table 31-2. Analog Routing Register Summary
Name Brief Description
{PRT[0..11]_AMUX}
These registers control the connection between the analog mux bus and the corresponding GPIO pin
{PRT15_AMUX}
{PRT[0..11]_AG}
These registers control the connection between the analog global buses and the corresponding GPIO pin. Port 12 is
{PRT12_AG}
the SIO port and the PRT12_AG register is for SIO reference selection.
{PRT15_AG}
{CMP[0..3]_SW0} Comparator positive input to analog globals 0-7
{CMP[0..3]_SW2} Comparator positive input to analog local bus
Comparator positive input to AMUXBUS and reference buffer
{CMP[0..3]_SW3}
Comparator negative input to AMUXBUS and VREF

{CMP[0..3]_SW4} Comparator negative input to analog globals 0-7

{CMP[0..3]_SW6} Comparator negative input to analog local bus
{CMP[0..3]_CLK} Comparator sampling clock selection and clock control register
{DSM0_SW0} Delta Sigma modulator positive input to analog globals 0-7
{DSM0_SW2} Delta Sigma modulator positive input to analog local bus
Delta Sigma modulator positive input to AMUXBUS and VSSA
{DSM0_SW3}
Delta Sigma modulator negative input to AMUXBUS, VSSA, and VREF

{DSM0_SW4} Delta Sigma modulator negative input to analog globals 0-7

{DSM0_SW6} Delta Sigma modulator negative input to analog local bus
{DSM0_CLK} Delta Sigma modulator clock selection
{DAC[0..3]_SW0} DAC voltage output to analog globals 0-7
{DAC[0..3]_SW2} DAC voltage output to analog local bus
DAC voltage output to AMUXBUS
{DAC[0..3]_SW3}
DAC current output to AMUXBUS and direct to pad
{DAC[0..3]_SW4} DAC current output to analog globals 0-7
{DAC[0..3]_SW6} DAC current to analog local bus
{DAC[0..3]_STROBE} DAC strobe selection
{SC[0..3]_SW0} Switched capacitor (SC) positive input to analog globals 0-7
{SC[0..3]_SW2} SC positive input to analog local bus
SC positive input to AMIUXBUS and VREF
{SC[0..3]_SW3}
SC negative input to AMUXBUS and VREF

{SC[0..3]_SW4} SC negative input to analog globals 0-7

{SC[0..3]_SW5} SC negative input to analog globals 8-15
{SC[0..3]_SW6} SC negative input to analog local bus
{SC[0..3]_SW7} SC output to AMUXBUS, other SC negative and positive inputs
{SC[0..3]_SW8} SC output to analog globals 0-7
{SC[0..3]_SW10} SC output to analog local bus
{SC[0..3]_CLK} SC clock selection
{ABUF[0..3]_MX} These registers select positive and negative inputs to the output buffer.
These registers control the switch between the output and negative input, the switch between the output and GPIO,
{ABUF[0..3]_SW}
the switch between the negative input and GPIO, and the switch between the positive input and GPIO.
{LUT[0..3]_CR} These registers select the signals to comparator LUT and also select the LUT function.
{LCDDAC_SW[0:4]} These registers select the signals on the LCD bias bus.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 373

Analog Routing

Table 31-2. Analog Routing Register Summary (continued)

Name Brief Description
{BUS_SW0} This register controls the switches that tie AGR[7:0] to AGL[7:0].
{BUS_SW2} This register controls the switches that tie abusL[7:0] to abusR[7:0] (left and right analog local bus) lines together.
{BUS_SW3} This register controls the switch that ties AMUXBUSR to AMUXBUSL.
{LPF0_CR0}
LPF registers
{LPF1_CR0}

374 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 32. Comparators

PSoC® 3 and PSoC® 5 devices each have four analog comparator modules. The positive and negative inputs to the compar-
ators come through muxes with inputs from analog globals (AGs), local analog bus (ABUS), Analog Mux Bus (AMUXBUS),
and precision reference. The output from each comparator is routed through a synchronization block to a two-input Lookup
Table (LUT). The output of the LUT is routed to the UDB Digital System Interface (DSI). The comparator can also be used to
wake the device from sleep. An ‘x’ used with a register name denotes the particular comparator number (x = 0 to 3).

32.1 Features
PSoC® comparators have the following features:
■ Flexible input selection
■ Speed power tradeoff
■ Optional 10 mV input hysteresis
■ Low input offset voltage (<1 mV)
■ Glitch filter for comparator output
■ Sleep wakeup

32.2 Block Diagram

Figure 32-1 on page 376 is a block diagram of PSoC Comparators.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 375

Comparators

Figure 32-1. Comparator Block Diagram

A G L0 AGR0
A G L1 AGR1
A G L2 AGR2
AGL3 AG R 3
A G L4 AGR4
A G L5 AGR5
A G L6 AGR6
AGL7 AG R 7
AM UXBUSL A M U XB U SR
abusl0 A N A IF abusr0
abusl1
refbufl + abusr1
refbufr

R eg C M P0 .SW *, C M P0.S W * com p0 + R eg C M P 1.SW *, C M P1.SW *

A G L0
A G L2 _ com p1
AGR0
AGR2
AGL4
AGL6
AM UXBUSL
_ AGR4
AGR6
AM UXBUSR
abusl2 abusr2
abusl3 abusr3
VREF0 VREF0
VR EF 1 V R E F1
R eg C M P 0.S W *, C M P 0.S W * R eg C M P 1 .SW *, C M P1.SW *

AGL0 AGR0
AGL1 AGR1
AG L2 AGR2
AG L3 AGR3
AGL4 AGR4
AGL5 AGR5
AGR6
AG L6
AG L 7
A M U XB U SL
+ AGR7
AM U X BU S R
abusl0 com p3 abusr0
abusl1
refbufl + _ abusr1
refbufr
R eg C M P 2.S W *, C M P 2.S W *
com p2 R eg C M P 3.S W *, C M P 3.S W *
A G L1
A G L3
A G L5
_ AGR1
AGR3
AGR5
A G L7 AGR7
AM UXBUSL AM UXBUSR
abusl2 4 4 4 4 4 4 4 4 abusr2
abusl3 abusr3
VREF0 V R EF 0
V R E F1 VREF1
R eg C M P 2.S W *, C M P 2.SW * R eg C M P 3.S W *, C M P 3.S W *
LU T 0 LU T 1 LU T2 LU T 3

UDB

32.3 How it Works 32.3.2 Power Configuration

The following describes the operation of PSoC comparators. The comparator can operate in three power modes – fast,
slow, and ultra low power. The power mode is configured
using power mode select (SEL[1:0]) bits in the comparator
32.3.1 Input Configuration
control (CMPx_CR) register.
Inputs to the comparators are as follows:
Power modes differ in response time and power consump-
■ Positive – from analog globals, analog locals, analog tion; power consumption is maximum in fast mode and mini-
mux bus, and comparator reference buffer. Refer to the mum in ultra low power mode. Exact specifications for
CapSense® chapter on page 397. power consumption and response time are provided in the
■ Negative – from analog globals, analog locals, analog datasheet.
mux bus, and voltage reference.

All of the possible connections to the positive and negative 32.3.3 Output Configuration
inputs are shown in Figure 32-1. Inputs are configured using Comparator output can pass through an optional glitch filter.
registers CMPx_SW0, CMPx_SW2, CMP_SW3, The glitch filter is enabled by setting the filter enable (FILT)
CMP_SW4, and CMP_SW6. bit in the control (CMPx_CR[6]) register. The output of the
comparator is stored in the CMP_WRK register and can be
read over the PHUB interface.

376 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Comparators

Four LUTs in the device allow logic functions to be applied 32.3.5 Wake Up from Sleep
to comparator outputs. LUT logic has two inputs:
The comparator can run in sleep mode and the output used
■ Input A – selected using MX_A[1:0] bits in LUT control
to wake the device from sleep. Comparator operation in
(LUTx_CR1:0) register
sleep mode is enabled by setting the override
■ Input B – selected using MX_B[1:0] bits in LUT Control (PD_OVERRIDE) bit in the control (CMPx_CR[2]) register.
(LUTx_CR5:4) register

The logic function implemented in the LUT is selected using 32.3.6 Comparator Clock
control (Q[3:0]) bits in the LUT Control register (LUTx_CR) Comparator output changes asynchronously and can be
register. The bit settings for various logic functions are given synchronized with a clock. The clock source can be one of
in Table 32-1. the four digitally-aligned analog clocks or any UDB clock.
Table 32-1. Control Words for LUT Functions Clock selection is done in mx_clk bits [2:0] of CMP_CLK
Control Word register. The selected clock can be enabled or disabled by
Output (A and B are LUT Inputs)
(Binary) setting or clearing the clk_en (CMP_CLK [3]) bit. Compara-
0000 FALSE(‘0’) tor output synchronization is optional and can be bypassed
0001 A AND B by setting the bypass_sync (CMP_CLK [4]) bit.
0010 A AND (NOT B)
0011 A 32.3.7 Offset Trim
0100 (NOT A) AND B
Comparator offset is dependent on the common mode input
0101 B voltage to the comparator. The offset is factory trimmed for
0110 A XOR B common mode input voltages 0.1V and Vdd - 0.1V to less
0111 A OR B than 1 mV. If the user knows the common mode input range
1000 A NOR B at which to operate the comparator, a custom trim can be
1001 A XNOR B done to reduce the offset voltage further.
1010 NOT B
The Comparator offset trim is performed in the CMPx_TR0
1011 A OR (NOT B) register. This register has two trim fields, trim1
1100 NOT A (CMPx_TR0[3:0]) and trim2 (CMPx_TR0[7:4]). If shorting of
1101 (NOT A) OR B the inputs is desired for offset calibration, the calibration
1110 A NAND B enable field (cal_en) in the control register(CMP_CR[4])
1111 TRUE (‘1’) helps to achieve it

The method for a custom trim is described as follows:

The output of the LUT is routed to the digital system inter-
face of the UDB array. From the digital system interface of 1. Set the two inputs ‘inn’ and ‘inp’ to the desired value.
the UDB array, these signals can be connected to other 2. Change the trim1 register settings:
blocks in the device or to an I/O pin. a. Depending on the polarity of the offset measured, set
or clear trim1 [3] bit.
The state of the LUT output is indicated in the LUT output
b. Increase the value of trim1 [2:0] until offset measured
(LUTx_OUT) bit in the LUT clear-on-read sticky status
is less than 1 mV.
(LUT_SR) register and can be read over PHUB interface.
3. If the polarity of the offset measured has changed, but
The LUT interrupt can be generated by all four LUTs and is the offset is still greater than 1 mV, use trim2 [3:0] to fine
enabled by setting the LUT mask (LUTx_MSK) bit in the tune the offset value. This is valid only for the slow mode
LUT mask (LUT_MSK) register. of comparator operation.
4. If trim1 [2:0] is 07h, and the measured offset is still
32.3.4 Hysteresis greater than 1 mV, set or clear trim2 [3], depending on
the polarity of offset. Increase the value of trim2 [2:0]
For applications that compare signals very close to each until the offset measured is less than 1 mV.
other, hysteresis helps to avoid excessive toggling of the
comparator output when the signals are noisy.

The 10 mV hysteresis level is enabled by setting the hyster-

esis enable (HYST) bit in the control (CMPx_CR5) register.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 377

Comparators

32.3.8 Register Summary

Table 32-2 is a summary listing of applicable registers.

Table 32-2. Registers

Register Function
CMPx_SW0 Configures connection between positive input and analog globals 0-7
CMPx_SW2 Configures connection between positive input and analog locals 0-1
CMPx_SW3 Configures connection between analog mux bus to the two inputs and the voltage reference to negative input, CapSense®
reference buffer to the positive input
CMPx_SW4 Configures connection between negative input and analog globals 0-7
CMPx_SW5
CMPx_SW6 Configures connection between negative input and analog locals 0-1
CMPx_TR0 Trims the offset. Two groups of 4-bits for lower and higher end of common mode input ranges.
CMP_WRK Stores the output state of the comparator
CMPx_CLK These registers enable and disable synchronization of the output for comparators and the clock signal for synchronization
CMPx_CR These registers are used to select the mode of operation of the comparator between the high speed and low speed modes
and to enable/disable the comparator channel
LUTx_CR Selects the input(s) and function for the LUT
LUT_SR Stores the status of LUT outputs. It’s a clear on read register.
LUT_MSK Enables interrupt request for a particular LUT output

378 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 33. Opamp

PSoC® 3 and PSoC® 5 devices have four operational amplifiers. An ‘x’ used with register name identifies the particular
opamp number (x = 0 to 3).

33.1 Features
PSoC® operational amplifiers have the following features:
■ 25 mA current drive capability
■ 3 MHz gain bandwidth for 200 pF load
■ Offset trimmed to less than 0.5 mV
■ Low noise
■ Rail-to-rail to within 50 mV of Vss or Vdda for 1 mA load
■ Rail-to-rail to within 500 mV of Vss or Vdda for 25 mA load
■ Slew rate 3 V/µs for 200 pF load

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 379

Opamp

33.2 Block Diagram

Figure 33-1 is the PSoC operational amplifiers block diagram.
Figure 33-1. Operational Amplifiers Showing Available Connections

OPAMP0.SW[0] OPAMP1.SW[0]

OPAMP0.SW[1] OPAMP1.SW[1]
P0[3] P3[4]

AGL4 AGR4
AGL6 AGR6

OPAMP0.MX[4] OPAMP1.MX[4]

AGL4 OPAMP0 P0[1] P3[6]

OPAMP1 AGR4
AGL5 AGR5
AGL6 AGR6
AGL7 AGR7
VREF VREF
abusl0 abusr0
abusl1 abusr1
abusl2 abusr2
abusl3 abusr3

OPAMP0.MX[3:0] OPAMP1.MX[3:0]

P0[2] P3[5]
OPAMP0.SW[2]
OPAMP1.SW[2]
OPAMP2.SW[0] OPAMP3.SW[0]

OPAMP2.SW[1] OPAMP3.SW[1]
P0[5] P3[2]

AGL5 AGR5
AGL7 AGR7

OPAMP2.MX[4] OPAMP3.MX[4]

AGL4 OPAMP2 P0[0] P3[7]

OPAMP3 AGR4
AGL5 AGR5
AGL6 AGR6
AGL7 AGR7
VREF VREF
abusl0 abusr0
abusl1 abusr1
abusl2 abusr2
abusl3 abusr3

OPAMP3.MX[3:0]
OPAMP2.MX[3:0]
P0[4] P3[3]
OPAMP2.SW[2] = analog switch OPAMP3.SW[2]

33.3 How it Works

PSoC 3 and PSoC 5 devices have up to four operational ABUFx_MX[3:0], is used to select an input from an inter-
amplifiers. The opamps are configurable as a unity gain buf- nal signal.
fer, to drive high current loads or as an uncommitted opamp. ■ Negative – The negative input analog switch, controlled
For example, a DAC output or voltage reference can be by bit ABUFx_SW[1], selects an input from an external
buffered using an opamp to drive a high current load. pin. The negative input mux, controller by bit
ABUFx_MX[3:0], selects an input from an internal signal.
33.3.1 Input and Output Configuration
The opamp output is connected directly to a fixed port pin.
The positive and negative inputs to the operational amplifier
can be selected through muxes and analog switches. A mux 33.3.2 Power Configuration
is used to connect an analog global, local analog bus, or ref-
erence voltage to an input, and an analog switch is used to The opamp can operate in three power modes – low,
connect a GPIO to an input. This is shown in Figure 33-1. medium, and high. Power modes are configured using the
Inputs are: (PWR_MODE[1:0]) power mode bits in the (OPAMPx_CR
[1:0]) control register. The slew rate and gain bandwidth are
■ Positive – The positive input analog switch, controlled
maximum in high power mode and minimum in low power
by bit ABUFx_SW[2], is used to select an input from an
mode. Refer to the device datasheet for gain bandwidth and
external pin. The positive input mux (controlled by bits
slew rate specifications in various power modes.

380 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Opamp

33.3.3 Buffer Configuration

The opamp is configured as a unity gain buffer by closing
the feedback switch, using the OPAMPx_SW [0] bit. Setting
the OPAMPx_SW[0] bit internally connects the output termi-
nal to the negative opamp input.

33.3.4 Register Summary

Table 33-1 summarizes applicable registers.

Table 33-1. Registers

Register Function
Controls positive input switch, negative input switch and
OPAMPx_SW
feedback switch.
OPAMPx_MX Selects the internal signal for positive and negative input.
OPAMPx_CR Configures the power mode.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 381

Opamp

382 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 34. LCD Direct Drive

The PSoC® Liquid Crystal Display (LCD) drive system is a highly configurable peripheral that allows the PSoC device to
directly drive a broad range of LCDs. The flexible power settings allow this peripheral to be used in applications where a bat-
tery is the power source.

34.1 Features
Key features of the PSoC LCD system are:
■ LCD panel direct drive
■ Type A (standard) and Type B (low power) waveform support
■ Wide LCD bias range support (2 V to supply voltage)
■ Static, 1/3, 1/4, and 1/5 bias voltage levels
■ Internal bias voltage generation
■ Up to 62 total common and segment outputs
■ Supports up to 16 common glasses (16:1 mux)
■ Drives up to 736 total segments (16 backplane × 46 front plane)
■ 64 levels of software controlled contrast
■ Ability to move display data from memory buffer to LCD driver through direct memory access (DMA) without CPU inter-
vention
■ Adjustable LCD refresh rate from 10 Hz to 150 Hz
■ Ability to invert LCD display for negative image
■ Various LCD driver drive modes, allowing power optimization

34.2 LCD System Operational Modes

PSoC 3 and PSoC 5 LCD architecture contains two operation modes.
■ LCD always active
■ LCD low power

LCD always active mode is used when the device is not in low power mode and when the LCD does not need to be opera-
tional in device low power mode.

LCD low power mode is used when the LCD needs to be operational while the device is in low power mode. This uses the
same LCD always active system, but with some additional hardware.

The LCD drive system doesn't work when the chip is placed in hibernate mode.

The details of both modes are discussed in the following sections.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 383

LCD Direct Drive

34.3 LCD Always Active

A complete functional LCD always active drive system is formed using the following major blocks:
■ Dedicated LCD hardware
❐ LCD DAC
❐ LCD driver
❐ LCD bias generator
■ System resources
❐ DMA
❐ Clocks: global
❐ RAM
❐ Universal digital block (UDB)
Figure 34-1. LCD Always Active System

Analog Global Bus

Bias Select
System Resources (LCDDAC.CR0[1:0])
Contrast Control LCD DAC
Dedicated LCD (LCDDAC.CR1[5:0])
Component Hardware Continuous Drive
(LCDDAC.CR0[3])

Drive/LCD CLK/Frame/ LCDDAC.SW

Mode[2:1] 0/1/2/3/4
Clock
UDB
V0,V1,V2,
V3,V4, GND

LCD CLK
Drive
drq
Display Frame LCD Driver Block Pin
Data DMA Mode[2:0]
LCD Bias

Port Data
LCD Bias Registers LCD CLK
RAM LCD Bias
Generator Drive
Frame LCD Driver Block Pin
Mode[2:0]
LCD Bias

Any LCD drive system requires the bias generating circuitry by setting the appropriate bits of the PRT[0..11]_LCD_EN
and system to interpret the data supplied, in order to display register. These GPIOS can be configured to act as either
correctly on the LCD. PSoC 3 and PSoC 5 contain dedi- common or segment drive pins by setting bits of
cated LCD drive hardware, which works in conjunction with PRT[0..11]_LCD_COM_SEG.
system resources. It contains a dedicated DAC that gener-
The LCD driver blocks are the final interface to the pins.
ates the five bias voltages, V0 to V4, along with ground.
Each pin capable of driving an LCD contains driver logic.
These bias voltages are distributed to all of the drivers of the
The function of this block is to select the bias level. It also
LCD-capable pins.This DAC also helps to set contrast
drives the pin, depending on the LCD refresh state, whether
control.
the pin is configured as common or segment, and the dis-
LCDs have two sets of pins: commons and segments. LCD play data.
functionality in PSoC 3 and PSoC 5 GPIOs can be enabled

384 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 LCD Direct Drive

The LCD display data resides in the system memory V4, from the LCD DAC are driven to each of the LCD
(SRAM). This display data needs to be transferred to the driver blocks.
LCD driver logic. This is done using the direct memory ■ Analog mux bus and analog local bus can be selected to
access controller (DMAC). The DMAC takes the display drive the LCD driver blocks, instead of the LCD DAC, by
data from the SRAM and loads it into the port data registers. setting the appropriate bits of the LCDDAC_SW[0...4]
The LCD driver latches this port data register value when a registers. This is useful if you require external dividers to
refresh action begins. generate the drive voltages and optimize the power by
Refreshing the LCD requires LCD state updates with accu- switching off the internal DAC. In this mode, there is no
rate timing. This is done using a configurable clock, sourced software contrast control available.
from the internal main oscillator (IMO), which feeds the UDB ■ The LCD DAC can directly drive the LCD pixel, bypass-
block. The UDB is responsible for generating all of the con- ing the LCD driver block. This is useful for driving the
trol signals required by the rest of the blocks of the LCD LCD even when the chip is put to sleep. You can do this
system. by setting the LCDDAC.CR0[3] bit, which enables the
continuous drive of the LCD DAC.
34.3.1 Functional Description
34.3.1.1.1 Contrast Control
This section provides details of the LCD DAC, LCD driver,
Contrast is controlled by varying the DAC output voltage,
UDBs, clocking, DMA, CPU, and RAM, which all contribute
V0. This can be done by setting the LCD contrast control
to generating and sequencing the driving voltage for the
register (LCDDAC_CR1[5:0]), which sets the 6-bit DAC
LCD glass.
input (D[5:0], as shown in Figure 34-2). Thus, it provides
34.3.1.1 LCD DAC 2 ^ 6 = 64 levels of contrast. Table 34-1 shows the V0 range
and step size for 3.0-V and 5.5-V supply voltage.
The LCD DAC is a 6-bit resistor ladder DAC. The LCD DAC
is responsible for contrast control and bias voltage genera- Table 34-1. LCD DAC V0 Range and Step Size
tion for the LCD drive system. When the device is put in low 3.0 V Supply 5.5 V Supply
power mode, the LCD can remain operational. During this V0 Range 2 V to 3 V 2 V to 5.5 V
low power mode, the DAC can directly drive the LCD pixel,
Step Size 27.3 mV 50 mV
bypassing the driver, thus compensating for the leakage.
This is possible in LCD low power mode, which is explained
34.3.1.1.2 Bias Ratio/Multiplex Ratio Selection
in section 34.4 LCD Low Power Mode on page 389.
Bias ratio/multiplex ratio is selected by setting the bias_sel
Figure 34-2. LCD DAC (inputs and outputs)
field of the LCDDAC_CR0 register. This sets the DAC out-
put voltages V1 to V4 as shown in Table 34-2 on page 386.

D[5:0]
pwrdn
V0
continuous drive
enable hv V1
holdb V2
lcd bias select[1:0] V3
V4

The LCD DAC generates five voltages that are driven to

LCD driver block. Important points regarding LCD DAC are:
■ All of the voltages V0 to V4 are generated using an inter-
nal resistor divider; V0 is the highest voltage and V4 the
lowest voltage. By default, the five bias voltages, V0 to

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 385

LCD Direct Drive

Table 34-2. LCD DAC Bias Select

Bias Select Input:
Multiplex Bias V0 V1 V2 V3 V4
lcd_bias_select[1:0]
b1b0 Ratio Range in Volt
11 Invalid – default to 16:1 Default to 1/5 2.0 V to supply 0.800 × V0 0.600 × V0 0.400 × V0 0.200 × V0
10 16:1 1/5 2.0 V to supply 0.800 × V0 0.600 × V0 0.400 × V0 0.200 × V0
01 8:1 1/4 2.0 V to supply 0.750 × V0 0.500 × V0 0.500 × V0 0.250 × V0
00 4:1 1/3 2.0 V to supply 0.666 × V0 0.333 × V0 0.666 × V0 0.333 × V0
00 3:1 1/3 2.0 V to supply 0.666 × V0 0.333 × V0 0.666 × V0 0.333 × V0
00 2:1 1/3 2.0 V to supply 0.666 × V0 0.333 × V0 0.666 × V0 0.333 × V0

34.3.1.2 LCD Driver Block

The LCD driver block is associated with each GPIO. The output of LCD DAC through MUX is provided to the LCD driver block
to drive the LCD glass. The architecture of the LCD driver block is shown in Figure 34-3.

Figure 34-3. LCD Driver Block

V0

hold_n_hw (global)
V1

pwrdn_n (global)
Inputs from LCD DAC V2
V3
V4
GND

com_seg
od_h (global) 1 0 1 0 1 0 1 0
(individual)
dispbInk (global) LCD Bias
LCD Bias
Generator
pwrdn_n (individual)
00 01 10 11
Disp_data (individual)
hold_n_hv (global) fr (global)

drvr_in

mode[2:0] (global)
Buffer
drive (global) bypass_en (global)
pts (global)

ESD Devices

drvr_out

386 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 LCD Direct Drive

The LCD driver contains three major blocks: Note that these buffer power modes are different than the
1. Buffer and associated control logic for power modes I/O drive modes.
2. 4:1 Output multiplexer Table 34-4. LCD Drive Modes
3. Common/Segment switches
Control Bits
Mode Drive Strength
As shown in Figure 34-3 on page 386, the LCD driver block Mode[2] Mode[1] Mode[0]
receives bias voltages V0 to V4 and GND voltage. It passes 0 0 0 High Drive Seg = 1x, com = 1x
through a set of 2:1 muxes controlled by the COM-SEG bit 0 0 1 High Drive Seg = 1x, com = 2x
of the PRT[x]_LCD_COM_SEG register. This register con-
0 1 0 High Drive Seg = 1x, com = 4x
figures the pin as either a common or segment drive pin. If
0 1 1 High Drive Seg = 2x, com = 2x
the bit is set, it configures the corresponding pin as com-
1 0 0 High Drive Seg = 2x, com = 4x
mon; otherwise, it is configured as a segment drive pin. As
1 0 1 High Drive Seg = 4x, com = 4x
shown in Figure 34-3, V4 and GND voltages are forwarded
to the next mux. If the pin is selected as a segment line, then 1 1 0 Low Drive Seg = 0.1x, com = 0.1x

V0, V2, V3, and GND are forwarded. These are the only 1 1 1 Low Drive Seg = 0.2x, com = 0.2x

voltages required at common and segment lines for any bias The LCD display size and capacitance and the application
ratio, multiplex ratio, and LCD update state. Out of these power budget are two criteria for selecting buffer modes.
four bias levels, only one level is selected by the 4:1 multi- The buffer is enabled only when the drive signal is high.
plexer. The select lines of the multiplexer are driven by dis- Drive signal high time can be configured according to the
play data and the frame signal. Frame is a global signal application requirements. The drive current provided by the
driven by the UDB control logic. This signal toggles every High Drive mode of the buffer (the mode that is normally
time the LCD waveform needs to be updated. Table 34-3 used) is high, so it charges the pixel capacitance quickly.
shows the 4:1 multiplexer output and driver input for differ- The disadvantage of this is higher power consumption. The
ent combinations of COM_SEG, DISP_DATA and the frame time for which the buffer is kept on depends on the power
signal. budget and the LCD waveform's rise time requirements. The
Low Drive mode of the buffer and the DAC are other
Table 34-3. LCD DAC Output Selection
options. It is possible to dynamically select the Low Drive
com_seg disp_data fr drvr_in/out mode by two mode control signals generated by the UDB.
0 0 0 V3 You would do this in the case of extremely leaky glasses,
0 0 1 V2 when it is preferable to use the buffer to drive the LCD con-
0 1 0 GND tinuously throughout the refresh period. This is more effec-
0 1 1 V0 tive than using the DAC, whose current drive ability is lower
1 0 0 V4 than that of the buffer Low Drive mode. Use the DAC when
1 0 1 V1 you have normal glasses and the charge leakage is small. If
1 1 0 V0
the leakage is small enough for the offset to be negligible,
then the pin can be tristated by clearing the bypass_en bit,
1 1 1 GND
after charging the pixel using the High Drive buffer mode.
34.3.1.2.1 Buffer Modes
The output of the 4:1 multiplexer is driven to the buffer,
which drives the common or segment line of the LCD. The
buffer in the LCD drive block has eight modes of operation,
selectable from the Mode[2:0] bits. Mode[0] comes from
LCDDRV_CR[1]; the remaining two bits are driven from the
UDB through the digital system interconnect (DSI).

Each mode has a different power drive capability. Depend-

ing on the LCD, the appropriate one can be used to elimi-
nate AC coupling between segment and common lines.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 387

LCD Direct Drive

In normal operation, the buffer in High Drive mode drives the Figure 34-4. The DAC Charging an LCD Segment Pin in
LCD for a while, then a low-power source (either the DAC or Two Different States
the buffer in Low Drive mode) takes over and drives the LCD
Buffer DAC
for the remaining time.
Driving LCD Driving LCD
■ When using High Drive and DAC:
Initially, for some period of time, the buffer quickly
charges the LCD pixel capacitance near to the desired Drive
value. Later, when the drive signal goes low, the DAC
directly drives the LCD for the remaining period (if the
bypass_en bit is set) to sustain the voltage at the LCD
pin. If the bypass_en bit is not set to 1, the pin is tristated t
and no source drives the LCD. This can lead to charge
leakage from the pixel capacitance.
■ When using High Drive and Low Drive: Pixel
The drive signal always remains high. This means that
Voltage
the buffer is always enabled. The UDB controls the time
for which the buffer remains in High Drive and Low Drive
modes. t
Slope depends on drive mode
of buffer selected.

34.3.1.2.2 LCD Driver Bias Generator

The LCD bias generator block creates a bandgap-based
voltage reference for the LCD driver block. The input to this
block is a 2.5-µA bandgap current. The output is a bias volt-
age and the associated ground line.

Figure 34-5 shows various control signals to the LCD driver

block.

Figure 34-5. Control Signals of LCD Driver Block

*1:4
Type A Multiplex Type B
Ratio (2x Type A Data Clock)
1/3 Bias

1 Frame 1 Frame 1 Frame

LCD Drive
Voltage Level

Display Data

Frame

LCD CLK

388 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 LCD Direct Drive

34.3.1.3 UDB To work more effectively with the DMA in transferring data to
the LCD drivers, port data registers are aliased to a sepa-
The UDB performs the following actions in the LCD system:
rate contiguous region in the memory map. These
■ Triggers the DMA periodically to bring the display data PRTx_DR_ALIAS registers are contiguous, to reduce the
from SRAM to the port data registers number of TDs required to move data.
■ Generates various control signals for the functioning of
An additional set of registers (per port), the
the LCD system hardware
PRTx_BIT_MASK registers, mask off the write capability to
❐ The drive signal, which is used to enable the driver the PRTx_DR_ALIAS registers on a bit level. This is an
buffer advantage if all of the pins on a given port are not being
❐ Two mode control signals for the buffer used for LCD; the unused pins can be masked off and used
❐ A synchronous LCD CLK, which is used to latch the for other purposes. The port data register (PRTx_DR) can
port data register value for a particular pin still be used to address pins masked off in the aliased data
❐ The frame signal registers.

The clock for the UDB is derived from the IMO. The clock
value changes with the refresh rate and the number of com- 34.4 LCD Low Power Mode
mons of LCD.
This mode is useful when LCD is required to be functional
34.3.1.4 DMA while the device is in low power mode. This requires special
hardware and firmware logic to wake the system up at regu-
DMA is used to transfer the display data into various port lar intervals, refresh the LCD, and put the device back to
data registers. The display data is stored in SRAM. Data sleep. Periodic refresh should happen at the specified rate,
transfer is initiated by the UDB at the beginning of the LCD even if there are other interrupts in the system.
refresh cycle. Depending on which and how many ports are
configured for the LCD drive, several transaction descriptors LCD low power mode uses all the of components that are
(TDs) associated with the DMA channel may need to be used for LCD always active mode. In addition to this, it also
chained together. uses a programmable wakeup source and small dedicated
digital logic to allow bug-free transitions to and from the low
There is no separate display memory, as such, in PSoC. power mode. Figure 34-6 on page 390 shows the block dia-
Display data resides in the SRAM connected to the periph- gram for the LCD low power mode.
eral hub (PHUB). The image/display buffer can be any block
of available memory.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 389

LCD Direct Drive

Figure 34-6. LCD Low Power Mode

System Resources Analog Global Bus

Bias Select
Dedicated LCD (LCDDAC.CR0[1:0])
Component Hardware Contrast Control LCD DAC
(LCDDAC.CR1[5:0])
LCDTIMER_CFG[1] Continuous Drive
(LCDDAC.CR0[3])
1-kHz ILO
CLK LCD INT
LCD Timer Clock UDB LCDDAC.SW
8-kHz OPPS Drive / LCD CLK / Frame /
0/1/2/3/4
Mode[2:1] / LP_ACK
V0,V1,V2,
V3,V4, GND

Frame 0x01 LCD CLK

LCD CLK
Data DMA drq
Drive
0x00 LCD Driver
nrq Frame Pin
Block
Mode[2:0]
drq LCD Bias
Display .
Data . DMA
. .. .
. .
.

LCD Bias LCD CLK

LCD Bias
RAM Generator Port Data Drive
Registers LCD Driver
Frame Pin
Block
Mode[2:0]
LCD Bias

A complete functional LCD low power system is formed PSoC 3 and PSoC 5 contain several clock sources that
using these major blocks: operate during device low power mode. ILO and OPPS
■ Dedicated LCD hardware timer are examples. These clock sources are used to trigger
periodic interrupts to the device to wake the system up. As
❐ LCD timer
shown in Figure 34-6, these two clock sources are select-
❐ LCD DAC able using a mux. The selected clock is fed to the 6-bit LCD
❐ LCD driver timer. It is a continuously running timer; that is, when the
❐ LCD bias generator timer overflows, the original period is reloaded in the timer
■ System resources register. The terminal count pulse from this timer triggers the
interrupt to the chip. This restores the main clocks of the
❐ Clocks: 1-kHz ILO and 8-kHz one pulse per second
(OPPS) chip. When this happens, the interrupt signal from the LCD
timer is intercepted by the UDB-implemented pulse genera-
❐ UDB implementation for sleep acknowledgement
tor. In response, the block generates a synchronous clock
❐ DMA for frame data transfer that causes several operations. See 34.4.1.2 UDB on
❐ UDB implementation for control signal generation page 391 for more details. Overall, the UDB's role is to pro-
(frame, drive, LCD mode, LCD CLK) vide control signals to various functional blocks of the LCD
❐ DMA for display data transfer low power system.
The blocks in bold are unique to the LCD low power system. At this time, the system must be put back to sleep after the
The other blocks are same as the LCD always active LCD refresh. In an LCD low power system, the CPU issues
system. a chip low power (LP) mode command to the power man-
What makes the LCD low power system different from the agement (PM) controller. (For this, firmware needs to be
LCD always active system? structured in a specific way explained in later section.) Con-
sent is given by the LCD hardware.
■ It can wake the system
■ It can continuously drive the LCD even when the chip is This is because the LCD refresh happens in hardware and
put in low power mode CPU doesn't know when it is completed. So, a control signal
(LP_ACK signal shown in Figure 34-6) is generated from the
UDB, which keeps the LP command from the CPU on hold

390 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 LCD Direct Drive

until the LCD refresh is completed. This control signal is The source can be selected by setting the clk_sel field of the
driven to the power management controller of the device. LCDTIMER_CFG register.

There are two DMAs used in this architecture. One DMA is The clock timer provides periodic interrupts to the system
used for the transfer of display data to the port data register, PM controller. The interrupt signal is also driven to the UDB
which is the same as in an LCD always active system. the to generate the LCD CLK signal.
other DMA is used to update the frame information into the
control register of the UDB each time the chip wakes up. 34.4.1.2 UDB
LCD low power mode uses the UDB to generate various sig-
34.4.1 Functional Description nals that control the functioning of the LCD system. These
This section gives details of the blocks and features used control signals are generated using the functional blocks
specifically in LCD low power mode. listed below:
■ Pulse generator
34.4.1.1 LCD Timer ■ BGREF timer
The LCD timer is a 6-bit timer dedicated only for the LCD ■ Drive pulse-width modulator (PWM)
drive application. Its period is set based on the required ■ Control register for frame data
refresh rate of the LCD. The period of this timer can be con-
■ Mode control signals to the LCD driver
figured by setting the period field of the LCDTMR_CFG reg-
ister. There are two options for the LCD timer clock source:
■ 1-kHz ILO
■ 8-kHz OPPS. This requires that an external 32-kHz crys-
tal be connected to the system.

Figure 34-7. LCD UDB Logic

LCD CLK DMA (Frame

Pulse Generator DRQ
Data)
NRQ

BGREF Timer

Drive PWM EN

TC PWM

Drive

S
SR Q LP_ACK
Latch
R

Control Frame
Register

Const Mode [2:1]

UDB

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 391

LCD Direct Drive

The pulse generator samples the interrupt signal from the 34.4.1.4 LCD DAC and Driver: Low Power
LCD timer; in response, it generates one synchronous clock Feature
pulse (LCD CLK), which is routed to the BGREF timer and
DMA (for frame data). This synchronous clock triggers these The LCD DAC and driver have some features that are useful
operations: for LCD low power mode functioning and help to achieve the
lowest power consumption when the LCD system is shut
■ Puts the sleep command issued by CPU, if any, on hold
down.
(using signal LP_ACK) until LCD refresh operation is
completed. The LCD DAC can remain active when the chip is put in
■ Enables the BGREF timer. The BGREF timer is used to sleep mode. In this mode, the DAC can continue to drive the
provide a 2.5-µs delay, which is necessary to stabilize inputs of LCD drivers. To enable this mode, set the
the bandgap reference circuit. continuous_drive bit in the LCDDAC.CR0 register to 1. The
LCD DAC receives a pwrdn signal, which shuts the DAC off
■ Triggers the DMA to transfer the frame data into the
when it is HIGH.
UDB control register. Frame is a square wave signal that
is used for proper sequencing of LCD refresh action. The LCD driver receives a display blank signal, dispbInk,
Each cycle of the frame signal represents one common controlled by the LCDDRV.CR register. This signal sets the
update state. output to be either tristated or grounded when the chip is in
low power mode. This function works when the power down
After the DMA transfer for frame data and the BGREF time-
signal (pwrdn_n) signal is low. The pwrdn_n signal is used
out are completed, Drive PWM is enabled. The Drive PWM
when the LCD system needs to be shut down.
output “Drive” signal is routed to all the LCD driver blocks
associated with the GPIO. It enables the LCD buffer to drive The buffer present in the LCD driver can be bypassed by
the LCD glass. The UDB also provides the two signals that setting the bypass_en bit of the LCDDRV.CR register to 1.
set the drive mode of the LCD buffer.
Thus, for operation in sleep mode, for an LCD low power
system, continuous_drive, bypass_en, and pwrdn bit must
34.4.1.3 DMA
be set to 1, and pwrdn_n must be set to 0. This causes the
Two DMA channels are used by the LCD component for: DAC to directly drive the LCD, bypassing the LCD driver
■ Transferring the frame information into the control regis- section, which is shut down in chip low power mode.
ter of the UDB from the system memory (RAM) The various operating modes of the LCD DAC and LCD
■ Transferring the display information from system mem- driver are summarized in Table 34-5 and Table 34-6 on
ory (RAM) into the port register page 393.

Table 34-5. LCD DAC Operating Modes

Chip Mode Block Mode pwrdn_n continuous_drive Description
Active Active 1 X LCD DAC is active. It can drive I/Os or LCD drivers depending on the LCD driver mode.
Sleep with
Sleep 0 1 LCD DAC is active and driving I/Os even though the chip is in sleep. LCD drivers are bypassed.
bypass drive
Active/
Sleep/ OFF 0 0 LCD DAC is powered down
Hibernate

392 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 LCD Direct Drive

Table 34-6. LCD Driver Operating Modes

Chip Mode Block Mode pwrdn_n dispbInk Drive bypass_en Description
Active Active drive 1 X 1 X LCD driver is driving the pin in one of the High Drive or Low Drive modes.
Active with
Active 1 X 0 1 LCD driver is bypassed. LCD DAC is driving the I/O.
bypass drive
Active with
Active 1 X 0 0 LCD driver is active but the I/O is tristated.
tristate drive
Off with LCD driver is powered down. LCD DAC is in sleep with bypass drive mode and driv-
Sleep 0 0 X 1
bypass drive ing the I/O.
Active/
Off with LCD driver is powered down. Output is grounded. This is the power down mode for
Sleep/ 0 1 X X
ground drive LCD applications. LCD DAC is off.
Hibernate
Active/
Off with LCD driver is powered down. Output is tri-stated. This is the power down mode for
Sleep/ 0 0 X 0
tristate drive nonLCD applications. LCD DAC is off.
Hibernate

34.4.2 Timing Diagram for LCD Low Power Mode

Figure 34-8 shows the timing in low power mode.

Figure 34-8. LCD Low Power Mode Timing Diagram

ILO

LCD COUNT 1 0 P P- 1 P- 2

LCD TC

LCD INT

BUS CLOCK ( Wakeup) ( Sleep)

LCD CLK

BGREF TIMER P 0

BGREF TIMER TC

DMA Frame( current) Display Data( next)

DMA TERMOUT( Frame)

“AND”
PWM( DRIVE_EN)

PWM TC

LP_ ACK

A refresh timer overflow triggers an interrupt to the PM sys- pleted and the BGREF timer overflows, the LCD drive buffer
tem and also drives the UDB pulse generator logic. After a is enabled using the drive signal from the Drive PWM. This
few microseconds, system clocks are restored. This puts all is when LCD glass refresh begins. The drive mode of the
of the resources on the chip in operation. The UDB-imple- LCD drive buffer determines the current drive. After the drive
mented pulse generator outputs an LCD CLK pulse, which: time is set, the drive line goes low, disabling the buffer. This
■ Triggers the DMA to transfer frame information into the also releases the sleep command hold set by the LCD CLK.
control register of the UDB This causes PM to execute the sleep command issued by
the CPU. During the rest of the period, the LCD is driven
■ Enables the BGREF timer (implemented using UDB)
continuously from the LCD DAC, bypassing the driver buffer.
■ Copies the display data from the port data register into
the driver for the present LCD state Figure 34-9 on page 394 shows the sequence of operations
and relative current consumption for low-power mode.
■ Clears the refresh rate timer interrupt
■ Puts the sleep command from the CPU on hold

After the frame information transfer, another DMA is trig-

gered to transfer the display data into the port data register
for the next LCD state. When the frame data transfer is com-

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 393

LCD Direct Drive

Figure 34-9. LCD Sequence of Operation

Chip Wake Up from NOT TO SCALE

LCD Source

Chip Power Active

Mode
Sleep Sleep

D E
DMA Track

Main/CPU Track A B C H

F G
Analog Track
End LCD
Drive Pulse
(LCD lp_ack
Turn On Asserts)
CPU and
Bus Clock
Begin LCD
Chip Drive Pulse
Transition
Relative into Active
Current Mode Turn On Chip
Consumption LCD DAC Transition
and Bias to Sleep
Generator Mode

0 1 2 3
Power
Phase

Main/CPU Track
A) Chip wake up process
B) ‘Main’ execution: Check for interrupts, request sleep
C) Power Manager (PM) asserts low power request (lp_req) to all
subsystems and waits for all acknowledge signals (lp_ack) to assert
H) PM Completes Active -> Sleep Mode transition

DMA Track
D) DMA TD: Update FR value
(must complete before starting ‘G’)
E) DMA TD: Setup Display Data for next LCD refresh cycle

Analog Track
F) LCD DAC and LCD bias generator power up (2.5 µs)
(must complete before starting ‘G’)
G) “Drive” pulse

394 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 LCD Direct Drive

34.5 LCD Usage Models

The LCD can be used in these cases:
■ The chip is always maintained in active mode. The LCD
driver buffer will drive in high drive mode for the speci-
fied time; later on, it will switch back to low drive mode.
This mode can be used when the system is always on
and a power saving feature is not needed. This uses
LCD always active mode.
■ The chip enters low power mode and the LCD does not
need to function. Disable the entire LCD system before
putting the device to low power mode. This also uses
LCD always active mode.
■ The chip enters low power mode and the LCD must be
functional. In this situation, the background LCD refresh
timer allows the chip to be put to sleep and awakened at
regular intervals to refresh the LCD glass. This system
uses LCD low power mode. There are restrictions in
refresh rates due to the low frequency clock used for the
LCD timer.
Table 34-7 shows the allowed refresh rate values for this
case:

Table 34-7. Refresh Rate Limits

ILO ECO
Commons
Max Min Max Min
2 125 21 128 32
4 125 21 128 32
8 63 21 128 20
16 31 - 128 20

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 395

LCD Direct Drive

396 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 35. CapSense®

PSoC® 3 and PSoC® 5 devices have a capacitive sensing feature called CapSense®. This feature allows users to take
advantage of the capacitive properties of their fingers to toggle aesthetically superior buttons, sliders, and wheels. Touch
pads and touch screens are common examples of capacitive sensing interfaces. The underlying principle of these technolo-
gies is the measurement of capacitance between a plate (the sensor) and its environment.

35.1 Features
Features of CapSense include:
■ Resources to support two capacitive sensors scanning simultaneously
■ Configurable low pass filter to remove switching noise for accurate measurement
■ Reference buffer with High Drive mode for faster measurement

35.2 Block Diagram

A block diagram of the overall capacitive sensing architecture is shown in Figure 35-1.

Figure 35-1. CapSense Module Block Diagram

I/O Pins I/O Pins

I/Os Reference Reference I/Os

(Left Side) Driver Driver (Right side)

AGL<0> AGR<0>
UDBs
AMUXBUSL AMUXBUSR

MUX MUX

LPF LPF
V-I DAC V-I DAC
Comparators Comparators

System Bus

LEFT SIDE RIGHT SIDE

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 397

CapSense®

35.3 How It Works connected to a large off-chip capacitor serving as integration

or modulation capacitor.
The PSoC device has configurable hardware for CapSense
to optimize factors such as speed, power, sensitivity, noise 35.3.4 GPIO Configuration for CapSense
immunity and resource usage. It implements CapSense
Sigma Delta (CSD) method of capacitive sensing. The GPIO switching structure supporting CapSense is
shown in Figure 35-2.
35.3.1 Reference Driver Figure 35-2. GPIO Structure
This driver is used to quickly initialize nets to a voltage inde-
pendent of the power supply. This ability speeds up capaci-
tive scanning and improves Power Supply Rejection Ratio Vdd

AMUXBUSx
(PSRR). Two reference drivers operate independently; one
drives to AMUXBUSL, and one for AMUXBUSR. The driver
is connected to the AMUXBUS by setting the out_en bit in
the {CAPSx_CFG0}.

The reference driver supports Normal and High drive

modes; the drive mode is selected using the boost bit in the
{CAPSx_CFG0} register. In Normal mode, capacitances up
to 100 pF can be driven in less than 600 ns. In High mode,
capacitances up to 30 nF can be driven in less than 15 µs.

35.3.2 Low Pass Filter

Two tunable Low Pass Filter (LPF) blocks are available. The
inputs are selectable in a 2:1 mux for each LPF. On the left
side, the LPF inputs are AMUXBUSL and AGL[0]; on the The port analog global mux register (PRT[x]_AMUX) is used
right side, the inputs are AMUXBUSR and AGR[0]. LPF to connect the port pin to the analog mux bus. The pull up or
input is selected by using the swin[1:0] bits in the LPFx.CR0 pull down is enabled using io_ctrl[1:0] bits in the
register. The outputs are connected through switches to CAPSx_CFG1 register.
abusl[0] and abusr[0], respectively. The tunability of the LPF
Sense capacitance is switched in two configurations, shown
allows the user to select a (nominal) R of either 200 k or
in Figure 35-3 on page 399 and Figure 35-4 on page 399, to
1000 k, and a C of either 5 pF or 10 pF. The rsel and csel
convert the capacitance into equivalent resistance for mea-
bits in the LPFx_CR0 register are used to select resistance
surement.
and capacitance respectively. The LPF control registers are
LPF0_CR0 and LPF1_CR0. The equivalent resistance can be calculated as:

1
35.3.3 Analog Mux Bus R s = --------------
 fs Cs 
All GPIO pins support CapSense operations except SIO and
USB pins. The primary analog mux bus for CapSense is the Here:
AMUXBUS, which has two nets (AMUXBUSL and AMUX- Cs=Sensor Capacitance
BUSR) for two simultaneous sensing operations. These can
also be shorted to form a single net that connects to all 1 and 2 = Non-overlapping clocks, which may be config-
GPIO. Refer to the device datasheet for details about ured in a pseudo random sequence (PRS).
GPIOs available in each package and to the Analog fs = Frequency of the clock
Routing chapter on page 359 for a diagram of AMUXBUS
connectivity for the GPIO. Cmod = External Modulation Capacitance

AMUXBUSL and AMUXBUSR nets connect to all GPIO pins The CapSense methods can generally be done with either
on their respective halves of the device. CapSense uses the switching high or switching low at the GPIO pin. The rest of
AMUXBUS net, along with an analog global net (AGR[0] the hardware is configured with the appropriate polarity to
with AMUXBUSR, and AGL[0] with AMUXBUSL) to provide match to the pull up or pull down choice.
feedback to the reference driver. This feedback is from a pin

398 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 CapSense®

Figure 35-3. Charging MUXBUS Through Sense Resistor

Vdd Vdd

AMUXBUSx

AMUXBUSx
1 RS
2

CS

Figure 35-4. Discharging the MUXBUS Through Sense Resistor

AMUXBUSx

AMUXBUSx
2

CS 1
RS

The CapSense clock is used for switching. Two alternatives GPIOs pins can be made as Shield Electrodes. The shield
are available to generate the CapSense clock (refer also to electrodes help in reliable operation in presence of water
Figure 21-1 on page 188). film or water droplets. The effect of these factors on shield
■ The UDB generates two global clocks (caps_dsi_lft and electrode is measured and is removed from the CapSense
caps_dsi_rt), and routes to GPIO logic of the I/O pins in Buttons. The CapSense algorithms discussed below sup-
the respective side. The PRT[x]_CAPS_SEL[y] registers port the shield electrode.
(per port per pin basis) are set to select the global clock
for switching the sensor during measurement. 35.3.5 Other Resources
■ The DSI output to the I/O pin can be used to source the CSD CapSense techniques use many resources in PSoC 3
CapSense clock from the UDB. The PRTx_BIE[y] must and PSoC 5 devices. These include UDBs, Comparators,
be programmed for input (per port per pin basis) and and V-I DAC. See the Universal Digital Blocks
PRT[x]_CAPS_SEL[y] is cleared to select the DSI output (UDBs) chapter on page 213, Comparators chapter on
signal for the CapSense clock. page 375, and Digital-to-Analog Converter chapter on
With either of these paths, the nonoverlapping clock phases page 409 for more detail on those.
discussed above are automatically generated within the
GPIO switching structure.

Note that to connect an external integration capacitance

(Cmod) statically (without switching), connect it to AMUXBUS
using PRT[x]_AMUX register and then PRTx_CAPS_SEL[y]
= 0 and PRTx_BIE[y] = 0.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 399

CapSense®

35.4 CapSense Delta Sigma 3. As the integration capacitor voltage moves back and
forth across the comparator threshold, the comparator
Algorithm high outputs are counted in an interval to give a measure
of the sense capacitor.
The CapSense Delta Sigma (CSD) algorithm shown in
4. The sense capacitance increases with touch, therefore
Figure 35-5 and Figure 35-6 on page 401 measures capaci-
equivalent resistance decreases. This decreased resis-
tance with the hardware configured like a Delta Sigma mod-
tance causes an increase in the current flowing through
ulator. Delta Sigma capacitive sensing operates by holding switch CapSense resistor.
an integration capacitor voltage near a target threshold, and
5. To maintain the voltage on Cmod near VREF during a
charging or discharging the capacitor, based on the present
touch, the IDAC sinks current for longer duration to com-
state of a comparator output. The sense capacitor is contin-
pensate for the larger sense capacitance. This changes
uously switched between Vdd and the integration capacitor,
the count value accordingly.
which drives the integrated voltage up on each switching
cycle. The CSD algorithm operates as follows: A PRS (pseudo random sequence) clock may be used
instead of a fixed clock source to drive the precharge
1. When the integration voltage reaches the reference volt-
age, the comparator enables current DAC to discharge switches. The PRS clock produces less radiated noise on
the capacitor. the sense capacitor, compared to a fixed clock source,
hence improving EMI and interference performance.
2. When the capacitor voltage discharges below the refer-
ence voltage, the current DAC is disabled to allow the
capacitor to continue charging.
Figure 35-5. CSD Hardware Configuration

VDD
UDB

1 PRSCLK Prescale
and PRS
2

CS IDAC En

Vin UDB
LPF UDB
Vmod
Initialize D Q
C MOD Ref Counter
AMUXBUS

Driver
Vref
C

UDB
CounterClock
Prescale

400 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 CapSense®

Figure 35-6. CSD Waveform

CMOD
Voltage

Comp Out
when No
Touch

Smaller count

Comp Out
when
Finger is
present
Larger Count

The PSoC device also supports other variants of the CSD

algorithm as follows:
■ Switched Capacitor Resistor (see Figure 35-3 on
page 399) is used to charge the integration capacitor; an
external bleeding resistor is used (instead of IDAC) to
discharge the integration capacitor, based on compara-
tor output.
■ Polarities are reversed so that the IDAC is used to
charge up the integration capacitor and Switched
Capacitor Resistor (see Figure 35-4 on page 399) dis-
charges the integration capacitor toward ground, based
on comparator output.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 401

CapSense®

402 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 36. Temperature Sensor

The PSoC® 3 and PSoC® 5 devices have an on-chip Temperature Sensor that is used to measure the internal die tempera-
ture. The temperature sensor uses the Delta Vbe method for digital temperature measurement.

The temperature sensor block has an auxiliary analog-to-digital converter (ADC) for measuring the internal die temperature.
The auxiliary ADC is a 10-bit accurate ADC in the system performance controller (SPC) primarily designed for measuring
temperature sensor output but can also be used for general purposes supplementing the main Delta-Sigma ADC. It is also
possible to route the analog output of diode in temperature sensor block to analog globals to measure temperature more
accurately using the Delta-Sigma ADC in PSoC 3.

36.1 Features
The temperature sensor offers the following features:
■ ± 5 degrees Celsius accuracy over commercial temperature range (-50ºC to +150ºC)
■ Ability to route temperature sensor output to analog global line, AGL3.

36.2 Block Diagram

The block diagram for the temperature sensor is illustrated in Figure 36-1.

Figure 36-1. Temperature Sensor

Temperature Sensor Core

Switch Network (Sequencer + Mode Select)

Digital
Parallel Current Paths To AGL3 Temperature

Vbe
Auxiliary
Curvature ADC
Temperature
Compensation
Diode
Circuit

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 403

Temperature Sensor

36.3 How It Works 36.4 Command and Status

The base-to-emitter voltage of a Bipolar Junction Transistor Interface
(BJT) device has a strong dependence on temperature at a
The commands associated with the temperature sensor are
constant collector current and zero collector-base voltage.
executed through the simple command/status register inter-
The temperature sensor output (Vbe) is measured with two
face. “Get Temp,” “Setup Temperature Sensor,” and “Dis-
different drive currents: first with low bias current and sec-
able Temperature Sensor” are commands associated with
ond with high bias current. A current ratio of 1:29 is main-
the temperature sensor. The command is sent as a series of
tained between the conversions.
bytes to either SPC_CPU_DATA or SPC_DMA_DATA,
By making the ratio between the two drive currents high, the depending on the source of the command. Response data is
voltage difference between the Vbe values is linearly pro- read via the same register to which the command was sent.
portional to temperature. The output voltage of the tempera- The status register, SPC_SR, indicates whether a new com-
ture sensor is either driven to the Delta Sigma ADC or other mand can be accepted, when data is available for the most
on-chip resources using analog global line (AGL3). To recent command, and success/failure response (status
increase accuracy, the PSoC 3 and PSoC 5 temperature code) for the most recent command.
sensors use the following techniques:
Table 36-1. Command Registers
■ Dynamic Element Matching technique is implemented
using a sequencer that cyclically selects among the Register Size (Bits) Description

eight current mirror paths during conversion (low current SPC_CPU_DATA 8 Data to or from CPU

mode and high current mode). SPC_DMA_DATA 8 Data to or from DMAC

■ Curvature compensation circuit to increase linearity Status – ready, data available, status
SPC_SR 8
code
when the temperature sensor output is routed to an
external resource with a High Z buffer such as the on-
The command sequence consists of a 2-byte key, followed
chip Delta Sigma ADC.
by command code and the parameters associated with the
■ A two point linear fit calibration routine for accurate tem- command.
perature measurements using the Auxiliary ADC.
■ Key byte #1 – always 0xB6
■ Key byte #2 – 0xD3 plus the command code (ignore
overflow)
■ Command code byte
■ Command parameter bytes
■ Command data bytes

Before sending a command to the SPC_CPU_DATA or

SPC_DMA_DATA register, the SPC_Idle bit in SPC_SR[1]
must be ‘1’. SPC_Idle will go to ‘0’ when the first byte of a
command (0xB6) is written to a DATA register, and then go
back to ‘1’ when command execution is complete or an error
is detected. Commands sent to either DATA register while
SPC_Idle is ‘0’ are ignored.

404 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Temperature Sensor

36.4.1 Status Codes 36.4.2 Temperature Sensor Commands

If the value of the 2-byte key is wrong or if any of the param-
36.4.2.1 Get Temperature
eters passed are invalid, the command is ignored and the
error condition is indicated by the status code in the Status “Get Temperature” (command code: 0x0E). This command
register (SPC_SR). The Status_Code bits (7:2 in the Status uses auxiliary ADC to measure the die temperature and the
register) are used to determine if the command operation is ADC output. It returns 2 bytes corresponding to a tempera-
executed successfully or any error occurred. Table 36-2 lists ture value. The first byte is the sign of the temperature (0 =
the status code bit values. negative, 1 = positive). The second byte is the magnitude.
These values are read from the SPC Data register. The
Table 36-2. Status Code Bit Values command sequence is shown in Figure 36-2.
Status_Code Bit Values
Description
(Bits[7:2] in SPC_SR register)
0x00 Command successfully executed
0x02 Invalid key
0x0B Invalid command code
0x0D Invalid parameter
Temperature Sensor Vbe is currently
0x0E
driven to an external device

Figure 36-2. Get Temperature Command Sequence

2 -B y te K e y C o m m a n d P a ra m e te r B y te s

0 x B 6 0 x E 1 0 x 0 E n u m S a m p

C o m m a n d C o d e
0 x D 3 + C o m m a n d C o d e

Command Parameters

numSamp. This parameter specifies the number of sam-

ples taken. The number of samples is equal to 2^numSamp.
Valid values for this parameter are 0, 1, 2, 3, 4, or 5, thereby
resulting in 1, 2, 4, 8, 16, or 32 samples, respectively. The
ADC output is read after the averaging has been done over
all the samples as specified by this parameter. The averag-
ing routine can be bypassed by selecting the numSamp
value as 0.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 405

Temperature Sensor

Reading Temperature Output

Once the command and its parameters are sent, the Temperature Sensor/ADC block is configured and starts the conversion.

When the conversion is complete, the DATA READY bit in the Status register (SPC_SR) is set. The CPU must poll this bit to
check if the ADC output is ready. When the bit is high, the first byte (Sign byte) of output is read from the Data register
(SPC_CPU_DATA). The DATA READY bit is reset once a read operation is done. When the second byte (Magnitude byte) is
ready to read, the DATA READY bit becomes high once again and the second byte is read from the Data register
(SPC_CPU_DATA).

36.4.2.2 Setup Temperature Sensor

“Setup Temperature Sensor” (command code: 0x11). The purpose of this command is to connect the raw temperature sensor
analog output onto AGL3 for measurement by the High Z buffer/Delta Sigma ADC(DSM) or other external resources. The
auxiliary ADC cannot be operated at the same time when the sensor output is routed to AGL3. This command disables the
functionality of the auxiliary ADC such that it does not load the sensor when the sensor output voltage is being driven into the
DSM or other external ADCs. The “Setup Temperature Sensor” and “Disable Temperature Sensor” are the commands asso-
ciated with this purpose and drive the temperature sensor output to AGL3. When temperature sensor output is routed to an
analog global line, auxiliary ADC cannot be used to measure the temperature.

Note that AGL3 should not be used by analog blocks other than the temperature sensor output when this command is exe-
cuted. Even though PSoC Creator™ takes care of routing, the user must ensure that there are no resource conflicts in using
AGL3. The command sequence is shown in Figure 36-3.

Figure 36-3. Setup Temperature Command Sequence

2-Byte Key Command Parameter Bytes

Sequence Sequence Curvature Compensation

0xB6 0xE4 0x11 clkDivider
Select Freeze Enable

Command Code
0xD3 + Command Code

406 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Temperature Sensor

Command Parameters 36.4.2.3 Disable Temperature Sensor

Sequence Select. The temperature sensor output (Vbe) “Disable Temperature Sensor” (Command code: 0x12). This
voltage is measured with low bias current and then with high command is used to disable the temperature sensor from
bias current. A current ratio of 1:29 is established between driving its output voltage to the analog global line (AGL3).
the low bias and high bias current. This ratio is fixed and not After calling this command, the “Get Temp” command can
configurable.The difference between the two output volt- be executed, as well as commands using the erase portion
ages is linearly proportional to temperature. of the Smart Write algorithm. This command has no param-
eters and does not return any value. The command
■ 0 – Low bias current.
sequence is shown in Figure 36-4.
The temperature sensor is driven with low bias current.
■ 1 – High bias current. Figure 36-4. Disable Temperature Command Sequence
The temperature sensor is driven with high bias current. 2-byte Key

Sequence Freeze. In low bias and high bias current

0xB6 0xE5 0x12
modes, Dynamic Element Matching (DEM) is implemented
by a sequencer that cyclically selects among the eight cur-
rent mirror paths. Command
0xD3 + Command Code
Code
■ 0 – Sequencer is enabled.
■ 1 – Sequencer is disabled.
No cycling of the current paths occurs.

clkDivider. This parameter sets the divider value for clock

generation from the SPC clock (spcCLK, which is 36 MHz).
This clock is used by the sequencer to cycle through the
current mirrors. The clock frequency is equal to:

spcCLK
------------------------------------------
- Equation 1
 clkDivider + 1
The clock divider value (clkDivider) is of 8 bits allowing clock
to have 256 different frequencies ranging from spcCLK
down to spcCLK/256 (spcCLK is 36 MHz). In general, the
slower the clock, the better the linearity that will be
achieved.

Curvature Compensation Enable. The temperature sen-

sor has a feature to correct for a curvature in its behavior
and align it to a more linear path, thus giving it more accu-
racy when its output is routed to an external resource with a
High Z buffer, such as the on-chip Delta Sigma ADC. A High
Z buffer is required because the curvature compensation cir-
cuit needs to be buffered before driving an external ADC
front end.
■ 0 – No curvature compensation is used.
■ 1 – Curvature compensation is enabled.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 407

Temperature Sensor

408 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 37. Digital-to-Analog Converter

The Digital-to-Analog (DAC) Converter is an 8-bit digital-to-analog converter that is configured to output either a voltage or a
current. The 8-bit DAC supports CapSense®, power supply regulation, and waveform generation.

37.1 Features
The DAC has the following features:
■ Adjustable voltage or current output in 255 steps
■ Programmable step size (range selection)
■ Eight bits of calibration to correct ± 25% of gain error
■ Source/sink option for current output
■ Output rate for current IDAC output: 8 Msps
■ Output rate for VDAC voltage output: 1 Msps
■ Monotonic in nature

37.2 Block Diagram

A block diagram of the DAC is shown in Figure 37-1.

Figure 37-1. DAC Block Diagram

ISOURCE Range
1x, 8x, 64x

Reference
Scaler Vout Iout
Source
R

3R

ISINK Range
1x, 8x, 64x

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 409

Digital-to-Analog Converter

37.3 How It Works

This DAC generates either a voltage or a current output. It is also be done using a UDB input. UDB control for the source-
built using current mirror architecture; current is mirrored sink selection is enabled using the DACx_CR1[3] bit.
from a reference source to a mirror DAC. Calibration and
value current mirrors are responsible for the 8-bit calibration 37.3.2 Voltage DAC
[DACx_TR] and the 8-bit DAC value. The current is then
diverted into the scaler to generate the current correspond- When used as a VDAC, the output is an 8-bit digital-to-ana-
ing to the DAC value. The DAC value can either be given log conversion voltage to support applications where refer-
from the register DACx_D or from 8 lines from the UDB. This ence voltages are needed. Here the reference source is a
selection is made using the DACx_CR1[5] bit. Using the voltage reference from the Analog reference block called
UDB to write the DAC value uses the DAC bus. Since there VREF(DAC). The DAC can be configured to work in voltage
is only one DAC bus available for each device, this bus must mode by setting the DACx_CR0 [4] register. In this mode,
be shared by all the DACs in the device. there are two output ranges selected by register
DACx_CR0[3:2].
The DAC is strobed to get its output to change for the input
■ 0V to 1.024 V
code. The strobe control is enabled by the
■ 0V to 4.096 V
DACx_STROBE[3] bit. The strobe sources for the DAC can
be selected from the bus write strobe, analog clock strobe to Both output ranges have 255 equal steps.
any UDB signal strobe. This selection is done on the basis
of setting in DACx_STROBE[2:0]. The VDAC is implemented by driving the output of the cur-
rent DAC through resistors and obtaining a voltage output.
■ Current (IDAC) Mode – The two mirrors for the current
Because no buffer is used, any DC current drawn from the
source and sink provide output as a current source or
DAC affects the output level. Therefore, in this mode any
current sink, respectively. These mirrors also provide
load connected to the output should be capacitive.
range options in the current mode.
■ Voltage (VDAC) Mode – The current is routed through The VDAC is capable of converting up to 1 Msps. In addi-
resistors according to the range and voltage across it tion, the DAC is slower in 4V mode than 1V mode, because
provided as output. the resistive load to Vssa is 4 times larger. In 4V mode, the
VDAC is capable of converting up to 250 ksps.
The output from the DAC is single-ended in both IDAC and
VDAC modes. 37.3.3 Output Routing Options
37.3.1 Current DAC Output routing options for the DAC are attained through two
separate muxes for current and voltage modes. These
When used as an IDAC, the output is an 8-bit digital-to-ana- muxes are controlled by the DACx_SWx registers, as shown
log conversion current. This is done by setting the in Figure 37-2 on page 411.
DACx_CR0 [4] register. The reference source is a current
reference from the analog reference called IREF(DAC). In
this mode, there are three output ranges selected by regis-
ter DACx_CR0 [3:2].
■ 0 to 2.048 mA, 8 µA/bit
■ 0 to 256 µA, 1 µA/bit
■ 0 to 32 µA, 0.125 µA/bit

For each level, there are 255 equal steps of M/256 where
M = 2.048 mA, 256 µA, or 32 µA. In the 2.040 mA configura-
tion, the block is intended to output a current into an external
600 load.

The IDAC is capable of converting up to 8 Msps. The user

also has the option of selecting if the output is a current
source or a sink. This is done by the DACx_CR1[2] register.
The selection between source and sink for the IDAC can

410 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Digital-to-Analog Converter

Figure 37-2. DAC Interconnect

DAC Bus
(data[7:0])
Register DAC0_SWV[4:0] Register DAC1_SWV[4:0]
AGL0 DAC0_D[7:0] DAC1_D[7:0] AGR0
AGL1 AGR1
AMUXBUS AMUXBUSR
abusl1
L V V abusr1
abusl3 DAC0 DAC1 abusr3
P0[6] I I P3[0]
AMUXBUSL AMUXBUSR
AGL0 AGR0
AGL1 AGR1
Register DAC0_SWI[3:0] DAC0_strobe DAC1_strobe Register DAC1_SWI[3:0]

Register DAC2_SWV[4:0] Register DAC3_SWV[4:0]

AGL4 DAC2_D[7:0] DAC3_D[7:0] AGR4
AGL5 AGR5
AMUXBUSL AMUXBUSR
abusl0 V V abusr0
abusl2 DAC3 abusr2
DAC2
P0[7] I I P3[1]
AMUXBUSL AMUXBUSR
AGL5 AGR4
AGL4 AGR5
Register DAC2_SWI[3:0] Register DAC3_SWI[3:0]
DAC2_strobe DAC3_strobe

The user can route output as follows: For example, the implementation of a 12-bit DAC using two
■ Voltage Mode – to the analog globals, analog mux bus, 8-bit DACs require:
or the analog local bus ■ One DAC scaled to the range 0 to 2.048 mA and the
■ Current Mode – to the analog globals, analog mux bus, second one scaled to the range 0 to 32 µA.
or to a specific port ■ The middle 4 bits of the lowest range DAC are used as
inputs to the lower 4 bits. See Figure 37-4 on page 412.
37.3.4 Making a Higher Resolution DAC This architecture may have problems of mismatch in the two
It is possible to achieve a higher resolution current output DACs and therefore might require adjustment and scaling.
DAC by summing the outputs of two 8-bit current DACs, The last two bits of the LSB DAC are used for minor calibra-
each one having a different segment of the input bus for tion requirements.
input. The range of the two DACs used partially overlap.

Figure 37-3. Higher Resolution DAC Example

12-Bit DAC

Input 8-Bit DAC

<0:7>
11:4 8 µA/Bit

GND 7:6

Input 8-Bit DAC

5:2
3:0 0.125 µA/Bit

Calibration
1:0
Bits

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 411

Digital-to-Analog Converter

Figure 37-4. 12-Bit DAC Using Two 8-Bit DACs Example

DAC for MSB, 8-BIT MSB

8 µA/Bit 1024 512 256 128 64 32 16 8

1 µA/Bit 128 64 32 16 8 4 2 1

1/8 µA/Bit 16 8 4 2 1 1/2 1/4 1/8

DAC for LSB, 4-BIT MSB

37.4 Register List

Table 37-1. DAC Register List
Register Name Comments Features
General Registers

DACx_CR0 DAC Control register 0 Select DAC mode, range, and speed

DACx_CR1 DAC Control register 1 Control DAC data source, reset, and direction

DACx_SW0 DAC Analog routing register 0 Routing for the DAC voltage output to analog (global) bus

DACx_SW2 DAC Analog routing register 2 Routing for the DAC voltage output to analog (local) bus

DACx_SW3 DAC Analog routing register 3 Routing for the DAC current/voltage output to AMUXBUS

DACx_STROBE DAC Strobe register DC strobe control

DACx_D DAC Data register

DACx_TR DAC Block Trim register DAC trim values

412 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 38. Precision Reference

A voltage/current reference with value independent of supply voltage and temperature is an essential building block of many
analog circuits. For example, accurate biasing voltages are critical for many circuit schemes; in ADC, a reference voltage is
required to quantify an input, while in V/I DAC, voltage/current reference is required to define the output full-scale range.

38.1 Block Diagram

The PSoC® 3 and PSoC® 5 devices have a curvature compensated voltage bandgap along with a trim buffer to get absolute
value accuracy. The trim buffer is a multiple reference generator. It takes the bandgap reference voltage as input and pro-
duces outputs ranging from 0.256V to 1.2V. The reference voltage is buffered by low power 5 A, high accuracy buffers, and
sent to multiple destinations. There is also a temperature corrected (to flat) current reference that is mirrored and sent to cur-
rent DAC.

The voltage reference block diagram is illustrated in Figure 38-1 on page 414.

38.2 How It Works

The principle of the bandgap circuit relies on two groups of diode-connected bipolar junction transistors running at different
emitter current densities. By canceling the negative temperature dependence of the PN junctions in one group of transistors
with the positive temperature dependence from a PTAT (proportional-to-absolute-temperature) circuit (which includes the
other group of transistors), a fixed DC voltage that does not change with temperature is generated.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 413

Precision Reference

Figure 38-1. Voltage Reference Block Diagram

10 µA
IREF(DAC)
Vcca
Vcca
Trim
Buffer Buffered in DSM Block
(I) Buffers 5 µA
1.2V by 10 µA Buffers
Bandgap Vcca VREF2 (DSM)
Generator (V) +_
+
_ 1.024V VREF1 (DSM) Delta Sigma ADC
+_
Vssa Vssa

+_ VREF0 (Comparator)

Vdda +_ VREF (Opamp)

BG_CR0[3]
+_ VREF (SC)
BG_CR0[2]
0
ABUSL0
1
0.9V +_ VREF (TEMP SENSOR)

0.8V
VREF1_CM (DSM)
Resistor String

Vssa

0.7V
VREF2_CM (DSM)

BG_CR0[1:0]

1
0.256V VREF1 (Comparator)
+_ 2

+_ VREF (DAC)

Vssa

Note 1 Analog supply Vdda or Vdda/2 can be routed to the analog blocks through the analog local bus, ABUSL0. The volt-
age level is selected using the BG_CR0[3] bit and the switch is enabled using the BG_CR0[2] bit.

Note 2 Reference voltage input (VREF1) to the comparator is selected using the BG_CR0[1:0] bits. It selects either bandgap
reference voltage or the analog supply voltage.

Note 3 IREF (DAC) is the reference current for the DAC during IDAC mode operation.

414 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Precision Reference

Table 38-1. Reference Voltages and Blocks

Voltage Block Value Description
VREF0 (Comparator) Comparator 1.024V To Comparator negative inputs
Vdda (or)
VREF1 (Comparator) Comparator Vdda/2 (or) To Comparator negative inputs
256 mV
VREF (Opamp) Opamp 1.024V To Opamp positive inputs
VREF (SC/CT) SC/CT Block 1.024V To SC/CT block positive and negative inputs
Comparator
Opamp
Vdda (or)
ABUSL0 DAC All blocks connected to the analog local bus ABUSL0 can get this voltage
Vdda/2
SC/CT
DSM
VREF (DAC) DAC 256 mV Reference voltage for DAC during VDAC mode operation
Reference voltage to Delta Sigma Modulator. This voltage is buffered in the DSM block by
VREF2 (DSM) DSM 1.2V
a 10 A buffer.
Reference voltage to Delta Sigma Modulator. This voltage is buffered in the DSM block by
VREF1 (DSM) DSM 1.024V
a 10 A buffer.
VREF1_CM (DSM) DSM 0.8V Common mode reference voltage for Delta Sigma Modulator
VREF2_CM (DSM) DSM 0.7V Common mode reference voltage for Delta Sigma Modulator
VREF (TEMP SENSOR) TEMP SENSOR 0.9V Analog ground option to auxiliary ADC

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 415

Precision Reference

416 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 39. Delta Sigma Converter

The PSoC® 3 and PSoC® 5 ADC is a high resolution ADC implemented in Delta Sigma technology. Delta Sigma converters
are integrating converters that provide high SNR/resolution by oversampling, noise shaping, averaging, and decimation. A
Delta Sigma Analog-to-Digital Converter (ADC) has two main components: a modulator and a decimator. The modulator con-
verts the analog input signal to a high data rate (oversampling), low resolution (usually 1 bit) bitstream, the average value of
which gives the average of the input signal level. This bitstream is passed through a decimation filter to obtain the digital out-
put at high resolution and lower data rate. The decimation filter is a combination of downsampler and a digital low pass (aver-
aging) filter that averages the bitstream to get the digital output.

39.1 Features
■ 8 - to 20-bit resolution
■ Configurable gain from 0.25 to 256
■ Differential/single ended inputs
■ Optional input buffer with RC low pass filter
■ Internal and external reference options
■ Reference filtering for low noise
■ Incremental/continuous mode
■ Gain and offset correction

39.2 Block Diagram

Figure 39-1 is the converter block diagram.

Figure 39-1. Delta Sigma Block Diagram

(From Analog Routing)

Positive
Input Mux
Input Delta Sigma
Buffer Modulator
Negative
Input Mux
High data rate (sampling rate)
low resolution bitstream in
thermometric format q[7:0]

Analog Interface
High data rate (sampling rate) low
resolution bitstream in 2's
complement (4-bit)

Decimator
24-bit Output Register High resolution (max 20 bits) low
data rate (sampling rate/
decimation ratio) output

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 417

Delta Sigma Converter

39.3 How It Works Figure 39-2. Input Buffer Structure

bypass_p
The PSoC 3, PSoC 5 Delta Sigma converter has a third-
order modulator, followed by a fourth-order decimation filter. rc
The modulator has a high impedance front end buffer fol-
lowed by a bypassable RC filter. INP A outp

■ The modulator sends out a high data rate bitstream in

thermometric format (see 39.3.2.6 Quantizer on Cfilt To Modulator
page 426). rc

■ The output of the modulator is passed on to the analog

INN A outn
interface that converts the thermometric output to two’s
complement (4 bit) and passes it on to the decimation fil-
ter.
■ The decimation filter takes 4-bit two’s complement input bypass_p
and provides a higher resolution (user selectable) output
at a lower data rate. An additional RC filtering option (DSM_BUF2[1]) is provided
A detailed description of the individual blocks and their con- for lower noise contribution from the buffer, at the cost of the
figuration options is given in this section. input voltage not settling completely. This incomplete set-
tling causes a gain error that must be corrected later, as a
part of the downstream filtering in the decimator. There is
39.3.1 Input Buffer
also an option to chop (DSM_BUF3[3]) the input and output
The input impedance of the modulator is very low and not stages of the buffer to keep the offset as low as 100 µV. The
suitable for many applications. For applications that require chopping frequency is user selectable (DSM_BUF3[2:0])
a higher input impedance, two buffers (one for each differen- and can vary from 1/2 to 1/256 of the input sampling fre-
tial input) are provided. Figure 39-2 shows the buffer and the quency. The buffer can also be operated in a low power
RC filter that follows it. mode (DSM_BUF2[0]).
The buffers are of very low noise, are independent of each The ADC (buffer) takes its inputs from analog globals, ana-
other, and can be bypassed (DSM_BUF0[1], DSM_BUF1[1]) log locals, analog mux bus, reference, and Vssa. Registers
or powered down (DSM_BUF0[0], DSM_BUF1[0]) individu- DSM_SW0, DSM_SW2, DSM_SW3, DSM_SW4,
ally by setting the bits listed in the braces. The buffer can DSM_SW6 help configure the positive and negative inputs.
also be used to amplify the input signal; it can be configured
Limit the maximum input signal amplitude to the modulator
to provide gain of 1, 2, 4 and 8 in DSM_BUF1[3:2] register
(after the buffer gain, if used) to the values in Table 39-1 for
bits. The buffer has two separate modes, selected in the
a proper operation. The values in Table 39-1 are for a
DSM_BUF0[2] bit to support a 0 to Vdd - 0.2 V input common
1.024V reference. For other reference values, scale the
mode range. The modes are:
maximum input amplitude accordingly.
■ Level Shifted – Buffer output can be level shifted up
from the input when the input is close to 0V input com- Table 39-1. Maximum Input Signal Levels (ADC Reference
mon mode voltage range. The operating range is 0 - Vref -> 1.024V)
vdda- 600 mV.
Modulator Quantization Levels
■ Rail-to-Rail – This is used when input is rail-to-rail. The Gain
operating voltage range is vssa+200 mV to vdda-200 2 Level 3 Level 9 Level
mV. 0.25 3.0000 3.5 3.5680

The input structure is illustrated in Figure 39-2. 0.5 1.5000 1.75 1.7840
1 0.75 0.875 0.892
2 0.3750 0.4375 0.4460
4 0.1875 0.2188 0.2230
8 0.0938 0.1094 0.1115
16 0.0469 0.0547 0.0558

418 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Delta Sigma Converter

39.3.2 Delta Sigma Modulator

The Delta Sigma modulator does:
■ Sampling the input signal (oversampling)
■ Optional gain by adjusting the ration of Cin1 to Cref
■ Coarse quantization (2, 3, or 9 levels/1, 1.5, or 2.2 bits)
■ Overload detection and chopping
PSoC 3, PSoC 5 Delta Sigma modulator implementation is shown in Figure 39-3.
Figure 39-3. Delta Sigma Modulator Implementation
VREF
VCM

Csumin
inp

Csum1
Cdac
o1p

Csum2 Csumfb

Cf1 Cf2 o2p

Cf3

Cin2 Cin3 Csum3

INP Cin1 o1p o2p o3p

INN INT1 INT2 INT3 Summer

o1p o2p o3p
Cin1 Cin2 Cin3 Csum3

Cf1 Cf2 Cf3

o3n
Csum2
Csumfb

o2n
Cdac
Csum1

inn
Csumin

Quantizer
b[8:0]

QLEV[1:0]

The Delta Sigma modulator consists of these subsystems:

■ Three active integrators
■ An active summer
■ A programmable quantizer
■ A switched capacitor feedback DAC

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 419

Delta Sigma Converter

A few points about the modulator: 39.3.2.2 Capacitance Configuration

■ The three active integrators and the programmable All of the capacitors shown in Figure 39-3 on page 419 have
quantizer form the third order modulator. The transfer binary weighted programmability. The value of a capaci-
function of the integrators and the quantizer together tance can be configured by setting the following three fields:
account for the high pass noise shaping. Higher the
■ Offset Capacitance – single bit that enables or disables
order of the modulator, better is the high pass filter
an offset capacitance
response and lower is the noise in the signal frequency
band. ■ Cap Array[n:0] – n+1 binary weighted bits
■ The three integrators and quantizer stages are followed ■ LSB Enable – additional unit capacitance
by an active summer. The analog input and the output of Capacitance configuration (configuration of the above fields)
all three opamp stages are summed here. is done in registers DSM_CR4 through DSM_CR12.
■ The summer output is quantized by a quantizer. The
Capacitance value is described by following equation:
quantizer is programmable to output 2, 3, or 9 levels.
■ The DAC (Vref, Vgnd and Cref constitute the DAC) con- Cap value = (offset × Coff) + (cap[n:0] × Cunit) + (EN × Cunit)
nects the quantizer output back to the first stage opamp Where:
input. It is this feedback DAC that ensures that the aver-
■ Coff is the offset capacitor value.
age of the quantizer output is equal to the average input
■ Cunit is the unit capacitor value.
signal level.
■ Offset is the binary value (single bit) programmed in the
39.3.2.1 Clock Selection offset field.
Any one of the four analog clocks or a UDB-generated clock ■ EN (LSB enable) is the binary value (single bit) pro-
can be used as the input sampling clock. The clock input grammed in the EN field.
can also be disabled. The DSM0_CLK register helps in ■ Cap[n:0] is the decimal equivalent of the binary value
selecting the clock source and enabling or disabling it. The programmed in the cap array[n:0] field.
maximum clock that can be applied to the modulator is
The unit capacitance, offset capacitance, and default values
6.144 MHz. Make certain that the clock to the decimator =
for all of the capacitances are given inTable 39-2.
fs/n, n = 2,3,4..., fs is the PHUB clock.

Table 39-2. Capacitance Values

Register Bit Description Value Default Typical Value
FCAP1OFFSET Offset cap for first stage feedback cap 3.4 pF 0
FCAP1[6:0] Binary weighted first stage feedback cap Cunit = 100 fF 1010000 8 pF
FCAP1EN Enable for LSB CAP of FCAP1 100 fF - 12.8 pF in 100 fF steps 0
IPCAP1OFFSET Offset cap for first stage input cap 4.8 pF 0
IPCAP1[6:0] First stage Input CAP (binary) Cunit = 100 fF 0101100 4.4 pF
IPCAP1EN Enable for LSB cap of IPCAP1 100 fF - 12.8 pF in 100 fF steps 0
DACCAP[5:0] DAC cap (each unit) - binary Cunit = 12 fF 101100
4.4 pF
DACCAPEN Enable for LSB CAP of DAC 12 fF - 768 fF in 12fF steps 0
RESCAP[2:0] Resonator cap (binary) Cunit = 12 fF 000
0fF
RESCAPEN Enable for LSB cap of RESCAP 12 fF - 96 fF in 12 fF steps 0
FCAP2[3:0] Second stage Feedback cap - binary Cunit = 50 fF 1011
0.55 pF
FCAP2EN Enable for LSB CAP of FCAP2 50-800 fF in 50 fF steps 0
IPCAP2[2:0] Second stage input CAP - binary Cunit = 50 fF 101
0.25 pF
IPCAP2EN Enable for LSB Cap of IPCAP2 50-400 fF in 50 fF steps 0
FACP3[3:0] Third stage feedback cap Cunit = 100 fF 1110
1.4 pF
FCAP3EN Enable for LSB Cap of FCAP3 100 fF-1.6 pF in 100 fF steps 0

420 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Delta Sigma Converter

Table 39-2. Capacitance Values (continued)

Register Bit Description Value Default Typical Value
IPCAP3[2:0] Third stage input cap Cunit = 50 fF 101
0.25 pF
IPCAP3EN Enable for LSB Cap of IPCAP3 50-400 fF in 50 fF steps 0
SUMCAPIN[4:0] Summer cap for input path Cunit = 50 fF 00101
0.25 pF
SUMCAPINEN Enable for LSB Cap of SUMCAPIN 50-1.55 pF in 50 fF steps 0
SUMCAPFB[3:0] Summer cap for feedback path Cunit = 50 fF 1010
0.5 pF
SUMCAPFBEN Enable for LSB Cap of SUMCAPFB 50-750 fF in 50 fF steps 0
SUMCAP1[2:0] Summer cap for first stage output 101
0.25 pF
SUMCAP21EN Enable for LSB Cap of SUMCAP1 0
SUMCAP2[2:0] Summer cap for second stage output Cunit = 50 fF 101
0.25 pF
SUMCAP2EN Enable for LSB Cap of SUMCAP2 50-350 fF in 50 fF steps 0
SUMCAP3[2:0] Summer cap for third stage output 101
0.25 pF
SUMCAP3EN Enable for LSB Cap of SUMCAP3 0

39.3.2.3 Gain Configuration

The modulator provides gain from 0.25 to 16 to the input sig- However, increasing only the input capacitance to increase
nal. Gain is the ratio of input and DAC capacitances, as gain disturbs the transfer characteristics of the modulator.
described in the following equation. Therefore, other capacitors also must be scaled to maintain
the modulator transfer characteristics. Recommended val-
Gain = C in  C ref Equation 1 ues of capacitors for gains of 1, 2, 4, 8 are shown in
Table 39-3, and those for 16, 0.25, and 0.5 are shown in
Table 39-4.

Table 39-3. Gains 1, 2, 4, and 8

Register Bit Gain = 1 Gain = 2 Gain = 4 Gain = 8
Bit Setting Typical Value Bit Setting Typical Value Bit Setting Typical Value Bit Setting Typical Value
IPCAP1OFFSET 0 0 1 1
IPCAP1[6:0] 010110 4 pF 1011000 8.8 pF 1111111 17.6 pF 1111111 17.6 pF
IPCAP1EN 0 0 0 1
DACCAP[5:0] 101100 101100 101100 010110
4 pF 4.4 pF 4.4 pF 2.2 pF
DACCAPEN 0 0 0 0
SUMCAPIN[4:0] 00101 01000 10000 10000
0.25 pF 0.4 pF 0.8 pF 0.8 pF
SUMCAPINEN 0 0 0 0
SUMCAPFB[3:0] 0101 1000 1000 0100
0.5 pF 0.4 pF 0.4 pF 0.2 pF
SUMCAPFBEN 0 0 0 0
SUMCAP1[2:0] 101 100 100 100
0.25 pF 0.2 pF 0.2 pF 0.2 pF
SUMCAP21EN 0 0 0 0
SUMCAP2[2:0] 101 100 100 100
0.25 pF 0.2 pF 0.2 pF 0.2 pF
SUMCAP2EN 0 0 0 0
SUMCAP3[2:0] 101 100 100 100
0.25 pF 0.2 pF 0.2 pF 0.2 pF
SUMCAP3EN 0 0 0 0

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 421

Delta Sigma Converter

Table 39-4. Gains 16, 0.5, and 0.25

Register Bit Gain = 16 Gain = 0.5 Gain = 0.25
Bit Setting Typical Value Bit Setting Typical Value Bit Setting Typical Value
IPCAP1OFFSET 1 0 0
IPCAP1[6:0] 1111111 17.6 pF 0010110 2.2 pF 0001011 1.1 pF
IPCAP1EN 1 0 0
DACCAP[5:0] 001011 101100 101100
1.1 pF 4.4 pF 4.4 pF
DACCAPEN 0 0 0
SUMCAPIN[4:0] 10000 00010 00001
0.8 pF 0.1 pF 0.05 pF
SUMCAPINEN 0 0 0
SUMCAPFB[3:0] 0010 1000 1000
0.1 pF 0.4 pF 0.4 pF
SUMCAPFBEN 0 0 0
SUMCAP1[2:0] 100 100 100
0.2 pF 0.2 pF 0.2 pF
SUMCAP21EN 0 0 0
SUMCAP2[2:0] 100 100 100
0.2 pF 0.2 pF 0.2 pF
SUMCAP2EN 0 0 0
SUMCAP3[2:0] 100 100 100
0.2 pF 0.2 pF 0.2 pF
SUMCAP3EN 0 0 0

39.3.2.4 Power Configuration

There are separate power settings for the first opamp stage, the summer, and the quantizer. The second and third stages
share the same power settings. The power for all of these stages is configured in registers DSM_CR14 and DSM_CR16. The
various configurable power settings are shown in Table 39-5.

Table 39-5. Configurable Power Settings

Register Bit Description Truth Table, Typical IDD
000 - LOW (42 µA)
001 - MEDIUM (114 µA)
010 - HIGH (430 µA)
011 - 1.5X (650 µA)
POWER1 Power control for first stage
100 - 2X (900 µA)
101 - C/2 at 3MSPS (254 µA)
110 = C/4 at 3MSPS (170 µA)
111 - 2.5X (1.35 mA)
000 - LOW (4 µA)
001 - MEDIUM (16 µA)
POWER2_3[2:0] Power control for second stage/third stage 010 - HIGH (62 µA)
011 - 1.5X (100 µA)
100 - 2X (135 µA)
000 - LOW (4 µA)
001 - MEDIUM (16 µA)
POWER_SUM[2:0] Power control for summer 010 - HIGH (62 µA)
011 - 1.5X (100 µA)
100 - 2X (135 µA)
00 - Very Low (2.2 µA)
01 - Normal (8.6 µA)
POWER_COMP[1:0] Comparator power control
10 - 6 MHz (17 µA)
11 - 6 MHz (35 µA)

422 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Delta Sigma Converter

Table 39-5 indicates how to configure power for the individual blocks. Power dissipation, capacitances, clock frequency and
quantization levels are interrelated to each other.
Configuring power without varying the other parameters mentioned above affects the proper operation of the modulator. The
tables below show a set of operational modes that indicate how to configure power based upon the other parameters or vice
versa.

Table 39-6. Power Configuration Based on Quantization Levels and Clock Frequency
Mode - 3 MHz 9 Level Mode - 6 MHz 9 Level Mode - 3 MHz 2 Level and 3 Level
Register Bit
Bit Setting Typical Value Bit Setting Typical Value Bit Setting Typical Value
FCAP1OFFSET 0 0 1
FCAP1[6:0] 1010000 8 pF 0010100 2 pF 1111110 16 pF
FCAP1EN 0 0 0
IPCAP1OFFSET 0 0 0
IPCAP1[6:0] 0101100 4.4 pF 0001011 1.1 pF 0101100 4.4 pF
IPCAP1EN 0 0 0
DACCAP[5:0] 101100 001011 101100
4.4 pF 1.1 pF 4.4 pF
DACCAPEN 0 0 0
RESCAP[2:0] 000 000 000
0fF 0fF 0fF
RESCAPEN 0 0 0
FCAP2[3:0] 1011 0001 1011
0.55 pF 0.1 pF 0.55 pF
FCAP2EN 0 0 0
IPCAP2[2:0] 101 001 101
0.25 pF 0.05 pF 0.25 pF
IPCAP2EN 0 0 0
FACP3[3:0] 1110 0011 1110
1.4 pF 0.3 pF 1.4 pF
FCAP3EN 0 0 0
IPCAP3[2:0] 101 001 101
0.25 pF 0.05 pF 0.25 pF
IPCAP3EN 0 0 0
SUMCAPIN[4:0] 00101 00001 00101
0.25 pF 0.05 pF 0.25 pF
SUMCAPINEN 0 0 0
SUMCAPFB[3:0] 1010 0010 1010
0.5 pF 0.1 pF 0.5 pF
SUMCAPFBEN 0 0 0
SUMCAP1[2:0] 101 001 101
0.25 pF 0.05 pF 0.25 pF
SUMCAP21EN 0 0 0
SUMCAP2[2:0] 101 001 101
0.25 pF 0.05 pF 0.25 pF
SUMCAP2EN 0 0 0
SUMCAP3[2:0] 101 001 101
0.25 pF 0.05 pF 0.25 pF
SUMCAP3EN 0 0 0
QLEVEL[1:0] 10 level=9 10 level=9 00 or 01 level=2 or 3
ODET_TH[4:0] 01100 12 01100 12 01100 12
FCHOP[2:0] 001 Fclk/4 001 Fclk/4 001 Fclk/4
NONOV[1:0] 01 3.5 ns 00 1.5 ns 01 3.5 ns
POWER1[2:0] 010 430 µA 010 430 µA 010 430 µA
POWER2_3[2:0] 010 62 µA 010 62 µA 010 62 µA
POWER_SUM[2:0] 010 62 µA 010 62 µA 010 62 µA
POWER_COMP[1:0] 01 9 µA 10 18 µA 01 9 µA

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 423

Delta Sigma Converter

Table 39-7. Power Configuration Based on Capacitances

Mode - C/2 Mode - C/4 Mode - C/8
Register Bit
Bit Setting Typical Value Bit Setting Typical Value Bit Setting Typical Value
FCAP1OFFSET 0 0 0
FCAP1[6:0] 0101000 4 pF 0010100 2 pF 0001010 1 pF
FCAP1EN 0 0 0
IPCAP1OFFSET 0 0 0
IPCAP1[6:0] 0010110 2.2 pF 0001011 1.1 pF 0000101 0.5 pF
IPCAP1EN 0 0 0
DACCAP[5:0] 010110 001011 000101
2.2 pF 1.1 pF 0.5 pF
DACCAPEN 0 0 0
RESCAP[2:0] 000 000 000
0fF 0fF 0fF
RESCAPEN 0 0 0
FCAP2[3:0] 0101 0001 1011
0.25 pF 0.1 pF 0.1 pF
FCAP2EN 0 0 0
IPCAP2[2:0] 010 001 101
0.1 pF 0.05 pF 0.05 pF
IPCAP2EN 0 0 0
FACP3[3:0] 0101 0011 1110
0.5 pF 0.3 pF 0.3 pF
FCAP3EN 0 0 0
IPCAP3[2:0] 010 001 101
0.1 pF 0.05 pF 0.05 pF
IPCAP3EN 0 0 0
SUMCAPIN[4:0] 00010 00001 00101
0.1 pF 0.05 pF 0.05 pF
SUMCAPINEN 0 0 0
SUMCAPFB[3:0] 0100 0010 0010
0.2 pF 0.1 pF 0.1 pF
SUMCAPFBEN 0 0 0
SUMCAP1[2:0] 010 001 101
0.1 pF 0.05 pF 0.05 pF
SUMCAP21EN 0 0 0
SUMCAP2[2:0] 010 001 101
0.1 pF 0.05 pF 0.05 pF
SUMCAP2EN 0 0 0
SUMCAP3[2:0] 010 001 101
0.1 pF 0.05 pF 0.05 pF
SUMCAP3EN 0 0 0
QLEVEL[1:0] 10 level=9 10 level=9 10 level=9
ODET_TH[4:0] 01100 12 01100 12 01100 12
FCHOP[2:0] 001 Fclk/4 001 Fclk/4 001 Fclk/4
NONOV[1:0] 01 3.5 ns 01 3.5 ns 01 3.5 ns
POWER1[2:0] 101 254 µA 110 170 µA 000 114 µA
POWER2_3[2:0] 001 16 µA 001 16 µA 001 16 µA
POWER_SUM[2:0] 001 16 µA 001 16 µA 001 16 µA
POWER_COMP[1:0] 10 18 µA 10 18 µA 10 18 µA

424 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Delta Sigma Converter

Table 39-8. Configuration Based on Power

Mode - Medium Power Mode - Low Power
Register Bit
Bit Setting Typical Value Bit Setting Typical Value
FCAP1OFFSET 0 0
FCAP1[6:0] 1010000 8 pF 1010000 8 pF
FCAP1EN 0 0
IPCAP1OFFSET 0 0
IPCAP1[6:0] 0101100 4.4 pF 0101100 4.4 pF
IPCAP1EN 0 0
DACCAP[5:0] 101100 101100
4.4 pF 4.4 pF
DACCAPEN 0 0
RESCAP[2:0] 000 000
0fF 0fF
RESCAPEN 0 0
FCAP2[3:0] 1011 1011
0.55 pF 0.55 pF
FCAP2EN 0 0
IPCAP2[2:0] 101 101
0.25 pF 0.25 pF
IPCAP2EN 0 0
FACP3[3:0] 1110 1110
1.4 pF 1.4 pF
FCAP3EN 0 0
IPCAP3[2:0] 101 101
0.25 pF 0.25 pF
IPCAP3EN 0 0
SUMCAPIN[4:0] 00101 00101
0.25 pF 0.25 pF
SUMCAPINEN 0 0
SUMCAPFB[3:0] 1010 1010
0.5 pF 0.5 pF
SUMCAPFBEN 0 0
SUMCAP1[2:0] 101 101
0.25 pF 0.25 pF
SUMCAP21EN 0 0
SUMCAP2[2:0] 101 101
0.25 pF 0.25 pF
SUMCAP2EN 0 0
SUMCAP3[2:0] 101 101
0.25 pF 0.25 pF
SUMCAP3EN 0 0
QLEVEL[1:0] 10 level=9 10 level=9
ODET_TH[4:0] 01100 12 01100 12
FCHOP[2:0] 001 Fclk/4 001 Fclk/4
NONOV[1:0] 01 3.5 ns 01 3.5 ns
POWER1[2:0] 010 114 µA 010 42 µA
POWER2_3[2:0] 010 16 µA 010 4 µA
POWER_SUM[2:0] 010 16 µA 010 4 µA
POWER_COMP[1:0] 01 9 µA 01 9 µA

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 425

Delta Sigma Converter

39.3.2.5 Other Configuration Options 39.3.2.7 Reference Options

The modulator can be chopped for a low offset of 100 µV. The Delta Sigma channel has selectable analog reference
The chopping frequency can be set from fclk/2 to fclk/256, input (REFBUF0) options, as shown in Figure 39-4 on
where fclk is the input sampling clock. Chopping enable and page 427. Also illustrated are the opamp output common
chopping frequency setting are done in the DSM_CR2 regis- mode (VCMBUF0) and the negative input buffer (REFBUF1)
ter selection schemes. The various reference selections for the
DSM ADC may be broadly classified into the following
The modulator can be configured for inverting the gain by
modes:
setting the sign bit in DSM_CR3[7].
■ Internal Reference (reference generated on-chip) that is
The modulator can be reset (all capacitances are reset) by buffered but unfiltered (Figure 39-5 on page 427)
the UDB or decimator, and the reset source is selected by
■ Internal Reference that is buffered and filtered with an
the DSM_CR2[7] register. More details about reset are in
external capacitor tied between P0[3] and ground or
the Reset chapter on page 179.
P3[2] and ground (Figure 39-6 on page 428)
39.3.2.6 Quantizer ■ External Reference source driving reference into the
DSM (Figure 39-7 on page 428)
The quantizer can be configured for 2, 3, or 9 levels. A 9
level quantizer offers a better SNR and a 2 level quantizer
offers better linearity. Depending on the application require-
ment, the user can choose quantization levels. The number
of quantization levels is configured in DSM_CR0[1:0] regis-
ter bits. The quantizer outputs data in thermometric format.
The quantizer output is stored in the register DSM_OUT1.
Thermometric format is explained by the pattern of output
levels shown in the following table. In thermometric format,
the number of ones increases from LSB to MSB as the
quantization level increases.

Table 39-9. Quantizer Output Data

Level Quantizer Output Data
2 Level Quantizer
Level 1 00000000
Level 2 11111111
3 Level Quantizer
Level 1 00000000
Level 2 00001111
Level 3 11111111
9 Level Quantizer
Level 1 00000000
Level 2 00000001
Level 3 00000011
Level 4 00000111
Level 5 00001111
Level 6 00011111
Level 7 00111111
Level 8 01111111
Level 9 11111111

426 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Delta Sigma Converter

Figure 39-4. Delta Sigma Channel Analog Reference Selection

vpwra Vcmx
(unbuffered VCM)
No Selection 00
VCMBUF0
0.8V 01
NC VCM To the opamps in the
0.7V 10
vpwra/2 DSM
11
vcm_res_div_en

vssd
en_buf_vcm
vcmsel<1:0> en_buf_vref_inn

+ To the INN Mux of the

vgnd
- Channel
S12 REFBUF1

vgnd Vpwra To the Quantizer

Resistor string
No
S13 S6
Selection 000 S5 S11
Reference of the
VDAC0L 001
vdda/4
DSM ADC (to the
010 S3 Cref branch in first
vdda/3 011 REFBUF0 integrator)
Vref = 1.024 V
100
S4 S10
from bandgap +
Vref = 1.2V 101
from bandgap - S0 S2 S7 S9
NA 110
en_buf_vref
NA 111

S1 S8
Resd1

Resd2

Resd3

Resd1

Resd2

Resd3
vdda
refmux<2:0>
vref_res_div_en

vdda/3
vdda/4

P3[2] P0[3]

vgnd

Figure 39-5. Connection Scenario: Internal Reference with No RC Filtering (using P0[3])

Vref for Quantizer

S6
S5

Vref for ADC

S3 Internal Reference
Vref Buffered Unfiltered
S4
From +
Mux
- S0 S2

S1
Res d1

Res d2

Res d3

No External Reference or
External Filtering

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 427

Delta Sigma Converter

Figure 39-6. Connection Scenario: Internal Reference with RC Filtering

S6
Vref for Quantizer
Resistor String
S5

S3
Vref S4
From +
Mux S0 S2 Vref for ADC
-
Internal reference
Buffered Filtered with
External Capacitor
S1

Res d1

Res d2

Res d3
C (External)

Figure 39-7. Connection Scenario: External Reference Only

Vref for Quantizer is the

S6 Same as the External Reference
S5

S3
Vref S4
from +
Vref is Driven by
Mux - S0 S2 an External Source

S1
Resd1

Resd2

Resd3

REFBUF0 is
Powered Down
(Output Tristated)

External Reference Input

428 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Delta Sigma Converter

There are several selectable options for internal reference, turbo power modes in the DSM_CR17 register. The com-
based on refmux[2:0] programming in DSM_REF0 register. mon mode voltage buffer, internal reference voltage buffer,
The places in the DSM block (Figure 39-3 on page 419) that and the negative input buffer are powered down, using
require a reference value are: DSM_CR17[1]; DSM_CR17[0], and DSM_REF0[3] register
■ DAC capacitor (Cref) sampling in the first integrator bits, respectively.
■ Reference for the resistive ladder inside the quantizer 1. Power on the VCMBUF0 for the DSM to function.
block 2. Turn on the reference buffer REFBUF1 only when you
want to drive the ADC reference to the negative input
■ Common Mode Voltage (VCM) for the differential cir-
mux of the DSM channel.
cuits. This voltage is typically 0.8V with an option to go to
0.7V for better head rooms. A provision for applying 3. Power down REFBUF0 only when you want to drive ref-
erence to the ADC from an off-chip source (See the
VDD / 2 is also provided.
external reference option in Table 39-10).
39.3.2.8 Reference for DSM: Usage To get low reference noise, the option to filter is provided
Guidelines with the special connections to pins P3 [2] and P0 [3], as
shown in Figure 39-4 on page 427 and Figure 39-7 on
The following table shows the state of various switches and
page 428. Therefore, for low noise floor requirements, use
the two reference buffers for certain selectable reference
the external capacitor filter. Only two pins, P3 [2] and P0 [3],
options.
are dedicated for this purpose in PSoC 3 and PSoC 5
Not every possible combination of closing the switches devices. The switches in Table 39-10 that are marked as
marked S0-S13 is discussed in this section. The configura- ON mean that the switch is closed, and a path is created for
tion of these switches (therefore the reference selection) is reference to reach DSM. Empty cells indicate that the
made in registers DSM_REF2 and DSM_REF3. The refer- switches are open.
ence buffers can be configured in low, medium, high, and

Table 39-10. Analog Reference Modes for the Delta Sigma Channel
SN Mode Switch States REFBUF0
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13
Internal Reference
1 ON ON ON ON
(No Filtering)
Internal Reference
2 ON ON ON ON ON
(Filter with P3[2])
Internal Reference
3 ON ON ON ON ON
(Filter with P0[3])
External Reference
4 ON ON OFF
only (P3[2])
External Reference
5 ON ON OFF
only (P0[3])
Vpwra is internal ref-
6 ON ON ON OFF
erence

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 429

Delta Sigma Converter

39.3.3 Analog Interface

The analog interface connects the modulator to the other blocks including the decimator and the UDB. As shown in
Figure 39-8 on page 430, the analog interface converts thermometric code sent by the modulator to two’s complement and
allows for selection of modulation input, selecting and synchronizing clocks.
Figure 39-8. Analog Interface

DSMn
vp

vn
ANALOG
dsmn_clk
dsmn_modbitin
dsmn_dout[7:0]

dsmn_startup_reset

CLK bypass_sync ANAIF

SYNC
SEL
clk_a[3:0] mx_clk[2:0] clk_en
dout_sync[7:0]
clk_a_dig[3:0]
CLK
SEL
dec_clk

dout_sat[7:0]
modbitin_en
mx_startup_reset
1 0
mx_modbitin[3:0]
tempcode_in[7:0]
TEMPCODE- qlev[1:0]
8 2SCOMP
lut_outputs[7:0]
dout2scomp[3:0]

out0[7:0]
out1[7:0]
1 0
mx_dout

dsmn_extclk_cp_udb dsmn_clk_udb
dsmn_startup_reset_udb
dsmn_dout2scomp[3:0]
dec_clk
dsmn_reset_dec

DECIMATOR dsmn_dout_udb[7:0]

dec_irq
dsmn_modbitin_udb dec_start

UDB

430 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Delta Sigma Converter

39.3.3.1 Conversion of Thermometric Code to input can be enabled by setting the DSM_CR3[4] register
Two’s Complement bit. Modulation input is selected by DSM_CR3[3:0] control
bits.
The following table shows the conversion from thermometric
format to two’s complement for 2, 3, and 9 level quantiza- 39.3.3.3 Clock Selection and Synchronization
tions performed by the analog interface. This two’s comple-
ment input is fed to the decimator. The output of the modulator (quantizer) Q[7:0] can be syn-
chronized with respect to the digitally aligned clock of the
Table 39-11. Two’s Complement Conversion Table analog clock selected for the modulator. As mentioned in
Inputs Output
39.3.2 Delta Sigma Modulator on page 419, clock selection
is done by DSM_CLK[2:0] register bits. Clock synchroniza-
qlev[1:0] dout[7:0] dout2scomp[3:0]
tion is enabled by clearing the DSM_CLK[4] register bit.

00 00000000 1111 -1
00 11111111 0001 +1
39.3.4 Decimator
The decimator takes the 4-bit input (low resolution) in two’s
01 00000000 1111 -1 complement format and converts it into a high resolution
01 00001111 0000 0 output. The 4-bit two’s complement values coming into the
01 11111111 0001 +1
decimator at the input sampling rate are averaged over a
specified number of samples (decimation ratio), down sam-
pled, and passed through an optional post-processing filter,
1x 00000000 1100 -4
achieving a higher resolution. The decimator in PSoC 3 and
1x 00000001 1101 -3
PSoC 5 devices is a fourth order Cascaded Integrator Comb
1x 00000011 1110 -2
(CIC) filter. The decimator structure is shown in Figure 39-9
1x 00000111 1111 -1 on page 432.
1x 00001111 0000 0
1x 00011111 0001 +1 39.3.4.1 Shifters
1x 00111111 0010 +2
There are two shifters in the block — one in front of the CIC
1x 01111111 0011 +3
filter and another one in front of the post processor. The
1x 11111111 0100 +4 input shift values are programmed depending on the deci-
mation ratio and quantization level to ensure that ADC
39.3.3.2 Modulation Input results are available in the Q31 format.
As discussed in 39.3.2.5 Other Configuration Options on The shift values are programmed in register DEC_SHIFT1.
page 426, modulator gain can be inverted by the sign bit in The shift values to be programmed in DEC_SHIFT1 and
DSM_CR3. The sign can also be changed by a direct digital DEC_SHIFT2 for various decimation ratios (DR1 and DR2)
input from LUTs or the UDB. The modulation input assists in and quantization levels are shown in Table 39-12 and
this process. Depending on whether the modulation input is Table 39-13 on page 432.
high or low, the gain is normal or inverted. The modulation

Table 39-12. Programmed Shifter1 Values for Various Decimation Ratios (Programmed in DR1)
Decimation Ratio Quantization Levels Max Values in Range Bit Width Shift Adjustment
8 2, 3 4095 to -4096 12 Left shift 20
8 9 16383 to -16384 14 Left shift 18
16 2,3 65535 to -65536 16 Left shift 16
16 9 262143 to -262144 18 Left shift 14
32 2, 3 1048575 to -1048576 20 Left shift 12
32 9 4194303 to -4194304 22 Left shift 10
64 2, 3 16777215 to -16777216 24 Left shift 8
64 9 67108863 to -67108864 26 Left shift 6
128 2, 3 268435455 to -268435456 28 Left shift 4
128 9 173741823 to -1073741824 30 Left shift 2

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 431

Delta Sigma Converter

Table 39-13. Programmed Shifter2 Values for Various The decimation ratios to be configured for 12, 14, 16 and 20
Decimation Ratios (Programmed in DR2) bit resolutions for 9 level quantization are shown in
Table 39-15.
Value of D2 Right Shift Value
1 No shift, bypass sync (boxcar) filter Table 39-15. Decimation Ratios for 9 Level Quantization
16 4
Final
32 5 Clock, Decimation Ratio
Resolution
64 6 12-bit 6.144 MHz, 16
128 7 14-bit 6.144 MHz, 32
256 8 16-bit 3.072 MHz, 64
512 9 20-bit 3.072 MHz, 16384 (CIC + post processor)
1024 10
39.3.4.3 Post Processing Filter
39.3.4.2 CIC Filter
The Post Processor receives 28-bit data from the output of
The CIC filter has four cascaded integrator sections operat- the CIC Decimation filter for further convenience or post pro-
ing at the modulator sample rate, followed by four cascaded cessing. Available functions are:
comb sections operating at a lower sample rate (determined
■ Add a programmable offset coefficient to the CIC result
by DR1). This combination implements a sinc4 Finite
Impulse Response (FIR) filter. The CIC filter is controlled by ■ Multiply a programmable gain coefficient to the CIC
a finite state machine that allows it to sequence events in result
the various modes of operation of the decimator. The deci- ■ Apply both offset and gain
mation ratio is programmed in the DEC_DR1 register. The ■ Apply a sinc1 FIR filter
registers in CIC filter are 32-bits wide and, therefore, for
■ Apply both a sinc1 filter and offset correction
proper operation, the decimation ratio should not exceed the
values given in Table 39-14. ■ Apply both a sinc1 filter and gain correction
■ Apply all three
Table 39-14. Maximum Decimation Ratio Values for CIC
When more than one of the three functions is enabled to
Level Bit Width Encoding (Decimal) Max Allowed
operate concurrently on the data, they are always performed
2 32 -1, 1 256
in the order: FIR > Offset > Gain. The decimator process is
3 32 -1, 0, 1 215 shown in Figure 39-9.
9 32 -4, -3, -2, -1, 0, 1, 2, 3, 4 152

Figure 39-9. Decimator

Sample
Data From
Shifter1

Modulator Sample
CIC - Decimation Data Out of
Decimator
Post Processor
Shifter2

FIR
Offset Gain

Decimation Post
Ratio DR1 Processor
Enabled

Decode of Which
PP Features
are Enabled

432 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Delta Sigma Converter

The offset value to be added is programmed in registers ■ Offset Value (write protected) – protected on writes so
DEC_OCOR, DEC_OCORM, and DEC_OCORH. The 24-bit that the underlying hardware does not incorrectly use
offset is given in signed two’s complement format. The reg- the field when it is partially updated by the system soft-
isters are coherency interlock protected (see 39.3.5 Coher- ware.
ency Protection on page 433). ■ Output Sample Value (read protected) – protected on
The gain correction coefficient is programmed in registers reads so that the underlying hardware does not update it
DEC_GCOR, DEC_GCORH. The number of bits that are when partially read by the system software or DMA.
valid in the above register is programmed in the Depending on the configuration of the block, not all bits
DEC_GVAL[3:0] register bits. This allows use of a part of of the output sample register are of interest.
the 16-bits for gain correction. The registers are coherency The coherency methodology allows for any size output field
interlock protected. If the gain feature is used, the value pro- and handles it properly. In the COHER register, coherency is
grammed into the DR1 register (CIC decimation ratio) can- both enabled, and a Key Coherency Byte is selected. The
not be smaller than 2+2*GVAL, allowing time for the Key Coherency Byte allows the user to tell the hardware
hardware to do a shift-add multiple during the decimation which byte of the field will be written or read last when an
period. update to the field is desired. Each for the three protected
The FIR filter is a summer that implements the sinc1 filter. It fields has a Coherency Interlock Flag (CIF). This flag signi-
is used in cases where decimation ratios greater than 128 fies whether the field is coherent.
are desired. When the FIR function is enabled, the Post Pro- The coherency hardware understands both 8-bit and 16-bit
cessor sums samples from the CIC filter, DR2 at a time, accesses and when tracking coherency, handles each
where DR2 (10 bits) is the decimation ratio programmed in appropriately. A hard or soft reset sets all CIF to coherent.
the DEC_DR2, DEC_DR2H[1:0] registers.
Gain correction, offset correction, and FIR filtering features 39.3.5.1 Protecting Writes (Gain/Offset) with
can be enabled and disabled in the DEC_CR[6:4] register Coherency Checking
bits. The Post Processor implements saturation logic that Starting from a coherent state (CIF is set), the software can
prevents over- and under-flow wraparound in the accumula- write any of the other non-key bytes. This action flags the
tor. If the DEC_CR[7] bit is set, the ALU does not wrap when field incoherent (clears the CIF). When a field is incoherent,
the most positive or negative number is exceeded. it is ignored by the underlying hardware, and a shadow reg-
The output of the conversion is stored in registers OUT- ister containing the last valid value is used. The field
SAMP, OUTSAMPM, and OUTSAMPH. In some configura- remains flagged incoherent until the Key Coherency Byte is
tions of the block, output results of interest are placed in bits written. At this time, the field is flagged coherent (CIF is
23:8 of the output sample field. To allow reading such val- again set), and the next time the hardware needs the field
ues in one bus cycle, an alignment feature is added to shift value, the new value is used, and the shadow register is
the result right by 8 bits. This feature is enabled by the updated with the new value.
OUTPUT_ALIGN bit of the DEC_SR register.
39.3.5.2 Protecting Reads (Output Sample)
39.3.5 Coherency Protection with Coherency Checking
Starting from a coherent state (CIF is set), the software can
Coherency refers to the hardware added to a block to pro-
read any of the other non-key bytes of the field. This action
tect against malfunctions of the block in cases where regis-
flags the field incoherent (clears the CIF). When a field is
ter fields are wider than the bus access, leaving intervals in
incoherent, it is protected against updates from the underly-
time when fields are partially written or read (incoherent).
ing hardware, and any new samples that may be generated
Coherency checking is an option and is enabled in the
while incoherent are dropped (without warning). The field
DEC_COHER register.
remains flagged incoherent until the Key Coherency Byte is
The hardware provides coherency checking on three regis- read. At this time, the field is flagged coherent (CIF is again
ter fields that are all up to three bytes wide: set), and the next time the hardware generates a new output
■ Gain and Gain Value (write protected) – really two fields, sample result, the field is updated.
but they are checked for coherency as if they are a sin-
gle field protected on writes so that the underlying hard-
ware does not incorrectly use the field when it partially
updated by system software.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 433

Delta Sigma Converter

39.3.6 Modes of Operation

This block has four primary operating modes:
■ Single Sample
■ Fast Filter
■ Continuous
■ Fast FIR
In Single Sample mode, the block sits in the standby state
waiting for one of two start signals (START_CONV bit in CR
register or ext_start). When a start is signaled, the block per-
forms one sample conversion (four decimation periods
where a decimation period is the count programmed in reg-
ister DEC_DR1). It then captures the result, and signals the
system by a polling or an interrupt that the process is com-
plete and waits for the next signal as it reenters the standby
state.
The Fast Filter mode captures single samples back to back,
resetting itself and the Modulator between each sample.
Upon completion of a sample, the next sample is initiated
continuously. Polling and interrupts mark result events. Fast
Filter mode is simply a continuous string of Single Samples
with channel resets between them. This mode should be
used when multiplexing channels.
If signaled to run Continuous, the filter resets the channel
then runs continuously from that point forward, until signaled
to stop, with no intervening resets of the channel. The hard-
ware blocks the first three decimation periods but then pro-
vides a result every decimation cycle thereafter.
Fast FIR mode is very much like Continuous mode, except
that the ADC channel is reset and the filter restarted when
the FIR decimation period (DR2) is reached. For example, if
the DR2 register is set to 15 and this mode is selected, the
filter:
■ Resets the channel
■ Blocks the first three decimation periods (DR1)
■ Produces 16 samples for the FIR function to operate on
■ Generates one output result
■ Repeats this sequence until signaled to halt
The decimator is set to one of the four modes by
DEC_CR[3:2] bits. All four modes are started by either a
write to the start bit in the DEC_CR[0] register or an asser-
tion of the input signal ext_start. Set the DEC_CR[1] register
bit when using the external start feature. When set, this bit
ignores the DEC_CR[0] start bit. Figure 39-10 on page 435
shows the state diagram of various modes of operation of
the decimator.

434 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Delta Sigma Converter

Figure 39-10. Decimator Modes

Single Sample Fast Filter

No Start No Start

IDLE IDLE

Start Start

Reset Modulator Reset Modulator

Clear Start Clear Start

Runs Once
Wait 3 Cycles to Prime Wait 3 Cycles to Prime
4 Stage CIC 4 Stage CIC

Runs until stopped by

Terminal Count not CSR write of Soft Terminal Count not
Reset
Count out DR1 Count out DR1

Terminal Count Terminal Count

Result in Output Register Result in Output Register

or to Post Processor if in Use or to Post Processor if in Use

Continuous Fast FIR

No Start No Start

IDLE IDLE

Start Start

Reset Modulator Reset Modulator

Clear Start Clear Start

Wait 3 Cycles to Prime Wait 3 Cycles to Prime

4 Stage CIC 4 Stage CIC

Terminal Count not Terminal Count not

Count out DR1 Count out DR1

Runs until stopped by Runs until stopped by

CSR write of Soft Terminal Count CSR write of Soft Terminal Count
Reset Reset
Result in Output Register Pass Result to Post Processor
Terminal Count not
or to Post Processor if in Use to Process

Count out DR2

Terminal Count

Result in Output Register

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 435

Delta Sigma Converter

436 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 40. Successive Approximation Register ADC

The PSoC® 5 architecture has two successive approximation register analog to digital convertors (SAR ADC) in addition to
the delta sigma ADC. The SAR ADC is designed for applications that require medium resolution and high data rate. The SAR
ADC takes its input from the analog globals, locals and the mux bus and the output can be taken from a register or be sent to
the UDB for further processing.

40.1 Features
■ 12-bit resolution
■ Single ended, differential input
■ Rail-to-rail input (0V to Vdda)
■ 1 MSPS sample rate
■ Four power modes
■ Single shot or continuous running mode
Figure 40-1. SAR ADC Block Diagram

AGL0 AGR0
AGL1 AGR1
AGL2 AGR2
AGL3 AGR3
AGL4 AGR4
AGL5 AGR5
AGL6 AGR6
AGL7 AGR7
abusL0 abusR0
abusL2 abusR2
VSSA VSSA
SAR0.SW*, or
DSI selection
AGL0
SAR0 SAR1 SAR0.SW*, or
DSI selection
AGR0
AGL2 AGR2
AGL4 AGR4
AGL6 AGR6
AMUXBUSL AMUXBUSR
abusL1 abusR1
abusL3 abusR3
VREF VREF
VSSA VSSA
SAR0.SW*, or SAR0.SW*, or
DSI selection DSI selection

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 437

Successive Approximation Register ADC

40.2 How It Works 40.2.3 Input Sampling

The input sampling time can be programmed from the 1 to
40.2.1 Input Selection 64 cycles in register SARx_CSR2[5:0] register bits. The
user can also retain the earlier DAC value or clear it at the
The SAR ADC takes differential inputs which are well con-
beginning of the new sampling clock. This is done in
nected to the analog routing structure. The positive input
SARx_CSR0[3] register bit. The conversion time is 18
connects to analog globals, analog locals and Vssa. The
cycles for input sampling time up to four cycles. The maxi-
negative input connects to analog globals, analog locals,
mum conversion time is 78 cycles for input sampling time of
analog mux bus, voltage reference and Vssa. The input
64 cycles. The sampling time is chosen based on the
selection, both positive and negative, is made through the
source's input impedance so that the input settling time is
input selection mux, which can be controlled through either
lower than the sampling time.
the SAR routing registers in the analog interface or through
the UDB. Setting the SARx_CSR[4] bit takes the positive
input through UDB and clearing the bit takes the positive 40.2.4 Power Modes
input through registers. Similarly, setting the SARx_CSR[3] The SAR ADC can be operated in different power modes.
bit takes the negative input through UDB and clearing the bit The user can configure to operate the SAR ADC in four
takes the negative input through registers. If the positive and power modes, namely maximum power, half of maximum
negative input selection is made through the registers, regis- power, 1/3 of maximum power or 1/4 of maximum power.
ters SARx_SW0, SARx_SW2, SARx_SW3, SARx_SW4 and There is a direct tradeoff between reducing the power with
SARx_SW6 help in making the selection. one of these modes and the SNR. The power selection is
done in SARx_CSR0[7:6] register bits.
40.2.2 Clock Selection
The clock to the SAR can come from one of the four avail- 40.2.5 Reference Selection
able analog clocks or a UDB generated clock. The clock The SAR ADC can take either an internal or an external ref-
selection for the SAR is made in SARx_CLK[2:0] register erence. The internal reference can be Vdda/2, 1.024V, 1,2V
bits. The clock can be enabled or disabled through the gate or DAC's output voltage. The reference selection is done in
control bit SARx_CLK[3]. The maximum input clock that can SAR_CSR1[7:5] register bits. In order for the vdda/2 refer-
be applied to the SAR is 18 MHz. The digital output will be ence selection be available, SAR_CSR3[6] register bit has
synchronized with respect to the corresponding digitally to be set.
aligned clock of the selected analog clock. This synchroni-
zation can be bypassed using SARx_CLK[4] register bit.

Table 40-1. SAR Analog Reference Modes

SN Mode Switch States
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13
1 External Reference ON OFF OFF OFF
Internal Reference with External
2 ON OFF OFF OFF
Capacitor
Internal Reference without External
3 OFF ON ON OFF
Capacitor
4 Vda as Reference Voltage OFF OFF ON ON

40.2.6 Operational Modes from the UDB. The selection between software and UDB
trigger is made in SARx_CSR0[2] register bit.
The SAR can be configured in two modes, single capture or
continuous. In single capture, the SAR ADC completes one As long the SOF stays high the conversion continues, the
conversion on a trigger; in the continuous mode the SAR conversion stops once the SOF goes low.
ADC performs continuous conversion. The trigger can be The two modes, single capture and continuous, is realized
either software or hardware. The software trigger comes in the way the SOF bit is configured, i.e., level or edge sen-
from SARx_CSR0[0] register bit and the hardware trigger is sitive SOF. In the level sensitive mode, the SAR ADC per-
forms the conversion as long as the SOF bit is asserted

438 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Successive Approximation Register ADC

high. So, the level sensitive mode is used for continuous Table 40-2. SAR Connections
conversion.
SAR0 Decode Table
In the edge sensitive mode, the SAR performs a conversion VP Connection VN Connection
on the edge and the bit is automatically reasserted low on 9 ABUSL[2] 9 Hi-Z (N/C)
the completion of the conversion (on the end of frame A VSSA A Hi-Z (N/C)
(EOF)). So, it has to be reasserted high for the next edge for B Hi-Z (N/C) B Hi-Z (N/C)
the SAR ADC to start conversion. This mode helps in per- C Hi-Z (N/C) C Hi-Z (N/C)
forming single sample conversions.
D Hi-Z (N/C) D Hi-Z (N/C)
In case of hardware enabled SOF, the user can sync the E Hi-Z (N/C) E Hi-Z (N/C)
conversion to a PWM frequency by configuring it in the edge F Hi-Z (N/C) F Hi-Z (N/C)
mode.
The level or edge triggered function of the SOF signal is
configured in the SARx_CSR0[1] register bit.

40.2.7 SAR ADC Output

The SAR ADC output includes:
■ End of Frame (EOF) bit
■ The output bits of user configured resolution
■ An optional interrupt on EOF
The resolution can be configured to be 8, 10 or 12 bits in
SARx_CSR2[7:6] register bits. Once a conversion is com-
plete the End of Frame (EOF) bit is asserted high in
SARx_CSR1[0] register bit. This bit is a clear on read sticky
status bit and is cleared automatically on a data read. The
conversion result is stored in the registers SARx_WRK0 and
SARx_WRK1 register. The SARx_WRK1 register bits [3:0]
stores the higher four bits [11:8] of the output. Coherency
protection can be applied to the SAR output by setting
SARx_CSR0[4] register bit. It ensures that a new output is
written only when both the registers are read.
The EOF output can be used to generate interrupt to the
CPU or DMA. The interrupt is enabled by setting the
SARx_CSR1[1] register bit. The interrupt can be made
edge/ level interrupt by setting/clearing SARx_CSR1[2] reg-
ister bit.

Table 40-2. SAR Connections

SAR0 Decode Table
VP Connection VN Connection
0 AGL[0] 0 AGL[0]
1 AGL[1] 1 AGL[2]
2 AGL[2] 2 AGL[4]
3 AGL[3] 3 AGL[6]
4 AGL[4] 4 AMUXBUSL
5 AGL[5] 5 ABUSL[1]
6 AGL[6] 6 ABUSL[3]
7 AGL[7] 7 VREFHI
8 ABUSL[0] 8 VSSA

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 439

Successive Approximation Register ADC

440 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Section G: Program and Debug

JTAG (4- or 5-wire) or Serial Wire Debugger (SWD) (2 wire) interfaces are used for programming and debug. The 1-wire Sin-
gle Wire Viewer (SWV) can also be used for “printf” style debugging. By combining SWD and SWV, the designer can imple-
ment a full debugging interface with just three pins. Using these standard interfaces enables the designer to debug or
program the PSoC® device with a variety of hardware solutions from Cypress or third-party vendors.
This section encompasses the following chapters:
■ Test Controller chapter on page 443
■ 8051 Debug on-Chip chapter on page 455
■ Cortex-M3 Debug and Trace chapter on page 465
■ Nonvolatile Memory Programming chapter on page 473

Top Level Architecture

Program and Debug Block Diagram

PROGRAM AND DEBUG

Program
System Bus

Debug and Trace

Boundary Scan

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 441

 Section G: Program and Debug

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 442

 41. Test Controller

The PSoC® 3 and PSoC® 5 architectures include a test controller used for the following purposes:
■ Access to I/O pins for boundary scan testing.
■ Access to the device memory and registers (via the PHUB) through either the PSoC 3 Debug on-Chip (DOC) module or
the PSoC 5 Cortex-M3 Debug Access Port (DAP) for functional testing, device programming, and program debugging.
The test controller connects to off-chip devices via the Joint Test Action Group (JTAG) interface or the Serial Wire Debug
(SWD) interface. These interfaces use I/O port pins; the exact number of pins depends on the type of interface used.

41.1 Features
The test controller has the following features:
■ Supports JTAG or SWD interface to a debug host
■ SWD interface available on either GPIO or USB pins
■ Supports boundary scan in accordance with the JTAG IEEE Standard 1149.1-2001 “Test Access Port and Boundary-
Scan Architecture”
■ Supports additional JTAG instructions/registers beyond IEEE Standard 1149, for access to the rest of the device
■ Interfaces to PSoC 3 or PSoC 5 debug modules for access to the rest of the device for program and debug operations

41.2 Block Diagram

In PSoC 3 architecture, the test controller translates JTAG instructions/registers or SWD accesses to register accesses in the
Debug on-Chip (DOC) module. See Figure 41-1.
Figure 41-1. PSoC 3 Test Controller Block Diagram

TDI

TDO/SWV
Debug
Test
TMS/SWDIO On- 8051
Controller
Chip

TCK/SWDCK

nTRST

SWV

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Test Controller

In PSoC 5 architecture, under certain JTAG instructions, the JTAG or SWD signals are simply passed to the ARM Debug
Access Port (DAP). See Figure 41-2.
Figure 41-2. PSoC 5 Test Controller Block Diagram

TDI
SWDITMS TDI_OUT
SWCLKTCK TMS_OUT
Test
nTDOEN TCK_OUT DAP Cortex-M3
Controller
TDO TDO_IN
SWDOEN SWDO_IN
SWDO

41.3 Background Information most GPIO and SIO port pins have a boundary scan cell
associated with them (see GPIO and SIO block diagrams in
The following information is provided to familiarize the user the I/O System chapter on page 187).
with the JTAG interface and the IEEE 1149 specification.
The interface used to control the values in the boundary
scan cells is called the Test Access Port (TAP) and is com-
41.3.1 JTAG Interface monly known as the JTAG interface. It consists of three sig-
In response to higher pin densities on ICs, the Joint Test nals: (1) Test Data In (TDI), (2) Test Data Out (TDO), and
Action Group (JTAG) proposed a method to test circuit (3) Test Mode Select (TMS). Also included is a clock signal
boards by controlling the pins on the ICs (and reading their (TCK) that clocks the other signals.
values) via a separate test interface. The solution, later for-
TDI, TMS, and TCK are all inputs to the device, and TDO is
malized as IEEE Standard 1149.1-2001, is based on the
output from the device. This interface enables testing multi-
concept of a serial shift register routed across all of the pins
ple ICs on a circuit board, in a daisy-chain fashion, as
of the IC – hence the name “boundary scan.” The circuitry at
shown in Figure 41-3.
each pin is supplemented with a multipurpose element
called a boundary scan cell. In PSoC 3 and PSoC 5 devices,
Figure 41-3. JTAG Interface to Multiple ICs on a Circuit Board
TMS

TCK

TMS Device 1 TMS Device 2 TMS Device 3

TCK TCK TCK
TDI
TDI TDO TDI TDO TDI TDO

TDO

444 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Test Controller

Within each device, the JTAG interface architecture is

shown in Figure 41-4. Data at TDI is shifted in, through one
of several available registers, and out to TDO.
Figure 41-4. JTAG Interface Architecture

Boundary Scan Path

Boundary
Scan Cells

IO Pads

Core
Logic

TDI Instruction Register

BYPASS Register

ID Register

Other Register

TCK
Test Access Port
TMS
Controller
TRST
TDO

The TMS signal controls a state machine in the TAP. The

state machine controls which register (including the bound-
ary scan path) is in the TDI-to-TDO shift path, as shown in
Figure 41-5 on page 446.
The following terms apply:
■ ir – the instruction register
■ dr – one of the other registers (including the boundary
scan path), as determined by the contents of the instruc-
tion register
■ capture – transfer the contents of a dr to a shift register,
to be shifted out on TDO (read the dr)
■ update – transfer the contents of a shift register, shifted
in from TDI, to a dr (write the dr)

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 445

Test Controller

Figure 41-5. TAP State Machine

TMS = 1
test logic reset
TMS = 0
TMS = 0
run test idle
TMS = 1

TMS = 1 TMS = 1
select dr scan select ir scan
TMS = 0 TMS = 0

TMS = 1 TMS = 1
capture dr capture ir
TMS = 0 TMS = 0 TMS = 0 TMS = 0

shift dr shift ir
TMS = 1 TMS = 1

TMS = 1
exit 1 dr exit 1 ir
TMS = 0 TMS = 0 TMS = 0 TMS = 0

pause dr pause ir
TMS = 1 TMS = 1

TMS = 0 TMS = 0
exit 2 dr exit 2 ir
TMS = 1 TMS = 1

update dr update ir
TMS = 1 TMS = 0 TMS = 1 TMS = 0

The registers in the TAP are: The standard set of instructions (values that can be shifted
■ Instruction – Typically 2 to 4 bits wide, holds the current into the instruction register), as specified in IEEE 1149, are:
instruction that defines which data register is placed in ■ EXTEST – Causes TDI and TDO to be connected to the
the TDI-to-TDO shift path. boundary scan path (BSR).
■ Bypass – 1 bit wide, directly connects TDI with TDO, The device is changed from its normal operating mode
causing the device to be bypassed for JTAG purposes. to a test mode. Then, the device's pin states can be
sampled using the capture dr JTAG state, and new val-
■ ID – 32 bits wide, used to read the JTAG manufacturer/
ues can be applied to the pins of the device using the
part number ID of the device.
update dr state.
■ Boundary Scan Path (BSR) – Width equals the number ■ SAMPLE – Causes TDI and TDO to be connected to the
of I/O pins that have boundary scan cells, used to set or BSR, but the device is left in its normal operating mode
read the states of those I/O pins.
During this instruction, the BSR can be read by the cap-
Other registers may be included in accordance with device ture dr JTAG state, to take a sample of the functional
manufacturer specifications. data entering and leaving the device.

446 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Test Controller

■ PRELOAD – Causes TDI and TDO to be connected to 41.3.2 Serial Wire Debug Interface
the BSR, but device is left in its normal operating mode.
The instruction is used to preload test data into the BSR The SWD interface was developed by ARM in response to
prior to loading an EXTEST instruction. the need for a debug interface that uses fewer pins than
JTAG. Boundary scan is not available from the SWD inter-
Optional, but commonly available, instructions are: face. Only two signals are used – a bidirectional data signal
■ IDCODE – Causes TDI and TDO to be connected to an (SWDIO) and a clock for the data signal (SWDCK).
IDCODE register.
Each data transfer consists of two or three phases:
■ INTEST – Causes TDI and TDO to be connected to the
■ Packet Request – External host debugger issues a
BSR. While the EXTEST instruction allows access to the
request to the device.
device pins, INTEST enables similar access to the core-
■ Acknowledge Response – Device sends an acknowl-
logic signals of a device.
edge response to the host.
For more information, see the IEEE Standard, available at
■ Data – Present only when a packet request is followed
http://www.ieee.org.
by a valid (OK) acknowledge response – The data trans-
fer is either:
❐ Device to host, following a read request – RDATA
❐ Host to device, following a write request – WDATA
Figure 41-6 shows a successful SWD write, and Figure 41-7
shows a successful SWD read.
Figure 41-6. Successful SWD Write

Clock

ACK[0:2]
RnW 0
APnDP

Parity
Parity
A[2:3]

Park
Start

Stop

Trn

Trn

1 0 0 WDATA[0:31]

Wire driven by: Host Target Host

Figure 41-7. Successful SWD Read

Clock

ACK[0:2]
RnW 1
APnDP

Parity
Parity
A[2:3]

Trn
Park
Start

Stop

Trn

1 0 0 RDATA[0:31]

Wire driven by: Host Target

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 447

Test Controller

In Figure 41-6 and Figure 41-7, the following sequence 9. The address, ACK and read and write data are always
occurs: transmitted LS bit first.
1. The start bit initiates a transfer; it is always logic ‘1’. The SWD interface can be reset by clocking 50 or more
2. The APnDP bit determines whether the transfer is an cycles with SWDIO high. To go back to the idle state
Access Port access, ‘1’, or a Debug Port access, ‘0’. SWDIO must be clocked low once.
3. The next bit is RnW, which is ‘1’ for a read from the For more information, see the ARM Debug Interface Archi-
device or ‘0’ for a write to the device.
tecture Specification, available at http://www.arm.com.
4. The ADDR bits are register select bits for the Access
Port or Debug Port.
5. The Parity bit has the parity of APnDP, RnW, and ADDR. 41.4 How It Works on PSoC 3 and
If the number of logical 1s in these bits is odd then Parity PSoC 5 Devices
must be ‘1’, otherwise ‘0’.
a. If the parity bit is not correct, the header is ignored; The PSoC 3 and PSoC 5 JTAG and SWD interfaces comply
there is no ACK response. with standard specifications and offer extensions unique to
b. When the host detects that the header was ignored, PSoC 3 and PSoC 5 architectures.
it must wait for a complete read transfer time before
attempting another transfer. 41.4.1 Clocking
6. The Stop bit is always logic 0.
The clock signal (TCK) for JTAG mode and the data signal
7. The Park bit is not driven by the host, the SWD interface clock (SWDCK) for SWD interface share the same I/O pin
on the device pulls the line high, and the device reads (P1[1]). (An alternate SWDCK can be input on the USB D-
this bit as a logic ‘1.’
pin, P15[7].) Clocking limits apply to both clocks in either
8. The ACK bits are the device-to-host response. Possible mode. The frequency of the clock must be between 1 MHz
values are shown in Table 41-1. and CPU_CLK/3 or 25 MHz, whichever is less.
Table 41-1. SWD Possible ACK Bit Values
41.4.2 PSoC 3 and PSoC 5 JTAG
ACK Code
[2:0]
Meaning Instructions
001 OK – header acknowledged, data transfer follows
The PSoC 3 and PSoC 5 JTAG interface complies with the
WAIT – previous transfer still being processed, host IEEE 1149.1-2001 specification, and provides additional
010
should retry
instructions. The instruction register is 4 bits wide. Instruc-
FAULT – a fault flag is set in the Debug Port control/sta-
100 tions are listed in Table 41-2.
tus register

The data phase includes a parity bit (odd parity, same as

for the packet request phase). Also, there is a single-
cycle turnaround time between the packet request and
the ACK phases, as well as between the ACK and the
data phases for write transfers.

Table 41-2. Additional PSoC 3 and PSoC 5 JTAG Instructions

Bit Code Instruction PSoC 3, PSoC 5 Function
1111 BYPASS See IEEE 1149.1-2001
1110 IDCODE See IEEE 1149.1-2001
SAMPLE /
0010 See IEEE 1149.1-2001. SAMPLE and PRELOAD share the same bit code.
PRELOAD
0000 EXTEST See IEEE 1149.1-2001
0100 INTEST Same as EXTEST
0101 CLAMP Connects TDI and TDO to the BYPASS register, and sets the pins to the current contents of the boundary scan register
1010 DPACC Connects TDI and TDO to the DP/AP Access register, for accesses to the Debug Port registers.
1011 APACC Connects TDI and TDO to the DP/AP Access register, for accesses to the Access Port registers.
1000 ABORT PSoC 5 devices only – aborts the current AP access instruction. Connects TDI and TDO to the DP/AP Access register.
Notifies the PSoC 3, PSoC 5 power manager that it may power down the Test Controller (TC) if necessary. If this instruc-
1100 SLEEP
tion is not set then the TC cannot be put to sleep.

448 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Test Controller

41.4.3 DP/AP Access Register

PSoC 3 and PSoC 5 architecture has a DP/AP Access register that is 35 bits wide. This register is used to transfer data
between the JTAG or SWD interface and the Debug Port and Access Port registers. The SWD interface enables direct reads
and writes of the DP/AP Access register; the JTAG interface uses the DPACC and APACC instructions.
In the JTAG update dr state, or when writing the register from the SWD interface, the structure is as shown in the following fig-
ure.
Figure 41-8. Writing the Register

DATAIN[34:3] A[2:1] RnW[0]

■ Bits 34 to 3 – 32 bits of data – If the Port register is less than 32 bits wide, only the N LS bits are transferred, where N is
the width of the Port register.
■ Bits 2 to 1 – 2-bit address for Debug or Access Port register select – In PSoC 5 devices, it is transferred to bits [3:2] of the
register select; bits [1:0] are 0.
■ Bit 0 – RnW – 1 = read (from device to debug host); 0 = write (to device from debug host)
In the JTAG capture dr state, or when reading the register from the SWD interface, the structure is as shown in the following
figure.
Figure 41-9. Reading the Register

34 3 2 1 0
ReadResult[34:3] ACK[2:0]

■ Bits 34 to 3 – 32 bits of data – If the Port register is less 41.4.4 JTAG/SWD Addresses (PSoC 3)
than 32 bits wide, only the N LS bits are transferred,
where N is the width of the port register. In the PSoC 3 architecture, the 2-bit address, transferred by
either JTAG or SWD as described above, is used to access
■ Bits 2 to 0 – ACK response code – Depending on the
Debug Port, Access Port, and ID Code registers as shown in
interface, the ACK response is as indicated in
Table 41-4.
Table 41-3.
Table 41-4. JTAG/SWD Addresses (PSoC 3)
Table 41-3. ACK Response for JTAG/SWD Transfers
DPACC APACC
ACK[2:0] JTAG SWD Address
(APnDP = 0) (APnDP = 1)
OK 010 001
00 IDCODE (SWD only)a –
WAIT 001 010
01 DBGPRT_CFG TRNS_ADDR
10 – –
11 – DATA_RW
a. The SWD protocol is designed around direct access to the DP/AP Ac-
cess register as described above. In addition, IDCODE can be read us-
ing the SWD interface with a packet request containing ADDR = 00,
APnDP = 0, and RnW = 1. This feature is not available in JTAG be-
cause JTAG has an IDCODE instruction.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 449

Test Controller

41.4.5 Debug Port and Access Port Registers (PSoC 3)

All of the registers listed in Table 41-5 are read/write, except for bit 7 of the DBGPRT_CFG register.

Table 41-5. Debug Port and Access Port Registers (PSoC 3)

Instruction Address
Name Size Function
(AP/DP) (Register Select)
Debug Port configuration register – transfer size (8, 16, or 32 bits), auto-increment
DBGPRT_CFG DPACC 01 8 bits
TRNS_ADDR, detect/clear write error
TRNS_ADDR APACC 01 24 bits Transfer address (see the Memory Map chapter on page 141)
DATA_RW APACC 11 32 bits Data to be written to or read from the address in TRNS_ADDR

41.4.6 PSoC 3 Register Access 4. To read from address 0xADD8E5:

Examples a. Write 0x00ADD8E5 to the TRNS_ADDR register, as
described above.
The following directions show how to access an address in
b. Read the DATA_RW register as described above
the 8051 xdata space, using either the JTAG or the SWD except that the address is 11 instead of 01 and the
interface. Assume the address value to be 0xADD8E5. RnW bit is 1 instead of 0.
1. To use JTAG to write the address value to the c. The test controller initiates a read transfer request to
TRNS_ADDR register, the debug host must: the PSoC 3 DOC; the data read from DATA_RW is
a. Shift the APACC instruction into the Instruction regis- invalid.
ter. d. Wait at least 5 TCK/SWDCK clock cycles, to avoid a
b. Shift a 0 (write) followed by a 01 (Access Port regis- WAIT response.
ter select) followed by a 0x00ADD8E5 (32-bit e. Read the DATA_RW register again. The data is now
address), into the 35-bit DP/AP Access register. For valid.
each element, the LS bit is shifted first.
Up to four sequential addresses can be written/read by set-
c. Go to the JTAG update dr state.
ting the transfer size in DBGPRT_CFG. If the TRNS_ADDR
2. To use SWD to write the address value to the auto-increment bit is set, sequential addresses can be writ-
TRNS_ADDR register, the debug host must:
ten/read without updating TRNS_ADDR at each access.
a. Send a packet request where APnDP = 1, RnW = 0,
and ADDR = 01. To do this, invoke the DPACC instruction through either
b. Get an ACK response from the PSoC device. JTAG or SWD. And then access the appropriate Debug Port
configuration registers.
c. In the data phase, send 0x00ADD8E5.
3. To write a value 0xDA to address 0xADD8E5: For PSoC 3 there is only one Debug Port configuration reg-
a. Write 0x00ADD8E5 to the TRNS_ADDR register, as ister, DBGPRT_CFG. Bits [2:1] determine if the transfer size
described above. is 8,16 or 31 bits. Bit [3] enables the auto address increment
functionality. For 8-bit increment write 2'b00 to Bits [2:1], for
b. Write 0x000000DA to the DATA_RW register, as
described above except that the address is 11 16 bit increment write 2'b01 to Bits [2:1], and for 32 bit incre-
instead of 01. ment write 2'b10 to Bits [2:1]. To enable auto increment write
a 1'b1 to Bit [3].
c. The test controller initiates a write transfer request to
the PSoC3 DOC.
41.4.7 Debug Port and Access Port
Registers (PSoC 5)
The registers listed in Table 41-6 on page 451 are part of
the ARM Cortex-M3 Debug Access Port (DAP). In the PSoC
5 Cortex-M3, the DAP consists of the SWD/JTAG Debug
Port (SWJ-DP) and the AHB Access Port (AHB-AP).
For further information on these ports and their registers,
see the ARM Debug Interface Architecture Specification (for
the SWJ-DP), and the ARM Cortex-M3 Technical Reference

450 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Test Controller

Manual (for the AHB-AP), both available at

http://www.arm.com.
Table 41-6. Debug Port and Access Port Registers (PSoC 5)
Instruction Address
Name Function
(AP/DP) (Register Select)
DP CTRL/STAT DPACC 01 Debug Port control/status register
Access port select – The MS byte of the SELECT register selects which Access Port
SELECT DPACC 10 (AP) is used on AP accesses. To select the Cortex-M3 AHB-AP, this byte should
always be 0x03. Bits [7:4] select which register in the AHB-AP is accessed.
SWD only – Returns the result of the last AP read access, without the need to start a
RDBUFF DPACC 11
new AP access operation.
00
AP Control Status APACC AHB-AP control/status register
(SELECT[7:4] = 0)
01
AP Transfer Address APACC AHB-AP transfer address register
(SELECT[7:4] = 0)
11
AP Data Read/Write APACC AHB-AP data read/write register
(SELECT[7:4] = 0)
00
AP Banked Data 0 APACC AHB-AP banked data register
(SELECT[7:4] = 1)
01
AP Banked Data 1 APACC AHB-AP banked data register
(SELECT[7:4] = 1)
10
AP Banked Data 2 APACC AHB-AP banked data register
(SELECT[7:4] = 1)
11
AP Banked Data 3 APACC AHB-AP banked data register
(SELECT[7:4] = 1)
10
AP Debug ROM Address APACC AHB-AP debug ROM address register (read only)
(SELECT[7:4] = 0xF)
11
AP Identification Register APACC AHB-AP ID register (read only)
(SELECT[7:4] = 0xF)

41.5 Boundary Scan Pin Order

For the 100-pin TQFP device, the PSoC 3, PSoC 5 boundary scan path (BSR) is connected to the I/O pins around the part
from TDI (P1[4]) through TDO (P1[3]), in the order shown in the following table.

Table 41-7. Boundary Scan Pin Order

BSR# Pin BSR# Pin BSR# Pin BSR# Pin BSR# Pin BSR# Pin
1 P1[5] 13 P15[1] 25 P15[3] 37 P0[7] 49 P15[5] 61 P6[5]
2 P1[6] 14 P3[0] 26 P12[2] 38 P4[2] 50 P2[0] 62 P6[6]
3 P1[7] 15 P3[1] 27 P12[3] 39 P4[3] 51 P2[1] 63 P6[7]
4 P12[6] 16 P3[2] 28 P4[0] 40 P4[4] 52 P2[2] 64 XRES_N
5 P12[7] 17 P3[3] 29 P4[1] 41 P4[5] 53 P2[3] 65 P5[0]
6 P5[4] 18 P3[4] 30 P0[0] 42 P4[6] 54 P2[4] 66 P5[1]
7 P5[5] 19 P3[5] 31 P0[1] 43 P4[7] 55 P2[5] 67 P5[2]
8 P5[6] 20 P3[6] 32 P0[2] 44 P6[0] 56 P2[6] 68 P5[3]
9 P5[7] 21 P3[7] 33 P0[3] 45 P6[1] 57 P2[7] 69 P1[2]
10 P15[6] 22 P12[0] 34 P0[4] 46 P6[2] 58 P12[4]
11 P15[7] 23 P12[1] 35 P0[5] 47 P6[3] 59 P12[5]
12 P15[0] 24 P15[2] 36 P0[6] 48 P15[4] 60 P6[4]

Similar boundary scan paths exist on the 68-pin QFN and 48-pin SSOP parts.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 451

Test Controller

41.6 Test Controller Interface 41.7.1 Changing Interface from SWD to

Pins JTAG
This can be done only if the port was acquired using the
Two NV latch bits determine the state of the JTAG/SWD
standard SWD pin pair. To switch to JTAG, clock in 50
interface pins at reset. The settings of the bits are shown in
cycles with SWDIO = 1 then clock in 0xE73C (LS bit first) on
the following table.
SWDIO. The test controller will then be configured for 4-wire
Table 41-8. JTAG / SWD Interface Bit Settings JTAG, and the TAP will be in the JTAG test logic reset state.

CNVL_DPS[1:0] Port Configuration

00 (default) 5 – Wire JTAG (nTRST is included)
41.7.2 Changing Interface from JTAG to
01 4 – Wire JTAG (nTRST is not used)
SWD
10 Serial Wire Debug (SWD) Clock in 50 cycles with TMS = 1, then clock in 0xE79E (LS
11 Debug Port Disabled (GPIO) bit first) on TMS. The test controller will then be configured
for SWD in the reset state.
In addition, PSoC 3 architecture contains a Single Wire
At power on reset, the PSoC 5 ARM Cortex-M3 DAP starts
Viewer (SWV) module, whose interface consists of a single
up in JTAG mode. For details on how to switch the DAP
output signal SWV. The test controller routes SWV to the
between the JTAG and SWD modes, see the ARM Core-
JTAG/SWD pins; SWV shares a pin with the JTAG TDO sig-
Sight™ Component Technical Reference Manual available
nal. When the pins are configured for SWD mode then SWV
at http://www.arm.com.
is also routed to the TDO/SWV pin. For further details on the
SWV, see the 8051 Debug on-Chip chapter on page 455.
41.7.3 Boundary Scan
To perform a boundary scan:
41.7 Test Controller Acquisition
1. At reset, assume that the pins state is unknown.
If the debug port is disabled, the only way to gain debug 2. Do a port acquire within the key window, which enables
access to the part is to enter a valid port acquire key within a the SWD interface.
key window period of 8 µs after reset (8 µs is only the initial 3. Shift to the JTAG interface.
window, it extends to 400 µs if 8 clocks are sampled in 8 µs).
4. Start doing boundary scan operations.
The port acquire key must be transmitted over one of the
two SWD pin pairs, as indicated in the following table.
41.7.4 Functional Test
Table 41-9. SWD Pin Pairs To perform a functional test:
SWD Pin Pair SWDIO SWDCK 1. At reset, assume that the pins state is unknown.
Standard P1[0] P1[1]
2. Do a port acquire within the key window, which enables
Alternate P15[6] (USB D+) P15[7] (USB D-) the SWD interface.
3. Use the SWD interface or, if desired, shift to the JTAG
The SWD packet request phase consists of: interface.
■ APnDP = 0 4. Start writing or reading PSoC 3 and PSoC 5 devices to
■ RnW = 0 or from registers and memory for functional tests.
■ ADDR = 11
41.7.5 Programming Flash/EEPROM
■ WDATA = 0x7B0C06DB with WDATA Parity = 0
To program Flash or EEPROM:
The SWD frame should be transmitted at least twice, ignor-
ing the ACK on the first transmit; it should be transmitted 1. At reset, assume that the pins state is unknown.
until the ACK response is OK. The SWD interface will be in 2. Do a port acquire within the key window, which enables
the idle state, ready for the next write. The debug host can the SWD interface.
then either continue using the SWD interface or switch to 3. Use the SWD interface or if desired shift to the JTAG
the JTAG interface. interface.
4. Start writing or reading to or from PSoC 3 and PSoC 5
SPC registers to program Flash/EEPROM. Refer to the
Nonvolatile Memory Programming chapter on page 473
for details.

452 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Test Controller

41.7.6 Program Debug/Trace

To perform a debug or trace:
1. At any time during normal operation, use the SWD or
JTAG interface as set up by the NV latch bits.
2. Start writing or reading to or from PSoC 3 DOC or
PSoC 5 Cortex-M3 DAP debug module registers to do
program debug/trace operations.
In PSoC 3, the test controller can access the DOC only
when the DOC is enabled. This is done under program con-
trol by setting the DEBUG_ENABLE bit in the
MLOGIC_DBG_DBE[0] register. The bit is 0 at reset.

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 42. 8051 Debug on-Chip

PSoC® 3 debug modules consist of the Debug on-Chip (DOC) and the Single Wire Viewer (SWV). The DOC interfaces
between the CPU and the Test Controller (TC). It is used to debug and trace code execution and to troubleshoot device con-
figuration. The DoC exists only on the 8051-based PSoC 3, CY8C38 family. The ARM Cortex-M3-based PSoC® 5 CY8C55
family uses ARM's CoreSight components for debug and trace. For details see the Cortex™-M3 Microcontroller chapter on
page 67.
The SWV module allows target resident code to communicate diagnostic information to the outside world through a single
pin. Usage examples include data monitoring, viewing OS task switches, printf debugging, and call graph profiling.

42.1 Features
The DOC is capable of taking over the 8051 CPU and using its PHUB interface to access any address accessible by the
CPU. It provides the following features:
■ TC interface for access via either JTAG or SWD
■ Access of CPU internal memory and SFRs, and the Program Counter (PC) (see the 8051 Core chapter on page 37)
■ CPU halt
■ CPU single step through instructions
■ 8 program address breakpoints
■ 1 memory access breakpoint
■ Watchdog trigger breakpoint
■ Breakpoint chaining
■ Trace CPU instruction execution:
❐ Trace CPU program counter (PC), accumulator (ACC), and one byte from CPU internal memory or SFR
❐ 2048 instruction trace buffer if tracing PC only
❐ 1024 instruction trace buffer if tracing PC, ACC, and a memory/SFR byte
❐ Continuous, triggered, or windowed mode
❐ On trace buffer full, either CPU halt or overwrite oldest trace
❐ When not tracing, trace buffer is available as normal SRAM
The SWV has the following features:
■ 32 stimulus port registers
■ Simple, efficient packing and serializing protocol
■ Two pin output modes, UART or Manchester encoding

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8051 Debug on-Chip

42.2 Block Diagram

In PSoC 3 devices, the TC translates JTAG instructions and registers or SWD accesses to register accesses in the Debug
on-Chip (DOC). SWV data is output through the TC onto a single pin SWV. The SWV pin is shared with the JTAG TDO signal.
Figure 42-1 shows a block diagram of the relationship among the TC, DOC, CPU, and SWV. (See the Test Controller chapter
on page 443.)
Figure 42-1. TC, DOC, CPU, and SWV

TDI

TD O /S W V
D ebug
T est
T M S /S W D IO on- 8051
C ontroller
C hip

T C K /S W D C K

nT R S T

SW V

The DOC module interfaces between the CPU and the TC, as shown in Figure 42-2. The memory interface is used for system
reads and writes through the CPU.
Figure 42-2. DOC, CPU, and TC Block Diagram

Debug on-Chip Flash

Internal
Test
Memory RAM
Controller
Interface
Interface
SFRs
Test
Controller

Address
Monitor CPU
Configuration
Trace Breakpoints
Registers

CPU Halt
CPU External
Memory/Registers

Trace
SRAM

456 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 8051 Debug on-Chip

42.3 How it Works Table 42-4. DOC_DBG_CTRL, STEP, Bit 2

DOC functions are controlled by accessing a series of regis- Setting Description
ters within the DOC. The DOC registers are accessible only 1 Single-step the CPU
through the TC interface; they are not accessible through 0 (default) No effect
the PHUB.
After writing a 1 to this bit, the CPU executes one instruction
42.3.1 Enabling and Activating then halts. The STEP bit is reset to 0. The following applies:
Before any DOC operations can be done, debugging must ■ The HALT bit must be set to 1 to write the STEP bit.
be enabled by the CPU. Bit 0, debug_enable, in the ■ The debug enable and the debug activate bits must both
MLOGIC_DEBUG register, is used by the CPU to enable or be set to 1 to write the HALT or STEP bit.
disable debug, as shown in Table 42-1.
■ Every write to the debug control register,
Table 42-1. MLOGIC_DEBUG, debug_enable, Bit 0 DOC_DBG_CTRL, must contain in bits [7:4] the debug
key value 0b1011, otherwise the write is ignored.
Setting Description
1 Enable debug
42.3.3 Accessing PSoC Memory And
0 (default) Disable debug
Registers
Then, the DOC module must be activated by the TC inter- The TC receives debug commands via JTAG or SWD, and
face. Bit 0, DBG_ACT, of the debug control register, passes them to the DOC. Based on the received address,
DOC_DBG_CTRL, is used by the TC to activate or deacti- either the TC or DOC registers are accessed, or the address
vate debug, as shown in Table 42-2. and data are passed on to the DOC memory interface. The
DOC has multiple memory interfaces; it decodes the incom-
Table 42-2. DOC_DBG_CTRL, DBG_ACT, Bit 0 ing address and sends it to the correct memory interface
Setting Description address output. When the memory access is complete, the
1 Activate debug DOC signals the TC either that the write is complete or that
0 (default) Deactivate debug data from a read command is available.
TC commands specify the data size as 8, 16, or 32 bits
Setting the DBG_ACT bit also pauses the Central Time- wide; along with the address and data, the data size is
wheel (CTW). This makes certain that CTW interrupts or passed to the DOC memory interface. All accesses to the
Watchdog Resets (WDR) do not occur while the CPU is TC and DOC registers are 32 bits wide; the data size setting
paused. Every write to the debug control register, does not apply.
DOC_DBG_CTRL, must contain in bits [7:4] the debug key
value 0b1011, otherwise the write is ignored. The DOC memory interface is used for system reads and
writes through the CPU. The DOC memory interface takes
over the CPU memory interfaces, allowing the DOC to per-
42.3.2 Halting, Stepping
form reads and writes to memory as if the request were
Bit 1, HALT, of the debug control register, coming from the CPU. There are four memory interfaces:
DOC_DBG_CTRL, controls CPU halt, as shown in Flash, CPU internal memory, CPU SFRs, and CPU external
Table 42-3. memory/registers. There is also a CPU Program Counter
(PC) interface. The interface chosen for a read or write
Table 42-3. DOC_DBG_CTRL, HALT, Bit 1 transaction depends on the address. See the following
Setting Description table.
1 Halt the CPU Table 42-5. PSoC Memory and Registers
0 (default) Un-halt the CPU
Address Range Description
0x050000 – 0x0500FF CPU internal memory
Bit 2, STEP, of the debug control register,
0x05014E – 0x05014F CPU PC (16-bit register)
DOC_DBG_CTRL, is used to control CPU stepping, as
0x050180 – 0x0501FF CPU SFR space
shown in Table 42-4.
0x050200 – 0x05FFFF TC and DOC registers
all other addresses CPU external memory/registers

The CPU must be halted before reading or writing the PC.

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8051 Debug on-Chip

42.3.4 Breakpoints breakpoint configuration register DOC_BKPT_CFG, is used

to enable or disable this feature. See Table 42-7.
The PSoC 3 DOC has eight program address breakpoints,
one memory access breakpoint, and a watchdog trigger Table 42-7. DOC_BKPT_CFG, WDRBKPT, Bit 10
breakpoint. These breakpoints are used to halt the CPU at
Setting Description
specified events in the execution of the program.
1 Disable WRES break in debug mode
0 (default) Enable WRES break in debug mode
42.3.4.1 Program Address Breakpoints
The program address breakpoints use the eight registers When enabled with the Watchdog triggered, the DoC halts
DOC_PA_BKPT0 through DOC_PA_BKPT7. To set a pro- the CPU. When the CPU is unhalted, WRES is asserted to
gram address breakpoint, write the address compare value the system.
to bits [15:0] and set the breakpoint enable in bit 16. When
the CPU Program Counter (PC) matches the compare value The BKPT_CFG register also contains a bit Watchdog
on an instruction fetch, the CPU is halted. Reset Triggered (bit 11, WDR_TRG). This is a read-only bit
that can be used to determine if the CPU was halted
Since the PC address is compared, the memory access because a WDR occurred. The bit is set to 1 if the CPU was
breakpoint is also able to act as a program access break- halted due to WDR, otherwise it is read as a 0.
point.
Before the CPU is unhalted, the breakpoint enable bit must
42.3.4.4 Breakpoint Chaining
be reset to ‘0’. Breakpoint chaining is used to halt the CPU after a series of
breakpoints occur. Besides the memory access breakpoint,
42.3.4.2 Memory Access Breakpoint all program address breakpoints can be chained.
To set the memory access breakpoint, use the To set up breakpoint chaining, do the following:
DOC_MEM_BKPT register. Write the address compare
1. Set all of the required compare values in registers
value to bits [23:0], and write one of the following to the con- DOC_PA_BKPT0 – DOC_PA_BKPT7, and
figuration bits [25:24]: See Table 42-6. DOC_MEM_BKPT.
Table 42-6. DOC_MEM_BKPT, Configuration Bits [25:24] 2. Set the memory access read/write configuration bits in
DOC_MEM_BKPT.
Setting Description
3. Do not set the breakpoint enable bits in
00 (default) Memory breakpoint disabled DOC_PA_BKPT0 – DOC_PA_BKPT7.
01 Break on read only
4. After the compare values are set, set the breakpoint
10 Break on write only chain enable bit, BC_ENA, in DOC_BKPT_CFG[0], to 1.
11 Break on read or write 5. Set the chain include bits in DOC_BKPT_CFG to 1 for
each breakpoint included in the chain. There is one bit
The compare address value is compared with all CPU for each breakpoint, as shown in Table 42-8.
addresses — PC, internal memory, SFRs, and external
memory. When any of those addresses matches the com- Table 42-8. DOC_BKPT_CFG
pare value and the read or write access matches the config- Chain Include Bit Corresponding Breakpoint
uration bits, the CPU is halted. Note that since the PC DOC_BKPT_CFG [1], CBKPT_0 DOC_PA_BKPT0
address is compared, the memory access breakpoint can DOC_BKPT_CFG [2], CBKPT_1 DOC_PA_BKPT1
also act as a program access breakpoint.
DOC_BKPT_CFG [3], CBKPT_2 DOC_PA_BKPT2
Before the CPU is unhalted, the configuration bits must be DOC_BKPT_CFG [4], CBKPT_3 DOC_PA_BKPT3
reset to disabled, 00. DOC_BKPT_CFG [5], CBKPT_4 DOC_PA_BKPT4
DOC_BKPT_CFG [6], CBKPT_5 DOC_PA_BKPT5
42.3.4.3 Watchdog Trigger Breakpoint DOC_BKPT_CFG [7], CBKPT_6 DOC_PA_BKPT6

If the Watchdog is triggered during debug mode, Watchdog DOC_BKPT_CFG [8], CBKPT_7 DOC_PA_BKPT7
Reset (WRES) can be used as a breakpoint to halt the CPU DOC_BKPT_CFG [9], CBKPT_8 DOC_MEM_BKPT
instead of resetting the system. Bit 10, WDRBKPT, of the
The chain include bits cannot be set unless BC_ENA is set
to 1.

458 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 8051 Debug on-Chip

The breakpoints are chained in numeric order; a lower num- To enable tracing, set the trace control bits, TRC_CNTRL, in
bered breakpoint must occur before a higher numbered DOC_TRC_CFG[1:0]. SeeTable 42-10.
breakpoint. For example, PA_BKPT5 cannot be set as the
trigger for PA_BKPT3. When the last breakpoint in the chain Table 42-10. DOC_TRC_CFG[1:0], TRC_CNTRL
is triggered, the CPU is halted. Setting Description
Trace disabled – trace buffer is available for use as
When breakpoint chaining is enabled, breakpoints not in the 00 (default)
SRAM
chain can still be enabled; the CPU can be halted either on
01 Trace in Continuous mode
an individual breakpoint or on a chain of breakpoints.
10 Trace in Trigger mode
The register DOC_BKPTCS is used to determine the break- 11 Trace in Window mode
points in the chain that have or have not yet triggered. There
is one bit for each breakpoint. See Table 42-9. The following applies:
■ In Continuous mode, trace runs constantly until the CPU
Table 42-9. DOC_BKPTCS
is halted.
Remaining Breakpoint
Corresponding Breakpoint ■ In Trigger mode, trace starts running when the CPU PC
in Chain (RBIC) Bit
DOC_BKPTCS [0] DOC_PA_BKPT0 equals the compare value in breakpoint register #6,
DOC_BKPTCS [1] DOC_PA_BKPT1
DOC_PA_BKPT6. The breakpoint enable bit in this reg-
ister need not be set. Trace then runs constantly until the
DOC_BKPTCS [2] DOC_PA_BKPT2
CPU is halted.
DOC_BKPTCS [3] DOC_PA_BKPT3
■ In Window mode, trace starts running when the CPU PC
DOC_BKPTCS [4] DOC_PA_BKPT4
equals the compare value in breakpoint register #6,
DOC_BKPTCS [5] DOC_PA_BKPT5
DOC_PA_BKPT6. Trace then runs constantly until the
DOC_BKPTCS [6] DOC_PA_BKPT6
PC equals the compare value in breakpoint register #7,
DOC_BKPTCS [7] DOC_PA_BKPT7
DOC_PA_BKPT7 or until the CPU is halted. The break-
DOC_BKPTCS [8] DOC_MEM_BKPT
point enable bits in these registers need not be set.
Trace restarts if the PC equals breakpoint register #6
If a bit is set to 1, that breakpoint is part of the chain and has again. If both breakpoint registers have the same value,
not yet triggered. If all bits are set to 0 and breakpoint chain- no tracing is done.
ing is enabled, then all breakpoints in the chain have trig-
gered, and the CPU is halted. The CPU registers written to the trace buffer are controlled
by bit 2, TRC_FLTR, in DOC_TRC_CFG[2]. See
Before the CPU is unhalted, the breakpoint chain enable bit, Table 43-11.
BC_ENA, must be reset to 0.
Table 42-11. DOC_TRC_CFG[2], TRC_FLTR
42.3.5 CPU Reset Registers Written Maximum Number of
Setting
to Trace Buffer Instructions Traced
The CPU can be held in a reset state by setting the bit RST,
PC, accumulator (ACC), and one
in DOC_CPU_RST[0]. This setting has no effect on overall 0
byte of CPU internal memory/SFR – 1024
(default)
system resets. 32 bits total
1 PC only – 16 bits 2048

42.3.6 Tracing Program Execution

The address of the internal memory/SFR byte is set in the
When CPU program tracing is enabled, as each CPU TRC_PMEM bits of register DOC_TRC_CFG[15:8]. Values
instruction is executed, copies of various CPU registers are 0x00 – 0x7F address the lower 128 bytes of CPU internal
written to a trace buffer. This operation is done in real time; memory. Values 0x80 – 0xFF address the CPU SFRs.
neither CPU nor system speed is affected. The trace buffer
can be examined to review program execution history.
The trace buffer size is 4096 bytes. If tracing is not being
done, the trace buffer can be used as an additional 4K of
SRAM, operating in the same manner as the rest of SRAM.

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8051 Debug on-Chip

The registers are written to the trace buffer after the instruc- Figure 42-3. Trace Buffer Memory
tion is executed; the values shown in Table 42-12 are
saved.
CPU DOC
Table 42-12. Saved Values in the Trace Buffer
Register Value Written to Trace Buffer
PC Address (in flash) of the first byte of the instruction
ACC Value after instruction execution write_data_doc
Internal memory/
Value after instruction execution
SFR byte

Trace Enable
write_data1
read_data1 4 KB
For example, if the instruction is POP 0xE0 (0xE0 is the
SFR address of ACC), and TRC_PMEM = 0x81 (the SFR
address of SP), then, in addition to the address of the
instruction, the trace contains the value popped from the
stack and the new value of the stack pointer.
write_data2
PHUB 4 KB
When tracing in trigger point or windowed mode, the internal read_data2
memory/SFR byte must be initialized before tracing can
begin. This is done as follows:
1. Load TRC_PMEM bits with the byte address.
2. Write a value to the memory/SFR at that address. If the write_data3
write_data_phub
value cannot be changed, read it first, then write the 4 KB
read value back to the address. read_data3
3. Set the TRC_CNTRL bits to enable tracing.
The CPU can be halted when the trace buffer is full. This is
controlled by the bit TRC_FULL, in DOC_TRC_CFG[3]. See At anytime, an external debug system can read the trace
Table 42-13. data via the JTAG/SWD interface, TC, DOC, CPU, and
PHUB.
Table 42-13. DOC_TRC_CFG, TRC_FULL
42.3.6.2 Trace Time Stamp
Setting Description
0 (default) Don’t halt CPU, oldest trace is overwritten Two registers are included in the DOC for time stamping
1 Halt CPU (counting the number of cycles in a trace window), as shown
in Table 42-14. The registers can be used only in trace Win-
When the CPU is unhalted, tracing may restart. Because the dow mode. Both registers are 32 bits wide.
CPU is halted when the buffer is full, tracing always restarts
Table 42-14. DOC Time Stamping Registers
at the beginning of the buffer.
Register Value
In Overwrite mode, the overwrite address is not available;
Number of clock cycles from when the trace is enabled
therefore, when the trace buffer is examined, it is impossible ENTR_TS
and CPU started and the trace window is enabled
to tell which trace is the oldest. Number of clock cycles from when the trace is enabled
EXIT_TS
and CPU started to the exit point of the trace window
42.3.6.1 Reading Traces
The trace buffer memory is located in the CPU external
memory space at address 0x002000; in a part with 8K
SRAM the trace buffer is contiguous to SRAM.
Writes to this memory are done either by the DOC in trace
mode or through the PHUB (by the CPU or DMAC). All
reads from the memory are done through the PHUB. See
Figure 42-3.

460 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 8051 Debug on-Chip

42.3.7 DOC Registers To select an output protocol, use the Pin Protocol bits, in
register SWV_SWO_SPP[1:0] (register SPPR in the ARM
The DOC registers are accessible only through the TC inter- document). See Table 42-16.
face; they are not accessible through the PHUB.
Table 42-15 shows these registers. Table 42-16. SWV_SWO_SPP[1:0], Pin Protocol Bits
Setting Description
Table 42-15. DOC Registers
00 Reserved
Size
Register Description 01 (default) Manchester
(Bits)
DOC_DBG_CTRL 8 Debug control 10 UART

DOC_PA_BKPTx 24 Program address breakpoint 0 to 7 11 Reserved

DOC_MEM_BKPT 32 Memory access breakpoint

DOC_BKPT_CFG 16 Breakpoint configuration
To output instrumentation trace data to the SWV pin, do the
following:
DOC_BKPTCS 16 Breakpoint chain status
DOC_TRC_CFG 16 Trace configuration 1. Set the bit ITMEN, SWV_ITM_CR[0], which enables the
module.
DOC_PC 16 CPU Program Counter
DOC_CPU_RST 8 CPU reset control
2. Set bits in the enable register, SWV_ITM_TER, corre-
sponding to any of the 32 stimulus registers
DOC_ENTR_TS 32 Entry time stamp
SWV_ITM_SPR_DATA[0..31] to be used.
DOC_EXIT_TS 32 Exit time stamp
3. Write the data to an enabled stimulus register
SWV_ITM_SPR_DATA[0..31]. All stimulus registers are
42.4 Serial Wire Viewer 32 bits in size; data written to a stimulus register is
loaded into a FIFO to be transmitted as a 4-byte Soft-
In addition to the DOC, the PSoC3 CY8C38 family includes ware Instrumentation Trace (SWIT) packet.
a Serial Wire Viewer (SWV) module. The SWV allows target Other types of packets may also be sent by the SWV under
resident code to communicate diagnostic information to the firmware program control, such as time stamps and syn-
outside world through a single pin. Usage examples include chronization packets. For details on these packets see the
data monitoring, viewing OS task switches, printf debug- ARM document CoreSight™ Components Technical Refer-
ging, and call graph profiling. ence Manual.
SWV data is output through the TC onto a single pin SWV.
The SWV pin is shared with the JTAG TDO signal and GPIO 42.4.1 SWV Protocols
pin P1[3]. To connect the pin to SWV, set to SWD mode the
Both Manchester and UART protocols operate over a single
NV latch bits that determine the state of the JTAG/SWD
pin (SWV) and do not require separate clock or control pins.
interface pins at reset. (See the Test Controller chapter on
Every data packet is in 8-bit multiples (bytes) when either
page 443.) SWV can be used simultaneously with SWD, but
protocol is selected.
not with JTAG.
For a trace capture device to correctly interpret trace data
The SWV is composed of two CoreSight™ components pro-
from SWV, it must be able to decode where data exists on
duced by ARM (http://www.arm.com). The components are
the various pin protocols. This section describes how proto-
the Instrumentation Trace Macrocell (ITM) and the Serial
cols must be decoded to establish the underlying transmit
Wire Output (SWO). Both components have multiple data,
data.
control and status registers. For details on these registers
see the ARM document CoreSight™ Components Technical
Reference Manual.

To control the bit rate of the output, use the Prescaler, in

register SWV_SWO_CAOSD[12:0] (register CODR in the
ARM document). The SWV is clocked by BUS_CLK, which
must be divided down to the desired bit rate. The actual divi-
sor is the value of the Prescaler plus one. The maximum fre-
quency that can exist on any CY8C38 family port pin is
33 MHz.

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8051 Debug on-Chip

42.4.1.1 Manchester Encoding

In the Manchester protocol, the SWV outputs up to eight bytes of data between a start bit and a stop bit, as shown in
Figure 42-4. Table 42-17 describes Manchester pin protocol encoding.
Figure 42-4. Manchester Encoded Data Sequence

ST DATA (1 to 8 Bytes) SP

Table 42-17. Manchester Pin Protocol Encoding

Pin Logic ‘0’ Logic ‘1’ Idle State (No Data) Valid Data
Start bit:
HIGH-LOW
transition/Logic ‘1’
LOW-HIGH HIGH-LOW LOW between 1 and 8 bytes of data
TRACESWO
(01) (10) (00)
Stop bit:
output LOW, not a valid Manchester symbol

Figure 42-5 shows how a sequence of bytes is transmitted using Manchester bit encoding.
Figure 42-5. Manchester Encoding Example

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

TRACECLKIN

TRACESWO
0 0 1 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 0 0 0

Start 0 1 1 0 0 1 0 1 Stop

42.4.1.2 UART Encoding

In the UART protocol, data is sent out in packets of ten bits, with start and stop bits, as shown in Figure 42-6 and Table 42-18.
Capture devices are expected to operate at the same clocking speed as the SWV pin and synchronize by waiting for a start
bit.
Figure 42-6. UART Encoding Example

Start D0 D1 D2 D3 D4 D5 D6 D7 Stop

Table 42-18. UART Encoding

Pin Logic ‘0’ Logic ‘1’ Idle State (No Data) Valid Data
10 bit sequence:
Logic ‘0’
TRACESWO LOW HIGH HIGH
8 data bits
Logic ‘1’

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 8051 Debug on-Chip

42.4.2 SWV Registers

SWV registers are as listed in Table 42-19.

Table 42-19. SWV Registers

Size
Register Description
(Bits)
SWV_SWO_CAOSD 32 Output speed divisor
Output protocol (Manchester or
SWV_SWO_SPP 32
UART)
SWV_ITM_CR 32 ITM control
Enable for each of the stimulus
SWV_ITM_TER 32
ports
SWV_ITM_SPRxx 32 Stimulus ports 0 to 31
SWV_ITM_SCR 32 Synchronization packet control

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8051 Debug on-Chip

464 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 43. Cortex-M3 Debug and Trace

The PSoC® platform provides extensive support for programming, testing, debugging, and tracing both hardware and firm-
ware. PSoC 5 supports four interfaces: JTAG, SWD, SWV, and TRACEPORT. Cortex-M3 debug and trace functionality
enables full device debugging in the final system using the standard production device.
Cortex-M3 debugging features are classified into two types: invasive debugging and noninvasive debugging. Invasive debug-
ging includes program halting and stepping, breakpoints, data watchpoints, register value access, and ROM-based debug-
ging. Noninvasive debugging includes memory access, instruction trace, data trace, software trace, and profiling.

43.1 Features
■ Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running,
halted, or held in reset.
■ JTAG or SWD access.
■ Flash Patch and Breakpoint (FPB) block for implementing breakpoints and code patches.
■ Data Watchpoint and Trace (DWT) block for implementing watchpoints, trigger resources, and system profiling.
■ Embedded Trace Macrocell (ETM) for instruction trace.
■ Instrumentation Trace Macrocell (ITM) for support of printf style debugging.
■ Support for six breakpoints and four watchpoints.
■ Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer (TPA).

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 465

Cortex-M3 Debug and Trace

Figure 43-1. Debug and Trace Block Diagram

Debug control and data access occurs through the to bus, memory, and peripherals located in the system bus
Advanced High-performance Bus-Access Port (AHB-AP) space.
interface. This interface is driven by either the Serial Wire
Debug Port (SW-DP) or Serial Wire JTAG Debug Port
(SWJ-DP) components.
43.2 How It Works
Through internal PPB, the debugger can access: The PSoC 5 JTAG and SWD interfaces comply with stan-
dard specifications and offer extensions unique to PSoC 5
■ Nested Vectored Interrupt Controller (NVIC). Debug
architecture.
access to the processor core is made through the NVIC.
■ DWT
43.2.1 Test Controller (TC)
■ FPB
The Test Controller is used for the following purposes:
■ ITM
■ Access to I/O pins for boundary scan testing.
Through external PPB, the debugger can access:
■ Access to the device memory and registers (via the
■ ETM PHUB) through PSoC 5 Cortex-M3 Debug Access Port
■ Trace Port Interface Unit (TPIU) (DAP) for functional testing, device programming, and
program debugging.
Through the DCode bus, the debugger can access memory
located in the code space. The system bus provides access The Test Controller's Debug on-Chip (DoC) differs between
PSoC 5 and PSoC 3 architectures. This is because the IP

466 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Cortex-M3 Debug and Trace

provided by the ARM contains debug functionality that is 43.2.3 TRACEPORT

accessed through the ARM's Debug Access Port (DAP).
Therefore, the Test Controller samples the JTAG/SWD input In PSoC 5 devices, the TRACEPORT pins are a part of the
signals and then outputs the same JTAG/SWD signals to TPIU and are used to provide the trace output. The TRACE-
the DAP. PORT has five pins and is used for the fast transmission of
large trace streams.
Figure 43-2. PSoC 5 Test Controller interface

TDI 43.3 Core Debug

SWDITMS TDI_OUT
SWCLKTCK TMS_OUT Core debug allows users to exercise features such as
Test
nTDOEN TCK_OUT DAP Cortex-M3 enabling debug, halting, stepping, and accessing the PSoC
Controller
TDO TDO_IN memory and registers. Core debug is accessed through the
SWDOEN SWDO_IN
core debug registers. The main core debug registers are:
SWDO
■ Debug Halting Control and Status Register (DHCSR)
■ Debug Exception and Monitor Control Register
In PSoC 5 devices, under certain JTAG instructions, the (DEMCR)
JTAG or SWD signals are simply passed to the ARM Debug
■ Debug Core Register Data Register (DCRDR)
Access Port. For more details refer to the Test
Controller chapter on page 443. ■ Debug Core Register Selector Register (DCRSR)
Among these the Debug Halting Control and Status Register
43.2.2 PSoC 5 JTAG Instructions allows enabling the core debug, providing status information
about the state of the processor and halting and stepping
The PSoC 5 JTAG interface complies with the IEEE 1149.1-
the processor. More details regarding these registers can be
2001 specification, and provides additional instructions. The
found in the ARM Cortex-M3 Technical Reference Manual,
instruction register is 4 bits wide. Instructions are listed in
available at http://www.arm.com.
Table 41-2 on page 448.

43.2.2.1 Debug Port and Access Port 43.3.1 Enabling the Debug
Registers The core debug can be enabled by setting the
The registers are part of the ARM Cortex-M3 Debug Access C_DEBUGEN bit of the Debug Halting Control and Status
Port (DAP). In the PSoC 5 Cortex-M3, the DAP consists of Register.
the SWD/JTAG Debug Port (SWJ-DP) and the AHB Access
Port (AHB-AP). The registers are listed in Table 41-6 on 43.3.2 Halting
page 451.
The debugger can halt the core by setting the C_DEBUGEN
For further information on these ports and their registers, and C_HALT bits of the Debug Halting Control and Status
see the ARM Debug Interface Architecture Specification (for Register. The core acknowledges when halted by setting the
the SWJ-DP), and the ARM Cortex-M3 Technical Reference S_HALT bit of the Debug Halting Control and Status Regis-
Manual (for the AHB-AP), both available at ter.
http://www.arm.com.
43.3.3 Stepping
43.2.2.2 Test Controller Interface Pins
The core can be single stepped by halting the core, setting
Two Nonvolatile (NV) latch bits determine the state of the the C_STEP bit to ‘1’, and then clearing the C_HALT bit to
JTAG/SWD interface pins at reset. The settings of the bits ‘0’. The core acknowledges completion of the step and re-
are shown in Table 41-8 on page 452. halts by setting the S_HALT bit of the Debug Halting Control
The Single Wire Viewer (SWV) interface consists of a single and Status Register.
output signal (TRACESWO) that shares a pin with the JTAG The core can exit halting debug by clearing the
TDO signal. When the pins are configured for SWD mode, C_DEBUGEN bit in the Debug Halting Control and Status
then SWV is also routed to the TDO/TRACESWO pin. Register.

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Cortex-M3 Debug and Trace

43.3.4 Accessing PSoC Memory and ■ Configuration Register (CFG) – The CFG Register
Registers provides information about the configuration of the
MEM-AP implementation. It indicates whether memory
The Debug Core Register Data Register (DCRDR) and accesses by the MEM-AP are big-endian or little-endian.
Debug Core Register Selection Register (DCRSR) are used
■ Debug Base Address Register (BASE) – The BASE
for accessing the PSoC memory and registers. The register
Register provides an index into the connected memory-
and memory access are 32 bits wide.
mapped resource. This index value points to one of the
To use the registers to read the contents of a register, the following, the start of a set of debug registers or a ROM
following steps should be performed: table that describes the connected debug components.
1. Set the C_DEBUGEN and C_HALT bits of the Debug For more details on the Memory Access Port and registers,
Halting Control and Status Register. This enables the refer to the ARM Debug Interface Architecture Specification,
debug and halts the core. available at http://www.arm.com.
2. Wait for the S_HALT bit of the Debug Halting and Status
Register to be set. This indicates that the core is halted.
3. Write to the DCRSR with bit 16 set to ‘0’, indicating it is a 43.4 System Debug
read operation.
The processor contains several system debug components
4. Poll until the S_REGRDY bit in DHCSR is ‘1’. that facilitate low cost debug, trace and profiling, break-
5. Write the register number to be read into the Debug points, watchpoints and code patching.
Core Register Selector Register.
The system debug components are:
6. Read the value from the Debug Core Register Data Reg-
ister. ❐ Flash Patch and Breakpoint (FPB) unit to implement
breakpoints and code patches.
To write to a register, the following steps should be per-
❐ Data Watchpoint and Trace (DWT) unit to implement
formed:
watchpoints, trigger resources, and system profiling.
1. Make sure the processor is halted by following steps 1 ❐ Instrumentation Trace Macrocell (ITM) for applica-
and 2 mentioned above. tion-driven trace source that supports printf style
2. Write data value to the DCRDR. debugging.
3. Write to the DCRSR with bit 16 set to ‘1’, indicating it is a ❐ Embedded Trace Macrocell (ETM) for instruction
write operation. trace. The processor is supported in versions with
4. Write the register number that you want to write to into and without the ETM.
the DCRSR.
5. Poll until the S_REGRDY bit in DHCSR is ‘1’. When the 43.4.1 Flash Patch and Breakpoint (FPB)
bit becomes ‘1’, the write operation is complete. Unit
The Memory Access Port (MEM-AP) provides access to the The main functions of the FPB are:
memory through the DAP. All accesses to a MEM-AP are
■ Implement hardware breakpoint (generates a breakpoint
made through the MEM-AP registers. All registers are 32
event to the processor to invoke debug modes such as
bits wide. The important registers required for memory
halt or debug monitor).
access include:
■ Patch instruction or data from code memory space to
■ Control/Status Word Register (CSW) – The CSW
SRAM.
Register configures and controls accesses through the
MEM-AP to or from a connected memory system. The FPB unit contains:
■ Transfer Address Register (TAR) – The TAR holds the ■ Two comparators for matching against literal loads from
memory address to be accessed. code space, and remapping to a corresponding area in
■ Data Read/Write Register (DRW) – The DRW holds a system space.
32-bit data value. In write mode, the DRW holds the ■ Six instruction comparators for matching against instruc-
value to write for the current transfer to the address tion fetches from code space, and remapping to a corre-
specified in TAR[31:0]. In read mode, the DRW holds the sponding area in system memory space. Alternatively, it
value read in the current transfer from the address spec- is possible to individually configure the comparators to
ified in TAR[31:0]. return a Breakpoint Instruction (BKPT) to the processor
core upon a match, providing hardware breakpoint capa-
bility.

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 Cortex-M3 Debug and Trace

The FPB has a flash patch control register that contains an 43.4.3 Instrumentation Trace Macrocell
enable bit to enable the FPB. In addition, each comparator (ITM)
comes with a separate enable bit in its comparator control
register. Both of the enable bits must be set to ‘1’ for a com- The ITM is a an application driven trace source that sup-
parator to operate. If the comparison for an entry matches, ports printf style debugging to trace Operating System (OS)
the address is remapped to the address set in the remap and application events, then emit diagnostic system infor-
register plus an offset corresponding to the comparator that mation. The ITM emits trace information as packets. There
matched, or is remapped to a BKPT instruction, if that fea- are three sources that can generate packets. If multiple
ture is enabled. sources generate packets at the same time, the ITM arbi-
trates the order in which packets are output. The three
43.4.2 Data Watchpoint and Trace (DWT) sources in decreasing order of priority are:
■ Software Trace. Software can write directly to ITM stimu-
The DWT has a number of debugging functionalities.
lus registers. This emits packets.
It has four comparators, each of which can be configured as ■ Hardware Trace. The DWT generates these packets,
follows: and the ITM emits them.
■ Hardware watchpoint (generates a watchpoint event to ■ Time Stamping. The ITM can generate timestamp pack-
processor to invoke debug modes such as halt or debug ets that are inserted into a trace stream to help the
monitor) debugger find out the timing of events. The ITM contains
■ ETM trigger (causes the ETM to emit a trigger packet in a 21-bit counter to generate the timestamp. The Cortex-
the instruction trace stream) M3 clock or the bit clock rate of the Serial Wire Viewer
■ PC sampler event trigger (SWV) output clocks the counter.

■ Data address sampler trigger One of the main uses of the ITM is to support printf style
■ The first comparator can also be used to compare debugging. The ITM contains 32 stimulus ports, allowing dif-
against the clock cycle counter instead of comparing to a ferent software processes to output to different ports, and
data address messages that can be separated later at the debug host.
Each port can be enabled or disabled by the Trace Enable
The DWT also has counters for counting: Register (SWV_ITM_TER) and can be programmed (in
■ Clock cycles (CYCCNT) groups of eight ports) to allow or disallow user processes to
■ Folded Instructions: A folded instruction is one that does write to it. The output messages can be collected at the
not incur even one cycle to execute trace port interface or the Serial Wire Viewer (SWV) on the
TPIU.
■ Load Store Unit (LSU) Operations: LSU counts include
all LSU costs after the initial cycle for the instruction The ITM is used in output of hardware trace packets. The
■ Sleep cycles packets are generated from the DWT and the ITM acts as a
trace packet merging unit. To use DWT trace, you need to
■ Cycles per instruction (CPI)
enable the DWTEn bit in the ITM Control Register
■ Interrupt overhead (SWV_ITM_CR).
■ PC sampling at regular intervals to count the number of
ITM has a timestamp feature that allows trace capture tools
core cycles
to find out timing information by inserting delta timestamp
■ Applications and debuggers can use the counter to mea- packets into the traces when a new trace packet enters the
sure elapsed execution time FIFO inside the ITM. The timestamp packet is also gener-
■ Interrupt events trace ated when the timestamp counter overflows.

When used as a hardware watchpoint or ETM trigger, the The timestamp packets provide the time difference (delta)
comparator can be programmed to compare either data with previous events. Using the delta timestamp packets,
addresses or program counters. Otherwise, it compares the the trace capture tools can then establish the timing of when
data addresses. each packet is generated and hence reconstruct the timing
of various debug events.

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Cortex-M3 Debug and Trace

43.4.4 Embedded Trace Macrocell (ETM)

The ETM is an optional debug component that enables reconstruction of program execution. The ETM is designed as a high
speed, low power debug tool that only supports instruction trace. This ensures that area is minimized, and that gate count is
reduced.
The Cortex-M3 system can perform low-bandwidth data tracing using the Data Watchpoint and Trace (DWT) and Instrumen-
tation Trace Macrocell (ITM) components. To enable support of instruction trace with a low pin count, data trace is not
included in the ETM. This considerably reduces gate count for the ETM because the triggering resources are simplified.
Because the ETM does not generate data trace information, the lower bandwidth reduces the requirement for complex trig-
gering capabilities. This means that the ETM does not include the following: internal comparators, counters, and sequencers.
For more details on system debug components and registers, refer to the Definitive Guide To ARM Cortex-M3 and
ARM Cortex-M3 Technical Reference Manual, both available at http://www.arm.com.

43.5 Tracing Interface

The Trace Port Interface Unit (TPIU) consists of SWV and TRACEPORT, which provides trace output from the DWT, ETM,
and ITM. TRACEPORT is faster but uses more pins. SWV is slower but uses only one pin. The SWV and TRACEPORT inter-
faces provide trace data to a debug host via the Cypress MiniProg3 or an external trace port analyzer. The 5-pin TRACE-
PORT is used for rapid transmission of large trace streams. The single pin SWV mode is used to minimize the number of
trace pins. SWV is shared with a JTAG pin.
Figure 43-3. TPIU Block Diagram

ETM TRACECLKIN
ATB ATB Asynchronous
Slave Interface FIFO
Port TRACECLK
Trace Out
Formatter
(serializer)
TRACEDATA
ITM
[3:0]
ATB ATB Asynchronous
Slave Interface FIFO
Port TRACESWO

APB
ATB
Slave
Interface
Port

The following functions are included in the TPIU: ■ APB Interface – The APB interface is the programming
■ Asynchronous FIFO – The asynchronous FIFO enables interface for the TPIU.
trace data to be driven out at a speed that is not depen- ■ TRACECLKIN – Decoupled clock from ATB to enable
dent on the speed of the core clock. easy control of the trace port speed. Typically this is
■ Formatter – The formatter inserts source ID signals into derived from a controllable clock source on-chip. Data
the data packet stream so that trace data can be re- changes on the rising edge only.
associated with its trace source. ■ TRACEPORT – It includes TRACEDATA[3:0] and
■ Trace Out – The trace out block serializes formatted TRACECLK.
data before it goes off-chip. ■ TRACESWO – Trace output pin for SWV.
■ ATB Interface – TPIU accepts trace data from the trace
sources ETM or ITM.

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 Cortex-M3 Debug and Trace

43.5.1 Single Wire Viewer (SWV) Figure 43-4. SPP Register

31 2 1 0
Single Wire viewer (SWV) allows target resident code to
communicate diagnostic information to the outside world NA SPP
through a single pin. The Serial Wire Viewer block is a com-
bination of the Instrumentation Trace Macrocell (ITM) and
the Serial Wire Output (SWO). ITM is a software application SPP DESCRIPTION
trace source.
2'h00 TRACEPORT MODE
The SWV's trace output (TRACESWO) is channeled Single Wire Output (Manchester).
2'h01
through the Test Controller, so that the Test Controller can This is the reset value
output the trace data over the TDO pin when SWD is
2'h10 Single Wire Output (NRZ)
enabled.
SWV can only be used when using the Serial Wire Debug
(SWD) because its trace data is output over the same pin as
43.5.2.2 Communicating with TRACEPORT
JTAG's TDO.
As shown in Figure 43-3 on page 470, the trace data is
43.5.1.1 Enabling SWV passed onto the debug host via the TRACEDATA pins if the
TRACEPORT mode is enabled. The output data on TRACE-
The Trace Enable Register (SWV_ITM_TER) is used to
DATA pins changes on both edges of TRACECLK.
enable the stimulus ports so that trace data can be written
into the stimulus port registers. Each bit in the Trace Enable
Register is set to enable the corresponding stimulus port
43.5.3 Using Multiple Interfaces
register. Also, the ITM should be enabled using the global Simultaneously
enable bit, ITMEn, in the Control Register (SWV_ITM_CR). If debugging and tracing are done at the same time, then
SWD may be used with either SWV or TRACEPORT, or
43.5.1.2 Communicating with SWV JTAG may be used with TRACEPORT, as shown in
Trace data is written into the stimulus port registers Table 43-1.
(SWV_ITM_SPR_DATA [0…31]). Each of the 32 stimulus
Table 43-1. Debug Configuration
ports has its own address. A write to one of these locations
causes data to be written into the FIFO if the corresponding Debug and Trace Configuration GPIO Pins Used
bit in the Trace Enable Register is set. Reading from any of All Debug and Trace Disabled 0
the stimulus ports returns the FIFO status. A '0' is returned if JTAG 4 or 5
the FIFO is full and a '0' is returned otherwise, only if the bit SWD 2
in the Trace Enable Register is set. SWV 1
TRACEPORT 5
43.5.2 TRACEPORT JTAG plus TRACEPORT 9 or 10

TRACEPORT is used for rapid transmission of large trace SWD plus SWV 3
streams. There are five TRACEPORT pins: four data pins, SWV plus TRACEPORT 7
TRACEDATA [3:0] and one clock pin, TRACECLK. TRACE-
PORT supports synchronous mode of operation while
TRACESWO does not.

43.5.2.1 Enabling TRACEPORT

TRACEPORT mode can be enabled using the Select Pin
Protocol Register (SWV_SWO_SPP). The format of the reg-
ister is as shown in Figure 43-4.
As shown in Figure 43-4, TRACEPORT can be enabled by
writing 2'h00 to the SPP[1:0] bits.

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Cortex-M3 Debug and Trace

472 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 44. Nonvolatile Memory Programming

PSoC® 3 and PSoC® 5 devices have three types of nonvolatile memory: Flash, Electronically Erasable Programmable Read
Only Memory (EEPROM), and Nonvolatile Latch (NVL). These can all be programmed by either the CPU running a boot
loader program or by an external system via the JTAG/SWD interface.

44.1 Features
The nonvolatile memory programming system has the following features:
■ Simple command/status register interface
■ Flash can be programmed at the 288-byte row level
■ Each row of Flash has 256 bytes of data plus an additional 32 bytes for ECC/configuration
■ EEPROM can be programmed at the 16-byte row level
■ All configuration NVL bytes can be programmed simultaneously
■ A single write once NVL byte can be programmed

44.2 Block Diagram

Figure 44-1 is a block diagram of the Flash programming system.
Figure 44-1. Flash Block Diagram

Test Controller (TC)

CPU Flash
Debug on-Chip (DOC)

Programming
PHUB
Interface

EEPROM NVL

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 473

Nonvolatile Memory Programming

44.3 How It Works

All programming operations are done through a simple com- 44.3.1 Commands
mand/status register interface summarized in Table 44-1.
Before sending a command to the SPC_CPU_DATA or
Table 44-1. Command and Status Register Summary SPC_DMA_DATA register, the SPC_Idle bit in SPC_SR[1]
must be ‘1’. SPC_Idle will go to ‘0’ when the first byte of a
Register
Size
Description command (0xB6) is written to a data register, and go back to
(Bits) ‘1’ when command execution is complete or an error is
SPC_CPU_DATA 8 Data to/from the CPU detected. Commands sent to either data register while
SPC_DMA_DATA 8 Data to/from the DMAC SPC_Idle is ‘0’ are ignored. All commands must adhere to
the format shown below:
SPC_SR 8 Status – ready, data available, status code
■ Key byte #1 – always 0xB6

Commands and data are sent as a series of bytes to either ■ Key byte #2 – 0xD3 plus the command code (ignore
SPC_CPU_DATA or SPC_DMA_DATA, depending on the overflow)
source of the command. Response data is read via the
■ Command code byte
same register to which the command was sent. The status
register, SPC_SR, indicates whether a new command can ■ Command parameter bytes
be accepted, when data is available for the most recent
■ Command data bytes
command, and a success/failure response for the most
recent command. The command codes are shown in Table 44-2. See 44.3.1.1
Command Code Descriptions on page 475 for details.

Table 44-2. Command Codes

Command
Command Name Memory Type Access Description
Code
0x00 Load byte NVL Any Loads a single byte of data into the volatile latch
0x01 Load multi bytes Flash, EEPROM Any Loads 1 to 32 bytes of data into the row latch
0x02 Load row Flash, EEPROM Any Loads a row of data
0x03 Read byte NVL Any Read a byte from NV memory
0x04 Read multi bytes Flash, EEPROM TC only Reads 1 – 256 data bytes, does not cross row boundaries
0x05 Write row Flash, EEPROM Any Erases then programs a row with data in row latch
0x06 Write NVL NVL TC only Programs all of user NVL with data in the volatile latch
0x07 Program row Flash, EEPROM Any Programs a row with data in row latch
0x08 Erase sector Flash, EEPROM Any Erases a 64-row sector
0x09 Erase all Flash TC only Erases all Flash, including ECC and row protection bytes
0x0B Protect Flash TC only Program Flash protection bits with data in row latch
0x0C Get Checksum Flash Any Computes 4 byte checksum for given memory locations

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 Nonvolatile Memory Programming

Some commands are available only when the device is Some commands use the row latch size for Flash and
being controlled by an external system via the JTAG/SWD EEPROM. Row latch sizes are shown in the following table.
interface and the test controller (see the Test
Controller chapter on page 443). Table 44-4. Row Latch Sizes
Array Type Size (Bytes)
Some commands require an array ID as a parameter. Array
Flash, with ECC Enabled 256
ID codes are shown in Table 44-3.
288
Flash, with ECC Disabled
Table 44-3. Array ID Codes (256 data bytes plus 32 configuration bytes)
EEPROM 16
Array ID
Memory Type
Code
0x00 – 0x3E Single Flash array 44.3.1.1 Command Code Descriptions
0x3F All Flash arrays (used by the Erase All command)
The following are descriptions of the command codes listed
0x40 Single EEPROM array
in Table 44-2 on page 474.
0x80 User NVL array
■ Command 0x00 – Load Byte
0xF8 Write Once NVL array
Command Parameter Bytes – Array ID, Address, Data
A Flash array has, at most, 64 KB plus ECC bytes. PSoC 3 This command loads the given data byte into the volatile
architecture has one Flash array, the size of which is 16 KB, latch for the selected NVL array (in accordance with the
32 KB, or 64 KB plus ECC bytes; therefore, the only valid array ID) at the given address. Only addresses within the
selected NVL array are valid.
array ID is 0x00. PSoC 5 architecture has one or more
arrays, where each array is 64K plus ECC bytes. For exam- ■ Command 0x01 – Load Multiple Bytes
ple, if a PSoC 5 device has 256 KB Flash, there are four Command Parameter Bytes – Array ID, Start address
arrays, and the only valid array IDs are 0x00 – 0x03. high, Start address low, Number of bytes (N), Data0, …,
DataN
An EEPROM array has, at most, 2 KB. PSoC 3 and PSoC 5
This command loads N + 1 given data bytes into a row
devices have one EEPROM array, the size of which is 512
latch for Flash or EEPROM. N may range from 0 to 31
bytes, 1 KB, or 2 KB. for Flash or 0 to 15 for EEPROM. The given start
PSoC 3 and PSoC 5 devices have one user NVL array and address + N must be less than the array row latch size.
one write once NVL array. See Table 44-4.
■ Command 0x02 – Load Row
For commands operating on Flash or EEPROM, all array
Command Parameter Bytes – Array ID, Data0, …,
IDs within the number of Flash and EEPROM arrays are
Data(row latch size -1)
valid. If a non-existent array is selected, the array ID wraps.
For example, if a device has two Flash arrays (IDs = 0 and This command loads the given data bytes into a row
latch for Flash or EEPROM. The number of data bytes
1) and a command is sent with array ID = 3 then the upper
expected equals the row latch size. See Table 44-4.
bits of the ID are truncated and so array ID 1 is selected.
■ Command 0x03 – Read Byte
Some commands require an address as a parameter. As
Command Parameter Bytes – Array ID, Address
with array IDs, any address is valid for a Flash or EEPROM
This command returns a data byte from the selected
array. Upper address bits are truncated to allow only
NVL array (per the array ID), at the given address. Only
addressing of valid locations. For example, if a device has
addresses within the selected NVL array are valid. Note
512 bytes EEPROM and address 0x202 (514) is passed as that when this command is executed all of the data bytes
a parameter, the operation takes place on address 0x002. are transferred from the nonvolatile cells to the volatile
Array IDs and addresses do not wrap for NVL accesses. latch portion of the NVL.
■ Command 0x04 – Read Multiple Bytes
Command Parameter Bytes – Array ID, Start address
high, Start address mid, Start address low, Number of
bytes (N)
This command returns N + 1 data bytes from Flash or
EEPROM, starting at the given address.
In Flash arrays, two address spaces exist – data and
ECC/configuration. Bit 7 of the Address high parameter
selects which of the two address spaces is addressed. If

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Nonvolatile Memory Programming

the bit is 0 then the data space is selected, otherwise the The row must have been previously erased (commands
ECC/configuration space is selected. For example, if the 0x08 and 0x09).
address is 0x80000B and N is 0x08, the command reads For Flash, data bytes and ECC/configuration bytes are
9 ECC/configuration bytes starting at address both programmed. If ECC is enabled, the ECC syn-
0x00000B. drome bytes are automatically generated and loaded
The address plus N must not cross a row boundary – into the ECC/configuration bytes of the row latch before
256 for the Flash data space, 32 for the Flash ECC/con- programming takes place.
figuration space, and 16 for EEPROM. For devices with multiple Flash arrays, the All Flash
Address wrapping applies; if the address is greater than array ID (0x3F) can be used with this command. This
the Flash or EEPROM size, the upper bits are then option causes each Flash array to have its addressed
ignored. For example, 16 bits of address are needed to row programmed with its row latch contents simultane-
access the data space in a 64 KB Flash array, so the ously with the other arrays, reducing the overall Flash
seven LS bits of the Address high parameter are programming time.
ignored. Address 0x045A8B actually addresses ■ Command 0x08 – Erase Sector
0x005A8B.
Command Parameter Bytes – Array ID, Sector ID
Similarly, 13 address bits are needed to access the 8 KB
ECC/configuration space associated with a 64 KB Flash This command erases a sector of Flash/EEPROM. A
array, and 11 address bits are needed to access a 2 KB sector is a block of 64 contiguous rows that starts at a
EEPROM. For example, for a 64 KB Flash array (which 64-row boundary. For Flash arrays, all associated ECC/
also has 8 KB ECC/configuration bytes), valid address configuration bytes are also erased. The sector ID wraps
ranges are: if it exceeds the number of sectors.
■ Command 0x09 – Erase All
❐ Data space – 0x000000 – 0x00FFFF (64 KB)
❐ ECC/configuration space – 0x800000 – 0x801FFF Command Parameter Bytes – None
(8 KB) This command erases all Flash data and ECC/configura-
■ Command 0x05 – Write Row tion bytes, all Flash protection rows, and all row latches
in all Flash arrays on the device.
Command Parameter Bytes – Array ID, Row ID high,
■ Command 0x0B – Protect
Row ID low, Temperature sign, Temperature magnitude
This command erases the addressed Flash/EEPROM Command Parameter Bytes – Array ID, Row Select
row and then programs it with the data in the row latch. If This command programs a Flash protection row with
the row ID is greater than the array size (in rows), then data in the Flash row latch (see 44.3.3 Flash Protection
the row ID wraps (the upper bits are ignored). Settings on page 477). This command can be executed
For Flash, data bytes and ECC/configuration bytes are only if none of the protection bits are currently set – no
both programmed. If ECC is enabled then the ECC syn- Flash protection. Any bytes of the protection row that are
drome bytes are automatically generated and loaded marked as unused space are programmed with 0x00.
into the ECC/configuration bytes of the row latch before This occurs regardless of what values are loaded into
programming takes place. the row latches prior to sending this command.
The die temperature parameters can be acquired by The Row Select parameter is used for Flash arrays that
sending the Get Temperature command (see the Tem- have a row size less than 256 bytes. Because all Flash
perature Sensor chapter on page 403). arrays have 256-byte rows, this parameter should
always be 0x00.
■ Command 0x06 – Write User NVL
When the Flash protection data is programmed, this
Command Parameter Bytes – Array ID command cannot be sent again until an Erase All com-
This command writes all of the bytes in the volatile latch mand is sent first.
for the selected NVL array (per the array ID) to that NVL For devices with multiple Flash arrays, the All Flash
array. All Flash protection bits must be cleared (no Flash array ID (0x3F) may be used with this command. This
protection) or the command fails. causes each Flash array to have its protection row pro-
■ Command 0x07 – Program Row grammed with its row latch contents, simultaneously with
Command Parameter Bytes – Array ID, Row ID high, the other arrays, reducing the overall Flash program-
Row ID low ming time.
This command programs the addressed Flash/EEPROM ■ Command 0x0C – Get Checksum
row with the data in the row latch. If the row ID is greater Command Parameter Bytes – Array ID, Start row high,
than the array size (in rows), the row ID wraps (the upper Start row low, Number of rows high, Number of rows low
bits are ignored). This command computes a 4-byte checksum for the
given number of Flash rows + 1, starting at the given

476 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Nonvolatile Memory Programming

row. The checksum is computed by a running simple 44.3.3 Flash Protection Settings
addition of all values in the rows. If ECC is disabled, the
computation includes all data from the user space and Each row of Flash has its own protection settings. For each
the ECC / configuration space. If ECC is enabled, the Flash array, Flash protection bits are stored in a “hidden”
computation includes only data from the user space. row in that array. A hidden row is one that is not readable by
the CPU, and contains no CPU program or data bytes. In
If the array ID is All Flash, the checksum computed includes
the hidden row, two bits per Flash row are packed into a
all Flash data on all Flash arrays on the device. The rest of
byte; therefore, each byte in the hidden row has protection
the command parameters are ignored. The checksum value
settings for four Flash rows. As shown in Figure 44-2, the
is returned MS byte first.
Flash rows are ordered so that the first two bits in the hidden
44.3.1.2 Command Failure Codes row correspond to the protection settings of Flash row 0.

In response to commands, a success/failure code is Protection is cumulative in that modes have successively
returned in the SPC_SR register: These codes are higher protection levels and include the lower protection
described in Table 44-5. modes. The following table shows the protection modes.

Table 44-5. Command Failure Codes Table 44-6. Protection Modes

External Internal
Success/Failure Mode Description Reada
Code (Bits[7:2] in Meaning Writeb Writec
SPC_SR register) 00 Unprotected Yes Yes Yes
0x00 Command successfully executed 01 Read Protect No Yes Yes
0x01 Invalid array ID 10 Disable External Write No No Yes
0x02 Invalid key 11 Disable Internal Write No No No
0x03 Array is asleep a. Read – Applies to Test Controller and Read Commands.
External access failure: command must be sent b. External Write – Test Controller/third-party programmers.
0x04 c. Internal Write – Boot loading or writes due to firmware execution.
via test controller
0x05 Invalid ‘N’ value
When a read/write/erase operation is to be done for a row,
0x07, 0x08 Program/Erase failure
the corresponding protection bits are checked. The com-
Protection check failure: protection settings are in
0x09 mand is executed only if allowed under the current protec-
a state that prevents the command from executing
0x0A Invalid address tion mode. If the command is not allowed, the command
0x0B Invalid command code
then fails.
0x0C Invalid row ID

44.3.2 Register Summary

All programming operations are done through a simple com-
mand/status register interface, shown in Table 44-1 on
page 474.

Figure 44-2. Flash Protection Bits

Page 0 Bits Page 1 Bits Page 2 Bits Page 3 Bits Page 255 Bits
[1:0] [1:0] [1:0] [1:0] ...... [1:0]

Byte 0 in Flash Hidden Row 0:

Contains protection data for Flash rows 0 through 3.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 477

Nonvolatile Memory Programming

478 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Glossary

The Glossary section explains the terminology used in this technical reference manual. Glossary terms are characterized in
bold, italic font throughout the text of this manual.

accumulator In a CPU, a register in which intermediate results are stored. Without an accumulator, it would be
necessary to write the result of each calculation (addition, subtraction, shift, and so on.) to main
memory and read them back. Access to main memory is slower than access to the accumulator,
which usually has direct paths to and from the arithmetic and logic unit (ALU).

active high 1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.

active low 1. A logic signal having its asserted state as the logic 0 state.
2. A logic signal having its logic 1 state as the lower voltage of the two states: inverted logic.

address The label or number identifying the memory location (RAM, ROM, or register) where a unit of
information is stored.

algorithm A procedure for solving a mathematical problem in a finite number of steps that frequently
involve repetition of an operation.

ambient temperature The temperature of the air in a designated area, particularly the area surrounding the PSoC
device.

analog See analog signals.

analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous
time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain
stages, and much more.

analog output An output that is capable of driving any voltage between the supply rails, instead of just a logic 1
or logic 0.

analog signals A signal represented in a continuous form with respect to continuous times, as contrasted with a
digital signal represented in a discrete (discontinuous) form in a sequence of time.

analog-to-digital (ADC) A device that changes an analog signal to a digital signal of corresponding magnitude. Typically,
an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs
the reverse operation.

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 479

Glossary

AND See Boolean Algebra.

API (Application Pro- A series of software routines that comprise an interface between a computer application and
gramming Interface) lower-level services and functions (for example, user modules and libraries). APIs serve as build-
ing blocks for programmers that create software applications.

array An array, also known as a vector or list, is one of the simplest data structures in computer pro-
gramming. Arrays hold a fixed number of equally-sized data elements, generally of the same
data type. Individual elements are accessed by index using a consecutive range of integers, as
opposed to an associative array. Most high level programming languages have arrays as a built-
in data type. Some arrays are multi-dimensional, meaning they are indexed by a fixed number of
integers; for example, by a group of two integers. One- and two-dimensional arrays are the most
common. Also, an array can be a group of capacitors or resistors connected in some common
form.

assembly A symbolic representation of the machine language of a specific processor. Assembly language
is converted to machine code by an assembler. Usually, each line of assembly code produces
one machine instruction, though the use of macros is common. Assembly languages are consid-
ered low level languages; where as C is considered a high level language.

asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock sig-
nal.

attenuation The decrease in intensity of a signal as a result of absorption of energy and of scattering out of
the path to the detector, but not including the reduction due to geometric spreading. Attenuation
is usually expressed in dB.

bandgap reference A stable voltage reference design that matches the positive temperature coefficient of VT with the
negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) refer-
ence.

bandwidth 1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maxi-
mum.

bias 1. A systematic deviation of a value from a reference value.

2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a
reference level to operate the device.

bias current The constant low level DC current that is used to produce a stable operation in amplifiers. This
current can sometimes be changed to alter the bandwidth of an amplifier.

480 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Glossary

binary The name for the base 2 numbering system. The most common numbering system is the base
10 numbering system. The base of a numbering system indicates the number of values that may
exist for a particular positioning within a number for that system. For example, in base 2, binary,
each position may have one of two values (0 or 1). In the base 10, decimal, numbering system,
each position may have one of ten values (0, 1, 2, 3, 4, 5, 6, 7, 8, and 9).

bit A single digit of a binary number. Therefore, a bit may only have a value of ‘0’ or ‘1’. A group of 8
bits is called a byte. Because the PSoC's M8CP is an 8-bit microcontroller, the PSoC devices's
native data chunk size is a byte.

bit rate (BR) The number of bits occurring per unit of time in a bit stream, usually expressed in bits per second
(bps).

block 1. A functional unit that performs a single function, such as an oscillator.

2. A functional unit that may be configured to perform one of several functions, such as a digital
PSoC block or an analog PSoC block.

Boolean Algebra In mathematics and computer science, Boolean algebras or Boolean lattices, are algebraic struc-
tures which "capture the essence" of the logical operations AND, OR and NOT as well as the set
theoretic operations union, intersection, and complement. Boolean algebra also defines a set of
theorems that describe how Boolean equations can be manipulated. For example, these theo-
rems are used to simplify Boolean equations, which will reduce the number of logic elements
needed to implement the equation.
The operators of Boolean algebra may be represented in various ways. Often they are simply
written as AND, OR, and NOT. In describing circuits, NAND (NOT AND), NOR (NOT OR), XNOR
(exclusive NOT OR), and XOR (exclusive OR) may also be used. Mathematicians often use +
(for example, A+B) for OR and for AND (for example, A*B) (since in some ways those opera-
tions are analogous to addition and multiplication in other algebraic structures) and represent
NOT by a line drawn above the expression being negated (for example, ~A, A_, !A).

break-before-make The elements involved go through a disconnected state entering (‘break”) before the new con-
nected state (“make”).

broadcast net A signal that is routed throughout the microcontroller and is accessible by many blocks or sys-
tems.

buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring
data from one device to another. Usually refers to an area reserved for I/O operations, into
which data is read, or from which data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as
it is received from an external device.
3. An amplifier used to lower the output impedance of a system.

bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets
with similar routing patterns.
2. A set of signals performing a common function and carrying similar data. Typically repre-
sented using vector notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.

byte A digital storage unit consisting of 8 bits.

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Glossary

C A high level programming language.

capacitance A measure of the ability of two adjacent conductors, separated by an insulator, to hold a charge
when a voltage differential is applied between them. Capacitance is measured in units of Farads.

capture To extract information automatically through the use of software or hardware, as opposed to
hand-entering of data into a computer file.

chaining Connecting two or more 8-bit digital blocks to form 16-, 24-, and even 32-bit functions. Chaining
allows certain signals such as Compare, Carry, Enable, Capture, and Gate to be produced from
one block to another.

checksum The checksum of a set of data is generated by adding the value of each data word to a sum. The
actual checksum can simply be the result sum or a value that must be added to the sum to gen-
erate a pre-determined value.

clear To force a bit/register to a value of logic ‘0’.

clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is
sometimes used to synchronize different logic blocks.

clock generator A circuit that is used to generate a clock signal.

CMOS The logic gates constructed using MOS transistors connected in a complementary manner.
CMOS is an acronym for complementary metal-oxide semiconductor.

comparator An electronic circuit that produces an output voltage or current whenever two input levels simul-
taneously satisfy predetermined amplitude requirements.

compiler A program that translates a high level language, such as C, into machine language.

configuration In a computer system, an arrangement of functional units according to their nature, number, and
chief characteristics. Configuration pertains to hardware, software, firmware, and documentation.
The configuration will affect system performance.

configuration space In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to
‘1’.

crowbar A type of over-voltage protection that rapidly places a low resistance shunt (typically an SCR)
from the signal to one of the power supply rails, when the output voltage exceeds a predeter-
mined value.

crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelec-
tric crystal is less sensitive to ambient temperature than other circuit components.

cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear
check (CRC) feedback shift register. Similar calculations may be used for a variety of other purposes such as
data compression.

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 Glossary

data bus A bi-directional set of signals used by a computer to convey information from a memory location
to the central processing unit and vice versa. More generally, a set of signals used to convey
data between digital functions.

data stream A sequence of digitally encoded signals used to represent information in transmission.

data transmission The sending of data from one place to another by means of signals over a channel.

debugger A hardware and software system that allows the user to analyze the operation of the system
under development. A debugger usually allows the developer to step through the firmware one
step at a time, set break points, and analyze memory.

dead band A period of time when neither of two or more signals are in their active state or in transition.

decimal A base-10 numbering system, which uses the symbols 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9 (called digits)
together with the decimal point and the sign symbols + (plus) and - (minus) to represent num-
bers.

default value Pertaining to the pre-defined initial, original, or specific setting, condition, value, or action a sys-
tem will assume, use, or take in the absence of instructions from the user.

device The device referred to in this manual is the PSoC device, unless otherwise specified.

die An unpackaged integrated circuit (IC), normally cut from a wafer.

digital A signal or function, the amplitude of which is characterized by one of two discrete values: ‘0’ or
‘1’.

digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC gen-
erator, pseudo-random number generator, or SPI.

digital logic A methodology for dealing with expressions containing two-state variables that describe the
behavior of a circuit or system.

digital-to-analog (DAC) A device that changes a digital signal to an analog signal of corresponding magnitude. The ana-
log-to-digital (ADC) converter performs the reverse operation.

direct access The capability to obtain data from a storage device, or to enter data into a storage device, in a
sequence independent of their relative positions by means of addresses that indicate the physi-
cal location of the data.

duty cycle The relationship of a clock period high time to its low time, expressed as a percent.

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Glossary

emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that
the second system appears to behave like the first system.

External Reset An active high signal that is driven into the PSoC device. It causes all operation of the CPU and
(XRES_N) blocks to stop and return to a pre-defined state.

falling edge A transition from a logic 1 to a logic 0. Also known as a negative edge.

feedback The return of a portion of the output, or processed portion of the output, of a (usually active)
device to the input.

filter A device or process by which certain frequency components of a signal are attenuated.

firmware The software that is embedded in a hardware device and executed by the CPU. The software
may be executed by the end user, but it may not be modified.

flag Any of various types of indicators used for identification of a condition or event (for example, a
character that signals the termination of a transmission).

Flash An electrically programmable and erasable, volatile technology that provides users with the pro-
grammability and data storage of EPROMs, plus in-system erasability. Nonvolatile means that
the data is retained when power is off.

Flash bank A group of Flash ROM blocks where Flash block numbers always begin with ‘0’ in an individual
Flash bank. A Flash bank also has its own block level protection information.

Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest
amount of Flash space that may be protected. A Flash block holds 64 bytes.

flip-flop A device having two stable states and two input terminals (or types of input signals) each of
which corresponds with one of the two states. The circuit remains in either state until it is made to
change to the other state by application of the corresponding signal.

frequency The number of cycles or events per unit of time, for a periodic function.

gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively.
Gain is usually expressed in dB.

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 Glossary

gate 1. A device having one output channel and one or more input channels, such that the output
channel state is completely determined by the input channel states, except during switching
transients.
2. One of many types of combinational logic elements having at least two inputs (for example,
AND, OR, NAND, and NOR (also see Boolean Algebra)).

ground 1. The electrical neutral line having the same potential as the surrounding earth.
2. The negative side of DC power supply.
3. The reference point for an electrical system.
4. The conducting paths between an electric circuit or equipment and the earth, or some con-
ducting body serving in place of the earth.

hardware A comprehensive term for all of the physical parts of a computer or embedded system, as distin-
guished from the data it contains or operates on, and the software that provides instructions for
the hardware to accomplish tasks.

hardware reset A reset that is caused by a circuit, such as a POR, watchdog reset, or external reset. A hardware
reset restores the state of the device as it was when it was first powered up. Therefore, all regis-
ters are set to the POR value as indicated in register tables throughout this document.

hexadecimal A base 16 numeral system (often abbreviated and called hex), usually written using the symbols
0-9 and A-F. It is a useful system in computers because there is an easy mapping from four bits
to a single hex digit. Thus, one can represent every byte as two consecutive hexadecimal digits.
Compare the binary, hex, and decimal representations:
bin = hex = dec
0000b = 0x0 = 0
0001b = 0x1 = 1
0010b = 0x2 = 2
...
1001b = 0x9 = 9
1010b = 0xA = 10
1011b = 0xB = 11
...
1111b = 0xF = 15
So the decimal numeral 79 whose binary representation is 0100 1111b can be written as 4Fh in
hexadecimal (0x4F).

high time The amount of time the signal has a value of ‘1’ in one period, for a periodic digital signal.

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Glossary

I2C A two-wire serial computer bus by Phillips Semiconductors (now NXP Semiconductors). I2C is an
Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The
original system was created in the early 1980s as a battery control interface, but it was later used
as a simple internal bus system for building control electronics. I2C uses only two bidirectional
pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100
Kbps in standard mode and 400 Kbps in fast mode.

ICE The in-circuit emulator that allows users to test the project in a hardware environment, while
viewing the debugging device activity in a software environment (PSoC Designer™).

idle state A condition that exists whenever user messages are not being transmitted, but the service is
immediately available for use.

impedance 1. The resistance to the flow of current caused by resistive, capacitive, or inductive devices in a
circuit.
2. The total passive opposition offered to the flow of electric current. Note the impedance is
determined by the particular combination of resistance, inductive reactance, and capacitive
reactance in a given circuit.

input A point that accepts data, in a device, process, or channel.

input/output (I/O) A device that introduces data into or extracts data from a system.

instruction An expression that specifies one operation and identifies its operands, if any, in a programming
language such as C or assembly.

instruction mnemonics A set of acronyms that represent the opcodes for each of the assembly-language instructions, for
example, ADD, SUBB, MOV.

integrated circuit (IC) A device in which components such as resistors, capacitors, diodes, and transistors are formed
on the surface of a single piece of semiconductor.

interface The means by which two systems or devices are connected and interact with each other.

interrupt A suspension of a process, such as the execution of a computer program, caused by an event
external to that process, and performed in such a way that the process can be resumed.

interrupt service rou- A block of code that normal code execution is diverted to when the M8CP receives a hardware
tine (ISR) interrupt. Many interrupt sources may each exist with its own priority and individual ISR code
block. Each ISR code block ends with the RETI instruction, returning the device to the point in
the program where it left normal program execution.

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 Glossary

jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption
that occurs on serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the inter-
val between successive pulses, the amplitude of successive cycles, or the frequency or
phase of successive cycles.

keeper A circuit that holds a signal to the last driven value, even when the signal becomes un-driven.

latency The time or delay that it takes for a signal to pass through a given circuit or network.

least significant bit The binary digit, or bit, in a binary number that represents the least significant value (typically the
(LSb) right-hand bit). The bit versus byte distinction is made by using a lower case “b” for bit in LSb.

least significant byte The byte in a multi-byte word that represents the least significant values (typically the right-hand
(LSB) byte). The byte versus bit distinction is made by using an upper case “B” for byte in LSB.

Linear Feedback Shift A shift register whose data input is generated as an XOR of two or more elements in the register
Register (LFSR) chain.

load The electrical demand of a process expressed as power (watts), current (amps), or resistance
(ohms).

logic function A mathematical function that performs a digital operation on digital data and returns a digital
value.

lookup table (LUT) A logic block that implements several logic functions. The logic function is selected by means of
select lines and is applied to the inputs of the block. For example: A 2 input LUT with 4 select
lines can be used to perform any one of 16 logic functions on the two inputs resulting in a single
logic output. The LUT is a combinational device; therefore, the input/output relationship is contin-
uous, that is, not sampled.

low time The amount of time the signal has a value of ‘0’ in one period, for a periodic digital signal.

low voltage detect A circuit that senses Vddd and provides an interrupt to the system when Vddd falls below a
(LVD) selected threshold.

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Glossary

M8CP An 8-bit Harvard Architecture microprocessor. The microprocessor coordinates all activity inside
a PSoC device by interfacing to the Flash, SRAM, and register space.

macro A programming language macro is an abstraction, whereby a certain textual pattern is replaced
according to a defined set of rules. The interpreter or compiler automatically replaces the macro
instance with the macro contents when an instance of the macro is encountered. Therefore, if a
macro is used five times and the macro definition required 10 bytes of code space, 50 bytes of
code space will be needed in total.

mask 1. To obscure, hide, or otherwise prevent information from being derived from a signal. It is usu-
ally the result of interaction with another signal, such as noise, static, jamming, or other forms
of interference.
2. A pattern of bits that can be used to retain or suppress segments of another pattern of bits, in
computing and data processing systems.

master device A device that controls the timing for data exchanges between two devices. Or when devices are
cascaded in width, the master device is the one that controls the timing for data exchanges
between the cascaded devices and an external interface. The controlled device is called the
slave device.

microcontroller An integrated circuit device that is designed primarily for control systems and products. In addi-
tion to a CPU, a microcontroller typically includes memory, timing circuits, and I/O circuitry. The
reason for this is to permit the realization of a controller with a minimal quantity of devices, thus
achieving maximal possible miniaturization. This in turn, will reduce the volume and the cost of
the controller. The microcontroller is normally not used for general-purpose computation as is a
microprocessor.

mnemonic A tool intended to assist the memory. Mnemonics rely on not only repetition to remember facts,
but also on creating associations between easy-to-remember constructs and lists of data. A two
to four character string representing a microprocessor instruction.

mode A distinct method of operation for software or hardware. For example, the Digital PSoC block
may be in either counter mode or timer mode.

modulation A range of techniques for encoding information on a carrier signal, typically a sine-wave signal. A
device that performs modulation is known as a modulator.

Modulator A device that imposes a signal on a carrier.

MOS An acronym for metal-oxide semiconductor.

most significant bit The binary digit, or bit, in a binary number that represents the most significant value (typically the
(MSb) left-hand bit). The bit versus byte distinction is made by using a lower case “b” for bit in MSb.

most significant byte The byte in a multi-byte word that represents the most significant values (typically the left-hand
(MSB) byte). The byte versus bit distinction is made by using an upper case “B” for byte in MSB.

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 Glossary

multiplexer (mux) 1. A logic function that uses a binary value, or address, to select between a number of inputs
and conveys the data from the selected input to the output.
2. A technique which allows different input (or output) signals to use the same lines at different
times, controlled by an external signal. Multiplexing is used to save on wiring and I/O ports.

NAND See Boolean Algebra.

negative edge A transition from a logic 1 to a logic 0. Also known as a falling edge.

net The routing between devices.

nibble A group of four bits, which is one-half of a byte.

noise 1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current,
or data.

NOR See Boolean Algebra.

NOT See Boolean Algebra.

OR See Boolean Algebra.

oscillator A circuit that may be crystal controlled and is used to generate a clock frequency.

output The electrical signal or signals which are produced by an analog or digital block.

parallel The means of communication in which digital data is sent multiple bits at a time, with each simul-
taneous bit being sent over a separate line.

parameter Characteristics for a given block that have either been characterized or may be defined by the
designer.

parameter block A location in memory where parameters for the SSC instruction are placed prior to execution.

parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the
sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).

path 1. The logical sequence of instructions executed by a computer.

2. The flow of an electrical signal through a circuit.

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Glossary

pending interrupts An interrupt that has been triggered but has not been serviced, either because the processor is
busy servicing another interrupt or global interrupts are disabled.

phase The relationship between two signals, usually the same frequency, that determines the delay
between them. This delay between signals is either measured by time or angle (degrees).

Phase-Locked Loop An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative
(PLL) to a reference signal.

pin A terminal on a hardware component. Also called lead.

pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC
device and their physical counterparts in the printed circuit board (PCB) package. Pinouts will
involve pin numbers as a link between schematic and PCB design (both being computer gener-
ated files) and may also involve pin names.

port A group of pins, usually eight.

positive edge A transition from a logic 0 to a logic 1. Also known as a rising edge.

posted interrupts An interrupt that has been detected by the hardware but may or may not be enabled by its mask
bit. Posted interrupts that are not masked become pending interrupts.

Power On Reset (POR) A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is
one type of hardware reset.

program counter The instruction pointer (also called the program counter) is a register in a computer processor
that indicates where in memory the CPU is executing instructions. Depending on the details of
the particular machine, it holds either the address of the instruction being executed, or the
address of the next instruction to be executed.

protocol A set of rules. Particularly the rules that govern networked communications.

PSoC® Cypress’s Programmable System-on-Chip (PSoC®) devices.

PSoC blocks See analog blocks and digital blocks.

PSoC Creator™ The software for Cypress’s next generation Programmable System-on-Chip technology.

PSoC Designer™ The software for Cypress’s Programmable System-on-Chip technology.

pulse A rapid change in some characteristic of a signal (for example, phase or frequency), from a base-
line value to a higher or lower value, followed by a rapid return to the baseline value.

pulse-width modulator An output in the form of duty cycle which varies as a function of the applied measurand.
(PWM)

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 Glossary

RAM An acronym for random access memory. A data-storage device from which data can be read out
and new data can be written in.

register A storage device with a specific capacity, such as a bit or byte.

reset A means of bringing a system back to a know state. See hardware reset and software reset.

resistance The resistance to the flow of electric current measured in ohms for a conductor.

revision ID A unique identifier of the PSoC device.

ripple divider An asynchronous ripple counter constructed of flip-flops. The clock is fed to the first stage of the
counter. An n-bit binary counter consisting of n flip-flops that can count in binary from 0 to 2n - 1.

rising edge See positive edge.

ROM An acronym for read only memory. A data-storage device from which data can be read out, but
new data cannot be written in.

routine A block of code, called by another block of code, that may have some general or frequent use.

routing Physically connecting objects in a design according to design rules set in the reference library.

runt pulses In digital circuits, narrow pulses that, due to non-zero rise and fall times of the signal, do not
reach a valid high or low level. For example, a runt pulse may occur when switching between
asynchronous clocks or as the result of a race condition in which a signal takes two separate
paths through a circuit. These race conditions may have different delays and are then recom-
bined to form a glitch or when the output of a flip-flop becomes metastable.

sampling The process of converting an analog signal into a series of digital values or reversed.

schematic A diagram, drawing, or sketch that details the elements of a system, such as the elements of an
electrical circuit or the elements of a logic diagram for a computer.

seed value An initial value loaded into a linear feedback shift register or random number generator.

serial 1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a
single device or channel.

set To force a bit/register to a value of logic 1.

settling time The time it takes for an output signal or value to stabilize after the input has changed from one
value to another.

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Glossary

shift The movement of each bit in a word one position to either the left or right. For example, if the hex
value 0x24 is shifted one place to the left, it becomes 0x48. If the hex value 0x24 is shifted one
place to the right, it becomes 0x12.

shift register A memory storage device that sequentially shifts a word either left or right to output a stream of
serial data.

sign bit The most significant binary digit, or bit, of a signed binary number. If set to a logic 1, this bit rep-
resents a negative quantity.

signal A detectable transmitted energy that can be used to carry information. As applied to electronics,
any transmitted electrical impulse.

silicon ID A unique identifier of the PSoC silicon.

skew The difference in arrival time of bits transmitted at the same time, in parallel transmission.

slave device A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.

software A set of computer programs, procedures, and associated documentation concerned with the
operation of a data processing system (for example, compilers, library routines, manuals, and
circuit diagrams). Software is often written first as source code, and then converted to a binary
format that is specific to the device on which the code will be executed.

software reset A partial reset executed by software to bring part of the system back to a known state. A software
reset will restore the M8CP to a know state but not PSoC blocks, systems, peripherals, or regis-
ters. For a software reset, the CPU registers (CPU_A, CPU_F, CPU_PC, CPU_SP, and CPU_X)
are set to 0x00. Therefore, code execution will begin at Flash address 0x0000.

SRAM An acronym for static random access memory. A memory device allowing users to store and
retrieve data at a high rate of speed. The term static is used because, once a value has been
loaded into an SRAM cell, it will remain unchanged until it is explicitly altered or until power is
removed from the device.

SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be
accessed in normal user code, operating from Flash.

stack A stack is a data structure that works on the principle of Last In First Out (LIFO). This means that
the last item put on the stack is the first item that can be taken off.

stack pointer A stack may be represented in a computer’s inside blocks of memory cells, with the bottom at a
fixed location and a variable stack pointer to the current top cell.

state machine The actual implementation (in hardware or software) of a function that can be considered to con-
sist of a set of states through which it sequences.

sticky A bit in a register that maintains its value past the time of the event that caused its transition, has
passed.

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 Glossary

stop bit A signal following a character or block that prepares the receiving device to receive the next
character or block.

switching The controlling or routing of signals in circuits to execute logical or arithmetic operations, or to
transmit data between specific points in a network.

switch phasing The clock that controls a given switch, PHI1 or PHI2, in respect to the switch capacitor (SC)
blocks. The PSoC SC blocks have two groups of switches. One group of these switches is nor-
mally closed during PHI1 and open during PHI2. The other group is open during PHI1 and closed
during PHI2. These switches can be controlled in the normal operation, or in reverse mode if the
PHI1 and PHI2 clocks are reversed.

synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock
signal.
2. A system whose operation is synchronized by a clock signal.

tap The connection between two blocks of a device created by connecting several blocks/compo-
nents in a series, such as a shift register or resistive voltage divider.

terminal count The state at which a counter is counted down to zero.

threshold The minimum value of a signal that can be detected by the system or sensor under consider-
ation.

Thumb-2 The Thumb-2 instruction set is a highly efficient and powerful instruction set that delivers signifi-
cant benefits in terms of ease of use, code size, and performance. The Thumb-2 instruction set is
a superset of the previous 16-bit Thumb instruction set, with additional 16-bit instructions along-
side 32-bit instructions.

transistors The transistor is a solid-state semiconductor device used for amplification and switching, and
has three terminals: a small current or voltage applied to one terminal controls the current
through the other two. It is the key component in all modern electronics. In digital circuits, transis-
tors are used as very fast electrical switches, and arrangements of transistors can function as
logic gates, RAM-type memory, and other devices. In analog circuits, transistors are essentially
used as amplifiers.

tristate A function whose output can adopt three states: 0, 1, and Z (high impedance). The function does
not drive any value in the Z state and, in many respects, may be considered to be disconnected
from the rest of the circuit, allowing another output to drive the same net.

UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data
and serial bits.

user The person using the PSoC device and reading this manual.

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Glossary

user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and
configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high
level API (Application Programming Interface) for the peripheral function.

user space The bank 0 space of the register map. The registers in this bank are more likely to be modified
during normal program execution and not just during initialization. Registers in bank 1 are most
likely to be modified only during the initialization phase of the program.

Vddd A name for a power net meaning "voltage drain." The most positive power supply signal. Usually
5 or 3.3 volts.

volatile Not guaranteed to stay the same value or level when not in scope.

Vss A name for a power net meaning "voltage source." The most negative power supply signal.

watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU will reset after a specified
period of time.

waveform The representation of a signal as a plot of amplitude versus time.

XOR See Boolean Algebra.

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 Index

Numerics A
24-bit data pointer registers ACC (SFR 0xE0) register . . . . . . . . . . . . . . . . . . . . . . . .40
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 active interrupt
32.768 kHz crystal oscillator . . . . . . . . . . . . . . . . . . . . 151 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
50% duty cycle mode . . . . . . . . . . . . . . . . . . . . . . . . . 157 PSoC 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 active mode
24-bit data pointer registers . . . . . . . . . . . . . . . . . . 64 entering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
active interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 exiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . 40 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . .171
arithmetic logic unit . . . . . . . . . . . . . . . . . . . . . . . . 40 PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
bit addressing mode . . . . . . . . . . . . . . . . . . . . . . . . 39 active mode boost converter . . . . . . . . . . . . . . . . . . . . .166
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 alternative active mode . . . . . . . . . . . . . . . . . . . . . . . . .171
boolean instructions . . . . . . . . . . . . . . . . . . . . . . . . 43 entering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
core enhancements . . . . . . . . . . . . . . . . . . . . . . . . 38 exiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
DPTR extension SFR . . . . . . . . . . . . . . . . . . . 38 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . .171
Dual DPTR . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 analog I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
vectored interrupt controller interface . . . . . . . 38 analog subsystem
CPU halt mechanisms . . . . . . . . . . . . . . . . . . . . . . 66 PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
CY wrapper logic . . . . . . . . . . . . . . . . . . . . . . . . . . 39 analog subsystem components
data transfer instructions . . . . . . . . . . . . . . . . . . . . 42 PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
direct addressing mode . . . . . . . . . . . . . . . . . . . . . 39 analog system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
dual data pointer registers . . . . . . . . . . . . . . . . . . . 63 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
external data memory space . . . . . . . . . . . . . . . . . 66 application diagram
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . .166
how it works . . . . . . . . . . . . . . . . . . . . . . . . . . 38, 413 arithmetic instructions
immediate constants mode . . . . . . . . . . . . . . . . . . 39 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
indirect addressing mode . . . . . . . . . . . . . . . . . . . . 39 arithmetic logic unit
instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . 38, 39 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
instruction set details . . . . . . . . . . . . . . . . . . . . . . . 44 asynchronous clocks . . . . . . . . . . . . . . . . . . . . . . . . . .160
internal data space . . . . . . . . . . . . . . . . . . . . . . . . . 39
interrupt controller interface . . . . . . . . . . . . . . . . . . 38
interrupt enable register . . . . . . . . . . . . . . . . . . . . . 65 B
interrupt nesting . . . . . . . . . . . . . . . . . . . . . . . . . . 112
B (SFR 0xF0) register . . . . . . . . . . . . . . . . . . . . . . . . . . .40
interrupt vector addresses . . . . . . . . . . . . . . . . . . 113
BASEPRI special register in PSoC 5
IO port access registers . . . . . . . . . . . . . . . . . . . . . 65
PSoC 5
jump instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 43
BASEPRI special register . . . . . . . . . . . . . . . .117
logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . 41
bit addressing mode
memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
program branching instructions . . . . . . . . . . . . . . . 43
block diagram
program memory space . . . . . . . . . . . . . . . . . . . . . 66
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
PSoC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
cache controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
register addressing mode . . . . . . . . . . . . . . . . . . . . 39
clock distribution system . . . . . . . . . . . . . . . . . . . .154
register specific instructions mode . . . . . . . . . . . . . 39
clock divider Implementation . . . . . . . . . . . . . . . . .157
special function registers . . . . . . . . . . . . . . . . . . . . 62
clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
wrapper logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Cortex-M3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
CY8C38 family SRAM accesses . . . . . . . . . . . . . .125

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 495

Index

CY8C55 family SRAM accesses . . . . . . . . . . . . . . 127 clock selection

debug and trace . . . . . . . . . . . . . . . . . . . . . . . . . . 466 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 clock selection by timer block . . . . . . . . . . . . . . . . . . . 296
external memory interface . . . . . . . . . . . . . . . . . . . 133 clock signal naming . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Flash programming system . . . . . . . . . . . . . . . . . . 129 clock source
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 selection by timer block . . . . . . . . . . . . . . . . . . . . 296
I/O drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 clock sources
internal low speed oscillator . . . . . . . . . . . . . . . . . 150 distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
internal main oscillator . . . . . . . . . . . . . . . . . . . . . 149 DSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
internal SRAM organization for the CY8C55 family 127 internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . 107 phase-locked loop . . . . . . . . . . . . . . . . . . . . . . . . 153
master clock mux . . . . . . . . . . . . . . . . . . . . . . . . . 155 clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . 158
MHzECO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 clock tree
phase shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 bypassed clock source output . . . . . . . . . . . . . . . 158
phase-locked loop . . . . . . . . . . . . . . . . . . . . . . . . . 153 phase delayed clk_sync output . . . . . . . . . . . . . . 158
PHUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 power gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
port interrupt controller unit . . . . . . . . . . . . . . . . . . 201 resynchronized clock output . . . . . . . . . . . . . . . . . 158
RESET module . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
resync option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 unsynchronized divided clock output . . . . . . . . . . 158
SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 clocks
SIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 asynchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SRAM organization for the CY8C38 family . . . . . . 126 high precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
USB clock mux . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 low power mode operation . . . . . . . . . . . . . . . . . . 160
USBIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 cock dividers
voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . 167 main part of clock distribution module . . . . . . . . . 157
watchdog timer circuit . . . . . . . . . . . . . . . . . . . . . . 175 compare types in pulse width mode . . . . . . . . . . . . . . 306
boolean instructions contention
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 CY8C38 family . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
boost converter CY8C55 family . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
application diagram . . . . . . . . . . . . . . . . . . . . . . . . 166 core enhancements
modes of operation . . . . . . . . . . . . . . . . . . . . . . . . 166 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 counter mode
status monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . 166 register configuration . . . . . . . . . . . . . . . . . . . . . . 302
bypassed clock source . . . . . . . . . . . . . . . . . . . . . . . . . 158 counters
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
CPU halt mechanisms
C 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
CPU system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
capture mode
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
crystal oscillator
capture signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
low power operation . . . . . . . . . . . . . . . . . . . . . . . 151
central processing unit
CY wrapper logic
cache controller . . . . . . . . . . . . . . . . . . . . . . . . .81, 87
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PHUB and DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
CY8C38 family
clock
contention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
clock block
PSoC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
RAM implementation . . . . . . . . . . . . . . . . . . . . . . 128
clock distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
CY8C55 family
clock distribution module . . . . . . . . . . . . . . . . . . . . . . . 157
contention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
RAM implementation . . . . . . . . . . . . . . . . . . . . . . 128
50% duty cycle mode . . . . . . . . . . . . . . . . . . . . . . 157
single cycle pulse mode . . . . . . . . . . . . . . . . . . . . 157
clock doubler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
clock frequency D
USB mode operations . . . . . . . . . . . . . . . . . . . . . . 156 data transfer instructions
clock generator 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 dead band feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

496 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Index

debug and trace external memory interface

introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
delay chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 connection to peripheral devices . . . . . . . . . . . . . .140
development kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
device configuration of nonvolatile latch . . . . . . . . . . . 121 how it works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
digital I/O introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
control by DSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
digital system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
digital-to-analog converter . . . . . . . . . . . . . . . . . . . . . . . 28 external memory support in EMIF . . . . . . . . . . . . . . . . .134
direct addressing mode external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 F
document
fast start IMO (FIMO) . . . . . . . . . . . . . . . . . . . . . . . . . .149
CPU system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FAULTMASK special register in PSoC 5
glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
PSoC 5
overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
FAULTMASK special register . . . . . . . . . . . . .117
revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
features
doubled clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
DPTR extension SFR
counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
8051 core enhancements . . . . . . . . . . . . . . . . . . . . 38
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
DSI control of digital I/O . . . . . . . . . . . . . . . . . . . . . . . 194
EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
DSI input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
DSI output to I/O port . . . . . . . . . . . . . . . . . . . . . . . . . 194
I/O system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
dual data pointer registers
interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . .107
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
low power modes . . . . . . . . . . . . . . . . . . . . . . . . . .169
Dual DPTR
nonvolatile latch . . . . . . . . . . . . . . . . . . . . . . . . . . .121
8051 core enhancements . . . . . . . . . . . . . . . . . . . . 38
PHUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
port interrupt controller unit . . . . . . . . . . . . . . . . . .201
power supply and monitoring . . . . . . . . . . . . . . . . .163
E pulse-width modulator . . . . . . . . . . . . . . . . . . . . . .295
EEPROM SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
EEPROM memory watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . .175
how erased . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 flash interrupt
how it works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 attempted flash write . . . . . . . . . . . . . . . . . . . . . . .130
PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 ECC – multi-bit . . . . . . . . . . . . . . . . . . . . . . . . . . .130
EMIF ECC – single bit . . . . . . . . . . . . . . . . . . . . . . . . . . .130
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Flash memory
external memory support . . . . . . . . . . . . . . . . . . . 134 CY8C38 family . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
how it works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 how it works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
memory mapped peripherals . . . . . . . . . . . . . . . . 140 PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
sleep mode behavior . . . . . . . . . . . . . . . . . . . . . . 137 free run mode
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
EMIF register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 free run timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . .301
enable signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 frequency generation . . . . . . . . . . . . . . . . . . . . . . . . . .147
enabling and disabling timer block . . . . . . . . . . . . . . . 297
enabling interrupts
PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 G
erasing EEPROM memory . . . . . . . . . . . . . . . . . . . . . 132
gated timer in pulse width
exceptions supported by PSoC 5 . . . . . . . . . . . . . . . . 117
timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
external crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 150
general purpose input/output interface
external data memory space
PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .479

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 497

Index

GPIO low power mode effect on I/O pins . . . . . . . . . . . . 200

block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 open drain modes . . . . . . . . . . . . . . . . . . . . . . . . . 192
GPIO pins in creation of buttons and sliders . . . . . . . . 197 overvoltage tolerance . . . . . . . . . . . . . . . . . . . . . . 200
port interrupt controller unit . . . . . . . . . . . . . . . . . 201
port interrupt controller unit pin configuration . . . . 202
H port register of digital I/O . . . . . . . . . . . . . . . . . . . 192
power up I/O configuration . . . . . . . . . . . . . . . . . . 200
help, getting
register summary . . . . . . . . . . . . . . . . . . . . . . . . . 202
development kits . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
resistive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 192
hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
resistive pull up and pull down mode . . . . . . . . . . 192
entering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SFR to GPIO (PSoC3 only) . . . . . . . . . . . . . . . . . 194
exiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SIO functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
low power modes . . . . . . . . . . . . . . . . . . . . . . . . . 172
slew rate control . . . . . . . . . . . . . . . . . . . . . . . . . . 192
hibernate regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
strong drive mode . . . . . . . . . . . . . . . . . . . . . . . . . 192
high impedance analog drive mode . . . . . . . . . . . . . . . 192
usage modes and configuration . . . . . . . . . . . . . . 190
high impedance digital drive mode . . . . . . . . . . . . . . . . 192
identifying reset sources . . . . . . . . . . . . . . . . . . . . . . . 180
high voltage interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 167
immediate constants mode
hot swap
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SIO pin support . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
imprecise power on reset . . . . . . . . . . . . . . . . . . . . . . 179
how it works
indirect addressing mode
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38, 413
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . 132
input signals of timer block . . . . . . . . . . . . . . . . . . . . . 297
EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
input voltage to boost converter . . . . . . . . . . . . . . . . . 166
external memory interface . . . . . . . . . . . . . . . . . . . 134
instruction set
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38, 39
I/O system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
instruction set details
interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . 108
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PHUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
internal data space
power regulators . . . . . . . . . . . . . . . . . . . . . . . . . . 165
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PSoC RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
internal low speed oscillator . . . . . . . . . . . . . . . . 148, 149
watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
internal main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 148
internal regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
interrupt controller
I block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
I/O drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 how it works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
high impedance analog . . . . . . . . . . . . . . . . . . . . . 192 interrupt execution . . . . . . . . . . . . . . . . . . . . . . . . 110
high impedance digital . . . . . . . . . . . . . . . . . . . . . 192 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
open drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 level interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
resistive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 priority decoding unit . . . . . . . . . . . . . . . . . . . . . . 110
resistive pull up and pull down . . . . . . . . . . . . . . . 192 pulse interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
strong . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 interrupt controller interface
I/O pins 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
low power mode behavior . . . . . . . . . . . . . . . . . . . 200 interrupt enable register
overvoltage tolerance . . . . . . . . . . . . . . . . . . . . . . 200 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
I/O power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 interrupt execution
I/O system interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . 110
analog I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 interrupt masking
CapSense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 PSoC 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
digital I/O controlled through DSI . . . . . . . . . . . . . 194 interrupt nesting
DSI input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
DSI output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 PSoC 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 interrupt service routine . . . . . . . . . . . . . . . . . . . . . . . . 113
how it works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
I/O port reconfiguration . . . . . . . . . . . . . . . . . . . . . 200 PSoC 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
I/O power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 200 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 interrupt vector addresses
LCD drive capabilities . . . . . . . . . . . . . . . . . . . . . . 196 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

498 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Index

PSoC 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 memory mapped peripherals in EMIF . . . . . . . . . . . . . .140

introduction MHz crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .150
clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 modes
I/O system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 active mode in low power modes . . . . . . . . . . . . .171
programming, testing, debugging, tracing . . . . . . 465 power consumption-reducing . . . . . . . . . . . . . . . .170
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
successive approximation register analog to digital con-
vertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 N
timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
nonvolatile latch
IO interfaces
device configuration . . . . . . . . . . . . . . . . . . . . . . . .121
PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
device configuration register map . . . . . . . . . . . . .121
IO port access registers
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
write once . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
J
jump instructions
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 O
on the fly duty cycle update . . . . . . . . . . . . . . . . . . . . .308
one shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
K oscillators
kill signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 external crystal . . . . . . . . . . . . . . . . . . . . . . . . . . .150
internal PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
summary table . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
L overview, document . . . . . . . . . . . . . . . . . . . . . . . . . 3, 21
document construction . . . . . . . . . . . . . . . . . . . . . .31
late arrival interrupts
getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
PSoC 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
LCD drive
overvoltage tolerance in I/O pins . . . . . . . . . . . . . . . . .200
I/O system capabilities . . . . . . . . . . . . . . . . . . . . . 196
level interrupt
interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . 110
logic diagram P
RESET module . . . . . . . . . . . . . . . . . . . . . . . . . . 180 peripheral device connection
logical instructions external memory interface . . . . . . . . . . . . . . . . . . .140
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 phase delayed clk_sync . . . . . . . . . . . . . . . . . . . . . . . .158
low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 phase select and control . . . . . . . . . . . . . . . . . . . . . . . .159
active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 phase shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
alternative active mode . . . . . . . . . . . . . . . . . . . . 171 phase-locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 PHUB
hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . 172 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
power mode transitions diagram . . . . . . . . . . . . . 169 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 how it works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
timewheel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 port interrupt controller
low voltage detect interrupt processing . . . . . . . . . . . . 168 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
low voltage interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 167 port interrupt controller unit . . . . . . . . . . . . . . . . . . . . . .201
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .202
M port register control of digital I/O . . . . . . . . . . . . . . . . . .192
power consumption-reducing modes . . . . . . . . . . . . . .170
main stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
power gating
mapping diagram
clock outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
digital system input to pad selection . . . . . . . . . . 194
power mode transitions in low power modes . . . . . . . .169
master clock mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
imprecise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
memory map
power regulators
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E 499

Index

how it works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 PSoC Ram

power supply how it works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
PSoC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PSoC3
PSoC 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SFR to GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
power supply and monitoring PSoC5
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . 114
precision power on reset . . . . . . . . . . . . . . . . . . . . . . . 179 PSW0xD0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
PRIMASK special register in PSoC 5 . . . . . . . . . . . . . . 117 pulse interrupt
priority decoding unit interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . 110
interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . 110 pulse width mode
process stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 114 comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . 306
product upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 compare types . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
program and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 pulse width modulator
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 dead band feature . . . . . . . . . . . . . . . . . . . . . . . . 308
PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 on the fly duty cycle update . . . . . . . . . . . . . . . . . 308
program branching instructions one shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 register configuration . . . . . . . . . . . . . . . . . . . . . . 306
program memory space pulse-width modulator
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Program Status Word SFR . . . . . . . . . . . . . . . . . . . . . . . 40
PSoC
active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 R
analog subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . 28
RAM implementation
analog subsystem components . . . . . . . . . . . . . . . . 28
CY8C38 family . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
CY8C55 family . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . 131
register addressing mode
enabling interrupts . . . . . . . . . . . . . . . . . . . . . . . . 108
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Flash memory on-chip . . . . . . . . . . . . . . . . . . . . . . 129
register map
general purpose input/output interface . . . . . . . . . . 27
nonvolatile latch . . . . . . . . . . . . . . . . . . . . . . . . . . 121
IO interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
register specific instructions mode
program and debug . . . . . . . . . . . . . . . . . . . . . . . . . 28
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
special input/output interface . . . . . . . . . . . . . . . . . 27
register summary
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
I/O system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
registers
timer blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
USB input/output interface . . . . . . . . . . . . . . . . . . . 27
EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
PSoC 3
pulse width modulator . . . . . . . . . . . . . . . . . . . . . 306
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
timer block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
8051 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
regulator
CY8C38 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
hibernate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
major components . . . . . . . . . . . . . . . . . . . . . . . . . 23
internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
PSoC 5
external . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
active interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
identifying sources . . . . . . . . . . . . . . . . . . . . . . . . 180
exceptions supported . . . . . . . . . . . . . . . . . . . . . . 117
introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . 114
software initiated . . . . . . . . . . . . . . . . . . . . . . . . . 179
interrupt masking . . . . . . . . . . . . . . . . . . . . . . . . . 117
watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
interrupt nesting . . . . . . . . . . . . . . . . . . . . . . . . . . 114
RESET module
interrupt service routine . . . . . . . . . . . . . . . . . . . . . 116
logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
interrupt vector addresses . . . . . . . . . . . . . . . . . . . 116
reset sources
late arrival interrupts . . . . . . . . . . . . . . . . . . . . . . . 116
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
major components . . . . . . . . . . . . . . . . . . . . . . . . . 23
reset summary table . . . . . . . . . . . . . . . . . . . . . . . . . . 181
power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
resynchronized clock . . . . . . . . . . . . . . . . . . . . . . . . . . 158
PRIMASK special register . . . . . . . . . . . . . . . . . . . 117
RETI instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
tail chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

500 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E

 Index

S sleep mode behavior . . . . . . . . . . . . . . . . . . . . . . .310

SAR ADC timer blocks
introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
SFR – GPIO interface . . . . . . . . . . . . . . . . . . . . . . . . . . 39 timer mode
single cycle pulse mode . . . . . . . . . . . . . . . . . . . . . . . 157 free run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
SIO period mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 stop on interrupt mode . . . . . . . . . . . . . . . . . . . . . .305
SIO functions timer reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
adjustable input level . . . . . . . . . . . . . . . . . . . . . . 197 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
hot swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 timers
regulated output level . . . . . . . . . . . . . . . . . . . . . . 197 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
sleep mode timewheel in low power modes . . . . . . . . . . . . . . . . . . .172
entering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 timing
exiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
external memory interface . . . . . . . . . . . . . . . . . . 137 timing diagram
gating off of clock network outputs . . . . . . . . . . . . 160 capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
interrupt service routine . . . . . . . . . . . . . . . . . . . . 113 free run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . 171 gated timer in IRQ mode . . . . . . . . . . . . . . . . . . . .305
low power modes . . . . . . . . . . . . . . . . . . . . . . . . . 171 gated timer in period mode . . . . . . . . . . . . . . . . . .304
nonvolatile latch behavior . . . . . . . . . . . . . . . . . . . 123 gated timer in pulse width mode . . . . . . . . . . . . . .303
timer block behavior . . . . . . . . . . . . . . . . . . . . . . . 310 timer reset signal . . . . . . . . . . . . . . . . . . . . . . . . . .300
sleep mode behavior in EMIF . . . . . . . . . . . . . . . . . . . 137 timing of EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
sleep regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 timing of external memory interface . . . . . . . . . . . . . . .138
slew rate control in I/O system . . . . . . . . . . . . . . . . . . 192
software initiated reset . . . . . . . . . . . . . . . . . . . . . . . . 179
special function registers U
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 unsynchronized divided clock . . . . . . . . . . . . . . . . . . . .158
special input/output interface update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 updating of clock divider . . . . . . . . . . . . . . . . . . . . . . . .160
SRAM upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 usage modes and configuration of I/O system . . . . . . .190
PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 USB clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
standby mode boost converter . . . . . . . . . . . . . . . . . . 166 USB input/output interface
status monitoring PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . 166 USB mode operation
supply pins clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . .156
PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 USBIO
synchronization of clock . . . . . . . . . . . . . . . . . . . . . . . 158 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
system clock operation . . . . . . . . . . . . . . . . . . . . . . . . 160
system integration
V
low power modes . . . . . . . . . . . . . . . . . . . . . . . . . 169
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
system wide resources . . . . . . . . . . . . . . . . . . . . . . . . 145 vectored interrupt controller interface
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 8051 core enhancements . . . . . . . . . . . . . . . . . . . .38
voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

T
tail chaining
W
PSoC 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
timer watchdog timer
introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
timer block disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
enabling and disabling . . . . . . . . . . . . . . . . . . . . . 297 enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 how it works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 operation in low power mode . . . . . . . . . . . . . . . . .176
selection of clock source . . . . . . . . . . . . . . . . . . . 296 protection settings . . . . . . . . . . . . . . . . . . . . . . . . .176

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Index

setting time period . . . . . . . . . . . . . . . . . . . . . . . . . 176

wrapper logic
8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
write once latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

502 PSoC 3, PSoC 5 Architecture TRM, Document No. 001-50235 Rev. *E