SynthWorks 4.

Structural Architecture = Connectivity

Structural code connects lower levels of a design.
Structural code has three pieces: component
6. Common Synthesizable Types
Type / Abbreviation
std_logic / sl
Value
UX01ZWLH -
Package
1164
VHDL Training Experts declarations, signal declarations, and component std_logic_vector / slv array of std_logic 1164
instances (creates the connectivity). signed / sv array of std_logic ns, sla
architecture Structural of MuxReg is unsigned / uv array of std_logic ns, sla
VHDL Quick Reference -- Component Declarations
boolean / bool
integer / int
(False, True)
31 31
-(2 - 1) to 2 - 1
std
std
component Mux8x2
port ( natural / int0+ 0 to 231 - 1 std
1. VHDL Designs Sel : In std_logic ; line access string textio
A design is partitioned in to a modular blocks. Each I0, I1 : In unsigned(7 downto 0); Enumerated type StateType is (S0, S1, S2, S3) ;
block in the design is created with an entity and Y : Out unsigned(7 downto 0)
); 7. Assigning Values
architecture. Each block is coded in a separate file.
end component ; A_sl <= '1' ; -- Character literal
Each entity and architecture is compiled into a library. component Reg8 B_slv <= "1111" ; -- string literal
Entity names within a library must be unique. The port ( C_slv <= X"F"; -- hex. 4 bits per character
architecture statement repeats the entity name, so the Clk : In std_logic ; E_slv <= (others => '1') ; -- aggregate
architecture name typically indicates the type of code it D : In unsigned(7 downto 0); L_int <= 15 ; -- universal integer
contains: RTL, structural, or testbench. Q : Out unsigned(7 downto 0) M_int <= 16#F# ; -- base literal (16 = base)
); N_bool <= TRUE ; -- boolean only true or false
2. Entity = IO of a Design end component ;
8. VHDL Operators
library ieee ; -- Signal Declarations Logic and, or, nand, nor, xor, xnor
use ieee.std_logic_1164.all ; signal Mux : unsigned(7 downto 0); Comp =, /=, <, <=, >, >=
entity MuxReg is begin Shift sll, srl, sla, sra, rol, ror
port ( -- Component Instantiations Add +, -
Clk : In std_logic ; -- Named Association Sign +, -
Sel : In std_logic ; Mux8x2_1 : Mux8x2 Mult *, /, mod, rem
A : In std_logic_vector(7 downto 0); port map ( Misc **, abs, not, and, or, nand, nor, xor, xnor
B : In std_logic_vector(7 downto 0); Sel => Sel,
Y : Out std_logic_vector(7 downto 0) I0 => A, Precedence increases from logic to misc. Underlined
); I1 => B, items are VHDL-2008.
end MuxReg ; Y => Mux 9. Concurrent Statements
); Concurrent statements are coded in the architecture.
3. RTL Architecture = Implementation
-- Positional Association
RTL code creates hardware and/or logic. RTL code
Reg8_1 : Reg8
9.1 Signal Assignments
contains assignments and process statements. Expression is evaluated immediately. Value is assigned
port map (Clk, Mux, Y);
architecture RTL of MuxReg is one delta cycle later.
end Structural ;
-- Declarations 9.2 Simple Assignment =logic and/or wires
signal Mux: 5. Common Packages Z <= AddReg ;
std_logic_vector(7 downto 0); Usage Abbr. Source Sel <= SelA and SelB ;
use std.standard.all ; -- * std IEEE YL <= A(6 downto 0) & '0'; --Shift Lt
begin YR <= '0' & A(7 downto 1); --Shift Rt
ieee.std_logic_1164.all ; 1164 IEEE
-- Code use ieee.numeric_std.all ; ns IEEE SR <= SI_sl & A(7 downto 1); --Shift In
Mux <= A when (Sel = '0') else B ; use ieee.numeric_std_unsigned.all; nsu IEEE 9.3 Conditional Assignment
use ieee.std_logic_arith.all ; sla Shareware
RegisterProc : process (Clk) Mux2 <=
use ieee.std_logic_unsigned.all ; slu Shareware
begin A when (Sel1 = '1' and Sel2 = '1')
use std.textio.all ; textio IEEE
if rising_edge(Clk) then else B or C ;
use ieee.std_logic_textio.all ; - Shareware
Y <= Mux ; ZeroDet <= '1' when Cnt = 0 else '0';
end if ; VHDL-2008 adds packages for fixed and floating point.
end process ; The conditional expression must be boolean. Also see
libraries work and std are implicitly referenced the if statement.
end RTL ; * package std.standard is implicitly referenced

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9.4 Selected Assignment 10.4 Case Statement 10.7 For Loop
See case statement for rules. Mux : process (S1, S0, A, B, C, D) RevAProc : process(A)
with MuxSel select variable MuxSel : begin
Mux41 <= std_logic_vector(1 downto 0) ; for i in 0 to 7 loop
A when "00", begin RevA(7 - i) <= A(i) ;
B when "01", MuxSel := S1 & S0 ; end loop ;
C when "10", case MuxSel is end process ;
D when "11", when "00" => Y <= A ; Loop index can be any identifier and does not need to
'X' when others ; when "01" => Y <= B ; be declared. For synthesis, loop index must be integer.
when "10" => Y <= C ;
9.5 Process = Container of Sequential Code when "11" => Y <= D ; 10.8 Creating Clock
Must have either a sensitivity list or wait statement. when others => Y <= 'X'; Clk1 <= not Clk1 after 10 ns ;
Combinational logic requires all inputs (signals read in end case ;
the process) to be on the sensitivity list. The "is" end process ; ClkProc : process
following the sensitivity list is optional. begin
A case statement can have zero or more assignments Clk2 <= '0'
Mux : process (MuxSel, A, B, C, D) is per target. The others choice must be last and is wait for 10 ns ;
begin required if all conditions are not covered. Since std_logic Clk2 <= '1' ;
case MuxSel is has 9 value, others is almost always required for wait for 10 ns ;
when "00" => Y <= A ; std_logic and std_logic_vector, end process ;
when "01" => Y <= B ;
when "10" => Y <= C ; The case expression must have locally static type. Prior Do not change the clock style of an existing testbench.
when "11" => Y <= D ; to VHDL-2008, this typically means use either a signal 10.9 Wait Until and after
when others => Y <= 'X'; or variable name or a slice of a signal or variable. Wait stops a process for at least a delta cycle. Wait until
end case ; Clk = '1' finds the next rising edge of clock and is used
end process ; Regular case statement does not use '-' as don't care.
extensively in testbenches.
10. Sequential Statements 10.5 Asynchronous Reset Flip-Flop
Asynchronous reset is specified before the clock. Clock Signal assignments using "after" always project a value
Contained in processes and subprograms. on a signal. "After" never causes a process to stop.
and reset must be on the sensitivity list.
10.1 Signal Assignment RegProc : process ( Clk, nReset) TestProc : process begin
Z <= AddReg ; begin wait until Clk = '1' ;
Sel <= Sel1 and Sel2 ; if (nReset = '0') then Addr <= "000" after tpd_Clk_Addr;
AReg <= '0' ; wait until Clk = '1' ;
Note: VHDL-2008 allows conditional and selected
BReg <= '0' ; Addr <= "001" after tpd_Clk_Addr;
assignments in sequential statements. elsif rising_edge(Clk) then -- and so on ...
10.2 Variable Assignment if LoadEn ='1' then
wait for tperiod_clk * 5 ;
Expression is evaluated and assigned immediately. AReg <= A ;
BReg <= B ; report "Test Done" severity failure;
MuxSel := S1 & S0 ; end if ; end process ;
10.3 IF Statement end if ; 10.10 VHDL-2008
end process ; VHDL-2008 simplifies case statement rules, allows
if (in1 = '1') then
NextState <= S1 ; 10.6 Synchronous Reset Flip-Flop std_logic and bit in a conditional expression (if, while,
Out1 <= '1' ; Synchronous reset is specified after the clock. Only …), allows selected and conditional assignment for
elsif (in2 = '1' and in3 = '1') then clock must be on the sensitivity list. signals and variables in a sequential code and more.
NextState <= S2 ; See SynthWorks' website for papers on VHDL-2008.
RegProc : process (Clk)
elsif (in4 and in5) = '1' then Let your vendors know you want these updates.
begin
NextState <= S3 ;
if rising_edge(Clk) then © 1999 – 2014 by SynthWorks Design Inc. Reproduction of
else
if (nReset = '0') then entire document in whole permitted. All other rights reserved.
NextState <= S4 ;
AReg <= '0' ;
end if ;
elsif LoadEn = '1' then
AReg <= A ;
SynthWorks Design Inc.
An IF statement can have one or more signal VHDL Hardware Synthesis and Verification Training
assignments per branch. Prior to VHDL-2008, the end if ; th
end if ; 11898 SW 128 Ave. Tigard OR 97223 (800)-505-8435
conditional expression must be boolean. With VHDL-
2008 it may also be bit or std_ulogic (std_logic). end process ; http://www.SynthWorks.com [email protected]

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