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VHDL Types

The document discusses various VHDL types including basic types like boolean and integer, synthesis types like std_logic and std_logic_vector, numeric types like signed and unsigned, fixed point types, and floating point types. It provides details on the class, usage, values, operators, and functions for each type.

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Nidhi
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40 views5 pages

VHDL Types

The document discusses various VHDL types including basic types like boolean and integer, synthesis types like std_logic and std_logic_vector, numeric types like signed and unsigned, fixed point types, and floating point types. It provides details on the class, usage, values, operators, and functions for each type.

Uploaded by

Nidhi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VHDL Types

• Basic Types
Type Class Synthesizable Usage
boolean enumerated Y indirect - comparisons
bit enumerated Y not recommended
character enumerated Y not recommended
severity_level enumerated N simulation
integer integer Y array indices,
natural integer (subtype) Y compile time calculation,
positive integer (subtype) Y simulation

compile time calculation,


real floating point N
simulation
time physical N simulation
bit_vector array of bit Y not recommended
string array of character Y simulation (file read/write)

Common – last updated 8/20/19 1 © tj


VHDL Types
• Synthesis Types – std_logic_1164
• 4 types
• std_ulogic • std_logic – resolved* version of std_ulogic
• std_ulogic_vector • std_logic_vector – resolved* version of std_ulogic_vector
• 9 metalogical values
Value Definition Synthesizable
* Resolved : allows high
‘U’ un-initialized N
impedance signals to
‘X’ Forcing Unknown N “resolve” to a 1 or 0, ie.
‘0’ Forcing 0 Y have multiple drivers
‘1’ Forcing 1 Y
‘Z’ High Impedance Y
‘W’ Weak Unknown N
‘L’ Weak 0 N ** Comparison of
‘H’ Weak 1 N std_logic_vectors can
‘-’ Don’t Care N return unexpected results

• Operators
• Comparison**: =, /=, <, <=, >, >= • Shifting: srl, sll, rol, ror
• Boolean: not, and, or, nand, nor, xor, xnor • Concatenation: &
Common – last updated 8/20/19 2 © tj
VHDL Types
• Numeric Types – numeric_std
• 2 types
• signed array of std_logic (analogous to a std_logic_vector)
• unsigned array of std_logic (analogous to a std_logic_vector)
• Values
• signed is interpreted as 2’s complement (positive and negative)
• unsigned is interpreted as unsigned magnitude (always positive)
• Operators
• Comparison: =, /=, <, <=, >, >= • Shifting: srl, sll, rol, ror
• Boolean: not††, and, or, nand, nor, xor, xnor • Concatenation: &
• Arithmetic†: sign -††††, abs††††, +, -, *†††, /†††, mod, rem, **†††††
• Functions
• resize resize unsigned using zero extension
resize signed using sign extension
† Arithmetic operators other than multiplication preserve the length of the result vector i.e. wrap
†† negation of 2’s complement most negative value will return the most negative value
††† * and / will create large logical solutions
†††† signed only
†††† only use with a base of 2
Common – last updated 8/20/19 3 © tj
VHDL Types
• Fixed Point Types – fixed_pkg
• 2 types Positive indices represent the integer portion of the number
• sfixed array of std_logic Negative indices represent the fractional portion of the number
• ufixed array of std_logic signal foo: sfixed(7 downto -8);
• Values msb 1 0 -1 -2 lsb

• sfixed is interpreted as 2’s complement fixed point number (positive and negative)
• unsigned is interpreted as unsigned magnitude fixed point number (always positive)
• Operators
• Comparison: =, /=, <, <=, >, >=
• Boolean: not, and, or, nand, nor, xor, xnor
• Arithmetic: †: sign -††††, abs††††, +, -, *†††, /†††, mod, rem
• Functions ††† * and / will create large logical solutions
• resize resize unsigned using zero extension †††† signed only
resize signed using sign extension
• is_negative determines if the value is less than 0
• add_carry create a carry out during addition
• scalb scales the value by a factor of two (shift)
• is_negative determines if the value is less than 0
• maximum, minimum provides the largest or smallest of two values
• saturate provides the largest possible value for the given range

Common – last updated 8/20/19 4 © tj


VHDL Types
• Floating Point Types – float_pkg
• 1 type Float 32 format is:
• float array of std_logic sign 8 bit exponent 23 bit mantissa
• 3 sub types mantissa is normalized to 1. xxx and the 1. removed
• float32 float(8 downto -23) exponent is biased by 127
• float64 float(11 downto -52) mantissa and exponent are unsigned
• float128 float(15 downto -112) Value = (-1*sign)*1.mantissa x 2(exponent-127)
• Overflow/Underflow/Rounding/Errors
• Complicated set of rules to deal with these
• Details are in the spec
• Operators
• Comparison: =, /=, <, <=, >, >=
• Boolean: not, and, or, nand, nor, xor, xnor
• Arithmetic: : sign -, abs, +, -, *, /, mod, rem
• Functions
• operator functions - Comparison and Arithmetic operations have corresponding functions
with special modes
• resize functions
• utility functions
• type conversions
• constants

Common – last updated 8/20/19 5 © tj

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