Embedded Systems CREC

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UNIT 3
UNIT-III DESIGN AND INTERFACING OF EMBEDDED SYSTEMS
Classes: 10
Embedded hardware and various building blocks, Processor Selection for an
Embedded System, Interfacing Processor, Memories and I/O Devices, I/O
interfacing concepts, Timer and Counting Devices. Embedded System Design and
Co-design Issues in System Development Process, Design Cycle in the
Development Phase for an Embedded System, Uses of Target System or its
Emulator and In-Circuit Emulator (ICE), Use of Software Tools for Development
of an Embedded System, Design metrics of embedded systems.

Embedded hardware and various building blocks:

The software embeds into hardware. Hardware consists of number of building blocks in a
circuit board or in ASIC or on the SoC along with the processors. Hardware consists of
following building blocks and devices in a system in general.
1. Power Source :
Various units in an embedded system operate in one of the ranges 5.0V±0,25 V. 3_3 V ±0.3V
2.0 V ±0,2 V and 1.5V± 0 2V.
2. Clock Oscillator and Clocking Unit(s):
The clock controls the time for executing an instruction,The frequency depends on the
processor circuit execution rate.
3. System Timer:
A timer circuit is suitably configured and functions as system dock. The system clock ticks
and generates system-interrupts periodically. The system-clock interrupt enables execution of
the system supervisory functions in the OS at the periodic intervals. System clock ticks can
be 60 times in second.
4. Real-Time Clock (RTC):
A real-time clock is required in a system. The clock drives the timers for various timing and
counting needs in a system. The clock also updates time and date in the system. A
microcontroller provides the timer circuits for the counting and tuning devices.
5. Reset Circuit, Power-up Reset and Watchdog-Timer Reset
A circuit for reset enables restart of the system from the beginning using a switch or signal.
The reset can also be performed by using an instruction to the processor. A power-up reset
circuit enables restart of the system from beginning whenever power is switched on in the
system. A watchdog-timer reset enables the restart of system when it is stuck up in certain
set of instructions for a period more than preset time-interval. Reset based on reset-switch,
reset-instruction or power-up or power-up reset and watchdog reset can be from same starting
instruction or the different starting instructions.

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6. Memory
Various forms of memories are used in a system. Figure shows a chart for the various forms
of memories that are present in systems. These are as follows:
(a) Internal RAM
(b) Internal ROM/PROM/EPROM
(c) External RAM for the temporary data and stack (in most systems)
(d) Internal caches (in pipelined and superscalar microprocessors)
(e) Internal EEPROM or flash
(I) Memory Stick (card): video, images, songs, or speeches and large storage in digital
camera, mobile systems
(g) External ROM or PROM for embedding soft are (in almost all other than
microcontrollers-based systems)
(h) RAM Memory buffers at the ports

Fig. The various forms of memory in the system

Table gives the functions assigned in the embedded system to the memories, ROM or PROM
or EPROM embeds the embedded software specific to the system.

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A system embeds(locates) the following either in the internal ROM, PROM or in an external
ROM or PROM of microcontroller; boot-up programs, initialization data, strings for an initial
screen-display or initial state of the system, the programs for various tasks, ISRs and
operating system kernel. The system has RAMs for saving temporary data, stack and buffers
that are needed during a program run. The system also has flash for storing non-volatile
results.
7 Input, Output and I/O Ports, I/O Buses and I/O interfaces
The system gets inputs from physical devices through the input ports. Following are the
examples

1. A system gets input from the touch screen, keypad, keyboard, sensors or transducer
circuits.
2.

A processor identifies each input port by its memory buffer address, called port address. Just
as a memory location holding a byte or word is identified by an address, each input port is
identified by the address. The system gets the inputs by the read operations at the port
addresses. The system has output ports through which it sends output bytes to the real world.
Each output port is identified by its memory-buffer address(es) called port address. The
system sends the output by a write operation to the port address. There are also general-
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purpose ports for both the input and output (I/O) operations.
8. Bus
Processor of a system might have to be connected to a number of other devices and systems.
A bus consists of a common set of lines to interconnect the multiple devices, hardware units
and systems. It enables the communication between two units at any given instance. The
remaining units remain in an in connected state during communication between these two. A
bus communication protocol specifies the ways of communication of signals on the bus. At
any instance, a pus may be a serial bus or a parallel bus transferring one bit or multiple data
bits respectively. Protocol also specifies ways of arbitration when several devices need to
communicate through the bus. Alternatively, protocol specifies ways of polling from each
device for need of the bus at an instance. Protocol also specifies ways of daisy chaining the
devices so that, at an instance, the bus is -anted to a device according to the device priority in
the chain.

9. Digital to Analog conversion (ADC):

DAC is a circuit that converts digital 8, 10 r 12 bits to analog output. A DAC operation is
done with the help of a combination of the Pulse Width Modulation (PWM) unit in a
microcontroller and an external integrator chip.
10. Analog to Digital Conversion (ADC):
ADC is a circuit that converts the analog input to digital. The output is of 4, 8 10 or 12 bits
from an ADC. Analog input is applied between + and – pins. ADC circuit converts them into
bits. The converted bits value depends on the reference voltage. When input +ve and -ve pins
are at voltage equal to reference +ve and -ve voltage pins, then all output bits = 1. When the
difference in voltage at inputs +ve and -ve pins = 0v then all output bits = 0.
An ADC unit in the embedded system microcontroller may have multichannels. It can then
take the inputs in succession from the various interconnected to different analog sources.
11. LED, LCD and Touch-Screen Displays:
A system requires an interfacing circuit and software to display.LED is used for indicating
ON status of the system. A flashing LED may indicate that, a specific task is under
completion or is running. It may indicate a wait status for a message. The display may show
the status or message. Display may be a line display, a multiline display or a flashing display.
An LSI (Lower scale integrated circuit) is used as display controller in case of the LCD
matrix display.
Touch screen is an input as well as output device, which is used by the user of a system to
enter a command, choose a menu or to give user reply as input. The input is on physical touch
as a screen position. The touch at a position is mostly by the finger or some times by stylus.
Stylus is a thin pencil shaped long object. It is held between the fingers and used just as a pen
to mark a dot. An LSI (Lower scale integrated circuit) functions as touch-screen controller.
The display-screen display is similar to a computer display unit screen.
12. Keypad, Keyboard or Virtual Keypad at touch screen:
The keypad or keyboard, is an important device for getting user inputs. A touch screen
provides virtual keypad in a mobile computing system. Virtual keypad is a keypad displayed

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on the LCD display screen on touch plate. A user can enter the inputs using touches. A tile is
displayed for a command on the LCD display screen. User can enter the command using
touch at the tile.
A keypad or keyboard may interface to a system. The system may provide necessary
interfacing circuit and software to receive inputs directly from the keys or touch screen
controller
13. Interrupt Handler:
A system may process a number of devices. The system processor controls and handles the
requirements of each device by running an appropriate ISR for each interrupting event, An
interrupts-handling mechanism must exist in each system. It handles interrupts from various
events or processors in the system. The system handled multiple interrupts, which may be
simultaneously pending for service.

Processor Selection for an Embedded System:

Processor Selection: Different systems require different features. A hardware designer takes
these into view and selects an optimum performance-giving processor. A system designer
uses the instruction cycle time as indicator to match the processor speed with the application.
1. A processor, which can operate at higher clock speed, processes more instructions per
second.
2. A processor gives high computing performance when there exist 9a) Pipelines and
superscalar architectures, (b) prefetch cache unit, caches, register files and MMU, and (c)
RISC core architecture and most instructions of single clock cycle.
3. A processor with register windows provides fast context switching in a multitasking
system.
4. Code-efficient instruction set and when needed dual 16/32 bit instructions set required for
smaller memory needs and higher energy efficiency due to less number of m
5. emory fetches.
6. A power-efficient embedded system requires a processor that has auto shut-down feature
for its units and programmability for disabling these when the processing need for a function
or instruction set does not have constraint of execution time. It is also required to have Stop,
Sleep and wait instructions. It may also require special cache design.
7. A processor with burst-mode access external memories fast, reads fast and writes fast.
8. It takes into account when considering a processor that an embedded system has to be
energy efficient. A processor must have auto shutdown features in its various structural units
when these are not employed during a particular time interval. Processor thus has high
computing power at lower power dissipation
Processor or Microcontroller Version Selection
The processor and microcontroller selection process needs the following parameters:
1. Processor instruction cycle in jis (typical)

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2. Internal bus width in Bits
3, CISC or RISC
architecture
4. Pipeline and superscalar architecture
5. On-Chip RAM and/or register file bytes
6. instruction cache
7. Data cache
8. Program memory EPROM/EEPROM/Flash
9. Program memory capacity in bytes
10. Data/Stack memory capacity in bytes
11. Main memory Harvard or Princeton architecture

12. External interrupts

13. Bit manipulation instructions
14. Floating-point processor
15. Interrupt controller
16. DMA controller channels
17. On-chip MMU
Microcontroller Version Selection:
There are numerous versions of 8051. Additional devices and units arc provided in these
versions. A version is selected for embedded system design as per the application as well as
its cost.
1. An embedded system in automobile for example requires CAN bus. Then a version with
CAN bus controller is selected.
2. An 8051 enhancement, 8052, has an additional timer.
3. Philips P83C528 has I2C serial bus.
4. The 8051-family member 83C152JA (and its sister JB., JC and JD) microcontrollers) have
two direct memory access (DMA) channels on-chip. The 805196K has a PTS (Peripheral
Transactions Server) that supports DMA functions. [Only single and bulk transfer modes are
supported, not the burst transfer mode] When a system requires direct transfer to memory
from external systems, the DMAC is used so that the system performance improves by a
separate processing unit for the data transfers nit and to the peripherals.

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Interfacing Processor, Memories and I/O Devices:
Computer-System Buses:
Bus is set of parallel lines (wires) which carry signals from one unit to another unit. Bus lines
interconnect several units, but at a given instance, only two of them communicate. Bus
enables interconnections among many units in a simple way. The signals are in specific
sequences according to a method or protocol. Computing system buses are as follows:
• System Bus also called memory bus, which interconnects the subsystems. it interconnects
the processor to memory system and other hardware units. This bus has high speed and
bandwidth. It is according to the processor, memory system bandwidth, and for read-write
cycles of instructions and data. (Bandwidth means number of bits transferred per second.)
• I/O Bus also called peripheral bus. interconnects the memory bus to a variable number of
I/O devices functioning at variable speeds. Devices or peripherals are designed to interface to
the I/O bus. The devices can be attached or withdrawn from the I/O bus at any time.
CPU/Microprocessor System buses Computing system hardware consists of processor,
memory and 1/O units (ports, devices and peripherals). System bus enables the
interconnections among multiple subsystems in the system CPU/microprocessor/processor in
a computing system interconnects to memory, I/O units, devices and peripherals through a
bus, called system bus or system memory bus. Three sets of signals—classified as address
bus, data bus and control bus define the system bus. A system-bus interfacing-design is
according to the timing diagram oldie processor signals, bus bandwidth and word length. A
simple structure of system bus is that same bus, which connects the memory also connects the
other subs stems (I/O units. ports, devices and peripherals). Processor interfaces memory as
well as I/O devices using system memory bus. Figure (a) shows the interfacing of processor,
memory and I/O devices using memory system bus in a simple bus structure.
1. Address Bus
Address bus signals are from processor to memory or other interfaced units. Address bus is
unidirectional When it has ‘n’ signals A0 to An-1, the Processor issues (send) addresses
between 0 and 2n-1 using the bus. The processor issues the address of the instruction byte or
word to the memory system. The address bus communicates the address to the memory. The
address bus of 32 bits fetches the instruction or data when an address specified by a 32-bit
number, between 0 and 232-1.

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Fig(a) Interfacing of processor, memory and I/O devices using memory system bus

2. Data Bus
A data bus is bidirectional. If it has ‘m’ bits then signals are D0-Dm-1 and processor reads a
word or instruction or writes a word. Data signals are from processor to memory during read

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cycle and memory to processor during write cycle. A data bus of 8, 16, 32 or 64 bits fetches,
loads, or stores the instruction or data.
• Read Cycle: Read cycle means a sequence of signals during which using the data-bus
processor (i) fetches instruction from program-memory section of memory, or (ii) loads data
word from data-memory section of memory. When the processor issues the address of the
instruction. it gets back the instruction from memory through the data bus. When it issues the
address of the data it processor loads the data through the data bus into a register.
• Write Cycle: Write cycle means a sequence of signals during which, using data bus, the
processor sends data word to data-memory address in memory. When it issues the address of
the data it stores the data in the memory through the data bus.
3. Control Bus
A control bus issues signals to control the timing of various actions during communication of
signals. These signals synchronize the subsystems.
(a) When the processor issues the address, after allowing sufficient time for the set-up of all
address bits, it also issues a memory-read control signal and waits for the data or instruction
after a time interval. A memory unit must place the instruction or data during the interval in
which memory-read signal is active (not inactivated by the processor).
(b) When the processor issues the address on the address bus, and (after allowing sufficient
time for the set-up of all address bits) it places the data on the data bus, it also then issues
memory-write control signal (after allowing sufficient time for the set-up of all data bits) for
store signal to memory. The memory unit must write (store) the data during the interval in
which memory-write is active (not inactivated by the processor).

I/O Devices and I/O interfacing concepts:

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Interfacing methods for I/O device:

Fig(a) I/O devices and components interfacing circuit with ports
 Method 1: I/O devices or components interface using ports, interfacing circuit consists
of decoder. The decoder circuit connects the processor address bus and control
signals. A port select output of the decoder is active when the address input
corresponds to the port address. Interfacing circuit is designed as per available control
signals and timing diagrams of the system bus signals. Fig(a) shows interface using
ports.

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Fig(b) I/O devices and components interfacing circuit using I/O bus

 Method 2: A method is interfacing through an I/O bus. Interfacing circuit consists of

I/O controller (called bridge or switch also). The switch circuit connects the processor
and memory on system memory bus with the I/O bus. Interfacing-circuit is designed
as per available control signals and timing diagrams of the system bus signals and I/O
bus. Fig(b) shows interface using I/O bus and switch circuit between system memory
bus and I?o bus.
I/O managing data
Memory mapped I/O and I/O mapped I/O operations are two types of operations based on
processor and memory organisation.
Memory mapped I/O is mapped into the same address space as program memory and/or
user memory, and is accessed in the same way.
Port mapped I/O uses a separate, dedicated address space and is accessed via a dedicated
set of microprocessor instructions.

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The difference between the two schemes occurs within the microprocessor. Intel has, for
the most part, used the port mapped scheme for their microprocessors and Motorola has
used the memory mapped scheme.
As 16-bit processors have become obsolete and replaced with 32-bit and 64-bit in general
use, reserving ranges of memory address space for I/O is less of a problem, as the
memory address space of the processor is usually much larger than the required space for
all memory and I/O devices in a system.
Therefore, it has become more frequently practical to take advantage of the benefits of
memory-mapped I/O. However, even with address space being no longer a major
concern, neither I/O mapping method is universally superior to the other, and there will
be cases where using port-mapped I/O is still preferable.
Memory-mapped IO (MMIO):

I/O devices are mapped into the system memory map along with RAM and ROM. To access
a hardware device, simply read or write to those 'special' addresses using the normal memory
access instructions.
The advantage to this method is that every instruction which can access memory can be used
to manipulate an I/O device.
The disadvantage to this method is that the entire address bus must be fully decoded for every
device. For example, a machine with a 32-bit address bus would require logic gates to resolve
the state of all 32 address lines to properly decode the specific address of any device. This
increases the cost of adding hardware to the machine.
Port-mapped IO (PMIO or Isolated IO):
I/O devices are mapped into a separate address space. This is usually accomplished by having
a different set of signal lines to indicate a memory access versus a port access. The address
lines are usually shared between the two address spaces, but less of them are used for
accessing ports. An example of this is the standard PC which uses 16 bits of port address
space, but 32 bits of memory address space.

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The advantage to this system is that less logic is needed to decode a discrete address and
therefore less cost to add hardware devices to a machine. On the older PC compatible
machines, only 10 bits of address space were decoded for I/O ports and so there were only
1024 unique port locations; modern PC's decode all 16 address lines. To read or write from a
hardware device, special port I/O instructions are used.

From a software perspective, this is a slight disadvantage because more instructions are
required to accomplish the same task. For instance, if we wanted to test one bit on a memory
mapped port, there is a single instruction to test a bit in memory, but for ports we must read
the data into a register, then test the bit.

Memory-mapped IO Port-mapped IO

Same address bus to address memory and I/O Different address spaces for memory
devices and I/O devices
IO is treated as memory IO is treated as IO
16-bit addressing is used 8-bit addressing is used
More decoder hardware is used Less decoder hardware is used
Can access 216 = 64k locations theoretically Can address 216 =256 locations
Access to the I/O devices using regular Uses a special class of CPU instructions
instructions to access I/O devices
Memory instructions are used Special IN and OUT instructions
Arithmetic and logic operations can be Arithmetic and logic operations cannot
performed directly on data be performed directly on data
Data transfer b/w accumulator and I/O
Data transfer b/w register and I/O

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 Timer and
Counting Devices:
Timing Devices

• A device, which counts the input at regular interval (δT) using clock pulses at
its input.
• The counts are incremented on each pulse and stored in a register, called
count register.
• A timer is a specialized type of clock which is used to measure time
intervals.
• A timer uses the frequency of the internal clock, and generates delay.
• Evaluation of Time
• The counts multiplied by the interval δT gives the time.
• For example, if a particular clock’s frequency is 1 MHz (period 1 µs), and
we have counted 3000 pulses on the clock signal, then the elapsed time is
3000 microseconds.
• The (present counts -initial counts) xδT interval gives the time interval
between two instances when present count bits are read and initial counts
were read or set.
• Suppose, we want to measure the time elapsed between any two successive
events.
• Lets assume that when the first event occurs, the timer is reset to zero, and
when the second event occurs, the timer output is 25000. If we know that
the input clock has period of 1 µs, then the time elapsed between the two
events is 25000×1 µs = 25 milliseconds.
• The (present counts -initial counts) xδT interval gives the time interval
between two instances when present count bits are read and initial counts
were read or set.
• Since this timer’s counter can count from 0 to 65535 (2 16-1), this particular
arrangement can measure time ranging from 0 to 65535 x 1 µs = 65.535
milliseconds, with a resolution of 1 µs.
• Has an input pin (or a control bit in control register) for resetting it for all
count bits = 0s.
• Has an output pin (or a status bit in status register) for output when all count
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 bits = 0s after reaching the maximum value, which also means after timeout
or overflow.

Counting Devices

• device, which counts the input due to the events at irregular or regular
intervals.
• A counter is a device that stores (and sometimes displays) the number of
times a particular event or process occurred, with respect to a clock signal.
• It is used to count the events happening outside the microcontroller.
• In electronics, counters can be implemented quite easily using register-type
circuits such as a flip- flop.
• A counter uses an external signal to count pulses.
• Free Running (Blind Counting) Device with a Pre-scaler, Compare and
Capture Registers.
• Pre-scalar can be programmed as p = 1, 2, 4, 8, 16, 32, .. by programming a
Pre-scaler register.
• Pre-scalar divides the input pulses as per the programmed value of p.
• Count interval = p xδT interval
• δ T = clock pulses period, clock frequency = δ T -1
• It has an output pin (or a status bit in status register) for output when all
count bits = 0s after reaching the maximum value, which also means after
timeout or overflow.
• Free running n-bit counter overflows after
p x( 2n -1)xδT interval
• This device useful for the Alarm or Processor Interrupts after preset
intervals with respect to another event from another source.
• For example, if we use a Prescaler to our previous 16-bit timer to divide the
clock frequency by 8, then the new range of the timer will be 65535 x 8 µs
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 = 524.280 milliseconds.
• Most microcontrollers are equipped with one or more precision timing
systems that can be used to perform a variety of precision timer functions
including generating events at specific times, determining the duration
between two events, or counting events.
• Example applications that require generating events include generating an
accurate 1 Hz signal in a digital watch, keeping a traffic light green for a
specific duration, or communicating bits serially between devices at a
specific rate, etc.

• Timer States

• Uses of Timer Device

• A timer cum counting device is a counting device that has two functions.
• (1) It counts the input due to the events at irregular instances.
• (2) It counts the clock input pulses at irregular intervals.

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Ten Forms of a Timer

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• SWT
• Innovative concept –VIRTUAL Timing device.
• A software, which executes and increases or decreases a count-
variable(count value) on an interrupt from system timer output or real time
clock interrupt.
• The software timer also generates interrupt on overflow of count-value or
on finishing value of the count variable.
• System Clock
• A hardware-timing device programmed to tick at constant intervals δT.
• An interrupt at each tick
• A chain of interrupts thus occur at periodic intervals.
• δ T is as per a preset count value
• The interrupts are called system clock interrupts, when used to control the
schedules and timings in the system
SWT and System clock
✓ System clock has fixed program to tick at constant intervals δT.
✓ SWTs have fixed but programmable to tick at intervals δT.
✓ An interrupt at each tick in both

✓ The interrupts called system clock and SWT interrupts, respectively

W
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18
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g

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✓ A timing device such that it is set for a preset time interval and an event
must occur during that interval else the device will generate the timeout
signal on failure to get that event in the watched time interval.

✓ On that event, the watchdog timer is disabled for generation of timeout or

reset

✓ Timeout may result in processor starting a service routine or start from

beginning

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e

✓ Assume that we anticipate that a set of tasks must finish in 100 ms

interval.

✓ The watchdog timer is disabled and stopped by the program instruction

in case the tasks finish within 100 ms interval.

✓ In case task does not finish (not disabled by a program instruction),

watchdog timer generates interrupts after 100 ms and executes a routine,
which is programmed to run because there is failure of finishing the task
in anticipated interval.

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 Watchdog Timer Application
✓ An application in mobile phone is that display is off in case no GUI
interaction takes place within a watched time interval.
✓ The interval is usually set at 15 s, 20 s, 25 s, 30 s in mobile phone.
✓ Mobile thus saves the power
✓ An application in temperature controller
✓ If controller takes no action to switch off the current within preset
watched time interval, the current switched off
✓ Warning signal raised as indication of controller failureFailure to switch off
current may burst a boiler in which water is heated.

Provisioning of watchdog timer

✓ A software task can also be programmed as a watchdog timer

✓ Microcontroller may also provide for a watchdog timer.

REAL TIME CLOCK:

• A clock, which is based on the interrupts at preset intervals.
• An interrupt service routine executes on each timeout (overflow) of this
clock.
• This timing device once started never resets or never reloaded with another
value.
• Used in a system to save the time and date.
• Used in a system to initiate return of control to the system (OS) after the set
system clock periods

RTC Application
• Assume that a hardware timer of an RTC for calendar is programmed to
interrupt after every 5.15 ms (=1 day period/ 224)
• Assume each tick (interrupt) a service routine runs and updates at a memory
location. Within one day (86400 s) there will be 224 ticks, the memory
location will reach 0x000000 after reaching the maximum value 0xFFFFFF.
RTC with 5.5 ms tick
• Within 256 days there will be 232 ticks, the memory location will reach
0x00000000 after reaching the maximum value 0xFFFFFFFF.
• A battery is used to protect the
memory for long period RTC for
implementing a software timer
• A hardware 16-bit timer ticks from processor clock after 0.5 µs. It will
overflow and execute an overflow interrupt service routine after 215 µs =
32.768 ms.

• The interrupt service routine can generate a port bit output after every time
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 it runs or can call a software routine or send a message for a task. If n = 30,
the RTC initiated software will run every 30 × 32.768 ms, which is close to
1 s.
Unmask and reset to mask of real time interrupt
• RTI is set to unmask and reset to mask the real time interrupt locally.

• If RTI and I bits permit the interrupt request for real time, the
microcontroller fetches the lower and higher bytes of the interrupt servicing
routine address from the addresses 0xFFF0 (higher byte) and 0xFFF1
(lower byte)
I/O TYPES AND EXAMPLES:
A port at a device can transmit (send) or receive through wire or wireless. Input port means a
circuit to where bit or bits can be input (received) from an external device, peripheral or
system. Output port means a circuit from where bit or bits can be output (sent) to an external
device, peripheral or system. Input-Output (I/O) port means a circuit where bit(s) can be input
or output. There are two types of I/Os, serial and parallel. Serial means in series of successive
instants. Parallel means at the same instance.
1. Serial Input Serial input port means a circuit to where bits can be input (received) in
successive time intervals. The time interval is known to the receiver port. The port assembles
the bits on receiving at successive instances.
2. Serial Output Serial output port means a circuit from where bits can be output (sent) in
successive time intervals. A time interval is known to the external device or system. The
external device assembles the bits on receiving at successive instances from the output port.
3. Serial I/O Serial Input-Output (I/O) port means a circuit where serially received or sent bits
can be input or output.
4. Parallel Input Parallel input port means a circuit where bits can be input (received) at an
instant. The processor at the input device, circuit or system reads the bits from the port at next
instant.
5. Parallel Output Parallel output port means a circuit from where bits can be output (sent) at
an instant. The external trial device can read the bits at the output port.
6. Parallel I/O Parallel Input-Output (I/O) port means a circuit where received or sent bits in
parallel can be input or output.
7. I/O Types (i) Serial Input, (ii) Synchronous Serial Output, (iii) Asynchronous Serial Input,
(iv) Asynchronous Sena u..tput, (v) Parallel Port One-bit Input, (vi) Parallel Port One-bit
Output, (vii) Parallel Port Input, and (viii) Parallel. Port Output.
Synchronous serial input:
The upper part of figure shows a synchronous input serial port at a device or system. Each bit
in each byte is in synchronisation and each received byte is in synchronisation.
Synchronisation means separation by a constant time interval or phase difference. A port
(device) processing element reads a successive instances and saves each byte at a port buffer
(register).

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Synchronous serial output:
The middle part of Figure shows a synchronous output serial port. The serial port device
optionally also sends the clock pulses at clock pin SCLK. Each bit in each byte is in
synchronisation with a clock. The serial port at device optionally sends the clock pulses at
SCLK pin.

Fig(1.a)

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Synchronous Serial Input/Output:
Figure at the left lower part shows a synchronous serial I/O port. Each bit in each byte is in
synchronisation at input with a clock input (optional) and each bit in each byte is in
synchronisation at output with the clock output (output). The bytes are sent or received at
constant rates
Asynchronous Serial Input:
Figure (b) on the left side shows asynchronous input serial port line SI (receive data). Each
bit is received in each byte at fixed intervals but each received byte need not be in
synchronisation. The bytes can separate by the variable intervals or phase differences.
Each bit at input port separates by T and bit transfer rate (for the serial line bits) is (1/T) baud
per second (bps), but different bytes are received at varying intervals. Baud is taken from a
German word for raindrops. Bytes pour from the sender like raindrops at irregular intervals.
The sender does not send the clock pulses along with the hits.
Asynchronous Serial Output:
Figure (1.b) on the left side shows as output serial port line SO (transmit data). Each bit in
each byte is at fixed intervals but each output byte need not in synchronisation (separates by a
variable interval or phase difference).

Fig(2) (a)m-bit parallel ports with m = 1,2,…7,8 (b) Two m/2 bit subsets for output bits in
parallel.

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Serial Communication and Advanced I/O:
Refer 5th unit “Synchronous/Asynchronous Interfaces (like UART, SPI,
I2C, and USB)” topic
Buses between the Networked Multiple Devices:

A distributed networked system means a number of systems on a common bus or a set of

buses, where each system interfaces to a bus. Each bus communicates as per a protocol. Bus
communication simplifies the number of connections and provides a common way (protocol)
of connecting different or same type of I/O devices. A communication system may use
protocols such as UART, 12C, CAN, USB, Wi-Fi or Bluetooth for synchronous or
asynchronous transmission from interface at device, or from the system to another interface.
Figure 5.16 shows a computer-system bus connected to serial-I/O bus using a bus controller,
and I/O bus networking the number of embedded systems distributed on a serial bus.
I2C : Inter integrated circuit (I2C) is important serial communication protocol in modern
electronic systems. Philips (now NXP semiconductors) invented this protocol in 1986. The
objective of reducing the cost of production of television remote control motivated Philips to
invent this protocol. I2C is a serial bus interface, can be implemented in software, but most of
the microcontrollers support I2C by incorporating it as hard IP (Intellectual Property). IIC can
be used to interface microcontroller with RTC, EEPROM and different variety of sensors. IIC
is used to interface chips on motherboard, generally between a processor chip and any
peripheral which supports I2C. I2C is very reliable wireline communication protocol for an
on board or short distances. I2C is a serial protocol for two-wire interface to connect low-
speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and
other similar peripherals in embedded systems.
I2C combines the best features of SPI and UARTs. With I2C, you can connect multiple
slaves to a single master (like SPI) and you can have multiple masters controlling single, or

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multiple slaves. This is really useful when you want to have more than one microcontroller
logging data to a single memory card or displaying text to a single LCD.

I2C protocol uses two wires for data transfer between devices: Serial Data Line (SDA) and
Serial Clock Line (SCL). The reduction in number of pins in comparison with parallel data
transfer is evident. This reduces the cost of production, package size and power consumption.
I2C is also best suited protocol for battery operated devices. I2C is also referred as two wire
serial interface (TWI).
SDA (Serial Data) – The line for the master and slave to send and receive data.
SCL (Serial Clock) – The line that carries the clock signal.
I2C is a serial communication protocol, so data is transferred bit by bit along a single wire
(the SDA line).

Like SPI, I2C is synchronous, so the output of bits is synchronized to the sampling of bits by
a clock signal shared between the master and the slave. The clock signal is always controlled
by the master.
CAN: A number of devices located and are distributed in a Vehicular Control Network
automobile uses a number of distributed embedded controllers. The controllers provide the
controls for brakes, engines. electric power. lamps. temperature, air conditioning, car gate.
front display panels. and cruising.

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The embedded controllers are networked and are controlled through a controller network bit.
Figure (a) shows a network of number of CAN controllers and CAN devices on a CAN bus.
Figure (b) shows six fields and interframe bits during a transfer of data bits on CAN bus, and
timing formats and sequences of frame bits.

 The CAN has a serial line, which is bidirectional.

 A CAN device receives or sends a bit at an instance by operating at the maximum rate
of 1Mbps.
 It employs a twisted pair connection to each node.
 The pair runs up to a maximum length of 40 m.
 A CAN version also functions up to 2Mbps. CAN (control area network) bus is a
standard bus in distributed network.
 CAN is mainly used in automotive electronics. It is also used in medical electronics
and industrial plant
USB: Universal Serial Bus (USB) is a set of interface specifications for high speed wired
communication between electronics systems peripherals and devices with or without
PC/computer. The USB was originally developed in 1995 by many of the industry leading
companies like Intel, Compaq, Microsoft, Digital, IBM, and Northern Telecom. The major
goal of USB was to define an external expansion bus to add peripherals to a PC in easy and
simple manner.
USB offers users simple connectivity. It eliminates the mix of different connectors for
different devices like printers, keyboards, mice, and other peripherals. That means USB-bus
allows many peripherals to be connected using a single standardized interface socket. It
supports all kinds of data, from slow mouse inputs to digitized audio and compressed video.

26
Various versions USB:
USB1.0: USB 1.0 is the original release of USB having the capability of transferring
12Mbps, supporting up to 127 devices. This USB 1.0 specification model was introduced in
January 1996.
USB1.1: USB 1.1 came out in September 1998. USB 1.1 is also known as full-speed USB.
This version is similar to the original release of USB; USB version 1.1 supported two speeds,
a full speed mode of 12Mbits/s and a low speed mode of 1.5Mbits/s.
USB2.0: Hewlett-Packard, Intel, LSI Corporation, Microsoft, NEC, and Philips jointly led the
initiative to develop a higher data transfer rate than the 1.1 specifications. USB 2.0, also
known as hi-speed USB. This hi-speed USB is capable of supporting a transfer rate of up to
480 Mbps, compared to 12 Mbps of USB 1.1. That's about 40 times as fast!
USB3.0: It is also called as Super-Speed USB having a data transfer rate of 4.8Gbps(~5Gbps)
That means it can deliver over 10x the speed of today's Hi-Speed USB connections
USB 3.1 : is the latest version of USB also known as Super-Speed USB+, which having data
transfer rate of 10Gbps.
The USB system is made up of a host, multiple numbers of USB ports, and multiple
peripheral devices connected in a tiered-star topology.

USB can support 4 data transfer types or transfer modes.

1. Control
2. Isochronous
3. Bulk
4. Interrupt

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 Embedded System Design and Co-design Issues in System
Development Process:
There are two approaches for the embedded-system design. (1) The software development
life cycle ends and the life cycle for the process of integrating the software into the hardware
begin at the time when a system is designed. (2) Both cycles concurrently proceed when co-
designing a time-critical sophisticated system.
The final design, when implemented, gives the targeted embedded system, and thus the final
product. Therefore, an understanding of the (a) software and hardware designs and
integrating both into a system, and (b) hardware-software co-designing are important aspects
of designing embedded systems. There is a hardware- software trade-off.
The selection of the hardware during hardware design and an understanding of the
possibilities and capabilities of hardware during software design are critical especially for a
sophisticated embedded-system development.
Choosing the Right Platform
1. Hardware- software trade-off -There is a trade-off between the hardware and software. It is
possible that certain subsystems in hardware, I/O memory access, real-time clock, system
clock, pulse-width modulation, timer, and serial communication are also implemented by the
software.
Hardware implementation provides the following advantages (i) Reduced memory for the
program (ii)Reduced Number of chips but an increased cost (iii) Simple coding for the device
drivers (iv) Internally embedded codes, which are more secure than at the external ROM.
Software implementation provides the following advantages: (i) Easier to change when new
hardware versions become available (ii) Programmability for complex operations (iii) faster
development time (iv) Modularity and portability (v) Use of a standard software-engineering
model (vi) RTOS (vii) Faster speed of operation of complex functions with high-speed
microprocessors (viii) Less cost for simple systems.
Choosing a Right Platform- A timer is a specialized type of clock which is used to measure
time intervals. A timer that counts from zero upwards for measuring time elapsed is often
called a stopwatch. It is a device that counts down from a specified time interval and
used to generate a time delay, for example, an hourglass is a timer.
A counter is a device that stores (and sometimes displays) the number of times a
particular event or process occurred, with respect to a clock signal. It is used to count
the events happening outside the microcontroller. In electronics, counters can be
implemented quite easily using register-type circuits such as a flip-flop.

Difference between a Timer and a Counter

The points that differentiate a timer from a counter are as follows −

Timer Counter

The register incremented for every The register is incremented considering 1 to 0

machine cycle. transition at its corresponding to an external input pin
(T0, T1).
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Maximum count rate is 1/12 of the Maximum count rate is 1/24 of the oscillator
oscillator frequency. frequency.

A timer uses the frequency of the A counter uses an external signal to count pulses.
internal clock, and generates delay.

2. System design of an embedded system also involves choosing a right platform. A platform
consists of a number of following units.
Processor, ASIP or ASSP, Multiple Processors, System-on-Chip, Memory Other Hardware
Units of System, Buses, Software language, RTOS, Code generation tools, tools for finally
embedding the software into binary image.
3. Embedded System Processors' Choice
■ Processor-Less System -We have an alternative to a microprocessor microcontroller or
DSP. Figure (a) shows the use of a PLC in place of a processor. We can use a PLC for the
clothes-in clothes-out type system. A PLC fabricates by the programmable gates, PALs
GALs, PLDs and CPLDs.

Figure (a) Use of a PLC in place of a processor (b) Use of a microprocessor,

microcontroller or a DSP (c) Processing of functions by using IP embedded into the
FPGA instead of processing by the ALU
A PLC has very low operation speed. It also has a very low computational ability. It has very
strong interfacing capability with its multiple inputs and outputs. It has system-specific
programmability. it is simple in application. Its design implementation is also fast. Automatic
chocolate-vending machine another exemplary application of PLC.
■ Fig (b) -System with Microprocessor, Microcontroller or DSP
■ System with Single-purpose Processor or ASSP in VLSI or FPGA Figure © shows the
processing of functions in using IP embedded into VLSI or FPGA instead of processing b the
ALU
A line of action in designing can be use of the IP, synthesising using V HDL like tool and
embedding the synthesis into the FPGA. This FPGA implements the functions, which if
implemented with the ALU and programmer coding will take a long time to develop.
■ Factors and Needed Features Taken into Consideration- We consider a general. purpose
processor choice or choose an ASIP (rnicrocontroller, DSP or network processor). the 32-hit
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system, 16 KB- on-chip memory. and need of cache, memory management unit, SIMD,
M1MD or DSP instructions arise, we use a microprocessor or DSP.

Memory and Processor sensitive software

Processor sensitive - A processor has different types of structural units. It can have memory-
mapped I/Os or 1/O-mapped I/Os. The I/O instructions are processor sensitive. A processor
may be having fixed point ALU only. Floating-point operations, when needed. are handled
differently than in a processor with floating-point operations.
Memory sensitive - (i) An example of a memory-sensitive program is video processing and
real-time video processing. The picture resolution actually used for processing and number of
frames processed per second will depend upon the memory available as well as processor
performance (ii) Memory address of I/O device registers, buffers, control-registers and vector
addresses for the interrupt sources or source groups are prefixed in a microcontroller
Memory-sensitive programs need to be optimized for the memory use by skilful
programming. (iii) When using certain instruction sets like Thumb in ARM processor helps
in 16-hit instructions, which save in less memory space than use of 32-bit ARM instruction
set.
Allocation of Addresses to memory, program segments and devices.
1.Functions, Processes, Data and stacks at the various segments of memory
Program routines and processes can have different segments. Each segment has a pointer
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address and an offset address. Using offset, a code or data word is retrieved from a segment.
A stack is a special data structure at the memory. It has a pointer address that always points to
the top of a stack. This pointer address is called a stack pointer. The other data sets, which are
also allotted memory are as following: String, Circular queue, A one-dimensional array, A
table, A has table, Look-up tables, A list.
2 Device, Internal devices and I/O devices addresses and device drivers
All I/O ports and devices have addresses. These are allocated to the devices according to the
system processor and the system hardware configuration. Device addresses are used for
processing by the driver. A device has an address, which is usually according to the system
hardware or may also be the processor assigned ones. These addresses allocated to the
following:
1. Device data Registers or RAM buffers
2. Device Control registers – it saves control bits and may save configuration bits also.
3. Device status registers – it saves flag bits as device ststus. A flag may include the
need for servicing and show occurrence of a device-interrupt.

Porting issues of OS in an embedded platform

The following porting issues may arise when the OS is used in an embedded platform: I/O
instructions, Interrupt servicing routines, data types, interface specific data types, byte order,
data alignment, linked lists, memory page size, time intervals.

Design Cycle in the Development Phase for an Embedded System

Unlike the design of a software application on a standard platform, the design of an

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embedded system implies that both software and hardware are being designed in parallel.
Although this isn’t always the case, it is a reality for many designs today. The profound
implications of this simultaneous design process heavily influence how systems are designed.

Figure shows the development process or an embedded system and Figure edit-test-debug
cycle during implementation phase of the development process. There are cycles of editing-
testing-debugging during the development phase, Whereas the processor part once chosen
remains fixed, the application software codes have to be perfected by a number of runs and
tests. Whereas the cost of the processor is quite small. The cost of developing a final targeted
system is quite high and needs a larger time frame Man the hardware circuit design.
The developer uses four main approaches to the edit-test-debug cycles.
I. An IDE or prototype tool
2. A simulator without any hardware
3. Processor only at the target system and uses an in-between ICE (in-circuit-emulator).
4. Target system at the lest stage.

Uses of Target System or its Emulator and In-Circuit Emulator (ICE)

An in-circuit emulator (ICE) is a hardware interface that allows a programmer to

change or debug the software in an embedded system. The ICE is temporarily installed
between the embedded system and an external terminal or personal computer so that the
programmer can observe and alter what takes place in the embedded system, which has no
display or keyboard of its own.

An in-circuit emulator (ICE) provides a window into the embedded system. The
programmer uses the emulator to load programs into the embedded system, run them, step
through them slowly, and view and change data used by the system's software.

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 An emulator gets its name because it emulates (imitates) the central processing unit
(CPU) of the embedded system's computer. Traditionally it had a plug that inserts into the
socket where the CPU integrated circuit chip would normally be placed. Most modern
systems use the target system's CPU directly, with special JTAG-based debug access.
Emulating the processor, or direct JTAG access to it, lets the ICE do anything that the
processor can do, but under the control of a software developer.

ICEs attach a computer terminal or personal computer (PC) to the embedded system.
The terminal or PC provides an interactive user interface for the programmer to investigate
and control the embedded system. For example, it is routine to have a source code level
debugger with a graphical windowing interface that communicates through a JTAG adapter
(emulator) to an embedded target system which has no graphical user interface.

Notably, when their program fails, most embedded systems simply become inert
lumps of non-functioning electronics. Embedded systems often lack basic functions to detect
signs of software failure, such as a memory management unit (MMU) to catch memory
access errors. Without an ICE, the development of embedded systems can be extremely
difficult, because there is usually no way to tell what went wrong. With an ICE, the
programmer can usually test pieces of code, then isolate the fault to a particular section of
code, and then inspect the failing code and rewrite it to solve the problem.

In usage, an ICE provides the programmer with execution breakpoints, memory

display and monitoring, and input/output control. Beyond this, the ICE can be programmed
to look for any range of matching criteria to pause at, in an attempt to identify the origin of a
failure.

Most modern microcontrollers use resources provided on the manufactured version of

the microcontroller for device programming, emulating, and debugging features, instead of
needing another special emulation-version (that is, bond-out) of the target microcontroller.[1]
Even though it is a cost-effective method, since the ICE unit only manages the emulation
instead of actually emulating the target microcontroller, trade-offs must be made to keep
prices low at manufacture time, yet provide enough emulation features for the (relatively few)
emulation applications.

Note: Debugging is the process of finding and resolving defects or problems within a
computer program that prevent correct operation of computer software or a system.

33
Use of Software Tools for Development of an Embedded System
Refer 1st unit topic “Software Tools used for Development of an Embedded
System”

Design metrics of embedded systems - low power, high

performance, engineering cost, time-to-market
Power dissipation – For many systems, particularly battery operated systems, such as mobile
phone or digital camera, the power consumed by the system is an important feature. The
battery needs to be recharged less frequently if power dissipation is small.
Performance – Execution time taken by instructions in the system is a measure of
performance. Smaller execution time for instructions means higher performance. For
example, in a mobile phone, if the voice signals process between antenna and speaker in 0.1s,
the the phone performance measure is o.1s. Consider another example, a digital camera if
shoots and saves a still image of 4M pixels in 0.2s then the camera performance measure is
0.2s(=5 images per second).
Process deadlines – Number of processes execute in the system. There are, for example,
processes for keypad input processing, refresh of graphic display, and audio and video signals
processing. Each process has a deadline within which each of them may be required to
complete the computations and give the results.
User Interfaces - User Interfaces, for example, user interactions through the keypad and
display or GUIs or VUIs.
Size - Size of system is measured in terms of (i) physical space required, (ii) RAM in KB and
internal flash memory requirements in MB or GB for running software and storing the data,
and (iii) number of million logic gates in the hardware.
Engineering cost - Initial cost of developing, debugging and testing the hardware and
software is called engineering cost. It is a one-time cost. It is therefore, called non-recurring
engineering (NRE) cost.
Manufacturing cost – Cost of manufacturing each unit tor shipping. Total cost per unit is
(NRE cost manufacturing cost for N units)/ N if N units are shipped.
Flexibility - Flexibility in a design enables offering the different versions of a product with-
out any significant change in engineering cost. Extra functions are necessitated by changing
environment or software re-engineering. Software is enhanced for new version by adding the
extra functions. The flexible design enables faster marketing. A manufacturer can offer the
product in advanced versions later on easily and that too in shorter timeframes.
Prototype development time - Time taken in days or months for developing the prototype and
in-house testing for the system functionalities. It includes engineering time and prototyping
time.
Time-to-market - Time taken in days or months after prototype development to put a product
for, users and consumers. System safety in terms of accidental tall from hand or table, theft
(for phone locking ability and tracing ability), and in terms of user safety when using a
34
product (for example. an automobile brake or engine)
Maintenance - Maintenance means changeability and additions in the system, for example,
adding or updating soft are. data and hardware. Example of software maintenance is
additional set-. ice or functionality of software. Example of data maintenance is additional
ring-tones, wallpapers, video-clips in a mobile phone or extending a card expiry-date in case
of a smart card. Example of hardware maintenance is providing the additional memory or
changing the memory stick in a mobile computer or digital camera.

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