Computer Architecture and Operating Systems
Computer Architecture and Operating Systems
ARCHITECTURE AND
OPERATING SYSTEMS
Main or
Secondary I/O
CPU Primary
Memory Devices
Memory
Interconnecting Bus
Main or
Secondary I/O
CPU Primary
Memory Devices
Memory
Interconnecting Bus
for execution.
• This fetch-decode-execute
cycle is repeated for each
succeeding instruction.
• It should be noted
that the
performance of a
computer system is
not only measured
in terms of the
speed of its CPU.
– In a multitasking or
multiprogramming
environment, the operating
system schedules the CPU to
execute another program to
maximize its utilization.
• ISRs for the different I/O devices are usually part of their
respective device drivers.
• Each device has its own ISR. If the keyboard was the one
that sent the interrupt signal, then the CPU will execute
the keyboard's ISR.
Program
ISR of
• If the printer made the Printer
interrupt request, the At this point, the printer
makes an interrupt
CPU will execute the request so CPU stops
ISR of the printer. executing the program
and starts executing the
ISR of the printer
• In order to understand what a cache memory is, it is better to present first the
two main technologies used in manufacturing RAM memory chips.
• There are generally two types of RAM chips available, static bipolar RAM chips
(SRAM chips) and dynamic RAM chips (DRAM chips).
SRAM DRAM
Access Time (Speed) Fast Access Times Relatively Slower
Low Packing Density. An
SRAM chip has limited High Packing Density. A
storage capability. For typical DRAM chip may
Packing Density
example, a typical SRAM have as much as 1 GB of
chip may have a maximum storage space.
of 1 MB of storage space.
Cost Very Expensive Much Cheaper
• For example:
4,096 MB
Number of Chips Required = = 4 chips
1,024 MB
cache memory.
• The CPU will now fetch these instructions and data from the
much faster cache memory thereby giving a remarkable
improvement in the over-all memory access speed.