Scribd
Upload
25 views15 pages

MPMC 2

Uploaded by

Marupaka
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
25 views15 pages

MPMC 2

Uploaded by

Marupaka
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
You are on page 1/ 15
i-2_ atone Master set se 2 a creer Merten ett fatmeceey 5 How dows Sant rea ae eS aT Frcaaes tr ent apt cme 3 | Pe sosteantnscstmat memory wo G4KB erica} 3. |The internal wemory of 8051 i of KB, with adres ane cence Typically this feces a CPU RYE? Earn ret Mem - joe compen tos # a valar sea Ni q Tmsersl Fregram Memon a SLT SEE a eie cp na [Te ean momen eonty neta Sapa PT ROR Soe a ae a ith des tp COL FET nap O00 OFF ONTROLL a 0 MICROPROCESSORS AND MIOROCONTED— ‘supported INIT-2 (rodent Merocanio re varios Prone yy Y 8 £051 Real Tne Cont) PART-B) essay questions with SOLUTIONS: ocettg) 2141 INTRODUCTION To Mickocoigliag tsbulted below. | BAA Overview of 208 wi ane Taterrupt Prioriyigg) 18. Draw the block lageam oa a ‘explain each Bock in de 1 [Reet a] anes 12 | extemal Hardware Inerupt 0 ‘The blosk diagram of micwcompuis iste in | ® TH Hegueney of te clock pulses and the fneioning aNto) : the figure te microcomputer depends upon the equeney 3. | Timevcounter 0 overflow (TFO) Tate (G16. Lstthe various applications of 605% mica, troller. Ans: frequency measrement, bad al fener, and covmting oF bs ec ean be done sing on hip timers 8051 has several appli Some of them ar, rotor by automaticaly | | ‘itching the output a desired frequency. 051 suport wo counter tine namely ier Onl | QIF. How dos eect ae timer 1. The size of each ti it. en ‘munications of 8051? + G14 Draw te TO and registers of 8051 microcon. ‘roller. items cro ioen.0 reise which conan it butler gual! era in stot * anes ‘Tnd Tare 4b eps which specifies the lower 4it and upper 4b of fie TMOD register respectively a ‘The register formas of TO dT are shown in igre, 1s for dt ansmission and reception 4 vw smroroceao bad ren, i Foes 6 a eading dia io SBUP einer ree : i [oxeT on [wt Two [cee Tor [oar Jo] : 1 a area, Taner) Teer 0) Figure Raitt Format of T and T1 ; ‘Sea srecrmum ALLW-OME 4OURMAL FORE GEE wonnne: samen Mater 9 toe gay ne entcan acne Lrreccton t Meroconvoters and 8051 RealTime Conv) the details of 8051 mireconroner chips. 1 cae see ee et ap et} oan [temennraceas - ieee baa 1 XCH mdi hain sb 2 2 AIDC: Ws yt wate nd eae ofS Se gw OS — Jono SLES Se ee orate ace thier ae oft seid ope wi sind Mecnenis | eae Raw A] ADOCARS 7 sa aa |e ‘Mremonics Deseris ov GHA, Ra) Bat — Examples | Bytes | lastroction ABDC A dics | cnt of eat A wi re T 1A Ro | Eathanges cones of A Wi SoGeaw ies iy =e See Gf} et ——emen] R | 7 sai ao ra Sea Oe = ; - = maT eye NGA. GR | Escangs cots ofA wak edie OT DOC a wan | ast nes ofS ot location addesed by a patculr ea ‘CHA, @RO | 7 3 ADDO A, th V za wit ca OS Introduct (' on to Microcontrollers and 8051 Real Time Control) tion ex: the specified intemal RANT Teaco XCHNEEE the lower order nibble ofthe accumulator with the lower order nemonie ° + Mnem« Ue ae Deeerisn Taampie | bye | mstruction | XCHD A. @Ri | Exchange 1 = a indirect RA Ren ci etificant nibble of A with that of | XCHD A,@RI[ 1 1 Lore M location addressed by a particular register in instruction moves a byte from the code or program memory to the accumulator. Mnemonics = T ae Description Bytes eine: MOVCA.@A*DPTR | Copi : pies the contents of exter 2 < to hou mal RQM address formed by (A+DPTR) | OVC A, @A+ M( @A+PC | Copies ‘the contents of extemal ROM address to (A¥PC) to] 1 7 Accumulator MOVC A, @Ri_._| Copies contents of address mentioned by Rito the Accumulator [1 2 (a) MOVX: The MOVX instruction transfers data between the accumulator and external data memory. Mnemonics Description Example | Bytes | Instruction Cycles MOVX A, @DPTR Copies contents of DPTR to Accumulator 4 2 MOVX @Ri, A Copies contents of A to the external address | MOVX@RLA| 1 2 in Ri 5 MOVX @DPTR, A. Copies data from A to DPTR “4 2 = 4. Address object Transfer MOV, DPTR, #data moves an immediate data of 16 bits into a pair of destination registers DPH and DPL.- Example: MOV DPTR, #data 16 G7. Explain the arithinetic Instructions of 8051. > _ ite yen t | Explain any four arithmetic instructions‘of 8051 microcontroller with examples. Meydunes 89h 5) (Refer Only rournsiition®) i ‘i Ans: - The following are the arithmetic instructions of 8051 . 1. ADD: It.adds a byte value to the accumulator and stores the result back into the accumulator. : Instruction Mnemonics ‘Description : Example ee ADD AcRa | Add contents of A and register, Ro _[ ADD A, RI 1 1 TRDD A, direct_| Add contents ofA and conten ofdiectbyte| ADD A,SOH_| 2 r | OD A-@ RI] Add contents stored in indir RAM location | ADDA@RI [1 1 ‘ADD A, @Ri | Avr ater, Rito A with cary fag A “Add contents of Aand immediate date ADDA, #3H[ 2 7 2 AP tue and the value of the CTY flag (0 the accumulator and stores the result accumulator. " ju Appr: kee Description Example — | Bytes | Instruction Cycles een ir comnts of register Br (0 Ay appears [1 a | with carry flag "ADI Girect | Add contents ‘of direct byte to A with ‘ADDC A, 60H. 2 | 1 DCA, direct : ; carry 08 geet RAM] ADDCA,@RI | 1 —T aa contents stored in mt ith ADDC A, @Ri | Tre tion of resister Ri to ‘ADDCA, HOH a | Je Xo DART RSG Ge EN ae in arcemelane eaermNONE BCD AeA UUNIT.2 docu es [_tastraction Cycle] Rg 2.19 [ae eae = | + Exon We eae ye nd lela DAN Danse c a — Explain masking opens 7 & nceane PY wg olan UNC: eocremncess the specited operand by [An oxigial ator of OEFH overtow 10 00H, (eer A ANE sy pretend, enn INCDPTTE Rimcremenns de 16 de panes 2 | z pies | lastrecion Gran i T hoa TmeRD | v ET z 1 _ carr | v UNIT-2_ (Introduction to Microcontrollers and 8051 Real Time Control) 2.23 (— Retrieval CPU Action CPU Action SP | 0A | Store lAdaress 0A] Get | OA | SP SP’ | 09 | Store | Address 09} Get 09 =| SP + 4 SP] 08 | Store:| Address 08] Get os | SP sp |. 07 Address 07 o7_ | sP 3 Insertion Increment of Sey ——I (Decrement of SP) Figure (1): Stack Operation 2.2 8051 Real Time Contra. 2.2.1 Programming Timer interrupts 42. Explain the use of timers and counters available in 8051 microcontroller. Oct-20, (R16), 048) (or) Explain the concept of timers and counter of 8051 microcontroller. pe ; Basic Registers of Timer & 8051 microcontroller consists of two timers i..,timerO and timer, Each timer register is of 16-bit wide. Since, 8051 isa 8-bit microcontroller, each register is separated into two registers as shown in figure below. big os [os] Figure (1}: TimerO Registers eo a EE Pm T= Figure (2k: Timert Registers Where, 1D0-D7— Lower byte register D8-D15- Higher byte ne as : register separated into two Fe Toe ee re represents higher byte register. Timer0 register is used in the same way as registers Ay, R2 etc. ea $ _ Timerl isa 16-bit register separated into two registers TLI and TLI. THI represents lower byte register and ‘THI represents higher byte register. Timer! register is ‘accessed similar to timer0, 4 The timers 0 and 1 use TMOD register for setting different modes. 3 ‘Timer Mode Register (TMOD) ‘Timers of 8051 microcontrollers has four types of modes. namely mode-0, model, mode 2 and mode 3. Selection of a particular mode is done by setting mode bits M1 and MO in a register known as Timer Mode register (TMOD) as shown in figure (3). : 3 [se wo [cue [ort | oa | wo ‘MI Gate Figure (3: Timer Mode Register (TMOD) ‘The gate bit decides the hardware or software control over timer/ counter. When TRx bit in TCON register = 1, @ . UGate INTxis high Gi) If Gate = 0 then, Timer/Counter x is enabled only when TRx is high ie,, software control. Where, x indicates 1/0, 1 then, Timer/Counter x is enabled when hardware control, ‘The timer/counter bit decides the type of operation (timer ‘or counter) to be performed. If C/T = 1, counter operation is performed. IfC/T = 0, timer operation is performed. S2/gpECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS wae : “Mode select bits MO, MI selects the timer mode, There Met pa ote ade? nd made 3 Shalt below: [a [wo [ato 0 [0 | Modeo. ° Mode ‘Mode 1: Mode ‘aas. Explain: TeON (1) TMOD registers in detal, ‘aos, 2160) (on Describe the timer control (TCON) and timer ‘mode control (TMOD) regiaters. (on) Explain about TCON special function register with a diagram in 8051 microcontroller. Nowee-18 18, a) Ans: © TCON cTimer Control Register) ‘TCON is an 8-bitrepister in which higher nibbles used. © sore-TE and Ti bits ofboth timer O and timer I wherees lower nibble is used for coatolling interop. Bit assignment OFTCON register is shown ia igure below. ‘uses when tier roll 1s 0, When processor vectors ‘to nemup service routine TF biti cleared 3 ‘TRI (Timert Rus Control Bi) It is sto enable the timer to count, when i is cleared Sime stops counting, ‘THO Crimer0 Overtow Fig) " ist wen ime roll 6100, When proceso vectors 1oinemuptscvce eine TPO bits clean ) TG WARMING: comrade RIANA a. ‘wer. But many manufacturers datasets have sx ete, Since the inlude Reset. ‘The 8051 have'fve interrupt which are avalalele “These extemal ntrupt af koi dees lotion of INTO 5 O03 Sei comminicaton contain onlyone iter hid is wed for bth tansnsion ad ception ‘Table below shows the inert vector able rib BS, Aayonm od ity i LIBLE face LEGAL poses. SND 2. (Inrodieton to unir-2 AroceoUoers a 051 Ret Tine Conch) Trap 2.28 all oll ell HYPE ay cll ‘Example: The seal interrpt could be asgned the highest fy by sing PS in IP regis lle 10. UNIT-2_(ntroduction to Microcontrollers and 8051 Ri = {eal Time Control) 2.25 errupt sept ROM Location (Hex) [Pin | Internal RAM(Iex) External hardware interna S009 9 Aa tt Timer O interrupn CTO)? UNTO 003 -P3.212) Auto ssid _ 0008, 2 Auto Extemal harvare inter 1 @N TY) bi Timer | iteupt cr) fas P3.3(13) Auto: Serial COM interrupt (RI and-TH) 0023 = | crear ty prograniner Table: Interrupt Ve (45. Draw and explain the following SFRs, a Jt (a) Ie : = [= Tren [rn rer] (b) IP pened 7 Ce ese : roe anes Ans: : Dec.-17, (R13), 10 —— te (#) Enabling and Disabling an Interrupt: When the ree parr fo reset pin is mode high, all interrupts are disabled | "eReess —————. (masked), that is none of them are recognized by the microcontroller, though they are enabled. These should be activated by software so that the microcontroller can respond (recognize) to interrupts. A register called IE (Interrupt Enable) is used for enabling (unmasking) and disabling (masking) the interrupts, Figure (1) shows TE bit addressable register. Te Ne 5s a aa toe ca | — [er | es [ent Figure (1: Interrupt Enable (IE) Spe IE.7 EA : Enable All: Disables all interrupts, if EA = 0 i, no interruft is recognized (acknowledged). If EA = 1, each interrupt source is individually enabled, or disabled by setting orclearing its enable bit. IEG : Reserved IES ET2: Enable Timer 2 Overflow Interrupt If ET2 = 1, timer 2 overflow or capture interrupt is enabled, If ET2 = 0, the timer 2 interrupt is disabled. IE.4 ES: Enable Serial Port Interrupt ES = | enables serial port interrupt and ES = 0 disables serial port interrupt. 1E3 ETI: Enable Timer1 Overflow Interrupt ET] =1 enables overflow interrupt and ET! =0 disables it TEZEX1: rnal Interrupt I~ EXL ries exnal interrupt} and EX1= O disables it TE.LETO: Enable Timer0 Overflow Interrupt ‘ ETO = 1 enables’ timer0 overflow interpt ETO = disables it. TEOEX0: Enable External Interrupt 0 es oa cle I ar) ©) Interrupt Priorities: Interrupt geo! priority ermine wheter a Hy eh ot lower priority. Fis 7 beset oe : Seer [ALLIN-ONE JOURNAL FOR ENGINEERING STUI ENTS! ES Figure (2k Interrupt Priority (IP) Special Function Register — Bitssetto tes higher priority and bits cleared to (O indicates lower priority. Interrupts with a high priority can interrupt another interrupt with alow priority. The lower priority interrupt continues after the higher is finished. Iftwo interrupts with the same priority occurs at atime, then the priority level shown in table (2) can be used. ‘S.No Interrupt Priority Level | 1, [Reset Highest 2, [External Interrupt o(iNTo) | 3, , | Timier/Counter 0 overflow (TFO) : 4, | External Interrupt 1 (INTL) : 5. | Timer/Counter 1 overflow (TF1) : 6._| Serial Com Interrupt (Ror TD “| Lowest ‘Table (2k Priority Level Table Example: The serial interrupt could be assigned the highest priority by setting PS bitin IP register to “1° all others to °0°. ree others 10 46. Give the sequenc nts that takes plac when the interrupt occurs in 8051, Ans: Interrupt Service Routine: Each interrupt has an Interrupt Service Routine (ISR). When an interrupt is recognized, the jcrocontroller branches to the ISR. For each interrupt there isa fixed location in memory that holds the address of its ISR. ‘The group of memory locations set aside to hold the addresses of ISRs is called the interrupt vector table. Steps In Executing an. Interrupt: The 8051, examines the interrupts at the chd of every machine cycle’(S6 state). Once the interrupt is recognized the microcontroller goes through the following steps, MICROPROCESSORS AND Nin se FenALPto generate the 1kHz square wave | & Whena low-level signal is applied tthe activated Gnome nse Soe (rel pent te ee ropa exci om 29 Fecal abe o prove eve Ta eo er a 2: Po genet the 1 kite square waveform sng ere ee lggeed eat Te tis fae of ealnchg np at | moma ee ON SO ea rogranning en blow pn ec ithe lt mode NT pn mag Sat te os of ner Stes hrgiers ation eos jusing mode 1 timer programming. ‘ar, (R19, O80) "MOV PI, #00000000B ; Timer 0 Mode 1 ‘made high prior tothe execution of RET! instruction | new incoming serial data "ke

ee ne mes afoyrsen a comma eee ‘ORG 30H intended = | cine ceref ein PCOX wet ane MAIN; MOV JE, #100061008 9 The tsl mice Tore # Mamie ers we HERE: SIMP HERE, ;StyTeruntl | Rmlememie titsecaes| cimeyersonnemnome {got inert trnnered an recive teeter ea , ee un bel abe Torani and ee | seer pins TxD and BD RP ged ae 7 sere re oly external hardware intros inthe | 5 : sn cn eet 8051 namely INTO, INT {Q55. What are the serial communication Interupt fet te dt ee SO oe eck an ao aan ey cana EBzend B30 gor 3, | oft mirecontao”? | RESShattie a == Toy re The net etre feats OO3H | Anas ae ane espe SH are et aside for INTO and INTI respectively “the imerrpts, which ae responable for serial |) The SBUF reps 6 ace connate ‘They are enabled and disabled using the TE register ‘communication in 8051 are as follows, | is used by serial port} iar: PCO Ree “Tresor two activation level forth exe ara ‘Transrolt faterrupt (TD) reise tea pts They ae roan actin si tanymiteiee ds Theat deat eiggered Interr¥Rt Tape including sop bit, in SBUF epiner #2 eri n “rode, basically INTO and NT! | 1 signif thatthe SBUF register is ready to transmit ee eo econ Ie the Jee otha of al VO po is peat ata ae | le i ee ay ne. fc tal wom OED | 2.32 soe un “Rene tain pon ono i an MOURA Cine avant ; MOV TMOD, #20; Hetialie timer 1 in mode 2 i NOTH ADIL Lenlomen tptO0 0 NOWSCONLestL Seta meth ctl i Now 08; Eel i samt Santee! wack: MOAR! Res bom? MOVPLA ——iSetitped | SIMPDACK Rape | 0 2.2.4 Programming 8051 Timers and Counters (5. Expun with waveform erent modes of counter In 8051. (on) 4 en ees ka id doe reo for) [tnt ate oan of Tow ae Cont. (Refer Only Mode 2) 0 ._Reseribe about the timer made 0 with a eat sketch n 851 microcontole, Nove 9 Refer Only Mose 0) 4 hen one : © EADS i won oft Tene TL Th per 3 |® Hallows faading of values between OO00H to IFFFH in TH and TL registers. _ . Seno Ta rs loses he mer stars by sting the run bit, TR using the instructions SETB TRO forint ‘neers come minum ve (IFFH ached hen ost COOH eng th ag HATE When T=, Getic saps and cl he fa ° singh nstrcons CLR TRO or Ter 0 i Operatonet mode Ofsted in gu) ee CL TR rT | verH {ay Jot unit Mode * iis a Vsbit tie Feit wie c tet which allows lating of aes tween OOOH to FFFFH in TLand TH registers ‘Once the estes are oad the SETI TRI fortine incr by sing the rn it, TR ing he instrcton SET TRO former © and 4 Qce the tier sar icount il the maximum value (FFFFH)s reached and then rolls o 0000H sein he flag bit TF high. :. VTP = lth timer stops and cles the agit sng the nsctons CLR TRO for Tener © and CLR TRI for Tier Ontecldbmeeaiei (XTAL an a Yo oo sek im, 5 enor ta ses Tr en ttt le er dagen $ Mnoanaeny $ tamer reer geet Tg: Te ete Sentara Senate 4 Once the tinier stn, it counts by incrementing the TL register uni the maximum value (FFH) i reaches and then rolls Sota ; When TF~ the TL register automatically reloads th xii vale from TH. Spauerctectetaces ter) aa ie ~ i os bed oa =F = r ar Het ineainees ee Me queemteygnanlomar tbat tem Soe ng Reena Tt at latent ot meri} rE Tha wrote ye ange a im Bees a Tb rasnebe edn eT nod sets the TF fag whenitoverows Operation of mode 3 sits in fe (8) “Teeter Feat or} FI} + oe wo po Bee ay

You might also like