excl Section, 43. it Set critica orithms, ample, tion 53, to exe 's algo 8 10 simulta. of their \s simul a smal Mutual es hard I exclue of varie | modify g incon - mutual that are (FCFS) t's algo: ads fal ray (0 sstpones tributed 1 neces ctworked 35 Hardware Solutions 10 the Mutual Exclusion pose multiple threads obtain the same ticket value. Inthe sample code provided, the su? thre what o 1) There is latency between a computer's sending a message and the receiving com Me ‘meaning that mutual exclusion algorithms must acount for delays J with the lowest unique identifier enters its ertical section frst, Does it matter in + these threads enter their critical sections? pate wien a thread modifies a shared variable and when another thread attempls to enter Peel section. 2) The whole system could suffer from indefinite postponement. Suppose a He exminated while choosing a ticket number, and therefore choosing for that thread Fae ero rue forever, Orher threads wishing to ener mutual exclsion Would wat for en he terminated thread to set the choosing array entry to false. 3) Unless the pro- Mert 3 ) » BS Haraware Solutions to the Mutual Exclusion Froblam {nthe preceding examples the software solutions to the mutual exclusion problem that make few assumptions about the system's instruction set and hardware capa fillies As discussed in Chapter 2, Hardware and Software Concepts, hardware Gesigners tend to implement mechanisms previously handled by software to e development time, This section presents several improve performance and reduc mechanisms provided in hardware to help solve the problem of mutual exclusion, BEN Pisabing Interrupts Iaigely that preemption allows multiple threads to access shared da nously, which can result in program errors. Threads are typically preempted by clock (to signal quantum expiration). Therefore, interrupts such as the interrupting simple way to enforce mutual exclusion is to disable (or mask) interrupts. Unfor- lunately, the disabling of interrupts places limitations on what software can do inside a critical section. For example,a thread that enters an infinite loop in its crit fal section after disabling interrupts will never yield its processor. On a uniproces- Sor system, the operating system could no longer use timer interrupts to gain tontrol of the processor, meaning that the system will hang, In real-time systems, Such as an air traffic control system, such a result could put people's lives at risk. Disabling interrupts is not a viable solution for mutual exclusion in a multi: Processor system. After all, its purpose is to ensure that preemption will not occur However, in a multiprocessor system, two threads can execute at the same time, tach on a different processor. If these threads are unsynchronized, disabling inter: upis alone does not prevent them from simultaneously executing inside their eriti- Gal sections. Therefore, simply disabling interrupts on either processor (or both) is rating system designers sufficient to enforce mutual exclusion. In general, op §Void disabling interrupts to provide mutual exclusion. However, there are a lim- lem 221ironows Concurrent Execution ted set of solutions in which it is optimal for the kernel to disable interrupts fop trusted code whose execution requires a short period of time. See the Linux anq Windows XP case studies in Chapters 20 and 21, respectively, for examples of hoy, current operating systems enforce mutual exclusion by disabling interrupts Sel? Review TIF) Ifa thread enters an infinite loop after disabling interrupts on a multiprocessor sy {em, the operating system ean no longer execute 2. Why should a thread avoid requesting blocking UO in a critical section in a uniprocessoe system while interrupts are disabled” Ang, 1) False. The operatit ‘not disabled. The thread inthe infinite loop can be aborted or restarted, but any data it sharas with other threads may be left in an inconsistent state, which may eause program errors 2, ‘When a thread requests blocking 1/O, the operating system places that thread in the Blocked state until it receives an UO completion event, Since such events are generated by hardware nterrupts, but the operating system would never receive this signal while interrup ;emained disabled. As a result, the thread will remain waiting in the blocked state for aq event it will never receive, This is an example of deadlock, which is further discussed iq Chapter 7, Deadlock and Indefinite Postponement 2B2 Test-and-Set Instruction Disabling interrupts is rarely a practical solution to the synchronization problem, so other techniques include the use of special hardware instructions. Recall from our previous examples that shared data can become corrupted because the system may preempt a thread after it has read the value at a memory location, but before the thread can write a new value to the location. The test-and-set instruction enables @ thread to perform this operation atomically (ic, indivisibly):. Such operations are also described as atomic read-modify-write (RMW) memory operations because the processor reads a value from memory, modifies its value in its registers and writes the modified value to memory without interruption The previous examples of software mutual exclusion required that a thread ting a critical section, then read a variable to determine that no other thread is exe set a variable, known as a lock, to indicate that the thread is executing its critical exclusive acess to critical sections section, The difficulty in guaranteeing mutual in software was that a thread could be preempted between testing the availabilty of is from entering their eritical a critical section and setting a lock to keep other threa sections, The testAndSet instruction eliminates the possibility of preemption occurring during this interval The instruction testandset( a, b > c of b, which may be either works as follows. First the instruction reads the v true or false. Then, the value is copied into a, and the instruction sets the value of bto true,ups are it shares 1085,2) loc ard errupts ¢ for an blem, so em ma fore the erations, registers s critical | sections ability of critical eemption be either e value of 55 Hardware Solutions to the Mutual Exclusion Frotlem critical fariable occupied. IfT> is not in its critical section, the value of occupied is False Inthis case, the testAndSet assigns false to variable plMustiWait and sets occu~ ed 10 true. The whi Te fails at this point and'T} enters ils critical section, Because the indivisible hardware instruction set occupied to true, T> will be unable to enter its critical section until T; has reset occupied to false. System: boolean occupied = 1 2 3 A 5 startThreadsQ); // init aun nth 6 7 Thread Ty: 8 9 void mainQ) 41 boolean plMustWwait = true; 13 while ¢ Idone ) mi 15 while C plMustwait > 16 ( v7 testAndSet( piustWait, occupied ); B } 2 piMusthait = true; BL Thread T2: Figure £17 | vestandset struction for mutual exclusion, (Part V of 2.)224 Asynchronous Concurrent Execution 33. void mainQ) 34 35 boolean p2Mustwait 36 37 while ( Idone ) 3B it 39 while C p2Mustwait > 40 { a testAndSet(, p2MustWvait, occupied 2 » 3 “4 tical section code 45 46 paMustWait = trues 47 occupied = false; 48 49 code outside critical section 50 51} // end while 52 53 } // end Thread tion for mutual exclusion. (Part 2 of 2.) Figure 5.1% | vestAndSet msi Now suppose that T? already is in its critical section when Ty wants to enter: I this case, occupied remains true during Ty's repeated while tests, Therefore, Tj continues its busy waiting until T eventually leaves its critical section and sei occupied to false. At this point, the testAndSet assigns occupied’s value to plMustuiait, thus allowing T; to enter Although tes ts critical se ndSet as used here does guarantee mutual exclusion, th solution may suffer from indefinite postponement. Itis possible for a thread to exit the critical section and loop around to call testAndSet before the competing thread has a chance to execute again. Self Review Does the algorithm in Fig. 5 2, (TIF) The testandSet prevent indefinite postponement? instruction enforces mutwal exclusion. Ans. 1) No, the algorithm in Fig. 5.13 requires a favoredProcess variable as discusse il Section 5.4.1, Dekker’s Algorithm, to prevent indefinite postponement. 2) False. Th testAndSet instruction is a tool that programmers use to simplify software solutions i mutual exclusion but the insteuetion itself does not enforce mutual exclusion, IGP Swap Instruction To simplify synchronization code and improve program efficiency, tures provide several atomic instructions. However, each architecture suppor different set of atomic operations, meaning the testAndSet instruction might nil55 Hardnare Solutions to the Mutual Excleston Frotiam 22F tion, we demon aiate J-modify-write memory station can provide functionality identical to the testandSet instruction. “a Tt is common for programs to exchange (or swap) values stored in two differ bles (consider, for example, the Quicksort algorithm). Although the con = gvailable £0 the application or system programmer. In this be iy pow another instruction that performs an atomic ent is simple, a successful exchange of values between two variables in most high P| programming languages requires three instructions and the creation of a tem- jevel proe™ porary variable: b= temp Because such swapping ops rations are performed regul ly, many architec- e the values of the ures support a sn vo variables atomically The instruction instruction that enables a thread to exchan, swap a, b) proceeds as follows, First the instruction loads the value of b, which may be either true or False, into a temporary register. Then, the value of a is copied to b and the value of the temporary register is copied to a. 2.) Figure 5.14 shows how a thread can employ swap to enforce mutual exclusion ener, Similar o Fie 513, the global boolean variable, occupied is true if either thread is 7 EP) iniscrtal section Thread Ty decides to ener its eral setion based on its local refs TH J joc variable, paMustwai. Similry thread" decides to enters rita section + and SF based on its local variable p2musthatt, Note thatthe swap instruction can be used interchangeably with the testAndSet instruction in this gorithm. The only differ ice between Fig. 5.13 and Fig. 5.14 is that we have created a “fast track” to the criti fal section, in which control of the critical section can be obtained by the execution of sion, the cad to ex competing [he Fever instruction (ie, by testing the loop condition after the swap instruction, Bien: 2 Bi crean|eecipied'= false; ; Sonsell) starcThreads(; // initialize and Taunch both threads “sie Ten 7 Trea, sot i : void maing) io { q boolean piMustwait = true; ast architée . supports vent ae: Ure 5.1% | swap mstruction for mutual exclusion. (Fart tof 2.)226 Asynchronous Concurrent. xecution 13 while ¢ Idone ) SAP at 15 do 16 { v swap( plMustWait, occupied ); 18 } white C piMustWait ); 19 20 critical section code 2 2 plMustait = true; 23 occupied = false; 24 25 de outside critical section 26 27 // end whit 28 29} // end Thread TL 30 31 ‘Thread T3: 32 33. void main Mf 35 boolean p2Musthait = true; 36 37 while ( done ) 38 ER 39 do 40 { 41 swap( p2MustWait, occupied ); a2 } white ( p2mustwait ); 43 44 / critical section cod 45 46 p2tus a7 occupied = false; 48 49 de outside critical section 50 51} // end white 52 53} // end Thread T2 Figure 2. | swap mstruction for nsutual exclusion. (Fart 2 of 2.) Salt Review 1. Why might it be more likely for a swap instruction to be on a system than a testAndset? Ang: Many algorithms require some sort of swapping, so hardware instruction, sw. ‘ery useful for algorithms other than ost those providing mutual exclusion