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UART

The document contains code for UART transmitter and receiver modules and testbenches to test their functionality. The transmitter module takes in a data byte and clock input and serially transmits the bits by generating start, data and stop bits. The receiver module receives the serial bits and reassembles the byte by detecting start, data and stop bits and storing it in an output register. The testbenches apply input test patterns and verify the correct operation of the modules.

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Brainz on Mob
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38 views9 pages

UART

The document contains code for UART transmitter and receiver modules and testbenches to test their functionality. The transmitter module takes in a data byte and clock input and serially transmits the bits by generating start, data and stop bits. The receiver module receives the serial bits and reassembles the byte by detecting start, data and stop bits and storing it in an output register. The testbenches apply input test patterns and verify the correct operation of the modules.

Uploaded by

Brainz on Mob
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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// UART Transmitter code

module uart_transmitter (
input clk, // System clock
input reset, // Reset signal
input enable, // Enable signal
input [7:0] data, // Data input
output reg tx, // Transmitter output
output reg tx_busy // Transmitter busy flag
);

reg [3:0] bit_count;


reg [10:0] shift_reg;
reg start_bit;
reg stop_bit;

always @(posedge clk or posedge reset) begin


if (reset) begin
tx <= 1'b1; // Idle state
tx_busy <= 1'b0;
bit_count <= 4'b0;
shift_reg <= 11'b0;
start_bit <= 1'b0;
stop_bit <= 1'b0;
end
else if (enable) begin
if (bit_count == 4'd0) begin
// Start bit
tx <= 1'b0;
start_bit <= 1'b1;
bit_count <= bit_count + 1;
end
else if (bit_count >= 4'd1 && bit_count <= 4'd8) begin
// Data bits
tx <= shift_reg[0];
shift_reg <= {shift_reg[9:0], data};
bit_count <= bit_count + 1;
end
else if (bit_count == 4'd9) begin
// Stop bit
tx <= 1'b1;
stop_bit <= 1'b1;
bit_count <= bit_count + 1;
end
else if (bit_count == 4'd10) begin
// End of transmission
tx_busy <= 1'b0;
bit_count <= 4'd0;
end
end
else begin
tx_busy <= 1'b0;
end
end

endmodule
// UART Receiver
module uart_receiver (
input clk, // System clock
input reset, // Reset signal
input rx, // Receiver input
output reg enable, // Enable signal
output reg [7:0] data, // Received data
output reg rx_valid // Receiver valid flag
);

reg [3:0] bit_count;


reg [10:0] shift_reg;
reg start_bit;
reg stop_bit;

always @(posedge clk or posedge reset) begin


if (reset) begin
enable <= 1'b0;
data <= 8'b0;
rx_valid <= 1'b0;
bit_count <= 4'b0;
shift_reg <= 11'b0;
start_bit <= 1'b0;
stop_bit <= 1'b0;
end
else begin
if (rx == 1'b0 && !start_bit && !stop_bit) begin
// Start bit detected
enable <= 1'b1;
bit_count <= 4'd1;
start_bit <= 1'b1;
shift_reg <= {shift_reg[9:0], rx};
end
else if (enable && bit_count >= 4'd1 && bit_count <= 4'd8) begin
// Data bits
shift_reg <= {shift_reg[9:0], rx};
bit_count <= bit_count + 1;
end
else if (enable && bit_count == 4'd9) begin
// Stop bit detected
enable <= 1'b0;
rx_valid <= 1'b1;
stop_bit <= 1'b1;
data <= shift_reg[7:0];
bit_count <= bit_count + 1;
end
else if (rx_valid && bit_count == 4'd10) begin
// End of reception
rx_valid <= 1'b0;
bit_count <= 4'd0;
end
else begin
// Idle state
enable <= 1'b0;
start_bit <= 1'b0;
stop_bit <= 1'b0;
end
end
end

endmodule
// Testbench for UART Transmitter
module uart_transmitter_tb;

// Inputs
reg clk;
reg reset;
reg enable;
reg [7:0] data;

// Outputs
wire tx;
wire tx_busy;

// Instantiate the UART Transmitter


uart_transmitter dut (
.clk(clk),
.reset(reset),
.enable(enable),
.data(data),
.tx(tx),
.tx_busy(tx_busy)
);

// Clock generation
always begin
#5 clk = ~clk;
end

// Testcase
initial begin
// Initialize inputs
clk = 0;
reset = 1;
enable = 0;
data = 8'b01010101;

// Reset
#10 reset = 0;

// Transmit data
#10 enable = 1;
#50 enable = 0;

// Wait for transmission completion


#100;

// End simulation
#10 $finish;
end

endmodule
//UART RECEIVER TESTBENCH
`timescale 1ns/1ps

module uart_receiver_tb;

reg clk;
reg reset;
reg rx;
wire enable;
wire [7:0] data;
wire rx_valid;

// Instantiate the UART receiver module


uart_receiver uart_inst (
.clk(clk),
.reset(reset),
.rx(rx),
.enable(enable),
.data(data),
.rx_valid(rx_valid)
);

// Clock generation
always #5 clk = ~clk;

// Testbench stimuli
initial begin
clk = 0;
reset = 1;
rx = 1;
#10 reset = 0;

// Wait for a few cycles for initialization


#20;

// Test 1: Receive byte 0x37


$display("Test 1: Receive byte 0x37");
rx = 0; // Start bit
#10;
rx = 1; // Data bits: 00110111 (LSB first)
#80;
rx = 0; // Stop bit
#10;
rx = 1; // Idle state

// Wait for reception to complete


#100;

// Verify the received data


if (enable && rx_valid && data === 8'h37)
$display("Test 1: PASSED - Correct byte received");
else
$display("Test 1: FAILED - Incorrect byte received");

// Test 2: Receive byte 0xAA


$display("Test 2: Receive byte 0xAA");
rx = 0; // Start bit
#10;
rx = 0; // Data bits: 10101010 (LSB first)
#80;
rx = 0; // Stop bit
#10;
rx = 1; // Idle state

// Wait for reception to complete


#100;

// Verify the received data


if (enable && rx_valid && data === 8'hAA)
$display("Test 2: PASSED - Correct byte received");
else
$display("Test 2: FAILED - Incorrect byte received");

// End the simulation


$finish;
end

endmodule

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