VERILOG INTERVIEW QUESTIONS

1. Explain Verilog
Verilog is a text-based hardware description language used to describe electronic systems and
circuits. Verilog is designed to be used in electronic design for timing analysis, test analysis (fault
grading and testability analysis), logic synthesis, and verification through simulation.
The following three levels of abstraction are supported by Verilog most frequently in a design:
 Behavioural level
 Register-transfer level
 Gate level

2. What is the complete form of VHDL in VLSI?

The acronym VHDL stands for Very High-Speed Integrated Circuit Hardware Description Language.
It is a programming language used to represent the digital system using modeling approaches,
including dataflow, behavioural, and structural, and to describe the circuits in digital systems.

3. What are the main applications for VHDL?

The principal applications of VHDL are as follows.
 The behaviour of electronic circuits; typically, digital circuits are described using the hardware
description language, or VHDL.
 It is mainly used to design hardware and test entities to check how it behaves.
 It is utilized as an entry format for designs by different EDA tools.

4. Are Verilog and VHDL the same thing?

VHDL and Verilog are not interchangeable. They are distinct from one another, with the primary
distinction being that Verilog is based on the C language, whereas VHDL is based on the Ada and
Pascal languages.

5.Describe HDL simulators.

Simulating expressions written in one of the Hardware Description Languages, such as Verilog,
VHDL, or System Verilog, is done using software programs known as HDL simulators.

6. How do VHDL and Verilog differ from one another?

This Verilog interview question is one of the most frequently asked. Let us compare them to identify
their significant differences.

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 VERILOG INTERVIEW QUESTIONS

VHDL Verilog

It was established in 1980, making it an older It was formed between late 1983 and early
language. 1984.

It uses the base languages, Ada and Pascal The base language is C.

The VHDL language is more compact. It contains comparatively more LOCs or

lines of code.

As a language that encompasses more extensive Considered to be of considerably lower level as a

capabilities than just modeling systems, VHDL language mainly used for modeling,
is more reliable and developed.

VHDL is not case sensitive Verilog is case sensitive

VHDL analyses and simulates the behavior of the They are only applied to describe digital
digital system in addition to describing its structure. systems.

7. Differentiate between blocking systems in Verilog from non-blocking systems?

This is just another of the general Verilog interview questions. In Verilog, blocking and non-blocking
procedural assignment statements are two different sorts. They differ in the assignment operators they
use, which are denoted by the symbols = and <=.

Blocking System Non-Blocking System

Blocking is the simple term for when one Non-blocking allows assignments to be executed
register assignment prevents another concurrently regardless of the sequence of
assignment from being executed dependencies.
simultaneously.

Assignments will only be blocked in order Non-blocking will plan the execution of
until the one before them is finished. In sequential assignments so that concurrent
execution of tasks is possible.

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 VERILOG INTERVIEW QUESTIONS

Blocking System Non-Blocking System

contrast, it does not stop when running in

parallel.

8. What is PLI? Mention its uses.

It is one of the most asked Verilog interview questions. Programming Language Interface is known
by the acronym PLI. It is a method that makes it easier for C and Verilog applications to interface
with one another. Additionally, it offers a way for the C program to access the simulator's internal
databases. The users can use PLI to implement challenging system calls using Verilog syntax.
Additionally, it offers the benefits of Verilog's parallel and hardware-related features and the
sequential development of a C program.

9. What do you mean by sensitivity list?

The sensitivity list defines that when changes are made to any of the list's elements, a begin-end
statement must be placed inside that element.

10. What do you know about Verilog parallel and full case statements?
In Verilog, there are two different kinds of case statements.
 Verilog parallel case statements: A statement that matches just one case item in a case
expression is referred to as a parallel case statement. The matching case items are known as
"overlapping case items," The case statement would not be parallel if you could find a case
expression that would fit more than one case item.
 Verilog full case statements: Every case expression in a Verilog full case statement must
have binary patterns that match either a case item or the default. The case statement would
not be regarded as complete if it did not include a case default and was likely to come across
a binary case expression that did not match any of the specified case elements.

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 VERILOG INTERVIEW QUESTIONS

11. What is the distinction between == and === in Verilog?

== ===

The key distinction between == and === The output of ===, on the other hand, can only
in Verilog is that the result of == can be either 0 or 1.
either be 1, 0 or X.

If two numbers are compared using == and one or The result of a === comparison between two
both numbers have one or more bits set to X, the numbers would be either 0 or 1.
result will be X.

Since it cannot compare Xs, == can only be used Xs can also be compared using ===.
to compare 1s and 0s.

12. What do you mean by $monitor, $display, and $strobe?

The $monitor, $display, and $strobe commands all have a similar syntax and display text on the
screen while a simulation is ongoing. Compared to waveform tools like cwaves, these commands are
often less user-friendly.
 $monitor:
Syntax: $Monitor(<format_string>,<parameter>,<parameter>)
When $Monitor is used, it will execute and display the parameters each time one of the parameters is
modified, that is, each time a new value for the parameter is displayed. Signals can be expressions,
variables, or strings, and signal values can be changed using the $Monitor command.
 $display:
Syntax: $display(<list of arguments>);
Another task for arguments is $display, which also aids debugging.
$display will always append a newline to the end of the string while showing the arguments.
 $strobe:
Syntax: $display(<list of arguments>);
In terms of the format of presenting its arguments, $strobe is quite similar to $display; however, it
will only display all of its arguments after the current time unit.

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 VERILOG INTERVIEW QUESTIONS

13. What are the primary differences between Verilog's Task and Function?
Another most frequently asked Verilog interview question. The key distinctions between a Task and
a Function in Verilog are as follows:

Task Function

In Verilog, tasks can activate both additional A function in Verilog can enable other functions
tasks and functions. but cannot allow a task.

A task is permitted to contain any event, delay, Event, delay, or timing control statements are
or timing control statement. not allowed. Hence they cannot be contained in
a function.

The simulation for tasks is also zero. However, Because the program time is not increased
they can also be carried out in a simulation time during the function routine, a function can do its
that is not zero if necessary. required task in zero simulation time.

A task may employ zero or more arguments of A function must receive at least one parameter
the output or input types arguments. when it is invoked.

Using the output and input statements, a task Functions cannot employ either output or input
can pass multiple values but cannot return a statements and only return a single value.
value.

14. How are blocking and non-blocking assignments executed?

Executing blocking and non-blocking assignments is a simple process. We must follow a
straightforward process of evaluating the right-side equation and updating the left-side expression
without interference from another Verilog statement to carry out blocking assignments. On the other
hand, there are two processes involved in non-blocking assignments:
 At the beginning of the time step, evaluate the right-hand side of every non-blocking
statement.
 After the time step, update the left side of all non-blocking statements.

15. What do you mean by continuous assignment?

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 VERILOG INTERVIEW QUESTIONS

Combinational logic is modelled using continuous assignment statements in Verilog. Combinational

logic refers to the digital logic that Boolean circuits implement. The sole pure function of the inputs
in combinational logic is the output. The present information depends on the present input and the
past inputs in sequential logic but not in combinational logic. The assigned statement or a wire
declaration is used to implement the continuous assignment statements.

Verilog Interview Questions for Experienced

16. What do you mean by inertial delay and transport delay?
 Inertial delay: The time it takes for a gate to change its output is known as the inertial delay.
 Transport delay: One sort of delay brought on by the wires connecting to the gates is
transport delay. The signal is delayed by the resistance and inductance of the wire.

17. What does a Verilog repeat loop do?

As its name suggests, the repeat loop behaves like loops used in popular programming languages like
the for a loop. A repeat loop will execute a piece of code as often as it is accessed. The repeating
piece of code will not make any reference to the loop cycle.
Syntax: repeat(<no. of times the loop will run>) <statement to be repeated>
Repetition in a line of code can be avoided with a repeat loop.

18. What are the key differences between Reg and Wire?
Reg and wire are often an interviewer’s favourite in the Verilog interview questions, so it is important
to prepare them thoroughly. Essential differences between Reg and Wire are:

Reg Wire

Reg is employed to store value. The wire is employed to determine value.

Reg can get the output without a driver. The wire needs drivers to obtain output values.

The reg components can be used for both The only type of logic that the wire elements can
sequential and combinational logic. model is combinational logic.

Reg cannot be used on an assigned statement's Wire can be used on the left-hand side of a given
left-hand side. statement.

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19. How do you write FSM code in Verilog?

In Verilog, there are primarily four approaches to writing FSM code:
 We are utilizing the first approach, which combines the output decoder, present state, and all
input decoders into a single operation.
 Using the second approach, all sequential and combinational circuits are isolated using a
different procedure.
 Using the third approach, the output decoder is segregated into different processes while the
input decoder and current state are integrated.
 The output decoder, present state, and all three input decoders are divided into three
processes using the fourth approach.

20. Which will be updated first between the variable and the signal?
Variables can only be used inside processes, whereas signals are used inside and outside. As a result,
signals are updated before variables are updated.

21. Is it required to list every input in the sensitivity disc for a pure combinational circuit? If
so, why then?
Yes. If you don't list every input in the sensitivity disc for a pure combinational circuit, the outcome
will have a pre- and post-synthesis mismatch.

22. Explain the Verilog concepts of freeze, deposit, force, and drive.
It is important to know the various concepts of Verilog used as they are often asked in Verilog
interview questions.
Freeze: For unresolved signals, use freeze. Throughout the simulation, the signal's value is frozen.
You cannot modify this value.
Deposit: Deposit ensures that a signal value is kept until it is altered or replaced by the simulation.
Throughout the simulation, it serves as value initialization.
Force: It can drive signals at any point during the simulation.
Drive: When the drive command gives a signal a value, it will "resolve" to a new value if the
simulation updates the signal.

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23. What distinguishes a $monitor from a $display?

The test bench results are displayed using the system commands or functions $monitor and $display.
The list of significant changes between $monitor and $display is below.

$monitor $display

Changes to the signal's value are made via the It is used to display a signal's value.
monitor. An expression, string, or variable can be
a signal.

There can be only one execution of the monitor You can use the display command more than
command. once.

24. What does the Verilog code timeframe 1 Ns/ 1 Ps mean?

A compiler directive used to calculate simulation or delay times is called the timeframe directive. The
timescale / reference_time_unit defines the unit of measurement for delays and times. The accuracy
to which the delays are rounded off is specified by time_precision.

25. In Verilog, what do the casex and casez statements mean?

Verilog has two different forms of case statements: casex and casez. All z values in the case
alternatives or the case expression are treated as don't cares in this case by casez. The character? can
also represent any bit position with the character z. All z and x values in the case item or the case
expression are treated as don't cares by casex. We must use casex, and casez since do not cares are
not permitted in a case statement.

26. Write a Verilog program to switch the contents of two registers with and without a
temporary register.
An example of a Verilog code that switches the contents of two registers with a temporary register:
always @ (posedge clock)
begin
temp=y;
y=x;

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 VERILOG INTERVIEW QUESTIONS

x=temp;
end.
Without a temporary register, a Verilog program can swap the contents of two registers:
always @ (posedge clock)
begin
x <= y;
y <= x;
end

27. How can a sine wave be produced using Verilog coding?

The CORDIC algorithm is the fastest and most effective method for creating sine waves.

28. What is the difference between blocking and non-blocking assignments?

In Verilog, the difference between blocking and non-blocking assignments depends on the way they
handle the execution of statements within procedural blocks, such as "always" blocks. Blocking
assignments are represented by the "=" operator, and it executes immediately in sequential order.
While the "<=" operator represents non-blocking assignments, and it introduces a level of
concurrency in Verilog, the RHS statement is computed concurrently with other statements, so it is
non-blocking in nature.

29. When should you use tasks instead of functions?

You should use tasks instead of functions in Verilog when you need to perform a sequence of
procedural actions or when you require multiple input/output variables. Tasks are more suitable for
modelling complex behaviour. They can contain both procedural statements and timing controls,
allowing you to model more complicated processes.

30. Can race conditions occur in Verilog?

Yes, race conditions can occur in Verilog. A race condition arises due to concurrent events happening
in different orders, and the final outcome depends on the order of timing of these events.

31.Which logic level is not supported by Verilog?

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 VERILOG INTERVIEW QUESTIONS

Verilog is versatile enough to model digital circuits using various logic levels; however, it is not
specifically designed to support analog circuit descriptions, as it is primarily focused on digital logic
modelling. For analog circuit design, another language called Verilog-A is typically used.

32.Which loops are supported by Verilog?

Verilog supports For loops, while loops, forever loops, and Repeat loops. In all these loops, begin
and end keywords are used to enclose multiple statements as a single block.

33.What are the features of VHDL?

Very High-speed integrated circuit HDL describes and simulates the system before making it into a
digital one. Its features are

 Complexity management
 Design data portability
 Independent of technology
 Efficient and less time consuming
 Readability

34.What is the Factory and Factory pattern?

A factory creates different objects for a prototype. It is done By calling the corresponding constructor
when different classes are registered with the factory.

The Factory pattern directly creates an object without calling the constructor method. It allows the
use of polymorphism for object creation.

35.What is Callback?

A callback is when a function calls another function taking the first one as an argument. It is used
when an event happens. It includes calling back a function

 to inject errors on transactions

 To train depending on transactions

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 VERILOG INTERVIEW QUESTIONS

Virtual Pure virtual

It allows the overriding of a function in a It has only declaration and no

derived class implementation

The base class does not need to implement a Any derivative class must
virtual function implement the function

 In the event of a specific occurrence

36. What is Virtual and Pure virtual function in Verilog?

37. What is DPI called?

The Direct programming interface is a bridge between system Verilog and any other foreign
programming language like Python. It ensures direct inter-language function calls doing
languages on both sides of the interface. It supports both functions and tasks across the
boundary.

38. What is Parameter and Typedef in Verilog?

A parameter is a constant value within the module structure used to define various attributes
for the module. It also characterizes the behaviour and physical representation of the module.

Typedef Enables users to craft unique names for type definitions for frequent use in their
codes. They are easily used while building technical array definitions.

39. Explain some uses of Clocking Blocks

Clocking Block is used for

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 VERILOG INTERVIEW QUESTIONS

 Specifying synchronization characteristics of a design

 Testbench driving the signals at the right time
 Cleaning the drive and sample design and race-free operations in specific applications

40. What is the need for an Alias in Verilog?

An alias statement offers a bidirectional and short circuit connection. Usually, a Verilog has a
one-way assign statement which may have delay and strength changes for unidirectional
assignment.

41. What is Verilog used for?

 To model electronic systems

 Designing and verifying digital circuits

 Verification of analog circuits and mixed-signal circuits

 Designing genetic circuits

42.What software is used for Verilog?

Some of the Verilog Simulators are Cascade, GPL Cyer, Icarus Verilog, Isotel Mixed Signal
& Domain Simulation, LIFTING, OSS CVC, TKGate, Verilator, Verilog Behavioural
Simulator, VeriWell

43. What is RTL in Verilog?

RTL is the Register transfer level. It means Verilog code describes data transformation as it
passes register to register. This transformation is done by combination logic that exists between
registers.

44.What Is Meant by Inferring Latches, how To Avoid It?

Consider the following :

always @(s1 or s0 or i0 or i1 or i2 or i3)

case ({s1, s0})

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 VERILOG INTERVIEW QUESTIONS

2’d0 : out = i0;

2’d1 : out = i1;
2’d2 : out = i2;
endcase

in a case statement if all the possible combinations are not compared and default is also not
specified like in example above a latch will be inferred ,a latch is inferred because to reproduce
the previous value when unknown branch is specified.

For example in above case if {s1,s0}=3 , the previous stored value is reproduced for this storing
a latch is inferred.

The same may be observed in IF statement in case an ELSE IF is not specified.

To avoid inferring latches make sure that all the cases are mentioned if not default condition is
provided.

45. In A Pure Combinational Circuit Is It Necessary to Mention All The Inputs In

Sensitivity Disk? If yes, why?
Yes, in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk
otherwise it will result in pre and post synthesis mismatch.

46. Tell Me Structure of Verilog Code You Follow?

A good template for your Verilog file is shown below.

// timescale directive tells the simulator the base units and precision of the simulation
`timescale 1 ns / 10 ps
module name (input and outputs);
// parameter declarations
parameter parameter_name = parameter value;
// Input output declarations
input in1;
input in2; // single bit inputs
output [msb:lsb] out; // a bus output

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 VERILOG INTERVIEW QUESTIONS

// internal signal register type declaration – register types (only assigned within always
statements). reg register
variable 1;
reg [msb:lsb] register variable 2;
// internal signal. net type declaration – (only assigned outside always statements) wire net
variable 1;
// hierarchy – instantiating another module
reference name instance name (
.pin1 (net1),
.pin2 (net2),
.
.pinn (netn)
);
// synchronous procedures
always @ (posedge clock)
begin
.
end
// combinatinal procedures
always @ (signal1 or signal2 or signal3)
begin
.
end
assign net variable = combinational logic;
endmodule

47. Can You List Out Some of Enhancements in Verilog 2001?

In earlier version of Verilog ,we use ‘or’ to specify more than one element in sensitivity list .
In Verilog 2001, we can use comma as shown in the example below.

// Verilog 2k example for usage of comma

always @ (i1,i2,i3,i4)

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 VERILOG INTERVIEW QUESTIONS

Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS of
combo logics . This removes typo mistakes and thus avoids simulation and synthesis
mismatches, Verilog 2001 allows port direction and data type in the port list of modules as
shown in the example below

module memory (
input r,
input wr,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);

48. There Is a Triangle and On It There Are 3 Ants One on Each Corner and Are Free to
Move Along Sides of Triangle What Is Probability That They Will Collide?
Ants can move only along edges of triangle in either of direction, let us say one is represented
by 1 and another by 0, since there are 3 sides eight combinations are possible, when all ants are
going in same direction, they won’t collide that is 111 or 000 so probability of not collision is
2/8=1/4 or collision probability is 6/8=3/4

49. Will Case Infer Priority Register If Yes How Give an Example?
yes, case can infer priority register depending on coding style
reg r;
// Priority encoded mux,
always @ (a or b or c or select2)
begin
r = c;
case (select2)
2’b00: r = a;
2’b01: r = b;
endcase
end

50. In the given Following Verilog Code, What Value Of “a” Is Displayed?

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 VERILOG INTERVIEW QUESTIONS

always @(clk) begin

a = 0;
a <= 1;
$display(a);
end

This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue for
the current simulation time:

1. Active Events (blocking statements)

2. Inactive Events (#0 delays, etc)
3. Non-Blocking Assign Updates (non-blocking statements)
4. Monitor Events ($display, $monitor, etc).
Since the “a = 0” is an active event, it is scheduled into the 1st “queue”.

The “a <= 1” is a non-blocking event, so it’s placed into the 3rd queue.

Finally, the display statement is placed into the 4th queue. Only events in the active queue are
completed this sim cycle, so the “a = 0” happens, and then the display shows a = 0. If we were
to look at the value of a in the next sim cycle, it would show 1.

51. What Is the Difference Between the Following Two Lines of Verilog Code?
#5 a = b;
a = #5 b;
#5 a = b; Wait five-time units before doing the action for “a = b;”.

a = #5 b; The value of b is calculated and stored in an internal temp register, after five-time
units, assign this stored value to a.

52. How Do You Implement the Bi-directional Ports in Verilog Hdl?

module bidirec (oe, clk, inp, outp, bidir);

// Port Declaration

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 VERILOG INTERVIEW QUESTIONS

input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir;
reg [7:0] a;
reg [7:0] b;
assign bidir = oe ? a : 8’bZ ;
assign outp = b;

// Always Construct

always @ (posedge clk)

begin
b <= bidir;
a <= inp;
end
endmodule

53. What Is Verilog Case (1) ?

wire [3:0] x;
always @(…) begin
case (1’b1)
x[0]: SOMETHING1;
x[1]: SOMETHING2;
x[2]: SOMETHING3;
x[3]: SOMETHING4;
endcase
end

The case statement walks down the list of cases and executes the first one that matches. So
here, if the lowest 1-bit of x is bit 2, then something3 is the statement that will get executed (or
selected by the logic).

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 VERILOG INTERVIEW QUESTIONS

54. Why Is It That “if (2’b01 & 2’b10)…” Doesn’t Run the True Case?
This is a popular coding error. You used the bit wise AND operator (&) where you meant to
use the logical AND operator (&&).

55. What Are Different Types of Verilog Simulators ?

There are mainly two types of simulators available.

 Event Driven
 Cycle Based
Event-based Simulator:
This Digital Logic Simulation method sacrifices performance for rich functionality: every
active signal is calculated for every device it propagates through during a clock cycle. Full
Event-based simulators support 4-28 states; simulation of behavioural HDL, RTL HDL, gate,
and transistor representations; full timing calculations for all devices; and the full HDL
standard. Event-based simulators are like a Swiss Army knife with many different features but
none are particularly fast.
Cycle Based Simulator:
This is a Digital Logic Simulation method that eliminates unnecessary calculations to achieve
huge performance gains in verifying Boolean logic:

 Results are only examined at the end of every clock cycle; and
 The digital logic is the only part of the design simulated (no timing calculations). By
limiting the calculations, Cycle based Simulators can provide huge increases in
performance over conventional Event-based simulators.
Cycle based simulators are more like a high-speed electric carving knife in comparison because
they focus on a subset of the biggest problem: logic verification.

Cycle based simulators are almost invariably used along with Static Timing verifier to
compensate for the lost timing information coverage.

56.What is the difference between: c = foo ? a : b; and if (foo) c = a; else c = b;

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 VERILOG INTERVIEW QUESTIONS

The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b =
'b11, you would get c = 'b1x. On the other hand, if treats Xs or Zs as FALSE, so you would
always get c = b.

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 VERILOG INTERVIEW QUESTIONS

PART-1
1. Write a Verilog code using behavioral modeling for a 4-bit shift register?
2. Write a Verilog code for positive edge triggered D-flip flop with (a) synchronous reset
and (b) asynchronous reset.
3. Describe the difference between the system tasks $monitor and $display?
4. List the differences between tasks and functions.
5. Is there any difference between "==" and "===" in behavioral modeling of verilog?
6. What is the use of non-blocking assignment in behavioral modeling of verilog? How is
it different from blocking- assignment?
7. Given the following Verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
8. Is there any problem in the following code: (a) For simulations (b) For synthesis
and for post synthesis.
always @(cntrl,a,b)
begin
if(cntrl)
a <= b;
end
9. Implement following logic's using minimum number of D Flip-Flops:
a) Clock Divide by 2
b) Clock Divide by 4
10. What is the difference between a Mealy and a Moore finite state machine?
11. Write a Verilog code to swap contents of two registers a and b without any
temporary register?
12. Write a Verilog code for a flip-flop and latch?
13. Write a Verilog code to detect a pattern 10110 from an input stream of bits.
14. What is the difference between reg and wire?
15. Write a Verilog code to print nth Fibonacci number?

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 VERILOG INTERVIEW QUESTIONS

PART-2
1.If a net has no driver, it gets the value.
a)0
b)X
c)Z
d)None of the above
2.Which logic level is not supported by verilog?
a)U
b)X
c)Z
d)None of the above
3.Which level of abstraction level is available in Verilog but not in VHDL?
a)Behavioral level
b)Gate level
c)Dataflow level
d)Switch level
4.Default value of reg is
a)X
b)Z
c)0
d)None of the above
5.If A= 4`b011 and B= 4b`0011, then the result of A**B will be.
a)9
b)6
c)27
d)None of the above
6.If A= 4b`001x and B= 4b`1011, then result of A+B will be.
a)110X
b)1100
c)XXXX
d)None of the above

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 VERILOG INTERVIEW QUESTIONS

7.If A= 4`1xxz and B= 4`b1xxx, then A= = =B will return.

a)1
b)X
c)Z
d)0
8.Initial value of a=1 and b=2, then what will be final value if,
always @ (posedge clock)
a<=b;
always @ (posedge clock)
b<=a;
a)a=2,b=1
b)a=1,b=2
c)Both a and b will have same value either 0 or 1
d)None of the above
9.Variable and signal which will be updated first?
a)Variable
b)Signal
c)Can't say
d)None of the above
10.How many flops will be synthesized by the given code?
always @ (posedge clock) begin
q1<=d;
q2<=q1;
q3<=q2;
end
a)1
b)2
c)3
d)None of the above
11.Which operators has highest precedence in verilog?
a)Unary
b)Multiplication
c)Addition

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 VERILOG INTERVIEW QUESTIONS

d)Conditional
12.What will be the value of c in following case (after 5 sim units)?
initial begin
a=0; b=1;
c = #5 a+b;
end
a)0
b)1
c)2
d)None of the above
13.What is equivalent hardware to meet the following behavior?
always@(a)
if(a==1'b1)
output =1;
else
output=0;
a)Mux
b)Flipflop
c)Latch
d)None of the above
14.Which of the following statement are correct?
a)UDPs can have only one output
b)UDPs can have 1 to 10 inputs
c)The Z logic value is not supported
d)All of the above
15.The task $stop is provided to
a)End simulation
b)Suspend simulation
c)Exit simulator
d)None of the above
16.Turn off delays means,gate output transition to
a)0
b)1

23
 VERILOG INTERVIEW QUESTIONS

c)X
d)Z
17.If there is mismatch in connecting wire such as
W1[7:0]=W2[15:0]
a)The end result is W1[7:0]=W2[15:0]
b)The end result is W1[7:0]=W2[7:0]
c)The end result is W1[15:0]=W2[7:0]
d)None of the above
18.Given the following Verilog code, what value of "a" is displayed?
always @ (clk)
begin
a = 0;
a <= 1;
$display(a);
end
a)0
b)1
c)Both a and b
d)None of the above
19.The LHS of procedural continuous assignments can be
a)Registers or concatenations of registers
b)Nets or concatenation of nets
c)Arrays of nets
d)None of the above
20.For the segment is given below choose the correct answers
bufif0 #(5,6,7) c1(out,in,cntrl)
a)5=rise 6=turnoff 7=fall
b)5=fall 6=rise 7=turnoff
c)5=rise 6=fall 7=turnoff
d)5=turnoff 6=rise 7=fall
21.Which procedural assignments should be used to model a perfect combinational logic
buffer?
a)always@(In)

24
 VERILOG INTERVIEW QUESTIONS

# 5 output<=In;
b)always@(In)
output= #5 In;
c)always@(In)
# 5 output=In;
d)always@(In)
output<= #5 In;
22.Which of the following statement is incorrect?
a)Tasks are part of functions
b)Functions are part of tasks
c)Function are always synthesizable
d)Functions have some inputs
23.Which is legal negative number?
a)4'd-3
b)6'-d3
c)-6'd3
d)None of the above
24.In a pure combinational circuit is it necessary to mention all the inputs in sensitivity
list?
a)No
b)Yes
c)It depends on the coding style
d)None of the above
25.Which is not a correct method of specifying time scale in verilog?
a)1ns/1ps
b)10ns/1ps
c)100ns/100ps
d)100ns/110ps
Answers:
1.c 2.a 3.d 4.a 5.c 6.c 7.d 8.a 9.b 10.c 11.a 12.b 13.a 14.d 15.b 16.d 17.b 18.a
19.a 20.c 21.c 22.a 23.c 24.b 25.d

25
 VERILOG INTERVIEW QUESTIONS

PART-3
1. What logic is inferred when there are multiple assign statements targeting the same
wire?
It is illegal to specify multiple assign statements to the same wire in a synthesizable code that
will become an output port of the module. The synthesis tools give a syntax error that a net is
being driven by more than one source.
2. What do conditional assignments get inferred into?
Conditionals in a continuous assignment are specified through the “?:” operator. Conditionals
get inferred into a multiplexer. For example, the following is the code for a simple Multiplexer:
wire wire1;
assign wire1 = (sel == 1'b1) ? a : b;

3. Why should a non-blocking assignment be used for sequential logic, and what would
happen if a blocking assignment were used? Compare it with the same code in a
combinational block.
The main difference between the blocking and non-blocking assignment is that, in the blocking
assignment, the RHS immediately gets assigned to the LHS, whereas for the nonblocking
assignment, the assignment to the LHS is scheduled after the RHS is evaluated.
Using blocking statements in a sequential logic
The following is an example of a Verilog module in which the blocking assignments have been
used in the sequential block.

26
 VERILOG INTERVIEW QUESTIONS

In the above example, the assignments to the reg1, reg2, reg3, out1 have been made as blocking
assignments. The synthesized result is a single FF, with the d input of in1, and q output of reg3,
as shown in the following figure:

This is because the intermediate results between in1 and out1 were stored in reg1, reg2, and
reg3 in a blocking format. As a result, the evaluation of the final result to out1 didn’t require
waiting for all the events of the RHS to be completed. Rather, they were immediately assigned
to the LHS in the order specified. Observe that the signals reg1, reg2, and reg3 have been
optimized away by synthesis.
Using nonblocking statements in a sequential logic
The following illustration of code uses the nonblocking assignments in a sequential block:

27
 VERILOG INTERVIEW QUESTIONS

In the above example, the assignments to the reg1, reg2, reg3, out1 have been made as
nonblocking assignments. The synthesized result is the inference of as many FFs as specified
in the always block [in this case, 4 FFs].

This is because the intermediate results between in1 and out1 were stored in reg1, reg2, and
reg3 in a nonblocking format. As a result, the evaluation of the result to each individual reg
required waiting for all the events of the RHS to be completed. In this case, it was the output
of the previous register controlled by the clk event. As a result, the output is a shift register.
Using blocking statements in a combinational logic
The following example illustrates the use of blocking statements in combinational logic:

In the above example, the blocking assignments are made in a combinational block. Note the
absence of posedge and “<=”, being replaced with “=”, in the assignments. The logic
synthesized out of this is a simple wire between in1 to out1.

28
 VERILOG INTERVIEW QUESTIONS

This is because all the assignments have been immediate, and there is no event to wait upon.
4. What are some reusable coding practices for RTL Design?
A reusable design mainly helps in reducing the design time of larger implementations using
IPs.
 Register all the outputs of crucial design blocks. This will make the timing interface
easy during system level integration.
 If an IP is being developed in both Verilog and VHDL, try to use the constructs that
will be translatable later into VHDL.
 Partition the design considering the clock domains and the functional goals.
 Avoid instantiation of technology specific gates.
 Use parameters instead of hard-coded values in the design.
 Avoid clocks and resets that are generated internal to the design.
 Avoid glue logic during top level inter-module instantiations.
5. Can the generate construct be nested?
 No. The generate construct cannot be nested. It is a syntax error to try to nest the
generate-endgenerate construct.
 However, the if, case, and for constructs within the generate endgenerate can be nested.
The constructs can also be used within one another, too, that is, if within case, for within
if etc.
 You can also use multiple non-nested generate-endgenerate constructs within the
module.
6. Why is one-hot encoding preferred for FSMs designed for high-speed designs?
Since there is one explicit FF per stage of a one-hot encoded state machine, there is no need
of output state decoding. Hence, the only anticipated delay is the clock to q delay of the FF.
This makes the one-hot encoding mechanism preferable for high-speed operation.
7. Discuss the main differences between $strobe and $monitor.
The differences between $strobe and $monitor are summarized in the following points:
 $strobe can be used to create new simulation events, simply by encapsulating the
$strobe system call within a simulation construct that moves simulation time, such as
@(posedge clock), @(negedge clock),@(any_signal) etc.There can exist multiple
$strobe system calls at the same time, with identical or different arguments.

29
 VERILOG INTERVIEW QUESTIONS

 $monitor stands alone. A given set of arguments of $monitor form their own unique
sensitivity list. Only one $monitor call can be active at any time. Each call to $monitor
replaces any previous call(s) to $monitor.
8. How can I selectively enable or disable monitoring?
$monitor can be selectively enabled or disabled by the $monitoron and the $monitoroff system
calls, respectively. The $monitoron and $monitoroff system calls affect only the most recent
call to $monitor.

30
 VERILOG INTERVIEW QUESTIONS

Following is the Verilog code for flip-flop with a positive-edge clock.

module flop (clk, d, q);
input clk, d;
output q;
reg q;

always @(posedge clk)

begin
q <= d;
end
endmodule

Following is Verilog code for a flip-flop with a negative-edge clock and

asynchronous clear.
module flop (clk, d, clr, q);
input clk, d, clr;
output q;
reg q;
always @(negedge clk or posedge clr)
begin
if (clr)
q <= 1’b0;
else
q <= d;
end
endmodule

Following is Verilog code for the flip-flop with a positive-edge clock and
synchronous set.
module flop (clk, d, s, q);
input clk, d, s;
output q;
reg q;
always @(posedge clk)
begin
if (s)
q <= 1’b1;
else
q <= d;
end
endmodule

Following is Verilog code for the flip-flop with a positive-edge clock and clock
enable.
module flop (clk, d, ce, q);
input clk, d, ce;
output q;
reg q;
always @(posedge clk)
begin
if (ce)
q <= d;
end
endmodule

31
 VERILOG INTERVIEW QUESTIONS

Following is Verilog code for a 4-bit register with a positive-edge clock,

asynchronous set and clock enable.
module flop (clk, d, ce, pre, q);
input clk, ce, pre;
input [3:0] d;
output [3:0] q;
reg [3:0] q;
always @(posedge clk or posedge pre)
begin
if (pre)
q <= 4’b1111;
else if (ce)
q <= d;
end
endmodule

Following is the Verilog code for a latch with a positive gate.

module latch (g, d, q);
input g, d;
output q;
reg q;
always @(g or d)
begin
if (g)
q <= d;
end
endmodule

Following is the Verilog code for a latch with a positive gate and an
asynchronous clear.
module latch (g, d, clr, q);
input g, d, clr;
output q;
reg q;
always @(g or d or clr)
begin
if (clr)
q <= 1’b0;
else if (g)
q <= d;
end
endmodule

Following is Verilog code for a 4-bit latch with an inverted gate and an
asynchronous preset.
module latch (g, d, pre, q);
input g, pre;
input [3:0] d;
output [3:0] q;
reg [3:0] q;
always @(g or d or pre)
begin
if (pre)
q <= 4’b1111;
else if (~g)
q <= d;
end endmodule

32
 VERILOG INTERVIEW QUESTIONS

Following is Verilog code for a tristate element using a combinatorial process

and always block.
module three_st (t, i, o);
input t, i;
output o;
reg o;
always @(t or i)
begin
if (~t)
o = i;
else
o = 1’bZ;
end
endmodule

Following is the Verilog code for a tristate element using a concurrent

assignment.
module three_st (t, i, o);
input t, i;
output o;
assign o = (~t) ? i: 1’bZ;
endmodule

Following is the Verilog code for a 4-bit unsigned up counter with

asynchronous clear.
module counter (clk, clr, q);
input clk, clr;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4’b0000;
else
tmp <= tmp + 1’b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned down counter with
synchronous set.
module counter (clk, s, q);
input clk, s;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk)
begin
if (s)
tmp <= 4’b1111;
else
tmp <= tmp - 1’b1;
end
assign q = tmp;
endmodule

33
 VERILOG INTERVIEW QUESTIONS

Following is the Verilog code for a 4-bit unsigned up counter with an

asynchronous load from the primary input.
module counter (clk, load, d, q);
input clk, load;
input [3:0] d;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge load)
begin
if (load)
tmp <= d;
else
tmp <= tmp + 1’b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned up counter with a

synchronous load with a constant.
module counter (clk, sload, q);
input clk, sload;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk)
begin
if (sload)
tmp <= 4’b1010;
else
tmp <= tmp + 1’b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned up counter with an

asynchronous clear and a clock enable.
module counter (clk, clr, ce, q);
input clk, clr, ce;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4’b0000;
else if (ce)
tmp <= tmp + 1’b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned up/down counter with an
asynchronous clear.
module counter (clk, clr, up_down, q);
input clk, clr, up_down;
output [3:0] q;

34
 VERILOG INTERVIEW QUESTIONS

reg [3:0] tmp;

always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4’b0000;
else if (up_down)
tmp <= tmp + 1’b1;
else
tmp <= tmp - 1’b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit signed up counter with an

asynchronous reset.
module counter (clk, clr, q);
input clk, clr;
output signed [3:0] q;
reg signed [3:0] tmp;
always @ (posedge clk or posedge clr)
begin
if (clr)
tmp <= 4’b0000;
else
tmp <= tmp + 1’b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit signed up counter with an

asynchronous reset and a modulo maximum.
module counter (clk, clr, q);
parameter MAX_SQRT = 4, MAX = (MAX_SQRT*MAX_SQRT);
input clk, clr;
output [MAX_SQRT-1:0] q;
reg [MAX_SQRT-1:0] cnt;
always @ (posedge clk or posedge clr)
begin
if (clr)
cnt <= 0;
else
cnt <= (cnt + 1) %MAX;
end
assign q = cnt;
endmodule

Following is the Verilog code for a 4-bit unsigned up accumulator with an

asynchronous clear.
module accum (clk, clr, d, q);
input clk, clr;
input [3:0] d;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4’b0000;
else
tmp <= tmp + d;

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 VERILOG INTERVIEW QUESTIONS

end
assign q = tmp;
endmodule

Following is the Verilog code for an 8-bit shift-left register with a positive-
edge clock, serial in and serial out.
module shift (clk, si, so);
input clk,si;
output so;
reg [7:0] tmp;
always @(posedge clk)
begin
tmp <= tmp << 1;
tmp[0] <= si;
end
assign so = tmp[7];
endmodule

Following is the Verilog code for an 8-bit shift-left register with a negative-
edge clock, a clock enable, a serial in and a serial out.
module shift (clk, ce, si, so);
input clk, si, ce;
output so;
reg [7:0] tmp;
always @(negedge clk)
begin
if (ce) begin
tmp <= tmp << 1;
tmp[0] <= si;
end
end
assign so = tmp[7];
endmodule

Following is the Verilog code for an 8-bit shift-left register with a positive-
edge clock, asynchronous clear, serial in and serial out.
module shift (clk, clr, si, so);
input clk, si, clr;
output so;
reg [7:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 8’b00000000;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule

Following is the Verilog code for an 8-bit shift-left register with a positive-
edge clock, a synchronous set, a serial in and a serial out.
module shift (clk, s, si, so);
input clk, si, s;
output so;
reg [7:0] tmp;
always @(posedge clk)
begin

36
 VERILOG INTERVIEW QUESTIONS

if (s)
tmp <= 8’b11111111;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule

Following is the Verilog code for an 8-bit shift-left register with a positive-
edge clock, a serial in and a parallel out.
module shift (clk, si, po);
input clk, si;
output [7:0] po;
reg [7:0] tmp;
always @(posedge clk)
begin
tmp <= {tmp[6:0], si};
end
assign po = tmp;
endmodule

Following is the Verilog code for an 8-bit shift-left register with a positive-
edge clock, an asynchronous parallel load, a serial in and a serial out.
module shift (clk, load, si, d, so);
input clk, si, load;
input [7:0] d;
output so;
reg [7:0] tmp;
always @(posedge clk or posedge load)
begin
if (load)
tmp <= d;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule

Following is the Verilog code for an 8-bit shift-left register with a positive-
edge clock, a synchronous parallel load, a serial in and a serial out.
module shift (clk, sload, si, d, so);
input clk, si, sload;
input [7:0] d;
output so;
reg [7:0] tmp;
always @(posedge clk)
begin
if (sload)
tmp <= d;
else
tmp <= {tmp[6:0], si};
end
assign so = tmp[7];
endmodule

37
 VERILOG INTERVIEW QUESTIONS

Following is the Verilog code for an 8-bit shift-left/shift-right register with a

positive-edge clock, a serial in and a serial out.
module shift (clk, si, left_right, po);
input clk, si, left_right;
output po;
reg [7:0] tmp;
always @(posedge clk)
begin
if (left_right == 1’b0)
tmp <= {tmp[6:0], si};
else
tmp <= {si, tmp[7:1]};
end
assign po = tmp;
endmodule

Following is the Verilog code for a 4-to-1 1-bit MUX using an If statement.
module mux (a, b, c, d, s, o);
input a,b,c,d;
input [1:0] s;
output o;
reg o;
always @(a or b or c or d or s)
begin
if (s == 2’b00)
o = a;
else if (s == 2’b01)
o = b;
else if (s == 2’b10)
o = c;
else
o = d;
end
endmodule

Following is the Verilog Code for a 4-to-1 1-bit MUX using a Case statement.
module mux (a, b, c, d, s, o);
input a, b, c, d;
input [1:0] s;
output o;
reg o;
always @(a or b or c or d or s)
begin
case (s)
2’b00 : o = a;
2’b01 : o = b;
2’b10 : o = c;
default : o = d;
endcase
end
endmodule

Following is the Verilog code for a 3-to-1 1-bit MUX with a 1-bit latch.
module mux (a, b, c, d, s, o);
input a, b, c, d;

38
 VERILOG INTERVIEW QUESTIONS

input [1:0] s;
output o;
reg o;
always @(a or b or c or d or s)
begin
if (s == 2’b00)
o = a;
else if (s == 2’b01)
o = b;
else if (s == 2’b10)
o = c;
end
endmodule

Following is the Verilog code for a 1-of-8 decoder.

module mux (sel, res);
input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel or res)
begin
case (sel)
3’b000 : res = 8’b00000001;
3’b001 : res = 8’b00000010;
3’b010 : res = 8’b00000100;
3’b011 : res = 8’b00001000;
3’b100 : res = 8’b00010000;
3’b101 : res = 8’b00100000;
3’b110 : res = 8’b01000000;
default : res = 8’b10000000;
endcase
end
endmodule

Following Verilog code leads to the inference of a 1-of-8 decoder.

module mux (sel, res);
input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel or res) begin
case (sel)
3’b000 : res = 8’b00000001;
3’b001 : res = 8’b00000010;
3’b010 : res = 8’b00000100;
3’b011 : res = 8’b00001000;
3’b100 : res = 8’b00010000;
3’b101 : res = 8’b00100000;
// 110 and 111 selector values are unused
default : res = 8’bxxxxxxxx;
endcase
end
endmodule

Following is the Verilog code for a 3-bit 1-of-9 Priority Encoder.

module priority (sel, code);
input [7:0] sel;
output [2:0] code;
reg [2:0] code;
always @(sel)
begin

39
 VERILOG INTERVIEW QUESTIONS

if (sel[0])
code = 3’b000;
else if (sel[1])
code = 3’b001;
else if (sel[2])
code = 3’b010;
else if (sel[3])
code = 3’b011;
else if (sel[4])
code = 3’b100;
else if (sel[5])
code = 3’b101;
else if (sel[6])
code = 3’b110;
else if (sel[7])
code = 3’b111;
else
code = 3’bxxx;
end
endmodule

Following is the Verilog code for a logical shifter.

module lshift (di, sel, so);
input [7:0] di;
input [1:0] sel;
output [7:0] so;
reg [7:0] so;
always @(di or sel)
begin
case (sel)
2’b00 : so = di;
2’b01 : so = di << 1;
2’b10 : so = di << 2;
default : so = di << 3;
endcase
end
endmodule

Following is the Verilog code for an unsigned 8-bit adder with carry in.
module adder(a, b, ci, sum);
input [7:0] a;
input [7:0] b;
input ci;
output [7:0] sum;

assign sum = a + b + ci;

endmodule

Following is the Verilog code for an unsigned 8-bit adder with carry out.
module adder(a, b, sum, co);
input [7:0] a;
input [7:0] b;
output [7:0] sum;
output co;
wire [8:0] tmp;

assign tmp = a + b;
assign sum = tmp [7:0];
assign co = tmp [8];

40
 VERILOG INTERVIEW QUESTIONS

endmodule
Following is the Verilog code for an unsigned 8-bit adder with carry in and
carry out.
module adder(a, b, ci, sum, co);
input ci;
input [7:0] a;
input [7:0] b;
output [7:0] sum;
output co;
wire [8:0] tmp;

assign tmp = a + b + ci;

assign sum = tmp [7:0];
assign co = tmp [8];

endmodule

Following is the Verilog code for an unsigned 8-bit adder/subtractor.

module addsub(a, b, oper, res);
input oper;
input [7:0] a;
input [7:0] b;
output [7:0] res;
reg [7:0] res;
always @(a or b or oper)
begin
if (oper == 1’b0)
res = a + b;
else
res = a - b;
end
endmodule

Following is the Verilog code for an unsigned 8-bit greater or equal

comparator.
module compar(a, b, cmp);
input [7:0] a;
input [7:0] b;
output cmp;

assign cmp = (a >= b) ? 1’b1 : 1’b0;

endmodule

Following is the Verilog code for an unsigned 8x4-bit multiplier.

module compar(a, b, res);
input [7:0] a;
input [3:0] b;
output [11:0] res;

assign res = a * b;

endmodule

41
 VERILOG INTERVIEW QUESTIONS

Following Verilog template shows the multiplication operation placed outside

the always block and the pipeline stages represented as single registers.
module mult(clk, a, b, mult);
input clk;
input [17:0] a;
input [17:0] b;
output [35:0] mult;
reg [35:0] mult;
reg [17:0] a_in, b_in;
wire [35:0] mult_res;
reg [35:0] pipe_1, pipe_2, pipe_3;

assign mult_res = a_in * b_in;

always @(posedge clk)

begin
a_in <= a;
b_in <= b;
pipe_1 <= mult_res;
pipe_2 <= pipe_1;
pipe_3 <= pipe_2;
mult <= pipe_3;
end
endmodule

Following Verilog template shows the multiplication operation placed inside

the always block and the pipeline stages are represented as single registers.
module mult(clk, a, b, mult);
input clk;
input [17:0] a;
input [17:0] b;
output [35:0] mult;
reg [35:0] mult;
reg [17:0] a_in, b_in;
reg [35:0] mult_res;
reg [35:0] pipe_2, pipe_3;
always @(posedge clk)
begin
a_in <= a;
b_in <= b;
mult_res <= a_in * b_in;
pipe_2 <= mult_res;
pipe_3 <= pipe_2;
mult <= pipe_3;
end
endmodule

Following Verilog template shows the multiplication operation placed outside

the always block and the pipeline stages represented as single registers.
module mult(clk, a, b, mult);
input clk;
input [17:0] a;
input [17:0] b;
output [35:0] mult;
reg [35:0] mult;
reg [17:0] a_in, b_in;
wire [35:0] mult_res;

42
 VERILOG INTERVIEW QUESTIONS

reg [35:0] pipe_1, pipe_2, pipe_3;

assign mult_res = a_in * b_in;

always @(posedge clk)

begin
a_in <= a;
b_in <= b;
pipe_1 <= mult_res;
pipe_2 <= pipe_1;
pipe_3 <= pipe_2;
mult <= pipe_3;
end
endmodule

Following Verilog template shows the multiplication operation placed inside

the always block and the pipeline stages are represented as single registers.
module mult(clk, a, b, mult);
input clk;
input [17:0] a;
input [17:0] b;
output [35:0] mult;
reg [35:0] mult;
reg [17:0] a_in, b_in;
reg [35:0] mult_res;
reg [35:0] pipe_2, pipe_3;
always @(posedge clk)
begin
a_in <= a;
b_in <= b;
mult_res <= a_in * b_in;
pipe_2 <= mult_res;
pipe_3 <= pipe_2;
mult <= pipe_3;
end
endmodule

Following Verilog template shows the multiplication operation placed outside

the always block and the pipeline stages represented as shift registers.
module mult3(clk, a, b, mult);
input clk;
input [17:0] a;
input [17:0] b;
output [35:0] mult;
reg [35:0] mult;
reg [17:0] a_in, b_in;
wire [35:0] mult_res;
reg [35:0] pipe_regs [3:0];

assign mult_res = a_in * b_in;

always @(posedge clk)

begin
a_in <= a;
b_in <= b;
{pipe_regs[3],pipe_regs[2],pipe_regs[1],pipe_regs[0]} <=
{mult, pipe_regs[3],pipe_regs[2],pipe_regs[1]};
end
endmodule

43
 VERILOG INTERVIEW QUESTIONS

Following templates to implement Multiplier Adder with 2 Register Levels on

Multiplier Inputs in Verilog.
module mvl_multaddsub1(clk, a, b, c, res);
input clk;
input [07:0] a;
input [07:0] b;
input [07:0] c;
output [15:0] res;
reg [07:0] a_reg1, a_reg2, b_reg1, b_reg2;
wire [15:0] multaddsub;
always @(posedge clk)
begin
a_reg1 <= a;
a_reg2 <= a_reg1;
b_reg1 <= b;
b_reg2 <= b_reg1;
end
assign multaddsub = a_reg2 * b_reg2 + c;
assign res = multaddsub;
endmodule

Following is the Verilog code for resource sharing.

module addsub(a, b, c, oper, res);
input oper;
input [7:0] a;
input [7:0] b;
input [7:0] c;
output [7:0] res;
reg [7:0] res;
always @(a or b or c or oper)
begin
if (oper == 1’b0)
res = a + b;
else
res = a - c;
end
endmodule

Following templates show a single-port RAM in read-first mode.

module raminfr (clk, en, we, addr, di, do);
input clk;
input we;
input en;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg [3:0] RAM [31:0];
reg [3:0] do;
always @(posedge clk)
begin
if (en) begin
if (we)
RAM[addr] <= di;

do <= RAM[addr];
end

44
 VERILOG INTERVIEW QUESTIONS

end
endmodule
Following templates show a single-port RAM in write-first mode.
module raminfr (clk, we, en, addr, di, do);
input clk;
input we;
input en;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg [3:0] RAM [31:0];
reg [4:0] read_addr;
always @(posedge clk)
begin
if (en) begin
if (we)
RAM[addr] <= di;
read_addr <= addr;
end
end
assign do = RAM[read_addr];
endmodule

Following templates show a single-port RAM in no-change mode.

module raminfr (clk, we, en, addr, di, do);
input clk;
input we;
input en;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg [3:0] RAM [31:0];
reg [3:0] do;
always @(posedge clk)
begin
if (en) begin
if (we)
RAM[addr] <= di;
else
do <= RAM[addr];
end
end
endmodule

Following is the Verilog code for a single-port RAM with asynchronous read.
module raminfr (clk, we, a, di, do);
input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign do = ram[a];
endmodule

45
 VERILOG INTERVIEW QUESTIONS

Following is the Verilog code for a single-port RAM with "false" synchronous
read.
module raminfr (clk, we, a, di, do);
input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [3:0] do;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
do <= ram[a];
end
endmodule

Following is the Verilog code for a single-port RAM with synchronous read
(read through).
module raminfr (clk, we, a, di, do);
input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [4:0] read_a;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
read_a <= a;
end
assign do = ram[read_a];
endmodule

Following is the Verilog code for a single-port block RAM with enable.
module raminfr (clk, en, we, a, di, do);
input clk;
input en;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [4:0] read_a;
always @(posedge clk)
begin
if (en) begin
if (we)
ram[a] <= di;
read_a <= a;
end
end
assign do = ram[read_a];
endmodule

46
 VERILOG INTERVIEW QUESTIONS

Following is the Verilog code for a dual-port RAM with asynchronous read.
module raminfr (clk, we, a, dpra, di, spo, dpo);
input clk;
input we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg [3:0] ram [31:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign spo = ram[a];
assign dpo = ram[dpra];
endmodule

Following is the Verilog code for a dual-port RAM with false synchronous
read.
module raminfr (clk, we, a, dpra, di, spo, dpo);
input clk;
input we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg [3:0] ram [31:0];
reg [3:0] spo;
reg [3:0] dpo;
always @(posedge clk)
begin
if (we)
ram[a] <= di;

spo = ram[a];
dpo = ram[dpra];
end
endmodule

Following is the Verilog code for a dual-port RAM with synchronous read
(read through).
module raminfr (clk, we, a, dpra, di, spo, dpo);
input clk;
input we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg [3:0] ram [31:0];
reg [4:0] read_a;
reg [4:0] read_dpra;
always @(posedge clk)
begin
if (we)

47
 VERILOG INTERVIEW QUESTIONS

ram[a] <= di;

read_a <= a;
read_dpra <= dpra;
end
assign spo = ram[read_a];
assign dpo = ram[read_dpra];
endmodule

Following is the Verilog code for a dual-port RAM with enable on each port.
module raminfr (clk, ena, enb, wea, addra, addrb, dia, doa, dob);
input clk, ena, enb, wea;
input [4:0] addra, addrb;
input [3:0] dia;
output [3:0] doa, dob;
reg [3:0] ram [31:0];
reg [4:0] read_addra, read_addrb;
always @(posedge clk)
begin
if (ena) begin
if (wea) begin
ram[addra] <= dia;
end
end
end

always @(posedge clk)

begin
if (enb) begin
read_addrb <= addrb;
end
end
assign doa = ram[read_addra];
assign dob = ram[read_addrb];
endmodule

Following is Verilog code for a ROM with registered output.

module rominfr (clk, en, addr, data);
input clk;
input en;
input [4:0] addr;
output reg [3:0] data;
always @(posedge clk)
begin
if (en)
case(addr)
4’b0000: data <= 4’b0010;
4’b0001: data <= 4’b0010;
4’b0010: data <= 4’b1110;
4’b0011: data <= 4’b0010;
4’b0100: data <= 4’b0100;
4’b0101: data <= 4’b1010;
4’b0110: data <= 4’b1100;
4’b0111: data <= 4’b0000;
4’b1000: data <= 4’b1010;
4’b1001: data <= 4’b0010;
4’b1010: data <= 4’b1110;
4’b1011: data <= 4’b0010;
4’b1100: data <= 4’b0100;
4’b1101: data <= 4’b1010;
4’b1110: data <= 4’b1100;

48
 VERILOG INTERVIEW QUESTIONS

4’b1111: data <= 4’b0000;

default: data <= 4’bXXXX;
endcase
end
endmodule

Following is Verilog code for a ROM with registered address.

module rominfr (clk, en, addr, data);
input clk;
input en;
input [4:0] addr;
output reg [3:0] data;
reg [4:0] raddr;
always @(posedge clk)
begin
if (en)
raddr <= addr;
end

always @(raddr)
begin
if (en)
case(raddr)
4’b0000: data = 4’b0010;
4’b0001: data = 4’b0010;
4’b0010: data = 4’b1110;
4’b0011: data = 4’b0010;
4’b0100: data = 4’b0100;
4’b0101: data = 4’b1010;
4’b0110: data = 4’b1100;
4’b0111: data = 4’b0000;
4’b1000: data = 4’b1010;
4’b1001: data = 4’b0010;
4’b1010: data = 4’b1110;
4’b1011: data = 4’b0010;
4’b1100: data = 4’b0100;
4’b1101: data = 4’b1010;
4’b1110: data = 4’b1100;
4’b1111: data = 4’b0000;
default: data = 4’bXXXX;
endcase
end
endmodule

Following is the Verilog code for an FSM with a single process.

module fsm (clk, reset, x1, outp);
input clk, reset, x1;
output outp;
reg outp;
reg [1:0] state;
parameter s1 = 2’b00; parameter s2 = 2’b01;
parameter s3 = 2’b10; parameter s4 = 2’b11;
always @(posedge clk or posedge reset)
begin
if (reset) begin
state <= s1; outp <= 1’b1;
end
else begin
case (state)
s1: begin

49
 VERILOG INTERVIEW QUESTIONS

if (x1 == 1’b1) begin

state <= s2;
outp <= 1’b1;
end
else begin
state <= s3;
outp <= 1’b1;
end
end
s2: begin
state <= s4;
outp <= 1’b0;
end
s3: begin
state <= s4;
outp <= 1’b0;
end
s4: begin
state <= s1;
outp <= 1’b1;
end
endcase
end
end
endmodule

Following is the Verilog code for an FSM with two processes.

module fsm (clk, reset, x1, outp);
input clk, reset, x1;
output outp;
reg outp;
reg [1:0] state;
parameter s1 = 2’b00; parameter s2 = 2’b01;
parameter s3 = 2’b10; parameter s4 = 2’b11;
always @(posedge clk or posedge reset)
begin
if (reset)
state <= s1;
else begin
case (state)
s1: if (x1 == 1’b1)
state <= s2;
else
state <= s3;
s2: state <= s4;
s3: state <= s4;
s4: state <= s1;
endcase
end
end
always @(state) begin
case (state)
s1: outp = 1’b1;
s2: outp = 1’b1;
s3: outp = 1’b0;
s4: outp = 1’b0;
endcase
end
endmodule

50
 VERILOG INTERVIEW QUESTIONS

Following is the Verilog code for an FSM with three processes.

module fsm (clk, reset, x1, outp);
input clk, reset, x1;
output outp;
reg outp;
reg [1:0] state;
reg [1:0] next_state;
parameter s1 = 2’b00; parameter s2 = 2’b01;
parameter s3 = 2’b10; parameter s4 = 2’b11;
always @(posedge clk or posedge reset)
begin
if (reset)
state <= s1;
else
state <= next_state;
end

always @(state or x1)

begin
case (state)
s1: if (x1 == 1’b1)
next_state = s2;
else
next_state = s3;
s2: next_state = s4;
s3: next_state = s4;
s4: next_state = s1;
endcase
end

51
 VERILOG INTERVIEW QUESTIONS

1.What value is inferred when multiple procedural assignments made to the same reg
variable in an always block ?
When multiple procedural assignments are made to the same reg (register) variable within the
same always block in a hardware description language like Verilog or VHDL, the last
assignment made in that block will take precedence. In other words, the value assigned to the
register variable in the last procedural assignment statement will be inferred as the final value
of that register.

2.How do you pass arguments to task in Verilog ?

In Verilog, you can pass arguments to a task using the task declaration and call the task with
appropriate arguments when needed. Here’s a basic example of how to pass arguments to a
task:
Declare a task with input and output arguments:
task my_task(input [7:0] arg1, output reg [7:0] result);
// Task code here
result = arg1 + 1;
endtask
endmodule
In this example, we have a module called test that calls the my_task task with the input_data
argument and stores the result in the output_result variable. Finally, it displays the result.
When you run the simulation, it will execute the task with the provided arguments, and you
can use the task’s output in your Verilog design.

3.Can a Function Modify Input Argument ?

No, in Verilog, functions cannot modify input arguments. Verilog functions are strictly
designed to be "pure" functions, meaning they take input arguments and return a value based
on those inputs without altering the input arguments themselves. This is a fundamental
characteristic of Verilog functions.
If you need to modify input data or variables within your Verilog code, you should use tasks
instead. Tasks in Verilog can have input and output arguments, and they can modify the values
of output arguments or other variables within their scope. Unlike functions, tasks are intended
for procedures that involve procedural assignments and modifications to variables.
 VERILOG INTERVIEW QUESTIONS

4.What are the difference between Module and Task in Reusable logic ?
In Verilog, both tasks and modules are used to encapsulate and create reusable logic. However,
they serve different purposes and have distinct characteristics:
1. Modules:
 Modules are used to define reusable hardware components.
 Modules describe the behaviour and structure of a part of your design.
 Modules can have input and output ports, internal logic (combinational and sequential),
and hierarchical instances.
 Modules are instantiated multiple times in your design hierarchy to create instances of
the hardware component.
 Modules are intended for structural representation and instantiation.
2. Tasks:
 Tasks are used to define reusable procedural blocks of code.
 Tasks do not have ports like modules; instead, they have input and output arguments.
 Tasks are called with arguments and execute a sequence of procedural statements.
 Tasks are useful for encapsulating sequences of operations or algorithms that need to
be reused in different parts of your design.
 Tasks are intended for behavioural representation.
In summary, modules are used to represent reusable hardware components with structural and
hierarchical characteristics, while tasks are used to encapsulate and reuse procedural blocks of
code with behavioural characteristics. Depending on your design needs, you can use both
modules and tasks to create efficient and maintainable Verilog code.

5.Can Task and Function declared externally ?

In Verilog, tasks and functions are typically declared and defined within modules or blocks of
code. They are local to the module or block in which they are declared and cannot be declared
externally or globally like modules or variables.
Tasks and functions have a limited scope and are meant to be used within a specific module or
design block to encapsulate and reuse specific pieces of logic or procedures.
In Summary Task and Function are declared and defined within the module and are accessible
only within that module. They cannot be declared externally or globally in the Verilog code.
6.Can Task return a Value ?
No, tasks in Verilog cannot return a value directly like functions. Tasks are designed for
performing a sequence of procedural operations and can have input and output arguments, but
they do not return values in the same way functions do.
If you need a Verilog construct that returns a value, you should use a function. Functions in
Verilog are specifically intended for this purpose. They take input arguments and return a single
value based on those inputs.
VERILOG INTERVIEW QUESTIONS
 VERILOG INTERVIEW QUESTIONS

1.How to Convert Binary to Seven Segment

A seven-segment display (SSD) is a form of electronic display device for displaying
decimal numbers. They can be used as an alternative to complex display's such as dot matrix.

An SSD has 7 segments and theoretically we can use it to display 2^7 = 128 combinations of
characters. But most of these combinations, does not make sense to a human eye. Decimal
numbers can be displayed correctly on a 7-segment panel as shown below:

The image on the right indicates the order in which the panels are accessed normally. This is
done using a 7-bit vector.

Here, I have written a Verilog code which takes in a BCD number and converts it into a 6-bit
vector format, which the seven-segment panel understands. Note that, to light up an individual
panel, we must switch it OFF(pass '0' through it).

Seven segment display Code:

//Verilog module.
module segment7(
bcd,
seg
);

//Declare inputs,outputs and internal variables.

input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;

//always block for converting bcd digit into 7 segment format

always @(bcd)
begin
case (bcd) //case statement
0 : seg = 7'b0000001;
1 : seg = 7'b1001111;
2 : seg = 7'b0010010;
3 : seg = 7'b0000110;
 VERILOG INTERVIEW QUESTIONS

4 : seg = 7'b1001100;
5 : seg = 7'b0100100;
6 : seg = 7'b0100000;
7 : seg = 7'b0001111;
8 : seg = 7'b0000000;
9 : seg = 7'b0000100;
//switch off 7 segment character when the bcd digit is not a decimal number.
default : seg = 7'b1111111;
endcase
end

endmodule

Testbench:

module tb_segment7;

reg [3:0] bcd;

wire [6:0] seg;
integer i;

// Instantiate the Unit Under Test (UUT)

segment7 uut (
.bcd(bcd),
.seg(seg)
);

//Apply inputs
initial begin
for(i = 0;i < 16;i = i+1) //run loop for 0 to 15.
begin
bcd = i;
#10; //wait for 10 ns
end
end

endmodule

2.Write a code to generate random Number in Verilog

Verilog has a system call ($random) that handles this. It returns a signed 32-bit integer. It is
used as follows:
module rand();
integer mynumber;

initial begin
mynumber = $random;
end
endmodule
 VERILOG INTERVIEW QUESTIONS

If random numbers in a certain range are required, this can be achieved with the following
code:

module rand();
integer mynumber;

initial begin
mynumber = {$random} %10 ; // random numbers between 0 and 9.
end
endmodule

Verilog Clock Generator

Simulations are required to operate on a given timescale that has a limited precision as specified
by the timescale directive. Hence it is important that the precision of timescale is good enough
to represent a clock period. For example, if the frequency of the clock is set to 640000 kHz,
then its clock period will be 1.5625 ns for which a timescale precision of 1ps will not suffice
because there is an extra point to be represented. Hence simulation will round off the last digit
to fit into the 3 point timescale precision. This will bump up the clock period to 1.563 which
actually represents 639795 kHz !

The following Verilog clock generator module has three parameters to tweak the three different
properties as discussed above. The module has an input enable that allows the clock to be
disabled and enabled as required. When multiple clocks are controlled by a
common enable signal, they can be relatively phased easily.

`timescale 1ns/1ps

module clock_gen ( input enable,

output reg clk);

parameter FREQ = 100000; // in kHZ

parameter PHASE = 0; // in degrees
parameter DUTY = 50; // in percentage

real clk_pd = 1.0/(FREQ * 1e3) * 1e9; // convert to ns

real clk_on = DUTY/100.0 * clk_pd;
real clk_off = (100.0 - DUTY)/100.0 * clk_pd;
real quarter = clk_pd/4;
real start_dly = quarter * PHASE/90;

reg start_clk;

initial begin
$display("FREQ = %0d kHz", FREQ);
$display("PHASE = %0d deg", PHASE);
$display("DUTY = %0d %%", DUTY);
 VERILOG INTERVIEW QUESTIONS

$display("PERIOD = %0.3f ns", clk_pd);

$display("CLK_ON = %0.3f ns", clk_on);
$display("CLK_OFF = %0.3f ns", clk_off);
$display("QUARTER = %0.3f ns", quarter);
$display("START_DLY = %0.3f ns", start_dly);
end

// Initialize variables to zero

initial begin
clk <= 0;
start_clk <= 0;
end

// When clock is enabled, delay driving the clock to one in order

// to achieve the phase effect. start_dly is configured to the
// correct delay for the configured phase. When enable is 0,
// allow enough time to complete the current clock period
always @ (posedge enable or negedge enable) begin
if (enable) begin
#(start_dly) start_clk = 1;
end else begin
#(start_dly) start_clk = 0;
end
end

// Achieve duty cycle by a skewed clock on/off time and let this
// run as long as the clocks are turned on.
always @(posedge start_clk) begin
if (start_clk) begin
clk = 1;

while (start_clk) begin

#(clk_on) clk = 0;
#(clk_off) clk = 1;
end

clk = 0;
end
end
endmodule
 VERILOG INTERVIEW QUESTIONS

Sequence Detector 1001 (Moore Machine + Mealy Machine + Overlapping/Non-

Overlapping)

1) Moore Machine (Non-Overlapping)

module sd1001_moore(input bit clk,

input logic reset,
input logic din,
output logic dout);

typedef enum logic [2:0] {S0, S1, S2, S3, S4} state_t;
state_t state;

always @(posedge clk or posedge reset) begin

if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
dout <=1'b0;
if(din)
state <= S1;
end
S1: begin
dout <= 1'b0;
if(~din)
state <= S2;
end
S2: begin
dout <= 1'b0;
 VERILOG INTERVIEW QUESTIONS

if(~din)
state <= S3;
else
state <= S1;
end
S3: begin
dout <= 1'b0;
if(din)
state <= S4;
else
state <= S0;
end
S4: begin
dout <= 1'b1;
if(din)
state <= S1;
else
state <= S0;
end
endcase
end
end

endmodule

2) Mealy Machine (Non-Overlapping)

module sd1001_mealy(input bit clk,

input logic reset,
input logic din,
output logic dout);
 VERILOG INTERVIEW QUESTIONS

typedef enum logic [1:0] {S0, S1, S2, S3} state_t;

state_t state;

always @(posedge clk or posedge reset) begin

if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
if(din) begin
state <= S1;
dout <=1'b0;
end
else
dout <=1'b0;
end
S1: begin
if(~din) begin
state <= S2;
dout <=1'b0;
end
else begin
dout <=1'b0;
end
end
S2: begin
if(~din) begin
state <= S3;
dout <=1'b0;
end
else begin
state <= S1;
dout <=1'b0;
end
end
S3: begin
if(din) begin
state <= S0;
dout <=1'b1;
end
else begin
state <= S0;
dout <=1'b0;
end
end
endcase
end
 VERILOG INTERVIEW QUESTIONS

end

endmodule

3) Moore Machine (Overlapping)

module sd1001_moore_over(input bit clk,

input logic reset,
input logic din,
output logic dout);

typedef enum logic [2:0] {S0, S1, S2, S3, S4} state_t;
state_t state;

always @(posedge clk or posedge reset) begin

if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
dout <=1'b0;
if(din)
state <= S1;
end
S1: begin
dout <= 1'b0;
if(~din)
state <= S2;
end
S2: begin
 VERILOG INTERVIEW QUESTIONS

dout <= 1'b0;

if(~din)
state <= S3;
else
state <= S1;
end
S3: begin
dout <= 1'b0;
if(din)
state <= S4;
else
state <= S0;
end
S4: begin
dout <= 1'b1;
if(din)
state <= S1;
else
state <= S2;
end
endcase
end
end

endmodule

4) Mealy Machine (Overlapping)

module sd1001_mealy_over(input bit clk,

input logic reset,
input logic din,
 VERILOG INTERVIEW QUESTIONS

output logic dout);

typedef enum logic [1:0] {S0, S1, S2, S3} state_t;

state_t state;

always @(posedge clk or posedge reset) begin

if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
if(din) begin
state <= S1;
dout <=1'b0;
end
else
dout <=1'b0;
end
S1: begin
if(~din) begin
state <= S2;
dout <=1'b0;
end
else begin
dout <=1'b0;
end
end
S2: begin
if(~din) begin
state <= S3;
dout <=1'b0;
end
else begin
state <= S1;
dout <=1'b0;
end
end
S3: begin
if(din) begin
state <= S1;
dout <=1'b1;
end
else begin
state <= S0;
dout <=1'b0;
end
end
endcase
 VERILOG INTERVIEW QUESTIONS

end
end

endmodule
Sequence Detector 110 (Moore Machine + Mealy Machine)

1) Moore Machine

module sd110_moore(input bit clk,

input logic reset,
input logic din,
output logic dout);

typedef enum logic [1:0] {S0, S1, S2, S3} state_t;

state_t state;

always @(posedge clk or posedge reset) begin

if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
dout <=1'b0;
if(din)
state <= S1;
end
S1: begin
dout <= 1'b0;
if(din)
 VERILOG INTERVIEW QUESTIONS

state <= S2;

else
state <= S0;
end
S2: begin
dout <= 1'b0;
if(~din)
state <= S3;
end
S3: begin
dout <= 1'b1;
if(din)
state <= S1;
else
state <= S0;
end
endcase
end
end

endmodule

2) Mealy Machine

module sd110_mealy(input bit clk,

input logic reset,
input logic din,
output logic dout);

typedef enum logic [1:0] {S0, S1, S2} state_t;

state_t state;
 VERILOG INTERVIEW QUESTIONS

always @(posedge clk or posedge reset) begin

if(reset) begin
dout <= 1'b0;
state <= S0;
end
else begin
case(state)
S0: begin
if(din) begin
state <= S1;
dout <=1'b0;
end
else
dout <=1'b0;
end
S1: begin
if(din) begin
state <= S2;
dout <=1'b0;
end
else begin
state <= S0;
dout <=1'b0;
end
end
S2: begin
if(~din) begin
state <= S0;
dout <=1'b1;
end
else begin
dout <=1'b0;
end
end
endcase
end
end

endmodule