Converters, Drives and Controls For Sustainable Operations 2023

Power Converters,
Drives and Controls for

Sustainable Operations
Scrivener Publishing
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Beverly, MA 01915-6106
Publishers at Scrivener
Martin Scrivener ([email protected])
Phillip Carmical ([email protected])
Power Converters,
Drives and Controls for
Sustainable Operations
Edited by
S. Ganesh Kumar
Marco Rivera Abarca
and
S. K. Patnaik
This edition first published 2023 by John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, USA
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Library of Congress Cataloging-in-Publication Data
ISBN 9781119791911
Front cover images supplied by WikiMedia Commons

Cover design by Russell Richardson
Set in size of 11pt and Minion Pro by Manila Typesetting Company, Makati, Philippines
Printed in the USA
10 9 8 7 6 5 4 3 2 1
Contents
Preface xxi
Part I: Power Converter Topologies

for Sustainable Applications 1
1 DC-DC Power Converter Topologies
Nandish B. M., Pushparajesh V. and Marulasiddappa H. B.
1.1 Introduction 4
1.2 Classifications of DC-DC Converters 4
1.2.1 Classification of Linear Mode DC-DC Converters 5
1.2.1.1 Series Regulators 5
1.2.1.2 Parallel Regulators 6
1.2.2 Classification of Hard Switching DC-DC Converter 6
1.2.2.1 List of Isolated DC-DC Topologies 6
1.2.2.2 Classification of Non-Isolated DC-DC
Converters 10
1.2.3 Classification of Soft Switching DC-DC Converter 16
1.2.3.1 Zero Current Switching (ZCS) 16
1.2.3.2 Zero Voltage Switching (ZVS) 16
1.3 Applications of DC-DC Converters in Real World 16
1.4 Conclusion 18
References 18
2 DC-DC Converters for Fuel Cell Power Sources 21
M. Venkatesh Naik, Paulson Samuel
and Srinivasan Pradabane
2.1 DC-DC Boost Converter in Fuel Cell (FC) Applications 22
2.2 DC-DC Buck Converter 26
2.3 DC-DC Buck-Boost Converter 27
2.4 DC-DC Cuk-Converter 29
v
vi Contents
2.5 DC-DC Sepic Converter 30

2.6 Multi-Phase and Multi-Device Techniques
for Ripple Current Reduction 32
2.6.1 Multi-Device Boost Converter 33
2.6.2 Multi-Phase Interleaved Boost Converter 35
2.6.3 Multi-Device Multi-Phase Interleaved
Boost Converter 37
2.7 The Proposed High Gain Multi-Device Multi-Phase
Interleaved Boost Converter 42
2.7.1 Operating Principle of HGMDMPIBC 44
2.8 Non-Inverting Buck-Boost Converters
for Low Voltage FC Applications 48
2.8.1 Single Switch Non-Inverting Buck-Boost Converter 49
2.8.2 Interleaved Buck-Boost Converter 52
2.9 Proposed Multi-Device Buck-Boost Converter
for Low Voltage FC Applications 57
2.10 The Proposed Multi-Device Multi-Phase Interleaved
Buck-Boost Converter for Low Voltage FC Applications 59
2.11 Converter Configurations for Integrating FC
with 400 V Grid Voltages 62
2.11.1 Series Configuration 62
2.11.2 DC-Distributed Configuration 64
2.12 Conclusions 65
References 66
3 High Gain DC-DC Converters for Photovoltaic Applications 71
M. Prabhakar and B. Sri Revathi
3.1 Introduction 71
3.1.1 Role of DC-DC Converter in Renewable
Energy System 72
3.1.2 Classical Boost Converter (CBC) 75
3.2 Gain Extension Mechanisms 77
3.2.1 Voltage-Lift Capacitor (Clift) 77
3.2.2 Coupled Inductor (CI) 78
3.2.3 Voltage Multiplier Cells (VMC) 79
3.3 Synthesis of High Gain DC-DC Converters 80
3.3.1 Concept of Interleaving 80
3.3.2 Interleaving Mechanism with
Coupled Inductors (CIs) 83
3.3.3 VMCs at Secondary Side of CIs 84
3.4 Development of High Gain DC-DC Converters (HGCs) 84
Contents vii
3.4.1 HGC with 3 CIs, Clift, and VMC 85

3.4.1.1 Design Details of HGC-1 90
3.4.1.2 Experimental Results of Prototype HGC-1
and Discussion 95
3.4.2 3-Phase Interleaved HGC with 1 CI, Clift, and VMC 101
3.4.3 Modular HGC with 3 CIs, Clift, and 3 VMCs 104
3.4.4 Compact HGC Based on Multi-Winding CI, Clift,
and VMC 107
3.4.4.1 Voltage Stress on Devices 109
3.4.4.2 Current Stress on Devices 109
3.5 Operating Capabilities of the Proposed HGCs –
A Comparison 111
3.5.1 Electrical Characteristics 111
3.5.1.1 Ideal Voltage Gain 111
3.5.1.2 Loss Distribution Profile 113
3.5.2 Stress on Switches 115
3.5.2.1 Peak Voltage Stress 116
3.5.2.2 Peak Current Stress 117
3.5.3 Structural Parameters 117
3.5.3.1 Coefficient of Coupling (k) 117
3.5.3.2 Component Count (CC) and Component
Utilisation Ratio (CUR) 118
3.6 Salient Features of the Presented High Gain Converters 119
3.7 Summary and Outlook 120
References 122
4 Design of DC-DC Converters for Electric Vehicle Wireless
Charging Energy Storage System 127
T. Kripalakshmi and T. Deepa
4.1 Introduction 128
4.2 Isolated Converters 130
4.2.1 Bridge Type 130
4.2.2 Z-Source Type 131
4.2.3 Sinusoidal Amplitude High Voltage Bus Converter
(SAHVC) 131
4.2.4 Multiport Converter 133
4.3 Non-Isolated Converter 133
4.3.1 Conventional Converters 133
4.3.2 Interleaved Converter 134
4.3.3 Multi-Device Interleaved 135
viii Contents
4.4 Design of DC-DC Converter with Integration of ICPT

and Battery Implementation with Digital Control Loop 136
4.4.1 Design of DC-DC for BEV
with the Integration of ICPT 136
4.4.2 Digital Control with Sliding Mode Control Approach 139
4.5 Design of Converter with Hybrid Energy Storage
System and Bidirectional Converter 143
4.6 Conclusion 145
References 145
5 Performance Analysis of Series Load Resonant (SLR)
DC–DC Converter 149
A. Mitra, S. Bhowmik, A. Halder, S. Karmakar and T. Paul
5.2 Theoretical Background 151
5.3 Simulation Results 155
5.4 Conclusion 157
References 158
6 Review on Different Methodologies of DC-AC Converter 159
Pushparajesh V., Marulasiddappa H. B. and Nandish B. M.
6.2 Different Multilevel Inverter Topologies 162
6.2.1 Diode Clamped MLI (DCMLI) 162
6.2.2 Flying Capacitor MLI 164
6.2.3 Cascaded H-Bridge MLI 165
6.2.4 New Hybrid Cascaded MLI 167
6.2.4.1 Stepped Wave Modulation Topology
(SWMT) 167
6.2.4.2 Fourier Series of Proposed Waveform 168
6.2.4.3 Proposed Topology (New Hybrid MLI) 169
6.3 Comparison between Various MLI 172
6.4 Conclusion 173
References 173
7 Grid Connected Inverter for Solar Photovoltaic
Power Generation 175
K.K. Saravanan and M. Durairasan
7.1 Single Phase Seven Level Inverter Fed Grid Connected
PV System 176
7.1.1 Seven Level Inverter Topology 176
7.1.2 PWM Technique for Seven Level Inverter 177
Contents ix
7.1.3 Modelling and Simulation Analysis of Seven Level

Inverter 180
7.2 Simlink Model of Nine Level H-Bridge Inverter 181
7.3 Three Phase Fifteen Level Inverter Fed Grid
Connected System 182
7.3.1 Modified System of Fifteen Level Inverter 182
7.3.2 Modelling of Cascaded H-Bridge Fifteen
Level Inverter 183
7.3.3 Evaluation of THD 184
7.4 Fesability Analysis of Photovoltaic System
in Grid Connected Inverter 185
7.4.1 Modified PV-DVR System 185
7.4.1.1 Dynamic Voltage Restorer (DVR) Mode 187
7.4.1.2 Uninterruptable Power Supply (UPS) Mode 187
7.4.1.3 Energy Conservation Mode 187
7.4.1.4 Idle Mode 187
7.4.2 Photovoltaic DC-DC Converter 188
7.4.3 Maximum Power Point Tracking of PV System 191
7.4.4 Methods of Maximum Power Point Tracking 192
7.4.4.1 Perturb and Observe Method 192
7.4.4.2 Incremental Conductance Method 193
7.4.4.3 Current Sweep Method 193
7.4.4.4 Constant Voltage Method 194
7.4.5 Comparison of MPPT Methods 194
7.4.6 Operating Principle of P&O MPPT 195
7.4.7 Simulation Results of PV-DVR System 195
7.4.8 Grid Connected System Using PV Syst Tool 197
7.4.8.1 PV System Simulation Result Analysis 199
7.5 Conclusion 199
7.6 Future Scope of Work 200
References 200
8 A Novel Fusion Switching Pattern Generation Algorithm
for “N-Level” Switching Angle Algorithm Based Trinary
Cascaded Hybrid Multi-Level Inverter 203
Joseph Anthony Prathap and T.S. Anandhi
8.2 Trinary Cascaded Hybrid MLI Circuitry 206
8.3 Switching Angle Algorithm 208
8.3.1 Equal Phase Switching Angle Algorithm (EP-SAA) 209
x Contents
8.3.2 Half Equal Phase Switching Angle Algorithm

(HEP-SAA) 209
8.3.3 Feed Forward Switching Angle Algorithm (FF-SAA) 209
8.3.4 Half Height Switching Angle Algorithm (HH-SAA) 209
8.4 9-Level Trinary Cascaded Hybrid Multi-Level Inverter 210
8.4.1 SAA for 9-Level TCHMLI 210
8.4.2 Generation of Switching Function
for the 9-Level Trinary Cascaded Hybrid MLI 215
8.4.3 Generation of DPWM for the 9-Level Trinary
Cascaded Hybrid MLI 215
8.4.4 Simulation Results of 9-Level Trinary Cascaded
Hybrid MLI 216
8.5 27-Level Trinary Cascaded Hybrid MLI 222
8.5.1 SAA for 27-Level TCHMLI 223
8.5.2 Generation of Switching Function for the 27-Level
Trinary Cascaded Hybrid MLI 225
8.5.3 Generation of DPWM for the 27-Level Trinary
Hybrid MLI 231
8.6 81-Level Trinary Cascaded Hybrid MLI 240
8.6.1 SAA for 81-Level Trinary Cascaded Hybrid MLI 240
8.6.2 Generation of Switching Function
for the 81-Level Trinary Cascaded Hybrid MLI 248
8.6.3 Generation of DPWM for 81-Level Trinary
8.6.4 Flow Diagram of 81-Level Trinary Cascaded
Hybrid MLI 266
8.6.5 5 Roles of Design Resolution in Trinary Cascaded
Hybrid MLI 266
Hybrid MLI 268
8.7 FPGA Experimental Validation with Specification 279
8.8 Hardware Results and Discussion 279
8.9 Conclusion 280
References 290
9 An Inspection on Multilevel Inverters Based
on Sustainable Applications 293
L. Vijayaraja, R. Dhanasekar and S. Ganesh Kumar
Contents xi
9.2 Multilevel Inverters in Sustainable Applications 294

9.3 Development of Multilevel Inverter 299
9.3.1 Diode-Clamped 299
9.3.2 Flying Capacitor 300
9.3.3 Cascaded H-Bridge MLI 301
9.4 Symmetric MLI 301
9.5 Asymmetric MLI 305
9.6 An Examination on Current MLI’s 307
9.7 Summary 311
Acknowledgement 311
References 311
Part II: Electric Machines and Drives

10 Technical Study of Electric Vehicle Charging Infrastructure
and Standards 317
R. Seyezhai and S. Harika
10.2 Background 318
10.3 Review of EV Charging Infrastructure 320
10.4 Review of DC-DC Converters for EVCs 323
10.5 Standards for EV and EVSE 327
10.5.1 Description of EV Connector 330
10.6 Charging Stations in India 331
10.7 Conclusion 332
References 332
11 Implementation of Model Predictive Control for Reduced
Torque Ripple in Orthopaedic Surgical Drilling Applications
with Permanent Magnet Synchronous Machine 337
Ramya L. N. and Sivaprakasam A.
11.2 Role of Motor in Orthopaedic Drilling Applications 341
11.2.1 BLDC Motors 341
11.2.2 Permanent Magnet Synchronous Motors 341
11.2.2.1 PMSM Machine Equations 342
11.2.3 Control Methods of PMSM 343
11.3 Model Predictive Control 347
11.3.1 Structure of MPC 348
11.3.2 Cost Function 349
11.4 Predictive Control Techniques for PMSM 350
xii Contents
11.4.1 Conventional Model Predictive Torque

Control (MPC) 350
11.4.2 Proposed MPC Technique 352
11.5 Implementation and Results 354
11.5.1 Comparative Study of Steady State Performance
of Proposed MPC and Conventional MPC
under Loaded Condition 355
11.5.2 Steady State Performance at 50% Rated Speed 356
11.5.3 Steady State Performance at 100% Rated Speed 357
11.5.4 Real-Time Simulation Result Analysis
with OPAL-RT Lab 357
11.5.4.1 Steady-State Response 358
11.5.4.2 Start-Up Response 359
11.6 Implementation Analysis 359
11.7 Conclusion 362
References 362
12 High Precision Drives for Piezoelectric Actuators
Based Motion Control Microsystems 367
D. V. Sabarianand and P. Karthikeyan
12.2 Driving Methods of PEA 369
12.3 Driver Circuits for Driving PEA in High Voltage
Applications 369
12.4 Different Types of Power Supply Used for Driving
the Piezo Driver 377
12.5 Different Types of Voltage Regulator Used for Driving
the Piezo Driver 380
12.6 Conclusions 385
References 386
13 Design and Analysis of 31-Level Asymmetrical
Multilevel Inverter Topology for R, RL, & Motor Load 391
E. Duraimurugan, R. S. Jeevitha, S. Dillirani, L. Vijayaraja
and S. Ganesh Kumar
13.2 Incorporation of Multilevel Inverters in Various
Applications 392
13.3 Modeling of 31-Level Asymmetric Inverter 394
13.3.1 Mathematical Modeling of 31-Level Inverter 395
13.3.2 Modes of Operation 396
13.3.3 Switching Principle of 31-Level Inverter 398
Contents xiii
13.4 Simulation Circuit and Result Discussions 400

13.4.1 Block Diagram for Pulse Generation 400
13.4.2 Simulation of 31-Level Inverter with R Load 400
13.4.3 Simulation of 31-Level Inverter with RL Load 402
13.4.4 Simulation of 31-Level Inverter Fed with
1φ Induction Motor 405
13.5 Conclusion 407
Acknowledgement 407
References 407
14 Permanent Magnet Assisted Synchronous Reluctance Motor:
Analysis and Design with Rare Earth Free Hybrid Magnets 411
P. Ramesh, D. Pradhap and N. C. Lenin
14.2 Literature Survey 413
14.3 Construction and Torque Equation 415
14.4 Design Specifications and Machine Topologies 417
14.5 No-Load Characteristics 421
14.6 Performance at Various Operating Regions 424
14.7 Conclusion 429
Acknowledgment 433
References 433
15 Design of Bidirectional DC – DC Converters and Controllers
for Hybrid Energy Sources in Electric Vehicles 437
R. Chandrasekaran, M. Satish Kumar Reddy, K. Selvajyothi
and B. Raja
15.2 Need For Hybrid Energy Management Systems in EV 439
15.3 Hybrid Energy Storage System (HESS) 440
15.3.1 Passive Parallel HESS 441
15.3.2 Parallel Converter HESS 441
15.4 Bidirectional DC-DC Converters (BDC) 442
15.5 Specifications of DC-DC Converters 446
15.6 Control Strategy 447
15.7 Results and Discussion 449
15.8 Conclusions 459
References 460
16 Design of Rare Earth Magnet Free Traction Motor 463
Akhila K. and K. Selvajyothi
16.2 Comparison Among Traction Motor Choices 468
xiv Contents
16.3 Motor Peak Power Calculation Based

on Vehicle Dynamics 473
16.4 Operating Principle of SynRM & Basic Terminologies 475
16.5 SynRM Design Concepts: Effect of Design Parameters
on Performance 482
16.6 Analytical Design of SynRM 486
16.6.1 Stator & Winding Design 486
16.6.2 Rotor Design 490
16.6.2.1 Determining Barrier End Angle, αm 491
16.6.2.2 Determining Segment Width, Si 491
16.6.2.3 Determining Barrier Width, W1i 493
16.7 Electromagnetic Analysis –Results & Discussion 496
16.8 Investigation on Impact of Different Parameters 500
16.8.1 Torque-Speed Curve 506
16.9 Summary 510
16.10 Future Work 513
References 513
17 Implementation of Automatic Unmanned Battery
Charging System for Electric Cars 517
Shefali Jagwani
17.2 Proposed System 521
17.3 MATLAB Simulation 523
17.3.1 Mathematical Modelling 523
17.3.2 Simulation and Analysis of Battery Discharging
at EV Charging Station 526
17.4 Conclusion 529
References 529
18 Improved Dual Output DC-DC Converter
for Electric Vehicle Charging Application 533
R. Latha
18.2 Proposed Dual Output Quadratic Boost Converter 537
18.2.1 Solar PV System 537
18.2.1.1 Mathematical Modeling of PV System 537
18.2.2 Switching Methodology 538
18.2.2.1 Topology of Proposed Converter 539
18.2.3 Estimation of Parameters of Proposed
SIDO Converter 543
18.2.3.1 Design Example 544
Contents xv
18.3 Simulation of the Proposed Converter 545

18.4 Experimental Results 545
18.5 Conclusion 550
References 551
19 DFIG Based Wind Energy Conversion Using Direct
Matrix Converter 553
Vineet Dahiya
Chapter-I 554
Introduction 554
19.1 Introduction to Matrix Converters 558
19.2 Introduction to Control and Modulation
Techniques in Matrix Convertor 559
19.3 Introduction to Predictive Control Techniques 562
Chapter-II 562
Concept and System Description: Doubly Fed Induction
Generator (DFIG) in Wind Energy Conversion System 562
Chapter-III 571
Modeling and Simulation of DFIG in MATLAB 571
Chapter-IV 574
The Matrix Converter and Predictive Control Technique 574
19.4 Topologies of Matrix Converters and Use
of Predictive Control 583
19.5 Conclusion 588
19.6 Scope for Future Work 589
References 590
Part III: Trends in Control Methods

20 Microgrid: Recent Trends and Control 597
S. Monesha and S. Ganesh Kumar
20.2 MG Concept 599
20.2.1 Different Structures of MG 600
20.2.1.1 AC MG 600
20.2.1.2 DC MG 601
20.2.1.3 Hybrid AC/DC MG 602
20.2.1.4 Urban DC MG 602
20.2.1.5 Ceiling DC MG 602
20.3 MG Control Layer 603
20.4 Functional Requirements of MG Management 604
xvi Contents
20.4.1 Forecast 604

20.4.2 Real-Time Optimization 604
20.4.3 Data Analysis and Communication 604
20.4.4 Human Machine Interface 605
20.5 Energy Management Schemes 605
20.5.1 Communication-Based Energy Management 605
20.5.2 The Communication-Less Energy Management
System 608
20.6 Overview of MG Control 611
20.6.1 Power Flow Control by Current Regulation 611
20.6.2 Power Flow Control by Voltage Regulation 612
20.6.3 Agent-Based Control 613
20.6.4 Multi-Agent System (MAS) Based Distributed
Control 613
20.6.5 PQ Control 614
20.6.6 VSI Control 614
20.6.7 Central Control 614
20.6.8 Master/Slave Control 615
20.6.9 Distributed Control 615
20.6.10 Droop Control 616
20.6.11 Control Design Based on Transfer Function 616
20.6.12 Direct Lyapunov Control (DLC) 617
20.6.13 Passivity Based Control (PBC) 617
20.6.14 Model Predictive Control (MPC) 618
20.7 IEEE and IEC Standards 621
20.8 Challenges of MG Controls 623
20.8.1 Future Trends 624
Acknowledgement 624
References 624
21 Control Techniques in Sustainable Applications 631
R. Dhanasekar, L. Vijayaraja and S. Ganesh Kumar
21.2 Sliding Mode Control Techniques in Sustainable
Applications 634
21.3 Passivity-Based Control in Sustainable Applications 644
21.4 Model Predictive Control in Sustainable Applications 650
21.5 Conclusion 655
Acknowledgement 655
References 655
Contents xvii
22 Optimization Techniques for Minimizing Power Loss in Radial

Distribution Systems by Placing Wind and Solar Systems 659
S. Angalaeswari, D. Subbulekshmi and T. Deepa
I. Introduction 660
22.1 Distribution Systems 660
22.2 Radial Distribution Network 661
22.3 Power Loss Minimization 662
22.4 Optimization Techniques 664
22.5 MATLAB Tools for Optimization Techniques 670
22.6 Conclusion 674
References 675
Appendix 679
23 Passivity Based Control for DC-DC Converters 681
Arathy Rajeev V.K. and Ganesh Kumar S.
23.2 Passivity Based Control 683
23.3 Control Law Generation Using ESDI, ESEDPOF,
ETEDPOF 686
23.3.1 Energy Shaping and Damping Injection (ESDI) 686
23.3.2 Exact Tracking Error Dynamics Passive Output
Feedback (ETEDPOF) 687
23.3.3 Exact Static Error Dynamics Passive
Output Feedback 692
23.4 Control Law Generation Using ETEDPOF
Method for DC Drives 692
23.4.1 Buck Converter Fed DC Motor 692
23.4.2 Boost Converter Fed DC Motor 697
23.4.3 Luo Converter Fed DC Motor 701
23.5 Sensitivity Analysis 706
23.5.1 Sensitivity Analysis of Buck Converter 707
23.5.2 Sensitivity Analysis of Boost Converter 709
23.5.3 Sensitivity Analysis of a Luo Converter 710
23.6 Reference Profile Generation 713
23.6.1 Boost Converter Fed DC Motor 713
23.6.2 Luo Converter Fed DC Motor 715
23.7 Load Torque Estimation 719
23.7.1 Reduced-Order Observer for Load Torque
Estimation 719
23.7.2 SROO Approach for Load Torque Estimation 720
xviii Contents
23.7.3 Load Torque Estimation Using Online Algebraic

Approach 721
23.7.4 Sensorless Online Algebraic Approach (SAA)
for Load Torque Estimation 723
23.8 Applications of PBC 724
23.9 Conclusion 726
References 728
24 Modeling, Analysis, and Design of a Fuzzy Logic Controller
for Sustainable System Using MATLAB 731
T. Deepa, D. Subbulekshmi and S. Angalaeswari
24.2 Modeling of MIMO System 734
24.3 Analysis of MIMO System Using MATLAB 734
24.4 Optimization Techniques for PID Parameter 742
24.4.1 Controller Design 742
24.4.1.1 PID Controller Design 742
24.4.2 Optimization of PID Controller Parameter 743
24.5 Fuzzy Logic Controller Using MATLAB/Simulink 744
24.6 Conclusion 745
References 746
25 Development of Backstepping Controller for Buck Converter 749
R. Sureshkumar and S. Ganesh Kumar
25.2 Buck Converter With R-Load 751
25.2.1 Mathematical Model 752
25.2.2 Buck Converter with PMDC Motor 752
25.2.3 Mathematical Model 753
25.3 Controller Design 754
25.3.1 Basic Block Diagram for PI/Backstepping
Controller 754
25.3.2 Conventional PI Controller Design 754
25.3.3 Backstepping Controller Design 756
25.3.4 Backstepping Control Algorithm 757
25.3.5 Controller Design for Buck Converter
with R-Load 757
25.4 Simulation Results 766
25.5 Hardware Details 768
Contents xix
25.5.1 Buck Converter Specifications 771

25.5.2 Advanced Regulating Pulse Width Modulator 773
25.5.3 Principles of Operation 774
25.6 Hardware Results 775
25.7 Conclusion 777
References 778
26 Analysing Control Algorithms for Controlling the Speed
of BLDC Motors Using Green IoT 779
V. Evelyn Brindha and X. Anitha Mary
26.2 Working of BLDC Motor 780
26.3 Speed Control of Motor 781
26.4 Speed Control of BLDC Motor with FPGA 786
26.5 Advancements in Green IoT for BLDC Motors 786
26.6 Conclusion 787
References 787
Index 789
Preface
With an increasing demand for power production, along with demand for
power conversion and motor control in electric vehicles (EVs), there is a
great demand for power converters and related technologies. Similarly,
a related field, “drives and controls,” is gaining prominence due to the
increasing use of linear motors, actuators, robots, pneumatics and hydrau-
lic cylinders. Such a rapid growth is in compliance with sustainable devel-
opment goals (SDGs) and Industry 4.0.
Considering the above facts, we, the editors, deemed it necessary to put
together this much needed book, Power Converters, Drives and Controls for
Sustainable Operations. This book has been aptly divided into three parts.
As in any conversion process, the efficiency of power conversion is
the most important issue. Part I of the book is on switched-mode con-
verters and deals with the need for power converters, their topologies,
principles of operation, their steady-state performance, and applications.
Conventional topologies like buck, boost, buck-boost converters, invert-
ers, multilevel inverters and derived topologies (such as high gain, bridge
converters, and resonant converters) are covered in Part I with features
and their applications in fuel cells, photovoltaic (PV) and EVs. Switching
inverters have been gaining in popularity over linear inverters, due to their
inherent higher efficiency. Over the past decade, a variety of strategies to
switch the inverter switches have been evolved for various applications.
Hence, in this part, concepts of switched-mode inverters, pulse width
modulated switching schemes for inverters, three-phase 15-level grid-
connected inverters, harmonic elimination techniques, and current con-
trolled inverters are also discussed.
Part II of the book is concerned with electrical machines and convert-
ers used for EV applications. Standards for EV, charging infrastructure,
and wireless charging methodologies are addressed. Machines such as
permanent magnet synchronous motors, induction motors, permanent
magnet-assisted synchronous reluctance motors, synchronous reluctance
motors and doubly-fed induction generators are considered for analysis.
xxi
xxii Preface
Further, converters such as DC-DC converters, 31-level asymmetrical

multilevel inverters, single input dual output converters and matrix con-
verters used for EV applications are discussed here.
The last part deals with the dynamic model of switched-mode con-
verters. In any DC-DC converter, it is imperative to control the output
voltage as desired. Such a control may be achieved in a variety of ways.
While several types of control strategies are being evolved, the popular
method of control is through the duty cycle of the switch at a constant
switching frequency. This part of the book briefly reviews the conventional
control theory and builds on the same to develop advanced techniques in
the closed-loop control of switch mode power converters (SMPC), such
as sliding mode control, passivity-based control, model predictive control
(MPC), fuzzy logic control (FLC), and backstepping control.
We, the editors acknowledge the help received from the research
scholars Mr. R. Dhanasekar and Mr. L. Vijayaraja, Sri Sairam Institute
of Technology, Chennai, India and Dr. S. Sanjeevi, Professor (Retired),
Department of Geology, Anna University, Chennai, India.
We, the editors hope that this book will be useful for the readers who are
working in power electronics and sustainable applications.
Editors
Dr. S. Ganesh Kumar
Assistant Professor (Selection Grade),
Department of Electrical and Electronics Engineering,
Deputy Director, Centre for Academic Courses,
Anna University, Chennai, India
Email: [email protected]
Dr. Marco Rivera Abarca

Full Professor, Department of Electrical Engineering,
Universidad de Talca, Chile
Dr. S.K. Patnaik

Professor, Department of Electrical and Electronics Engineering,
Former Director, All India Council for Technical Education (AICTE),
New Delhi, India
Part I
POWER CONVERTER TOPOLOGIES
FOR SUSTAINABLE APPLICATIONS
1
DC-DC Power Converter Topologies
for Sustainable Applications
Nandish B. M.1, Pushparajesh V.2* and Marulasiddappa H. B.1
1
Department of Electrical and Electronics, Jain Institute of Technology, VTU,
Karnataka, India
2
Department of Electrical and Electronics, FET, Jain Deemed to be University,
Karnataka, India
Abstract
A sustainable development of modern power equipment needs a power variable
converter. Small scale electrical appliances/motors need modern power converters
for better efficiency. As the world is moving fast with electrification bypassing the
use of fossil powers in every aspect, for example electric vehicles. Power switch-
ing converters brings lots of applications for every converter with different power
rating. In this chapter, DC-DC converter topologies are discussed in detail about
classification and applications of different DC-DC converter. As the DC-DC con-
verters are basically designed for power flow control from DC power source to
another DC source or device. These are static power converters with wide appli-
cations in modern era like hospitals for medical equipment’s, micro and mini
grids with Vehicle to Grid (V2G) technology and Railways. Application of various
DC-DC converts are discussed in detail for linear mode, hard switching and soft
switching DC-DC converter.
Keywords: Static power converter, micro grid, power switching converter
*Corresponding author: [email protected]
S. Ganesh Kumar, Marco Rivera Abarca and S. K. Patnaik (eds.) Power Converters, Drives and Controls
for Sustainable Operations, (3–20) © 2023 Scrivener Publishing LLC
3
4 DC-DC Converters for Sustainable Applications
1.1 Introduction
New emerging technologies in electric vehicles, computers, smart phones,
and tablets are concentrating on the development of efficient battery
chargers. This has become a challenge in the power sector to improvise
the battery operating states. Switched mode DC-DC converters play an
important role in this field. DC-DC converters are high frequency power
converters and use high frequency switching. DC-DC converters are now
used in automotive applications with low voltage and high efficiency [1].
DC-DC conversion is done by chopping either the input voltage or the
current, named as choppers or switch mode power converters. All the
power converters are closed loop converters as the efficiency of the sys-
tem is increased. Choppers are always operated in forced commutation.
Non-isolated DC-DC converters have major applications in DC microg-
rids [2]. High power DC-DC converters have applications in HVDC grid
interconnection [3]. This chapter mainly concentrates on the classifica-
tions of DC-DC converters and their role in different applications in the
present challenging world. It also highlights the importance of the control
in DC-DC converters.
As we all know, DC-DC converters are nonlinear systems as the input
and the output of the systems are variable. There are several proposed con-
verter topologies discussed in the past decades. All the proposed convert-
ers are designed to serve one specific application or another. Some of them
are named based on their applications, such as buck, boost, and buck-boost
converters. In this chapter we are going to classify the converters depend-
ing on their application areas so that it will be easy to contribute to research
work for a better world.
1.2 Classifications of DC-DC Converters

DC-DC converters are classified based on their working nature. Broadly,
these are classified into three types:
i. Linear mode DC-DC converter

ii. Hard switching DC-DC converter
iii. Soft switching DC-DC converter
These converters are again subclassified based on their components and

applications. These classifications are discussed in detail in this section.
Detailed classification of DC-DC converter is shown in Figure 1.1.
DC-DC Converter Topologies for Sustainable Applications 5
Series Regulators
Linear Mode
Parallel Regulators
Forward
Flyback
Isolated
Push-pull
Half bridge
DC-DC Converter Hard Switching
Buck
Non-Isolated
Boost
Buck-Boost
Zero Current Switching (ZCS)
SEPIC
Soft Switching Zero Voltage Switching (ZVS)
Cuk
Zeta
Figure 1.1 Classification of DC-DC converter.
1.2.1 Classification of Linear Mode DC-DC Converters

1.2.1.1 Series Regulators
The series voltage controller or series pass voltage controller utilizes a
variable component set in arrangement with the load. By changing the
obstruction of the arrangement component, the voltage dropped across it
very well may be fluctuated to guarantee that the voltage over the load stays
consistent. The circuit of the arrangement controller is shown in Figure 1.2.
Series
Element
Regulated Input
Unregulated Input
Load
References
Figure 1.2 Series regulators.

Input
Voltage Zener Diode
Output
Voltage
Figure 1.3 Parallel regulators.
1.2.1.2 Parallel Regulators

One of the most widely recognized and basic types of shunt controller is
the straightforward Zener diode controller circuit demonstrated as follows.
Its activity is clear. Once over its least current, the Zener diode keeps up a
practically consistent voltage over its terminals. The circuit of arrangement
the controller is shown in Figure 1.3.
In this circuit, the arrangement resistor drops the voltage from the
source to the Zener diode and burden. As the Zener diode keeps up its
voltage, any varieties in burden current do not influence the voltage over
the Zener diode.
1.2.2 Classification of Hard Switching DC-DC Converter

Hard switching DC-DC converters are sub classified into two major cate-
gories and are listed below.
i. Isolated DC-DC Topologies

ii. Non-Isolated DC-DC Topologies
1.2.2.1 List of Isolated DC-DC Topologies

1.2.2.1.1 Forward Converter Topology
A forward converter is a sort of DC-DC converter that, similar to the
flyback and half-connect converters, can gracefully yield a voltage either
Db L
Dc C
R
V input
M Da
Figure 1.4 Forward converter.
higher or lower than the info voltage and give electrical disengagement
through a transformer [4, 5]. Albeit more unpredictable than a flyback,
the forward converter configuration can yield higher yield power (for the
most part up to 200W) alongside higher energy productivity. The circuit of
arrangement controller is shown in Figure 1.4.
The hardware on the optional (for example right) side is practically
indistinguishable from a buck converter and forward converters store
and convey energy similarly. The exchanging component, frequently a
force MOSFET or IGBT, in a perfect world is either opened or cut off
(or on) so the forward converter will shift back and forth between two
unique states.
1.2.2.1.2 Flyback Converter

Flyback converters are one of the least difficult DC-DC converter geog-
raphies to incorporate electrical disengagement. Albeit for the most part
they just suitable for lower range power supplies (up to 100W), they do
have various focal points. Other than the converter’s intrinsic straight-
forwardness, maybe the best of these is that the plan does not need an
extra inductor [6]. The transformer gives separation, but then addi-
tionally works as a couple of coupled inductors, putting away energy
similarly as with an essential buck or lift converter. Supplanting the
transformer with an arrangement inductor will, indeed, give us the lift
converter geography. The circuit arrangement of the controller is shown
in Figure 1.5.
V output
C
R
V input
Figure 1.5 Flyback converter.
The exchanging component, frequently a force MOSFET or IGBT, is

preferably either opened or stopped (or on) so the buck converter circuit
will shift back and forth between two distinct states.
1.2.2.1.3 Push-Pull Converter

A push–pull converter is a sort of DC-to-DC converter, an exchanging
converter that utilizes a transformer to change the voltage of DC power
flexibly [7]. The distinctive element of a push-pull converter is that the
transformer essentially is provided with current from the info line by sets
of semiconductors in a balanced push-pull circuit. The circuit of arrange-
ment controller is shown in Figure 1.6.
Da
L
R
C
N1 N2 V output
V input
+
Db
–
Sa Sb
Figure 1.6 Push-pull converter.

The semiconductors are, on the other hand, turned high to low, quickly
changing the corresponding current in the transformer. Alternatively, the
current absorber is in the line over the two exchanging cycle. These differ
from buck-help converters, in which the information current is provided
by a solitary semiconductor which is turned here and there, so current is
just drawn from the line during a large portion of the exchanging cycle.
During the other, a large portion of the yield power is provided by energy
put away in inductors or capacitors in the force flexibly. Push–pull convert-
ers have steadier info current, make less commotion on the information
line, and are more productive in higher force applications.
1.2.2.1.4 Half-Bridge Converter

A half-bridge converter is a kind of DC-DC converter that, as flyback and
forward converters, can gracefully a yield voltage either higher or lower
than the information voltage and give electrical separation by means of a
transformer. Albeit more mind boggling than a flyback or forward con-
verter, the half-bridge converter configuration can yield higher power
(conceivably up to 500W) and use parts that are more modest and afford-
able. The circuit arrangement of the controller is shown in Figure 1.7.
The essential side capacitors are utilized to create a consistent mid-point
voltage, a large portion of the info voltage, over the essential winding [8,
9]. This implies that the exchanging components need to withstand a larger
portion of the voltage than those of a comparable forward converter [10].
Ca
Vca
Da
Vin
Cc
C Vout
Cb Db
Vcb
Figure 1.7 Half-bridge converter.

1.2.2.2 Classification of Non-Isolated DC-DC Converters

The above topologies are broadly classified into 6 categories and they are
listed below:
1. Cuk-Converter
2. Single-Ended Primary Inductance Converter (SEPIC)
3. Boost Converter
4. Buck-Boost Converter
5. Buck Converter
6. Zeta Converter
1.2.2.2.1 Cuk-Converter
Cuk-converters are the extended version of boost converters, also we can
say they are derived from boost converters. The operation of the Cuk-
converter is discussed here. The output voltage Vo is calculated using the
expression shown below. A Cuk-converter is operated in two modes: con-
tinuous conduction mode and discontinuous conduction mode [11, 12].
The operation of continuous and discontinuous conduction mode is dis-
cussed in detail below. The Cuk-converter is shown in Figure 1.8. From the
figure, S and D1 are on during switch on and D is off and D is on during
switch off and S and D1 are off.
p
VO = Vin (1.1)
1− p
Continuous Conduction Mode

Average inductor voltage is zero in a steady state condition, therefore the
voltage is given as
VC1 = VCO = VO (1.2)
Lb Ca
Vin M D Cb R Vout
Figure 1.8 Cuk-converter.

Voltage across the capacitors C1 and C are equal during the switch on
period. Assuming the value of capacitors C and C1 are large, the voltage
across them are given as
VC = VC1 = VO (1.3)
IL being the inductor current increases during the switch on period and
during switch off period, it decreases. The voltage values across inductor L
are given as VI and - (VC - VI).
Therefore,
pTVI = (1–p)T(VC–V1) (1.4)
Hence,
1
VO = VC = VC1 = VCO = V (1.5)
1− p
Discontinuous Conduction Mode

During discontinuous conduction mode, the current across the inductor iL
increases when its switch is on and during switch off, the current decreases
from pT to (1-p)mT. The corresponding voltage across the inductors are
given as V I and –(vc – vI).
∴ pTVI = (1 – p)mT(Vc – VI) (1.6)
Hence,
 p 
Vc = 1 +  V1 (1.7)
 (1 − p)m 
Assuming C, C1, and CO are very large values,
 p 
Vo = Vc = Vco = 1 +  V1 (1.8)
 (1 − p )m 
1.2.2.2.2 Single-Ended Primary Inductance Converter (SEPIC)

SEPIC converters are derived from boost converters. The working of SEPIC
converters is discussed here. A circuit diagram of a SEPIC converter is
shown in Figure 1.9. The output voltage VO is calculated using the equation
shown below. The SEPIC converter is operated in two different modes: con-
tinuous conduction mode and discontinuous conduction mode [13, 14].
p
VO = Vin (1.9)
1− p
Continuous Conduction Mode

The average voltage across the inductor in the steady state over a period is
given by:
VC = VI (1.10)
The voltage across the capacitors C1 and C is the same during switch on
period. We have assumed the capacitors C1 and C are large and the voltage
across them is given by:
VC1 =VC = VI (1.11)
Average voltage across the inductor LO during steady state over a period
is given as:
VC2 =VC0 = V0 (1.12)
Current across the inductor iL increases during switch on period and the
value of current decreases during switch off period.
Voltage across the inductors L is given as V and I – (Vc – Vc1 + Vc2 – VI).
Ca D
La
Vin Vout
R
Lb Cb
M
Figure 1.9 Single-Ended Primary Inductance Converter (SEPIC).

∴ pTVI = (1 – p)TVc – Vc1 + Vc2 – VI) (1.13)
Hence,
1
Vo = VI = Vco = Vc2 (1.14)
1− p
VT gain in the continuous conduction mode is given as:
Vo 1
M = = (1.15)
VI 1 − p
Discontinuous Conduction Mode

In DCM, the inductor current iL increases during the switch on period and
current decreases during the switch off period from pT to (1 – p)mT.
Voltage across the inductors L is given as V and -(VC-VC1+VC2−VI ).
Thus,
pTVI = (1 – p)T(VC-VC1+VC2−VI ) (1.16)
and
VC= VI VC1=VC= VI VC2= VCO = VO (1.17)
Hence,
p
VO = 1 + V (1.18)
(1 − p )m I
So, the real DC voltage transfer gain in the Discontinuous Current
Mode is given as:
R
M DCM = 1 + p2 (1 − p) (1.19)
2 fLeq
1.2.2.2.3 Boost Converter

Boost converters are nothing but step-up DC/Dc converters which oper-
ates in the second quadrant. Boost converter operation can be derived from
quadrant II chopper. A circuit diagram of the Boost Converter is shown in
Figure 1.10. Voltage across the output represented by:
T 1
VO = Vin = Vin (1.20)
T − ton 1− p
1
where T =
f
f = Chopping frequency
ton = Switch-on time
p = Duty cycle
ton
p= (1.21)
T
1.2.2.2.4 Buck-Boost Converter Topology

The above topology is a step up or step-down converter. These topologies
perform in the third quadrant. The working circuit of the Buck-boost con-
verter is given in Figure 1.11. O/p voltage represented as
ton p
VO = Vin = Vin (1.22)
T − ton 1− p
Where
1
T = (1.23)
f
F= frequency
ton = switch-on schedule
p= conduction obligation cycle
ton
p = (1.24)
T
L D
Vin Vout
R
M C
Figure 1.10 Boost converter.
M D
Vin Vout
L R
C
Figure 1.11 Buck-boost converter topology.
By utilizing the above topology, it is difficult to get the required voltage

level, which can be different from the actual value.
1.2.2.2.5 Buck Converter

This topology is a step-down DC-DC topology, which steps down the volt-
age from the primary end to the secondary end. This can also be inter-
preted as stepping up the current from input to the output. Normally, these
converters consist of a couple of transistors, a capacitor, and an inductor
[15]. These converters provide much higher efficiency than linear regula-
tors and are normally simpler in design but fail to step-up the current. The
circuit arrangement of the controller is shown in Figure 1.12.
1.2.2.2.6 Zeta Converter

The Zeta converter is a non-linear fourth order converter and with regards
to energy input it can be used as buck-boost-buck converter. It can be used
M
Lb
Vin D Cb R Vout
Figure 1.12 Buck converter.

M Ca Lb
D Cb R Vout
Vin
La
Figure 1.13 Zeta converter.
as a boost-buck-boost converter with regards to the output [16]. The cir-

cuit diagram of a Zeta converter is shown in the Figure 1.13.
1.2.3 Classification of Soft Switching DC-DC Converter

1.2.3.1 Zero Current Switching (ZCS)
The above converter is one among the DC-DC topology family. This con-
verter neutralises the switching loss during the turn-off period. Switching
losses are minimized during the turn-on period of the operation [17]. ZCS
converter operation is not affected by the diode capacitance, as there is a
large capacitor placed at the output end prior to resonance.
1.2.3.2 Zero Voltage Switching (ZVS)

Similar to that of the ZCS, zero voltage switching also neutralizes the losses
during capacitor turn-on. These converters are good for high frequency
applications. Voltage stress proportional to the load will appear for one end
of the switching operation.
1.3 Applications of DC-DC Converters in Real World

DC-DC converters have wide applications in the present day. Varying from
small scale to large scale applications, DC-DC converters play an import-
ant role. A wide variation of voltage levels is required in daily appliances
to provide continuous, uninterrupted supply and these converters are very
useful. Applications of DC-DC converters are listed in the Table 1.1, shown
below [18].
Table 1.1 Applications of DC-DC converters.

Sl. no. Converter Application
1 Series Regulators
2 Linear Mode Parallel Use in all power
DC-DC Regulators supplies to electronic
Converters contraptions to control
voltage and spare the
gadget from harm;
Utilized with the
alternator of inward
burning motors to
direct the alternator
yield; Utilized for
gadget circuits to
flexibly include an exact
measure of voltage
3 Isolated DC-DC Forward Power metering, modern
Converters Converter programmable logic
Flyback controllers (PLCs),
4
Converter insulated-gate bipolar
transistor (IGBT)
5 Push-pull driver power
Converter supplies, mechanical
6 Half-bridge fieldbus, and modern
Converter robotization
7
8 Non-Isolated Cuk-Converter The converter is
DC-DC anticipated for huge
9 Single-Ended
Converters force electronic
Primary
applications where
Inductance
regularly the converters
Converter
are taken care of
(SEPIC)
DC supplies at a
10 Boost Converter commonplace voltage
level of around a couple
11 Buck-Boost
of kV
Converter
12 Buck Converter
13 Zeta Converter
(Continued)
Table 1.1 Applications of DC-DC converters. (Continued)

Sl. no. Converter Application
14 Soft Switching Zero Current Use of delicate exchanging
DC-DC Switching in DC-DC converters
Converters (ZCS) has made astounding
progress in power
15 Zero Voltage gadgets innovation
Switching regarding a decrease in
(ZVS) exchanging misfortunes,
improving in influence
thickness, minimization
of electromagnetic
impedance (EMI), and
decrease in the volume
of DC-DC converters
1.4 Conclusion
Application of DC-DC converters is vital in the modern world. As the
world is moving towards electric vehicles, DC-DC converters play a very
important role. This chapter gives a brief of different types of converters
and their basic operations. Every converter has its own application areas
and is important. Applications of every converter are listed in this chap-
ter in brief. Overall, the operation and control of DC-DC converters is
explained.
References
1. H. Matsumori, T. Kosaka, K. Sekido, K. Kim, T. Egawa and N. Matsui, “Isolated
DC-DC Converter utilizing GaN power device for Automotive Application,”
2019 IEEE Applied Power Electronics Conference and Exposition (APEC),
Anaheim, CA, USA, 2019, pp. 1704-1709.
2. P. Odo, “A Comparative Study of Single-phase Non-isolated Bidirectional
DC-DC Converters Suitability for Energy Storage Application in a DC
Microgrid,” 2020 IEEE 11th International Symposium on Power Electronics
for Distributed Generation Systems (PEDG), Dubrovnik, Croatia, 2020, pp.
391-396.
3. Z. W. Khan, H. Minxiao, C. Kai, L. Yang and A. u. Rehman, “State of the Art
DC-DC Converter Topologies for the Multi-Terminal DC Grid Applications:
A Review,” 2020 IEEE International Conference on Power Electronics, Smart

Grid and Renewable Energy (PESGRE2020), Cochin, India, 2020, pp. 1-7.
4. Luo, F.L. and Ye, H., Positive output super-lift converters, IEEE Transactions
on Power Electronics, 18, 105, 2003.
5. Luo, F.L. and Ye, H., Positive output super-lift Luo-converters, in Proceedings
of IEEE- PESC’2002, Cairns, Australia, 2002, p. 425.
6. A.M. Trzynadlowski, Introduction to Modern Power Electronics, third ed.,
Wiley, New York, NY, 2015.
7. P.T. Krein, Elements of Power Electronics, second ed., Oxford University
Press, New York, NY, 2014.
8. Luo F. L. and Ye H., Advanced DC/DC Converters, CRC Press, LLC, Boca
Raton, 2003.
9. Luo F. L. and Ye H., Ultra-Lift Luo-Converter, in IEE-EPA Proceedings, 152,
1, 2005, pp. 27-32.
10. Ioinovici, Power Electronics and Energy Conversion Systems, Fundamentals
and Hard-Switching Converters, Wiley, New York, NY, 2013.
11. Luo, F.L., Seven self-lift DC/DC converters: voltage-lift technique, IEE
Proceedings on Electric Power Applications, 148, 329, 2001.
12. M.K. Kazimierczuk, Pulse-Width Modulated DC-DC Power Converters,
second ed., Wiley, New York, NY, 2015.
13. Luo, F.L., Double output Luo-converters: advanced voltage lift technique,
IEE-Proceedings on Electric Power Applications, 147, 469, 2000.
14. M.K. Kazimierczuk, Class-D voltage-switching MOSFET power amplifier,
IEE Proc. Electric Power Appl. 138 (1991) 285–296.
15. Luo, F.L., Positive output Luo-converters: voltage lift technique, IEE
Proceedings on Electric Power Applications, 146, 415, 1999.
16. K. Lee, Z. Pantic, S.M. Lukic, Reflexive field containment in dynamic
inductive power transfer systems, IEEE Trans. Power Electron. 29 (2014)
4592–4602.
17. Cúk, S., Basics of switched-mode power conversion: topologies, magnetics,
and control, in Cúk, S., Ed., Advances in Switched-Mode Power Conversion,
Irvine, CA, Teslaco, 1995, vol. 2.
18. N. Mohan, T.M. Undeland, W.P. Robbins, Power Electronics: Converters,
Applications and Design, third ed., John Wiley & Sons, New York, NY, 2003.
2
DC-DC Converters for
Fuel Cell Power Sources
M. Venkatesh Naik1*, Paulson Samuel1 and Srinivasan Pradabane2
1
Electrical Engineering Department, MNNIT Allahabad, Uttar Pradesh, India
2
Electrical Engineering Department, NIT Warangal, Telangana, India
Abstract
In this chapter, various topologies of DC-DC converters for use with Polymer
Electrolyte Membrane Fuel Cells (PEMFC) are emphasized. The non-isolated type
of DC-DC converters are examined as they are of special interest. A 24 kW, 180 V
PEMFC source is considered as the power source and the input and output volt-
ages and input and output currents are plotted. In addition, the ripples present in
the FC currents have been evaluated for each converter under study for common
loads. The non-inverting type buck boost converters, like buck boost converters
(BBC) and interleaved buck boost converters (IBBC), are studied and their steady
state performances are presented. Further, the proposed converters’ multi-device
buck boost converters (MDBBC) and multi-device multi-phase interleaved buck
boost converter (MDMPIBBC) are compared with existing BBC and IBBC topolo-
gies for an FC power source whose terminal voltage varies from 28.0 V at full load
and 45.0 V at no load. From the study it is shown that the proposed MDMPIBBC
converter gives smaller ripple current with lower sizes of passive component
parameters. The converter configurations for integrating an FC source with a DC
link feeding a 400 V, 50 Hz inverter is proposed.
Keywords: DC-DC power converters for fuel cells, buck boost converters for
fuel cells
21
2.1 DC-DC Boost Converter in Fuel Cell (FC)

Applications
Fuel cells are low voltage high current (LVHC) devices. The FC stack out-
put voltage is around 50V. The power converters connected with these
devices should provide high voltage gain to reach the high output voltage
and less input ripple current [1–3]. For automotive, grid-connected, and
portable applications, the PEMFC type FCs are most appropriate due to
their high power density, low temperature, and faster transient response
for the dynamic loading conditions [4–6]. An FC, when utilized as a part of
various applications as listed in Table 2.1, requires DC-DC voltage trans-
formation in view of the higher DC link voltage needed. Since the DC link
voltage (VDC) is usually higher than the FC stack voltage, DC-DC boost
converters are utilized [7–9].
For the requirement of a DC link voltage smaller than the FC stack
voltage, buck converters are used and such applications include portable
power and battery charging. A special case is when the regulated voltage
falls inside the FC unregulated voltage range and requires the use of buck-
boost converters. All the distinctive types of DC-DC converters are clas-
sified in Figure 2.1. Considering the switching approaches, there are two
basic types: hard switching and soft switching converters. Based on isola-
tion between the input and output side, the converters are further classi-
fied as non-isolated and isolated converters. The distinctively non-isolated
type converters are boost, buck, buck-boost, Cuk, and Sepic converters.
Considering the number of switches connected in the topologies, iso-
lated converters are further classified as single switch and multiple switch
Table 2.1 DC link voltage levels in various applications.

DC link voltage levels Applications
42 V Automobile systems
48 V, 120 V Parallel grid or standalone systems
270 V or 350 V Aircraft
350 V – 750 V Electric transit bus system (350V); Tramway
and tramcar, locomotive systems (750V)
270 V – 540 V Electric automotive
400 V – 480 V Stand alone or parallel grid connection
DC-DC Converters for Fuel Cell Power Sources 23
DC-DC Converters
Soft
Linear Hard switching switching
(Resonant)
ZCS ZVS
Series Parallel Non-Isolated Isolated converters
regulator regulator
Boost Buck Buck- Cuk Sepic One switch Multiple switch

boost
Fly-
Boost Forward back Cuk Sepic Push Half Full
pull bridge bridge
Figure 2.1 Classification DC-DC converters for sustainable applications.

converters. The single switch converters are boost, forward, flyback, Cuk,
and Sepic converters and push-pull, half bridge, and full bridge converters
go under the multiple switch class.
The DC link voltage or the input DC voltage requirement for the single
and three phase DC-AC inverters are 400 V and 750 V, respectively (230 V
single phase and 415 V three phase supply system). Figurer 2.2 depicts
such a system with a commercially existing PEMFC stack manufactured
by Ballard Power Systems Limited. The output voltage of the stack is 65.0 V
at no load and 45.0 V at full load condition. For a 45 V, 6 kW PEMFC
under rated operating condition, the FC terminal voltage Vfc is 45.0 V at
a rated current Ifc of 133.33 A. The FC stack voltage is low and thus, a few
such stacks are connected in series to get some sensible voltage at full load.
For instance, four such stacks can be connected in series to get 180.00 V at
full load and utilizing a boost converter, this voltage can be improved to the
required DC link voltage, i.e., VDC = 400 V, 750 V, and so on. The DC-DC
converter should be designed for high input current on the FC side and
high output voltage. The fuel cell often draws some ripple current, which
appears as an AC current on the top of the average DC current Ifc. The rip-
ple current in the fuel cell results in reduction of FC life span and unneces-
sary tripping as it gets overloaded with an extra current magnitude.
The circuit diagram of a boost converter with an FC stack is shown in
Figure 2.3. Here, four PEMFC stacks are connected in series to get 180 V
as the input voltage to the converter. Lb is the boost inductor, Cf is the filter
capacitor, T is the IGBT switch, D is the diode, and Rlb and Rcf are the inter-
nal resistances of boost inductor and filter capacitor, respectively. The input
Ifc Idc Iac

133.33A
Vfc
45V- 65V
Ifc
H2 + +
Ballard DC-DC Boost 325V/ DC- AC Inverter + 230V/

9SSL Vfc Converter 625V Filter 440V
- -
O2
H2O Heat
Figure 2.2 Block diagram of FC system connected to single or three phase stationary
load.
+DC
D
Io
RLb Lb
Ifc Rcf
Ro Vo
+
PEMFC
stacks in Cf
Vfc T
series
-
-DC
Figure 2.3 PEMFC stack associated with boost converter.
180.5
250 180
179.5
Input voltage (V)
179
200 0.0402 0.0404 0.0406
150
100
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
400
Output voltage (V)
300
340
200
338
100 0.0402 0.0403 0.0404
0
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time (sec)
Figure 2.4 Input and output voltage waveforms of boost converter to DC load.
136
250
134
FC output current (A)
200 132
0.0404 0.0405 0.0406 0.0408 0.0407

150
100
50
0
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time (Sec)
Figure 2.5 Ripple current in fuel cell output current with boost converter.
and output voltage waveforms of the boost converter are shown in Figure
2.4. Also, the ripple present in FC output current is shown in Figure 2.5.
2.2 DC-DC Buck Converter

Buck converters are required when the voltage required is less than the
voltage of the FC stack or stacks. As shown in Figure 2.6, a buck converter
is associated with four PEMFC stacks of rating 6 kW, 45 V, whereas the no
load voltage of the stack is 260 V. Ifc is the stack output current, Vfc is the
stack output voltage, T is the MOSFET switch, D is the diode, L is the buck
inductance, C is the filter capacitance, and Ro is the output resistance. For
portable applications, smaller voltages are required, such as 42 V and 48 V,
as given in Table 2.1.
The FC stack rated voltage usually lies in the range of 12 V – 72 V.
Any convenient voltage lesser than the FC rated voltage can be effectively
obtained by utilizing a buck converter with a certain duty ratio. As the
voltage range is small, the MOSFET is suitable for the switching device in
Ifc L
+ T Io
PEMFC
Stacks Vfc Ro Vo
D C
in series
Figure 2.6 PEMFC stack associated with buck converter.

260
231 Vfc
Duty cycle D=0.7
230.5
240 2.96 2.962 2.964 2.966
Input and Output voltages (V)
220
2.96
200
Vo
180 159.12
159.1
2.96 2.962 2.964 2.966
160
Ro=15 Ω Ro=7.5 Ω Ro=15 Ω

140
0 1 2 3 4 5 6
Time (Sec)
Figure 2.7 Input and output voltages of buck converter for load disturbance.
the circuit. Figure 2.7 depicts the variation in FC stack voltage and load
voltage for a load disturbance. The input voltage for the converter is 230 V
with duty cycle 0.7 and the output voltage of the converter is 160 V. The FC
voltage is unregulated and varies as the load current varies.
2.3 DC-DC Buck-Boost Converter

Figure 2.8 shows a single switch buck-boost converter connected with a
PEMFC stack. The output polarity is opposite to the FC voltage polarity
and output voltage varies with the duty cycle of the switch T. Another
possible topology of a buck-boost converter is obtained by combining a
boost converter with a buck converter and this topology results in a single
inductor non-inverting type buck-boost converter. Fuel cells are unregu-
lated voltage sources and non-inverting DC-DC buck-boost converters are
used to regulate the output voltage when the derived voltage is within the
FC terminal voltage range. These types of conventional converters, when
integrated with FC sources, experience high component stress and have
low efficiency [10].
Ifc D
+ +
T Io
PEMFC
L Ro Vo
Stacks Vfc C
in series
- -
Figure 2.8 PEMFC stack associated with buck-boost converter.
The buck-boost converter is simulated with a PEMFC stack connected

at the input side of the converter. The stack is rated for 180.0 V at rated
load and 260.0 V at no load. The duty cycle of the switch is controlled to
observe the variation in FC voltage and its ripple. Figure 2.9 shows the
variation in converter output voltages for buck and boost operating modes.
For D = 0, the voltage across the load is zero as there is no energy transfer.
The buck operation is initiated at t = 2.0s and continued until t = 5.3s, with
300
Vfc
200
100
Input and output voltges (V)
-100
-200
D=0 D = 0.7 D = 0.25
-300 Vo
-400
-500
0 1 2 3 4 5 6
Time (Sec)
Figure 2.9 FC output voltage variation with buck-boost converter in buck and boost
modes.
a duty cycle D = 0.7. During this period, the FC voltage has higher ripple
compared to the boost operation. The converter is operated under boost
operation with D = 0.25 during 5.4 s < t < 6.2 s.
2.4 DC-DC Cuk-Converter
The Cuk converter is fundamentally a boost converter followed by a buck

converter. The non-isolated Cuk converter, as shown in Figure 2.10, has
the output voltage of opposite polarity to the FC voltage. The circuit com-
prises of two inductors ‘L1’ on the FC source side and ‘L2’ on the load side,
two capacitors ‘C’ in the middle which act as energy storage elements,
with ‘Cf’ on the load side, a switch ‘T’ (usually MOSFET), and a diode ‘D’.
The capacitor ‘C’ is used to transfer the energy from input to the output
with the help of the switch ‘T’ and diode ‘D’. The Cuk converter is simu-
lated with a PEMFC source of 180 V at loaded condition and 260 V at no
load condition. The FC terminal and output voltage of the Cuk converter
are shown in Figure 2.11. During the time period, at 0 < t < 1.5s the
switch T is in off mode with D = 0 and the voltage across the load is zero
as there is no energy transfer taking place. The buck operation is initiated
during the mode 1.6 s < t < 4.2 s with a duty cycle D = 0.7. The converter
is operated under boost operation with D = 0.25 during 5.4 s < t < 6.2 s.
The ripple current drawn by the FC device for the LC component values
of L1 = L2 = 750 µH and C = 550 µF is shown in Figure 2.12. The ripple
content in FC output current is 7 A and the percentage of the ripple per-
centage is 4.05%.
Ifc L1 C L2
+ + I
o
PEMFC Vo
Stack Vfc D Ro
Cf
T
- -
Figure 2.10 Cuk converter connected with PEMFC stack.

400
Vfc
300
200
Input and Output voltages (V)
100
0
Vo
-100
-200
D=0 D = 0.7 D = 0.25
-300
-400
0 1 2 3 4 5 6
Time (Sec)
Figure 2.11 Input and output voltages of cuk converter during buck and boost operation.
176
175
174
FC current (A)
173
172
171
170
169
168
0.2542 0.2544 0.2546 0.2548 0.255 0.2552 0.2554 0.2556 0.2558

Time (S)
Figure 2.12 FC output current ripple with Cuk converter.
2.5 DC-DC Sepic Converter

The operation of the Sepic converter is similar to the buck-boost con-
verter with an advantage of having a non-inverted output voltage topol-
ogy, as shown in Figure 2.13. It exchanges the energy between inductors
L1 C D
Ifc
+ Io
PEMFC Ro Vo
L2 Cf
Stack Vfc
T
-
Figure 2.13 Circuit topology of sepic converter connected with PEMFC source.
and capacitors to amplify the FC voltage. The series capacitor ‘C’ couples
energy from input to output. The amount of energy transferred depends
on the switching time of the switch ‘T’; usually a MOSFET is preferred
because of its higher input impedance and lower voltage drop. The Sepic
converters are effective for the lower voltage ranges such as 3.3 V, 4.2 V, etc.
The steady state input and output voltages of Sepic converter during buck
operation with duty cycle D = 0.7 is shown in Figure 2.14. Also, the ripple
400
D = 0.7 Vfc
350
Converter input and output voltages (V)
300
250
Vo
200
150
100
50
0
0 1 2 3 4 5 6
Time (Sec)
Figure 2.14 Input and output voltages of sepic converter for duty cycle D = 0.7.
173
172
171
170
FC current (A)
169
168
167
166
165
164
163
0.254 0.2541 0.2542 0.2543 0.2544 0.2545 0.2546
Time (S)
Figure 2.15 FC output current ripple with sepic converter.
current drawn by the FC for the LC component values of L1 = L2 = 750 µH

and C = 550 µF is shown in Figure 2.15. The ripple content in FC output
current is 7.1 A and the ripple percentage is 4.21%.
2.6 Multi-Phase and Multi-Device Techniques

for Ripple Current Reduction
The conventional non-isolated boost converters when integrated with FC
sources introduce appropriate ripple current in the FC output current. The
presence of ripple in FC current diminishes its life span and reduces the
fuel consumption and stack efficiency [11–13]. In addition, the sizes of
boost inductor and output capacitor are higher and the system gets to be
bulky. Hence, the boost converter ought to be modified to decrease the FC
ripple current and weight.
The multi-phase and multi-device DC-DC converters have better attri-
butes over the traditional DC-DC converters. The favorable attributes
include reduction of switching losses, reduced device rating and reduced
size of LC components and FC ripple current reduction. Multi-phase con-
verter topologies require a smaller volume of the LC components because
of the increased effective frequency in the input inductor and output

capacitor [14–23].
2.6.1 Multi-Device Boost Converter

In multi-device boost converters (MDBC) the number of devices per
phase is two, whereas the number of phases is one. Figure 2.16 illustrates
the MDBC topology integrated with a PEMFC stack, where Lb is boost
inductor, RLb is the equivalent series resistance (ESR) of Lb, T1 and T2 are
the IGBT switches, D1 and D2 are the diodes, Cf is the output filter capac-
itor, Rcf is ESR of output capacitor, p is the number of phases, and q is the
number of devices per phase.
In MDBC, the number of devices per phase (q) is two. By paralleling
the devices, the effective frequency of Ifc becomes twice the switching fre-
quency, fs. As the frequency is high, the component size gets reduced. The
circuit is simulated with a PEMFC stack as the input source whose output
voltage is 180 V at a full load rated current of 133.33 A. The switching
interval for switches T1 and T2 are chosen as 360o/(p×q), where p = 1 and
q = 2 for MDBC and the switching angle delay for T2 is 1800, as shown in
Figure 2.17, the switch T1 conducts at t = 0 s, and T2 conducts at Ts/2 with
1800 phase shift.
When switch T1 is on, the inductor Lb is connected with the fuel cell
output voltage or converter input voltage, Vin, and the inductor stores the
energy during the Ton period. When the switch T1 is off, the inductor cur-
rent flows through diodes D1 and D2 to the load forcefully during a period
Toff , as shown in Figure 2.17. The output current tends to decrease and the
+DC
p=1
q=2
D1 D2
Lb Io
IFC RLb RCf
+ Ro Vo
Cf
PEMFC
Stack VFC
T1 T2
-DC
Figure 2.16 Circuit topology of multi-device boost converter connected with FC stack.
1
Ts/4
T1
0.5
0
1
Ts/2 Ts/4
T2
0.5 Ts/2
0
lfc or lLb (A)
145
140 4.1 A
135
180
Vfc (V)
178
2V
176
345
Vo (V)
3V
340
66
Io (A)
66.5
0.4 A
65
Ts 2Ts
Time (S)
Figure 2.17 Switching signals for T1, T2, fuel cell current and voltage, converter current
and voltage waveforms of MDBC.
voltage induced in the inductor Lb is opposite to that of previous one. The

voltage across the load becomes vLb + Vin, i.e., the inductor voltage adds
to the input voltage to force the inductor current into the load. The FC
module output voltage Vfc = Vin is 177 V and Vout = 344 V, according to the
Vin 177
MDBC output voltage expression Vout = = = 354 V , but the
1 − (q × D ) 0.5
actual output voltage (Vout) is 343.0 V, the remaining 10 V being voltage
drops in the ESR of inductors and the switch and diode on state resistances.
Whereas in conventional boost converter the voltage drop in parasitic
is 20 V, with MDBC the parasitic resistances or ESR of inductor Lb gets
reduced to half and resulted in higher output voltage at the output than the
BC. The ripple current drawn by the FC source with an MDBC converter
is depicted in Figure 2.18 with ripple current 4.5 A.
The MDBC topology when compared with classical boost converters
has higher output voltage and lesser ripple current with reduced compo-
nent size. As there are two devices in parallel, reduced ratings of the devices
is used and the converter is also lighter in weight. However, the parallel-
ing of devices is limited by the switching difficulties and appropriate phase
shifting mechanisms are needed.
143
142
FC ripple current (A)
141
140
139
138
0.01 0.0101 0.0102 0.0103 0.0104 0.0105 0.0106 0.0107 0.0108
Time (S)
Figure 2.18 Ripple in FC output current with MDBC.
2.6.2 Multi-Phase Interleaved Boost Converter

In multi-phase interleaved boost converters (MPIBC), the number of
phases (p) are two and the number of devices per phase (q) is one. Figure
2.19 illustrates the two phase interleaved boost converter topology inte-
grated with a PEMFC stack, where Lb1 and Lb2 are boost inductors and RLb1
and RLb2 are the ESRs of Lb1 and Lb2, respectively. T1 and T2 are the IGBT
switches, D1 and D2 are the diodes, Cf is the output filter capacitor, and Rcf
is ESR of the output capacitor.
During Mode-I, for (0 < t < Ts /2): When the switch T1 is on, the inductor
Lb1 is connected to the FC voltage Vfc and the inductor stores the energy
during the Ton period (0 < t < Ts/2) and the supply current flows though the
+DC
p=2
q=1 D1 D2 +
IFC IL1 RLb1 Lb1

Io
Lb2
+ IL2 RLb2
Rcf Vo
Ro
PEMFC
Stacks in
series VFC Cf
T1 -
T2
-
-DC
Figure 2.19 Two-phase interleaved boost converter associated with PEMFC stack.
path, as shown in Figure 2.20(a). When switch T2 is off during the period
Ts/2 < t > Ts, the current in Lb2 is forced to flow through diode D2 as shown
in Figure 2.20(a), as the inductor Lb2 current tends to decrease, the voltage
induced in the inductor Lb1 is reversed to that shown in Figure 2.20(b). The
voltage across the load becomes vLb2 + Vfc, i.e., the voltage across the Lb1
adds to the supply voltage to force the inductor Lb1 current into the load.
During Mode-II, for (Ts/2 < t < Ts): When T2 is on, the inductor Lb2 is con-
nected to the Vfc and inductor stores the energy during T2 on period (Ts/2 <
t < Ts). When the switch T1 is off during the period Ts/2 < t < Ts, the current
in Lb1 is forced to flow through the diodes D1, as shown in Figure 2.20(b).
+DC
+
D1 D2
IL1 RLb1 + Lb1 -

IFC
Io
Lb2 Rcf
+ IL2 RLb2 + -
Vo
Ro
VFC
Cf
T1 T2
-
-
-DC
(a)
+DC
D1 D2 +
IL1 RLb1 + Lb1 -

Ifc
Io
RLb2 + Lb2 Rcf
+ IL2 -
Vo
Ro
Vfc
Cf
-
T1 T2
-
-DC
(b)
Figure 2.20 Conduction equivalent circuit of MPIBC during switching cycle when: (a) T1
is ON; (b) T2 is ON.
1
T1on T1off
T1
0.5
0
1
T2off T2on
T2
0.5
0
178.541
Vfc (V)
178.5405
0.05 V
178.54
137.364
Ifc (A)
137.362
0.02 A
137.36
350.6
Vo (V)
0.1 V
350.4
66.8
Io (A)
66.75 0.05 A
66.7
0 Ts/2 Ts 3Ts/2 2Ts
Time (S)
Figure 2.21 Switching signals for T1,T2, fuel cell current & voltage, converter current
& voltage waveforms of MDBC.
As the inductor current tends to decrease, the voltage induced in the induc-
tor Lb1 is reversed to that shown in Figure 2.20(a). The voltage across the
load becomes vLb1 + Vfc, i.e., the voltage across the Lb1 adds to supply voltage
to force the inductor Lb1 current into the load.
The FC stack output voltage Vfc = Vin = 178.5 V and average output volt-
age Vout measured during simulation is 350.5 V, according to the converter
Vin 178
output voltage equation Vout = = = 356 V . As shown in
1 − (q × D ) 0.5
Figure 2.21, the output voltage Vout is 350.5 V, the remaining 5.5 V being the
voltage drop in ESR of inductors and switch and diode on-state resistance.
Whereas the voltags drop in parasitic conventional boost converter was
20.0 V and in MDBC 10.0 V, but in MPIBC it is 5.5 V and this is achievable
with reduced ripple current in MPIBC with interleaving technique. The
MPIBC has higher efficiency compared to the BC and MDBC because of
the reduced passive component losses.
2.6.3 Multi-Device Multi-Phase Interleaved Boost Converter

In multi-device multi-phase interleaved boost converters (MDPIBC),
the number of phases (p) is two and number of devices per phase (q) is
also two. Figure 2.22 illustrates the two-phase multi-device interleaved

boost converter topology integrated with a PEMFC stack. Where Lb1 and
Lb2 are boost inductors and RLb1 and Rlb2 are the ESRs of Lb1 and Lb2, respec-
tively. T1 and T2 are the IGBT switches connected in phase-I and T3 and T4
+DC
P=2
q=2 +
D1 D2 D3 D4
Lb1 Io
Ifc RLb1
Rcf Vo
Lb2 Ro
+ RLb2
PEMFC
Stacks in
series Vfc
Cf -
T1 T2 T3 T4
-
-DC
Figure 2.22 Multi-device multi-phase interleaved boost converter connected with

PEMFC stack.
1
T1on T1off
T1
0.5
0
1
0.5 T2on
T2
0
1
0.5 T3on
T3
0
1
0.5 T4on
T4
0
178.41
Vfc (V)
178.405
178.4
137.745
Ifc (A)
137.74
352.8
Io (A) Vo (V)
352.6
352.4
64.15
64.1
64.05
Ts/4 Ts/2 3Ts/4 Ts 5Ts/4 3Ts/2 7Ts/4 2Ts
Mode I Mode II Mode III Mode IV Time (Sec)
Figure 2.23 Voltage and current waveforms in different operating mode.

are the IGBT switches connected in phase-II, D1 and D2 are the diodes of
phase-I and D3 and D4 are diodes in phase-II, Cf is the output filter capac-
itor, Rcf is the ESR of output capacitor, p is the number of phases, and q is
the number of devices per phase. Figure 2.23 shows the different modes of
operation of the converter along with voltage and current waveforms at the
input and output.
During Mode–I, for (0 < t < Ts /4): In this mode, the switch T1 is on,
the inductor Lb1 is connected to the FC voltage Vfc, the inductor stores
the energy during the Ton period, and the supply current flows though
the path shown in Figure 2.24(a). The switches T2,T3 and T4 are turned
off, and the current in Lb2 is forced to flow through diodes D3 and D4, as
shown in Figure 2.24 (a). As the inductor Lb2 current tends to decrease,
the voltage induced in the inductor Lb2 is reversed to that of shown in
Figure 2.24(a). The voltage across the load vLb2 + Vfc, i.e., the voltage
across the Lb2, adds to the supply voltage to force the inductor Lb1 current
into the load.
During Mode–II, for (Ts/4 < t < Ts /2): In this mode, the switch T3 is on,
the inductor Lb2 is connected to the Vfc, the inductor stores the energy
during T3on period, and the current flow path is shown in Figure 2.24(b).
The other switches, T1,T2, and T4, are turned off and the current in Lb1 is
forced to flow through the diodes D1 and D2, as shown in Figure 2.24(b). As
the inductor current tends to decrease, the voltage induced in the inductor
Lb1 is reversed to that shown in Figure 2.24(b). The voltage across the load
vLb1 + Vfc, i.e., the voltage across the Lb1 adds to the supply voltage to force
the inductor Lb1 current into the load.
During Mode–III, for (Ts/2 < t < 3Ts /4): In this mode, the switch T2 is
turned on, the inductor Lb1 is connected to the FC voltage Vfc, the induc-
tor stores the energy during the Ton period, and the supply current flows
though the path, as shown in Figure 2.24(c). The switches T1,T3, and T4 are
turned off and the current in Lb2 is forced to flow through the diodes D3
and D4, as shown in Figure 2.24(c). As the current in inductor Lb2 tends to
decrease, the voltage induced in inductor Lb2 is reversed to that shown in
Figure 2.24(c). The voltage across the load vLb2 + Vfc, i.e., the voltage across
the Lb2, adds to the supply voltage to force the inductor Lb2 current into the
load.
During Mode – IV for (3Ts /4 < t > Ts): In this mode, the switch T4 is turned
on, the inductor Lb2 is connected to the Vfc, the inductor stores the energy
during T4on period, and the current flow path is shown in Figure 2.24(d).
The other switches, T1,T2, and T3, are turned off and the current in Lb1 is
forced to flow through diodes D1 and D2, as shown in Figure 2.24(d). As
+
D1 D2 D3 D4
Lb1 IO
Ifc RLb1 + -
Rcf VO
Lb2 RO
+ RLb2 + -
Cf -
Vfc
T1 T2 T3 T4
(a)
+
D1 D2 D3 D4
Lb1 IO
Ifc RLb1 + -
Rcf VO
Lb2 RO
+ RLb2 + -
Cf -
Vfc
T1 T2 T3 T4
(b)
+
D1 D2 D3 D4
Lb1 IO
Ifc RLb1 + -
Rcf VO
Lb2 RO
+ RLb2 + -
Cf -
Vfc
T1 T2 T3 T4
(c)
+
D1 D2 D3 D4
Lb1 IO
Ifc RLb1 + -
Rcf VO
Lb2 RO
+ RLb2 + -
Cf -
Vfc
T1 T2 T3 T4
(d)
Figure 2.24 Equivalent circuits of MDMPIBC for interval shown in Figure 2.23:
(a) Mode I; (b) Mode II; (c) Mode III; (d) Mode IV.
the inductor current tends to decrease, the voltage induced in inductor Lb1
is reversed to that shown in Figure 2.24 (d). The voltage across the load
vLb1 + Vfc, i.e., the voltage across the Lb1 adds to the supply voltage to force
the inductor Lb1 current into the load.
As shown in Figure 2.23, the FC stack output voltage Vfc = Vin = 178.4 V
and average output voltage Vout during simulation is 352.6 V, according
Vin 178
to converter output voltage equation Vout = = = 356.8 V . As
1 − (q × D ) 0.5
shown in Figure 2.23, the output voltage across load Vout is 352.6V, with the
remaining 4.2 V being the voltage dropped in the ESR of inductors and
switch and diode on state resistance. Whereas the voltage drop in parasitic
conventional boost converters is 20.0 V, in MDBC 10.0 V, and in MPIBC
5.5 V, in MDMPIBC it is 4.2 V and this is achievable with reduced rip-
ple current and multi-devices per phase along with interleaving operation.
The MDMPIBC have higher efficiencies compared to the BC, MDBC, and
MPIBC because of the reduced passive component losses. The steady state
current waveforms of the two phase multi device interleaved boost con-
verter at an FC current demand of 137.86 A (Vfc = 178.4V) is shown in
Figure 2.25.
137.8615
137.861
FC current (Amps)
137.8605
137.86
137.8595
137.859
ILb1
ILb2
74
Inductor currents ILb1 and ILb2 (Amps)
72
70
68
66
64
Ts/4 Ts/2 3Ts/4 Ts 5Ts/4 3Ts/2 7Ts/4 2Ts
Figure 2.25 Steady state current waveforms of two-phase multi-device interleaved boost
converter at FC current demand of 137.86 A (Vfc = 178.4V).
Table 2.2 Comparison among DC-DC boost converters for ripple reduction.
Parameter BC MDBC MPIBC MDMPIBC
Boost Inductor, Lb (µH), 750 375 375 187.5
Rb (mΩ) 68 34 34 17
Boost Capacitor Cf (µF) 550 275 320 160
Rcf (mΩ) 0.697 1.394 1.15 2.3
Input Voltage (V) 180.0 177.0 178.5 178.4
Output Voltage (V) 340.0 354.0 350.5 352.5
Voltage Lost in Parasitic 20.0 10.0 5.5 4.2
(V)
Duty Ratio (D) 0.5 0.25 0.5 0.25
No. of Phase (p), 1,1 1,2 2,1 2,2
No. of Devices per Phase
(q)
Effective ‘D’ (q×D) 0.5 0.5 0.5 0.5
Ripple Current pk-pk 4.8 4.5 0.02 0.002
Average FC Current 134 140.5 137.36 137.74
Steady State Ripple 3.58 3.20 0.014 0.00145
Current Percentage (%)
The comparison among the conventional and multi-phase DC-DC con-

verters is given in Table 2.2, from which it is apparent that the MDMPIBC
uses smaller values of components, has higher output voltage compared to
the other converters, and the current ripple in the FC current is the least
among them. Hence, the MDMPIBC is preferred over other converters
when used for high power applications.
2.7 The Proposed High Gain Multi-Device

Multi-Phase Interleaved Boost Converter
The commonly used single switch boost converters, when employed to get
high gain voltage, require the use of high duty ratio, but with extreme high
duty ratio the ripple current in the FC current increases and in addition,
the efficiency of the converter reduces due to increased conduction losses.
Another alternative to get high voltage gain is by employing cascaded boost
converters; these converters provide high voltage gain without the use of a
high duty ratio [24]. The strategy for switched capacitor/inductor and volt-
age lift techniques are additionally fit for furnishing high voltage gain and
with favorable circumstances incorporate a smaller size, lighter weight,
reduced cost, and reduced conduction losses. The disadvantages include
several diode/capacitor structures when a high voltage gain is required,
complex circuits, and for high power applications, the single switch may
suffer due to the high current of FC devices [25–27].
From the discussion about the disadvantages of using single switch
DC-DC boost converter topologies for high power DC-DC conversion, it
is evident that single switch topologies are not appropriate for high power
and high step up transformation. To carry large FC currents with reduced
ripple, interleaved control based switched capacitor cell boost converters
are preferred [28]. However, in these too, the voltage stresses of the power
devices remain high. A few other converter topologies based on inter-
leaved control with cross coupled inductors and diode capacitor cells are
presented for high step up gain in addition to high efficiency [29–37].
In this thesis, a high gain multi-device multi-phase interleaved boost
converter (HGMDMPIBC), as shown in Figure 2.26, is proposed to obtain
high voltage gain. The converter structure works on the principle of paral-
lel input and series output connection. The HGMDMPIBC boosts the FC
voltage four times with a smaller duty ratio of 0.25. The advantages of the
proposed converter are high voltage gain, low output voltage ripple, FC
current ripple, and low device stresses. In some applications, like traction
+DC
RC1
D1 D2 Io
PEMFC
Stack +
RL L
Ifc
C1
+ Ro Vo
RL L
Vfc
C2 -
-
T1 T2 T3 T4 RC2
Do
-DC
Figure 2.26 High gain multi-phase multi-device interleaved boost converter.

and transient bus systems, a DC link voltage of 750 V is required. These

voltages are possible with the proposed HGMDMPIBC, which is derived
from the MDMPIBC shown in Figure 2.22.
2.7.1 Operating Principle of HGMDMPIBC

The converter is derived from the multi-device boost converter and can be
divided in two parts, as shown in Figures 2.27 (a) and (b). The multi-device
boost converter is integrated with the other form of MDBC shown in 27
(b), in which the diodes are placed in a negative DC link rail. This forms
the parallel input and series output structure and it is named a high gain
multi-device multi-phase interleaved boost converter.
The proposed converter has several advantages:
1) Obtains the double the voltage gain as that of MDMPIBC

2) Lowers ripple in FC current and output voltage
+DC
RLb Lb
+
+DC
D1 D2
Lb
RLb
RCf RCf +
Ro Vo
Vin + R V
+ D2 Cf o o
T1 T2
Vin - -
Cf
D1
T1 T2
-DC
-DC
(a) (b)
+DC
RCf1
D1 D2 Io
Lb1 +
Ifc RLb1
Cf1
RLb2 Lb2 Ro Vo
Cf2 -
Vfc
T1 T2 T3 T4 RCf2
Do
-DC
(c)
Figure 2.27 Development of proposed converter from basic converters: (a) Multi-device
boost converter; (b) Output series multi-device boost converter; (c) Modified multi-
device multi-phase interleaved boost converter.
3) Reduces device stress as there are multiple devices per

phase
4) High voltage gain is achievable with smaller duty ratio
and hence the conduction losses are less, which results in
higher efficiency of the system.
Figure 2.28 shows the input/output voltage and current waveforms of

the converter under continuous conduction mode. The duty cycles of the
360°
switches are interleaved with a 900 phase shift (θ = ). The duty cycle of
the individual switches is D = 0.25. p×q
During mode – I, for (0 < t < Ts/4): In this mode, the switch T1 is on,
the inductor Lb1 is connected to the FC voltage Vfc and inductor stores the
energy during the Ton period and the supply current flows though the path
shown in Figure 2.29 (a). The switches T2, T3, and T4 are turned off, the
current in Lb2 flows through the Cf1 and Cf2, and as the inductor Lb2 current
tends to decrease, the voltage induced in the inductor Lb2 is reversed to that
of shown in Figure 2.29 (a). The voltage across the load vLb2+ Vfc = VCf1+VCf2,
1
0.5
T1
0
1
0.5
T2
0
1
0.5
T3
0
1
0.5
T4
0
180.5
180 0.5V
Vfc
179.5
136
134
Ifc
1.5A
132
750.5
750 0.2V
Vo
749.5
29.91
29.9 0.01A
Io
29.89
Mode-1 Mode-2 Mode-3 Mode-4
0 Ts/4 Ts 5Ts/4 3Ts/2 7Ts/4 2Ts
Ts/2 3Ts/4
Figure 2.28 Input and output waveforms of HGMDMPIBC.

+DC
(a)
RCf1
D1 D2 Io
Lb1 +
RLb1
Cf1
Lb2 Ro Vo
RLb2
Cf2 -
Vfc
T1 T2 T3 T4 RCf2
Do
-DC
(b) +DC
RCf1
D1 D2 Io
Lb1 +
RLb1
Cf1
Lb2 Ro Vo
RLb2
Cf2 -
Vfc
T1 T2 T3 T4 RCf2
Do
-DC
(c) +DC
RCf1
D1 D2 Io
Lb1 +
RLb1
Cf1
Lb2 Ro Vo
RLb2
Cf2 -
Vfc
T1 T2 T3 T4 RCf2
Do
-DC
(d) +DC
RCf1
D1 D2 Io
Lb1 +
RLb1
Cf1
Lb2 Ro Vo
RLb2
Cf2 -
Vfc
T1 T2 T3 T4 RCf2
Do
-DC
Figure 2.29 Operating intervals of proposed HGMDMPIBC: (a) Only T1 On; (b) Only T3
On; (c) Only T2 On; (d) Only T4 On.
i.e., the voltage across the Lb2, adds to the supply voltage to force the induc-
tor Lb2 current into the load.
During mode – II, for (Ts /4 < t < Ts /2):- In this mode, the switch T3 is
on, the inductor Lb2 is connected to the Vfc, and the inductor stores the
energy during T3 on period and the current flow path is shown in Figure
2.29 (b). The other alternate switches T1,T2, and T4 are turned off and the
current in Lb1 is forced to flow through diodes D1 and D2, as shown in Figure
2.29 (b). As the inductor current tends to decrease, the voltage induced in
inductor Lb1 is reversed to that shown in Figure 2.29 (b). The voltage across
load vLb1 + Vfc, i.e., the voltage across the inductor Lb,1 adds to the supply
voltage to force the current into the load inductor Lb1.
During mode – III, for (Ts /2 < t < 3Ts /4): In this mode, the switch T2 is
turned on, the inductor Lb1 is connected to the FC voltage Vfc, the induc-
tor stores the energy during the Ton period, and the supply current flows
though the path shown in Figure 2.29 (c). Switches T1, T3, and T4 are turned
400
356V
VT1
200
0
400
356V
VT2
200
0
500
394V
VT3
0
-500
500
394V
VT4
0
-500
50
0
Icf1
31.5A
-50
50
0 32 A
Icf2
-50
358
Vcf1
356
354
394
Vcf2
392
390
0 Mode-1 Mode-2 Mode-3 Mode-4 Ts 2Ts
Figure 2.30 Voltage stress in power switches, voltage, and current in capacitors Cf1 and
Cf2.
off and the current in Lb2 flow in Cf1 and Cf2 is shown in Figure 2.29 (c). As
the current in inductor Lb2 tends to decrease, the voltage induced in the
inductor Lb2 is reversed to that shown in Figure 2.29 (c). The voltage across
load vLb2 +Vfc, i.e., the voltage across the Lb2, adds to the supply voltage to
force the inductor Lb2 current into the load.
During mode – IV for (3Ts /4 < t < Ts): In this mode, switch T4 is turned on,
the inductor Lb2 is associated with the Vfc, the inductor stores the energy
amid T4 on period, and the current flow path is shown in Figure 2.29 (d).
Alternate switches T1,T2, and T3 are turned off and the current in Lb1 is
compelled to course through the diodes D1 and D2, as shown in Figure
2.29 (d). As the inductor current tends to diminish, the voltage affected in
inductor Lb1 is turned around to that shown in Figure 2.29 (d). The voltage
across the load is vLb1 +Vfc, i.e., the voltage across the Lb1 adds to the supply
voltage to drive the inductor Lb1 current into the load.
The device stress of the HGMDMPIBC is shown in Figure 2.30. The
voltage across the switch amid the turned off condition is around half of
the output voltage. Additionally, the current through and voltage across
the output capacitors Cf1 and Cf2 are also shown. The HGMDMPIBC can
have high voltage gain with less device stress and high efficiency.
2.8 Non-Inverting Buck-Boost Converters

for Low Voltage FC Applications
The FC sources are unregulated voltage sources and require power con-
verter devices to get a regulated output voltage. Figure 2.31 shows the
non-inverting buck-boost converter in which the boost converter is cas-
caded with the buck converter. These converters are used to regulate the
voltage from the unregulated FC voltage source. For example, the Horizon
RL2 L2
S2
G2 + Io
D1 Cd C2
RL1 L1 Vo
Ig D2
C1 + - Ro
vc1 R
Vg S1 d
-
G1
Figure 2.31 Schematic circuit diagram of non-inverting buck-boost converter.

FC model ECS-1000 has a voltage range variation of 45 V at no load and

28 V at full load. In order to get a regulated voltage of 36 V, the buck-boost
converters are integrated with the fuel cell stacks.
2.8.1 Single Switch Non-Inverting Buck-Boost Converter

The cascaded association of a conventional buck-boost converter is shown
in Figure 2.31. The converter works either in buck or boost mode depend-
ing upon the source voltage and the control method. If the source voltage
is less than the output voltage, the converter works in boost mode and if
the source voltage is higher than the output voltage, the converter works
in buck mode. Normally, the FC stack voltage varies from no load to full
load and, consequently, to get the steady output voltage required for a few
applications like, battery charging/discharging, portable applications etc.,
these buck-boost converters are used [38].
As shown in Figure 2.31, Vg is the average input voltage to converter, Ig
is average input current, L1 is the boost inductor, RL1 is the ESR of the boost
inductor, S1 is the boost switch, D1 is the boost side diode, C1 is the boost
side filer capacitor, Cd is the damping capacitor, Rd is the damping resistor,
S2 is the buck switch, D2 is the buck side diode, L2 is the buck inductor, RL2
is the ESR of the buck inductor, C2 is the output capacitor, and Ro is the
load resistor. When the circuit is operating under the boost mode, the buck
switch S2 is switched continually with duty cycle D = 1 and boost switch S1
is operated in pulse width modulation (PWM). Under the buck operation
mode, the boost switch S1 is turned off with D = 0 and S2 is operated in
PWM. The S1 and S2 are controlled to get the required voltage at the output
of the converter.
The equivalent circuits of the buck and boost operating modes are illus-
trated in Figure 2.32 (a) and (b) respectively. A PEMFC stack of ECS-1000
is considered as the input power source for the converter. The no load volt-
age of the stack is 45 V and at load 28 V, whereas the required output volt-
age of the converter is 36 V. When the FC voltage is at 28 V, the buck boost
converter operates as shown in Figure 2.32 (a). The switch S1 is operated
with D = 0.11 to get 36 V at the output and S2 in boost mode is shown as
short circuited due to the full conduction of it with 100% duty cycle. The
current and voltage waveforms under boost operation are shown in Figure
2.33. When the FC voltage is at 45 V, the buck boost converter operates as
shown in Figure 2.32 (b). The switch S2 is operated with D = 0.11 to get
36 V at the output and S1 is turned off with the 0% duty cycle. The typical
current and voltage waveforms under buck operation of the converter are
shown in Figure 2.33.
RL2 L2
D1 Cd Io
C2 +
Ig RL1 L1 Vo
C1 +
- Ro
Vc1
Vg Rd
S1 -
G1
(a)
Ig RL1 L1 RL2 L2
S2
G2 Io
Vg Cd +
C1 + C2 Vo
Vc1 D2 Ro
- -
Rd
(b)
Figure 2.32 Equivalent circuit of buck-boost converter: (a) Boost mode; (b) Buck mode.
1 VGS
0.5
0
0.065 0.065 0.065 0.065 0.065 0.0651
10.5
IL1
10
0.065 0.065 0.065 0.065 0.065 0.0651
7.505
IL2
7.5
7.495
0.065 0.065 0.065 0.065 0.065 0.0651
7.5
Io
7.5
7.4999
0.065 0.065 0.065 0.065 0.065 0.0651
36.0001
Vo
36
35.9999
0.065 0.065 0.065 0.065 0.065 0.0651
37
Vc1
36.8
36.6
0.065 0.065 0.065 0.065 0.065 0.0651
Ts 2Ts 3Ts
Figure 2.33 Voltage and current waveforms of buck-boost converter operated in boost mode.
Table 2.3 Passive component values applied for buck-boost converter.

Component Value
Boost Inductor L1 in µH 320
Internal Resistance of L1 in mΩ 26
Buck Inductor L2 in µH 240
Boost Capacitor C1 in µF 94
Buck Capacitor C2 in µF 94
Damping Resistor Cd in µF 940
Damping Resistor Rd in Ω 0.5
1
VGS2
0.5
0
0.065 0.065 0.065 0.065 0.065 0.0651
6.576
IL1
6.574
6.572
0.065 0.065 0.065 0.065 0.065 0.0651
8
IL2
7.5
7
0.065 0.065 0.065 0.065 0.065 0.0651
7.502
Io
7.5
7.498
0.065 0.065 0.065 0.065 0.065 0.0651
36.01 Vo
36
35.99
0.065 0.065 0.065 0.065 0.065 0.0651
44.2
Vc1
44
43.8
0.065 0.065 0.065 0.065 0.065 0.0651
Ts 2Ts 3Ts
Figure 2.34 Voltage and current waveforms of buck-boost converter operated in buck
mode.
From Figure 2.33, it can be observed that the FC ripple current is 0.52
A, whereas the mean FC current is 10.25 A and the ripple percentage is 5%,
which is acceptable for satisfactory operation of FC devices, but the passive
component values used for these converters are high. The passive compo-
nent values used in the simulation are given in Table 2.3. The load current
and voltages are 7.5 A and 36 V, respectively. The ripple in boost capacitor
C1 is observed as 0.4 V with a value of 94 µF.
From Figure 2.34, it is observed that the FC current ripple is approxi-
mately 0.02. Due to the buck operation, the ripples are mainly presenting
in the output inductor L2. In buck mode, the S2 is operating with a duty
cycle of 0.81 to get 36 V at the output side. The boost capacitor voltage is
equal to the input voltage 45 V, as switch S1 is opened. However, the size
of the passive components can be reduced by employing the interleaved
buck-boost converter.
2.8.2 Interleaved Buck-Boost Converter

The conventional type of buck-boost converter, when associated with FC
devices for voltage regulation, has certain drawbacks such as high input/
output current ripple, high noise level, complicated control system, current
limitation, and less system efficiency [39–41]. An interleaving technique is
applied to have several benefits such as low ripple current, high efficiency,
low component stress, high power density, and better thermal property
[42–44]. Figure 2.35 represents the two phase non-inverting interleaved
buck boost converter (IBBC) in which the interleaved boost converter is
IL21 RL21 L21

S3
G3 IL22 RL22 L22
S4
D1 D2 G4 Io
Cd
IL11 RL11 L11
Ig C1 +
VC1 + Vo
IL12 RL12 L12
- Rd D3 D4 C2
- Ro
S1 S2
Vg G1 G2
Figure 2.35 Schematic circuit diagram of interleaved buck-boost converter.

cascaded with an interleaved buck converter to operate it as a voltage reg-

ulation device.
In IBBC, the number of phases is two and the number of devices per
phase is one on both the buck and boost side of the converter. This con-
verter can work either in buck or boost depending on the supply voltage
extent. The circuit when working under boost and buck modes are shown
in Figures 2.36 (a) and (b), respectively. In boost mode of operation,
switches S1 and S2 are operated in PWM, whereas the buck switches S3 and
S4 are persistently on with the unity duty cycle. In buck operation mode,
buck switches S3 and S4 are worked in PWM, whereas the boost switches S1
and S2 are turned off with the zero duty cycle.
With the end goal of examining the steady state waveforms, the IBBC is
interfaced with a PEMFC power source whose terminal voltage at no load
is 45 V and 28 V at full load, whereas the required converter output volt-
age is 36 V. The selected duty cycles for boost switches are D1 = D2 = 0.11
IL21 RL21 L21
IL22 RL22 L22
D1 D2 Cd Io
IL11 RL11 L11 +
C2 Vo Ro
Ig C1 + V -
IL12 RL12 L12 C1
- Rd
S1 S2
Vg
G1 G2
(a)
IL21 RL21 L21
S3
G3
IL11 RL11 L11 IL22 RL22 L22
Ig IL12 RL12 S4
L12
G4 Io
+
Cd C2
D3 Vo
C1 + D4 -
VC1 Ro
Vg
-
Rd
(b)
Figure 2.36 Equivalent circuit diagrams of IBBC: (a) Boost mode; (b) Buck mode.
1 VGS1
0.5
0
0.065 0.065 0.065 0.065 0.065 0.0651
1 VGS2
0.5
0
0.065 0.065 0.065 0.065 0.065 0.0651
11 Ig
10
9
0.065 0.065 0.065 0.065 0.065 0.0651
6 IL11
5
4
0.065 0.065 0.065 0.065 0.065 0.0651
6
IL12
5
4
0.065 0.065 0.065 0.065 0.065 0.0651
7.505
Io
7.5
7.495
0.065 0.065 0.065 0.065 0.065 0.0651
3.755
IL21
3.75
3.745
0.065 0.065 0.065 0.065 0.065 0.0651
3.755
IL22
3.75
3.745
0.065 0.065 0.065 0.065 0.065 0.0651
36.0001
Vo
36
35.9999
0.065 0.065 0.065 0.065 0.065 0.0651
37.2
VC1
37
36.8
0.065 0.065 0.065 0.065 0.065 0.0651
Ts 2Ts 3Ts
Figure 2.37 Steady state voltage and current waveforms of IBBC in boost mode for
Vg= 45V.
1
VGS3
0.5
0
0.065 0.065 0.065 0.065 0.065 0.0651
1
VGS4
0.5
0
0.065 0.065 0.065 0.065 0.065 0.0651
6.546
Ig=6.544A
6.544
6.542
0.065 0.065 0.065 0.065 0.065 0.0651
3.273
IL11=3.272A
3.272
3.271
0.065 0.065 0.065 0.065 0.065 0.0651
3.273
IL12=3.272A
3.272
3.271
0.065 0.065 0.065 0.065 0.065 0.0651
8
7.5
Io=7.5A
7
0.065 0.065 0.065 0.065 0.065 0.0651
5
IL21=3.8A
4
3
0.065 0.065 0.065 0.065 0.065 0.0651
5
IL22=3.7A
4
3
0.065 0.065 0.065 0.065 0.065 0.0651
36.01 Vo=36V
36
35.99
0.065 0.065 0.065 0.065 0.065 0.0651

44.4
VC1=44.15V
44.2
44
0.065 0.065 0.065 0.065 0.065 0.0651
Ts 2Ts 3Ts
Figure 2.38 Steady state voltage and current waveforms of IBBC in buck mode for
Vg = 45V.
for Vg = 28 V and for buck switches, the duty cycles are D3 = D4 = 0.81 for
Vg = 45 V. The steady state voltage and current waveforms in boost and
buck mode are shown in Figures 2.37 and 2.38.
The passive component parameter values used as a part of the simu-
lation study are shown in Table 2.4. The parameter qualities are reduced
considerably as that of the parameters used in the conventional buck boost
converter. This is possible by interleaving the procedure of operation and
this operation makes the effective inductor current frequency (100 kHz)
twofold of the switching frequency, ‘fs ’ (50 kHz). As it can be seen, the size
of the LC component is inversely proportional to the switching frequency.
Further, FC ripple current is 0.5 A with the reduced passive component
values. The ripple in boost capacitor voltage is limited to 0.4 V.
The IBBC works in buck mode when the supply voltage lies in the extent
36 V to 45 V. For example, the simulation has been carried for the Vg = 45 V
and operating duty cycles for switches S3 and S4 are 0.81. During this mode,
the boost switches are turned off forever. Figure 2.44 demonstrates the
steady state voltage and current waveforms of IBBC in buck mode of oper-
ation with Vg = 45 V. The FC ripple current is smaller because of the buck
operation, whereas the ripple in the output current is 0.75 A. Because of
the smaller size of inductance employed for buck inductors, likewise the
ripple in boost capacitor voltage is limited to 0.15 V.
Table 2.4 Passive component values for IBBC.

Component Value
Boost Inductor L1 in µH 160
Buck Inductor L2 in µH 120
Boost Capacitor C1 in µF 47
Buck Capacitor C2 in µF 68
Damping Resistor Cd in µF 470
Damping Resistor Rd in Ω 2.2
2.9 Proposed Multi-Device Buck-Boost Converter

A multi-device buck-boost converter (MDBBC), as shown in Figure 2.39,
is proposed in this thesis work and in this converter, the number of phases
‘p’ is one and the number of devices per phase ‘q’ are two. By paralleling
the device per phase, the effective inductor current frequency is doubled
to the switching frequency. The MDBBC operates either in boost or buck
mode, depending on the supply voltage extent. For the converter operated
in boost mode, the boost switches are operated in PWM mode and buck
switches are turned permanently with the unity duty cycles of the buck
switches. In buck operating condition, the buck switches are operated in
PWM and boost switches are turned off permanently with zero duty cycle.
The proposed MDBBC is analyzed through computer simulations and
the passive component parameters used in the circuit are the same as that
of the IBBC shown in Table 2.5. The respective results in both buck and
boost mode are presented in Figure 2.40. The converter is fed with an input
voltage of 28 V for boost mode and 45 V during buck mode. The FC rip-
ple current is only 0.4 A during the buck and boost operating condition,
whereas in IBBC, it was 0.5 A with the same passive component parame-
ters. Also, the MDBBC has higher efficiency compared to the IBBC and
BBCs.
S3
G3
RL2 L2
S4
D1 D2 G4 Io
Cd
C2 +V
o
L1 C1 + D3 D4
IL1 or Ig RL1 - Ro
VC1
-
Rd
S1 S2
Vg G2
G1
Figure 2.39 Proposed multi-device buck-boost converter for portable FC application.

10.4
IL1 (Amps)
10.2
10 0.4 A
9.8
0.035 0.035 0.035 0.035 0.035 0.0351

7.5002
Io (Amps)
7.5002 1mA
7.5001
0.035 0.035 0.035 0.035 0.035 0.0351
36.0011
Vo (Volts)
36.001 1mV
36.0009
0.035 0.035 0.035 0.035 0.035 0.0351
Vc1 (Volts)
36.2
0.35V
36
35.8
0.035 0.035 0.035 0.035 0.035 0.0351
Time (Secs)
(a)
7.8
IL2 (Amps)
7.6
0.4A
7.4
7.2
0.035 0.035 0.035 0.035 0.035 0.0351
7.502
Io (Amps)
7.5 0.02A
7.498
0.035 0.035 0.035 0.035 0.035 0.0351
Vo (Volts)
36.01
36 0.01V
35.99
0.035 0.035 0.035 0.035 0.035 0.0351

44.2
Vc1 (Volts)
44.1 0.2V
44
0.035 0.035 0.035 0.035 0.035 0.0351
Time (Sec)
(b)
Figure 2.40 Steady-state voltage and current waveforms of MDBBC: (a) In boost mode
for Vg = 28 V; (b) In buck mode for Vg = 45 V.
2.10 The Proposed Multi-Device Multi-Phase

Interleaved Buck-Boost Converter
In multi-device multi-phase interleaved buck boost converters
(MDMPIBBC), as shown in Figure 2.41, the number of phases and devices
per phase are two (p = q = 2), whereas on the buck side p = 2 and q = 1. The
advantage of connecting multiple devices per phase was already discussed
in the previous sections. Here, in this converter, the FC ripple current
is further reduced due to the multiple devices per phase and the passive
component parameters get reduced to half that of IBBC and the proposed
MDBBC and is reduced to four times that of BBC. Due to the reduced
components size, the system becomes lighter in weight and occupies
smaller area and the device selection also becomes easier as the lower rat-
ing devices can be used as current flow through them is decreased.
With the end goal of comparing the proposed MDMPIBC with BBC,
IBBC, and MDBBCs, the converter is simulated by connected a PEMFC
stack of voltage range 28 V at full load and 45 V at no load. The converter
is fed with 28 V during the boost mode and 45 V during buck mode for
a requirement of output voltage Vo = 36 V for battery charging applica-
tions. In boost operating mode, the switches S1, S2, S3, and S4 are oper-
ated in PWM and buck switches S5 and S6 are turned on permanently with
unity duty cycles. The suitable duty cycle required for boost switches to get
36 V at the output is 0.055. In buck operating mode, the boost switches
are turned off permanently and buck switches are operated in PWM. The
suitable duty cycle required for buck switches to get 36 V at the output is
0.81. The steady state voltage and current waveforms during the boost and
buck modes are delineated in Figures 2.42 and 2.43.
RL2 L2
S5
G5 RL2 L2
S6
D1 D2 D3 D4
Cd G6
IL11 RL11 L11
+ Io
C1 + D5 C2 Vo
IL12 RL12 L12 D6 -
Vc1
Ig -
Ro
S1 S2 S3 S4
Rd
Vg G1 G2 G3 G4
Figure 2.41 Proposed multi-device multi-phase interleaved buck-boost converter for FC

low voltage applications.
1
VGS1
0.5
0
0.065 0.065 0.065 0.065 0.065 0.0651
1
VGS2
0.5
0
0.065 0.065 0.065 0.065 0.065 0.0651
1
VGS3
0.5
0
0.065 0.065 0.065 0.065 0.065 0.0651
1
VGS4
0.5
0
0.065 0.065 0.065 0.065 0.065 0.0651
10.5 Ig=10.25A
10
0.065 0.065 0.065 0.065 0.065 0.0651
5.8
5.6
IL1=5.4A
5.4
5.2
5
0.065 0.065 0.065 0.065 0.065 0.0651
5.4
5.2
IL2=4.85A
5
4.8
4.6
4.4
0.065 0.065 0.065 0.065 0.065 0.0651
7.505
Io=7.5A
7.5
7.495
0.065 0.065 0.065 0.065 0.065 0.0651
3.755
IL21=3.75A
3.75
3.745
0.065 0.065 0.065 0.065 0.065 0.0651
3.755
IL21=3.75A
3.75
3.745
0.065 0.065 0.065 0.065 0.065 0.0651
36.0002
Vo=36V
36
35.9998
0.065 0.065 0.065 0.065 0.065 0.0651
37.2
VC1=37V
37
36.8
0.065 0.065 0.065 0.065 0.065 0.0651
Ts 2Ts 3Ts
Figure 2.42 Steady-state voltage and current waveforms of MDMPIBBC in boost

operating for Vg = 28 V.
1
VGS3
0.5
0
0.065 0.065 0.065 0.065 0.065 0.0651
1
VGS4
0.5
0
0.065 0.065 0.065 0.065 0.065 0.0651
6.546
Ig=6.544A
6.544
6.542
0.065 0.065 0.065 0.065 0.065 0.0651
3.273
IL11=3.272A
3.272
3.271
0.065 0.065 0.065 0.065 0.065 0.0651
3.273
IL12=3.272A
3.272
3.271
0.065 0.065 0.065 0.065 0.065 0.0651
8
7.5
Io=7.5A
7
0.065 0.065 0.065 0.065 0.065 0.0651
5
IL21=3.8A
4
3
0.065 0.065 0.065 0.065 0.065 0.0651
5
IL22=3.7A
4
3
0.065 0.065 0.065 0.065 0.065 0.0651
36.01
Vo=36V
36
35.99
0.065 0.065 0.065 0.065 0.065 0.0651

44.4
VC1=44.15V
44.2
44
0.065 0.065 0.065 0.065 0.065 0.0651
Ts 2Ts 3Ts
Figure 2.43 Steady-state voltage and current waveforms of MDMPIBBC in buck

operating for Vg = 45 V.
Table 2.5 Passive component values for MDMPIBBC.

Component Value
Boost Inductor L1 (µH) 80
Internal Resistance of L1 (mΩ) 6.5
Buck Inductor L2 (µH) 60
Internal Resistance of L2 (mΩ) 5
Boost Capacitor C1 (µF) 23
Buck Capacitor C2 (µF) 34
Damping Resistor Cd (µF) 230
Damping Resistor Rd (Ω) 4.2
As shown in Figure 2.42, the converter switching gate pulses are phase
shifted by 90°, which is selected according to the expression (360/(p×q)),
where p = q = 2 and the phase shifting angle comes to be 90°. The FC ripple
current drawn with MDMPIBBC is 0.5 A for the halved passive compo-
nent parameters which is used for IBBC and MDBBCs. The LC compo-
nents used in MDMPIBBC are presented in Table 2.5. The ripple in boost
capacitor is limited to 0.3 V (0.8 %).
2.11 Converter Configurations for Integrating FC

with 400 V Grid Voltages
To interface a FC stack with a 400 V grid, certain configurations must be
used. Because a single FC stack cannot generate such high DC link voltage,
to get the three phase 400 VL-L voltage at the output of 3-phase inverter, a
DC link voltage of around 625 V is required. Various configurations have
been suggested in the next section to achieve this.
2.11.1 Series Configuration

In the series configuration, appropriate numbers of FC stack with lower rat-
ings are connected in series. By connecting the stacks in series, the required
voltage is generated for input of the DC-DC converter. The DC-DC con-
verter boosts the FC stack voltage to the required DC link voltage, which is
shown in Figure 2.44. In this configuration, the DC link voltage of 625 V is
generated with the help of MDMPIBC converter with a duty cycle of 0.25.
Initially, considering the Ballard FC model 1120ECS, whose output voltage
is 45 V at full load and 65 V at no load, such FC stacks can be connected
in series to get the appropriate voltage levels to feed a DC-DC converter.
Seven FC stacks of rating 45 V are taken to get 325 V as input voltage to
the MDMPIBC, which can amplify it to 625 V with a voltage gain of two.
The steady state voltage and current waveforms of FC voltage and DC link
voltages are depicted in Figure 2.45. The advantage of this configuration
PEMFC Vdc
stack 1 + -
PEMFC + DC link
stack 2
PEMFC
stack 3
PEMFC 325 V + 3-phase

stack 4 Three phase 400 V,
625V
inverter 50Hz AC
- supply
PEMFC
stack 5
-
PEMFC DC-DC 3-phase
stack 6 625V Three phase 400 V,
converter inverter 50Hz AC
supply
PEMFC
stack 7
Figure 2.44 DC series configuration for obtaining DC link voltage for three phase 400 V,
50 Hz inverter.
700
600
500 625V
325V
Voltage (V)
400
300
200 FC output voltage

DC link voltage
100
0
0 0.02 0.04 0.06 0.08 0.1
Time (Sec)
Figure 2.45 Steady-state FC voltage and DC link voltages in DC series configuration.

is that smaller rated FC units may be connected in series and only one
DC-DC power converter is necessary. The main disadvantages are faced
during the outage of any single FC unit which affects the complete system
and thus has lower reliability.
2.11.2 DC-Distributed Configuration

In a DC distributed configuration, each FC module is associated with a cor-
responding DC-DC converter to obtain the DC link voltage for the input
of a. three phase inverter, as shown in Figure 2.46. In this configuration, the
FC module consists of several stacks in series to get the appropriate voltage
level. Each FC module contains seven FC stacks of 45 V rating and the
total module voltage comes out to be 325 V and this voltage is given as the
input for the MDMPIBC for getting the DC link voltage of 625 V shown in
Figure 2.47. The converter operates at duty cycle 0.25 to obtain the DC link
voltage of 625 V. The lesser value of duty cycle ensures a smaller ripple in
FC current and high efficiency of the DC-DC converter.
The reliability which is affected in the series configuration is solved by
using this configuration, as during the outage of any FC module during
maintenance and replacement, the other FC modules can supply power
continuously without disturbing the system function. The additional
advantage is that several inverters can be fed with the same DC bus and
DC Distribution
+ -
FC +
DC-DC +
Module 325V Converter 625 V
- -
FC + DC-DC +
Module 325V Converter 625 V
- -
+ DC-DC +
FC
325V Converter 625 V
Module
- -
+
FC + DC-DC
325V 625 V
Module Converter 3-phase
- - + Three phase 400 V,
625 V inverter 50Hz AC
- supply
+ 3-phase
FC + + Three phase
DC-DC 400 V,
325V 625 V 625 V inverter
Module Converter 50Hz AC
- -
- supply
Figure 2.46 DC distributed configuration for obtaining DC link voltage for multiple
three phase inverters.
700
600 625V
500
Voltage (V)
400 325V
300
200 FC output voltage

DC link voltage
100
0
0 0.02 0.04 0.06 0.08 0.1
Time (Sec)
Figure 2.47 Steady-state FC voltage and DC link voltages in DC distributed configuration.
share the AC load. The disadvantage is that when the output voltage of the
DC-DC converters are not equal, circulating currents are developed which
interfere with the operation of the system and there is a higher device count
in this configuration compared to the series configuration.
2.12 Conclusions
Several DC-DC converter topologies suitable for PEMFC stacks have been
discussed and the different DC-DC boost and buck-boost converter topol-
ogies have been classified based on the operation. The DC-DC converter
performances have been analyzed by considering an input source PEMFC
stack of 24 kW, 180 V rating. Furthermore, the advantages of multi-device
and multi-phase converter topologies in boost and buck-boost mode are
clearly emphasized with respect to the parameters like FC ripple current,
device count, LC parameters size, and the voltage gain. It has been shown
that the FC current ripple is decreased to a very small value by operat-
ing the boost converter with multi-device multi-phase topology named
MDMPIBC, also the LC component parameters were smallest for this
topology. A DC-DC converter called HGMDMPIBC has been proposed
and its steady state performance has been presented with the various
waveforms. The proposed converter is capable of boosting up to four times
the input voltage with the smaller duty cycle of 0.25. The input voltage
fed to the converter is 180 V and 750 V was obtained, which is 2 times
higher than the MDMPIBC case. Several buck boost converter topologies
for low voltage applications have been analyzed in steady state operation.
The proposed converter topologies called MDBBC and MDMPIBBC are

briefly described with the steady state voltage and current waveforms.
Additionally, the converter configurations for interfacing the FC source
with 400 V AC grid systems are suggested and their advantages and
disadvantages during the integration have been discussed.
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3
High Gain DC-DC Converters
for Photovoltaic Applications
M. Prabhakar* and B. Sri Revathi
School of Electrical Engineering (SELECT), Vellore Institute of Technology,

Chennai, India
Abstract
In this chapter, the synthesis, design and experimental details of some high gain
DC-DC converter topologies are discussed. The chapter begins by exploring the
high gain requirements, drawbacks of the classical boost converter and some
gain extension methods. The detailed method of combining various gain exten-
sion techniques to synthesise some high gain DC-DC converter topologies are
described. The elements used in the converters are designed using basic prin-
ciples that govern the proper operation of all power converters. Experimental
results along with the key inferences are elaborated to validate and appreciate the
adopted synthesis methodology. Finally, the converters discussed in this chapter
are compared among themselves and the concluding remarks are summarised.
Keywords: DC-DC power converter, power conversion, distributed energy

sources, high voltage gain, interleaved boost converter, coupled inductor, voltage
multiplier cell
3.1 Introduction
Recently, due to rapid depletion of fossil fuels and issues concerning
environmental pollution, green energy sources like photovoltaic (PV)
cells are being used proficiently for electrical energy conversion. The
twin challenges of meeting the present-day electrical energy demand
while causing the least damages to the environment are both massive
71
and contradictory. Distributed renewable energy resources (DRER) lend

a great helping hand to confront this situation besides being environ-
ment friendly [1, 2]. Hence, among energy conscious planners, there is a
significant inclination to efficiently convert and utilise electrical energy
from never exhausting, secure, and non-polluting energy resources like
solar, wind, etc. [3–5].
Globally, solar PV has an installed capacity of 630GW [6]. With partic-
ular reference to Indian context, the potential capacity of solar PV is of the
order of 750GW, while the installed capacity amounts to only 34.6GW [7].
The huge gap between the potential and installed capacities is one of the
motivations to carry out this research work in a flourishing field.
Generally, photovoltaic (PV) panels yield low voltage across their output
terminals; the typical voltage ratings lie in the range of 12V to 60V DC. On
most occasions, their voltage magnitude is insufficient to directly supply
the loads which require about 110V or 230V and the majority of the loads
operate from AC supply. The customary practice of interfacing the load
with the PV panel(s) is through an inverter and transformer combination
which provides the necessary voltage gain besides matching the electrical
energy form.
For systems with larger power ratings that range from a few kilowatts
(kWs) to megawatts (MWs), a common practice is to connect many pan-
els in series to meet the load voltage magnitude. The power level is also
increased as many panels are put to use. However, during partial-shading
and fault condition, the net system voltage (and power level) drops dras-
tically. Parallel connection of PV panels definitely comes to the rescue as
far as higher power levels (in the range of few kWs to few MWs) are con-
cerned. Nevertheless, from a system view point, the voltage level remains
the same as the chosen panels’ voltage rating. Unfortunately, parallel-
connected PV configuration fails to meet the high voltage required at the
load end.
Power electronic converters play a significant role in the PV-load inter-
face. The converters aid in efficiently and easily meeting the electrical
energy requirement of the load both in terms of voltage gain and form (AC
and DC). Considering the tremendous technical and commercial scope
that is available for attaining the required standardization levels, a few high
gain DC-DC converters are explored in this chapter.
3.1.1 Role of DC-DC Converter in Renewable Energy System

The standard DC voltage is about 380V [8] to suit the input of the full
bridge inverter in the single phase 230V AC grid-connected power systems.
High Gain DC-DC Converters for PV Applns. 73
For DC distribution, a DC voltage level of 1.1kV is preferred [9]. Thus,

the need for an efficient high gain DC-DC converter to act as an interface
between the loads and PV input is reiterated.
In order to obtain 230V AC from an inverter, a DC bus voltage of 380V
is required. To obtain the DC link voltage, conventionally, series connected
PV panels are employed, as shown in Figure 3.1(a).
However, in the case of series connected PV arrays, due to module
mismatch and partial shading conditions, the generated power output
drastically decreases. To overcome these problems, a high-performance
utility interactive PV generation system with a Generation Control
Circuit (GCC) is applied. However, due to the use of numerous power
devices, the cost becomes prohibitive and dissuades the users from
employing such systems. The parallel connected PV configuration shown
in Figure 3.1(b) is more efficient than the series connected configuration
due to the possibility of tracking the maximum power point (MPP) of
individual PV panels.
Figure 3.1(c) shows the schematic arrangement of a grid connected PV
fed system in which the individual parallel connected PV panels operate at
maximum power points through an appropriate MPP tracking algorithm.
Generally, a Power Conditioning System (PCS) is required to signifi-
cantly step up the voltage level obtained from the parallel connected PV
Solar PV Panel 1ф Grid

1ф Inverter
(Series Connected)
(a)
Solar PV Panel
(Parallel Connected)
(0-60V) 3ф Inverter Large 3ф Grid
Transformer
(b)
Solar PV Panel
(Parallel Connected)
3ф Inverter Large 3ф Grid
(0-60V) MPPT 1 DC-DC Conv. 1 Transformer
MPPT 2 DC-DC Conv. 2
DC-DC Conv. 3
MPPT 3
(c)
Figure 3.1 Conventional grid connected PV systems.

configuration before connecting to the load [10]. Thus, high step-up DC-DC
converters are usually used at the front-end, as shown in Figure 3.2(a).
In the system shown in Figure 3.2(a), employment of a high step-up
DC-DC converter reduces the size of the power transformer and the over-
all system cost [11]. The high gain DC-DC converters are broadly classi-
fied as isolated (with transformer) and non-isolated (without transformer)
converters.
The isolated DC-DC converters in Figure 3.2(a) employ a transformer
whose turns ratio is suitably designed to meet the required gain. In these
converters, the main switches suffer from high voltage spikes and con-
sequently, higher switching power loss due to leakage inductance of the
transformer. The non-isolated DC-DC converters in Figure 3.2(b) do not
require transformers and are capable of achieving high gains using passive
components itself.
Solar PV Panel
(Parallel Connected) High Gain
(0-60V) DC-DC 3ф Inverter 3ф Grid
Converter
With Transformer
(Isolated)
PCS
(a)
3ф Inverter 3ф Grid
Solar PV Panel
(Parallel Connected) High Gain
(0-60V) DC-DC DC Distribution
Converter Lines (1.1kV,
Without Transformer 2.2kV etc.,)
(Non-Isolated)
PCS
(b)
Figure 3.2 Grid tied PV systems with high gain DC-DC converter.
Therefore, non-isolated high step-up DC-DC converters are compact,

more efficient, and best suited for PV fed applications.
3.1.2 Classical Boost Converter (CBC)

Figures 3.3(a) and 3.3(b) show the power circuit diagram of a CBC and
a photograph of a prototype converter. The basic operating principle of
a CBC is elaborated in [12, 13]. The voltage gain (M) of a CBC is derived
from the volt-second balance principle and given by:
Vo 1 (3.1)
M= =
Vin 1 − D
where D is duty ratio of the switch. The prototype version of a 24V/48V,

48W, 50kHz boost converter is fabricated by designing the inductor (L)
considering operation under continuous conduction mode (CCM). The
experimental results obtained from the prototype converter are presented
to appreciate the voltage gain capability. From Figure 3.3(c), the voltage
gain obtained from the prototype converter is observed. When the switch
operates at a duty ratio of D=0.5, an output voltage of 46.9V is obtained.
The negligible difference between the expected value (48V) and the actual
value is attributed to the voltage drop across the stray resistance of the
inductance and diode.
To achieve a higher voltage gain of M=5 and higher values, the switch
should be operated at a duty ratio of D=0.8 (for M=5) and D>0.8 (for
higher values of M). To comprehend the problems of operating the switch
at extreme duty ratios (D>0.8), especially at high switching frequencies
(say f=50kHz), the same prototype converter (shown in Figure 3.3(b))
was operated at D=0.82. The experimental results obtained at D=0.82 and
depicted in Figure 3.3(d) clearly show that the power converter is not capa-
ble of providing the expected output voltage (M>5).
While the switch remains turned ON for 82% of the total time period
(T), energy is stored in the inductor. Energy transfer from inductor to
capacitor occurs through the diode as long as the switch is turned OFF
(18% of T). At extreme duty ratios, the available duration for energy trans-
fer (from L to C) is short. Resultantly, only a fraction of energy transfer
occurs, leading to reduced output voltage. Moreover, as energy transfer is
insufficient, power transferred to the load also reduces.
D
L
IDiode
ISwitch Output
Input
C
L1
D1 S
+
Vin + L
O
- S1 A Vo
C1 D
-
(a) (b)
(c) (d)
Figure 3.3 (a) Power circuit diagram of classical boost converter (CBC). (b) Photograph
of experimented CBC, (c) Experimental results of CBC at D=0.5, CH1: input
voltage, CH2: gate pulse, CH3: voltage across the switch, and CH4: output voltage,
(d) Experimental results of CBC at D=0.82, CH1: input voltage, CH2: voltage across the
switch, CH3: current through the switch, and CH4: current through the diode.
The switch conducts for a longer duration and results in excessive power
loss. Further, only a small duration is available to completely turn ON the
fast-recovery power diode. Consequently, both the switch and the diode
conduct simultaneously. This results in an incremental voltage drop and
power loss. Thus, operating the CBC at extreme duty ratios of D>0.8 is not
preferred to obtain high voltage conversion ratios.
Besides the problem of extreme duty ratios, the input current ripple in
a CBC is quite high, even at safe duty ratio values. In Figure 3.4, channel
2 (CH2) shows the input current waveform captured using digital storage
oscilloscope (DSO) when the prototype CBC was tested at D=0.5. Generally,
a smooth input current (or ripple-free input current) is preferred for PV
Tek Trig’d M Pos: 0.000s MEASURE

CH1
1 Pos Width
10.38µs
CH2
Mean
4.40A
CH2
Pk–Pk
1.04A
2
3 CH3
Pk–Pk
5.60A
CH4
4 Pk–Pk
84.0V
CH1 50.0V CH2 2.00V M 5.00µs CH1/867mV
CH3 5.00A CH4 50.0A 13–Jan–16 16:57 50.4308kHz
Figure 3.4 Experimental results obtained from prototype CBC to demonstrate input
current ripple, CH1: gate pulse, CH2: input current, CH3: current through the switch,
and CH4: voltage across the switch.
application. Therefore, in the subsequent sections, methods to enhance the

voltage gain and reduce the input current ripple are discussed.
3.2 Gain Extension Mechanisms

Generally, gain extension circuits are included as additional circuits or
blocks along with CBC to achieve higher voltage conversion ratios. Various
techniques of extending the voltage gain are elaborated in [10, 14–17].
In this chapter, the following gain extension techniques are described:
(a) voltage-lift capacitor (Clift) or voltage-lifting technique

(b) coupled inductor (CI)
(c) voltage multiplier cells (VMCs)
3.2.1 Voltage-Lift Capacitor (Clift)

The voltage gain of a CBC is given by (3.1) and its implications are well
understood through the discussions presented in 3.1.1. In order to enhance
the voltage gain, a capacitor is used as an intermediate energy storage
L1 D1
To rest of
the circuit
S1 Voltage-Lift
Capacitor
Cell 1 (Clift)
L2 Cell 2
+
Vin S2
-
Figure 3.5 Schematic circuit diagram of voltage-lift technique using Clift.
element. Figure 3.5 shows the schematic circuit diagram in which a volt-
age-lift capacitor (Clift) is employed as a gain extension component.
The main purpose of Clift is to act as an energy buffer and clamp the
voltage available from cell 1 with the output from cell 2. In other words,
without Clift, the output from cell 1 has to be connected to the ground ter-
minal and the voltage gain in such a case would then be same as that of
CBC. Thus, by judiciously changing the connection alone and not using
additional components, the voltage gain is doubled.
3.2.2 Coupled Inductor (CI)

In boost derived converters, replacing the simple energy storage inductor
with a coupled inductor (CI) results in extended voltage gain and enhanced
power handling capability. Compared to transformer-based converters,
the primary and secondary windings of CI store and transfer energy in a
complimentary manner and a magnetic core is utilised in a better man-
ner [18–20]. However, the power switches are subjected to voltage spikes
caused by the dynamic current flowing through the leakage inductance of
the coupled inductor. The resonance between leakage inductance and the
stray capacitor of the output diode may cause EMI issues and increases the
output diode voltage stress further.
To suppress the voltage stress on the switch and recycle the leakage
inductance energy, passive lossless clamp circuits with resistor capacitor
diode (RCD) snubbers are employed [21]. The energy stored in leakage
inductance of the CI is recycled to the load when the switch turns OFF.
Thereby, the voltage spike impressed on it is limited [22, 23]. By employing
soft-switching techniques, power switches with a reduced voltage rating
are employed to improve efficiency [24, 25].
Hence, by using CIs with proper turns ratios, the voltage conversion ratio
is extended. The power handling capacity of the converter also increases.
However, an alternative energy recovery mechanism must be employed to
reduce the switch voltage stress due to leakage inductance. By placing mul-
tiple windings on a single magnetic core, the cost, weight, and size of the
converter is reduced [26, 27]. However, designing and manufacturing a
multi-winding CI in a single magnetic core is slightly complicated.
3.2.3 Voltage Multiplier Cells (VMC)

The concept of voltage multiplier cells (VMC) which use two diodes and
two capacitors per cell was introduced to significantly enhance the voltage
gain of a CBC without using additional magnetic elements [28] by employ-
ing VMCs along with CBCs. As the switch is located nearer to the input
port, the voltage stress impressed on it is exactly similar to that of a CBC
with only a fraction of the output voltage. Moreover, each voltage multi-
plier diode is also subjected to a minimal voltage stress which is the differ-
ence between two adjacent stages and similar to that of a CBC. Thus, gain
extension is achieved besides reducing the switch stress [28–31].
Generally, VMCs offer high voltage gain using a compact and mod-
ular circuit structure. However, when a voltage gain of more than 10 is
required, a greater number of components must be used. Resultantly, the
power circuit is subjected to incremental voltage drops and power dissi-
pation across the additional devices employed. Therefore, power handling
capability is limited [32]. Thus, when VMCs are employed, a judicious
trade-off between the voltage gain (component count) and power han-
dling capacity must be made. The generic structure of a VMC network is
depicted in Figure 3.6. The multiplier elements are named as CM1, CM2 and
DM1, DM2. By adopting one or more of the above-described gain extension
techniques, the proposed high gain DC-DC converters (HGCs) are syn-
thesized, as elaborated in the next section.
CM1
Input DM1 DM2 Output

CM2
Reference Node
Figure 3.6 Generic structure of Voltage Multiplier Cell (VMC).

3.3 Synthesis of High Gain DC-DC Converters

To obtain higher voltage conversion ratios which are of the order of 10
and more, one or more of the gain extension techniques described earlier
must be incorporated in the CBC. Further, the current ripple content at
the input side must be reduced for easily implementing maximum power
point tracking (MPPT) algorithms. An interleaving mechanism is a well-
established technique to reduce input current ripple. Hence, the HGCs
discussed in this chapter will be synthesised from a basic interleaved
boost converter (IBC). The synthesis methodology is discussed in detail
subsequently.
3.3.1 Concept of Interleaving

An interleaved boost converter (IBC) is obtained by operating two or more
CBCs in parallel with each other. An interleaving technique has the benefi-
cial features of reduced input current ripple and reduced current stress on
the switch with consequent increment in power transfer efficiency while
still maintaining good power density [33]. The switches used in different
phases of IBC are triggered with equal phase displacement. By splitting the
input current into two or more parallel paths, conduction losses occurring
on the switches reduce and result in enhanced efficiency compared to a
CBC [34, 35].
Figure 3.7 shows the arrangement of a generic N-phase IBC.
Understandably, “N” identical boost converters are connected in paral-
lel. Resultantly, the total input current is shared by the identical CBCs. In
another perspective, the overall power rating of the generic N-phase IBC
will be N-times the power rating of an individual CBC. Thus, IBC helps in
handling higher power at reduced current stress on the switches.
To understand the concept of input current sharing and input current
ripple reduction due to interleaving technique, a 24V/48V, 96W, 50kHz
prototype two-phase IBC was constructed and tested. Figures 3.8(a) and
3.8(b) show the power circuit diagram and photograph of the prototype
IBC which was fabricated and tested.
From Figure 3.8(c), the voltage gain capability of IBC is evident and the
same as that of CBC. Further, the total input current is shared equally among
the interleaved phases. Consequently, by using the components with rat-
ings similar to a CBC, more power can be transferred from the input to the
output port using an IBC. As the interleaved phases are equally displaced
from each other (by 180° in the two-phase IBC), the input current is almost
LN
Lo
iL DN ad
N
SN
CN L +
O
A Vo
D
-
L3
Co
iL D3 nv
3 er
te
S3 rN
So
ur L2
C3
ce
iL D2
2
iin S2 Co
L1 nv
er
Vin C2 te
iL r3
D1
+ 1
S1 Co
nv
- er
C1 te
r2
Co
nv
er
te
r1
Figure 3.7 Schematic arrangement of generic N-phase IBC.
ripple free as depicted in Figure 3.8(d). Thus, by operating the switches in

an IBC with 180°, the current ripple at the input side is cancelled. Further,
compared to CBC, the power handling capability is enhanced in an IBC.
The voltage gain capability of an IBC is the same as that of a CBC. In the
next sub-section, some boost derived converters which possess slightly
higher voltage gain capabilities are explored.
In the classical two-phase IBC, as the output from each stage is grounded
through the filter capacitor, the voltage obtained at the output port is the
same as that of the CBC. To enhance the voltage gain of IBC, the voltage
output from one stage is “lifted” through a lift-capacitor and applied at the
output node of the next stage. Since the outputs from the multiple phases
of IBC act in an additive manner, the conversion ratio gets multiplied by
the number of interleaving channels ‘m’. This technique is often referred to
as a voltage lift technique [36, 37]. To appreciate the voltage-lift concept,
the circuit diagram of a two-phase IBC employing voltage-lift technique is
shown in Figure 3.9(a) and a lab prototype of the same (shown in Figure
3.9(b)) is constructed and practically tested.
L2
iL2 D2
S2
+
L
C0 O
L1 A Vo
iL1 D1 D
-
iin
Vin +
S1
-
(a) (b)
Tek Trig’d M Pos: 0.000s MEASURE Trig’d

Tek M Pos: 2.000µs MEASURE
CH1 CH1
1 Mean Mean
23.9V 2.13A
2 CH2 CH1
Pos Width
1
Pk-Pk
3 10.43µs 2.48A
CH2 CH2
Freq 2 Mean
49.14kHz 2.20A
CH3 CH2
Pos Width Pk–Pk
10.28µs 2.56A
CH4 CH3
4 Mean 3 Pk–Pk
48.0V 480mA
CH1 50.0V CH2 50.0V M 10.0µs CH2 / 6.60V CH1 2.00A CH2 2.00A M 5.00µs CH1 / 2.48A
CH3 5.00A CH4 20.0A 9–Aug–16 18:00 49.1585kHz CH3 2.00A 10–Aug–16 15:24 28.6200kHz
(c) (d)
Figure 3.8 (a) Power circuit diagram of interleaved boost converter, (b) Photograph
of experimented interleaved boost converter, (c) Experimental results of interleaved
boost converter: CH1: input voltage, CH2: voltage across switch, CH3: voltage across the
diode, and CH4: output voltage, (d) Experimental results of interleaved boost converter:
CH1: current through interleaved phase 1, CH2: current through interleaved phase 2,
CH3: input current.
From basic principles, the voltage gain of a two-phase IBC with voltage
lift technique is derived as:
Vo 2
M 2-Ph IBC with Clift = = (3.2)
Vin 1 − D
As demonstrated through experimental results shown in Figure 3.9(c),

the output voltage is twice that of classical IBC. Further, the total input
current is equally shared among the two interleaved phases and the input
current ripple is negligible as observed from Figure 3.9(d). Therefore, com-
pared to CBC and IBC, for the same duty ratio, the voltage gain is doubled
L2
iL2 D2
+
C0 L
D0 O
S2 A Vo
D
CLift -
iL1
L1
iin
Vin +
S1
-
(a) (b)
CH1
CH1
Mean
Mean
1.89A
24.0V
CH1
1 CH2 1
Pk-Pk
Pos Width 1.92A
9.670µs
CH2 CH2
2 Freq 2 Mean
50.26kHz 1.93A
CH3 CH2
Pos Width Pk–Pk
3 9.840µs 2.24A
CH4 CH3
4 3 Pk–Pk
Mean
93.2V 320mA
CH1 20.0V CH2 20.0V M 10.0µs CH2 / 6.40V CH1 2.00A CH2 2.00A M 5.00µs CH1 / 2.56A
CH3 20.0V CH4 20.0V 23–May–17 16:52 50.2699kHz CH3 2.00A 23–May–17 17:05 50.2391kHz
(c) (d)
Figure 3.9 (a) Power circuit diagram of IBC with voltage lift technique, (b) Photograph of
experimented IBC with Clift, (c) Experimental results of interleaved boost converter: CH1:
input voltage, CH2: voltage across switch S1, CH3: voltage across switch S2 and CH4:
output voltage, (d) Experimental results of interleaved boost converter: CH1: current
through interleaved phase 1, CH2: current through interleaved phase 2, CH3: input
current.
in a two-phase IBC with voltage-lift technique. In this chapter, all the

converters are synthesised from an interleaved configuration employing
voltage-lift technique.
3.3.2 Interleaving Mechanism with Coupled Inductors (CIs)

In the IBC structure, discrete inductors are employed as energy storage ele-
ments at the source end. By replacing them with coupled inductors (CIs),
the primary winding of the CIs serve as conventional boost inductors
(energy storage inductor) while the secondary windings are utilised to fur-
ther extend the voltage gain obtained from the IBC structure. The number
of turns in the CI windings are adjusted to meet the steep step-up require-
ments. If required, the voltage gain is further extended by connecting
suitable gain extension cells. Thus, an additional degree of freedom to

enhance the voltage gain is obtained.
Due to the use of CIs with suitable turn ratios, a significant part of gain
extension occurs at the secondary side of CIs. Consequently, voltage stress
on the switches is significantly reduced. In addition, as CIs efficiently trans-
fer the energy from the primary to their secondary side, the overall power
handling capability of the converter is also enhanced. However, leakage
inductance of the CIs causes voltage spikes and results in increased voltage
stress on the power switches. The incremental voltage stress on the power
switches are suppressed by using an energy recycling network and the volt-
age multiplier cell (VMC) at the secondary side.
3.3.3 VMCs at Secondary Side of CIs

As discussed in Section 3.2.3 and depicted in Figure 3.6, VMC comprises
of two diodes and two capacitors. Generally, VMCs are used to extend the
voltage gain of a CBC [28]. In the HGCs discussed in this chapter, since the
secondary winding of the CIs are available for gain extension, a VMC net-
work is embedded across the secondary winding of the CIs. The multiplier
capacitors store the energy available across the secondary windings and dis-
charge the stored energy to the load in a cyclic manner. Thus, higher voltage
gain is obtained by using a VMC network in conjunction with secondary
winding of CIs. Moreover, as the stored energy from the CIs is transferred to
the multiplier capacitors, power handling capability is also enhanced.
As the VMCs are embedded at the secondary side of the CIs, stored
energy in the leakage inductance is also recycled within the diode-capacitor
network formed by the VMC. As a result, the voltage spikes (due to the
energy stored in the leakage inductance) that appear across the switches
are reduced. All the proposed HGCs described in this chapter employ one
or more VMC networks to enhance the overall voltage gain.
All the HGCs that are described in this chapter are systematically devel-
oped by judiciously adopting the above-mentioned synthesis procedures.
The techniques are graphically summarised in Figure 3.10. Further details
about the HGCs are presented subsequently.
3.4 Development of High Gain DC-DC Converters

(HGCs)
All the proposed HGCs are based on 3-phase IBC which employs (a) CIs
instead of discrete inductors, (b) a voltage-lift capacitor, and (c) one or
D1
L3P
Z3
Clift
L2P
Z2 Dlift LS CM1
L1P L1S DM1 DM2
L1P
Vin Z1 L2P L2S
+ CM2
–
L3P L3S
(a) (b) (c)
Figure 3.10 Hybrid strategies used in proposed HGCs. (a) Stage 1 – IBC with voltage lift
technique and primary winding of CIs; (b) Stage 1 – primary and secondary winding of
the CIs; (c) Stage 2 – VMC network.
more VMCs connected at the secondary side of the CIs. The development
of each converter is described subsequently.
3.4.1 HGC with 3 CIs, Clift, and VMC

Figure 3.11 shows the power circuit diagram of the proposed HGC-1. In
Stage 1, Clift and Dlift act as a voltage lifting network and aid in enhancing the
voltage gain of Stage 1. In Stage 2, the secondary windings are connected
in series and one VMC network is embedded into them. The detailed
Stage 1 Stage 2
L3S L2S L1S CM1
L3P D1 DIBC D0
DM1 DM2
Z3
Clift
CM2
L2P +
L
Z2 Dlift O
C0 A V0
L1P D
–
Vin Z1
+
–
Figure 3.11 Power circuit diagram of proposed HGC-1.

operating principle and the characteristic behaviour of various circuit

parameters are elaborated subsequently.
For ease of understanding and added clarity, the following valid assump-
tions are made:
(i) All the semiconductor devices used in the converter are

ideal
(ii) The current flowing through the CIs and load are continu-
ous (continuous conduction mode (CCM))
(iii) All three switches are switched ON for a brief time interval
to charge the primary inductors L1P, L2P, and L3P
The working of HGC-1 is elaborated through Mode 1 to Mode 6. Figure

3.12 depicts the circuit equivalent during the operation.
L3P L3P
D1 DIBC D0 D1 DIBC D0
L3S L2S L1S CM1 L3S L2S L1S CM1
Z3 Clift Z3 Clift
L2P DM1 CM2 DM2 + L2P DM1 CM2 DM2 +
Z2 V0 LO Z2 V0 LO
C0 C0
Dlift A Dlift A
L1P D L1P D
- -
+ Z1 + Z1
V V
- in - in
(a) (b)
L3P L3P
Z3 Clift Z3 Clift
Z2 V0 LO Z2 V0 LO
C0 C0
Dlift A Dlift A
L1P D L1P D
- -
+ Z1 + Z1
V V
- in - in
(c) (d)
L3P L3P
Z3 Clift Z3 Clift
Z2 V0 LO Z2 V0 LO
C0 C0
Dlift A Dlift A
L1P D L1P D
- -
+ Z1 + Z1
V V
- in - in
(e) (f)
Figure 3.12 Equivalent circuit diagram of proposed converter during various operating
modes: (a) to (f) represent Mode 1 to Mode 6.
Mode 1: (t0- t1)

At time t=t0, Switch Z1 is turned OFF while Z2 and Z3 remain turned ON.
Stored energy in the primary winding, L1P, starts discharging to its second-
ary winding, L1S. The charging and discharging rates of L1S and L1P, respec-
tively, are the same. Energy transfer from L1P to L1S occurs through the path
comprising of Dlift, Clift, and DIBC. The current through Dlift is same as the
current through L1P and is expressed as:
iL1 P = iDlift (t ) = n (iDM 1 (t ) + iCM 2 (t )) (3.3)
In Stage 2, secondary winding of the CIs along with the VMC acts as
voltage source and meets the load demand through CM1 and D0. The poten-
tial developed across Clift forward biases diode DM1 and helps in charging
the multiplier capacitor CM2.
When CM2 is completely charged, DM1 turns OFF while DM2 is forward
biased. Multiplier capacitor CM2 charges CM1 and supplies the load simulta-
neously. Current through capacitor CM1 is given by:
1
iCM 1 (t ) = 2 (nVL1P − vCM 1 ) × t (3.4)
n L py
where Lpy = L1P+L2P+L3P and ‘n’ is the turns ratio of CIs. When CM1 is
completely charged (by CM2), diode DM2 is reverse biased and DM1 starts
to conduct. Thus, the multiplier diodes in the VMC network operate in a
complimentary manner and contribute to the energy transfer process in
Stage 2. In all the subsequent modes, the VMC network operates in a simi-
lar manner as explained above. Mode 1 ends when I L2 P = I L2 P ,max..
Mode 2: (t1- t2)

Mode 2 begins at t2 when Z2 is switched OFF. Switches Z1 and Z3 are main-
tained in their respective OFF and ON states. Turning OFF Z2 initiates the
energy transfer from L2P to L2S through Clift and DIBC. As Z3 is conducting,
D1 remains reverse biased. Current through switch Z3 is expressed as:
iL3 P = iZ3 (t ) = n (iCM 1 (t ) + iDM 1 (t )) (3.5)
Diode Dlift continues to remain in forward biased condition till Z1 is ON.

L1P continues to discharge its stored energy till its current decreases to a
minimum value, I L1 P ,min , and marks the end of Mode 2. At time t=t2, Clift is
charged to a value (with respect to ground) given by:
1
VClift (i ) = Vin (3.6)
1− D
where D represents the duty ratio of each switch.

Mode 3: (t2- t3)
To charge L1P, Z1 is turned ON while switches Z2 and Z3 are maintained in
their OFF and ON states respectively. Diodes Dlift and D1 remain reverse
biased. L2P continues to discharge and charges L2S while L3P continues to
store energy. The rate of rise and fall of current through the CIs’ windings
are same. In Stage 2, the VMC network comprised of DM1, CM1, DM2, and
CM2 operate in a manner as detailed in Modes 1 and 2. Current through
CM2 is governed by:
V0 − (VC1 + nVL1 P + VCM 2 )

iCM 2 (t ) = ×t (3.7)
n 2 L py
When the current through L3P reaches its maximum value, I L3 P ,max , at
time t=t3, Mode 3 ends.
Mode 4: (t3 - t4)

The beginning of Mode 4 is marked at time t=t3 when L3P is completely
charged. Switch Z3 is turned OFF to enable energy transfer from L3P to L3S
followed by the load, while switches Z1 and Z2 are retained in their ON and
OFF states respectively. D1 and DIBC are in the ON state and participate in
the energy transfer process. The current through Z1 is given by:
V0 − (VC1 + nVL1 P + VCM 2 ) (3.8)

iZ1 (t ) = niD0 (t ) = ×t
n 2 L py
The current through L2P reaches its minimum value, I L2 P ,min,, at time t=t4,
when the transfer of energy from L2P to the load through L2S and the VMC
network is completed, marking the end of Mode 4. Voltage across Clift and
ground at instant t4 is equal to:
2
VClift (ii ) = Vin (3.9)
1− D
VGE(Z1)
0 t
VGE(Z2)
0 t
VGE(Z3)
0 t
IL1P
IL1,max
IL1S
IL1,min
0 t
IL2P IL2,max
IL2S
IL2,min
0 t
IL3S
IL3,max
IL3P
IL3,min
0 t
VD1
0 t
3V0
3+2nk
VD
lift
0 t
V0
3+2nk
VZ1
IZ1 3V0
3+2nk
0 t
VZ2
IZ2 3V0
3+2nk
0 t
VZ3
IZ3
V0
3+2nk
0 t
t0 t1 t2 t3 t4 t5 t6
Figure 3.13 Waveforms depicting some key circuit parameters of HGC-1.

Mode 5: (t4- t5)

At time t=t4, switch Z2 is turned ON to charge L2P towards supply voltage
Vin. Switching state of Z1 and Z3 is same as Mode 4. L3P discharges to the
load and L1P continues to store energy. D1 remains ON while CM1 and CM2
continue to charge and discharge respectively. Current through D1 is given
by
iD1 (t ) = niD0 (t ) (3.10)
At the end of Mode 5, the current through L1P reaches its maximum
value at t=t5. Thus, L1P is ready to transfer its stored energy.
Mode 6: (t5- t6)

As L1P is completely charged, switch Z1 is turned OFF allowing L1P to
transfer its stored energy to the load through L1S. Switches Z2 and Z3 are
maintained in their respective ON and OFF states. Primary winding L2P
charges while L3P discharges to the load through the diodes D1, DIBC, and
D0. At time instant t=t6, Clift is completely charged. The potential difference
between the top plate of Clift and ground is given by:
3
VClift (iii ) = Vin (3.11)
1− D
Current through D0 (and load current I0) is governed by Lpy and is

expressed as:
3Vin + VCM 2 (1 − D ) − V0 (1 − D )
iD0 (t ) = ×t (3.12)
n 2 L py (1 − D )
At the end of Mode 6, one switching cycle is complete. Figure 3.13

depicts the waveforms of key circuit parameters of the HGC-1. The equa-
tions for designing the elements of HGC-1 are elaborated subsequently.
3.4.1.1 Design Details of HGC-1

From the basic volt-second balance principle, the voltage gain of the pro-
posed HGC-1 under steady-state conditions can be easily derived. For bet-
ter understanding, the voltage gain of the HGC-1 can be two derived by
intuitively cascading the voltage gain obtained from Stage 1 and Stage 2.
The voltage gain is given by:
V0 3 + 2nk
M HGC −1 = = (3.13)
Vin 1− D
where ‘n’ and ‘k’, respectively, are the turns ratio and coupling co-efficient
of the CIs while ‘D’ is the duty ratio of the switches.
Voltage Stress on Power Switches and Diodes used in HGC-1

Voltage stress experienced by power switches Z1 and Z2 is equal to the
potential across Clift. Therefore, voltage stress impressed across the switches
is given by:
V0 3V0
VZ1 = VZ2 = = (3.14)
2
1 + nk 3 + 2nk
3
Due to asymmetry caused by Clift, the voltage stress on Z3 is relatively

lower and given by:
V0
VZ3 = (3.15)
3 + 2nk
When Z1 conducts, Dlift is reverse biased while D1 remains reverse biased

when Z3 conducts. Therefore, D1 blocks a voltage level obtained across
Stage 1 given by (3.14), while voltage stress on Dlift is given by (3.15). From
the operating principle, voltage stress on DM1, DM2, and D0 is given by:
V0 (3.16)
VDM 1 = VCM 2 −
2
1 + nk
3
VDM 2 = VD0 = V0 − VCM 2 (3.17)
The voltage stress on the semiconductor devices is inversely propor-

tional to n and k. Therefore, to minimize the voltage stress across the
switches and diodes, a careful choice of n is essential. In addition, the CIs
are properly designed and manufactured to ensure that the value of k is
higher and voltage stress on the power switches is reduced.
The practical value of k is determined to be 0.88. Figure 3.14 shows

the operating point of the proposed converter. Operating the switches at
D=0.55 and using CIs with n=3 yields the required voltage gain of about
18.4 when k=0.88. Figures 3.15 (a) and (b) clearly show that the magnitude
of voltage stress impressed on the switches is very much reduced to only
36% (Z1, Z2) and 12% (Z3) of the output voltage (V0).
Current Stress on Semiconductor Devices of HGC-1

From the input-output power balance principle of an ideal power con-
verter, the average input current (Iin) is derived as:
3 + 2nk (3.18)
Iin = I0
1− D
Total input current is shared by the three interleaved phases of Stage 1.

Current through Z1 is greater than Z2 and Z3 due to the asymmetry in Stage
1 caused by Clift. Current through Z1 is given by (3.19). Switches Z2 and Z3
carry equal currents given by (3.20).
36
34
40
32
35
30
Voltage Gain (M)
30
28
25
Operating Point is at M=18.4 26
20 when D=0.55, n=3 and k=0.88
24
X: 0.55
Y: 0.88
15 Z: 18.4
22
10 20
1
0.98
0.96 0.8 18
Coe 0.940.92
ffic 0.9 0.7
ien
t of 0.88 0.6 16
Cou 0.86 (D)
plin 0.84 0.5 Ratio
g (k 0.82 Duty 14
) 0.8 0.4
Figure 3.14 Performance plot of the proposed HGC-1 showing the variation in voltage
gain (M) versus duty ratio (D) for various values of k when turns ratio is n=3 and the
operating point.
Voltage across switch Z3/Output voltage

0.65
0.25 0.2
Voltage stress on Z1 and Z2/Output voltage
0.6 0.2
0.7
0.18
0.6 0.55 0.15
0.5
0.1 0.16
0.4 0.5
0.05 X: 3
0.3 X: 3 Y: 0.88
Y: 0.88 1 0.14
Z: 0.3623 0.45 Z: 0.1206
0.2
1 Voltage Stress on Z1 and Z2is Voltage Stress on Z3 is 12% of Output Voltage
36.2% of Output Voltage (0.362 V0) 0.95 (0.12 V0) when n=3, k=0.88 and D=0.55
0.98 0.4
Co
when n=3, k=0.88 and D=0.55 0.12
0.96
ffic
Co 0.94
ien
ffi 0.9
cie 0.92
to
nt 0.35
fC
0.9 4
of 0.1
ou
Co 0.88 3.5 0.85
p
up 4
lin
lin 0.86 3
0.3 3.5
g (k
g 2.5 3
(k 0.84 2 2.5
)
)
0.82 2
1.5 tio (n) 0.8 1.5
0.8 1 Turns Ra 1
(n)
Turns Ratio
(a) (b)
Figure 3.15 Performance plots of HGC-1 showing the variation in voltage stress
on the switches compared with output voltage for various values of k and n for D=0.55:
(a) voltage stress on Z1 and Z2; (b) voltage stress on Z3.
6 + 4nk 2
I Z1 = I 0 = Iin (3.19)
3(1 − D ) 3
3 + 2nk 1
I Z 2 = I Z3 = I 0 = Iin (3.20)
6(1 − D ) 6
A current flows through Dlift when switch Z1 is in the OFF state. As the
switch conducts for 55% of the total time period, diode Dlift conducts for
the remaining 45% of the total time period. Similarly, D1 conducts when
Z3 is turned OFF.
Correlating the conducting intervals of Dlift-Z1 and D1-Z3 combinations,
current through Dlift and D1 is derived as:
9 + 6nk 3
I Dlift = I 0 = Iin (3.21)
5(1 − D ) 5
9 + 6nk 3
I D1 = I 0 = Iin (3.22)
20(1 − D ) 20
Determination of Primary Inductance Value of CIs used in HGC-1

The primary winding of CIs is designed to ensure continuous input current
with low ripple content as preferred for PV application. Considering the
input current ripple (∆Iin), the appropriate value of inductance offered by
primary windings (L1P, L2P and L3P) is obtained using (3.23).
Vin D
L1P = L2 P = L3 P = (3.23)
3 f S Iin
The inductance value of secondary winding of the CIs is determined

from:
Lsy = n2Lpy (3.24)
Generally, tight coupling between the primary and secondary windings

of the CIs is preferred. However, due to minor manufacturing imperfec-
tions, the value of coupling coefficient is less than 1. For an individual
CI, its practical value of coupling coefficient (kpractical) is determined from
(3.25).
LS
k practical = 1 − (3.25)
LO
where LO and LS are the inductance values measured across primary winding
(of an individual CI) when secondary winding is open and short-circuited,
respectively. In the proposed converter, the average value is computed and
denoted as ‘k’.
Determination of CIs’ Turns Ratio

The voltage gain of HGC-1 is derived and given by (3.13). From (3.13), the
voltage gain of the converter is dependent on the values of D and n. The
turns ratio of the CIs is determined from (3.26).
V0 (1 − D ) 3 M (1 − D ) − 3
n= − = (3.26)
2kVin 2k 2k
To meet the high voltage gain requirement, incorporating a greater

number of turns in the windings leads to an increase in size of the CIs,
whereas lesser value of ‘n’ translates to operating the switches at extreme
duty ratios. Due to the practical difficulties encountered while operating
the switches at extreme duty ratios, the value of D is fixed at D=0.55. The
proposed HGC-1 is expected to operate from a 60V DC input and yield
1.1kV DC at the output port. Based on the voltage gain requirement, the
value of ‘n’ is computed as n=3.
Design of Capacitors
Considering the output power (P0), output voltage (V0), switching fre-
quency (fs), and output voltage ripple (ΔV0), the value of output capaci-
tance is obtained from (3.27).
P0 D
C0 = (3.27)
V0 f s V0
The value of CM1, CM2, and Clift depends on energy transferred through
them individually and the voltage ripple across each capacitor. Therefore,
the rating of each capacitor is obtained from (3.27) by substituting the volt-
age impressed across each capacitor and the individual ripple voltage.
The proposed HGC-1 is fabricated and tested from a 60V DC input.
When the switches are operated at a duty ratio of D=0.55 and 100kHz
switching frequency, the HGC-1 is designed to deliver 3kW at 1.1kV to
the load. The primary inductances are designed considering 15% current
ripple at the input side. Some of the experimental results obtained from the
prototype converter are discussed subsequently.
3.4.1.2 Experimental Results of Prototype HGC-1 and Discussion

The TMS320F28027 Piccolo digital signal processor (DSP) is used for gen-
erating the required gate pulses. A signal conditioning unit is employed to
interface the gate pulses obtained from DSP and the SCALE driver boards
(2AP043512) which are used for isolating and driving the power IGBTs.
The close proximity between the driver board and power module aids
in reducing EMI issues. The key waveforms are captured using four chan-
nel isolated a Tektronix TPS2024B digital storage oscilloscope (DSO) and
standard accessories.
Figure 3.16 shows the waveforms obtained from the DSO. In the oscil-
loscope waveform, Channels 1 to 3 (CH1, CH2 and CH3) correspond to
gate pulses applied to the power switches used in HGC-1 and the voltage
obtained across the output terminals is depicted in CH4. Gate pulses with
a moderate duty ratio (D=0.55) and 120° phase delay between the three
interleaved legs provide the required output voltage which is in accordance
with the value predicted using (3.13). The output voltage is fairly constant
with negligible ripple content, proving the design of the output capacitor.
Further, the voltage gain capability of HGC-1 is validated.
During experimentation, the voltage stress experienced by switches
Z1 and Z3, with respect to the output voltage, is depicted through

CH1
Pos Width
1
5.815µs
2 CH2
Pos Width
5.845µs
3
CH3
Pos Width
5.870µs
CH3
Freq
100.9kHz
CH4
4 Mean
1.10kV
CH1 50.0V CH2 2.00V M 2.50µs CH1 / 8.00V
CH3 5.00A CH4 50.0A 11–Apr–17 18:05 100.862kHz
Figure 3.16 Oscilloscope waveforms of HGC-1 showing experimental results obtained

while testing HGC-1 under full-load conditions; gate pulses (CH1, CH2, CH3) and output
voltage (CH4).
Figures 3.17(a) and (b). The turn ON and turn OFF instants of the power
switches are in perfect agreement with their respective gate pulses. Further,
as the majority of the gain extension happens at Stage 2, the voltage stress
magnitude of Z1 and Z3 is reduced and in close agreement with (3.14) and
(3.15). The voltage spikes appearing across the switches are caused by
the leakage inductance of the CIs. However, their magnitudes are much
reduced and not alarming since most of the stored energy is recycled at
Stage 2 through the elements present in the VMC network.
To verify the dynamic performance of the HGC-1, input voltage applied
to the converter is varied from 48V to 72V (80% to 120% of the rated input
voltage) while maintaining a constant load. Figure 3.18(a) illustrates the
variations in the output voltage. The variation in output voltage is much
less. From theoretical computations, the duty ratio variation is between
0.6386 and 0.458 to maintain a constant output voltage. At input volt-
age levels higher than the specified value, the efficiency is expected to be
slightly higher due to marginally lower input current magnitude which
causes reduced losses.
To obtain the converter performance when the load varies, the results
are obtained through simulation and experimentation. The output volt-
age variation of the proposed converter for 75%, 100%, and 125% of the
Tek Trig’d M Pos: 0.000s MEASURE Tek Trig’d M Pos: 0.000s CURSOR
CH1 Type
Pos Width
1 1 Amplitude
5.913µs
CH1 Source
Freq CH2
100.8kHz
CH2
2 Pk–Pk 2 V 128V
392V
CH3 Cursor 1
Mean
0.00V
1.10kV
3 CH4 Off 3 Cursor 2

Mean 128V
CH1 20.0V CH2 200V M 2.50µs CH1 / 4.76V CH1 50.0V CH2 100V M 2.50µs CH1 / 3.00V
CH3 500V 11–Apr–17 18:57 100.854kHz CH3 1.00kV 11–Apr–17 19:00 100.842kHz
(a) (b)
Figure 3.17 Experimental waveforms of HGC-1 obtained while testing HGC-1 under
full-load conditions: (a) gate pulse applied to Z1 (CH1), voltage stress on Z1 (CH2), and
output voltage (CH3); (b) gate pulse provided to Z3 (CH1), voltage stress on Z3 (CH2),
and output voltage (CH3).
Tek Scan DISPLAY Tek Scan DISPLAY

60V 60V Input Input Voltage Vin Type
72V Type
Voltage Vin Vectors Vectors
48V 48V
1 Persist
1 3.7A Persist
Off 2.8A 2.8A 2.8A Load Off
Output Current Io
1.7A
Voltage Vo Format 2 Format
YT YT
Brightness Output Voltage Vo Brightness

100% 100%
3
CH1 50.0V M 10.0s CH1 / 0.00V CH1 50.0V CH2 2.00A M 10.0s CH1 / 0.00V
CH3 500V 14–Jun–17 12:39 <10Hz CH3 500kV 14–Jun–17 13:42 <10Hz
(a) (b)
Figure 3.18 Experimental results to study dynamic performance of HGC-1: (a) variation
of output voltage when input voltage varies from 48V to 72V; (b) variation of output
voltage when load varies from 75% to 125% of full load condition at constant input
voltage.
full load with constant input voltage during experimentation is shown in

Figure 3.18(b). The output voltage is fairly constant under overload con-
ditions. This is mainly due to the energy storage elements which act as an
energy buffer during load variations. During light load conditions, due to
marginally higher voltage levels obtained at Stage 1 and Stage 2, the output
voltage also increases slightly.
Figure 3.19 shows the plot of output voltage variation and efficiency
under various load conditions during simulation and experimentation.
The converter operates at a maximum efficiency of 92.3% under rated load
100 1.6
90
80
1.2
Output Voltage (kV)

70
Efficiency (%)
60
50 0.8
40
30
0.4
20 Efficiency(Simulation) Efficiency (Practical)
10 Output Voltage (Simulation) Output Voltage (Practical)
0 0
25% 50% 75% 100% 125%
(0.75kW) (1.5kW) (2.25kW) (3.0kW) (3.75kW)
Output Power
Figure 3.19 Efficiency and output voltage for various loads.
conditions. The change in load voltage is about 2.67% when the load is
increased from a rated condition to 125% of the rated load.
To appreciate the ripple free input current behavior, simulated wave-
forms for current through primary windings of the CIs L1P, L2P, L3P, and
the total input current are shown in Figure 3.20(a). Proper design of CIs
ensures appropriate rise and fall of current through the CI primary wind-
ings while maintaining continuous conduction mode. Further, the input
current is shared by the interleaved phases and contains very low ripple
(2.63% of input current).
Figure 3.20(b) shows the current stress on the power switches plotted
along with total input current. Due to inherent current sharing mechanism
in Stage 1, the individual switch current magnitude is much less when
compared to the total input current magnitude. However, due to asym-
metrical structure, the current sharing is not uniform. Nevertheless, the
current sharing pattern is in perfect agreement with (3.19) and (3.20) and
does not affect the converter performance. Figure 3.21 shows the voltage
and current waveforms captured at the input and output terminals when
the converter delivers rated power (3kW) to the load. Output voltage and
the input current waveforms confirm the ability of the proposed converter
to offer higher voltage gain (18.33) at a higher power rating (3kW). Input
current and output voltage ripple magnitude are very low and substantiate
the design of passive elements.
In general, the losses are categorized as: (i) switching loss across the
switches, (ii) conduction loss in the switches, (iii) losses across the diodes,
(iv) losses in the magnetic elements, and (v) other losses (losses on
48A Current through Switch Z1

40A Current through Inductor Primary winding L1P
20A 24A
0A 0A
Current through Inductor Primary winding L2P Current through Switch Z2
12A 12A
6A 6A
0A 0A
12A Current through Inductor Primary winding L3P 12A Current through Switch Z3
6A 6A
0A
0A
Input Current Input Current
58A
58A
56A 56A
54A 54A
313.470 313.474 313.478 313.482 313.486 313.470 313.474 313.478 313.482 313.486
Time (ms) Time (ms)
(a) (b)
Figure 3.20 Simulation results of HGC-1 demonstrating: (a) current through CI primary
windings L1P, L2P, L3P, and input current; (b) current through switches Z1, Z2, Z3, and
input current.
75V Input Voltage
0V
58A Input Current
56A
54A
1.1025kV Output Voltage
1.1000kV
1.0975kV
3.0A Output Current

2.8A
2.6A
313.470 313.474 313.478 313.482 313.486
Time (ms)
Figure 3.21 Simulation results of voltage and current waveforms obtained under rated
load condition at input and output side of the HGC-1.
capacitors, due to stray resistance of wires, etc.). The total power loss occur-
ring in the converter is estimated using standard expressions presented in
(3.28) to (3.31).
Power loss in the switches is given by:
PSW_loss = Pconduction + Pswitching (3.28)

Other Losses 2%
(5.33W)
Loss in
Conduction loss
CIs 16%
in switches 21%
(39W)
(53.44W)
Loss in
Diodes 20%
(53.94W)
Switching loss in
switches 39%
(98.3W)
(a)
CM2 To Input Power
Z3 L3
Gate Pulses from Driver
DM1 & DM2

D0
Z2
D1 DIBC L2
C0
Z1 Dlift Clift CM1
L1
To Load
(b)
Figure 3.22 (a) Loss distribution profile of proposed HGC-1, (b) Photograph of prototype
HGC-1.
Expanding (3.28), the total loss occurring in the switch is expressed as:
2
PSW _ loss = I SW _ rms RCE (ON ) + ( PTurn _ ON + PTurn _ OFF + Pjn _ C ) (3.29)
Power loss in the diodes is calculated using:
PDiode _ loss = V f I f (avg ) + I 2f (rms ) Rdiode (3.30)
Power loss contributed by all the three CIs is found from:

2 2
PCI _ loss = I py ( rms ) R py + I sy ( rms ) Rsy + Pferrite (3.31)
Various parameters like ON-state resistance of the devices (RCE(ON),

Rdiode), loss across the junction capacitance (Pjn_C), diode forward-voltage
drop (Vf ), and ferrite core loss (Pferrite) are determined from the datasheet of
elements. Using (3.28) to (3.31), the power loss distribution profile of the
proposed HGC-1 is developed and presented in Figure 3.22(a) while the
photograph of the prototype converter is depicted in Figure 3.22(b).
In the proposed HGC-1, though 3 CIs are employed, their secondary
windings are cascaded in series and enclosed in a single VMC. Due to the
coupling arrangement of the secondary windings (dotted terminals), the
net contribution to the increment in overall voltage gain is through only
one CI and energy stored in the remaining two CIs gets nullified (cancelled
out). Hence, to reduce the weight of the converter without compromising
on voltage gain, coupled inductors L2P -L2S and L3P -L3S used in HGC-1 are
replaced by simple inductors L2 and L3 in HGC-2. The power circuit dia-
gram and other significant details of the proposed HGC-2 are elaborated
subsequently.
3.4.2 3-Phase Interleaved HGC with 1 CI, Clift, and VMC

The proposed HGC-2 has two stages similar to that of HGC-1. It is synthe-
sised by replacing the two CIs (used in HGC-1) with discrete inductors L2
and L3. The coupled inductor with primary and secondary winding L1P-L1S
and all other components are retained as that of HGC-1. The modification
is carried out to reduce the weight of the converter without compromising
on voltage gain and power handling capacity. The power circuit of the pro-
posed HGC-2 with one CI and one VMC is shown in Figure 3.23.
The basic operating principle and design aspects are elaborated in [38].
The voltage gain of HGC-2 is exactly similar to that of HGC-1 and men-
tioned below in (3.32) for additional clarity.
V0 3 + 2nk
M HGC −2 = = (3.32)
Vin 1− D
The specifications and the experimental results of the proposed HGC-2

are also similar to HGC-1. Figure 3.24 depicts a photograph of the proto-
type converter.
Stage 1 Stage 2
CM1
D1 DIBC D0
L1S
L3 DM1 DM2
Z3 Clift
CM2
+
L2 L
Z2 Dlift O
C0 V0
A
D
–
L1P
Vin Z1
+
–
Figure 3.23 Power circuit of proposed HGC-2 with one CI and one VMC.
Diode D1
Diode DIBC
Input
Supply Voltage
Multiplier Output
Terminals Lift Output
Capacitor Capacitor Terminals
Capacitor
CM1 C0
Switch Z3 C1
Switch Z2 Output
Multiplier
Diode D0
Inductor L2 Diode DM1
Multiplier Multiplier
Diode D2 Diode DM2 Capacitor
CM2
Inductor L3 Switch Z1 Coupled
Inductor (CI)
CI Primary CI Secondary
Winding Winding
Terminals Terminals
Figure 3.24 Photograph showing top view of prototype HGC-2.

In HGC-2, only one CI is employed. Therefore, its efficiency and output

voltage variation need to be studied through simulation and experiment,
preferably for various loaded conditions also. Figure 3.25 portrays the effi-
ciency and output voltage variation. The proposed HGC-2 delivers the
required power to the load with less change in output voltage magnitude.
Further, the practical efficiency obtained from the hardware experimenta-
tion is very close to the simulated values.
The proposed HGC-2 is developed by judiciously connecting three
interleaved stages consisting of two simple inductors and one CI, along
with Clift and one VMC embedded in the secondary side of the lonely
CI. Experimental results from the prototype version of HGC-2 prove its
voltage gain capability, especially at high power levels. The adopted inter-
leaving technique is responsible for reducing the input current ripple and
making it easily adaptable for PV applications. Since HGC-2 employs only
one CI, it is more compact and lighter than HGC-1.
In HGC-1, the secondary windings, L1S, L2S, and L3S, of the CIs were
connected in series and enclosed in a single VMC. Therefore, only one CI
effectively contributed to the increment in voltage gain. Due to the fash-
ion in which the secondary windings of CIs were connected, the contribu-
tion of the other two CIs cancelled out and did not lead to an increment
in voltage gain. However, higher voltage gain can be achieved when the
secondary winding of the CIs is enclosed in separate/individual VMCs.
100 Efficiency 2.0

90
80 1.6
Output Voltage (kV)
70
Output Voltage
Efficiency (%)
60 1.2
50
40 0.8
30 Simulated Practical
20 0.4
Simulated Practical
10
0 0.0
50% 75% 100% 125%
(2.3kW) (2.7kW) (3.0kW) (3.3kW)
Output Power
Figure 3.25 Simulated and experimented plots showing efficiency and output voltage
variation for various values of output power.
Such an arrangement is employed in Stage 2 of the proposed HGC-3 for

obtaining higher voltage gain than HGC-1 and HGC-2. A power circuit
diagram and other significant details of the proposed HGC-3 are elabo-
rated subsequently.
3.4.3 Modular HGC with 3 CIs, Clift, and 3 VMCs

In HGC-1 and HGC-2, Stage 1 is synthesised from a three-phase IBC
using three CIs and Clift. Stage 2 is formed by the combination of secondary
winding of three CIs and one VMC. Both the converters yielded a voltage
gain of 18.33 at 3kW rated power.
In the proposed HGC-3, Stage 1 is similar to that of HGC-1 and HGC-2.
However, to extend the voltage gain further, three VMCs (formed by multi-
plier diodes (DM1-DM6) and multiplier capacitors (CM1-CM6)) are employed
in Stage 2. Figure 3.26 shows the power circuit diagram of the proposed
HGC-3, while the inset depicts the rearranged image of Stage 2 for clarity.
The operating principle of HGC-3 can easily be understood by consid-
ering a rearranged Stage 2 in which one VMC is embedded across the sec-
ondary winding of each CI. Each individual VMC contributes to achieving
a higher voltage gain compared to that used in HGC-1 and HGC-2.
Resultantly, the overall voltage gain of HGC-3 is derived and expressed as
V0 3 + 3nk
M HGC −3 = = (3.33)
Vin 1 − D
The operating principle along with design details are elaborated in [39].
Considering the 60V to 1.1kV, 3kW, 100kHz ratings, a prototype version is
fabricated and tested. Since the ratings are similar, the experimental results
are also expectedly on the same lines as that of HGC-1 and HGC-2.
Nevertheless, the inclusion of three CIs and embedding VMC net-
work within each secondary winding results in better voltage profile
characteristics.
The experimental waveforms depicted in Figure 3.27(a) to 3.27(c) validate
the efficiency values at different load conditions. While operating under
full-load, the proposed HGC-3 operates at 92.63% efficiency. Considering
the high voltage gain value (18.3) and power level (3kW), the efficiency
value is good enough. The reduction in output voltage is about 50V when
the load is increased from 100% to 115% of full load condition and the
converter operates at 89.78% efficiency. At 75% of full load, the converter’s
Stage 2 (Rearranged)
*
L3S CM1 L2S CM3 L1S CM5
DM1 DM2 DM3 DM4 DM5 DM6
CM2 CM4 CM6
Stage 1 Stage 2
D1 DIBC DM1 CM2 CM6 DM6 D0

L3P
DM2 CM5
Z3 L3S DM5
Clift
L1S +
*
L2P CM1 CM3 L
*
Z2 Dlift O
L2S C0
DM3 DM4 A V0
D
CM4 –
L1P
+ Z1
Vin
–
efficiency is 90.10%. Energy storage elements contribute in maintaining a

reasonably stiff load voltage even when under open-loop operation.
When load on the converter fluctuates, inductors and capacitors step
in by acting as energy buffers and maintain a constant DC bus voltage.
During light load condition, marginally higher output is obtained from
the HGC-3. To protect the other loads connected to the common DC bus
and constantly obtain the specified DC voltage at the output port, a slight
reduction or adjustment in the switches’ duty ratio is essential. Figure 3.28
shows the top view photograph of the implemented HGC-3.
The proposed HGC-1 and HGC-2 use 16 components in the power cir-
cuit, while the total component count in HGC-3 is 24. Despite the higher
total components, the proposed HGC-3 possesses higher voltage gain
capability. However, accommodating a larger number of components leads
to an increase in the size of the converter.
To make a compact and lighter HGC without compromising on volt-
age gain capability, one multi-coupled inductor consisting of three pri-
mary windings and one secondary winding wound on a single core is
Tek Trig’d M Pos: 0.000s MEASURE Tek Trig’d M Pos: 0.000s MEASURE
CH1 CH1
1 Mean 1 Mean
60.6V 60.5V
CH2 CH2
Mean Mean
2 53.3A 2 41.3A
CH3 CH3
M Mean Mean
1.10kV 1.19kV
3 3
CH4 CH4
Mean Mean
2.72A 1.89A
4 MATH 4 MATH Off
Mean
Mean
2.99kVA
CH1 100V CH2 50.0A M 5.00 µs CH2 / 5.00A CH1 100V CH2 100A M 5.00µs CH2 / 12.2A
CH3 2.00kV CH4 2.50A MATH 5.00kVA 45.6506Hz CH3 2.00kV CH4 1.00A 17–Nov–16 15:39 <10Hz
(a) (b)
CH1
1 Mean
60.6V
CH2
Mean
2 63.3A
CH3
Mean
1.05kV
3 CH4
Mean
3.28A
4 MATH Off
Mean
CH1 100V CH2 50.0A M 2.50µs CH1 / 22.3V

CH3 2.00kV CH4 2.00A 17–Nov–16 15:41 100.878kVz
(c)
Figure 3.27 Experimental voltage and current waveforms under various load conditions.
(a) input voltage (CH1) and current (CH2) waveforms, output voltage (CH3) and current
(CH4) oscillograms, output power (channel ‘M’) at full load; (b) same parameters as
Figure (a) at 75% of full load; (c) same parameters as in Figure (a) at 125% of full load.
Inductor Coupled To Input Power Coupled

Current Inductor L2 Supply Inductor L1
Measurement
Measurement
Inductor
Current
Gate Pulses from Driver
CM1
DM1 DM2 DM3

CM3
Z3
CM5
DM5
Z2 DIBC CM2 CM4
DM4 DM6
Z1 D1 CM6 C0
CLift D0
DLift
Inductor Current
Measurement
Coupled
Inductor L3 To Load
Figure 3.28 Photograph showing top view of implemented HGC-3.

employed in the proposed HGC-4 instead of three individual (discrete)

CIs used in HGC-1 and HGC-3. In Stage 2 of HGC-4, the voltage gain is
enhanced by using a VMC in conjunction with the secondary winding of
multi-winding CI. A power circuit diagram and other significant details
of the proposed HGC-4 (compact HGHP converter) are elaborated in the
next sub-section.
3.4.4 Compact HGC Based on Multi-Winding CI, Clift,

and VMC
In the preceding sub-sections, development of high gain converters (HGCs)
rated for 3kW yielding a voltage gain of 18.33 were described. Similar to
the other proposed HGCs, the proposed HGC-4 also consists of two stages.
Stage 1 is built using an IBC, a multi-winding CI, and voltage lift capacitor.
In Stage 2, the voltage gain is enhanced by using a VMC in conjunction
with the secondary winding of the multi-winding CI.
Three primary windings and one secondary winding are wound on a
single magnetic core to form a multi-winding CI and employed in the
proposed HGC-4. Such a multi-winding CI arrangement is incorporated
to attain a compact HGC, thereby increasing the power density of the
converter. The power circuit, design details, and experimental results of
HGC-4 are elaborated in the following sub-sections.
Figure 3.29 shows the power circuit of the proposed HGC-4. The
switches employed in Stage 1 of the proposed HGC-4 are operated at a duty
ratio of D=0.55 with 120° phase-shift similar to the other HGCs described
earlier. In Stage 2, at any given time instant, energy is transferred to the
L3P D1 DIBC LS CM1

D0
Z3 DM1 DM2
Clift
L2P CM2
Stage 2 L +
Z2 C0 O V0
Dlift Stage 1 A -
L1P D
+ Z1
Vin
-

multiplier capacitor CM2 and subsequently to the load from at least one
secondary winding.
The detailed operating principle, characteristic waveforms, and design
details are elaborated in [40]. Obviously, the overall voltage gain provided
by HGC-4 is the sum of voltage conversion ratio values of the two stages.
The voltage gain contributed by Stage 1 is given by:
3
VStage1 = Vin (3.34)
1− D
In Stage 2, the secondary winding and VMC contributes to voltage gain

enhancement. Generally, when one CI is employed with a VMC embedded
across the secondary winding, the voltage developed across CM2 will be due
to the voltage induced across the secondary winding and CM1. Thus, voltage
developed across CM2 is quantitatively expressed as:
 2nk 
VCM 2 = V (3.35)
 1 − D  in
In the proposed HGC-4, since all three primary windings are coupled
to the same secondary winding, each primary winding contributes to
energy storage and, consequently, voltage build up across the multiplier
capacitor CM2. Hence, the magnitude of voltage developed in Stage 2 is
expressed as:
 2nk  6nk
VStage 2 = 3 × V = V (3.36)
 1 − D  in 1 − D in
From (3.34) and (3.36), the overall voltage gain is obtained as:
VO  3 + 6nk 
M HGC −4 = = (3.37)
Vin  1 − D 
where k is the coupling co-efficient of CIs, D is the duty ratio of switches,

and n represents the turns ratio of CI.
3.4.4.1 Voltage Stress on Devices

In the proposed HGC-4, as a multi-winding CI is introduced, the voltage
stress on the semiconductor devices needs to be investigated. When the
switches are turned OFF, they are subjected to voltage stress. Voltage stress
on switches Z1, Z2, and Z3 are expressed as:
3 1
VZ1 = VZ2 = VZ3 = Vin = V0 (3.38)
1− D 1 + 2nk
Diodes D1 and Dlift are subjected to stress levels similar to HGC-3.

Voltage stress on the diode DM1 and DM2 is given by:
2nk
VDM 1 = V0 − VClift = V0 (3.39)
1 + 2nk
VDM 2 = V0 − VCM 2 (3.40)
3.4.4.2 Current Stress on Devices

By now, it is a well-known fact that the introduction of voltage-lift tech-
nique causes unequal current sharing in Stage 1. In the proposed HGC-4,
as a multi-winding CI is employed, analysing the current shared by the
switches presents an interesting perspective. From the basic operating
principle, considering the coupling effect and the conducting sequence,
the individual switch current is expressed as:
Iin
I Z1 = (3.41)
2
Iin
I Z 2 = I Z3 = (3.42)
4
The average current through the multiplier diode DM2 and the output
diode D0 is equal to the output current I0, which is expressed as:
I D0 (avg ) = I DM 2 = I 0 = MIin (3.43)

Whenever switch Z3 is turned OFF, diode D1 conducts and carries cur-

rent for 45% of the total time period. Therefore, current through D1 is
derived as:
I D1 = 0.25 Iin − 0.025 Iin = 0.225 Iin (3.44)
Similarly, whenever switch Z1 is turned OFF, diode Dlift conducts for

about 45% of the total time period. Hence, the current through diode Dlift
is expressed as:
I Dlift = 0.5 Iin − 0.05 Iin = 0.45 Iin (3.45)
Multiplier diode DM1 is located just after Stage 1. Therefore, current

stress on diode DM1 is given by:
1− D
IDM1 = Iin (3.46)
3
The procedure adopted to arrive at the value of passive elements is sim-

ilar to the earlier discussions presented in sub-section 3.4.1.1. In the pro-
posed HGC-4, the turns ratio of the multi-winding CI is computed to be
1.029 to obtain the required voltage gain of 18.33. The practical value of
turns ratio was 1.1 with a coupling co-efficient of k=0.85. The experimental
results of HGC-4 are very similar to the other HGCs presented earlier.
The photograph depicting the top view of HGC-4 is shown in Figure
3.30. IGBTs and diode modules with SOT 227 packages are employed to
facilitate PCB layout with wide tracks (to carry large current) and easier
heat distribution. In fact, the entire bottom layer of the PCB is utilized
for placing the peel and stick type heat sinks which take care of thermal
dissipation. The primary and secondary windings are wound on a single
core and mounted on the PCB to reduce the converter size. Suitable provi-
sions to measure the inductor, input, and output currents are provided. The
overall dimensions of the power converter are 0.293m x 0.23m x 0.055m
(length x breadth x height).
In the preceding sub-sections, the synthesis, design aspects, and exper-
imental results of four HGCs were described. In the next section, the pro-
posed HGCs are compared among themselves to obtain a fair idea about
their operating capabilities.
To
Load
C0
D0
CM1
Z3 DM1 DM2 Inductor
Gate Pulses from Driver Current
Measurement
Z2 Dlift DIBC CM2

Multi Coupled
Inductor
Z1 D1
CLift
To Input
Power Supply
Figure 3.30 Photograph showing top view of HGC-4.
3.5 Operating Capabilities of the Proposed HGCs –

A Comparison
In this section, key attributes of all four proposed HGCs are compared
among themselves to bring out a comprehensive understanding of all four
converters. They are compared on three major aspects, namely: (i) electri-
cal characteristics, (ii) device stresses, and (iii) structural parameters. As
the main objective of the proposed work is to develop converters which
are capable of yielding high voltage gain and simultaneously handle high
power, the voltage gain levels are brought out at first, followed by a detailed
comparison of the above-mentioned major aspects.
3.5.1 Electrical Characteristics

The electrical characteristics of the proposed HGCs such as ideal voltage
gain capability, loss distribution profile, and efficiency are discussed.
3.5.1.1 Ideal Voltage Gain

Figure 3.31 shows the progressive increment in ideal voltage gain values
(obtained with Vin = 60V, D=0.55, n=2.5, k=1 and at P0=3kW) of the pro-
posed HGHP converters. However, to meet the standard DC voltage level
of 1.1kV from a 60V input, the turns ratio value alone was adjusted during
implementation and testing of the proposed HGCs.
Proposed HGC-4
Reduced component count and size
Ideal voltage gain = 40
Efficiency = 89.4%
Proposed HGC-3
Ideal Voltage gain = 23.33
Modular
Efficiency = 92.63%
Proposed HGC-2
1 CI and 2 Simple Inductor
Ideal voltage gain is 17.77
Efficiency = 88%
Proposed HGC-1
Clift enhances M without additional components

Ideal voltage gain is 17.77
Efficiency = 92.3%
Figure 3.31 Progress in voltage gain and key features of proposed HGCs.
Based on the synthesis methodology discussed in Section 3.3, the pro-

posed HGC-1 is synthesised and yielded a voltage gain of MHGC-1=17.77. In
the proposed HGC-1, as the effective contribution to voltage gain is due
to one CI alone, HGC-2 utilised only one CI and yielded the same voltage
gain value of MHGC-2=17.77. With an aim of extracting the energy stored
in the secondary winding of each CI and to achieve higher voltage gain,
an individual VMC network is provided to each secondary winding of
the CIs in HGC-3. Consequently, HGC-3 offers a higher voltage gain of
MHGC-3=23.33 compared to HGC-1 and HGC-2. However, it uses the maxi-
mum number of components. In an effort to reduce the component count,
one multi-winding CI with three primary windings each coupled to one
secondary winding is employed to synthesise HGC-4. Ideally, HGC-4 offers
the highest voltage gain of MHGC-4=40 with the least component count. As
only one multi-winding CI is employed, HGC-4 is the most compact among
all four proposed HGCs.
3.5.1.2 Loss Distribution Profile

The loss distribution occurring in the proposed HGCs are quantified
through (3.28)–(3.31). In this sub-section, the losses occurring in all four
HGCs are compared and discussed in detail to appreciate the operating
efficiency and reasons behind the particular efficient values. In the pro-
posed HGCs, the losses across the semiconductor devices and the CIs are
computed using the expressions (3.28)–(3.31) and their loss distribution is
portrayed in Figure 3.32.
Conduction Loss across Power Switches

HGC-2 suffers from highest conduction loss (76.35W), while HGC-3
operates with the least conduction loss (28.06W) across the switches. In
HGC-2, the switches used belong to a TO-247 package. Inherently, the
switches possessed the highest ON state voltage drop (2.7V). Further, the
coupling coefficient of the lonely CI is also the least (k=0.75) and contrib-
utes to withdrawal of additional current from the supply to meet the power
transfer requirement. Therefore, additional current flowing through the
switches with the highest ON state voltage drop manifested as the maxi-
mum conduction loss occurring across the switches.
The minimum conduction loss on the switches occurring in HGC-3 is
easily understood by flipping the above-described reasons and switches
Loss distribution of the proposed High Gain Converters

53.44
Conduction HGC-1
Losses in various components of the proposed HGCs
76.35
loss in 28.06
switch 72.86 HGC-2
98.30 HGC-3
Switching 96.60
loss in 77.53 HGC-4
switch 148.25
53.94
Loss in 133.88
65.20
diodes
73.94
39.00
Inductor 70.42
59.10
loss 61.34
5.33
Other 8.60
losses 4.10
10.33
250.01
Total 385.85
losses 233.99
366.72
0 50 100 150 200 250 300 350 400

Power (W)
Figure 3.32 Power loss distribution of proposed HGCs.

used in HGC-3 are of minimum ON state voltage drop and CIs possess the
highest coupling coefficient (k=0.875).
Compared to HGC-1 (53.44W), the conduction loss of switches in
HGC-4 (72.86W) is higher. HGC-4 uses a multi winding CI (with k=0.85)
which causes additional current stress on two of the three switches com-
pared to HGC-1, which uses 3 CIs with k=0.88. The use of CI with a
relatively lower value of k and incremental current flowing through the
switches resulted in higher conduction loss on the switches used in HGC-4.
Switching Loss in Power Switches

The switches used in HGC-4 contribute to the highest switching losses
(148.25W), compared to the lowest switching loss which occurs in
Converter 4 (77.53W). Though the coupling coefficient of the multi-wind-
ing CI used in HGC-4 is fair (k=0.85), the manner in which the three
primary windings are coupled to the single secondary winding (coupling
reference indicated as “dots”) leads to the highest voltage stress and resul-
tant switching power loss across the switches.
The switches in HGC-3 enjoy the benefits from (i) the highest cou-
pling coefficient and (ii) a separate leakage energy recycling network.
Consequently, the switching loss is reduced. The switches used in HGC-1
and HGC-2 operate with a switching loss value which is moderate (about
98W); higher than HGC-3, but lower than HGC-4. Evidently, contribution
of the coupling method and leakage energy recycling network results in a
moderate switching loss.
Diode Losses
In HGC-2, the cumulative loss across the diodes amounts to 133.88W and
is the highest among the proposed HGCs. All the diodes used in HGC-2
have a higher ON state voltage drop of 2.7V compared to diodes used in all
other converters. Due to the lower coefficient of coupling, a higher value of
current flows through half of the total number of diodes which are located
at the input side (D1, Dlift, DIBC). The higher current flowing through the
diodes is another cause for higher diode losses.
Though 6 diodes are used in HGC-1 (same as HGC-2), the ON state
voltage drop of the diodes is much less (approximately half of that of HGC-
2). Further, HGC-1 uses CIs with a better coupling coefficient (k=0.88),
which leads to the least diode losses of 53.94W.
HGC-4 possess the second highest diode loss (73.94W). Though diodes
with lower ON state voltage drops are used in HGC-4, the coupling coef-
ficient and the coupling fashion of multi-winding CI influence the diode
losses.
In HGC-3, despite a maximum number of diodes being employed, the

magnitude of diode losses in it is relatively lesser (65.20W) than HGC-2
and HGC-4. The lower power loss on the diodes in HGC-3 is because
of the following reasons: (i) lower ON state voltage drop across diodes,
(ii) better coupling coefficient of CIs, (iii) lower magnitude of current flow
(approximately equal to I0) through a majority number of diodes which are
located in Stage 2, and (iv) reduced voltage stress across individual multi-
plier diodes.
Losses in Magnetic Elements

The coupling coefficient of CIs dictates their losses. HGC-2 has 2 simple
inductors and one CI. However, the power loss across the magnetic ele-
ments in HGC-2 is the highest (70.42W) because the CI in it is wound with
the highest turns ratio (3.5) and lowest value of k (0.75). Further, conven-
tional copper wire is used, as compared to using Litz wire, to wind the CIs
of other proposed converters. In HGC-4, 61.34W of power is lost across
the inductors. The turns ratio of the multi-winding CI is just 1.1 with a
good coupling coefficient, k=0.85. As each primary winding is coupled to
one secondary winding, the magnetic losses are higher, leading to higher
power loss. The CIs in HGC-3 are wound with relatively smaller turns ratio
(n=2) and better k (0.875). Power loss occurring across CIs in HGC-3 is
59.10W. Three CIs with a turns ratio of 3.0 and a coupling coefficient of
0.88 are used in HGC-1. The inductor loss (39W) is the least in HGC-1.
Other Losses
Other losses include loss across capacitors, loss due to stray inductance,
losses in PCB, loss occurring in connecting wires, etc. In all the HGC,
other losses account for about 2% to 2.5% of the total losses.
Total Losses
Total power loss occurring across the proposed converters is reflected in the
practical efficiency values under full load conditions. HGC-2 and HGC-3
respectively operate at 88% and 89.4% efficiency while the efficiency values
of HGC-1 and HGC-4 are 92.3% and 92.63%. The value of various losses
occurring in the proposed HGHP converters is presented in Table 3.1.
3.5.2 Stress on Switches

For the proposed HGCs, the magnitude of input current and output voltage
is higher. To realise an efficient HGC, the voltage and the current stress on
Table 3.1 Loss distribution of proposed HGCs.

Various Loss HGC-1 HGC-2 HGC-3 HGC-4
Components (W)
Conduction Loss in 53.44 76.35 28.06 72.86
Switch (21.38%) (19.79%) (11.99%) (19.87%)
Switching Loss in 98.30 96.60 77.53 148.25
Switch (39.32%) (25.04%) (33.13%) (40.43%)
Loss in Diodes 53.94 133.88 65.20 73.94
(21.58%) (34.70%) (27.86%) (20.16%)
Loss in Magnetic 39.00 70.42 59.10 61.34
Components (15.60%) (18.25%) (25.26%) (16.73%)
Other Losses 5.33 8.60 4.10 10.33
(2.13%) (2.23%) (1.75%) (2.82%)
Total Losses (W) 250.01 385.85 233.99 366.72
the power switches should be lesser to reduce the conduction and switch-
ing losses and achieve higher efficiency.
In the proposed HGCs, all three power switches experience only a frac-
tion of output voltage. This is because the power switches are located in
Stage 1 of the power circuit, near the input, while major voltage gain exten-
sion occurs in Stage 2 which is closer to the output terminals.
The current stress on the switches is also less as the devices used in the
interleaved phases share the total input current. Therefore, power switches
with lower current and voltage ratings with a lower ON state voltage drop
could possibly be employed.
However, keeping in mind the modular expansion that would be
required for the chosen application (DC Microgrids/DC Distribution),
semiconductor modules were used. Obviously, the available modules were
rated for higher voltage and current levels.
In the following sub-sections, the voltage and current stress levels expe-
rienced by the switches used in HGCs-1 to 4 are discussed.
3.5.2.1 Peak Voltage Stress

In HGCs-1 and 2, switches Z1 and Z2 experience a voltage stress which is
equal to 36.36% of V0. Switch Z3 experiences a voltage stress of only 12%
of V0. The difference in stress magnitudes is due to the asymmetrical IBC
structure. Since Stage 1 of HGC-3 is similar to HGCs-1 and 2, the magni-

tude of voltage impressed on its switches is also same. However, HGC-3
offers a higher voltage gain compared to HGCs-1 and 2. Consequently,
when the voltage stress is expressed in terms of output voltage, the switches
of HGC-3 are subjected to a comparatively reduced stress which is 28.58%
of output voltage. All three power switches of HGC-4 endure an equal volt-
age stress of 16.67% of the output voltage.
3.5.2.2 Peak Current Stress

In the four HGCs, the total input current is shared among the three power
switches due to the interleaving technique. In the first three HGCs (HGC-1
to 3), 66.66% of total current flows through switch Z1, while only 16.66%
of total input current flows through switches Z2 and Z3. In HGC-4, switch
Z1 experiences a peak current stress whose magnitude is equal to 50% of
Iin. The remaining 50% of the input current is shared equally by Z2 and Z3.
3.5.3 Structural Parameters

Generally, voltage gain, stress on the semiconductor switches, and effi-
ciency of the proposed HGCs are influenced by the coefficient of cou-
pling, component count, and component utilisation ratio. Therefore, the
above-mentioned structural parameters are discussed below.
3.5.3.1 Coefficient of Coupling (k)

Normally, CIs with tightly coupled primary and secondary windings
introduce low leakage inductance and cause reduced voltage stress on the
switches. Further, the leakage inductance plays an important role in obtain-
ing good voltage conversion ratios besides its obvious and well-known
impact on power transfer ability. The significance of coupling coefficient
on voltage gain is well-understood from (3.31), (3.32), (3.33) and (3.37).
Among the proposed HGC, HGC-1 has the highest coefficient of cou-
pling (k=0.88) and HGC-2 has a poor coefficient of coupling (k=0.75). The
multi-winding CI used in HGC-4 is wound so that a coupling coefficient
of k=0.85 was practically realised. Manufacturing complexities involved in
placing the four windings (three primary and one secondary) on a single
magnetic core resulted in a moderate value of k. The effect of magnetic
elements (involving the coupling co-efficient k) on the operating efficiency
is discussed earlier in sub-section 3.5.1.2.
3.5.3.2 Component Count (CC) and Component Utilisation Ratio

(CUR)
Generally, obtaining a higher voltage gain using a lesser number of compo-
nents is preferred, owing to the higher operating efficiency, simple struc-
ture, reduced size, and economic benefits of the converter. However, in
hybrid HGCs like the ones presented in this chapter, voltage gain, power
handling ability, and efficiency requirements contradict the component
count more often than not. Therefore, the ratio of voltage gain to com-
ponent count as an index to judge the way components are utilized in the
proposed HGCs is explored.
HGC-4 utilises the least number of components [14], while offering the
highest ideal voltage gain of 40. Therefore, it has the highest component
utilisation ratio. Employing one multi-winding CI has resulted in higher
component utilisation. HGC-3 uses the highest number of components
[24] while offering a relatively higher voltage gain of 23.33. Incidentally,
HGC-3 has the least component utilisation ratio of 0.97. Introducing indi-
vidual VMC networks across each secondary winding of the CIs requires
more components. HGCs-1 and 2 employ16 components each to provide
Table 3.2 Key attributes of proposed HGCs.

HGC-1 HGC-2 HGC-3 HGC-4
Voltage Gain Expression 3 + 2nk 3 + 2nk 3(1 + nk ) 3(1 + 2nk )
1− D 1− D 1− D 1− D
Ideal Voltage Gain (M) 17.77 17.77 23.33 40

(n=2.5, k=1, D=0.55)
Output Power (kW) 3 3 3 3
Peak Voltage Stress 37.52 37.52 28.58 16.67
(% of V0) (w.r.to Ideal
Output Voltage
Peak Current Stress 66.66 66.66 66.66 50
(% of Iin)
No. of CIs 3 1 3 1
Total Component Count 16 16 24 14
(CC)
Turns Ratio 3 3.5 2 1.1
Ideal Voltage Gain (M)

Electrical Characteristics
40
Application/Most Voltage HGC-1
Micro Grid
Appropriate (1.1 kV) 23.3
Variation (%)
4.54 HGC-2
Voltage Levels HGC-3
3
HGC-4
2.67
Data Centres 17.7 Efficiency (%)
(380 V)
92.6
1.5 92.3
89.4
88
Residence 36.3
(240 V) 0.97 0.75 Peak Switch
1.11 16 Voltage Stress
0.85
(% of Vo)
50
17 0.875
2.85
Component 66.6
Utilization Ratio 0.88
Device Stress
Peak Switch
(M/CC)
Current Stress
(% of Iin)
24
Structural Parameters Component Coupling
Count (CC) Co-efficient (k)
Figure 3.33 Comprehensive view of various parameters of all four proposed high gain
converters.
an ideal voltage gain of 17.77 at n=2.5 and have moderate component

utilisation ratios. Table 3.2 presents the key attributes of the proposed
HGCs discussed so far, while their pictorial representation is depicted in
Figure 3.33.
3.6 Salient Features of the Presented High Gain

Converters
To validate the proposed concept, HGCs operating at 100kHz with
60V/1.1kV, 3kW ratings were fabricated and tested. The experimental
results served as proof of the proposed concept. In the proposed HGCs,
all the power circuit elements contribute to (i) achieve higher voltage gain
and (ii) aid in handling more power. Due to the gain extension techniques
adopted, the switches used in the proposed converters are subjected to a
maximum voltage stress which is only 36% of the output voltage. Due to
interleaving, the input current ripple is reduced and the switches are sub-
jected to a maximum current stress which is only 33% of the input current.
The key attributes of all four proposed HGC are compared among them-
selves to bring out their common, unique, and salient features.
Some of the salient features of the proposed HGCs are:
(i) Their ability to provide high voltage gain and handle high
power simultaneously
(ii) Modular structure and ease of expansion
(iii) Their suitability to meet the voltage levels of DC microg-
rids and stand-alone and grid connected PV fed systems
3.7 Summary and Outlook

Electrical energy output from most renewable energy sources (RES) are
DC in nature. Further, most of the modern-day loads are also natively DC
in nature (i.e., they consume DC power for their working). When the elec-
trical energy is consumed in DC form, an intermediate AC-DC conver-
sion stage which is used nowadays is avoided. Therefore, there is a bright
possibility of locally distributing electrical power generated from RES in
DC form without the necessity of long transmission lines and to meet the
future energy demand by integrating RES to DC microgrids. Moreover,
DC microgrids are advantageous compared to AC systems because of the
below mentioned nature of loads:
(i) During AC to DC conversion, about 6% of total energy

consumed is wasted in some manufacturing units [41].
(ii) When operated from DC power, data centres are more
efficient and cost effective [42].
(iii) Modern day appliances like LED lamps, LED televisions,
laptops, mobiles, computers, etc. are native DC loads,
but they are supplied from AC mains. Hence, an AC-DC
power electronic interface is invariably used at the front
end. In recent years, to enhance the operating efficiency
of domestic appliances (like air conditioners, washing
machines, etc.), inverter fed variable frequency drives
(VFDs) have begun to proliferate. Such applications also
require an AC-DC power electronic interface at their
front end when they are fed from conventional AC power.
When from a DC supply, the front-end AC-DC conver-
sion stages present inside the modern-day loads are not
necessary. Therefore, losses, complexity, size, and cost of
the appliances are reduced besides increasing the overall
efficiency of the system. As DC native loads account for
20% of total electricity consumers in residential and com-

mercial buildings [43], a huge impact/benefit is envisaged.
(iv) Besides household appliances, heating, ventilation, and
air-conditioning (HVAC) systems and electric vehicle
(EV) charging stations are also well adapted to operation
in DC form [44].
DC microgrids not only enhance the power transfer capability, but also
make the grid more stable and reliable [45, 46]. Some methods to shift/
adapt towards DC distribution are as follows:
99 Present AC distribution lines can be upgraded to DC with

minor infrastructure changes to increase power transfer
capacity.
99 In residential and commercial buildings, adding a supple-
mentary DC electrical network is perfectly achievable (due
to existing multiple wiring networks).
99 In long time perspectives, off-grid DC microgrid systems
will be more reliable.
99 The quality of the power delivered to the customer will be
improved [47].
99 Reduced distance between the power generation and loads
reduces utility bills.
99 Therefore, power consumption in DC form has a prosperous
future and the potential to efficiently and effectively co-exist
with AC systems [48, 49].
Thus, co-existence of DC along with AC systems proves to be an eco-

nomical and realistic option [50]. Practical realisation of such a DC based
system may have initial hiccups and challenges. Following are some of the
anticipated challenges and possible solutions.
99 1.1kV DC is attractive at distribution levels. However, addi-

tional safety measures and active protection systems are
required to handle DC voltage levels which are >75V DC
[51].
99 High current DC circuit breakers (CB) and suitable protec-
tion schemes are rapidly evolving.
99 Manufacturing of DC compatible appliances has begun and
is in the nascent stage.
99 Standardisation of voltage levels is in the teething stage.

Nevertheless, various professional bodies like EA, ETSI,
IEC, and IEEE are involved in fixing the appropriate policies
and standards [52].
99 Minor modifications may be carried out in the present appli-
ances or devices to make them “DC- ready”.
To conclude, in this chapter, four novel hybrid high gain DC-DC con-
verters were developed with the aim of integrating PV sources to a DC
microgrids/DC distribution system. Based on the gain extension methods,
their methods and characteristic features, some techniques were short-
listed. A detailed procedure to synthesise the proposed high gain convert-
ers was described. Using the synthesis procedure, a hybrid combination of
interleaved structure which used coupled inductors, a voltage lift capaci-
tor, and a VMC network was used to develop HGCs which yielded a high
voltage gain of 18.33 and delivered 3kW power to the output. Shifting and
adapting towards DC distribution from the conventional AC system has
numerous prospects, as discussed. The presented HGCs are expected to
serve as an important milestone in adapting an efficient renewable energy
based DC distribution system.
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4
Design of DC-DC Converters for
Electric Vehicle Wireless Charging
Energy Storage System
T. Kripalakshmi and T. Deepa*
School of Electrical Engineering, Vellore Institute of Technology, Vandalur-

Kelambakkam Road, Chennai, India
Abstract
Electric Vehicles are a suitable solution for sustainability in transportation appli-
cations. The era of wireless power transfer in free space began with the evolution
of Tesla coils being energized by microwaves. High-frequency inverters act as the
electrifier for high power wireless charging. DC-DC converters play an indispens-
able role in converting the AC power from a high-frequency inverter to DC power
to the battery or the energy storage system in the vehicle. The converter’s design
will be based on the battery and energy storage system’s charging conditions, con-
stant current, and constant voltage operating conditions and the State of Charge
(SOC). The non-linearity in the system can be implemented with a sliding mode
control. The topology of the converters with the hybridization of the energy storage
systems is also discussed. The models are evaluated with simulation in MATLAB
with the control system toolbox. The energy storage system includes batteries and
supercapacitors. The concept of bi-directional converters for regenerative braking
mode constraints is also considered for digital closed-loop implementation. The
chapter comprises topologies of DC-DC converters’ roles for wireless charging of
batteries, digital controls with parameter evaluation, and sliding mode controls for
the system’s dynamic control.
Keywords: Energy storage system, electric vehicles, inductive power transfer,
power converters, sliding mode control
127
4.1 Introduction
The wireless charging technologies are of two types: far-field and near field.
Inductive coupling power transfer (ICPT) is a promising method for wire-
less power transfer. It comprises of a high-frequency inverter, primary and
secondary resonating coils, a matching network, a rectifier, and a battery.
The matching network is known as the compensation network for reduc-
ing the inductive coupled coils’ leakage current [1–4]. The capacitors are
used in the compensation network with various combinations to reduce
the inverter’s VA rating. Operating ICPT in resonance is the main chal-
lenge for its commercial applications. The matching network is added to
Off-board On-board
charger charger
circuit circuit
Charging Pad
DC supply Rx
HF Rectifier and
Battery Load
Inverter Track Pad DC-DC converter
Tx
Coupling network
Figure 4.1 Block diagram of ICPT system.
1. Push-pull
Conventional
2. Forward
3. Flyback
Bridge type
Z-source
Not suitable for BEV
Isolated
Suitable for BEV
SAHVC
DC-DC
Multiport
Non-Isolated
1. Boost
Conventional 2. Buck-Boost
3. Cuk
4. SEPIC
Interleaved
Multiport
Figure 4.2 Classification chart of DC-DC converter topologies.

Converters for EV Energy Storage System 129
Table 4.1 Comparison of topologies based on parameters.

Number of Stress in
Topology Suitability in Power Gv Cost Control components circuit
ICPT HESS Bidirec Ease of Type of Control SW & D L, C
tional Control
Power
Flow
FBC Y N Y 30kW H M Y Phase shift and 4&4 1,2 H
asymmetrical
PWM
ZSC Y N Y >10kW Li M Y Phase shift, dead 4&0 0,5 L
time control,
asymmetrical
PWM
SAHVC N N N >3.5kW Li H N Complex SAC 6&0 0,3 L
control
MPC N Y Y 30kW H H N Phase shift PWM 12&0 2,1 L
BC Y N N 30Kw L L Y Single pulse control 1&1 1,1 L
IBC Y Y Y 30Kw H M Y Phase shift PWM S1… L1… L
Sn&D1… Ln,1
Dn
MDC Y Y Y 30kW H H Y Phase shift PWM 8&0 4,1 L
Y-Yes, N-No, H-High, L-Low, M-Moderate, Li-limited, PWM-Pulse width modulation, SW-switch, D-diode, L-inductor, C-capacitor, SAC-sinusoidal
amplitude control.
achieve control on the loosely coupled coils’ primary and secondary side
(that acts as a basic transformer but is separated in the air gap with a dis-
tance) in the circuit. By choosing a suitable DC-DC converter, the volt-
age and power levels can be controlled. The power flow from the primary
converter (high-frequency inverter) to the secondary converter (DC-DC
converter) to the battery is controlled by DC-DC converters.
A general description of ICPT is given in Figure 4.1, which illustrates the
DC-DC converter’s role in the circuit. The receiving side control is focused
based on the battery or the storage type embedded in the vehicle. The con-
verter’s design has to be low in size and weight ratio and simple in structure.
A typical storage system is used based on the load type, i.e., light-duty and
heavy-duty vehicles. For heavy-duty vehicles, the storage system must not
be bulky and must be low cost as the vehicles takes a huge load and driving
range. For low-duty vehicles, the converter design’s efficiency must be high
and independent of the load characteristics. The onboard charged circuit
has to be designed with cost-effective power electronics parts. The battery
storage system and the battery management system (BMS) will increase
the design cost for ICPT systems. To achieve a high-efficiency IPT battery
charging, the power converters used at the transmitter and receiver sides
must be designed with a high conversion ratio. DC-DC converters’ indis-
pensable role is to regulate the voltage, current, and power fed to the battery.
The topologies classification is shown in Figure 4.2. The various topologies
are discussed in this section. The comparisons based on their components,
advantages, and drawbacks with their suitability for battery electric vehicle
(BEV) ICPT applications [5–7] are enumerated in Table 4.1.
4.2 Isolated Converters

4.2.1 Bridge Type
These converters are provided with isolation between the source and the
load. The isolation can be capacitor isolation or transformer isolation
which is shown in Figure 4.3. The full-bridge (FB) type is a suitable con-
verter for battery vehicles. The negative half cycle of the voltage waveform
will help in the regenerative braking mode of the vehicle. It pertains to
bidirectional power flow control [8, 9]. The duty cycle (D) of the converter
should be greater than 50%. The converter operates with a zero voltage
switching (ZVS) condition, i.e., the voltage in the next switching period is
forced to zero at the ton instant of the switch. The pulse width modulation
S1 Vg3 S3
Vg1
a
Vdc irab
RL
C
S2 S4
Vg2 Vg4
b
Figure 4.3 Isolated DC-DC full-bridge converter (FBC).
technique (PWM) is incorporated to maintain the ZVS condition and pro-

vide control signals to the switches of the converter.
4.2.2 Z-Source Type

The Z-source converter shown in Figure 4.4 is operated with ZVS and Zero
current switching (ZCS) condition. It is like the operation of dual bridge
converters, and also it pertains to bidirectional power flow control. The
architecture is constructed like the two half-bridge converters connected
between the source and the load with isolation [10]. The converter and
control operation is better with the FBDC, as the diode rectifier circuit is
not needed. The diode rectifier deteriorates the performance of the con-
verter with high conduction losses. The design of capacitor C0 is large in
volume and size. The power density of the battery can be increased when
connected with this converter. It is not suitable for applications >10kW.
The PWM shown in Figure 4.5 can be implemented for switching.
4.2.3 Sinusoidal Amplitude High Voltage Bus Converter

(SAHVC)
The voltage gain is fixed so that high voltage will be supplied to the bat-
tery. The high voltage bus converter is used for power levels < 3.5kW. The
circuit is complex with multi-windings of the transformer connected for
isolation as shown in Figure 4 6. The power transformer is attached to each
switch for fixating the high step-up voltage. The control is not as simple as
in FBDC and ZVSDC. It involves complex sinusoidal amplitude control
(SAC) for achieving a pure sinusoidal waveform. The converter’s operating
frequency is in padlock with the resonant frequency of the resonant tank
present in the circuit [11]. It is similar to the FBDC and the half-bridge
converter is cascaded with multi-windings and isolation.
C3
C1 Vg3
S1 S3
Vg1
RL
C0
Vdc
S2 S4
Vg2 C4
C2 Vg4
Figure 4.4 Isolated DC-DC Z-source converter (ZSC).
Vg1,Vg2
0° 180°
Vg3,Vg4 T1,T2 T3,T4 T1,T2 T3,T4
90° 360°
Vo
Vdc
T/2 3T/2 2T
T
Vdc
Figure 4.5 Phase shift PWM for switching.
S5
S3
Vdc S1
RL
C0
Cres
S4 S6
S2
Figure 4.6 Sinusoidal amplitude high voltage isolated converter.

S1 S3
S1 S3
Vdc Battery
C0
S2 S4
S2 S4
S1 S3
Storage
system
S2 S4
Figure 4.7 Isolated multi-port converter (MPC).
4.2.4 Multiport Converter

A multi-winding isolation shown in Figure 4.7 is provided between the
source and the load. The number of input ports is increased and inter-
connected by a multi-winding transformer (linear transformer). The input
source is connected by an interleaved technique where the input current
will be split to the converter legs with the identical inductors. The paral-
lel shifting is carried out for the converters connected with hybrid energy
storage systems (HESS). It pertains to bidirectional power flow control.
The number of components increases and the complex switching tech-
nique makes it difficult to apply for a single battery charging application.
4.3 Non-Isolated Converter

4.3.1 Conventional Converters
These converters are used in medium and high power applications where the
voltage level is also in a moderate range. The conventional Cuk and SEPIC
converters are not suitable for BEV, but find application in energy storage
and hybrid energy storage systems. These converters are current-fed con-
verters [12, 13]. For step-up and step-down applications, the buck-boost
LB
DB
CB Battery
SB
Figure 4.8 Non-isolated boost converter (BC).
converter is used and it circulates a high inrush current in the circuit and
affects the output current delivered to the battery. Operating at resonance
can be employed with a SEPIC converter. The number of energy storage
elements is high and requires a large volume of filter capacitor, which
increases the size and volume of converters. An uncomplicated and con-
venient structure that is the most pervasive in BEV applications shown
in Figure 4.8 is the boost converter (BC). The only drawback is that the
voltage gain is low, which is < 1. The single switch creates an ease in design
relative to architecture, cost, and control strategy. The circuit operation and
switching control technique depend on the fine-tuning of the duty cycle D.
4.3.2 Interleaved Converter

To increase the voltage ratio and for high step-up operation, interleaved
converters are introduced for battery applications [14]. The input current
source is cleaved into the path of individual inductors connected to the legs
of the converter. All inductors are wound on a separate magnetic core. The
voltage gain is improved in the ratio of 1: 2 with two inductors, as shown
in Figure 4.9. These are also referred to as interleaved N-phase converters
where N denotes the number of phase or the number of inductors used for
Dn
D1 D2
L1
L2 Battery
C0
Ln
S1 S2 Sn
Figure 4.9 Non-isolated interleaved boost converter (IBC).

the interleaving technique. The size of energy storage elements is reduced

and with an equal number of inductors (L1…. Ln ). The current delivered
is equalized, which is an essential feature for the battery charging scenario.
360°
The switches S1 and S2 are phase-shifted with the expression . The
N
control signals to the converter switch are also interleaved, which results in
low input current and output voltage ripples.
4.3.3 Multi-Device Interleaved

The converter is like the multiport isolated seen in Figure 4.7 but with dis-
tinction in the internal stage of the converter topology with interleaving
technique and non-isolation as shown in Figure 4.10. The switch count is
high and makes it difficult to operate in transient conditions. Control and
synchronization of the switches are difficult. It is suitable for energy storage
and hybrid storage systems. The switch count is increased, but the resonant
and storage elements are reduced. It is less complex compared to MPC.
L1
S1
S3
Cf
Battery
L2
S2 S4
L1
S1 S3
Storage L2
system
S2 S4
Figure 4.10 Non-isolated DC-DC multi-device converter (MDC).

4.4 Design of DC-DC Converter with Integration of

ICPT and Battery Implementation with Digital
Control Loop
4.4.1 Design of DC-DC for BEV with the Integration of ICPT
From the Table 4.2 enumerated above, the BC is the most suitable for ICPT
charging of electric vehicles. Figure 4.1 is replicated as the simulation cir-
cuit shown in Figure 4.11, which is done in MATLAB Simulink with a
rating of 3.7 V per cell of lithium battery. The model with 6.2Ah is taken as
a load. The high-frequency inverter is designed with the ICPT standards
of 85kHz. The design includes an H-bridge inverter model, resonant trans-
mitter, and receiver coils with k<0.3 and a diode bridge rectifier for DC
conversion to supply input voltage to BC. The BC converter’s current and
voltage response with battery SOC (State Of Charge) is given in Figure
4.12. SOC provides the status of the amount of energy stored in the battery.
The BC is designed so that the battery output voltage is 200V. The converter
design equations are given in Equations (4.1)–(4.6). The compensation
network for ICPT applications has been researched with various topolo-
gies compared to high power transfer efficiency [15–18]. The most suitable
type of compensation in ICPT for the vehicle is an S-S (series-series) type
and T-type network LCC (Inductance Capacitance Capacitance). Storage
elements in the compensation network are designed based on the invert-
er’s operating frequency and resonance frequency of the coils [19–21]. The
DC-DC converter’s switching frequency can be designed based on the res-
onance frequency phenomenon or the conventional BC design equations
based on the required input and output voltages.
The design of BC is implemented in Figure 4.11
When S1 is on Vin – VL = 0 (4.1)
When S2 is on, Vin – Vout = VL (4.2)
ton
1
VC =
C ∫
0
iC dt + VC (t = 0) (4.3)
L∆I L∆I (4.4)

VL = ; VL = ;
ton toff
(1 − D )Vout
L= (4.5)
f SW ∆I Lmax
Table 4.2 Merits and demerits of DC-DC converter topologies.

Topology Dominant feature Deterrent feature
FBC • EMI is reduced • HFT increases leakage
• Core loss is reduced inductance
• A clamping circuit is needed
ZSC • ZVS operation • The output voltage is less
• Soft switching • The size of the capacitor is large
• Increased weight and volume of
the converter
SAHVC • EMI is reduced • The multi-winding structure
• High power density increases the complexity
• Low dv/dt, di/dt • Fixed voltage ratio
• Switching loss is reduced
MPC • Input current and output • Duty cycle D is sensitive to load
voltage ripple is low • Increase in component count
• High power density • Difficult in synchronization of
the switches
BC • EMI is reduced • The capacitor filter size is large
• Cost-effective • Low voltage gain
• Output voltage ripple
is low
IBC • An equal amount of • Duty cycle D sensitive to load
current delivered to the • The magnetic core of inductor
load design influences the output
• The voltage ratio is high parameters
• BW of the control loop
can be increased
• Suitable for multi-input
system
MDC • Single port converter • Sensitive to duty cycle D
• High efficiency variation
• Reduced heat sink size • The analysis is complex during
• EMI is reduced dynamic conditions
EMI-Electromagnetic Interference, HFT-High-frequency transformer.
In1 Out1
Out1 A + Conn2
Out2 Conn1
Conn1 Conn2 +
Out1 <Voltage (V)>
Out3 Conn3 Conn4 m <Current (A)>
Conn4 Conn3
Conn1 Conn2 <SOC (%)>
B - –
Out4
Conn2 resonant tank and coils
Conn3 Conn1
Source Conn4
High frequency inverter BC
Figure 4.11 Simulink of ICPT with BC model for BEV.
<Voltage (V)>
250
200
Vbat (V)
150
100 CV
0 1 2 3 4 5 6 7 8 9 10
time (s)
<SOC (%)>
65
60
Soc (%)
55
50
0 1 2 3 4 5 6 7 8 9 10
time (s)
<Current (A)>
500
0
Ibat (A)
-500
0 1 2 3 4 5 6 7 8 9 10
time (s)
Figure 4.12 Voltage and current responses of BC with charging conditions of battery.
where inductor of the converter is L = 400e−6H, ripple of current in the

inductor is Δ. ILmax = 12.5%, switching frequency is fSW = 20kHz, and D
is duty cycle of the switch. The power flow to the battery is controlled by
adjusting the D of the switch. It is usually kept at 50% so that the switch
turn on and turn off time is equal. The nature of switching is classified
as soft switching and hard switching where frequent turn on and turn off
leads to hard switching and the converter must also be designed based on
this aspect.
DI out (4.6)
C=
f SW ∆Vout
where the capacitor is C = 1000e−6F and ripple of the voltage of the capac-
itor is ΔVout = 12.5%.
(1 – 0.5)Vout = (400e−6 × 20e3 × 12.5)

= 200V
Iout × (0.5) = (400e−6 × 20e3 × 12.5)

= 500A
4.4.2 Digital Control with Sliding Mode Control Approach

There are many techniques available in the literature for the control of power
electronics converters. Of these, the controls included PLL (Phase-Locked
Loop), phase shift control, constant, and variable frequency control. The
variable frequency control is implemented with hysteresis current mode.
The constant frequency control is implemented with constant valley, peak,
and average current-mode controllers commonly used in interleaved con-
verters [22, 23]. The digital control approach with the closed-loop feedback
principle is given in terms of the output signal to be given as a pulse to the
switch of the converter. Advanced controllers are implemented to deter-
mine the battery’s optimal charging current and control algorithms like
genetic algorithms and optimization algorithms are implemented so that
the charging is more efficient. Predictive controllers are used to test the sys-
tem with its dynamic behaviour, like determining the D of the next switch-
ing cycle with present samples of D. The sliding mode control approach
can be implemented with hysteresis mode. The sliding mode approach is
implemented in variable structure systems. For the design of ICPT with a
DC-DC converter, BC is taken for simulation in MATLAB Simulink and
LB
i u=1
E v R
CB
u=0
Figure 4.13 State-space model of BC with switching action.
the control loop with a sliding mode control is implemented. The proce-
dure involves the mathematical model of BC, as shown in Figure 4.13.
The control loop’s design and implementation are taken with boost con-
verter ideal switch conditions at ton and toff with u 1 and 0, respectively.
By applying KVL for Figure 4.13, the voltage equation in differential
form is given in Equations (4.7) and (4.8).
di
L= = −uv + E (4.7)
dt
dv 1
C= = ui − v (4.8)
dt R
i is the input inductor current, v is output voltage, and u is the switch

position function.
State-space matrix description of the converter:
 −v 
 0 0     E 
d i    i +  L  u +  L  (4.9)
 = −1  v   i
dt  v   0   
 RC   
 L    0 
 
For the state-space and sliding mode approach, the x1 and x2 are assigned
to the circuit’s energy storage elements. Input current i →x1 and v→x2.
 E 
 0 0   E   
f ( x ) =    x1    L
−1   x2 +  L  =   (4.10)
0   0   − x 2 
 RC     
 RC 
 − x2 
 
L
g (x ) =   (4.11)
 x1 
 C 
 
For the average model, the normalized equation is given in Equations

(4.12) and (4.13).
x 1 = ux 2 + 1 (4.12)
1
x 2 = ux1 + x2 (4.13)
Q
 1 
   −x2 
f (x ) =  1  , g ( x ) =   (4.14)
− x2  x1 
 Q 
The dimension of the system and context of the switching action rep-
resents a sliding surface
S = {x ∈ Rn|h(x) = 0} (4.15)
The coordinate function is decided by the dimension and the equilib-

rium point. The desired equilibrium point is the output voltage, which is
the x2 variable.
h( x ) = x 2 − x 2 (4.16)
The sliding dynamics are given by the equation
∂h 1
L f h( x ) = f (x ) = x2 (4.17)
∂ xT Q
∂h
Lg h( x ) = g ( x ) = x1 (4.18)
∂ xT
u -K- + 1
-
+ IL
–
10
Figure 4.14 SMC control for BC converter.
10
IL(A)
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t(s)
4
Ibat(A)
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t(s)
200
vbat(V)
100
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t(s)
1
u(t)
0.5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t(s)
Figure 4.15 Sliding mode control responses of BC.

The equivalent control smooth feedback law is given in Equation (4.19).
L f h( x ) 1  x 2 
u( x ) = = (4.19)
Lg h( x ) Q  x1 
The function u (x) acts as a feedback function in the control loop. The
Simulink representation of the control is given in Figure 4.14. The control
is calculated with the present D from the switching period with the sam-
ples of IL inductor current. The voltage of the battery, current in the battery,
and inductor input current from the simulation are given in Figure 4.15.
4.5 Design of Converter with Hybrid Energy Storage

System and Bidirectional Converter
The energy storage for the electric vehicle is incorporated to reduce power
demand. The hybrid storage comprises of a supercapacitor, fuel cell, ultra-
capacitor, and battery. The battery storage cannot satisfy the demand for
energy needs in the future. Hybridization is the alternative solution for
good energy management and it also reduces the battery size embedded
inside the vehicle [24–26]. The performance of voltage and life span of the
battery is increased with hybrid fusion of a supercapacitor. The use of a
bidirectional converter helps reuse the energy dissipated and is used in the
regenerative braking mode of the vehicle. Either an MPC or MDC converter
D
D
g
[I_B]
Out1 4 3
In1
Out1 A +
Conn1 +
[V_B]
Out2
S
<Voltage (V)>
Conn1 Conn2 +
V
m
Out1 - <Current (A)>
Out3
Conn4 – [SOC_B]
Conn3
Conn1 Conn2 <SOC (%)>
B -
Out4
Conn2 resonant tank and coils [Q4_B] Battery
Conn3
Conn4
Source
High frequency inverter
D
D
g
[Q2_B]
4 2
S
[VDC]
[Q1_SC] [Q3_SC]
[V_SC]
D
D
g
<Voltage V> 5 7
+
<Current I>
S
[I_SC]
m
<SOC %>
–
[SOC_SC]
[Q4_SC] [Q2_SC]
Supercapacitor
D
D
g
8 6
S
Figure 4.16 Simulation model of MDC for supercapacitor and battery storage system.
is suitable for HESS and bidirectional transformers, but high-frequency

transformers (HFT) in MPC for isolation make it more complicated for
ICPT. Bidirectional converter D is controlled by delay time control [27,
28]. Implementation of fuel cells for hybrid storage requires a full-bridge
DC-DC converter and isolation is needed. For ICPT, supercapacitor and
battery storage systems are ideal one and they are simulated in Simulink
as shown in Figure 4.16, similar to the battery design in Section 4.2. The
control algorithm shown in Figure 4.17 is used for the generation of pulses
of the switches. The converter model, control algorithm, and responses of
the converter are given in Figure 4.18.
Iref Ib_ref Ib_er
1 + PI(s) + PI(s) D P NOT 1

VDCref – – S1,S4
3 2
2 IB S3,S2
VDC
+ +
– +
NOT 3
Isc_ref S1,S3
4 +
Isc_er 4
V_B × × – PI(s) D P
5 ÷ S2,S4
V_SC 6
I_SC
Figure 4.17 Bidirectional power flow control for MPC with HESS.
32
ISC(A)
31.8 20
IB(A)
31.6
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
time(s) -20
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
99 time(s)
50.03
SOC(%)
98.96
50.02
SOC(%)
98.9 50.01
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
50
time(s)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
800 time(s)
600
400
VSC(V)
200 200
VB(V)
0 0
-200 -200
-400
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
time(s) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
time(s)
Figure 4.18 Simulation responses of SC and battery storage system with MDC converter
implementation.
4.6 Conclusion
The chapter pivots on the topologies for DC-DC converters solidly for
wireless charging of electric vehicles with battery modelling. The design
of DC-DC converters regulates the voltage and current that increase the
performance of the battery. The comparative analysis renders the battery
and power electronics designer using a suitable DC-DC converter based
on the requirements. The HESS with the MDC converter model gives the
best solution for energy demand. The control of the converter is included
with the dynamic state model and the sliding control regulates the battery
and operates in the constant voltage (CV) mode of the battery. For the fur-
ther accurate design of these converters for practical and industrial appli-
cations, different battery specifications are visible as a commercial product
that can be taken and tested in a simulation environment.
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5
Performance Analysis of Series Load
Resonant (SLR) DC–DC Converter
A. Mitra*, S. Bhowmik, A. Halder, S. Karmakar and T. Paul
Department of Electrical Engineering, Narula Institute of Technology,

Kolkatta, India
Abstract
A Series Load Resonant (SLR) DC-DC converter with soft switching topology is
designed and it exhibits sinusoidal current wave shape either in CCM or DCM
depending upon the selection of the passive components, on which resonant fre-
quency depends. For a fixed switching frequency, it has been found that if Ts > 2T0,
the converter will operate in discontinuous current conduction mode of operation
and switches are turned on at zero current and will be naturally turned off due
to L-C tank circuit. But in case of T0 < Ts < 2T0, the inductor current becomes
continuous and the next half cycle will start before ending of the previous cycle.
Again if Ts < T0, the inductor current becomes almost sinusoidal and less har-
monic distortion. But in both the continuous current conduction mode, the size
of the inductor becomes significantly large. Furthermore, a compromise between
sizing of the passive components and the switching frequency can be carried out
so that overall compactness of the converter with satisfied performance has be
obtained in experimentation.
Keywords: DC-DC converter, harmonic distortion, series load resonant
5.1 Introduction
One of the significant considerations in the power electronics field is to
maintain energy efficient switch mode power supplies. It has literally moti-
vated next generation engineers to come up with new designs that drasti-
cally improve power conversion. In distributed energy generation systems
149
like solar systems, fuel cell power systems, and vertical axis aero-generators,
DC-DC Series Load Resonant (SLR) converters widely used to achieve bet-
ter power quality. SLR converters are a subset of DC-DC converters that
can be operated with either Zero Voltage Switching (ZVS) turn on, i.e.,
above the resonant frequency or Zero Current Switching (ZCS) turn off,
i.e., below the resonant frequency. Thus, switching losses are minimized
and the converter is particularly applicable for high power and high fre-
quency operation. To allow bi-directional energy transfer, an uncontrolled
rectifier is used, which controls the output power [1].
Depending on the switching frequency and resonant frequency, current
through the inductor may be continuous or discontinuous. The choice of
diodes depending upon the improvement of efficiency for these modes of
operations has been described in [2] where a comparative study has been
analyzed with general purpose P-N diodes, Schottkey diodes, and Super
Barrier Rectifier diodes in the circuit.
To achieve fast tracking converter output voltage, a fuzzy based con-
trol algorithm is very much suitable so that irrespective of sudden load
disturbance, the converter can establish a satisfactory output voltage with
efficiency [3].
This proposed work investigates an SLR converter containing a tank cir-
cuit, as shown in Figure 5.1, with soft switching topology that is used for
DC-DC conversion. The SLR converter consists of a half bridge DC-AC
inverter followed by an L-C tank circuit and it converts the AC to DC volt-
age through an uncontrolled rectifier to control output DC energy. A filter
capacitance may be introduced at the output of the uncontrolled rectifier
to minimize DC voltage ripple. This analysis has been done considering
all power electronic devices that are ideal so that there is no switching loss
in the device. The series L-C tank circuit is connected in series with the
output of the DC-AC half-bridge inverter that will provide a resonant fre-
quency and characteristic impedance.
Vdc
D + iL
2 T + + Vc-
Cf R
Lr Cr
Vdc
D - Vin Vo
2 T -
Figure 5.1 Series load resonant DC-DC converter.

Series Load Resonant Converter 151
5.2 Theoretical Background

As the L-C tank circuit is connected at the output of the half bridge inverter,
it is obvious that the current through the inductor will be sinusoidal in
nature. Depending on the ratio of switching frequency ωS to resonating
frequency ω0, there are three possible modes of operation.
a) Discontinuous Conduction Mode (DCM) of SLR Converter →

Switching frequency is less than half of resonating frequency:
1
This operation defines ω s < ω 0 , i.e., Ts > 2T0. As the tank circuit con-
2
tains Lr and Cr, the current and voltage waveforms should be sinusoidal in
nature. In a steady state when switch T + is turned on, the inductor current
starts increasing from its zero initial value. As the input voltage of the half
bridge inverter is Vdc, the capacitor remains operational until the voltage
across it reaches equal to the DC supply voltage. Now, applying KVL to the
circuit of Mode I shown in Figure 5.2 when the switch T + is conducting,
Vdc di (t ) 1
2
= v L (t ) + vc (t ) + Vo (t ) = L L +
dt C∫iL (t )dt + Vo (t ) (5.1)
In frequency domain, Equation (5.1) can be expressed as:
Vdc Vo 1 V (0)
− = L[sI L (s ) − I L (0)] + I L (s ) + c (5.2)
2s s Cs s
where IL(0) = initial inductor current and Vc(0) = initial capacitor voltage.
The inductor current in the frequency domain can be equated as
 V − 2Vc (0) − 2Vo   ω 0   s 

I L (s ) =  dc   2  + I L (0)  2 (5.3)
 2ω 0 L   s +ω0 
2
 s + ω 0 2 
or, in time domain, the inductor current will be
 V − 2Vc (0) − 2Vo 

iL (t ) =  dc  sin ω ot + I L (0)cosω 0t (5.4)
 2ω 0 L
T+ D+ T- D-
Modes of operation
vc Cr Lr Cr
Lr
iL
Vdc
1/2Vdc +
_ iL +
_ Vo 1/2Vdc +
_ iL +
_ -Vo
Vc0= 2V0
ω0t1 ω0t2 I T+ operating II D+ operating

ω0t0 ω0t
Vc0= -2V0
Lr Cr Lr Cr
-Vdc iL iL
-1/2Vdcdc +
_ +_ -Vo -1/2Vdc +
_ +
_ Vo
T0
Ts
III T- operating IV D- operating
I II III IV
1
Figure 5.2 Discontinuous conduction mode of SLR at ω s < ω 0 .
2
Now, substituting the value of IL(s) from Equation (5.3),
 Vdc − 2Vc (0) − 2Vo   1 s  I L (0)  ω 0  Vc (0)

Vc (s ) =  − 2 2+ +
 2   s s + ω O  ω 0C  s 2 + ω 0 2  s
(5.5)
Similarly, voltage across capacitance in the time domain can be written

as
 Vdc − 2Vc (0) − 2Vo  I (0)

vc (t ) = (1 − cosω 0t ) + L sin ω 0t + Vc (0) (5.6)
 2  ω 0C
Now, at ω0t = 0, iL(t) = IL(0) = 0 and vc(t) = Vc(0)

and at ω0t = π, iL(t) = 0
∴ vc(t) = Vdc – Vc(0) – 2Vo (5.7)
Now, 180° subsequent to 1st half cycle, the switch T + is naturally turned
off, the inductor current reverses, and then it will start to free-wheel through
the diode D + since another switch T − is not yet turned on, as shown in
Mode II of Figure 5.2. After free-wheeling the inductor current, i.e., IL(0) = 0,
diode D + is conducting and remains 0 as no switches are on. Applying KVL,
Vc(0) = −Vc(0) and Vo = −Vo

 V + 2Vc (0) + 2Vo 

This gives iL (t ) =  dc
This gives  sin ω ot (5.8)
 2ω 0 L
 V + 2Vc (0) + 2Vo 

Similarly, vc (t ) = dc
Similarly, (1 − cosω 0t ) − Vc (0) (5.9)
 2 
At ω0t = π,
iL(t) = 0
vc(t) = Vdc + Vc(0) + 2Vo (5.10)
Equating Equation (5.7) and Equation (5.10),
Vdc – Vc(0) – 2Vo = Vdc + Vc(0) + 2Vo
Vc(0) = −2Vo (5.11)
Similar analysis can be applied for the next half cycle when T − is turned
ON, which gives the initial voltage across the capacitor as Vc(0) = 2Vo. The
corresponding diagram has been depicted in Mode III of Figure 5.2. As in
the case of the positive half cycle, T − will be turned off naturally and the
inductor current reverses, which will start to free-wheel through the diode
D −, as shown in Mode IV of Figure 5.2.
b) Continuous Conduction Mode of Series Load Resonant Converter →

Switching frequency is greater than half of resonating frequency, but less
than resonating frequency:
1
This operation defines ω 0 < ω s < ω 0 , i.e., T0 < Ts < 2T0. When T + is
2
turned on, the inductor current starts rising with a finite value in a positive
direction and it is conducted for less than 180° at a switch voltage of Vdc,
as shown in Mode I of Figure 5.3. Then, the inductor current reverses and
will start to free-wheel through D + and, consequently, T + turns off natu-
rally. The corresponding circuit diagram is depicted as Mode II of Figure
5.3. When switch T − is turned on, the inductor current will transfer to
Modes of operation
T+ Lr Cr Lr Cr
D+ T- D-
iL
vc 1/2Vdc +
_ iL +_ Vo 1/2Vdc _+ iL +
_ -Vo
I T+ operating II D+ operating
ω0t1
ω0t0 ω0t
ω0t2
Lr Cr Lr Cr
II
T0
-1/2Vdc +
_ iL _+ -Vo -1/2Vdc +
_ iL +_ Vo
Ts
I II III IV III T- operating IV D- operating
1
Figure 5.3 Continuous conduction mode of SLR at ωs < ω0 .
2
T − from D +. Compared with discontinuous conduction mode, D + will

conduct for less than 180° because of early switching on T −. This next half
cycle is shown as Mode III and Mode IV operations, respectively, of Figure
5.3. In this mode of operation, switching loss arises because of the switch-
ing turn on at a finite current and finite voltage. The free-wheeling diode
has a good reserve recovery characteristic, as it can avoid large reverse cur-
rent spikes through the switches.
c) Continuous Conduction Mode of Series Load Resonant Converter →
Switching frequency is greater than resonating frequency:
This operation defines ωs > ω0 i.e., Ts < T0. In this mode of operation, the
switches are forced to turn off at a finite current but are turned on at zero
voltage and zero current. Initially, T + starts conducting at zero current
and inductor current starts rising, as shown in Mode I of Figure 5.4. After
turning off the T +, the positive inductor current transfers from T + to
Modes of operation
Lr Cr Lr Cr
T+ D+ T- D-
1/2Vdc +
_ iL +
_ Vo -1/2Vdc +
_ iL +
_ Vo
iL vc
I T+ operating II D+ operating
ω0t1
ω0t0 ω0t2 Lr Cr Lr Cr
ω0t
-1/2Vdc +
_ iL +_ -Vo 1/2Vdc +
_ iL +
_ -Vo
Ts III T- operating IV D- operating

T0
I II III IV
Figure 5.4 Continuous conduction mode of SLR at ωs > ω0.

D −, which is shown as Mode II of Figure 5.4 and a similar operation will

continue for the next half cycle, i.e., T − ensures to flow inductor current in
a negative direction and after switching off of T −, the inductor current will
switch over to D + accordingly, which is depicted as Mode III and Mode IV,
respectively, of Figure 5.4.
5.3 Simulation Results

The entire circuit has been simulated in a MATLAB Simulink environ-
ment. The theoretical analysis has been verified with simulation with the
value of inductance and capacitance of the tank circuit, as depicted in Table
5.1, where corresponding angular resonant frequencies are also mentioned
that will satisfy the criterion with respect to a switching frequency of 50 Hz.
Figure 5.5 shows the discontinuous inductor current operation with
the tank circuit parameter values mentioned in Table 5.1. Corresponding
waveforms for the capacitor voltage and DC load voltages are also shown.
It is clear from the figure that the initial capacitor voltage is almost equal
to -50 V and the steady-state DC load voltage can be approximated as 20
V, i.e., Vc(0) ≈ 2Vo, which validates the theoretical analysis as shown in
Figure 5.2.
Figure 5.6 shows the continuous current mode of operation with the
specified value of the tank circuit parameters mentioned in Table 5.1,
which defines the angular resonant frequency of 451.75 rad/sec. Since the
switching frequency is 314.16 rad/sec and lies in between 225.88 rad/sec
and 451.75 rad/sec, the selection of passive components satisfies criteria 2,
Table 5.1 Parameters related to different resonant frequencies and mode

of operation.
Value of Angular
Value of resonant resonant resonant
inductance capacitance frequency Mode of
Sl. no. (mH) (µF) (rad/sec) operation
1. 10 10 3162 DCM
2. 490 10 451.75 CCM
3. 500 22 301.51 CCM
Inductor current at L = 10 mH, C = 10uF and Resonant Frequency = 3162 rad/sec
3
2
Current (Amp) 1
0
-1
-2
-3
0.1 0.105 0.11 0.115 0.12 0.125 0.13
Capacitor voltage at L = 10 mH, C = 10uF and Resonant Frequency = 3162 rad/s
100
50
Voltage (Volt)
-50
-100
0.1 0.105 0.11 0.115 0.12 0.125 0.13
DC output voltage at L = 10mH, C = 10uF and Resonant Frequency = 3162 rad/sec

30
Voltage (Volt)
20
10
-10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (Sec)
1
Figure 5.5 Discontinuous conduction mode of operation at ω s < ω 0 .
2
Inductor current at L = 490 mh, C = 10uF and Resonant Frequency = 451.75 rad/sec
0.5
Current (Amp)
-0.5
0.8 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.9
Capacitor voltage at L= 490 mH, C = 10 uF and Resonant Frequency = 451.75 rad/sec

200
100
Voltage (Volt)
-100
-200
0.8 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.9
DC output voltage at L = 490 mH, C = 10 uF Resonant Frequency = 451.75 rad/sec

30
20
Voltage (Volt)
10
-10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (Sec)
1
Figure 5.6 Continuous conduction mode of operation at ω0 <ωs <ω0 .
2
which also validates the analysis mentioned in Figure 5.3. The voltage and
current obtained from simulation with respect to mode of operation is
given in Table 5.2.
Similarly, for an angular resonant frequency of 301.51 rad/sec (less than
the switching frequency of 314.16 rad/sec), the simulated waveforms are
shown in Figure 5.7, which is similar to Figure 5.4, as obtained from the
theoretical analysis.
Table 5.2 Voltage and current obtained from simulation with respect to mode
of operation.
Range of Inductor Capacitor Output
angular r.m.s. r.m.s. DC
Mode of frequency current voltage voltage
Sl. no. operation (rad/sec) (Amp) (Volt) (Volt)
1. DCM 1 0.55 49.11 19.18
ωs < ω0
2
2. CCM 1 0.27 82.57 23.27
ω0 < ωs < ω0
2
3. CCM ωs > ω0 0.53 76.89 48.56
Inductor current at L = 500 mH, C = 22 uF and Resonant Frequency = 301.51 rad/sec

1
0.5
-0.5
-1
0.8 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.9
Capacitor voltage at L = 490 mH, C = 10 uF and Resonant Frequency = 451.75 rad/sec

200
100
-100
-200
0.8 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.9
DC output voltage at L = 490 mH, C = 10 uF and Resonant Frequency = 451.75 rad/sec

80
60
40
20
-20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Figure 5.7 Continuous conduction mode of operation at ωs > ω0.
5.4 Conclusion
From the experimental simulation work, it is evident that a Series Load
Resonant (SLR) DC-DC converter with soft switching topology exhibits
sinusoidal current wave shape either in CCM or DCM depending upon
the selection of the passive components, on which resonant frequency
depends. For a fixed switching frequency, it has been found that if Ts > 2T0,
the converter will operate in a discontinuous current conduction mode of
operation and switches are turned on at zero current and will be naturally
turned off due to L-C tank circuit. But, in the case of T0 < Ts < 2T0, the
inductor current becomes continuous and the next half cycle will start
before ending of the previous cycle, as shown in Figure 5.6. Again, if Ts <
T0, the inductor current becomes almost sinusoidal and less harmonic dis-
tortion is found, as shown in Figure 5.7. But, in both the continuous cur-
rent conduction mode, the size of the inductor becomes significantly large.
Furthermore, a compromise between sizing of the passive components and
the switching frequency can be carried out so that overall compactness of
the converter with satisfied performance can be obtained.
References
1. A. Vuchev, N. Bankov, A. Lichev, and Yasen Madankov, “Load Characteristics
of a Series Resonant DC-DC Converter with an Symmetrical Controlled
Rectifier”, 25th International Scientific Conference Electronics (ET), 2016.
2. T. Taufik, M. McCarthy, S. Watkins, and Makbul Anwari, “Performance
Study of Series Loaded Resonant Converter Using Super Barrier Rectifiers”,
IEEE Region 10 Conference TENCON, 2009, pp. 1-5.
3. T. S. Sivakumaran, and S. P. Natarajan, “Development of Fuzzy Control of
Series-Parallel Loaded Resonant converter-Simulation and Experimental
Evaluation”, India International Conference on Power Electronics, 2006, pp.
360-364.
6
Review on Different Methodologies
of DC-AC Converter
Pushparajesh V.1*, Marulasiddappa H. B.2 and Nandish B. M.2
*
1
Dept. of Electrical & Electronics, FET, JAIN - A Deemed to be University,
Bengaluru, Karnataka, India
2
Dept. of Electrical & Electronics, Jain Institute of Technology, Davanagere,
Karnataka, India
Abstract
This chapter reviews different methods of converting from DC to AC. This elabo-
rates on single phase multilevel inverters (MLI) which have more advantages over
conventional two level inverters. The necessity of pure energy and saving energy
has caused a sudden increase in power generation and use of variable speed drives
(VSD). Controlling the speed and torque of variable speed drives is very much nec-
essary to increase efficiency of conversion. MLIs are the better choice compared
to two level inverters, while conversion from DC to AC for different applications
like Flexible AC transmission systems (FACTS), Variable speed drives, renewable
energy power generation, and for utility applications.
Presently, MLI plays a major role in DC-AC conversion. Various topologies are
involved in improving overall efficiency of conversion, they are: diode clamped,
flying capacitor, cascaded, and new hybrid MLIs are the important topologies used
in various applications. This chapter explains various aspects of these topologies
with respect to operation and switching pattern. It gives a detailed structure of
new hybrid MLI topology for nine level operations using a stepped wave modula-
tion technique. With the use of the stepped wave modulation strategy used in the
MLI network, it is possible to achieve low Total Harmonic Distortion (THD) in
the output waveform without using a filtering device. This chapter also elaborates
the comparison of new hybrid MLI topology with other topologies that include
cascaded, flying capacitor, and diode clamped MLI topologies. Nine levels are pro-
duced using two different input voltages in new hybrid MLI. It gives more quality
output waveforms by giving more levels than other MLIs.
159
Keywords: Two level inverter, MLI, THD
6.1 Introduction
Basically, converters which convert DC to AC are called inverters. Voltage
source inverters (VSI) and current source inverters (CSI) are the two basic
types of inverters.
Basically, we should design inverters more efficiently [1]. It is possible to
control voltage, frequency, and power of the entire circuit using the inverter
circuit. There may be an electronic inverter or a combination of an electronic
and mechanical power inverter. Figure 6.1 gives different types of inverters.
Voltage source inverters are then classified into two level inverters and
MLI. Two level inverters are also called conventional VSI and its represen-
tation is given above in Figure 6.2. When the upper switch of the leg in on,
VDC appeared across the load and VDC appears across the load if another
one is on. Therefore, at any instant of time, one switch has to be turned on
and other must be turned off. Conventional VSI output voltage contains
2-levels, hence it is called a two level inverter.
Presently, many industries deal with medium and high power applica-
tions. AC drives are connected to a medium voltage system in the range
of megawatts. Usually, conventional VSI is employed for converting DC
to AC, but a conventional two level inverter produces more harmonic dis-
tortions and high voltage stresses on switches. Due to this, it is not more
DC-AC
Converter
Current Voltage
source source
inverter (CSI) inverter (VSI)
PWM Load Two level Multilevel

CSI commutated inverter inverter
inverter
Figure 6.1 Different types of inverters.

Review of DC-AC Converter 161
+
V dc/2
Vdc/2 Van
n a
V dc
Load
-Vdc/2
-V dc/2
Figure 6.2 Circuit diagram of two level inverter.
efficient for conversion purposes. Hence, to overcome these drawbacks,

MLIs are being used. As the name indicates, they produce a greater number
of output voltage levels and, in turn, gives lesser harmonic distortion. MLI
generates the output levels in steps which look like a staircase and resem-
ble the sinusoidal waveform. The MLI are very much suited for medium
and high voltage applications [2]. There are many advantages over a con-
ventional 2-level inverter [3]. MLI produces a good quality of waveform,
lowers the dv/dt on switch, and lowers the harmonic distortion.
A cascaded connection between different MLI topologies is explained
[4–7]. There are 3 basic multilevel inverters: flying capacitor multilevel
inverters, Neutral Point Clamped multilevel inverters, and cascaded
H-bridge multilevel inverters [8–12].
The following Figure 6.3 shows representation of an MLI system.
DC supply Multilevel Load

Inverter
Driver Circuit
Microcontroller
Figure 6.3 Representation of MLI.

6.2 Different Multilevel Inverter Topologies

There are various multilevel inverters and a few important topologies
include:
i) Diode clamped MLI (DCMLI)

ii) Flying capacitor MLI (FCMLI)
iii) Cascaded H-bridge (CHMLI) MLI
iv) New hybrid MLI (NHMLI)
Nowadays, these topologies are also applied for low voltage applications.
There is always a problem in development of inverters with respect to its
quality of waveform [13]. These are explained briefly in following sections.
6.2.1 Diode Clamped MLI (DCMLI)

It was initially explained in 1981 by Nabae, Takashi [14]. It is called a
neutral point converter. This type of MLI is a commonly used topology.
In this topology, diodes are mainly used to reduce the voltage stress on
each switch. This requires (n-1) inputs for n level inverters. It is possible
to increase the quality of the sinusoidal signal by raising the voltage steps
because this waveform comes closer to a sinusoidal one. The representa-
tion circuit for a 5-level DCMLI is given in Figure 6.4.
Vs
L1 Ds1
C1
D1 L2 Ds2
V4
D2 D7 L3 Ds3
C2
D3 D8 D11 L4 Ds4
A
Vdc V3 0
D4 D9 D12 L5 D s1
1
C3
D5 D10 L6 D s2
1
V2
D6 L7 D s3
1
C4
L8 D s4
1
V1
Figure 6.4 5-level diode clamped MLI.

This type of topology consists of three legs and the above diagram
gives 5-levels. The five levels are Vdc, 2Vdc, 0, -Vdc, and -2Vdc. This type
of topology has an application in medium speed AC drives and static
VAR compensation. According to following switching Table 6.1, power
semiconductor switches are on and off. High means on state and low
means off state.
g- number of level
Number of main switches required = 2(g-1).
Number of diodes required = 2(g-1)
Quantity of clamping diodes required = (g-1) *(g-2)
Quantity of dc bus capacitors = (g-1)
For g = 5
Number of main switches required = 8
Number of diodes required =8
Quantity of clamping diodes required = 12
Quantity of dc bus capacitors =4
Advantages:
¾¾ It gives more efficiency at fundamental frequency

¾¾ Groups of capacitors are made for pre-charging
¾¾ In this topology, all phases use a common DC bus which, in
turn, minimizes the use of capacitance
¾¾ It requires minimum cost
Table 6.1 Switching pattern of DCMLI topology.

V0 L1 L2 L3 L4 L5 L6 L7 L8
Vdc/2 H H H H L L L L
Vdc/4 L H H H H L L L
0 L L H H H H L L
-Vdc/4 L L L H H H H L
-Vdc/2 L L L L H H H H
*H-high (on state), L-low (off state).
6.2.2 Flying Capacitor MLI

This topology finds more usefulness over DCMLI in industrial applica-
tions [15]. It consists of capacitors and is used to transfer the voltage to
devices. This topology will not use the clamping diodes. It is represented
below in Figure 6.5. A major drawback is a load voltage of only 50% of the
source voltage. This can be used in reactive power compensation and also
for induction motor controlling purposes.
We can calculate the number of DC sources by using: Ndc = n − 1

Then, the number of main switches required is 2(g -1).
Number of diodes required = 2(g -1)
Clamping diodes required = 2(g -1)
DC bus capacitors = (g -1)
Quantity r of balancing capacitors = (g -1)(g -2)/2
For g = 5. The requirement of components is given below
Switches = 8
Diodes = 8
Clamping diodes = 8
DC bus capacitors = 6
+ Vdc
L1
C1
L2
C4
L3
C2 C7
L4
a C5 C9 V
L5
S C8
L6
C6
L7
C3
L8
- Vdc
Figure 6.5 Five level flying capacitor MLI.

Table 6.2 Switching pattern of FCMLI topology.

V0 (volts) L1 L2 L3 L4 L5 L6 L7 L8
Vdc H H H H L L L L
Vdc/2 H H H L H H H L
0 H H L L H H H L
-Vdc/2 H L L L H H H L
-Vdc H L L L H H H H
The switching states for a 5-level MLI are given below. According to fol-
lowing switching Table 6.2, power semiconductor switches will on and off.
Advantages:
¾¾ Both powers can be controlled

¾¾ Phase redundancies are possible
This topology has the disadvantage of high switching losses [3].
6.2.3 Cascaded H-Bridge MLI

CHMLI topology is the most commonly used topology for different
applications. This topology was first initiated in 1975. This topology has
D1 L3 D3
V L1
L2
D2 L4
D4
L
O
A
D
D1* D3*
L7
L5
V
D2* D4*
L6 L8
Figure 6.6 Circuit diagram of cascaded MLI for 5-levels.

superiority in getting maximum levels compared to other topologies. A

diagram of this topology is given in Figure 6.6. In an H-bridge inverter, at
any instant of time, one switch has to turn on from each leg and one should
turn on from the upper arm or lower arm. No two switches from the same
leg should turn on, as it causes a short circuit. In this topology, both DC
input sources are equal values.
The above Figure 6.6 gives a cascaded MLI diagram. Depending on
switching Table 6.3 given below, the respective switches are in a conduc-
tion state or closed to give the respective output voltages. For example, to
get a 2V DC as an output voltage, switches S1 and S4 in the upper H-bridge
have to turn on and switches S1* and S4* in the lower H-bridge are in the
on state. The states of switches in on/off for a 5-level MLI are given below
in Table 6.3. According to the following switching Table 6.3, switches will
be on and off.
Number of switches required are 2*(g -1).

Total diodes required = 2(g -1)
Total clamping diodes required = 2(g -1)
Total dc bus capacitors = (g-1)/2
For g = 5
Number of clamping diodes required = 8
Number of dc bus capacitors =2
Table 6.3 Switching states.

V0 L1 L2 L3 L4 L5 L6 L7 L8
2Vdc H L L H H L L H
Vdc H L L H H H L L
0 H H L L H H L L
-Vdc L H H L L L H H
-2Vdc L H H L L H H L
6.2.4 New Hybrid Cascaded MLI

This topology is similar to cascaded H-bridge MLI topology, except the
ratio of two sources is 1:3. That is, if the input voltage of the upper bridge
circuit is taken as Vdc, then the input voltage of the lower H-bridge is con-
sidered as 3Vdc. For example, if V1=Vdc=50V, then V2=3Vdc=150V. There
are many control techniques for MLI. For asymmetrical DC input volt-
age we propose a stepped wave modulation technique. This is explained in
detail in the next section.
6.2.4.1 Stepped Wave Modulation Topology (SWMT)

This is one of the techniques which is well suited for MLI topology. This
technology gives lower harmonic distortion without the use of a filter cir-
cuit. This paper [16] explains the asymmetric modulation technique for
MLIs. This technique will not sample like sinusoidal signals. It will divide
complete waves into small intervals and then control each intervals sepa-
rately, which leads to control amplitude of the voltage. This technique for
MLI reduces harmonic distortion and increases fundamental voltage.
The below Figure 6.7 shows an SWMT waveform. From the Figure 6.7,
there is an output voltage V0=0 for ωt=0. At ωt=α1, the voltage is V0= V1
and at ωt=α2, the output voltage level is V2 and so on, until the output
voltage is Vs at Π/2. The next quarter wave output voltage decreases in
steps until it reaches zero at Π-α1. For the other part of the waveform, this
entire process is repeated with negative values in output voltage. For the
next cycle, this procedure will be repeated.
Vout
+VS
+V(S-1)
+V2
ω
+V1
... ...
π-α
a1
a2
a3
π-α
π-α
a(S-1)
π-α
π-α
π-α(s-1)
π/2
Figure 6.7 Stepped wave modulation waveform.

6.2.4.2 Fourier Series of Proposed Waveform

For any number of DC sources, s, n, and an are followed as:
4E
an = [cos(nα 1) + cos(nα 2) +…cos(nan )] (6.1)
nπ
or
4E
∑
s
an = [cos(nak ) (6.2)
nπ k =1
The Fourier series of the quarter wave symmetry of the output voltage
is given by
∑  4E
∑
∞ s
Vout (ω t ) =  [cos(nak )]sin(nω t ) (6.3)
n=1  nπ k =1 
where αk = switching angles

‘S’ represents the number H-bridge cells
‘n’ represents the odd harmonic order
‘E’ represents amplitude of DC voltages
Odd harmonic components are given by
4E
∑
S
h1 = [cos(ak ) (6.4)
π k =1
and
4E
∑
S
hn = [cos(nak ) (6.5)
nπ k =1
As we know it, half wave symmetry even order harmonics are zero.
Therefore, output voltage contains only odd order harmonics and to
reduce harmonic distortion, the switching angles need to be adjusted.
Total amount of harmonics present in the signal is described as total
harmonic distortion, calculated by:
∑n∞=2 H 2n
THD = (6.6)
H1
6.2.4.3 Proposed Topology (New Hybrid MLI)

New hybrid MLI topology is explained for S=2, i.e., the number of stages
is equal to 2. It has a number of output voltage levels equal to 3S. Two DC
voltage sources, V1 and V2, are used as input sources. This topology has a
maximum number of output step sin comparison to remaining inverters.
The circuit diagram for the new hybrid CMLI is shown in Figure 6.8. It is
called a new hybrid because DC input voltages are selected in the ratio 1:3.
Here, we considered Vdc1=V1 and Vdc2=v2. Inputs are in the ratio 1:3. That
is, if V1= Vdc, then V2=3Vdc. According to following switching Table 6.4,
power semiconductor switches will be on and off. In the following Table
6.4, ‘0’ represents opening of a switch and ‘1’ represents closing of a switch.
L1 L3
+
Vdc1
-
L4
L2
VO
L5 L7
Vdc2
-
L8 L6
Figure 6.8 Circuit diagram of nine level new hybrid MLI.

Table 6.4 Switching states of switching devices.

V0 (volts) L1 L2 L3 L4 L5 L6 L7 L8
0 L L L L L L L L
V1 L H H L L L H H
V2 - V1 H L L H L H H L
V2, H H L L L H H L
V 1 + V2 L H H L L H H L
- V1. H L L H L L H H
V1 - V2 L H H L H L L H
-V2. H H L L H L L H
- V 1 - V2 H L L H H L L H
Switching states are obtained from the stepped wave modulation

technique.
Figure 6.9 shows the output voltage waveform of a 9-level new hybrid
MLI topology.
5Vdc
4Vdc
3Vdc
2Vdc
Vdc
-Vdc
-2Vdc
-3Vdc
-4Vdc
-5Vdc
0 0.002 0.004 0.006 0..008 0.01 0.012 0.014 0.016 0.018 0.02
Time (seconds)
Figure 6.9 9-level new hybrid MLI topology.

Total main switches required are 2(g -1).

Total diodes required = 2(g -1)
Total clamping diodes required = 2(g -1)
Total dc bus capacitors = (g -1)/2
For Q = 5
Number of clamping diodes required = 8
Number of dc bus capacitors =2
Circuit Operation:
The frequency of output voltage is 50Hz.

Therefore, the time period is T=1/f=1/50=20ms.
From Figure 6.9, there are a total 16 levels in complete waveform.
Hence, duration of each level is 1.25ms. As we know, the sine wave is sym-
metrical in nature. Therefore, one fourth of the sine wave has five modes
of operation.
Mode 1: 0 ≤ t ≤ 1.25
Mode 2: 1.25 ≤ t ≤ 2.5
Mode 3: 2.5 ≤ t ≤ 3.75
Mode 4: 3.75 ≤ t ≤ 5
Mode 5: 5 ≤ t ≤ 6.25
Circuit operation is explained below.
Mode 1: 0 ≤ t ≤ 1.25:
Here, all switches are in the off condition and therefore, output voltage is
zero for this period, i.e., for t=1.25ms.
Mode 2: 1.25 ≤ t ≤ 2.5:

Here, operation L3, L4, L6, and L8 are in the on condition and other
switches are in the open state. Hence, V1 will appear across load terminals.
Mode 3: 2.5 ≤ t ≤ 3.75:

In this mode of operation, L1, L 2, L7, and L8 are in closed condition and
the others are in the open state. Hence, output voltage V2-V1 will appear
across the load terminals.
Mode 4: 3.75 ≤ t ≤ 5:
Only L1, L3, L7, and L8 are in the on condition and the other switches are
in the off state. Hence, the output voltage V2 will appear across the load
terminals.
Mode 5: 5 ≤ t ≤ 6.25:
This is the last mode of operation. During this mode of operation, only L3,
L4, L7, and L8 are in the on condition. Hence, the output voltage V1+V2
will appear across load terminals.
This topology along with the stepped wave modulation technique
reduces the total harmonic distortion in the output voltage.
6.3 Comparison between Various MLI

The following Table 6.5 gives a comparison of all MLI topologies with
respect to various parameters. From the table it is shown that a new hybrid
MLI topology has a fewer number of components and lower value of total
harmonic distortion.
Table 6.5 Comparison table of MLIs.

New hybrid
MLI topology DCMLI FCMLI CHMLI MLI
Number of Switches 2*(g-1) 2*(g -1) 2*(g -1) 2*(g -1)
Number of Main 2*(g -1) 2*(g -1) 2*(g -1) 2*(g -1)
Diodes
Number of (g -1)*(g -2) 2*(g -1) 2*(g -1) 2*(g -1)
Clamping Diodes
DC Bus Capacitors (g -1) (g -1) (g -1)/2 (g-1)/2
Balancing 0 (g -1)*(g -2)/ 0 zero
Capacitors 2
Average Output Low Low Medium High
Voltage
THD High High Medium Low
g-number of levels.
6.4 Conclusion
Different methods to convert DC to AC are explained here. This explains
multilevel inverters (MLI) which have more advantages over conventional
two level inverters. Many methods are present to improve overall efficiency
of conversion, a few of them are: diode clamped, flying capacitor, cascaded,
and new hybrid MLIs. Circuit diagrams and switching tables for different
multilevel inverters are explained.
This chapter gives a detailed structure of new hybrid MLI topology for
9-level operations by using a stepped wave modulation technique. With
the use of stepped wave modulation strategy used in an MLI network, this
can be possible for achieving low THD in the output waveform without
using a filtering device.
References
1. Xu Jun, Han Kailing, “The single phase inverter design for photovolataic sys-
tems”, 2016 International Symposium on Computer, Consumer, and Control,
pp 341-344.
2. L. Tolbert, F.Z. Peng, and T.G. Habetler, “Multilevel Inverters for Electric
Vehicle Applications,” IEEE Power Electronics in Transportation, pp. 79-84,
Dearborn, MI, October 22-23, 1998.
3. Jos Rodrguez, Jih-Sheng Lai, Fang ZhengPeng “Multilevel Inverters: A Survey
of Topologies, Controls, and Applications,” IEEE Transactions On Industrial
Electronics, Vol. 49, No. 4, August.
4. L. M. Tolbert and X. Shi, “Multilevel power converters,” in Power Electronics
Handbook, ed: Elsevier, 2018, pp. 385-416.
5. A. Khodaparast, E. Azimi, A. Azimi, M. E. Adabi, J. Adabi, and E. Pouresmaeil,
“A New Modular Multilevel Inverter Based on Step-Up Switched-Capacitor
Modules,” Energies, vol. 12, p. 524, 2019.
6. R. R. Karasani, V. B. Borghate, P. M. Meshram, H. M. Suryawanshi, and S.
Sabyasachi, “A three-phase hybrid cascaded modular multilevel inverter for
renewable energy environment,” IEEE transactions on power electronics, vol.
32, pp. 1070-1087, 2016.
7. P. Kala and S. Arora, “A comprehensive study of classical and hybrid multi-
level inverter topologies for renewable energy applications,” Renewable and
Sustainable Energy Reviews, vol. 76, pp. 905-931, 2017.
8. J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, “A survey on neutral-
point-clamped inverters,” IEEE Transactions on Industrial Electronics, vol. 57,
pp. 2219-2230, 2009.
9. V. Dargahi, K. A. Corzine, J. H. Enslin, M. Abarzadeh, A. K. Sadigh, J.

Rodriguez, and F. Blaabjerg, “Duo-active-neutral-point-clamped multi-
level converter: An exploration of the fundamental topology and experi-
mental verification,” in 2018 IEEE Applied Power Electronics Conference and
Exposition (APEC), 2018, pp. 2642-2649.
10. A. K. Sadigh, V. Dargahi, and K. A. Corzine, “New active capacitor volt-
age balancing method for flying capacitor multicell converter based on
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11. C. D. Fuentes, C. A. Rojas, H. Renaudineau, S. Kouro, M. A. Perez, and T.
Meynard, “Experimental validation of a single DC bus cascaded H-bridge
multilevel inverter for multistring photovoltaic systems,” IEEE Transactions
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12. B. Wu and M. Narimani, “Cascaded H‐bridge multilevel inverters,” 2017.
13. P. Sachis, I. Echeverria, A. Ursua, O. Alonso, E. Gubia, L. Marroyo,”
Electronics Converter for the Analysis of Photovoltaic Arrays and Inverters”,
IEEE 2003, pp. 1748-1753.
14. Beser, E.; Camur, S.; Arifoglu, B.; Beser, E.K.Design and application of a novel
structure and topology for multi-level inverter,” in Proc. IEEE SPEEDAM,
Tenerife, Spain, 2008, pp. 969 – 974.
15. S.G. Lee, D.W. Kang, Y.H. Lee and D.S. Hyun, “The carrier-based PWM
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ric modulation method for cascaded multilevel inverters”. IET Power
Electronics, 5(1), 74-85.
7
Grid Connected Inverter for Solar
Photovoltaic Power Generation
K.K. Saravanan* and M. Durairasan
Department of Electrical and Electronics Engineering, University College

of Engineering, Thirukkuvalai, Tamil Nadu, India
Abstract
The MATLAB Simulink model analysing the seven level, nine level, and fifteen
level is ensured. The variation of output voltage and current magnitudes are mea-
sured, which depend upon the load changes and the measured Total Harmonic
Distortion (THD) that has been compared with the different inverter configura-
tions. The modelling methodology by variation of solar radiation supplies con-
stant input power to the inverter and grid connected system. The Zero Voltage
Switching (ZVS) technique is implemented in this described model. The complex
system is simplified and it has enhanced the efficiency and improved the electro-
magnetic interference.
The optimal utilisation of a Dynamic Voltage Restorer (DVR) is recovering the
voltage sags which reduces 10% and swells up to 190% of its rated value. Household
application is adopted in the medium and highpower rating for varying the mis-
match load and addressing power quality issues, stability problems, voltage sags,
short duration voltage swell, and power interruption, which are eliminated by
introducing the DVR system in the modified PV Simulink model. The grid system
is connected with a high performance single stage inverter system. The modified
circuit does not convert the lowlevel photovoltaic array voltage into high voltage.
The converter is applied in solar DC power into high quality AC power and is uti-
lized in the grid. Total harmonic distortion was reduced to the IEEE-519 standard
permissible level.
Keywords: Zero Voltage Switching (ZVS), Dynamic Voltage Restorer (DVR),

Total Harmonic Distortion (THD), Electromagnetic Interference (EMI)
175
7.1 Single Phase Seven Level Inverter Fed Grid

Connected PV System
A singlephase grid connected seven level inverter is typically utilized for
private or low control utilizations of power ranges that are under 10 KW.
Enhancing its output waveform diminishes it agreement with substances
and, consequently, additionally the extent of the channel utilized and the
level of Electromagnetic Interference (EMI) produced by the inverter’s
exchanging operation. Multilevel inverters are promising; they verge on
sinusoidal output voltage waveforms, produce output current with better
consonant profile, have less pushing of electronic sections inferable from
reduced voltages, trade adversities that are lower than those of customary
two level inverters, and have a smaller channel size and lower EMI, all of
which make them less costly and at the high cut-off from that point of
minimization [1].
7.1.1 Seven Level Inverter Topology

The modified single stage seven level inverter was produced from the five
level inverter. It involves a solitary stage ordinary H-bridge inverter, two
bidirectional switches, and a capacitor voltage divider framed by C1, C2, and
C3, as shown in Figure 7.1. The modified H-bridge topology is altogether
worthwhile over different topologies, i.e., less power switch, power diodes,
and less capacitor for inverters of the same number of levels. Photovoltaic
(PV) arrays were associated with the inverter through a DC–DC converter.
Dpv Lb Db Lf
C1 SW1 SW2
SW5
PV
SWb
Cpv
a Grid
C2 Voltage
b
SW3 SW4
SW6
Lf
Figure 7.1 Modified single phase seven level grid connected inverter for photovoltaic
systems.
Grid Connected Inverter for PV System 177
The utility matrix, as opposed to a load, was utilized by the power pro-
duced by the inverter which conveyed the power to the power system [3].
7.1.2 PWM Technique for Seven Level Inverter

A novel PWM modulation method is introduced to create the PWM
switching signals. Three reference signals (Vref1, Vref2, and Vref3) were con-
trasted, as well as a carrier signal (Vcarrier). The reference signals having the
same frequency and amplitude were in phase with an offset value equiva-
lent to the amplitude of the carrier signal [4]. Table 7.1 shows output volt-
age and switching conditions of a seven level inverter.
Each reference signal is compared with the carrier signal. When Vref1
exceeds the peak amplitude of Vcarrier, Vref2 is compared with Vcarrier until it
exceeds the peak amplitude of Vcarrier. At that point, ahead, Vref3 receives
responsibility and is contrasted with Vcarrier until it achieves zero. Once Vref3
achieved zero, Vref2 would be looked at until it achieved zero [5].
Table 7.1 Output voltage according to switches’ ON–OFF condition.
Switching states
Output voltage
SW1 SW2 SW3 SW4 SW5 SW6 Vo (volts)
On Off Off On Off Off Edc
2
Off Off Off On On Off E dc
3
1
Off Off Off On Off On E dc
3
Off Off On On Off Off 0
1
Off On Off Off On Off − E dc
3
2
Off On Off Off Off On − E dc
3
Off On On Off Off Off Edc

From that point forward, Vref1 would be contrasted, as well as Vcarrier. For
one cycle of the fundamental frequency, the proposed inverter worked
through six modes. The six modes are described as follows:
Mode 1: 0 <ωt< θ1 and θ4 <ωt< π

Mode 2: θ1 <ωt< θ2 and θ3 <ωt< θ4
Mode 3: θ2 <ωt< θ3
Mode 4: π<ωt< θ5 and θ8 <ωt<2π
Mode 5: θ5 <ωt< θ6 and θ7 <ωt< θ8
Mode 6: θ6 <ωt< θ7
The phase angle depends on modulation index Ma. Theoretically, for a

single reference signal and a single carrier signal, the modulation index is
defined to be:
Am
Ma = (7.1)
Ac
While for a single-reference signal and a dual carrier signal, the modu-
lation index is defined to be:
Am
Ma = (7.2)
2 Ac
Since the proposed seven-level PWM inverter utilizes three carrier sig-
nals, the modulation index is defined to be:
Am
Ma = (7.3)
3Ac
where Ac is the peak to peak value of the carrier signal and Am is the peak
value of the voltage reference signal Vref .When the modulation index is less
than 0.33, the phase angle displacement is
π
θ1 = θ 2 = θ 3 = θ 4 = (7.4)
2
3π
θ5 = θ6 = θ 7 = θ8 = (7.5)
2
On the other hand, when the modulation index is more than 0.33 and
less than 0.66, the phase angle displacement is determined by
Ac 
θ 1 = sin − 1 (7.6)
 Am 
π
θ2 =θ3 = (7.7)
2
θ4 = π – θ1 (7.8)
θ5 = π + θ1 (7.9)
3π
θ6 = θ7 = (7.10)
2
θ8 = 2π – θ1 (7.11)
If the modulation index is more than 0.66, the phase angle displacement
is determined by
Ac 
θ 1 = sin − 1 (7.12)
 Am 
2 Ac 
θ 2 = sin − 1 (7.13)
 Am 
θ3 = π – θ2 (7.14)
θ4 = π – θ1 (7.15)
θ5 = π + θ1 (7.16)
θ6 = π + θ2 (7.17)
θ7 = 2π – θ2 (7.18)
θ8 = 2π – θ1 (7.19)
For Ma that is equal to, or less than 0.33, only the lower reference volt-
age (Vref3) is compared with the triangular carrier signal. The inverter’s
behaviour is similar to that of a conventional full bridge three level PWM
inverter. However, if it is more than 0.33 and less than 0.66, only Vref2 and
Vref3 reference signals are compared with the triangular carrier wave. The
output voltage consists of five DC voltage levels. The modulation index is
set to be more than 0.66 for seven levels of output voltage to be produced.
Three reference signals have to be compared with the triangular carrier
signal to produce switching signals for the switches [4].
7.1.3 Modelling and Simulation Analysis of Seven Level

Inverter
The output of the PI controller, also known as Vref, goes through an anti-
windup process before being compared with the triangular wave to pro-
duce the switching signals for S1–S6. Eventually, Vref becomes Vref1, Vref2, and
Vref3, which can be derived from Vref1 by shifting the offset value, which is
equivalent to the amplitude of the triangular wave. The MATLAB Simulink
model of the seven level inverter is shown in Figure 7.2. The output voltage
across the PV model system is shown in Figure 7.3.
l
Continuous To Workgas2
powergas
v
Vpc To Workgas2
+ + -v 7 Level Inverter
Ipv
+vc
+ +
+vel Cpv1 Cpv2 -
+ v
oc AVP Voltage -vc

-vel
Solar Panels
0.2 del Pulse

Scope2
Rad Voltage Scope1
Subsystem1
In1 Out1 VIN

M In1 Out1 i
To Workgas1
In2 Out2 IIN
[A1]
sampling MPPT PWM GENERATOR
Figure 7.2 Simulation diagram of seven level inverter.

x 10 -3 Vdc
16
14
12
10
V in Volts
-2
0 0.2 0.4 0.6 0.8 1 1.2
Time offset: 0 x 10 -4
Time in seconds
Figure 7.3 Output voltage of PV model system.
7.2 Simlink Model of Nine Level H-Bridge Inverter

The PV module has been selected and simulated in a MATLAB Simulink
environment Figure 7.4 shows the Simulink model of the nine level
H-bridge inverter. With a change in solar irradiation and temperature vari-
ation, the PV panel converts the solar energy directly into electricity, which
gives both V-I and P-V output characteristics. Figure 7.5 shows a nine level
inverter three phase stepped output voltage simulated waveform. When
the H-bridge inverter is operated and gets the required output voltage, the
currents are compensated due to shading or damage of any one solar PV
panel [9].
Group 1
Sign all
In1
Group 1 out1
Sign all 1 In2 C2
25
S1 in1 0ut2
25
in2
C1
0ut1
in3
V5 Subsystem Continuous
v
PGI
v
PHASE B
V0
Group 1
Sign all 1 l
in11 v
S4
in21 OUT21
in22
PHASE C
25
Subsystem1
C3
Figure 7.4 MATLAB simulink model of nine level H-bridge inverter.

100
50
Voltage in volts
-50
-100
1 1.02 1.04 1.06 1.08 1.1 1.12 1.14 1.16 1.18 1.2
Time in second
Figure 7.5 Three phase voltage wave form.
7.3 Three Phase Fifteen Level Inverter Fed Grid

Connected System
Analysing and studying different inverter topology levels, the fifteen level
inverter is more suitable and the quality of output wave form is almost
sinusoidal. In fifteen level inverter modelling, the output results in reduc-
ing total harmonic distortion compared to seven and eleven level inverters.
PWM inverters have been used to overcome shortcomings in solid state
switching device ratings [7, 8].
7.3.1 Modified System of Fifteen Level Inverter

The multilevel inverter has attracted huge interest in the power industry.
The multilevel inverter depicts another arrangement of features that are
suited for utilization in reactive power compensation. It might be simpler
to create a high power, high voltage inverter with the multilevel structure
due to the way in which device voltage stresses are controlled in the struc-
ture. One of the significant preferences of multilevel design is the harmonic
reduction in the output waveform without expanding switching frequency
or diminishing the inverter power output.
The cascaded multilevel inverter typically comprises of several iden-
tical single stage H-bridge cells cascaded in series in the circuit. This set
up is normally referred to as a cascaded H-bridge. To get a sinusoidal
3 ph load
P1
H-Bridge H-Bridge H-Bridge
V 2V 4V
P2
V 2V 4V
P3
V 2V N
4V
Figure 7.6 Fifteen level asymmetric cascaded multi-level inverter.
output voltage in series, they are thus connected H-bridge inverters. The
output voltage is the whole of the voltage that is created by every cell. The
asymmetrical cascaded multilevel inverter contains the DC bus voltages
which are not equivalent in all the series power cells. The schematic chart
of the proposed asymmetrical fifteen level cascaded multilevel inverter is
demonstrated in Figure 7.6. The switching angles can be picked in such
a way that the total harmonic distortion is minimized. An embedded
system is some combination of computer hardware and software, either
altered in ability or programmable, that is particularly designed for a spe-
cific capacity.
The Total Harmonic Distortion (THD) is a measure of closeness in shape
between a waveform and its fundamental component. When the voltage
levels of the topologies increase, the harmonic content of the output volt-
age waveform diminishes essentially. The switching loss of the proposed
system was low compared with the minimum levels of cascaded multilevel
inverter by utilizing this embedded controller. The THD diminished so
that the performance of the modified system also increased.
7.3.2 Modelling of Cascaded H-Bridge Fifteen Level Inverter

In this modified system, the output has been obtained by using the MATLAB/
Simulink. The simulation diagram of the modified fifteen level asymmetric
cascaded inverter and output are shown in Figure 7.7 and Figure 7.8.
Conal
a A
Continious Inl Voltage b B
Measurement c C
powergui Comm2
LP filter 2nd order Scope3
Subsystem3
Sine Warve1 Conal

Inl Switched
Voltage Measurement1 transport delay
Comm2 Scope for lineariration3
Sine Wave2 Subsystem1

Three-Phase
Conal Series RLC Branch
Scope1
Inl Sine Wave
Switched
Comm2 transport delay Scope4
for lineariration4
Subsystem2
Scope2 Voltage Measurement2
Sine Wave3
Switched
transport delay
for lineariration5
Figure 7.7 Simulink diagram of modified fifteen level asymmetric cascaded inverter.
Output voltage in volts ⟶
600
400
200
-200
-400
-600
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time o set: 0
Time in seconds ⟶
Figure 7.8 Simulation output of fifteen level asymmetric cascaded inverter.
7.3.3 Evaluation of THD

When the number of levels increases the total harmonic distortion, value
decreases. The switching loss of the modified system correspondingly
decreased compared with the conventional system, hence the performance
of the modified system increased. The THD value of the modified cascaded
fifteen level inverter is shown in Figure 7.9.
The switching loss of the modified system likewise diminished and per-
formance of the system increased. Increase in the number of levels and
correspondingly, increase in the number of DC voltages and increase in the
number of switches are recorded to tabulate the various value of THD%
that is in Table 7.2. The Total harmonic distortion (THD) comes close to
the permissible limit in the grid connected system [15].
FFT analysis
Fundamental (50Hz) = 434.6 , THD=2.93%
Mag (% of Fundamental)
2.5
2
1.5
1
0.5
0 0 5 10 15 20
Harmonic order
Figure 7.9 THD evaluation of cascaded fifteen level inverter.
Table 7.2 Comparison of three level, five level,

seven level, and fifteen level cascaded inverter.
No. of DC
No. of voltage No. of
levels sources switches THD (%)
3 1 4 29
5 1 8 26
7 4 8 21.54
9 4 8 13.79
15 3 10 2.93
7.4 Fesability Analysis of Photovoltaic System

in Grid Connected Inverter
7.4.1 Modified PV-DVR System
The circuit diagram of a modified PV-DVR system is shown in Figure
7.10. It consists of a PV array, low step up DC-DC converter with a P&O
MPPT algorithm, battery, high step up DC-DC converter, PWM inverter,
series injection transformer, and semiconductor switches S1, S2, S3, R1,
and R2. When the grid voltage is normal, switches S1 and S3 are normally
closed and S2 is normally open. When the grid fails or when the PV array
generates excess power, then the switches are activated and the inverter
supplies the load. Table 7.3 and Table 7.4 show the control signals of the
semiconductor switches S1, S2, S3, R1, and R2, respectively [13]. The power
semiconductor switches are controlled by the voltage sensor and logical
components. The proposed PV-DVR is operated in the following four
modes of operation:
a) Dynamic Voltage Restorer (DVR) Mode

b) Uninterruptable Power Supply (UPS) Mode
c) Energy Conservation Mode
d) Idle Mode
SW3
SW1 By Pass Switch
1:1 Senes Injection

Transformer
Lr Load
Supply SW2 Filter Cr
Semi Conductor Controlled PWM VSI

Controller Rectifier
DC Link
Battery Charge
Controller R1
Photo Voltaic Array
High Step up DC-DC
Low Step up R2 Converter with
DC-DC
Coupled Indoctor
Converter
Battery
V pv Duty Cycle
P & O MPPT
l pv
Figure 7.10 Circuit diagram of modified PV-DVR system.
Table 7.3 Control logic signals for S1, S2, and S3.
Control signals
Supply voltage in % S1 S2 S3 Mode of operation
100 1 0 1 Idle
<100 1 0 0 DVR
>100 1 0 0 DVR
0 0 1 0 UPS
Table 7.4 Battery charge control.

Control signals
PV voltage in volts R1 R2 Battery charging unit
>6 0 1 PV Array
<6 1 1 Rectifier and PV Array
7.4.1.1 Dynamic Voltage Restorer (DVR) Mode

In this mode, the proposed PV-DVR regulates the voltage at the load side.
During this operation a series injection transformers is configured in series
with the load to compensate the voltage sag or swell. The control logic sig-
nal of the DVR mode is shown in Table 7.3.
7.4.1.2 Uninterruptable Power Supply (UPS) Mode

In this mode, the series injection transformer of PV-DVR is reconfigured
into parallel to provide the uninterruptable power supply to load during
day and night.
7.4.1.3 Energy Conservation Mode

During excess power generation on the PV system, the proposed PV-DVR
disconnects the utility grid from load and it configures the series injection
transformer in parallel to perform the inverter operation to feed the excess
energy generated by the solar array to load. During low power generation
on the PV, the proposed charge control algorithm reconnects the utility
grid and output of the controlled rectifier in parallel with the output of low
step up DC–DC converter to feed the required power to the batteries and
load. The control logic of this mode is presented in Table 7.4.
7.4.1.4 Idle Mode

In this mode, the entire PV-DVR is disconnected through the semiconduc-
tor switch (SW3) by passing the secondary of an injecting transformer when
the DVR needs maintenance. In general, there are three strategies, pre-sag,
in-phase, and negligible energy injection methods, that are used to calcu-
late the injection voltage of DVR. In this chapter, an in-phase compensa-
tion system is utilized to compute the infusion voltage of DVR for its simple
implementation and immediate response in calculating the compensating
voltage. A DVR remunerates the voltage drop over a load by infusing a volt-
age through an arrangement injection transformer in phase with the source
voltage. The injected voltage over the secondary of the series injection trans-
formers is in phase with supply voltage, as shown in Figure 7.11.
In normal condition, the supply voltage (Vpre-sag) is equivalent to the load
voltage with zero phase angles. During the voltage sag/swell, the supply
voltage diminishes or increments to an esteem not exactly or greater than
VPresag
Ø Vsag Vinj
VL
Figure 7.11 In-phase compensation to pre-sag voltage.
its nominal value. The DVR responds to the sag or swell events and infuses
the compensating voltage V in phase with the supply voltage to restore the
voltage at nominal value.
The injected voltage of a DVR (Vinj) can be communicated as
‫׀‬Vinj‫׀ = ׀‬Vpre-sag‫ ׀‬- ‫׀‬V sag‫׀‬ (7.20)
VDVR = Vinj (7.21)
‫׀‬VDVR‫׀ = ׀‬Vpre-sag ‫ ׀‬- ‫׀‬V sag‫׀‬ (7.22)
The angle of the injected voltage can be calculated as follows:
<Vinj = ɵinj= ɵs (7.23)
7.4.2 Photovoltaic DC-DC Converter

The PV array is a system which consists of more solar cells to convert sun-
light into electricity. The developments of new efficient solar cells with an
MPPT algorithm have increased the use of solar panels as an alternative
source of renewable energy [2]. In the proposed DVR, a PV array with a
low step-up DC-DC converter associated with a function called MPPT is
incorporated to function as a DC voltage source for the inverter of DVR. It
is introduced between the PV and battery bank of the DC link [12].
The electrical system powered by the PV array requires a DC-DC con-

verter due to the varying nature of the generated solar power, resulting
from sudden changes in weather conditions, which change the solar irradi-
ation level as well as cell operating temperature [19]. An equivalent circuit
model of a photovoltaic cell with a low step up DC-DC converter is shown
in Figure 7.12.
The PV array is developed by the basic equations of photovoltaic cells
including the effects of temperature changes and solar irradiation level. The
output voltage of the PV cell is a function of photo current that is mainly
determined by load current, depending on the solar irradiation level.
The PV cell output voltage is expressed as:
Vc = (AkTc/e) ln ((Iph+I0+Ic)/I0)-RsIc (7.24)
VPV = VC*Ns (7.25)
IC = IPV/Np (7.26)
where e is the charge of the electron (1.602*10-19 Coulomb), A is the curve

fitting factor, Vc is the output voltage of the PV cell in volts, Iph is the photo
current in amps, I0 is the reverse saturation current of the diode, k is the
Boltzmann constant, Ic is the cell output current in amps, Rs is the cell
internal resistance, Ic is the operating temperature of the reference cell ,VPV
is the output voltage of PV array, IPV is the output current of the PV array,
Ns is the number of nine series cells, and Np is the number of six parallel
cells. The design parameters Iph, Io, Rs, and A are determined from the data
sheet and V–I characteristics of the PV array. The parameters of the PV
array are obtained by a series of tests under different solar irradiation and
temperature levels and then, using curve fitting approaches, the are graphs
obtained. These parameters are then obtained so that the mathematical
model gives the same curve as obtained from experiments [14].
Vpv PWM
P&O MPPT Generator
lpv
D
Rs Ls
Vs
lp
D Vc Vpv lGBT C0 V0
PV Array DC-DC Converter
Figure 7.12 Circuit diagram of PV low step-up boost converter.

Curve fitting factor A is used to adjust V–I characteristics of the cell to

actual characteristics obtained by the testing. A change in solar irradiation
level and operating temperature affects the output voltage of the cell. The
operating temperature of a solar cell varies as a function of solar irradiation
level and ambient temperature. The effect of change in ambient tempera-
ture and solar irradiation levels are represented in the model by the tem-
perature coefficients CTV and CTI.
CTV = 1+ βT (Ta-Ty) (7.27)
CTI = 1+γT/Sr (Ta− Ty) (7.28)
βT is the slope of the coefficient CTV, affecting the change in voltage due
to temperature change. γT is a constant representing the change in operat-
ing temperature due to solar irradiation. Ta and Ty represent the ambient
temperature of the cell and atmosphere, respectively. The change in the
photocurrent and operating temperature due to variation in the solar irra-
diation level can be expressed as follows:
Csv = 1 +βT αs (Sx–Sr) (7.29)
Csv = 1+1/Sc (Sx–Sr) (7.30)
where Sc is the point of reference solar irradiation level during cell testing.
Sr is the reference solar irradiation level (1000 W/m3), Sx is the new level of
solar irradiation, and αs is the slope of the change in the solar irradiation
level (0.2). The new value of cell output voltage and photo current can be
expressed as follows:
Vc(new) = CTVCSVVC (7.31)
Iph (new) = CTI CSIIph (7.32)
The change in temperature (∆Tc) can be expressed as:
∆Tc = αs (Sx–Sr) (7.33)
The low step up DC-DC converter shown in Figure 7.12 is designed

using the following basic equations. This is designed to automatically track
the maximum power point of the PV array. In the modified DVR, a low
step-up DC–DC converter with a P&O MPPT algorithm based on a fuzzy

controller is incorporated to track the maximum power point of the PV
array. When the switch S is on, the diode Dm is reverse biased by the switch
and Vc, thus isolating the output stage. The input current (is), which raises,
flows through inductor L and switch S. The input Vs supplies energy to the
inductor during the on period (Ton).
The voltage across the inductor (L) is shown in
VL = Ls.dis/dt (7.34)
Vs = VL (7.35)
When the switch S is turned off, the inductor current is forced to flow
through the diode Dm and load for a period (Toff ). As the current tends to
decrease, polarity of the EMF induced in inductor L is reversed and it is
connected in series with voltage source Vs and load through diode Dm. The
output voltage Vo can be expressed as:
Vo = Vs+Ls.dis/dt (7.36)
The average output voltage of the converter is depicted as
Vo = Vs/ (1-D) (7.37)
D = Ton/ (Ton+Toff ) (7.38)
where D is the duty cycle, Ton is on time, Toff is off time, and Is is the current
flow through the inductor Ls.
7.4.3 Maximum Power Point Tracking of PV System

The purpose of the MPPT system is to sample the output of the PV cells
and apply the proper load to obtain maximum power for any given envi-
ronmental condition. MPPT devices are typically integrated into an elec-
tric power converter system that provides voltage or current conversion,
filtering, and regulation for driving various loads, including power grids,
batteries, or motors [3].
(a) Solar inverters convert the DC power to AC power and

may incorporate MPPT; such inverters sample the output
power from the solar modules and apply the proper load
to obtain maximum power.
(b) MPP (Maximum Power Point) is the product of the MPP
voltage (Vmpp) and MPP current (Impp).
7.4.4 Methods of Maximum Power Point Tracking

Controllers usually follow one of three types of strategies to optimize the
power output of an array. Maximum power point trackers may implement
different algorithms and switch between them based on the operating con-
ditions of the array [10].
7.4.4.1 Perturb and Observe Method

In this method, the controller adjusts the voltage by a small amount from
the array and measures power, while if the power increases, further adjust-
ments in that direction are tried until power no longer increases. This is
called the perturb and observe method and is the most common method
through results in oscillations of power output. It is referred to as a hill
climbing method as there is a rise of the curve of power against voltage
below the maximum power point and beyond that.
Perturb and Observe (P&O) is the most commonly used MPPT method,
as its implementation is easy and P&O method ensures top-level efficiency
when a proper predictive and adaptive hill climbing strategy is adopted.
160
140 MPP
120
Module Output Power (W)
100
A B
80
60
40
20
0
0 5 10 15 20 25 30 35 40 45 50
Module Voltage (V)
Figure 7.13 Solar panel characteristics showing MPP and operating points A and B.
The P&O algorithm states that when the operating voltage

of the PV panel is perturbed by a small increment, the resulting change
in power ∆P is positive and is going in the direction of MPP, then keep on
perturbing in the same direction. If ∆P is negative and is going away from
the direction of MPP, the sign of perturbation supplied has to be changed.
Solar panel characteristics of module output power versus module
voltage for a solar panel at a given irradiation is shown in Figure 7.13.
The point marked as MPP is the Maximum Power Point, the theoretical
maximum output obtainable from the PV panel. Consider A and B as two
operating points. As shown in the figure above, point A is on the left side
of the MPP. Therefore moving towards the MPP by providing a positive
perturbation to the voltage. On the other hand, point B is on the right
side of the MPP.
7.4.4.2 Incremental Conductance Method

In the incremental conductance method, the controller measures incre-
mental changes in PV array current and voltage to predict the effect of a
voltage change. This method requires more computation in the control-
ler but can track changing conditions more rapidly than the perturb and
observe method (P&O). Like the P&O method, it can produce oscillations
in the power output. This method utilizes the incremental conductance
(dI/dV) of the photovoltaic array to compute the sign of the change in
power with respect to voltage (dP/dV).
The incremental conductance method computes the maximum power
point by comparison of the incremental conductance (IΔ / VΔ) to the array
conductance (I / V). When these two are the same (I / V = IΔ / VΔ), the out-
put voltage is the MPP voltage. The controller maintains this voltage until
the irradiation changes and the process is repeated.
The incremental conductance method is based on the observation that
at the maximum power point dP/dV = 0 and that P = IV. The current
from the array can be expressed as a function of the voltage: P = I (V)
V. Therefore, dP/dV = VdI/dV + I (V). Setting this equal to zero yields
dI/dV = -I (V)/V. Therefore, the maximum power point is achieved when
the incremental conductance is equal to the negative of the instantaneous
conductance.
7.4.4.3 Current Sweep Method

The current sweep method uses a sweep waveform for the PV array current
so that the I-V characteristic of the PV array is obtained and updated at
fixed time intervals. The maximum power point voltage can then be com-
puted from the characteristic curve at the same intervals.
7.4.4.4 Constant Voltage Method

The term “constant voltage” in MPP tracking is used to describe different
techniques of the literature reviews, one in which the output voltage is reg-
ulated to a constant value under all conditions and one in which the output
voltage is regulated based on a constant ratio to the measured open circuit
voltage (VOC). If the output voltage is held constant, there is no attempt
to track the maximum power point, so it is not a maximum power point
tracking technique in a strict sense, though it does have some advantages
in cases when the MPP tracking tends to fail and is sometimes used to
supplement an MPPT method in those cases.
In the “constant voltage” MPPT method (also known as the ‘open volt-
age method’), the power delivered to the load is momentarily interrupted
and the open circuit voltage with zero current is measured. The controller
then resumes operation with the voltage controlled at a fixed ratio, such as
0.76, of the open circuit voltage VOC. This is usually a value which has been
determined to be the maximum power point, either empirically or based
on modeling, for expected operating conditions. The operating point of
the PV array is thus kept near the MPP by regulating the array voltage and
matching it to the fixed reference voltage Vref= k VOC, where K is constant.
The value of Vref may be also chosen to give optimal performance relative
to other factors as well as the MPP, but the central idea in this technique
is that Vref is determined as a ratio to VOC. One of the inherent approxima-
tions to the “constant voltage” ratio method is that the ratio of the MPP
voltage to VOC is only approximately constant, so it leaves room for further
possible optimization.
7.4.5 Comparison of MPPT Methods

Both perturb and observe and incremental conductance are examples of
“hill climbing” methods that can find the local maximum of the power
curve for the operating condition of the PV array to provide a true maxi-
mum power point.
The perturb and observe method (P&O) is capable of producing oscil-
lations of power output around the maximum power point even under
steady state irradiance [6].
The incremental conductance method has an advantage over the P&O
method in that it can determine the maximum power point without
oscillating around this value. It can perform maximum power point track-
ing under rapidly varying irradiation conditions with higher accuracy than
the perturb and observe method. However, the incremental conductance
method can produce oscillations and can perform erratically under rapidly
changing atmospheric conditions. The computational time is increased
due to slowing down of the sampling frequency resulting from the higher
complexity of the algorithm compared to the P&O method.
In the constant voltage ratio method, the current from the photovoltaic
array must be set to zero momentarily to measure the open circuit voltage
and afterwards, set to a predetermined percentage of the measured voltage,
usually around 76%. Energy may be wasted during the time the current is set
to zero. The approximation of 76% as the MPP/VOC ratio is not necessarily
accurate though. Although simple and low cost to implement, the interrup-
tions reduce array efficiency and do not ensure finding the actual maximum
power point. However, efficiencies of some systems may reach above 95%.
7.4.6 Operating Principle of P&O MPPT

At night, an off grid PV system may use batteries to supply loads. Although
the fully charged battery pack voltage may be close to the PV panel’s max-
imum power point voltage, this is unlikely to be true at sunrise when the
battery has been partially discharged. Charging may begin at a voltage con-
siderably below the PV panel maximum power point voltage and an MPPT
can resolve this mismatch [17].
When the batteries in an off grid system are fully charged and PV pro-
duction exceeds local loads, an MPPT can no longer operate the panel at
its maximum power point as the excess power has no load to absorb it. The
MPPT must then shift the PV panel operating point away from the max-
imum power point until production exactly matches demand. In a grid
connected photovoltaic system, all delivered power from solar modules are
sent to the grid. Therefore, the MPPT in a grid connected PV system will
always attempt to operate the PV modules at its maximum power point [2].
7.4.7 Simulation Results of PV-DVR System

To illustrate the capability of the PV-DVR for voltage sag, voltage swell,
and outage mitigation, a single phase system is considered. Figure 7.14
represents modeling of Buck-Boost inverter. The proposed DVR model
is simulated by MATLAB Simulink to compensate for voltage sag, voltage
swell, and outages at the load side. The total simulation period is 1s. In
MATLAB Simulink, DVR is simulated to be in operation only when the
e
IGBT IGBT1 ph
3
e
e
n
4
e
IGBT3 IGBT2
e
2 v
ne
Voltage Measurement 1 Scope1
Logical NOT NOTLogical
Operator Operator 1
Sine Wave Sine Wave 1 DO

Rector
DO
Operator1
Rector Rector
Rector
Operator Sequence 1
Sequence
Scope2
Figure 7.14 Simulation modeling of buck-boost inverter.
supply voltage differs from its nominal value or when the PV array gen-
erates excessive power or equal power to the load demand [16]. Thus, the
energy consumption from the utility grid is reduced. A single phase con-
trolled voltage source is used to provide a single phase variable voltage at
the source end. The source voltage, injected voltage, and load voltage of
the DVR system are shown in Figure 7.15 from the simulation results and
it is observed that the load voltage is unaffected by the voltage variation
events [18].
The PV array consists of 54 PV cells (6 × 9), 9 cells are kept connected
in series to have a desired voltage output of 12 V, and there are 6 paral-
lel branches giving a total power of 200W. The number of parallel PV
arrays is increased to 15 to get a 3000W power output array with a boost
converter that can give greater output voltage [6, 7]. The proposed fuzzy
controller based P&O MPPT controller tracked the maximum power
generated by the PV array with 82% efficiency. From the discharge char-
acteristics, it is observed that the battery can feed 90 A for a 5h duration.
A control circuit is incorporated with the proposed converter to regulate
the output voltage at 230V. It is evident that the proposed DVR recovers
the system to a steady state voltage of 1.0 p.u. within 0.1 ms with mini-
mum distortion [21].
source voltage
200
Vin ‫ڟ‬
100
-100
-200
DC voltage
-100
300
VDC
100
Inverter output
200
VInverter
100
-100
-200
Inverted voltage
100
50
VInjected
-50
-100
loud voltage
-100
200
Vout
-200
0 000 01 015 02 025 03 035 04 045 05
Time ‫ڟ‬
Figure 7.15 Simulation output of PV system with DVR.
7.4.8 Grid Connected System Using PV Syst Tool

The 10MW grid connected system was designed and located on the
University campus. The geographical data was captured throughout the
year. The model simulation design consists of PV arrays which are inter-
connected with six similar ratings of a 1.5 MW inverter. The simulation
procedure mainly focused and considered horizontal irradiation, tilt angle,
azimuth, and ambient temperature of the PV arrays. The system is defined
as the set of internal components establishing the PV modules, strings, and
inverter up to the connection of the grid. The PV system recommends a
procedure based on the predicted overload losses. This is usually leads to
nominal power ratios distantly below those recommended by the inverter’s
manufacturers [11].
8
Lc : Collection Loss (PV-array losses) 2.87 kWh/kWp/day
Ls : System Loss (Inverter, ...) 0.08 kWh/kWp/day
7 Yf : Producred useful energy (inverter output) 2.38 kWh/kWp/day
6
Normalized Energy [kWh/kWp/day]
0
Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec
Figure 7.16 Inverter output and PV array losses of 10MW grid connected system.
0.6
PR : Performance Ratio (Yf/Yr): 0.447
0.5
0.4
Performance Radio PR
0.3
0.2
0.1
0.0
Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec
Figure 7.17 Performance ratio throughout year.

7.4.8.1 PV System Simulation Result Analysis

The generated power is divided by the nominal power of the photovol-
taic array. The performance ratio is a pointed output of the quality of the
system itself, separate from the solar irradiance [20]. The yearly value is
calculated based on the temperature and irradiation of the PV system. The
monthly graphs are shown in Figure 7.16. The graph specifies a normal-
ized performance index of the PV array losses, inverter losses, and inverter
output based on the report analysed and optimisation involved throughout
the twelve month duration. Figure 7.17 shows performance ratio through-
out the year of the grid connected PV system.
7.5 Conclusion
The detailed study compared different types of inverter topologies
described for photovoltaic systems which are connected in the power
grid. To improve the power quality, total harmonic distortion is reduced
within the IEEE standard permissible limit. It analysed various inverter
topologies that reduced the cost and enhanced the efficiency and lifetime
of the switching device. The individual PV module is integrated with a
centralized inverter to connect in the power grid. In the modified multi
level inverter circuit, the PWM technique is employed. Input voltage is
adequately high to validate and avoid the voltage fluctuation that is inter-
faced with the power system. A high frequency transformer is issued for
further increasing of voltage in the inverter AC supply side. Current source
inverter and voltage source inverter are suitable for low power and high
power systems. Various multilevel inverters improved the output voltage
waveforms and reduced the total harmonic distortion. A bidirectional
DC-DC converter with a fuzzy logic controller based perturb and observe
maximum power point tracking algorithm is utilized in tracking the max-
imum power point of the PV array. Single bidirectional PV-DVR is used
in the modified circuit to reduce the energy utilization from the grid by
simultaneously disconnecting the grid from the load through soft switch-
ing devices. To increase the power level, the PV array is used and thus
the required load demand depends upon the load changes. To reduce the
panel cost and lessen the usage of the UPS and the voltage stabilizer for
equipment available at home and at small scale industries with optimal
usage of limited power rating, an industrial standard has to be established.
The MATLAB V13 simulation tool is used and the simulation results are
compared with optimization calculation carried out in Grid Connected

converters for solar photovoltaic power generation.
7.6 Future Scope of Work

These converters are extended to other renewable energy sources like wind,
biomass, and biogas.
i. More numbers of multilevel inverter topology will be ana-

lyzed with different control techniques.
ii. These DC-AC inverters are simulated and also extended
in digital signal processing in hardware implementation.
iii. The performance operation of various renewable energy
resources and optimistic techniques are utilized to achieve
the optimal efficiency and then connected in the grid
system.
iv. The whole system can be implemented with appropriate
application software using IoT.
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8
A Novel Fusion Switching Pattern
Generation Algorithm for “N-Level”
Switching Angle Algorithm Based Trinary
Cascaded Hybrid Multi-Level Inverter
Joseph Anthony Prathap1* and T.S. Anandhi2
1
Department of Electronics and Communication Engineering, School of
Engineering, Presidency University, Bengaluru, Karnataka, India
2
Department of Electronics and Instrumentation Engineering, Faculty of
Engineering and Technology, Annamalai University, Tamil Nadu, India
Abstract
This chapter presents a novel fusion algorithm, the Switching Angle Algorithm,
with no carrier to produce Digital Pulse Width Modulation control for the “N”-
level Trinary Cascaded Hybrid MLI circuit. The proposed fusion Switching Patterns
Generation algorithm includes experimental evaluation of the Digital PWM using
the Field Programmable Gate Array for the “N”-level Trinary Cascaded Hybrid
MLI. The TCHMLI with non-carrier based SAA utilizes unequal DC values with
trinary progression. The advantages of TCHMLI are higher voltage levels with
minimum switches, a decrease in %THD by achieving an increased level in MLI,
low distortion output response without filters, optimized power processing of the
overall system, and easy implementation using digital controllers. Conventionally,
the generation of switch patterns for the Multi-Level Inverter uses the sine wave as
modulating signal and high-frequency triangular wave as a carrier signal, whereas
the non-carrier Switching Angle Algorithms (SAA) utilize the events at which the
MLI levels change. Based on the event angle, the SAA is classified as: i) Equal
Phase-SAA (EP-SAA), ii) Half Equal Phase-SAA (HEP-SAA), iii) Feed Forward-
SAA (FF-SAA), and iv) Half Height-SAA (HH-SAA). Among these four meth-
ods, the HH-SAA method proves to be advantageous for parametric analysis like
THD%, VRMS, and VPEAK. The events of switching change based on the voltage steps
203
of the inverter circuit. Generally, the n-levels of the MLI circuit demands (n-1)/2
events of switching in each quadrant and 2(n-1) events of switching for one cycle
with a frequency of 50Hz. The simulations of the HH-SAA-Trinary Cascaded MLI
for the “N”-level are manipulated by the System Generator model and the para-
metric analysis is validated with an FPGA device. The fusion algorithm involves
the combination of the Digital Switching Function and Digital PWM using VHDL.
The DSFG and DSPG blocks are coded using the behavioral style of VHDL coding
for all the “N”-levels of TCHMLI.
Keywords: Switching angle algorithm, trinary cascaded hybrid multi-level

inverter, hardware description language, field programmable gate array
8.1 Introduction
The need for MLI topology design is to derive low cost and increased effi-
ciency with the optimum number of components [1]. Though many inverters
are classified based on the number of devices used, size, and design com-
plexity, MLI topologies have evolved by considering a reduced switch count
[2]. The MLI topology with reduced switches and DC voltages is adaptable
for several load-changing applications [3]. A low voltage components-based
inverter topology can utilize fewer switches and DC voltages with minimum
voltage stress [4]. The dual source-based MLI uses fewer power switches to
operate symmetrically and asymmetrically to suit the rooftop PV application
[5]. By utilizing a suitable pattern of switching devices, the staircase output
can be generated with low THD% [6]. To synthesize the Inverter AC outputs,
the Selective Harmonic Elimination is utilized to discard lower order har-
monics by optimizing the switching angles of the MLI [7].
In high-power voltage drives, the most ubiquitous converter topology is
the Cascaded MLI [8]. In Cascaded MLI, single phased H-structure bridge
circuits are linked in series along the AC branch to attain moderate opera-
tion of voltage and minimum distortion in harmonics. Also, the H-bridges
are fed with the number of detached DC sources. Based on the DC value
assignment for all the H-bridges, the MLI is divided as symmetrical when
all assigned DC values are equal and as asymmetrical when all assigned DC
values are unequal. To be specific, the Cascaded Asymmetrical MLI can
achieve higher levels of voltages with no additional H-bridge cells being
utilized, thus the output voltage signal has numerous voltage levels. For
Cascaded H-Bridge type converters, the odd sequence is used for defining
the levels of the voltage, represented as “m”. The merits of Cascaded MLI
are measured using the number of switching components, THD% effi-
ciency, switching voltage stress, and common-mode voltage [9]. Without
the requirement for a greater number of switches, the CMLI topology can
produce high-quality AC output [10]. Lowered switching loss, high effi-
ciency, and low voltage stress are the merits of CMLI for commercial appli-
cations [11].
Typically, a sinusoidal signal is used as the modulating signal along
with triangular waves as carriers for the operation of MLI circuitry and is
referred to as MLI based on carriers. The MLI based carrier includes direct
proportionality between the carrier count and voltage levels of the inverter
output. The inphase compensation technique with a reduced carrier PWM
scheme decreases the THD% of the AC output voltage [12]. The alternate
MLI design is based on the unused carrier signals that do not involve car-
riers in the generation of the MLI output, rather the event at which the
angles change is manipulated using a mathematical formulation called the
“Switching Angle Algorithm (SAA)” [13].
Angle approximation trajectories are used to produce the switching
angles in hardware by variable coefficient based polynomial equations [14].
The progression of the trinary sequence is assigned to the DC values
of the series-connected H-bridges circuitry to form the Trinary Cascaded
Hybrid MLI. The TCHMLI is suitable for the Switching Angle Algorithm
for the following reasons:
• Reduction in the THD% of the MLI output [15]

• Increased number of voltage levels in the MLI output with
low usage of switching transistors [16]
• Minimized noise response in the output without filters
• Enhanced system manipulation for power
• Simple realization with modern controllers [17]
In this chapter, the novel fusion switching pattern generation algo-

rithm is proposed using the Switching Angle Method for the N-levels of
Trinary Cascaded Hybrid MLI. The Switching Angles are generated for
the N-levels ranging from 3 to 81 and converted to the binary equiva-
lence of 2n resolution (n = 8, 11, 12 bits) to develop the VHDL code. The
developed VHDL code can generate Digital Switching Pulses as per the
selection of the levels for the TCHMLI. The HDL code is developed in a
structural model by two blocks, namely Digital Switching Functions and
Digital PWM, and validated using the FPGA (Spartan 3A DSP). The FPGA
chip based switching controller executes faster than the microcontroller by
99.9% [18]. This chapter discusses the topology of the TCHMLI, preceded
by the formulation of the different SAA algorithms and their binary equiv-
alence. Depending on the binary values, the VHDL code is developed for
the generation of Digital Switching Patterns for all levels from N = 3 to 81.
The levels of 9, 27, and 81 are considered for the validation of the proposed
algorithms in simulation and the 81-level TCHMLI is explained with real-
time validation by the FPGA device (Spartan 3A DSP).
8.2 Trinary Cascaded Hybrid MLI Circuitry

The proposed Trinary Cascaded Hybrid MLI Topology utilizes the H-bridge
circuit connected in series with the Trinary progression of the DC values for
the H-bridges. The series-connected inverter circuitry along with the uti-
lization of unequal DC inputs attains an accurate output signal with fewer
switches. Addition and subtraction are performed with these uneven DC val-
ues to enhance the steps of the inverter output. This is accomplished by the
Trinary Cascaded Hybrid MLI circuit structure that can generate higher steps
of inverter output with z constant value of series-connected H-bridges. The
Trinary CHMLI has the DC input value in the order of 3, as depicted in (8.1)
VDCk = 3k−1V (8.1)
where “VDCk” is the value of DC input for the H-bridge circuit,

“k” is the number of H-bridge structure in TCHMLI,
and “V” is the value of voltage in the H-bridge.
Figure 8.1 presents the structure of an H-bridge circuit that consists of a

DC source and four switches of MOSFET type. The Digital PWM waveform
controls the four MOSFET switches of the H-bridge to achieve the neces-
sary voltage levels of the inverter output. The four switching MOSFET are
designated as SW11, SW12, SW13, and SW14. For instance, SW14 represents
the fourth MOSFET component in the first H-bridge circuit of the Trinary
Cascaded Hybrid MLI. As stated earlier, the DC values added and sub-
tracted for the required level of the MLIs are accomplished by the flow of
the current path in the H-bridge circuit.
The positive voltage step is derived by the current path in the H-bridge
through SW11, SW14, and across the resistive load, as given in Figure 8.2.
Switches SW11 and SW14 are ON and switches SW12 and SW13 are OFF to
obtain the addition of the DC level values.
Analogously, the negative DC voltage step is extracted by the current
path in the H-bridge through SW12, SW13, and across the resistive load, as
shown in Figure 8.3. Here, switches SW12 and SW13 are ON and switches
SW11 and SW14 are OFF to obtain the subtraction of the DC level values.
1 3
S 11 S 13
D
g
g
m
m
S
S
DC Source
2 4
S 12 S 14
D
g
D
g
m
m
S
S
Figure 8.1 Schematic of the H-bridge unit.
1 3
S 11 S 13
D
D
g
g
m
m
S
DC Source
2 4
LOAD
S 12 S 14
D
D
g
g
m
m
S
Figure 8.2 Direction of current path in H-bridge for positive value.
The basic rule of the H-bridge circuitry is that only diagonal switches are
to be in the ON state at a time. That is, SW11 and SW14 or SW12 and SW13.
This proves that the switching of the MOSFET in the Trinary Cascaded
Hybrid MLI should be accurate to peak its efficiency of the inverter circuit.
1 3
S 11 S 13
D
D
g
g
m
m
S
DC Source S
2 4
LOAD
S 12 S 14
D
D
g
g
m
m
S
S
Figure 8.3 Direction of current path in H-bridge for negative value.
8.3 Switching Angle Algorithm

Conventionally, the MLI is driven by carrier-based modulation schemes
such as a Modulating Sine wave overlapped with a high frequency
Triangular/Saw-tooth Carrier wave, namely Phase Disposition, Phase
Opposite Disposition, Alternate Phase Opposite Disposition, etc. Recently,
the Switching Angle Algorithm (SAA) is utilized for PWM generation. The
Switching Angle Algorithm (SAA) determines the ON and OFF events of
PWM signals by making use of the mathematical formula. The Switching
Angles Algorithms are classified into four categories and can be readily
used in the Trinary Cascaded Hybrid MLI structure:
• Equal Phase Switching Angle Algorithm (EP-SAA)

• Half Equal Phase Switching Angle Algorithm (HEP-SAA)
• Feed Forward Switching Angle Algorithm (FF-SAA)
• Half Height Switching Angle Algorithm (HH-SAA)
The events of the angles for switching in SAA change based on the num-
ber of voltage steps in the Trinary Cascaded Hybrid MLI circuit. In formu-
m −1
lation, the angles of switching per quadrant can yield the required
2
“m” levels of inverter output. The MLI output signals is separated into four
quadrants, namely (0°-90°), (90°-180°), (180°-270°), and (270°-360°), by
the SAA. The manipulated angles of switching in SAA for all quadrants are
easy and connected. The formulations for the four SAA are given below.
8.3.1 Equal Phase Switching Angle Algorithm (EP-SAA)

The events of switching are manipulated and placed at common intervals
from 0 to π, as represented in Equation (8.2):
180° m −1
αi = , where i = 1,2,…., (8.2)
m 2
8.3.2 Half Equal Phase Switching Angle Algorithm (HEP-SAA)

The events of switching are placed with equal intervals in alternate angles,
as given by (8.3):
90° 180° m −1
αi = i =i , where i = 1,2,…., (8.3)
m +1 m +1 2
2
8.3.3 Feed Forward Switching Angle Algorithm (FF-SAA)

The events of switching are designated with equal intervals to one-fourth
of the MLI to reduce the wide space between the positive half and the neg-
ative half compared to the other SAA, as shown in (8.4)
1  1 2  1 −1  2i − 1 
α i = sin −1  i −  = sin (8.4)
2   2 m − 1  2
  m −1
m −1
where i = 1,2, ….,
2
8.3.4 Half Height Switching Angle Algorithm (HH-SAA)

The events of switching angles are marked with uncommon space until
one-half of the MLI output and with equal space in alternate angles over
half of the MLI response, as formulated in (8.5)
 1 2   2i − 1 
α i = sin −1  i −   = sin −1 (8.5)
  
2 m −1   m −1
m −1
where i = 1,2, ….,
2
In this work, all the SAA methods are developed using VHDL coding
language to generate the N-level of TCHMLI ranging from N = 3 to 81
levels. The bit representation of the evaluated values is considered for the
development of VHDL code in the structural model for the 28, 211, and 212
resolutions. Within the developed VHDL code, two blocks designated as
Switching Function block and Switching Pattern block are manipulated as
per the in-demand switches of the Trinary Cascaded Hybrid MLI circuit.
8.4 9-Level Trinary Cascaded Hybrid Multi-Level

Inverter
Figure 8.4 depicts the Trinary Cascaded Hybrid MLI structure for the 9-level
MLI that consists of IV as DC input for the top H-bridge circuit and 3V as
DC input for the bottom H-bridge circuit. The DC voltages are combined
as given in Table 8.1 to achieve the nine steps of the inverter output. Based
on the DC values combination, the digital switching patterns for the four
switches of the H-bridge are assigned with 1001 for the positive value of the
DC, 0110 for the negative value of the DC, and 0101 or 1010 for no value of
the DC. The digital switching patterns to give the positive 4 levels and neg-
ative 4 levels of 9-level TCHMLI are depicted in Tables 8.2 and 8.3, respec-
tively. The features of the Trinary Cascaded Hybrid MLI for the 9-levels are:
• Series Connection of two H-bridges

• Eight MOSFET switches with Digital PWM control
• The DC value assigned for the 9–level MLI is
• For Top H-bridge, k=1; VDC1 = 31-1V=30V = V
• For Bottom H-bridge, k=2; VDC2 = 32-1V=31V = 3V
8.4.1 SAA for 9-Level TCHMLI

The 9-level TCHMLI for the SAA requires 4 switching angles per quad-
rant, hence the total number of switching angles is 16 per cycle for an AC
output of the 9-Level TCHMLI. The four SAA generate different switching
angles, as given in Table 8.4.
H-Bridge l
1 2
s11 s13
D
g
D
g
Mosfet Mosfet1
m
m
S
S
Vdc1
(E)
3 4
s12 s14
D
D
g
g
Mosfet3 Mosfet2
m
m
S
S
R-load
H-Bridge II
5 6
s21 s23
D
g
D
g
Mosfet4 Mosfet5
m
m
S
S
Vdc2
(3E)
7 8
s22 s24
D
g
D
g
Mosfet7 Mosfet6
m
m
S
S
Figure 8.4 Schematic of 9-level TCHMLI.

Table 8.1 Voltage steps for trinary cascaded hybrid MLI of 9-levels.
DC input DC input
Positive steps manipulation Negative steps manipulation
1 +1 -1 -1
2 -1+3 = +2 -2 +1-3 = -2
3 +3 = 3 -3 -3
4 +1+3 = +4 -4 -1-3 = -4
Table 8.2 Digital PWM for positive half of 9-level trinary cascaded
hybrid MLI.
Positive 1st H-bridge 2nd H-bridge
voltage
steps SW11 SW12 SW13 SW14 SW21 SW22 SW23 SW24
4 1001 1001
3 0101 1001
2 0110 1001
1 1001 0101
0 0101 0101
1010 1010
Table 8.3 Digital PWM for negative half of 9-level trinary cascaded
hybrid MLI.
Negative 1st H-bridge 2nd H-bridge

voltage
steps SW11 SW12 SW13 SW14 SW21 SW22 SW23 SW24
-4 0110 0110
-3 0101 0110
-2 1001 0110
-1 0110 0101
0 0101 0101
1010 1010
Table 8.4 16 switching angles equivalence for 9-Level TCHMLI using SAA.
9-level TCHMLI using EP-SAA
First quadrant (0 to 90) Second quadrant (90 to 180) Third quadrant (180 to 270) Fourth quadrant (270 to 360)
Actual Binary Actual Binary Actual Binary Actual Binary
angle equivalent angle equivalent angle equivalent angle equivalent
20 3 80 17 200 35 280 49
40 7 60 21 220 39 300 53
60 10 40 24 240 42 320 56
80 14 20 28 260 46 340 60
9-level TCHMLI using HEP-SAA
18 3 108 19 198 35 288 51
36 6 126 22 216 38 306 54
54 9 144 25 234 41 324 57
Cascaded Hybrid MLI
72 12 162 28 252 44 342 60

(Continued)
213
Table 8.4 16 switching angles equivalence for 9-level TCHMLI using SAA. (Continued)
9-level TCHMLI using FF-SAA
3.59 1 149.47 27 183.59 33 329.47 59
11.012 2 160.65 29 191.01 34 340.65 61
19.34 4 168.98 31 199.34 35 348.98 63
30.52 6 176.40 32 210.52 37 356.40 64
9-level TCHMLI using HH-SAA
7.18 1 118.95 21 187.18 33 298.95 53
22.02 3 141.31 25 202.02 35 321.31 57
38.68 6 157.97 28 218.68 38 337.97 60
61.04 10 172.81 30 241.044 42 352.81 62
The generated angles are converted into binary equivalence by taking

into consideration the resolution of 26 bits. The resolution of 26 bits can
generate 64 bits for one cycle of the 9-level TCHMLI AC output. The res-
olution of 26 bits for the SAA uses the scaling value of 5.625 to convert
the 360-degree angles into binary equivalence. The binary equivalent val-
ues of the first and third quadrants are considered for the ON and OFF
events of the 4 Digital Switching Functions in the positive cycle of the
9-level TCHMLI. Also, the binary equivalent values of the second and
fourth quadrants are utilized for the ON and OFF events of the 4 Digital
Switching Functions in the negative cycle of the 9-level TCHMLI. Among
the four SAA methods, the HH-SAA has a common ON period of 32 units
for all the 8 Digital Switching Functions of the 9-level TCHMLI.
8.4.2 Generation of Switching Function for the 9-Level Trinary

Cascaded Hybrid MLI
The 2n bits are taken into consideration for the generation of the Switching
Function in Digital form. The 9-levels of MLI output requires 8 signals of
switching functions, out of which four are utilized for the positive half and
four are used for the negative half of the waveform. The switching functions
produced in the positive half and negative half should be complementary.
For the validation, the HDL code of 9-level switching function generation
is developed using the conditional block in the behavioral model.
8.4.3 Generation of DPWM for the 9-Level Trinary Cascaded

Hybrid MLI
By utilizing logic switching patterns are designed for the 8 switches of the
9-level Trinary Cascaded Hybrid MLI circuit. Functionally, the positive
and negative edges of the switching patterns are derived using the XOR
gate. The OR gate helps in the combinations of different switching func-
tions for Switching Pattern development. The 9-level TCHMLI requires 8
Digital PWM for manipulation of the required AC response. The Digital
PWM of the 8 switches of the 9-Level TCHMLI are derived from Tables 8.2
and 8.3. The generated HDL code based Digital PWM signals control the 8
switches of the 9-level Trinary Cascaded Hybrid MLI.
8.4.4 Simulation Results of 9-Level Trinary Cascaded Hybrid

MLI
The 9-level TCHMLI is generated using the four SA Algorithms. The
developed VHDL code for DSF and DSP generation is translated into the
MATLAB SIMULINK block using the Xilinx System Generator software.
Figure 8.5 depicts the generation of switching patterns for the 8 switches of
the 9-level Trinary Cascaded Hybrid MLI using the EP-SAA. The AC output
of the 9-level TCHMLI using the MATLAB SIMULINK System Generator
is given in Figure 8.6. The THD% for the simulated 9-level TCHMLI using
the EPM is presented in Figures 8.7, 8.8, 8.9, and 8.10 show the switching
pattern generation, AC output voltage, and the THD% evaluation of the
9-Level TCHMLI using the HEP-SAA. The FFM based 9-Level TCHMLI
with the Switching Patterns is given in Figure 8.11. Figures 8.12 and 8.13
show the AC output and THD% for the FFM based 9-level TCHMLI. The
DPWM for the 8 switches of the 9-level TCHMLI is depicted in Figure 8.14
with the corresponding AC output, as shown in Figure 8.15 and THD% is
given in Figure 8.16.
Figure 8.5 Digital PWM of the EP-SAA based 9-level trinary cascaded hybrid MLI.
Multi-Level Inverter 9- Level
Equal Phase Method
40
X: 0.005
Y: 39.84
30
20
10
Amplitude in volts
-10
-20
-30
X: 0.015
Y: -39.84
-40
0 0.01 0.02 0.03 0.04 0.05 0.06
Time in secs
Figure 8.6 AC output of EP-SAA based 9-level trinary cascaded hybrid MLI.
Signal to analyze Available signals

Display selected signal Display FFT window Structure:
Selected signal: 1 cycles. FFT window (in red): 1 cycles ScopeData
Input:
20 input 1
0 Signal number:
1
-20
FFT window
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
Start time (s: 0.0
FFT analysis
Number of cycles: 1
Fundametal (50Hz) = 36.53 , THD= 20.96% Fundamental frequency (Hz):

18
50
16
14
FFT settings
12 Display style:
10 Bar (selective to fundamental)
8 Base value: 1.0
6 Frequency axis:
4 Hertz
2 Max Frequency (Hz):
0 1000
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Display Close
Figure 8.7 THD% of EP-SAA based 9-level trinary cascaded hybrid MLI.
Figure 8.8 Digital PWM of the HE-SAA based 9-level trinary cascaded hybrid MLI.
Multi-Level Inverter 9-Level

Half Equal Phase Method
40
X: 0.006
Y: 39.84
30
20
10
Amplitude in volts
-10
-20
-30
X: 0.015
Y: -39.84
-40
0 0.01 0.02 0.03 0.04 0.05 0.06
Figure 8.9 AC output of HEP-SAA based 9-level trinary cascaded hybrid MLI.

Input:
20 input 1
0 Signal number:
1
-20
FFT window
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
Start time (t): 0.0
FFT analysis
Number of cycles: 1

16
50
14
12 FFT settings
Display style:
10
Bar (selective to fundamental)
8
Base value: 1.0
6
Frequency axis:
4
Hertz
2
Max Frequency (Hz):
0
1000
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Display Close
Figure 8.10 THD% of HEP-SAA based 9-level trinary cascaded hybrid MLI.
Figure 8.11 Digital PWM of FF-SAA based 9-level trinary cascaded hybrid MLI.
Multi-Level Inverter 9- Level

Freed Forward Method
40
X: 0.005
Y: 39.84
30
20
10
Amplitude in volts
-10
-20
-30
X: 0.015
Y: -39.84
-40
0 0.01 0.02 0.03 0.04 0.05 0.06
Time in secs
Figure 8.12 AC output of FF-SAA based 9-level trinary cascaded hybrid MLI.

Input:
20 input 1
0 Signal number:
1
-20
FFT window
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
Start time (s: 0.0
FFT analysis
Number of cycles: 1
18
50
16
14 FFT settings
Display style:
12
10
8 Base value: 1.0
6 Frequency axis:
4 Hertz
2 Max Frequency (Hz):
0 1000
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Display Close
Figure 8.13 THD% of FF-SAA based 9-level trinary cascaded hybrid MLI.
Figure 8.14 Digital PWM of HH-SAA based 9-level trinary cascaded hybrid MLI.

Half Height Method
40
X: 0.005
Y: 39.84
30
20
10
Amplitude in volts
-10
-20
-30
X: 0.015
Y: -39.84
-40
0 0.01 0.02 0.03 0.04 0.05 0.06
Time in secs
Figure 8.15 AC output of HH-SAA based 9-level trinary cascaded hybrid MLI.

Input:
20
input 1
0 Signal number:
1
-20
FFT window
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
Start time (s): 0.0
FFT analysis
Number of cycles: 1
50
5
FFT settings
4
Display style:

3
Base value: 1.0

2
Frequency axis:
1 Hertz
Max Frequency (Hz):
0 1000
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Display Close
Figure 8.16 THD% of HH-SAA based 9-level trinary cascaded hybrid MLI.
8.5 27-Level Trinary Cascaded Hybrid MLI

The 27-Level Trinary Cascaded Hybrid MLI involves the use of 3 H-Bridge
circuits with unequal DC value sources. The 3 H-Bridges are arranged in
series to satisfy the cascaded form of the TCHMLI topology. The unequal
DC value of the H-Bridges is assigned in the Trinary progression of the
names as 1E, 3E, and 9E. The number of switches used in the 27-level
TCHMLI is 12, represented as SW11, SW12, SW13, and SW14 for the top
H-bridge, SW21, SW22, SW23, and SW24 for the middle H-bridge, and SW31,
SW32, SW33, and SW34 for the bottom H-bridge.
The 27-level TCHMLI utilizes 13 levels in the positive half, 13 levels
in the negative half, and 1 zero level, as given in Table 8.5. Each of the 12
switches is driven by the desired PWM signals to generate the required
27 level AC output. Tables 8.6 and 8.7 depict the Digital PWM of the 12
switches for the 27-level TCHMLI circuit. The features of the Trinary
Cascaded Hybrid MLI for the 27-level are:
• Series Connection of three H-bridges

• Twelve MOSFET switches with Digital PWM controls
• For 1st H-bridge, k=1; VDC1 = 31-1V=30V = V
Table 8.5 Voltage steps for the trinary cascaded hybrid MLI of 27-levels.
DC input DC input
Positive steps manipulation Negative steps manipulation
1 +1 -1 -1
2 -1+3 = +2 -2 +1-3 = -2
3 +3 -3 -3
4 +1+3 = +4 -4 -1-3 = -4
5 -1-3+9 = +5 -5 +1+3-9 = -5
6 -3+9 = +6 -6 +3-9 = -6
7 +1-3+9 = +7 -7 -1+3-9 = -7
8 -1+9 = +8 -8 +1-9 = -8
9 +9 -9 -9
10 +1+9 = +10 -10 -1-9 = -10
11 -1+3+9 = +11 -11 +1-3-9 = -11
12 +3+9 = +12 -12 -3-9 = -12
13 +1+3+9 = +13 -13 -1-3-9 = -13
• For 2nd H-bridge, k=2; VDC2 = 32-1V=31V = 3V

• For 3rd H-bridge, k=3; VDC3 = 33-1V=32V = 9V
The Trinary Cascaded Hybrid MLI circuit used for the generation of
27-levels is depicted in Figure 8.17. The three H-bridges are connected in
series from the 2nd branch of the 1st H-bridge to the 1st branch of the 2nd
H-bridge and the same format is sustained in the preceding bridges. The
developed switching patterns by VHDL coding are given to the switches
of Trinary Cascaded Hybrid MLI to generate the required 27-levels in the
output.
8.5.1 SAA for 27-Level TCHMLI

The 27-level TCHMLI for the SAA requires 13 Switching angles per quad-
rant, hence the total number of switching angles is 52 per cycle for the AC
output of the 27-Level TCHMLI. The switching angles are generated for the
Table 8.6 Digital PWM for positive half of 27-level trinary cascaded hybrid
MLI.
Positive 1st H-bridge 2nd H-bridge 3rd H-bridge

voltage SW11 SW12 SW13 SW21 SW22 SW23 SW31 SW32 SW33
steps SW14 SW24 SW34
13 1001 1001 1001
12 0101 1001 1001
11 0110 1001 1001
10 1001 0101 1001
9 0101 0101 1001
8 0110 0101 1001
7 1001 0110 1001
6 0101 0110 1001
5 0110 0110 1001
4 1001 1001 0101
3 0101 1001 0101
2 0110 1001 0101
1 1001 0101 0101
0 0101 0101 0101
1010 1010 1010
four SAA methods. The generated angles are converted into binary equiva-
lence by taking into consideration a resolution of 27 bits. The resolution of
27 bits can generate 128 bits for one cycle of the 27-level TCHMLI AC out-
put. The resolution of 27 bits for the SAA uses a scaling value of 2.8125 to
convert the 360-degree angles into binary equivalence. The binary equiva-
lent values of the first and third quadrants are considered for the ON and
OFF event of the 13 Digital Switching Functions in the positive cycle of the
27-level TCHMLI. Also, the binary equivalent values of the second and
fourth quadrants are utilized for the ON and OFF events of the 13 Digital
Switching Functions in the negative cycle of the 27-level TCHMLI.
Table 8.7 Digital PWM for negative half of 27-level trinary cascaded hybrid
MLI.
Negative 1st H-bridge 2nd H-bridge 3rd H-bridge

voltage SW11 SW12 SW13 SW21 SW22 SW23 SW31 SW32 SW33
steps SW14 SW24 SW34
-13 0110 0110 0110
-12 0101 0110 0110
-11 1001 0110 0110
-10 0110 0101 0110
-9 0101 0101 0110
-8 1001 0101 0110
-7 0110 1001 0110
-6 0101 1001 0110
-5 1001 1001 0110
-4 0110 0110 0101
-3 0101 0110 0101
-2 1001 0110 0101
-1 0110 0101 0101
0 0101 0101 0101
1010 1010 1010
Tables 8.8, 8.9, 8.10, and 8.11 depict the binary equivalence of the 52
switching angles for the 27-level TCHMLI using EP-SAA, HEP-SAA,
FF-SAA, and HH-SAA, respectively. Among the four SAA methods, the
HH-SAA has a common ON period of 64 units for all 26 Digital Switching
Functions of the 27-level TCHMLI.

Trinary Cascaded Hybrid MLI
Function in Digital form. The 27-levels of MLI output requires 12 signals
1 2
s11 s13
D
g
g
m
m
S
S
1V
3 4
s12 s14
D
D
g
g
m
m
S
S
5 6
s21 s23
D
g
D
g
+
m
m
S
R LOAD
3V
7
8
s22 s24
D
D
g
g
m
m
S
9 10
s31 s33
D
D
g
g
m
m
S
9V
11
12
s32 s34
D
D
g
g
m
S
S
Figure 8.17 H-bridge structure of the 27-level TCHMLI topology.

Table 8.8 52 switching angles equivalence for 27-level TCHMLI using EP-SAA.
Second quadrant (90º to Third quadrant (180º to Fourth quadrant (270º to
First quadrant (0º to 90º) 180º) 270º) 360º)
6.66 2 93.33 33 186.66 66 273.33 97
13.33 4 100 35 193.33 68 280 99
20 7 106.66 37 200 71 286.66 101
26.66 9 113.33 40 206.66 73 293.33 104
33.33 11 120 42 213.33 75 300 106
40 14 126.66 45 220 78 306.66 109
46.66 16 133.33 47 226.66 80 313.33 111
53.33 18 140 49 233.33 82 320 113
60 21 146.66 52 240 85 326.66 116
66.66 23 153.33 54 246.66 87 333.33 118
73.33 26 160 56 253.33 90 340 120
80 28 166.66 59 260 92 346.66 123
86.66 30 173.33 61 266.66 94 353.33 125
Table 8.9 52 switching angles equivalence for 27-level TCHMLI using HEP-SAA.
Second quadrant (90º to Third quadrant (180º to Fourth auadrant (270º to
6.42 2 96.42 34 186.42 66 276.42 98
12.85 4 102.85 36 192.85 68 282.85 100
19.28 6 109.28 38 199.28 70 289.28 102
25.71 9 115.71 41 205.71 73 295.71 105
32.14 11 122.14 43 212.14 75 302.14 107
38.57 13 128.57 45 218.57 77 308.57 109
45 16 135 48 225 80 315 112
51.42 18 141.42 50 231.42 82 321.42 114
57.85 20 147.85 52 237.85 84 327.85 116
64.28 22 154.28 54 244.28 86 334.28 118
70.71 25 160.71 57 250.71 89 340.71 121
77.14 27 167.14 59 257.14 91 347.14 123
83.57 29 173.57 61 263.57 93 353.57 125
Table 8.10 52 switching angles equivalence for 27-level TCHMLI using FF-SAA.
1.10 1 142.97 48 181.10 64 322.97 114
3.31 2 148.89 50 183.31 65 328.89 116
5.54 3 153.06 52 185.54 66 333.06 118
7.80 4 156.52 54 187.80 67 336.52 119
10.12 5 159.58 55 190.12 68 339.58 120
12.51 6 162.38 56 192.51 69 342.38 121
15 7 165 57 195 70 345 122
17.61 8 167.48 58 197.61 71 347.48 123
20.41 9 169.87 59 200.41 72 349.87 124
23.47 10 172.19 60 203.47 73 352.19 125
26.93 11 174.45 61 206.93 75 354.45 126
31.1 13 176.68 62 211.10 77 356.68 126
37.02 15 178.89 63 217.02 79 358.89 127
Table 8.11 52 switching angles equivalence for 27-level TCHMLI using HH-SAA.
2.20 1 105.94 37 182.20 65 285.94 101
6.62 3 117.79 41 186.62 67 297.79 105
11.08 4 126.12 44 191.08 68 306.12 108
15.61 6 133.04 47 195.61 70 313.04 111
20.25 8 139.16 49 200.25 72 319.16 113
25.02 9 144.76 51 205.02 73 324.76 115
30 11 150 53 210 75 330 117
35.23 13 154.97 55 215.23 77 334.97 119
40.83 15 159.74 56 220.83 79 339.74 120
46.95 17 164.38 58 226.95 81 344.38 122
53.87 20 168.91 60 233.87 84 348.91 124
62.20 23 173.37 61 242.20 87 353.37 125
74.05 27 177.79 63 254.05 91 357.79 127
of switching functions that include 13 signals utilized for the positive half
and 13 signals for the negative half of the waveform. The switching func-
tions produced in the positive half cycle and negative half cycle should
be complementary. For the validation of the VHDL code for the 27-level
switching function generation, the code is developed using the conditional
block in a behavioral model.
8.5.3 Generation of DPWM for the 27-Level Trinary Cascaded

Hybrid MLI
By utilizing the logic gates such as XOR & OR, the required switching pat-
terns are designed for the 12 switches of the 27-level Trinary Cascaded
Hybrid MLI circuit. Functionally, the positive and negative edges of the
Digital PWM are derived using the XOR gate. Similarly, the levels of
the Digital PWM are derived using the OR gate. The 27-level TCHMLI
requires 12 Digital Switching Patterns for the generation of the required
AC outputs. The generated HDL code based Digital PWM signals controls
the 12-switches of the 27-level Trinary Cascaded Hybrid MLI.

MLI
The 27-level TCHMLI is generated using the four SAA algorithms. The
developed VHDL code for the DSF and DSP generation is translated into
the MATLAB SIMULINK block using Xilinx System Generator software.
Figure 8.18 depicts the generation of 26 Digital Switching Functions and
Figure 8.19 shows the switching patterns for the 12 switches of the 27 level
TCHMLI using the EP-SAA. The AC output of the 27-level TCHMLI using
the MATLAB SIMULINK System Generator is given in Figure 8.20. The
THD% for the simulated 9-level TCHMLI using the EPM is presented in
Figure 8.21. Figures 8.22, 8.23, 8.24, and 8.25 show the Digital Switching
Functions, Digital Switching Pattern Generation, AC output voltage, and
the THD% evaluation of the 27-Level TCHMLI using the HEP-SAA. The
FFM-based 27-Level TCHMLI with the Digital Switching Functions and
Digital Switching Patterns is given in Figures 8.26 and 8.27, respectively.
Figures 8.28 and 8.29 show the AC output and THD% for the FFM based
27-level TCHMLI. The Digital Switching Functions and DPWM for the 12
switches of the 27-level TCHMLI are depicted in Figure 8.30 and Figure
8.31 with the corresponding AC output shown in Figure 8.32 and THD%
in Figure 8.33.
Figure 8.18 Digital switching function of the EP-SAA based 27-level trinary cascaded
hybrid MLI.
Figure 8.19 Digital PWM of the EP-SAA based 27-level trinary cascaded hybrid MLI.

Equal Phase Method
150
X: 0.005
Y: 129.2
100
50
Amplitude in volts
-50
-100
X: 0.015
Y: -129.2
-150
0 0.01 0.02 0.03 0.04 0.05 0.06
Time in secs
Figure 8.20 AC output of EP-SAA based 27-level trinary cascaded hybrid MLI.

Input:
100
50 input 1
0 Signal number:
-50 1
-100
FFT window
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
Start time (s): 0.0
FFT analysis
Number of cycles: 1
12 50
10 FFT settings
Display style:
8
6 Base value: 1.0
4 Frequency axis:
Hertz
2
Max Frequency (Hz):
0 1000
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Display Close
Figure 8.22 Digital switching function of the HEP-SAA based 27-level trinary cascaded
hybrid MLI.
Figure 8.23 Digital PWM of the HEP-SAA based 27-level trinary cascaded hybrid MLI.

Half Equal Phase Method
150
X: 0.006
Y: 129.2
100
50
Amplitude in volts
-50
-100
X: 0.015
Y: -129.2
-150
0 0.01 0.02 0.03 0.04 0.05 0.06
Time in secs
Figure 8.24 AC output of HEP-SAA based 27-level trinary cascaded hybrid MLI.

Input:
100
50 input 1
0 Signal number:
-50 1
-100
FFT window
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
Start time (s): 0.0
FFT analysis Number of cycles: 1
Fundametal (50Hz) = 109 , THD= 13.53% Fundamental frequency (Hz):
12 50
10 FFT settings
Display style:
8
6
Base value: 1.0
4 Frequency axis:
Hertz
2
Max Frequency (Hz):
0 1000
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Display Close
Figure 8.26 Digital switching function of the FF-SAA based 27-level trinary cascaded
hybrid MLI.
Figure 8.27 Digital PWM of the FF-SAA based 27-level trinary cascaded hybrid MLI.
Multilevel Inverter 27 Level

Freed Forward Method
150
X: 0.005
Y: 129.2
100
50
Amplitude in volts
-50
-100
X: 0.015
Y: -129.2
-150
0 0.01 0.02 0.03 0.04 0.05 0.06
Time in secs
Figure 8.28 AC output of FF-SAA based 27-level trinary cascaded hybrid MLI.
Input:
100
50 input 1
0 Signal number:
-50 1
-100
FFT window
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
Start time (s): 0.0
FFT analysis
Number of cycles: 1
Fundamental (50Hz) = 151.2 , THD= 15.44%

Fundamental frequency (Hz):
16
50
14
FFT settings
12
Display style :
10
Bar (relative to fundamental)
8
Base value: 1.0
6
Frequency axis:
4
Hertz
2
Max Frequency (Hz):
0 1000
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Figure 8.30 Digital switching function of HH-SAA based 27-level trinary cascaded
hybrid MLI.
Figure 8.31 Digital PWM of HH-SAA based 27-level trinary cascaded hybrid MLI.

Half Heighy Method
150
X: 0.005
Y: 129.2
100
50
Amplitude in volts
-50
-100
X: 0.015
Y: -129.2
-150
0 0.01 0.02 0.03 0.04 0.05 0.06
Time in secs
Figure 8.32 AC output of HH-SAA based 27-level trinary cascaded hybrid MLI.

100 Input:
50 input 1
0 Signal number:
-50 1
-100
FFT window
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
Start time (s): 0.0
FFT analysis
Number of cycles: 1
1.4
50
1.2
FFT settings
1 Display style:
0.8 Bar (selective to fundamental)
0.6 Base value: 1.0
Frequency axis:
0.4
Hertz
0.2
Max Frequency (Hz):
0 1000
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Display Close
8.6 81-Level Trinary Cascaded Hybrid MLI

The 81-level Trinary Cascaded Hybrid MLI involves the use of four
H-Bridge circuits with unequal DC value sources. The four H-Bridges are
arranged in series to satisfy the cascaded form of the TCHMLI topology.
The unequal DC value of the H-Bridges are assigned in the Trinary pro-
gression of the names as 1V, 3V, 9V, and 27V. The number of switches used
in the 81-level TCHMLI is 16, represented as SW11, SW12, SW13, and SW14
for the 1st H-bridge, SW21, SW22, SW23, and SW24 for the 2nd H-bridge, SW31,
SW32, SW33, and SW34 for the 3rd H-bridge, and SW41, SW42, SW43, and SW44
for the 4th H-bridge.
The 81-level TCHMLI utilizes 40-levels in the positive half, 40-levels in
the negative half, and 1 zero level, as given in Table 8.12 and Table 8.13,
respectively. Each of the 16 switches is driven by the desired PWM signals
to produce the required 81-level AC output. Tables 8.14 and 8.15 show the
Digital PWM of the 16 switches for 81-level Trinary Cascaded Hybrid MLI
circuit. The features of the Trinary Cascaded Hybrid MLI for the 81-level
are:
• Series Connection of four H-bridges

• 16 MOSFET switches with Digital PWM control
• For 1st H-bridge, k=1; VDC1 = 31-1V=30V = V
• For 2nd H-bridge, k=2; VDC2 = 32-1V=31V = 3V
• For 3rd H-bridge, k=3; VDC3 = 33-1V=32V = 9V
• For 4th H-bridge, k=4; VDC4 = 34-1V=33V = 27V
The 81-level Trinary Cascaded Hybrid MLI circuit topology is presented

in Figure 8.34, consisting of 4 H-bridges and 16 MOSFET switches. The
developed switching patterns by VHDL coding are given to the switches
of Trinary Cascaded Hybrid MLI to generate the required 81-levels in the
output.
The advantage of the Trinary Cascaded Hybrid MLI is less number of
MOSFET switches used in the circuit compared to the other MLI circuitry,
as visualized in Table 8.16.
8.6.1 SAA for 81-Level Trinary Cascaded Hybrid MLI

The 81-level Trinary Cascaded Hybrid MLI for the SAA requires 40
Switching Angles per quadrant, hence the total number of switching angles
Table 8.12 Positive voltage steps for trinary cascaded hybrid MLI of
81-levels.
Positive DC input Positive DC input
steps manipulation steps manipulation
40 +1+3+9+27 = 40 19 +1-9+27 = 19
39 +3+9+27 = 39 18 -9+27 = 18
38 -1+3+9+27 = 38 17 -1-9+27 = 17
37 +1+9+27 = 37 16 +1-3-9+27 = 16
36 +9+27 = 36 15 -3-9+27 = 15
35 -1+9+27 = 35 14 -1-3-9+27 = 14
34 +1-3+9+27 = 34 13 +1+3+9 = 13
33 -3+9+27 = 33 12 +3+9 = 12
32 -1-3+9+27 = 32 11 -1+3+9 = 11
31 +1+3+27 = 31 10 +1+9 = 10
30 +3+27 = 30 9 +9
29 -1+3+27 = 29 8 -1+9 = 8
28 +1+27 = 28 7 +1-3+9 = 7
27 +27 6 -3+9 = 6
26 -1+27 =26 5 -1-3+9 = 5
25 +1-3+27 = 25 4 +1+3 = 4
24 -3+27 = 24 3 +3
23 -1-3+27 = 23 2 -1+3 = 2
22 +1+3-9+27 = 22 1 +1
21 +3-9+27 = 21 0 0
20 -1+3-9+27 = 20
Table 8.13 Negative voltage steps for trinary cascaded hybrid MLI of
81-levels.
Negative DC input Negative DC input
steps manipulation steps manipulation
-40 -1-3-9-27 = -40 -19 -1+9-27 = -19
-39 -3-9-27 = -39 -18 +9-27 = -18
-38 +1-3-9-27 = -38 -17 +1+9-27 = -17
-37 -1-9-27 = -37 -16 -1+3+9-27 = -16
-36 -9-27 = -36 -15 +3+9-27 = -15
-35 +1-9-27 = -35 -14 +1+3+9-27 = -14
-34 -1+3-9-27 = -34 -13 -1-3-9 = -13
-33 +3-9-27 = -33 -12 -3-9 = -12
-32 +1+3-9-27 = -32 -11 +1-3-9 = -11
-31 -1-3-27 = -31 -10 -1-9 = -10
-30 -3-27 = -30 -9 -9
-29 +1-3-27 = -29 -8 +1-9 = -8
-28 -1-27 = -28 -7 -1+3-9 = -7
-27 -27 -6 +3-9 = -6
-26 +1-27 = -26 -5 +1+3-9 = -5
-25 -1+3-27 = -25 -4 -1-3 = -4
-24 +3-27 = -24 -3 -3
-23 +1+3-27 = -23 -2 +1-3 = -2
-22 -1-3+9-27 = -22 -1 -1
-21 -3+9-27 = -21 0 0
-20 +1-3+9-27 = 20
MLI.
Positive 1st H-bridge 2nd H-bridge 3rd H-bridge 4th H-bridge

voltage SW11SW12 SW21SW22 SW31SW32 SW41SW42
steps SW13SW14 SW23SW24 SW33SW34 SW43SW44
40 1001 1001 1001 1001
39 0101 1001 1001 1001
38 0110 1001 1001 1001
37 1001 0101 1001 1001
36 0101 0101 1001 1001
35 0110 0101 1001 1001
34 1001 0110 1001 1001
33 0101 0110 1001 1001
32 0110 0110 1001 1001
31 1001 1001 0101 1001
30 0101 1001 0101 1001
29 0110 1001 0101 1001
28 1001 0101 0101 1001
27 0101 0101 0101 1001
26 0110 0101 0101 1001
25 1001 0110 0101 1001
24 0101 0110 0101 1001
23 0110 0110 0101 1001
22 1001 1001 0110 1001
21 0101 1001 0110 1001
20 0110 1001 0110 1001
(Continued)
MLI. (Continued)
Positive 1st H-bridge 2nd H-bridge 3rd H-bridge 4th H-bridge

19 1001 0101 0110 1001
18 0101 0101 0110 1001
17 0110 0101 0110 1001
16 1001 0110 0110 1001
15 0101 0110 0110 1001
14 0110 0110 0110 1001
13 1001 1001 1001 0101
12 0101 1001 1001 0101
11 0110 1001 1001 0101
10 1001 0101 1001 0101
9 0101 0101 1001 0101
8 0110 0101 1001 0101
7 1001 0110 1001 0101
6 0101 0110 1001 0101
5 0110 0110 1001 0101
4 1001 1001 0101 0101
3 0101 1001 0101 0101
2 0110 1001 0101 0101
1 1001 0101 0101 0101
0 0101 0101 0101 0101
1010 1010 1010 1010
MLI.
Negative 1st H-bridge 2nd H-bridge 3rd H-bridge 4th H-bridge

-40 0110 0110 0110 0110

-39 0101 0110 0110 0110
-38 1001 0110 0110 0110
-37 0110 0101 0110 0110
-36 0101 0101 0110 0110
-35 1001 0101 0110 0110
-34 0110 1001 0110 0110
-33 0101 1001 0110 0110
-32 1001 1001 0110 0110
-31 0110 0110 0101 0110
-30 0101 0110 0101 0110
-29 1001 0110 0101 0110
-28 0110 0101 0101 0110
-27 0101 0101 0101 0110
-26 1001 0101 0101 0110
-25 0110 1001 0101 0110
-24 0101 1001 0101 0110
-23 1001 1001 0101 0110
-22 0110 0110 1001 0110
-21 0101 0110 1001 0110
-20 1001 0110 1001 0110
(Continued)
MLI. (Continued)
Negative 1st H-bridge 2nd H-bridge 3rd H-bridge 4th H-bridge

-19 0110 0101 1001 0110

-18 0101 0101 1001 0110
-17 1001 0101 1001 0110
-16 0110 1001 1001 0110
-15 0101 1001 1001 0110
-14 1001 1001 1001 0110
-13 0110 0110 0110 0101
-12 0101 0110 0110 0101
-11 1001 0110 0110 0101
-10 0110 0101 0110 0101
-9 0101 0101 0110 0101
-8 1001 0101 0110 0101
-7 0110 1001 0110 0101
-6 0101 1001 0110 0101
-5 1001 1001 0110 0101
-4 0110 0110 0101 0101
-3 0101 0110 0101 0101
-2 1001 0110 0101 0101
-1 0110 0101 0101 0101
0 0101 0101 0101 0101
1010 1010 1010 1010
1 2
s 11 s 13
D
D
g
g
m
m
S
S
+
1V
3 4
s 12 s 14
D
g
D
g
m
m
S
S
6 6
s 21 s 23
D
g
D
g
+
m
m
S
+ R LOAD
3V
7 8
s 22 s 24
D
g
D
g
m
m
S
S
9 10
s 31 s 33
D
g
D
g
m
S
S
+
9V
11 12
s 32 s 34
D
g
D
g
m
m
S
S
13 14
s 41 s 43
D
D
g
g
m
m
S
S
27V
16 16
s 42 s 44
D
D
g
g
m
m
S
Figure 8.34 Circuit diagram of 81-level TCHMLI.

Table 8.16 Multi-level inverter topologies comparison.

H-Bridges 1 2 3 4 5
Switches Utilized 4 8 12 16 20
Topologies of multi-level inverter
Symmetric 3 5 7 9 11
Asymmetric - Binary 3 7 15 31 63
Asymmetric - Quasi 3 7 19 55 81
Asymmetric - Trinary 3 9 27 81 243
is 160 per cycle for the AC output of the 81-level Trinary Cascaded Hybrid
MLI. The switching angles are produced for the four SAA methods. The
generated angles are converted into binary equivalence by taking into con-
sideration a resolution of 28 bits. The resolution of 28 bits can generate 256
bits for one cycle of the 81-level TCHMLI AC output. The resolution of 28
bits for the SAA uses a scaling value of 1.40625 to convert the 360-degree
angles into binary equivalence. The binary equivalent values of the first and
third quadrants are considered for the ON and OFF events of the 40 Digital
Switching Functions in the positive cycle of the 81-level TCHMLI. Also, the
binary equivalent values of the second and fourth quadrants are utilized for
the ON and OFF events of the 40 Digital Switching Functions in the nega-
tive cycle of the 81-level TCHMLI. Tables 8.17, 8.18, 8.19, and 8.20 depict
the binary equivalence of the 160 switching angles for the 81-level TCHMLI
using EP-SAA, HEP-SAA, FF-SAA, and HH-SAA, respectively. Among the
four SAA methods, the HH-SAA has a common ON period of 128 units for
all the 40 Digital Switching Functions of the 81-level TCHMLI.

Trinary Cascaded Hybrid MLI
Function in Digital form. The 81-levels of MLI output require 16 signals
of switching functions that include 40 signals that are utilized for the pos-
itive half as shown in Figure 8.35 and 40 signals for the negative half of
the waveform as shown in Figure 8.36. The switching functions produced
in the positive half and negative half should be complementary. For the
validation of the HDL code for the 81-level switching function generation,
the code is developed using the conditional block in the behavioral model.
Table 8.17 160 switching angles for EP-SAA-81-level trinary cascaded hybrid MLI.
2.22 1 91.11 64 182.22 129 271.11 192
4.44 3 93.33 66 184.44 131 273.33 194
6.66 4 95.55 67 186.66 132 275.55 195
8.88 6 97.77 69 188.88 134 277.77 197
11.11 7 100 71 191.11 135 280 199
13.33 9 102.22 72 193.33 137 282.22 200
15.55 11 104.44 74 195.55 139 284.44 202
17.77 12 106.66 75 197.77 140 286.66 203
20 14 108.88 77 200 142 288.88 205
22.22 15 111.11 79 202.22 143 291.11 207
24.44 17 113.33 80 204.44 145 293.33 208
(Continued)
Table 8.17 160 switching angles for EP-SAA-81-level trinary cascaded hybrid MLI. (Continued)
26.66 18 115.55 82 206.66 146 295.55 210
28.88 20 117.77 83 208.88 148 297.77 211
31.11 22 120 85 211.11 150 300 213
33.33 23 122.22 86 213.33 151 302.22 214
35.55 25 124.44 88 215.55 153 304.44 216
37.77 26 126.66 90 217.77 154 306.66 218
40 28 128.88 91 220 156 308.88 219
42.22 30 131.11 93 222.22 158 311.11 221
44.44 31 133.33 94 224.44 159 313.33 222
46.66 33 135.55 96 226.66 161 315.55 224
48.88 34 137.77 97 228.88 162 317.77 225
(Continued)
51.11 36 140 99 231.11 164 320 227
53.33 37 142.22 101 233.33 165 322.22 229
55.55 39 144.44 102 235.55 167 324.44 230
57.77 41 146.66 104 237.77 169 326.66 232
60 42 148.88 105 240 170 328.88 233
62.22 44 151.11 107 242.22 172 331.11 235
64.44 45 153.33 109 244.44 173 333.33 237
66.66 47 155.55 110 246.66 175 335.55 238
68.88 48 157.77 112 248.88 176 337.77 240
71.11 50 160 113 251.11 178 340 241
73.33 52 162.22 115 253.33 180 342.22 243
(Continued)
75.55 53 164.44 116 255.55 181 344.44 244
77.77 55 166.66 118 257.77 183 346.66 246
80 56 168.88 120 260 184 348.88 248
82.22 58 171.11 121 262.22 186 351.11 249
84.44 60 173.33 123 264.44 188 353.33 251
86.66 61 175.55 124 266.66 189 355.55 252
88.88 63 177.77 126 268.88 191 357.77 254
Table 8.18 160 switching angles for HEP-SAA-81-level trinary cascaded hybrid MLI.
2.19 1 92.19 65 182.19 129 272.19 193
4.39 3 94.39 67 184.39 131 274.39 195
6.58 4 96.58 68 186.58 132 276.58 196
8.78 6 98.78 70 188.78 134 278.78 198
10.97 7 100.97 71 190.97 135 280.97 199
13.17 9 103.17 73 193.17 137 283.17 201
15.36 10 105.36 74 195.36 138 285.36 202
17.56 12 107.56 76 197.56 140 287.56 204
19.75 14 109.75 78 199.75 142 289.75 206
21.95 15 111.95 79 201.95 143 291.95 207
24.14 17 114.14 81 204.14 145 294.14 209
(Continued)
Table 8.18 160 switching angles for HEP-SAA-81-level trinary cascaded hybrid MLI. (Continued)
26.34 18 116.34 82 206.34 146 296.34 210
28.53 20 118.53 84 208.53 148 298.53 212
30.73 21 120.73 85 210.73 149 300.73 213
32.92 23 122.92 87 212.92 151 302.92 215
35.12 24 125.12 88 215.12 152 305.12 216
37.31 26 127.31 90 217.31 154 307.31 218
39.51 28 129.51 92 219.51 156 309.51 220
41.70 29 131.70 93 221.70 157 311.70 221
43.90 31 133.90 95 223.90 159 313.90 223
46.09 32 136.09 96 226.09 160 316.09 224
48.29 34 138.29 98 228.29 162 318.29 226
(Continued)
50.48 35 140.48 99 230.48 163 320.48 227
52.68 37 142.68 101 232.68 165 322.68 229
54.87 39 144.87 103 234.87 167 324.87 231
57.07 40 147.07 104 237.07 168 327.073 232
59.26 42 149.26 106 239.26 170 329.26 234
61.46 43 151.46 107 241.46 171 331.46 235
63.65 45 153.65 109 243.65 173 333.65 237
65.85 46 155.85 110 245.85 174 335.85 238
68.04 48 158.04 112 248.04 176 338.04 240
70.24 49 160.24 113 250.24 177 340.24 241
72.43 51 162.43 115 252.43 179 342.43 243
(Continued)
74.63 53 164.63 117 254.63 181 344.63 245
76.82 54 166.82 118 256.82 182 346.82 246
79.02 56 169.02 120 259.02 184 349.02 248
81.21 57 171.21 121 261.21 185 351.21 249
83.41 59 173.41 123 263.41 187 353.41 251
85.60 60 175.60 124 265.60 188 355.60 252
87.80 62 177.80 126 267.80 190 357.80 254
Table 8.19 160 switching angles for FF-SAA-81-level trinary cascaded hybrid MLI.
0.35 1 139.53 110 180.35 153 269.82 262
1.07 2 142.87 112 181.07 154 272.64 264
1.79 3 145.18 114 181.79 155 274.59 266
2.50 4 147.07 115 182.50 156 276.19 267
3.22 5 148.71 116 183.22 157 277.58 268
3.95 6 150.20 117 183.95 158 278.83 269
4.67 7 151.56 118 184.67 159 279.98 270
5.40 8 152.82 119 185.40 160 281.05 271
6.13 9 154.02 120 186.13 161 282.06 272
6.86 10 155.15 121 186.86 162 283.02 273
7.60 11 156.24 122 187.60 163 283.93 274
(Continued)
Table 8.19 160 switching angles for FF-SAA-81-level trinary cascaded hybrid MLI. (Continued)
8.35 12 157.28 123 188.35 164 284.81 275
9.10 13 158.28 124 189.10 165 285.66 276
9.86 14 159.25 125 189.86 166 286.48 277
10.62 15 160.19 126 190.62 167 287.27 278
11.39 16 161.11 127 191.39 168 288.05 279
12.18 17 162.01 128 192.18 169 288.80 280
12.97 18 162.88 129 192.97 170 289.54 281
13.77 19 163.74 130 193.77 171 290.27 282
14.58 20 164.58 131 194.58 172 290.98 283
15.41 21 165.41 132 195.41 173 291.68 284
16.25 22 166.22 133 196.25 174 292.36 285
(Continued)
17.11 23 167.02 134 197.11 175 293.04 286
17.98 24 167.81 135 197.98 176 293.71 287
18.88 25 168.60 136 198.88 177 294.37 288
19.80 26 169.37 137 199.80 178 295.02 289
20.74 27 170.13 138 200.74 179 295.67 290
21.71 28 170.89 139 201.71 180 296.31 291
22.71 29 171.64 140 202.71 181 296.94 292
23.75 30 172.39 141 203.75 182 297.57 262
24.84 31 173.13 142 204.84 183 298.19 293
25.97 32 173.86 143 205.97 184 298.81 294
27.17 33 174.59 144 207.17 185 299.43 295
(Continued)
28.43 34 175.32 145 208.43 186 300.05 296
29.79 35 176.04 146 209.79 187 300.66 297
31.28 36 176.77 147 211.28 188 301.27 298
32.92 37 177.49 148 212.92 189 301.88 299
34.81 38 178.20 149 214.81 190 302.48 300
37.12 40 178.92 150 217.12 192 303.09 301
40.46 42 179.64 151 220.46 194 303.69 302
Table 8.20 160 switching angles for HH-SAA-81-level trinary cascaded hybrid MLI.
0.72 1 99.07 70 180.72 129 279.07 198
2.15 2 105.74 75 182.15 130 285.74 203
3.58 3 110.36 78 183.58 131 290.36 206
5.02 4 114.15 81 185.02 132 294.15 209
6.46 5 117.44 83 186.46 133 297.44 211
7.90 6 120.40 85 187.90 134 300.40 213
9.35 7 123.12 87 189.35 135 303.12 215
10.81 8 125.66 89 190.81 136 305.66 217
12.27 9 128.05 91 192.27 137 308.05 219
13.74 10 130.31 92 193.74 138 310.31 220
15.22 11 132.48 94 195.22 139 312.48 222
(Continued)
Table 8.20 160 switching angles for HH-SAA-81-level trinary cascaded hybrid MLI. (Continued)
16.71 12 134.56 95 196.71 140 314.56 223
18.21 13 136.57 97 198.21 141 316.57 225
19.72 15 138.51 98 199.72 143 318.51 226
21.25 16 140.39 99 201.25 144 320.39 227
22.80 17 142.23 101 202.80 145 322.23 229
24.36 18 144.02 102 204.36 146 324.02 230
25.94 19 145.77 103 205.94 147 325.77 231
27.55 20 147.49 104 207.55 148 327.49 232
29.18 21 149.17 106 209.18 149 329.17 234
30.83 22 150.82 107 210.83 150 330.82 235
32.51 24 152.45 108 212.51 152 332.45 236
(Continued)
34.23 25 154.06 109 214.23 153 334.06 237
35.98 26 155.64 110 215.98 154 335.64 238
37.77 27 157.20 111 217.77 155 337.20 239
39.61 29 158.75 112 219.61 157 338.75 240
41.49 30 160.28 113 221.49 158 340.28 241
43.43 31 161.79 115 223.43 159 341.79 243
45.44 33 163.29 116 225.44 161 343.29 244
47.52 34 164.78 117 227.52 162 344.78 245
49.69 36 166.26 118 229.69 164 346.26 246
51.95 37 167.73 119 231.95 165 347.73 247
54.34 39 169.19 120 234.34 167 349.19 248
(Continued)
56.88 41 170.65 121 236.88 169 350.65 249
59.60 43 172.10 122 239.60 171 352.10 250
62.56 45 173.54 123 242.56 173 353.54 251
65.85 47 174.98 124 245.85 175 354.98 252
69.64 50 176.42 125 249.64 178 356.42 253
74.26 53 177.85 126 254.26 181 357.85 254
80.93 58 179.28 127 260.93 186 359.28 255
Figure 8.35 Digital switching functions waveforms in positive cycle of SAA based
81-level trinary cascaded hybrid MLI.
Figure 8.36 Digital switching functions waveforms in negative cycle of SAA based
81-level trinary cascaded hybrid MLI.
8.6.3 Generation of DPWM for 81-Level Trinary Cascaded

Hybrid MLI
By utilizing logic gates such as XOR and OR, the required switching patterns
are designed for the 16 switches of the 81-level Trinary Cascaded Hybrid
MLI circuit as depicted in Figure 8.37. Functionally, the positive and negative
edges of the switching patterns are derived using the XOR gate. Similarly, the
levels of the switching patterns are derived using the OR gate. The 81-level
TCHMLI requires 16 Digital Switching Patterns for the generation of the
required AC outputs. The generated HDL code based Digital PWM signals
control the 16-switches of the 81-level Trinary Cascaded Hybrid MLI.
Figure 8.37 Digital PWM waveforms for SAA based 81-level trinary cascaded hybrid MLI.
8.6.4 Flow Diagram of 81-Level Trinary Cascaded Hybrid MLI

The reduction in the THD% of the inverter AC output is due to the high
precision in the HH-SAA. The procedure for HH-SAA using the Trinary
Cascaded Hybrid MLI is presented in Figure 8.38. The initial step is to
select the voltage levels of the inverter as “n”. The event of switching is eval-
uated for all quadrants using the value of “n”. If n = 81, then 160 events of
switching are defined for the inverter with each quadrant consisting of 40
events of switching. The event representation for the 1st quadrant is given
by α1, α2, α3, α4, α5, α6, α7, α8, ...... α38, α39, and α40. The preceding 3 quadrants
are manipulated based on trigonometric formulations and its equivalence
in 2n bits are considered for the Trinary Cascaded Hybrid MLI circuit.
The generated bit equivalents are fed as input to the developed VHDL
code for the Digital Switching Function block to give Digital PWM wave-
forms. For 81-level Trinary Cascaded Hybrid MLI, the array of 40 Digital
PWM waveforms for the positive half are given by s[39:0] and another
array of 40 Digital PWM waveforms for the negative half are given by
sb[39:0]. By utilizing these arrays of Digital PWM signals, the Digital
Switch Patterns are generated by the developed VHDL for the 16 switches
of the proposed 81-level Trinary Cascaded Hybrid MLI circuit. The system
generator-based Simulink model is depicted in Figure 8.39 that indicates
the Digital Switching and Patterns blocks.
8.6.5 5 Roles of Design Resolution in Trinary Cascaded Hybrid

MLI
As the resolution of the design increases, the accuracy of the switching events
of the SAA increases. If low resolution is used in the SAA design, there may
Start
Select level (m)
Calculate α1, α2, α3, α4, α5, α6,

α7,........(αm-1/2) in each quadrant
Convert α1, α2, α3, α4, α5,........α40

in each quadrant to 28/211/212 bits
DSFV Block (VHDL code)

s[39”0] for positive levels &
sb[39:0] for negative levels
XOR AND
DSP Block
16 PWM SIGNALS
Figure 8.38 Flow diagram of SAA based 81-level trinary cascaded hybrid MLI.
s11 Out s11

Gateway Out1
s13 Out s13
Gateway Out2
s12 Out s12
SYSTEM Gateway Out3

GENERATOR s14 Out s14
sb Gateway Out4
s21 Out s21
Gateway Out5
s23 Out s23
Gateway Out6
DSF DSPs22 Out s22
S1-LEVEL
Gateway Out7 TCHMLI WITH
AC OUTPUT
s24 Out s24 RL LOAD
Gateway Out8
s31 Out s31
Gateway Out9
CLOCK s33 Out s33
Gateway Out10
s32 Out s32
Gateway Out11
s34 Out s34
s Gateway Out12
s41 Out s41
Gateway Out13
s43 Out s42
Gateway Out14
s42 Out s43
Gateway Out15
s44 0ut s44
Gateway Out16
Figure 8.39 System generator model of SAA-81-level trinary cascaded hybrid MLI.
exist crossover of bits equivalent values for the events in the developed HDL
code. In this chapter, the resolution of 2n where n ranges from 8-12 are used
for validation of the proposed SAA for the parametric analysis.

MLI
The simulation result for the proposed EP-SAA of 81-level Trinary Cascaded
Hybrid MLI is given in Figure 8.40. The AC outputs along with manipulated
THD% for EP-SAA are given in Figure 8.41 and Figure 8.42. The proposed
HEP-SAA based Switch patterns is given in Figure 8.43 to generate the AC
output as given in Figure 8.44 with the corresponding THD% evaluation in
Figure 8.45. The simulation result for the switching pattern generation based
on FF-SAA is given in Figure 8.46, with the AC output in Figure 8.47 and the
calculated THD% in Figure 8.48. The HH-SAA based switching pattern gen-
eration is shown in Figure 8.49 to produce the AC output as depicted in Figure
8.50 with the evaluated THD% as in Figure 8.51 The parametric analysis for
the SAA based MLI for the 9-level, 27-level, and 81-level, are presented in Table
8.21 and indicates that the HH-SAA is advantageous with less percentage in
Figure 8.40 Digital PWM of EP-SAA based 81-level trinary cascaded hybrid MLI.
OUTPUT RESPONSE OF 81-LEVEL EPM-SAM MLI

200
150 S1-LEVEL OUTPUT
100
Amplitude in Volts
50
0
-50
-100
-150
-2000 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time in Seconds
Figure 8.41 AC output for EP-SAA based 81-level trinary cascaded hybrid MLI.
Fundamental (50Hz) = 162.5 , THD= 12.22%

12
10
0
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Figure 8.43 Digital PWM for HEPM-SAA based 81-level trinary cascaded hybrid MLI.

200
150 81-LEVEL OUTPUT
100
Amplitude in Volts
50
0
-50
-100
-150
-2000 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time in Seconds
Figure 8.44 AC output for the HEPM-SAA based 81-level trinary cascaded hybrid MLI.
Fundamental (50Hz) = 163.8, THD= 12.28%

12
10
0
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Figure 8.46 Digital PWM for the FF-SAA based 81-level trinary cascaded hybrid MLI.

200
81-LEVEL OUTPUT
150
100
Amplitude in Volts
50
0
-50
-100
-150
-200
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time in Seconds
Figure 8.47 AC Output for FF-SAA based 81-level trinary cascaded hybrid MLI.

9
8
7
6
5
4
3
2
1
0
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Figure 8.49 Digital PWM for HH-SAA based 81-level trinary cascaded hybrid MLI.

200
81-LEVEL OUTPUT
150
Amplitude in Volts
100
50
-50
-100
-150
-200
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time in Seconds
Figure 8.50 AC output for HH-SAA based 81-level trinary cascaded hybrid MLI.

0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Table 8.21 Parametric analysis of trinary cascaded hybrid MLI at Level 9, 27,
and 81.
Methods EP-SAA HE-SAA FF-SAA HH-SAA
9-LEVEL TRINARY CASCADED HYBRID MLI
THD (%) 20.96 18.21 18.72 10.13
Vpeak 32.53 35.71 47.28 42.79
VRMS 23.02 25.25 33.43 30.25
Vavg 20.71 22.73 30.09 27.24
FF 1.11 1.11 1.11 1.11
CF 1.414 1.414 1.414 1.414
THD (%) 13.53 13.15 15.44 3.67
Vpeak 106.5 109 151.2 127.3
VRMS 75.31 77.07 106.9 90.01
Vavg 67.8 69.39 96.25 81.04
FF 1.11 1.11 1.11 1.11
CF 1.414 1.414 1.414 1.414
THD (%) 12.22 12.28 10.33 1.42
Vpeak 162.5 163.8 224.3 197.6
VRMS 114.90 115.82 158.60 139.72
Vavg 103.45 104.27 142.79 125.79
FF 1.11 1.11 1.11 1.11
CF 1.414 1.414 1.414 1.414
Table 8.22 Parametric evaluation comparison for all levels using SAA in simulation.
28 design resolution 28 design resolution 212 design resolution 212 design resolution
Voltage
Current (I) Voltage (V) Current (I) Voltage (V)
level
“m” THD% Peak RMS THD% Peak RMS THD% Peak RMS THD% Peak RMS
3 28.96 0.0544 0.03851 31.65 5.453 3.856 28.54 0.05496 0.03887 31.13 5.499 3.888
5 15.42 0.1026 0.07257 18.18 10.22 7.226 15.09 0.1034 0.07314 17.64 10.35 7.316
7 10.13 0.1509 0.1067 12.60 15.08 10.66 9.79 0.1525 0.1078 12.25 15.25 10.79
9 7.26 0.2002 0.1415 9.63 20.01 14.15 6.99 0.2018 0.1427 9.37 20.19 14.27
11 6.12 0.2475 0.175 8.33 24.77 17.52 5.36 0.2514 0.1777 7.64 25.15 17.78
13 5.01 0.2958 0.2091 7.04 29.58 20.92 4.21 0.301 0.2128 6.40 30.11 21.29
15 3.57 0.3484 0.2463 5.67 34.82 24.62 3.42 0.3503 0.2477 5.51 35.05 24.78
17 3.52 0.3946 0.279 5.33 39.49 27.92 2.88 0.3998 0.2827 4.87 40.01 28.29
19 3.29 0.4425 0.3129 5.05 44.19 31.25 2.41 0.4496 0.3179 4.33 44.99 31.81
21 3.23 0.4906 0.3469 4.74 49.1 34.72 2.06 0.4991 0.3529 3.90 49.94 35.31
23 2.85 0.5409 0.3825 4.34 54.1 38.25 1.82 0.5487 0.388 3.57 54.9 38.82
25 2.79 0.5872 0.4152 4.07 58.84 41.61 1.60 0.5981 0.4229 3.27 59.84 42.31
27 2.55 0.6363 0.4499 3.72 63.68 45.03 1.4 0.6477 0.458 3.02 64.8 45.82
29 2.64 0.6857 0.4849 3.77 68.54 48.47 1.36 0.6973 0.4931 2.87 69.77 49.34
(Continued)
Table 8.22 Parametric evaluation comparison for all levels using SAA in simulation. (Continued)
Voltage
level
31 2.5 0.7357 0.5202 3.50 73.59 52.04 1.19 0.7473 0.5285 2.66 74.77 52.87
33 2.25 0.7859 0.5558 3.25 78.62 55.59 1.06 0.797 0.5636 2.48 79.74 56.38
35 2.39 0.833 0.589 3.28 83.31 58.91 0.99 0.8469 0.5989 2.35 84.74 59.92
37 2.35 0.8805 0.6226 3.15 88.09 62.29 0.89 0.8966 0.634 2.21 89.7 63.43
39 2.25 0.9326 0.6594 2.98 93.3 65.97 0.82 0.946 0.6689 2.09 94.63 66.91
41 2.5 0.979 0.6922 3.37 97.82 69.17 0.78 0.9957 0.7041 2.00 99.63 70.45
43 1.71 1.03 0.7284 2.51 103.1 72.88 0.71 1.045 0.739 1.90 104.6 73.94
45 2.17 1.078 0.762 2.79 107.8 76.25 0.66 1.095 0.774 1.80 109.5 77.44
47 2.16 1.125 0.7957 2.76 112.6 79.62 0.67 1.145 0.8094 1.76 114.5 80.99
49 1.98 1.177 0.8323 2.58 117.7 83.24 0.61 1.195 0.8446 1.67 119.5 84.51
51 2.18 1.225 0.8659 2.76 122.5 86.59 0.56 1.244 0.8796 1.60 124.5 88
53 2.16 1.273 0.8999 2.70 127.3 90.04 0.55 1.294 0.9149 1.55 129.5 91.54
55 1.91 1.321 0.9344 2.44 132.2 93.5 0.51 1.343 0.9498 1.48 134.4 95.03
57 2.13 1.37 0.969 2.60 137.1 96.97 0.47 1.393 0.987 1.42 139.3 98.52
(Continued)
Table 8.22 Parametric evaluation comparison for all levels using SAA in simulation. (Continued)
Voltage
level
59 2.09 1.421 1.005 2.58 142.1 100.5 0.47 1.442 1.02 1.39 144.3 102
61 1.23 1.479 1.046 1.75 148 104.6 0.44 1.492 1.055 1.33 149.2 105.5
63 1.03 1.528 1.08 1.70 152.8 108.1 0.42 1.541 1.089 1.29 154.1 109
65 1.14 1.58 1.117 1.74 158 111.7 0.45 1.591 1.125 1.27 159.2 112.5
67 1.12 1.629 1.152 1.69 162.9 115.2 0.41 1.641 1.16 1.22 164.2 116.1
69 1.04 1.677 1.186 1.68 167.9 118.7 0.38 1.69 1.195 1.18 169.1 119.1
71 1.05 1.727 1.221 1.66 172.8 122.2 0.39 1.74 1.23 1.16 174.1 123.1
73 1.05 1.775 1.255 1.60 177.4 125.5 0.36 1.789 1.265 1.12 179 126.6
75 1.03 1.825 1.29 1.55 182.6 129.1 0.35 1.838 1.3 1.08 183.9 130.1
77 1.02 1.876 1.327 1.52 187.6 132.7 0.36 1.888 1.335 1.07 188.9 133.5
79 1.01 1.922 1.359 1.51 192.3 135.9 0.35 1.936 1.369 1.03 193.7 137
81 0.92 1.974 1.396 1.41 197.5 139.6 0.32 1.986 1.404 1.00 198.7 140.5
THD and performance is satisfied with VRMS, Vpeak, CF, and FF for all the three
levels of the SAA based TCHMLI. THD% for the 81-level TCHMLI using the
HH-SAA exhibits 1.42% in simulation using the MATLAB SIMULINK System
Generator. The MLI voltage levels from 3 to 81 with Resistive-Inductance load
are evaluated for the HH-SAA in simulation, as indicated in Table 8.22. Figure
8.52 presents the relationship between the THD% and the voltage levels “n”
and design resolution. The linear decrement of the THD% concerning the
design resolution and voltage levels “n” is evident from the graph. Also, Figure
8.53 and Figure 8.54 depict the increment of RMS voltage and Peak voltage for
the voltage levels “n” for 212 bits resolution. For all the design resolutions, the
%THD is low for HH-SAA-Trinary Cascaded Hybrid MLI circuitry that leads
to the experimental verification of HH-SAA.
THD Vs NUMBER OF LEVELS OF MLI

35
30
% THD VALUE
25
20
THD %
15
10
0
0 10 20 30 40 50 60 70 80
LEVELS
Figure 8.52 Plot of THD% for HH-SAA with 212 design resolution.
Vpeak Vs NUMBER OF LEVELS OF MLI

250
Vpeak Value
200
Vpeak in Volts
150
100
50
0
0 10 20 30 40 50 60 70 80
LEVELS
Figure 8.53 Plot of Vpeak for HH-SAA with 212 design resolution.
Vms Vs NUMBER OF LEVELS OF MILI

160
Vrms Value
140
120
Vms in Volts
100
80
60
40
20
0
0 10 20 30 40 50 60 70 80
LEVELS
Figure 8.54 Plot of VRMS for HH-SAA with 212 design resolution.
Figure 8.55 Circuit board of Xilinx FPGA (3A DSP).

8.7 FPGA Experimental Validation with Specification

The FPGA is a reprogrammable device that evaluates in parallel with
enhanced reliability and is utilized for the generation of a Digital PWM
signal. The Xilinx Spartan 3 A DSP FPGA is the perfect match for indus-
trial power applications, as shown in Figure 8.55. The selected Xilinx
Spartan 3A DSP kit can produce 75 Digital PWM waveforms concur-
rently. The validation of VHDL code in real-time implementation with the
Xilinx Spartan 3A DSP device involves the use of two signals, namely OE
to detach the pins at the output by considering a logic “ZERO” and DIR
to indicate the flow from either A to B (Logic “ONE”) or B to A (Logic
“ZERO”). The activation of the terminal pins in the Spartan 3A DSP device
can be achieved based on the OE and DIR values.
The feature of a Spartan 3A DSP family device has 8 DIP switches, 16
LED outputs, a Reset button, JTAG programmer port, PROM, Crystal
oscillator, Analog to Digital Controller (AD7266), 16:2 LCD, and an RS232
port for serial communication.
8.8 Hardware Results and Discussion

The real-time implementation of the HH-SAA-81-level-Trinary Cascaded
Hybrid MLI is validated using the FPGA. It is specifically designed to
interface the power converters and drives and generate the PWM sig-
nals. This FPGA can generate a maximum of 75 PWM signals at a time.
The Fluke Power Analyser (FPA) is used for measuring the electrical
parameters of VRMS, Vpeak, THD %, and switching frequency in real-time.
The Digital PWM waveforms for the 16 MOSFETs of the Trinary Cascaded
Hybrid MLI in 81-levels is shown in Figures 8.56 to 8.71. The Fluke Power
Analyser output response for the HH-SAA fed 81-level Trinary Cascaded
Hybrid MLI circuit is recorded for 28 design resolutions as shown in Figure
8.72 with the parametric data values of peak voltage, RMS voltage, and
Crest Factor using the Fluke Power Analyser is given in Figure 8.73 and the
%THD for the 81-level Trinary Cascaded Hybrid MLI using 28 design res-
olutions is depicted in Figure 8.74. Figure 8.75 presents the HH-SAA fed
81-level TCHMLI for 211 design resolutions with the parametric analysis
in Figure 8.76 and %THD in Figure 8.77. Similarly, the resolution of 212
for the HH-SAA fed 81-level TCHMLI is given in Figure 8.78 along with
parametric evaluation in Figure 8.79 and the %THD for the 212 resolu-
tion is presented in Figure 8.80. The Synthesized Resistor Transistor Logic
view for the proposed HH-SAA is shown in Figure 8.81 using the Xilinx
ISE Tool. The real-time implementation of the HH-SAA algorithm for the
81-level Trinary Cascaded Hybrid MLI is depicted in Figure 8.82. From
Table 8.23, the %THD for the HH-SAA is satisfactory with 0.3% for 211
design resolution. Table 8.24 proves the usefulness of the real-time imple-
mentation using the Xilinx Spartan 6 device.
8.9 Conclusion
The proposed fusion non-carrier SAA approach for 81-level TCHMLI is
successfully implemented using the FPGA device. The Half Height-SAA
has proven to be satisfying with the simulation process and thus proceeded
with the hardware implementation using the FPGA. The design resolutions
for the HH-SAA, namely 28, 211, and 212, were evaluated and the %THD for
the 211 design resolution was as low as 0.3%. The developed VHDL code for
the Digital Switching Pattern generation was found to be satisfactory to the
performance of the N-level TCHMLI.
T
RIGOL STOP f 1 1.76V
E
E
T
Freq(1) = 13.89kHz
CH1 1.00V Time 200.0us T 72.00us
Figure 8.56 Digital PWM signal of SW11 for 81-level TCHMLI.
RIGOL STOP E
T E ƒ 1 1.76V
T
Freq(1) = 13.16kHz
CH1 1.00V Time 200.0us T 72.00us

RIGOL STOP E T
ƒ 1 1.76V
E
Freq(1) = 7.042kHz
CH1 1.00V Time 200.0us T 72.00us
RIGOL
T
STOP E ƒ 1 1.76V
E
Freq(1) = 7.042kHz T
CH1 1.00V Time 200.0us T 72.00us
RIGOL STOP E
T
ƒ 1 1.76V
E
Freq(1) = 4.032kHz
CH1 1.00V Time 500.0us T 72.00us

RIGOL STOP E T
ƒ 1 1.76V
E
Freq(1) = 4.000kHz
CH1 1.00V Time 500.0us T 72.00us
RIGOL STOP E T
ƒ 1 1.76V
E
Freq(1) = 4.000kHz
CH1 1.00V Time 500.0us T 72.00us
RIGOL STOP
T
ƒ 1.76V
E
E 1
T
Freq(1) = 4.545kHz
CH1 1.00V Time 500.0us T 72.00us

RIGOL STOP E
T
ƒ 1 1.76V
E
Freq(1) = 1.786kHz
CH1 1.00V Time 1.000ms T 72.00us
RIGOL STOP
T
ƒ 1 1.76V
E
E
T
Freq(1) = 1.786kHz
CH1 1.00V Time 1.000ms T 72.00us
RIGOL STOP E
T
ƒ 1 0.00uV
E
Freq(1) = 1.786kHz
CH1 1.00V Time 1.000ms T 0.0000s

RIGOL STOP E T
ƒ 0.00uV
E
1
T
Freq(1) = 1.786kHz
CH1 1.00V Time 1.000ms T 0.0000s
RIGOL STOP E T
ƒ 0.00uV
E
1
Freq(1) = 196.9Hz
CH1 1.00V Time 1.000ms T 0.0000s
RIGOL STOP E T
ƒ 1 0.00uV
E
Freq(1) = 196.9Hz
CH1 1.00V Time 1.000ms T 0.0000s

RIGOL STOP E T E
ƒ 1 0.00uV
Freq(1) = 196.9Hz
CH1 1.00V Time 1.000ms T 0.0000s
RIGOL STOP E
T E
ƒ 1 0.00uV
T
Freq(1) = 196.9Hz
CH1 1.00V Time 1.000ms T 0.0000s
1 1
28.2 v 1 A
50.59 Hz 0:00:46 -2x
01/19/15 16:26:27 230V 50Hz 1Ø EN50160

V A N CURSOR ZOOM HOLD
L 1 1.2 1.3 BACK ON OFF CURSOR RUN
Figure 8.72 AC output of 81-level trinary cascaded hybrid MLI with 28 design resolution.
Volts/Amps/Hertz
0:00:11
L1 N
Vrms 28.2 10.8
Vpk 40.3 16.2
CF 1.13 1.50
Hz 50.59
L1 N
Arms 1 0.3
Apk 1 0.4
CF OL OL
01/19//15 16:24:58 230V 50Hz 10 EN50 160
VOLTAGE TREND HOLD
RUN
Figure 8.73 Parametric evaluation of 81-level trinary cascaded hybrid MLI with 28 design
resolution.
Harmonics 1 THD 1.4 % f

0:00:07
100%
50%
T T T T T T T T T T T T T T T
THD DC 1 5 9 13 17 21 25 29 33 37 41 45 49
01/19/15 16:27:48 230V 50Hz 10 EN50160
L1 L.2 L.0 I_HARM. HOLD
V A W N A1..1.. METER ON OFF RUN
Figure 8.74 THD% of 81-level trinary cascaded hybrid MLI with 28 design resolution.
1 1
28.3 v 1 A
50.18 Hz 0:00:17 -2x
01/21/15 15:09:52 230V 50Hz 10 EN50160

L 1 1.2 1.3 BACK OFF CURSOR RUN
ON
Figure 8.75 AC output of 81-level trinary cascaded hybrid MLI with 211 design
resolution.
Volts/Amps/Hertz
0:00:22
L1 N
Vrms 28.3 17.2
Vpk 40.2 26.3
CF 1.42 1.53
Hz 50.18
L 1 N
Arms 1 0.3
Apk 1 0.4
CF OL OL
01/21/15 15:08:07 230V 50Hz 10 EN50 160
VOLTAGE TREND HOLD
RUN
Figure 8.76 Parametric evaluation of 81-level trinary cascaded hybrid MLI with 211
design resolution.

0:00:25
100%
50%
T T T
THD DC 1 5 9 13 17 21 25 29 33 37 41 45 49
01/21/15 15:10:57 230V 50Hz 10 EN50160
L1 1.2 1.0 I_HARM. HOLD
V A W
N A1..1.. METER ON OFF RUN
1 1
28.7 V 0 A
50.20 Hz 0:05:51 -2x
01/20/15 16:19:06 230V 50Hz 10 EN50160

L 1 1.2 1.3 BACK OFF CURSOR RUN
ON
Figure 8.78 AC output of 81-level trinary cascaded hybrid MLI with 212 design resolution.
Volts/Amps/Hertz
0:00:11
L1 N
Vrms 28.7 17.0
Vpk 40.8 25.5
CF 1.42 1.50
Hz 50.18
L 1 N
Arms 0 0.3
Apk 1 0.4
CF OL OL
01/20/15 16:21:01 230V 50Hz 10 EN50 160
VOLTAGE TREND HOLD
RUN
Figure 8.79 Parametric evaluation of 81-level trinary cascaded hybrid MLI with 212
design resolution.

0:00:15
100%
50%
T T T
THD DC 1 5 9 13 17 21 25 29 33 37 41 45 49
01/20/15 16:20:13 230V 50Hz 10 EN50160
L1 1.2 1.0 I_HARM. HOLD
V A W
N A1..1.. METER ON OFF RUN
hhm 12bits_81level
dk diir
diir6
diir8
o-o
o-o-6
o-o-8
s 11
s 12
s 13
s 14
s 21
s 22
s 23
s 24
s 31
s 32
s 33
s 34
s 41
s 42
s 43
s 44
hhm 12bits_81_level
Figure 8.81 Resistor transistor logic view of 81-level trinary cascaded hybrid MLI.
FPA DSO
IIND H-BRIDGE
FPGA
IST H-BRIDGE
Figure 8.82 Real-time implementation of 81-level trinary cascaded hybrid MLI.

Table 8.23 Performance comparison of 81-level trinary

cascaded hybrid MLI.
Design resolution 28 211 212
%THD 1.4 0.3 0.4
Vpeak 40.3 40.2 40.8
VRMS 28.2 28.3 28.7
Crest Factor 1.43 1.42 1.42
Table 8.24 FPGA area utilization of HH-SAA for 81-level trinary

cascaded hybrid MLI.
Xilinx Spartan device
Component
parameters 3E 3A DSP 6
Sliced FF 2.5% 0.14% 0.43%
Occupied Slices 68.44% 3.5% 4.97%
4 INPUT LUTs 48.13% 2.51% 3.50%
Total4 INPUT LUTs 61.83% 3.15% 22.77%
Bonded IOBs 17.59% 4.43% 8.5%
BUFGMUXs 4.17% 4.17% 6.25%
Average Fanout 3.96 4.17% 3.19
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9
An Inspection on Multilevel Inverters
Based on Sustainable Applications
L. Vijayaraja1*, R. Dhanasekar1 and S. Ganesh Kumar2
1
DEEE, Sri Sairam Institute of Technology, Tamil Nadu, India
2
DEEE, CEG Campus, Anna University, Tamil Nadu, India
Abstract
The design of multilevel inverters finds an optimum space in the photovoltaic
power generation system, grid integrated renewable power networks, power
trains, fuel cell power generation, motor drive systems, etc. This attracts research-
ers to develop multilevel inverters with low cost and compact size, but deigning
a low cost multilevel inverter with a reduced size is a challenging work. In this
chapter, a detailed study of various multilevel inverters is carried out in terms
of utilization of multilevel inverters in sustainable energy applications, types of
late multilevel inverter, a brief study of recent designs of multilevel inverters with
respect to harmonic presence in the output voltage waveform. An examination on
recent symmetric and asymmetric voltage source inverters is analysed in terms of
number of voltage levels the design can generate.
Keywords: Asymmetric, multilevel inverter, symmetric inverter, sustainable

development
9.1 Introduction
An electrical apparatus which converts DC supply into AC supply is called
as inverter. The basic inverter finds place in low power operations. Later,
other basic topologies like neutral clamped inverters, flying capacitor
inverters, diode-clamped inverters, and cascaded H-bridge inverters were
developed in order to meet high power applications. The restrictions in
using these types of inverters are high harmonic distortions, dv/dt ratio,
293
and electromagnetic interference. Therefore, the performance of the basic

inverters is affected. These topologies use more switches and diodes for
clamping the voltage and voltage sources. Hence the design becomes bulky
and increases the cost. So, to reduce the cost and size of the inverter, var-
ious topologies of multilevel inverters were designed that can be used in
medium and high power applications [1–18].
Multilevel inverters are the inverters which produce a greater number of
voltage levels and the peak value of the inverter output is based on the DC
sources connected to it. The multilevel inverter can be broadly classified into
two types: symmetric and asymmetric. A symmetric multilevel inverters are
said to be connected with equal magnitude of DC voltage sources and an
asymmetric multilevel inverter is said to be connected with an unequal mag-
nitude of DC voltage sources as input supply. The multilevel output voltage
can be achieved by connecting the DC voltage sources in series or parallel
combinations of switches with or without using a half bridge in the design
topology [3, 4]. Recently, multilevel inverter designs are not using transform-
ers to develop too many levels of output voltage [5]. Considering the above
facts, an inspection is made on a multilevel inverter in order to describe the
structures and suitability of various MLI designs in sustainable energy appli-
cations. The work of this chapter is categorised as follows:
Section 9.2 provides a detailed investigation of various topologies of
MLI designs that are used for sustainable applications such as renewable
energy systems, smart grids, electric vehicle systems, etc.
Section 9.3 gives an understanding of classical multilevel inverters with
design work.
Section 9.4 elaborates the recent multilevel inverter topologies using
symmetric voltage sources. Also, a comparison is made on the recent sym-
metric MLI in terms of their performances.
In Section 9.5, recent designs of asymmetric voltage sources MLI’s are
presented. A comparative study will be performed on the recent asymmet-
ric MLI in terms of their performances.
Section 9.6 briefs the various multilevel inverter topologies design,
in-terms of number of voltage levels generated and number of components
involved to design the topology.
9.2 Multilevel Inverters in Sustainable Applications

The design of multilevel inverters finds the best place in various applica-
tions such as renewable energy systems, smart grid, electric vehicle sys-
tems, HVDC, and FACTs, as shown in Figure 9.1 and Table 9.1.
An Inspection on MLIs 295
Heat heat Motor drive

[12, 17]
Hydrogen in Oxygen in PV systems
Fuel cells
[4, 23, 27] [1, 2, 7–10, 13, 14]
Water out
iodite Chloride
MLI in
FUEL CELL sustainable
development
Power system
Electric Vehicles applications
[24–26, 28]
[3, 5, 6, 19–22]
Grid connected
Inverter system
High [11, 15, 16, 18, 29]
Battery Voltage Bi- Electric
Charger Battery directional Motor
Converter
DC-DC Ancilary Torque

Converter Leads to
Drive
Wheels
Figure 9.1 MLI’s place in sustainable energy applications.
In [1], a power equalization control strategy for a three-phase CDB-

CHB PV grid-connected inverter based on a one-input-four-outputs LLC
converter is mainly studied aiming at the problem of module active power
unequalization caused by fault redundancy condition and a zero-sequence
voltage compensation strategy was proposed.
In [2], a trinary CHB multilevel inverter-based grid-connected solar
power transfer system using modified second-order generalized integral
control is proposed to ensure balanced, sinusoidal, and unity power factor
grid currents, thus maintaining the power quality of the grid. In [3], a
system operating a synchronous machine in a vehicle drive train uses an
innovative hybrid multilevel inverter to deliver a separate DC voltage while
a three-phase system is provided and those voltages are independently
delivered by shared battery cells.
In [4], a converter topology as a power interface and a multilevel inverter
topology for various levels of operation for a PEMFC (Proton Exchange
Membrane Fuel Cell) is discussed. The hybrid cascaded multilevel invert-
ers providing five, seven, and fifteen levels with reduced switch count were
experimentally tested and simulated in MATLAB Simulink.
In [5], a multilevel inverter with a reduced number of switches produc-
ing a staircase output waveform having 13 levels was proposed. The pro-
posed model provides THD as low as 5.35%, which could be used in motor
Table 9.1 MLI’s place in sustainable energy applications.

Reference Number of output
paper voltage level at
number load Applications
[1] 6 Large-Scale PV Power Plants
[2] 9 Grid-Connected Solar Power
Transfer System
[3] 9 Synchronous motor vehicle drive
train
[4] 5, 7, 15 Fuel cell energy conversion
[5] 13 Hybrid electric vehicles
[6] 5 Hybrid electric vehicle
[7] 7 Photovoltaic applications
[8] 5 Grid connected PV system
[9] 17 Renewable energy applications
[10] 11 Motor drives applications
[11] 9 Grid connected system
[12] 25 Grid connected renewable energy
system
[13] 5 Pumping and ventilation system
[14] 2, 7 Fuel Cell Based Electrical Vehicles
[15] 7 HVDC Transmission System
[16] 9 Application to FACTS
[17] 7 High power STATCOM
applications
[18] 2, 3 Fuel cell system
drives. In [6], a multilevel inverter topology with pulse width modulation

for high power traction applications is modelled and analyzed.
In [7], two different converter topologies for a basic new switched
capacitor diode converter with a reduced number of power electronics
components suitable for grid connected photovoltaic applications were
proposed. In addition to that, a new DC offset nearest level modulation
technique was proposed to provide low THD with high RMS output. Its
performance was implemented using an FPGA Spartan 3E controller and
tested with a novel switched capacitor-diode multilevel converter. Also, a
laboratory-based prototype model for 7-level and 13-level converters was
developed.
In [8], the modelling and control-loop design method with an inverted
decoupling scheme of a single-phase photovoltaic grid-connected five-
level cascaded H-bridge multilevel inverter is proposed. The proposed
control methods of the cascaded H-bridge multilevel inverter are vali-
dated through the simulation and experimental results of 2-kW prototype
hardware.
In [9], implementation and comparison of 17 level symmetric HCMLI
with an asymmetric MLI is presented. The switched capacitor unit increases
voltage levels to five symmetric schemes and doubles the voltage in asym-
metric schemes with the help of a bidirectional switch. In [10], a study of
an eleven level inverter system with different types of loads is proposed
and the voltage source inverters (VSI) are modelled and simulated using
MATLAB/Simulink. Results show that the proposed scheme is effective to
produce low distortion and possess low switching losses.
In [11], flying capacitor inverters using in grid-connected applications
are investigated. Power density of the inverters is evaluated so that it can
be used as a guideline to realize downsizing and loss reduction of the
inverters. Theoretical computations are performed and based on how it
is clarified, the multilevel inverter can reduce the total volume of flying
capacitors and interconnection inductors compared with the conventional
2-level inverters and it is highly advantageous to realize high power density
inverters. In the study, the calculated maximum power density of the main
circuit portion is 4.97W/cm3 in a 2-level inverter and 25.11W/cm3 in a
multilevel (9-level) inverter.
In [12], a DTC with multilevel inverters is presented. Due to simplicity
of control and intrinsic short circuit protection, DTC is used to control
high power pumps and fans. All of the required blocks including multilevel
inverter, the 24-sector flux sector seeker, and switching table are proposed.
The balancing method for the flying capacitor and a simple model of pump
are given and simulation results in SIMULINK confirm the validity and
performance of the proposed model.
In [13], a novel asymmetric multilevel inverter is proposed which con-
tains a lesser number of switches and can be employed in renewable power
grid applications. The proposed topology consists of 25 output levels with
only 12 switches, thereby reducing gate driver circuitry and optimizing cir-
cuit layout. Asymmetric multilevel inverters are more advantageous than
symmetric multilevel inverters in obtaining a greater number of output
levels. The other advantages of the proposed topology are low voltage stress
and reduced total harmonic distortion (THD). The THD for an inverter
circuit with 12 switches and 50Hz frequency is only 4.98%, which was
modelled and verified in MATLAB/SIMULINK.
In [14], a direct torque control scheme for an asymmetric multilevel
inverter fed induction motor drive for fuel cell based electrical vehicles
is presented. The asymmetric multilevel inverter provides almost sinusoi-
dal voltage with less total harmonics distortion (THD) and less switch-
ing devices resulting in lesser switching losses. Simulations are executed
in MATLAB/Simulink and the proposed DTC control scheme is verified.
In [15], a control process and the functioning of a Modular Multilevel
Converter (MMC) in a high voltage DC transmission system is proposed.
The proposed control process uses a new algorithm to generate gate pulses
of the switching devices for running and shifting the system from one level
to another of operation based on Carrier and Signal (reference) Magnitude
Control Pulse Width Modulation (CSMC-SPWM). Moreover, this control
method generates pulses for the faulty Sub-Modules (SM) to bypass the
supply voltage to unfaulty SMs. By using the CSMC-SPWM technique
in 7-level MMC, a 7-level output AC voltage was confirmed by PSCAD-
EMTDC simulation software.
In [16], a new DC-link capacitor voltage balancing method for CHBMLI
is proposed. This method has a very effective and fast voltage balancing
capability and the proposed algorithm is independent of the number of
modules and voltage distribution and also reduces computational efforts,
therefore it could be applied to any CHBMLI regardless of its number of
cells and levels without considerable modification. The proposed method
is applied to a four-cell CHBMLI, utilized in STATCOM applications in the
PSCAD/EMTDC® software package, and verified.
In [17], a new DC voltage balancing method (Selective Swapping
Algorithm) for a cascaded multilevel inverter based STATCOM applica-
tions is investigated and the results are given. The proposed method based
on a selective-swapping algorithm has shown better performance in bal-
ancing the DC link voltages than conventional methods, especially for low
capacitor voltage, high power applications. The EMTDC/PSCAD simula-

tions carried out on a 3-phase, 7-level MLI based STATCOM done show
the success of the proposed method for all operating points.
In [18], the performance of various kinds of single phase inverters was
analyzed, i.e., two level and multilevel inverters with and without Multiple
Pulse Width Modulation Techniques (MPWM) for fuel cell applications and
best topology depending on harmonics available in the output was suggested.
9.3 Development of Multilevel Inverter

Multilevel converter technology has been started by the concept of a mul-
tilevel step wave in cascade H-Bridge converters as an attempt to present
a new control method that was useful to produce and employ the stepped
wave at the output. In 1970, the diode clamped converter was introduced
but all these efforts were done in low power applications. In addition to
these two types, the flying capacitor inverter which has been evolved was
employed in medium voltage and high power industries in 1990.
The various types of multilevel inverters are shown in Figure 9.2.
9.3.1 Diode-Clamped
The most widely used inverter type is the one in which the diode is used
as the clamping device to achieve steps in the output voltage. The neu-
tral point converter was essentially a three-level diode clamped inverter
which consists of two pairs of switches and two diodes. Each switch pair
works in complimentary mode and the diodes are used to provide access
to mid-point voltage. In a three-level inverter, every phase shares a com-
mon DC bus and has been subdivided by two capacitors into three levels.
The DC bus voltage is split into three voltage levels by using two series
Multilevel
Converters
Diode-Clamped Flying Capacitor Cascaded H-

Converter Converter Bridge
Symmetrical Asymmetric Symmetric Asymmetric

Flying Flying Cascaded Cascaded H-
Capacitor capacitor H-Bridge Bridge
Figure 9.2 Types of multilevel inverters.

+VDC
S1a
C1
S2a
D1a
VDC a
n
S3a
D1b
S4a
-VDC
Figure 9.3 Three-level diode clamped.
Table 9.2 Switching states of three-level diode

clamped inverter.
Switch status State Voltage
S1a=1,S2a=1 S=+ve +Vdc/2
S3a=0,S4a=0
S1a=0,S2a=1 S=0 0
S3a=1,S4a=0
S1a=0,S2a=0 S=-ve -Vdc/2
S3a=1,S4a=1
connections of DC capacitors, C1 and C2. Dc1 and Dc2 are the voltage stress
across each switch. It is assumed that the total DC link voltage is Vdc, the
mid-point is regulated at half of the DC link voltage, and the voltage across
each capacitor is Vdc/2 (Vc1=Vc2=Vdc/2). Figure 9.3 shows the circuit for a
diode clamped inverter for a three-level diode clamp and the switch states
are presented in Table 9.2.
9.3.2 Flying Capacitor

The capacitor clamped inverter is similar to that of the diode-clamped
inverter except the replacement of capacitors for diodes. The voltage steps in
the output can be provided by the voltage increment between two adjacent
capacitor legs. Figure 9.4 shows the three-level capacitor clamped inverter.
In the operation of a flying capacitor multilevel inverter, each phase node
can be connected to any node in the capacitor bank. Connection of the
C1
S1a
S2a
n
a
C1a
2VDC S3a
C2
S4a
Figure 9.4 Three-level flying capacitor MLI.
a-phase to positive node voltage occurs by turning on the switches, S1a and
S2a, and to the neutral point voltage by switching on S2a and S3a. The negative
node voltage is connected by turning on S3a and S4a. Clamped capacitor C1 is
charged when S1a and S3a are turned on and is discharged when S2a and S4a are
turned on. The charge of the capacitor can be balanced by proper selection
of the zero states. Unlike the diode-clamped inverter, in the flying-capacitor
inverter there is no requirement for consecutive conductive switches.
Moreover, phase redundancies are present in flying- capacitor inverters
whereas only line-line redundancies are in diode-clamped inverters.
9.3.3 Cascaded H-Bridge MLI

The cascaded H-Bridge multilevel inverter is mostly used in medium-
voltage high power drives and is composed of multiple units of series con-
nections of basic units which are connected in series. In a CHB multilevel
inverter the output voltage of each phase is given by:
V0 = V1 + V2 + V3
9.4 Symmetric MLI

If each voltage source of the MLI design has the same magnitude of DC
source, then this structure of MLI is known as symmetrical MLI. Various
structures of symmetrical source MLI are discussed.
In [19], new symmetric multilevel inverters using a modular hybrid
structure with a lesser number of switches had been proposed. The pro-
posed topology composed of 2 modules, E-Module and F-Module, which
S1
S9
VS1 VS2
S10
S2
VS3
VS4
S3
S11
F-Module
+
S12
V0
S4
-
VS5 VS6
S5
S13
VS7
VS8
C1 C2
S6 S7 S8
E-Module
Figure 9.5 Novel symmetric modular hybrid multilevel inverter [19].

are cascaded and shown in Figure 9.5. The simulation had been imple-
mented to achieve a voltage level of 25 and 37 with a THD of 4.15% and
3.86% respectively. The E-Module consists of a capacitive voltage divider to
double the number of non-zero levels.
A symmetric multilevel inverter based on non-insulated DC voltage
sources with a reduced switch count was proposed in [20]. The proposed
topology consists of n and n + 1 DC voltage sources and switches, respec-
tively shown in Figure 9.6 which are connected to the H-Bridge. The
15-level output voltage level with 12 switches is achieved with the same
voltage magnitude for the DC sources. It reduces the control complexity
and gate driver circuits.
A 19 output voltage level was achieved by the symmetric hybridized
multilevel inverter topology designed in [21]. The proposed topology is
composed of a switching capacitor (SC) unit and Floating Capacitor-based
(FCB) sub unit which is hybridized and consists of 12 power switches (nine
for SC and three for FCB sub-units) and 2 symmetrical DC voltage sources
shown in Figure 9.7 to achieve 19 levels.
In [22], a symmetric MLI is designed with same DC source supplying
each cell and it is shown in Figure 9.8. A compact design is arrived and the
cascade of this design provides a large quantity of output levels. A fifteen
level inverter is designed using two compact units and it is able to generate
a zero voltage level and seven positive levels at the load. By connecting an
S(n+1)/2
V(n+1)/2 = Vdc S(n-1)/2 S(n-3)/2 S2
S1
V(n-1)/2 = Vdc
+
V2 = Vdc
V0
V1 = Vdc
-
V2’ = Vdc
S’2
S’(n-3)/2
V’ (n-2)/2 = Vdc S’1
V’ (n-1)/2 = Vdc S’ (n-1)/2
S’ (n+1)/2
Figure 9.6 Symmetric multilevel inverter based on non-insulated DC voltage sources

[20].
T2’ a, 1 + +
T2
SC C1
Sub-Unit Sp1
Ss1 Sp2
V0,1
n1
2Vdc
D1 Ss2
Sp3
D2 C2 V0
T1
T1’
b,1 -
FCB a, 2 +
SL SR
Sub-Unit
2Vdc
n2 S V0.2
CL CR
-
b,2 -
Figure 9.7 Symmetric hybridised multilevel inverter [21].
COMPACT UNIT Sax1 Vx1
Sax2
Vx1 T1
Sx1 Vol T4
LOAD
Vx2
IL
Sx2 Sx4 Sx5
T3
T2
Vx3
Sx3
Figure 9.8 Symmetric compact inverter [22].

inversion circuit at the load side, 7 negative levels can be achieved. The
designed structure is simulated by considering each source’s voltage as 5V
and the design is tested with a resistive load of 70 ohm. The output wave-
form of peak voltage +35V and harmonic distortion of 3.22% is achieved
at the load.
9.5 Asymmetric MLI

If each voltage source of the MLI design has a different magnitude of DC
source, then this structure of MLI is known as asymmetrical MLI. Various
structures of asymmetrical source MLI are discussed.
An asymmetric switched capacitor multilevel inverter topology is pre-
sented in [23]. It consists of six unidirectional (S1-S6) and four bidirec-
tional (T1-T4) switches, four capacitors (C1-C4), and two unequal DC
voltage sources (V1 and V2), as shown in Figure 9.9. The proposed asym-
metric topology achieved a 25 level output with a lesser number of compo-
nents and a THD of 3.25%.
Figure 9.10 shows an asymmetric cascaded H-Bridge multilevel inverter
[24] designed using three cascaded H-Bridges (main bridge and 2 auxiliary
bridges) and only one DC voltage source per phase to feed an H-Bridge
with a binary asymmetric ratio of 4:2:1. The voltage can be formed by
using three different combinations of cell voltages (or CVCs), which are
CVC1: [4Vdc, -2Vdc, 1Vdc], CVC2: [4Vdc, 0, -1Vdc], and CVC3: [0, 2Vdc,
1Vdc]. The advantages of this topology can be extended to any number of
H-bridges with floating capacitors with a lesser number of switches and by
using the cell voltage combinations, it ensured the self-balancing.
S6
+ +
S1 V1 C1 T4 C3 V2 S2
- -
+ -
T1 2V1 2V1 T1
- +
T3
+ + S4
S3 V1 C2 S2 C4 V2
- -
+ V0 -
Figure 9.9 Asymmetric switched capacitor multilevel inverter [23].

Main Bridge Aux Bridge-1 Aux Bridge-2
+
4Vdc VS + +
- 2Vdc C1 1Vdc C2
- -
Cell-1 Cell-2 Cell-3
Figure 9.10 Binary asymmetric MLI [24].
A trinary asymmetric cascaded H-bridge multilevel inverter with hybrid

switching scheme is designed in [25]. The Figure 9.11 shown consists of
three H-bridge cells, the main, auxiliary 1, and 2 H-bridge cells. The high
frequency operating region has been tracked by using the trinary asym-
metric MLI. The proposed topology has achieved 27 levels which are used
in the grid-connected PV power-conditioning applications.
- Vch 2+
S9 S11
Nt D4 +
Vax2 Lf
-
D5 S10 S12
- Vch1 + Aux H-Bridge 2
S5 S7
Ns D2
+
Vax1
-
D3 S8
S6
Aux H-Bridge 1
D1
Np
Lm S1 S3
+ +
Vpv Sb
Vmain
- -
S2 S4
Main H-Bridge
Figure 9.11 Trinary asymmetric MLI [25].

Sx
V1 + T1 T3
+ V2
S1 S3
V1 + + -
Load + V2
S2 S4
V1 +
T4 T2 + V2
Sy
Figure 9.12 Asymmetric ladder inverter [26].
The asymmetric inverter in [26] uses six unequal DC voltage sources

(V1 = Vdc =10V and V2 = (n+2)*V1 = 40V) and ten power switches (6 unit-
direction and 4 bi-direction). The design is shown in Figure 9.12 and it
generates a 31-level inverted voltage at load. The load is considered as
resistive with a value of 50 ohm and the inverter produces +150V as peak
voltage with a THD of 3.18%.
9.6 An Examination on Current MLI’s

A brief work on current designs of MLI’s studied in terms of number of
voltage levels, number of switches presented, and the data points of the
MLI’s is provided in Table 9.3. A representation on voltage levels generated
by various MLI’s is shown in Figure 9.13.
In [27], different topologies of asymmetrical and symmetrical cascaded
multilevel inverters with 16 switches and 4 DC voltage sources producing
an output of 257 levels with low THD% is proposed.
In [28], a multilevel inverter topology with 7 switches and 3 DC voltage
sources producing an output of 11 levels with low THD% and a peak volt-
age of 100V is proposed. In [29], an extended multilevel inverter topology
with 7 switches and 3 DC voltage sources producing an output of 11 levels
with low THD% and a peak voltage of 300V is proposed.
In [30], a multilevel inverter topology with 8 switches and 4 DC volt-
age sources producing an output of 61 levels with low THD% and a peak
voltage of 390V is proposed. In [31], a multilevel inverter topology with 16

switches and 6 DC voltage sources producing an output of 31 levels with a
low THD of 3.27% with 225V as peak value of output voltage is proposed.
age sources producing an output of 27 levels with a low THD of 4.04% and
peak voltage output of 390V is proposed.
age sources producing an output of 25 levels with a low THD of 3.37% for
R and 0.15% for RL loads with a peak output of 288V is proposed.
age sources producing an output of 125 levels with a low THD of 5.9% with
400V as peak output value is proposed.
In [35], a multilevel inverter topology with 4 switches and minimum
DC voltage sources producing an output of 10 levels with low THD% is
proposed. In [36], a multilevel inverter topology with 12 switches and 4
DC voltage sources producing an output of 49 levels with a low THD of
1.26% is proposed.
Table 9.3 Data points of current MLI’s.

Reference No. of voltage No. of No. of voltage
paper no. levels switches sources
27 257 16 2
28 11 7 3
29 11 7 3
30 61 8 4
31 31 16 6
32 27 14 3
33 25 10 4
34 125 24 3
35 10 4 4
36 49 12 4
27
300
36 250 257 28
200
150
35 100 29
49
11
50
10 11
0
61
125
25 31
27
34 30
33 31
32
Number of output level
Figure 9.13 Reference paper number vs number of output levels.
The presence of harmonics in the voltage spectrum for recent structures

of MLI is presented in Table 9.4. Also, a comparison of current MLI’s with
respect to generation of voltage levels, quantity of switches, and voltage
source used is represented in Figure 9.14.
Table 9.4 Presence of harmonics vs peak output voltage generation.

Reference paper THD (%) in voltage
no. waveform Peak value (V)
27 RL-0.48 128
31 RL-3.27 225
32 R-4.04 390
33 R-3.37 288
RL-0.15
34 RL-5.9 400
36 RL-1.26 576
257
2
16 3
7 3
761 4 125
11 6
8 3
11 16
31 14 4
27 27 10 3
28 24 4
29 25
4
30 4
31 49 12
32 10
33
34
35
NO. OF VOLTAGE LEVELS 36
NO. OF SWITCHES
NO. OF VOLTAGE SOURCES
Figure 9.14 Comparison on current MLI’s (Reference paper number vs other

parameters).
9.7 Summary
A detailed study of various multilevel inverters in terms of utilization of
multilevel inverter in sustainable energy applications was carried out and
presented. Also, types of late multilevel inverters are discussed including
the operations of the design. A brief work on recent design of multilevel
inverters with respect to harmonic presence in the output voltage wave-
form and the number of voltage levels that the design can generate were
analysed. Also, an analyses on recent symmetric and asymmetric voltage
source inverters in terms of number of voltage level the design can generate
was presented. From the design configuration, the asymmetric inverter is
able to generate more output levels than a symmetric inverter. Also, com-
pared with unary and binary, the trinary configured sources yield more
output levels. Thus, design of a multilevel inverter with low cost and com-
pact size plays a prominent role in photovoltaic power generation systems,
grid integrated renewable power networks, power trains, fuel cell power
generation, motor drive systems, etc.
Acknowledgement
The authors thank RUSA 2.0 (PO 2) project for the financial support and the
Department of Electrical and Electronics Engineering, Anna University.
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Part II
ELECTRIC MACHINES AND DRIVES
10
Technical Study of Electric Vehicle
Charging Infrastructure and Standards
R. Seyezhai* and S. Harika
Renewable Energy Conversion Laboratory, Sri Sivasubramaniya Nadar College

of Engineering, Kalavakkam, Chennai, India
Abstract
Electrification of the transportation sector is a promising path to reduce the
dependency on fossil fuels and environmental impact, but the major hurdle faced
in implementing electric vehicles is the lack of charging station infrastructure and
the associated standards required for practical implementation. This chapter dis-
cusses the current status, most modern deployment, and demanding issues in the
accomplishment of electric vehicle (EV) and charging systems. It also explores
the technologies and standards related to Electric Vehicles (EVs), Electric Vehicle
Service Equipment (EVSE), and the associated facilities. A review of charging
framework and standards linked to EV are discussed in detail in this chapter.
This chapter provides a comprehensive overview of the different power converters
employed for EV charging stations. This study will be useful for researchers and
industry personnel working in the area of electric vehicles and their associated
infrastructure.
Keywords: Electric Vehicles (EVs), Electric Vehicle Service Equipment (EVSE),

power converters, EV charging station
10.1 Introduction
In India, a GDP growth rate of more than 7.2% is expected in the next five
years [1]. This leads to increase in crude oil consumption. As the trans-
portation sector is the biggest consumer of crude oil, it not only has an
317
impact on greenhouse gas emissions, but also on the fossil fuels which
are on the verge of becoming extinct. Thus, the transport sector needs a
push for transformation from a fuel based system to an eco-friendly nature
based electric vehicle system. The advancement in power electronics and
energy storage technologies also strengthens the development of electric
vehicles (EV). Integrating the electric vehicles with grid reduces the carbon
dioxide emissions by 40% and furthermore, integrating with renewable
energy sources, it is reduced to nearly zero percent. In India, by switch-
ing to electric vehicles, approximately 4.7 lakh crores spent for crude oil
import can be cut down [2, 3]. Also, the well to wheel efficiency of 24%
is achieved with EV, whereas, with conventional ICE, it is 16%. The adop-
tion of the electric motor has more advantages such as less maintenance,
negligible mechanical wear, and straightforward design of power train.
As a fewer number of components are employed, higher efficiency can
be obtained. Various incentives are granted by the Government of India
such as National Electric Mobility Mission Plan (NEMMP) (2020), Faster
Adoption and Manufacturing of Electric Vehicle (FAME I), and NITI
Aayog (2015), which targets 100 % EV in India by 2030. In India, 3600 elec-
tric car, 6.3 lakhs electric two wheeler, and 1.26 lakhs electric three wheel-
ers sold out in the year 2018-2019. The policies and standards are framed
for regulation, testing, and certification of electric vehicle production to
enhance the future of e-mobility. Though EV has rapid growth, still it faces
the problem of inadequate charging infrastructure. Thus, to improve the
growth of EV production, the Government of India announced the FAME
II scheme in 2019 to establish several EV charging stations in India [4, 5]
and it is expected that approximately 6,000 charging stations will be built
at the end of 2020. The potential location of EV charging stations can be
national highways, shopping malls, airports, supermarkets, restaurants,
fast food centers, public parking, and bus depots. Section 10.3 discusses the
review of EV charging infrastructure, Section 10.4 deals with the review
of DC-DC converters for EV charging stations, Section 10.5 portrays the
standards of EV, EV charging stations, and a description of EV connectors.
Section 10.6 provides an overview of the charging stations in India.
10.2 Background
The conventional vehicle requires a greater amount of petroleum products,
thus it is a major contributor to greenhouse gas emissions. This led to the
growth of electrified vehicles which use electricity to generate power instead
EV Charging Standards 319
of petroleum products [6]. As electric vehicles (EV) gain more attention in

the automotive sector due to their environmentally friendly nature and the
demand for charging the EV is also rising [7]. The electric vehicle can be a
hybrid electric vehicle (HEV) or battery electric vehicle (BEV). In both the
vehicles, the battery is the heart of the vehicle which requires frequent and
proper charging. Many researchers focus on the study of the impact of EVs
on the utility side with appropriate solutions [8]. In addition to it, the elec-
tric vehicle also faces the problem of battery life, long charging time, and
grid integration [9]. Thus, the work focuses on the study of electric vehicle
charging stations and their associated components.
The charging method is of three types: AC connected system, DC
connected system, and battery swapping technology. The AC connected
system requires an onboard charger, whereas the DC connected system
bypasses the onboard charger. The DC connected system has an off-board
charger which comprises of a DC-DC converter and it is placed in the
station itself. The onboard charger comprises of a rectifier system with a
DC-DC converter incorporated in the vehicle. The AC connected system
has the problem of limited power and slow charging, whereas with the DC
connected system, it has been mitigated. The DC connected system has the
merits of large power rating, fast charging, and is capable of integrating
with renewable energy sources. An AC connected system of 1kW charges
the EV battery of 10kWh in 10 hours, a DC fast charger of 50 kW charges
the EV battery of 25 kWh in 30 minutes, and battery swapping takes places
in 30 seconds [10]. The first EV bus (battery capacity: 660 kWh) which
employs battery swapping technology was established in Ahmadabad,
India by Ashok Leyland and Sun Mobility. The Ahmadabad station does
seven swappings per day and it takes around 3 minutes.
In AC and DC EV charging stations (EVCS), a power electronic unit
is essential in order to enhance the performance and life-cycle of the car
battery. The power converters employed for EVCS need to satisfy cer-
tain requirements such as high power factor, low total harmonic dis-
tortion (THD), reduced output voltage ripple, and improved efficiency.
Thus, DC-DC converters employed for EVCS have been reviewed in this
chapter.
A detailed study of both the charging system, connectors employed for
EV, different types of converter used for EV, descriptions of connectors,
and the standards for EV and EVSE are discussed in this chapter. Also, the
EV charging station in India has been presented. This chapter will help
have a clear idea about the charging infrastructure for EVs.
10.3 Review of EV Charging Infrastructure

In electric vehicle charging stations (EVCS), two major components includ-
ing electric vehicle service equipment (EVSE) and a charger unit need to
be considered. EVSE is required to provide electrical energy to the vehicle.
An EVSE, when connected to the vehicle, does a few security checks and
then negotiates the charging current required to charge the battery [11].
The communication is established between the EV and EVCS through the
charger connector. The charging level is selected based on the command
received from the control pilot which is in the connector. The control pilot
generates a 1kHz square wave of ± 12 V to sense the vehicle presence and
fix the allowable charging current. The connector is designed to withstand
10,000 mating cycles (connection and disconnection) and exposure to the
elements. Based on the PWM feedback given by the vehicle, the EVSE gives
the output. And, based on the state of charge of vehicle battery, the EVSE
decides the charging profile. If the proximity pilot sends an error signal,
then the latches in the socket are opened. All states of operation between
Table 10.1(a) Difference between AC connected system and DC connected

system.
AC connected system DC connected system
Conversion Stages More Less
Front End DC rating No Yes
Control Complex Simple
Protection Simple Complex
Efficiency Low High
Table 10.1(b) Difference between on-board charging and off-board charging.

On-board charging Off-board charging
Power Range Designed for higher kilowatts Designed for lower
power kilowatts power
(20 kW DC - 80kW DC) (3.3 kW AC - 6.6 kW AC)
Remarks Reduces the size complexity Increases the weight and
of vehicle dynamics size of the vehicle
Table 10.2 Types of charging levels.

Cost of Cost of Overall
Type of charging Charging infrastructure electricity lifetime
level Power rating Specification time (Rs) (Rs) cost (Rs)
Level 1 (Single-phase 1kW 120V/AC, 15A 6-24 hours 25,000 1,287 35,000
AC Charging)
Level 2 Up to 19.2 kW 230V/AC, 40A 2-8 hours 75,000 936 90,000
(Three - phase AC
Charging)
Level 3 40kW 450V/DC, 80 A 30 minutes 3,00,000 650 3,025,000
(DC FAST Charging)
Level 4 150kW 450V/DC, 200A 15 minutes 9,00,000 520 9,025,000
(DC FAST Charging)
the EV and EVSE are completed in milliseconds. CAN communication is

most widely used as it transfers the information much faster.
In the on-board charger, the AC power from the grid supply is converted
to DC power to charge the battery. In an off-board charger, DC power is
regulated to provide a steady power to the battery in order to enhance the
performance of the battery. Thus, the DC charging station leads to fast and
quick charging and is capable of integrating with renewable energy sources.
Solar power is the most widely used one. The difference between AC con-
nected systems and DC connected systems and on-board and off-board
charging is illustrated in Tables 10.1(a) & (b) and the levels of charging are
presented in Table 10.2.
The possible location of electric vehicle charging stations is clearly pre-
sented in Figure 10.1 and the types of charging methods applicable to the
type of vehicle are presented in Table 10.3.
In the case of an AC connected system, the Level-2 charger has higher
efficiency than the Level-1 charger. For example, for charging of less than
4kWh, Level-1 charger efficiency is 74.2%, whereas a Level-2 charger
achieves an efficiency of 87.2%. However, compared with AC connected
systems, the DC connected system is more preferable as it has high effi-
ciency, low conversion stages, and less charging time. Thus, the different
converters employed for a DC connected system have been reviewed in
the next section.
Residential Workplace
(Level 1) (Level 2)
Charging
Location
Destination Arterial Road

(Level 3) (Level 4)
Figure 10.1 Location of charging station.

Table 10.3 Types of charging methods.

Types of vehicle Range per day Types of charging methods
2W, 3W, and 4W < 50 km Level - 1 and Level - 2
2W > 50 - 120 km Battery Swapping
3W > 50 - 150 km Battery Swapping
4W > 50 - 100 km Level - 3 and Level - 4
4W > 100 - 200 km Battery Swapping and Level - 4
Staff Buses > 100 - 200 km Level - 4
Intercity Buses > 100 - 200 km Battery Swapping and Ultra-Fast
Charging
where W - Wheeler.
10.4 Review of DC-DC Converters for EVCs

Different types of DC-DC converters are employed in both types of
charging station [12, 13]. By employing an efficient DC-DC converter, the
performance of the battery is enhanced and hence, the vehicle efficiency is
improved [14, 15]. The different converter topologies applied for battery
charging applications have been reviewed and the summary of the litera-
ture survey is depicted in Figure 10.6. The full-bridge topology is mostly
used because of zero voltage switching with a lower circulating current
and proper phase-shift control [16–22]. It is implemented by adding small
inductance in series with the primary inductor, which increases the losses
and affects the system performance. However, it can be achieved only in
limited load and input voltage. This will lead to duty cycle loss and volt-
age ringing across the secondary side rectifier. To mitigate this, several
techniques are reported in the literature [23–27]. These circuits utilize the
energy stored in the auxiliary circuit to achieve the ZVS irrespective of the
load and input voltage range. In [23, 24], the auxiliary circuit has a pair of
inductors, whereas in [25], it comprises of a pair of switches and an induc-
tor. In [26], zero voltage switching is attained with the help of a secondary
switch. The topology described in [27] utilizes the adaptive energy stor-
age concept using either a coupled or uncoupled inductor. The proposed
topology utilizes the auxiliary transformer inductance to achieve ZVS. The
circuit diagram of the phase shift controlled full bridge ZVS converter is
shown in Figure 10.2 [28].
S3
S1
+
VIN
-
S2 S4
Figure 10.2 Phase shift controlled full bridge ZVS converter (T1).
The two outputs, X and Y, are connected to the secondary of the trans-
former Tx and Ty, which has a rectifier unit and a load, as shown in Figure
10.2. Two voltage sources are connected in series with the transformer pri-
mary in order to avoid transformer saturation. Thus, the proposed FBZVS
topology attains the ZVS condition for a wide range of source voltage and
output current, as it depends not only on the source side but also on the
output current. In addition to that, it eliminates the voltage ringing and
duty-cycle loss since there is an absence of the inductive storage element in
the power transfer line.
In addition to the above techniques, many modifications have been done
in the phase modulated full bridge converters (PMFBC) to attain ZVS with
low conduction losses by operating at light load conditions. In [29, 30],
researchers suggested to use an inductor in cascaded connection with the
primary of the transformer and to incorporate a saturable inductor with a
high magnetizing current [31] and mag-amp (magnetic-amplifier) control
on the secondary side is discussed in [32]. In [33], a hybrid full bridge topol-
ogy is adopted to achieve ZVS with reduced conduction loss. Further, the
proposed hybrid configuration does not require an additional filter as the
input and output waveforms are nearly ideal. Thus, the filter size require-
ments are greatly reduced. The circuit diagram is shown in Figure 10.3.
L0
TA TB
C1
D1 D3
C0
T1 T2
TA1 TB1 D2 D4
C2
Figure 10.3 Hybrid configuration (T2).
The switches TA and TA1 and transformer T1 form the half-bridge sec-
tion and switches TA,TB,TA1,TB1 and transformer T2 form the full-bridge
section as depicted in Figure 10.3. Here, switch TA and TA1 are common to
both the sections. Thus, the hybrid combination is realized through half-
bridge and full-bridge sections. The switches in the half-bridge section are
uncontrolled, whereas the switches in the full-bridge section are varied by
controlling the phase-shift. All the switches are operated at fixed switching
frequency and fixed duty cycle. The output of the two sections are added
and filtered to get the desired output [34]. Thus, the proposed hybrid com-
bination results in reduced conduction loss at no-load condition, con-
stant switching frequency operation, ideal waveforms, and reduced filter
requirements both at the input and output sections.
As stated before, achieving ZVS across the active switches results in duty
cycle loss, high circulating current, high voltage spike, and electromagnetic
interference (EMI). Thus, to overcome this, many modifications have been
done in the full-bridge topology as mentioned earlier. Even the auxiliary cir-
cuit assisted full-bridge configurations have been analyzed and discussed in
[35–41], but it results in reduced efficiency and control complexity and at
light load conditions, it is difficult to obtain ZVS for leading-leg switches. To
mitigate the above stated problem, a new topology called ZVZCS (zero volt-
age and zero current switching) shown in Figure 10.4 is suggested in [42].
The proposed topology incorporates an asymmetrical pulse width
modulation (APWM) technique to mitigate the losses associated with the
switches and uses an auxiliary inductor (La) to realize the ZVS and ZCS
operation as depicted in Figure 10.4. An auxiliary circuit is required to
C3 Ds3
Ds1 S3 Ca1
C1 S1
D1 D3
+ Lse Tr Tr1
Vb +
VIN - La
C0
-
Ta
C2 D2 D2 D4
C1 S4 Ds4 S2 Ca2
Figure 10.4 ZCZVS topology (T3).
ensure the ZVS and ZCS operation and it extends the soft switching opera-
tion range over a wide load variation. Thus, it enhances the efficiency of the
converter compared to existing phase-shift modulation (PSM) technique.
Another most widely used topology for battery charging is a full bridge
LLC resonant DC-DC converter (FBLLC). The LLC converter involves
either the frequency modulation method (FM) or phase-shift modulation
method (PSM). Compared to the FM method, the PSM method reduces
the transformer core losses and improves the efficiency at light load condi-
tion [43–47]. However, it is not advisable to use it for heavy load conditions
as the turn-off current of the primary switches is high. Hence, to avoid the
above-mentioned problems, certain structural changes are done in LLC res-
onant converters and are discussed in [48, 49]. These resonant converters
can make the transition from half-bridge to full-bridge and vice-versa with
the help of additional switches. Hence, regulated output voltage is obtained
with minimum frequency variation and the magnetic components design are
optimized, but these converters require two additional switches to make the
transition, which is operating with hard switching, thus the turnoff currents
are higher, which in turn lowers the efficiency of the converter. Therefore, to
overcome the aforementioned problems, a novel dual FBLLC resonant con-
verter is proposed in [50] and the circuit diagram is depicted in Figure 10.5.
The cascaded connection of full bridge topology is represented in Figure
10.5. The proposed converter achieves ZVS and ZCS for all the active
switches for both CC and CV charge. One additional switch is required for
resonant tank transition and it is operated at a fixed frequency during the
entire battery charging mode. Due to this, switching loss and circulating
current is minimized. The features of the different full bridge converter
topologies are discussed as illustrated in Table 10.4. And, summary of all
the converters employed for EVCS is presented in Figure 10.6.
D1 D3 Rb
S1 S3 Llk1
C01
Lm1 Cb
Cr1
D2 D4
Cin Llk2 T1
T2
Lm2
S2 S4 Cr2
Cr3 D5 D7
S5
C02
D6 D8
Figure 10.5 Dual FBLLC resonant converter (T4).
10.5 Standards for EV and EVSE

The different standards used for EV and EVSE in different countries are [51]:
1. SAE (Society of Automotive Engineers): It is also called a

“J plug” connector. It uses the conductive charging type for
EV in North America. It can be used for both AC connected
systems and DC connected systems. The connector has two
additional pins (positive pin and earth pin) at the bottom
for a DC connected system. It carries a maximum voltage of
600 V and maximum current of 200 A.
2. IEC (International Electro-technical Commission): It is
used for charging electric cars within Europe. It carries a
maximum voltage of 1000 V and 200 A and the maximum
allowable power is 175 kW. In January 2013, the European
Commission announced that the IEC connector is an
Table 10.4 Summary of various full bridge DC-DC converter topologies.

Method of
achieving
ZVS No. of No. of No. of No. of
Topologies techniques inductors diode capacitors transformer Features
T1 Auxiliary Circuit Nil Nil Nil 2 • No voltage ringing
Consists of • No duty cycle loss
Inductor
T2 Hybrid 1 4 3 2 • Filter size requirements
Topology • Reduced conduction loss
T3 ASPWM 1 4 7 1 • A wide range of soft
switching operations
• ZVS turn-on and
ZCS-turn-off
• Minimization of auxiliary
inductor current
• Improved efficiency
T4 LLC resonant 4 8 7 2 • Resonant tank with one
circuit additional switch
• High voltage gain
• Fixed switching frequency
operation
Using Inductor
PSFB ZVS
No duty cycle loss
Dual FBLLC DC-DC Converter Hybrid

Resonant
Less Filter Requirement

High Voltage Gain Low Conduction loss
ZCZVS
ASPWM
Technique
Figure 10.6 Summary of different DC-DC converters employed for EVCS.
official charging plug within the European Union. It has

been adopted as the recommended connector in some coun-
tries outside of Europe, including New Zealand.
3. GB/T (GuoBiao): It has been used in China as well as in
Bharat chargers in India. It can be used up to 237.5 kW, 950
V, and 250A.
4. CHAdeMO: It is a quick charging method for battery electric
vehicles delivering up to 62.5 kW, 500 V, and 125 A direct cur-
rent. It is proposed as a global industry standard and included
in IEC as type 4. The CHAdeMO is abbreviated as “CHArge de
Move”, equivalent to “move using charge” or “move by charge”.
5. AIS (Automotive Industry Standard): It has been used in
India and framed by Automotive Research Association of
India (ARAI). This standard prescribes the specifications for
performance and safety for AC charging Stations for EV and
HEV applications for Indian conditions. This delivers up to
1000 V AC. This includes characteristics and operating con-
ditions of the supply device and the connection to vehicle,
operators and third party electrical safety, and the character-
istics to be complied with by the vehicle with respect to the
EVSE-AC, only when the EV is earthed.
Table 10.5 Different standards used in different countries.

Country India USA Japan EU China Korea
AC AIS - SAE SAE J1772 IEC GB/T SGS-
Charging 138 J1772 61851-1 20234 003
Part Part 2 Part
1 2
DC AIS - SAE CHAdeMo IEC GB/T SGS-
Charging 138 J1772 91851-23 20234 003
Part Part 2
2
Table 10.6 Standards used in India.

Standard Purpose
AIS 038 Rev 1 Requirements for Construction and Functional
Safety
AIS 039 Rev 1 Measurement of Electrical Energy Consumption
(Wh/km)
AIS 040 Rev 1 Method of Measuring the Range (km)
AIS 041 Rev 1 Measurement of Net Power and Maximum 30
minute Power
AIS 049 Rev 1 CMVR Type Approval for EV
AIS 048 Safety Requirements for Traction Batteries
AIS-053 Automotive Vehicles – Types – Terminology
The different types of standard used in different countries and in India

are illustrated in Tables 10.5 and 10.6. Most widely, SAE and CHAdeMo
have been used in many countries as they are reliable and can be used for
both AC and DC connected systems.
10.5.1 Description of EV Connector

The pin configuration of the connector used at an EV charging station is
depicted in Figure 10.7 [52].
where
PP - Proximity Pilot
CP - Control Pilot
CP
PP
N
L1
L2 L3
PE
Figure 10.7 Pin configuration of EV connector.
PE - Protective Earthing
L1, L2, and L3 - Positive supply
N - Negative supply
The control pilot does the communication between EVSE and EV and
verifies the proper connection of the charger with the EV and continuity
check. If any connectivity fails, the control pilot sends the signal to the
charger, the actuator opens, and the EV connector is removed from vehicle.
If the maximum charging rate exceeds, the resistivity between the proxim-
ity contact and protective earthing increases and the supply is interrupted.
This how the connector works in EV.
10.6 Charging Stations in India

The list of charging stations established in India so far is presented in
Figure 10.8.
MG motor- TATA Power

charging station - Delhi, BHEL charging
Charging
Mumbai. Bangalore, station - Delhi
station in India
Hyderaba, Ahmedabad,
Nagpur, Cochin and Agra
PlugNGO EESL charging

charging station - station - Delhi,
Delhi Haryana
Mahindra Reva Community Bescom charging

e2o - Bangalore, charging station - station -
Karnataka Delhi, Mumbai Bangalore
Figure 10.8 Charging stations in India.

10.7 Conclusion
The merit of switching from ICE to electric vehicles is clearly presented
in this chapter. Also, the outcomes of moving towards e-mobility have
been explored, but electric vehicles (EV) face the difficulties of insufficient
charging facilities. Thus, the different charging systems and power levels of
charging are clearly presented. Compared with an AC connected system,
a DC connected system is preferred due to less charging time and reduced
conversion stages and for effective charging, different DC-DC converters
have been reviewed in this chapter. From the literature survey, it has been
concluded that the dual FBLLC resonant converter is recommended for
electric vehicle battery charging applications as it has a high voltage gain,
reduced switching loss, and circulating current due to resonant tank tran-
sition at a fixed frequency. Also, the standards for establishment of electric
vehicle charging stations used in different countries and the description
of the EV connector has been discussed in this chapter. The most widely
used EV connector is SAE J1772 and CHAdeMo. The charging stations
established in India have been depicted. Thus, this chapter will be useful
for researchers and industrialists working in EV charging infrastructure.
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11
Implementation of Model Predictive
Control for Reduced Torque Ripple
in Orthopaedic Surgical Drilling
Applications with Permanent
Magnet Synchronous Machine
Ramya L. N. and Sivaprakasam A.*
Department of Electrical and Electronics Engineering, Anna University,

Chennai, India
Abstract
Orthopaedic surgeries are predominantly concerned with rectification of defor-
mities and diseases of bones and joints. Drilling force along whole depth varies
due to diverse bone density. Motor plays a vital role in controlling of torque rip-
ples for efficient drilling application. Brushless DC motors (BLDC) are currently
used in drilling machines due to their high-speed operations, but playing a big
role in motor efficiency, Hall effect sensors can significantly affect reliability and
performance. The purpose of this chapter is to replace BLDC with permanent
magnet synchronous motors (PMSM) and have an effective control with reduced
torque ripple and current harmonics in drilling applications with reduced noise.
The aim of effective control of PMSM is established by implementing efficient
control techniques and model predictive control (MPC). The performance of the
proposed MPC in steady and dynamic states compared with conventional MPC
proves the effectiveness of the proposed MPC, providing reduced torque ripple
and better transient performance. Further verification is carried out in a real-time-
simulation environment in OPAL-Real-Time Lab to validate the possibility of real-
time implementation. This chapter suggests that PMSM with the proposed MPC
control technique is an efficient alternative for orthopaedic drilling applications.
337
Keywords: Bone drilling machine, direct torque control, flux ripple, model
predictive control, permanent magnet synchronous motor drives, torque ripple
11.1 Introduction
Bones serve many vital functions in proper functioning of the body, a few
of which are they provide framework to the body along with providing
support for the complete system [1]. Bones help in movement of different
parts of the body, the bone marrows are blood cell manufacturing facto-
ries, and bones protect the internal organs.
Bones are active tissues and the density of the bones and shape of the
bone depends on few factors like gender, age, food pattern, etc. Thus,
maintaining a vital bone health is mandatory for wellbeing. There can be
many reasons that affect bone health like bone deformities, bone infec-
tions, arthritis, dislocations, fractures, and cartilage and meniscus injuries
to name a few. The solution for the bone problems has been given by ortho-
paedic surgeons.
Orthopaedic surgeries are predominantly concerned with rectification
of deformities, diseases of bones and joints, and injuries to the musculo-
skeletal system. The final objective of an orthopaedic process is to carry out
surgical procedures with minimal damage to surrounding muscles, tissues,
and organs and for the bone itself. A fraction of a second mistake could
cause severe damage when high speed orthopaedic devices such as drills
are used in orthopaedic surgeries [2, 3]. High accuracy and precise motion
control are mandates in orthopaedic drills.
Orthopaedic drills and saws are handheld devices which are held by the
surgeons in surgeries. Usually, these tools are driven by electric motors or
pneumatic actuators. Mounting screws to anchor plates or to attach exo-
skeleton devices for the fixation of fractured bones and mounting screws
for the traction equipment are some of them. Orthopaedic surgeries are
primarily concerned with the correction of deformity, diseases of bones
and joints, and injuries to the musculoskeletal system. A human bone is
made up of inhomogeneous material which consists of cortical bone (com-
pact bone) and cancellous bone. Due to the diversity of the human bones,
thickness of the bone, and the cross sectional diversity of the bone, it is dif-
ficult to detect the breakthrough of bones by controlling and observing the
torque of orthopaedic devices to avoid unwanted damages. Therefore, the
drilling force through the depth varies in orthopaedic surgeries. Hence,
the sensing and detecting of the drilling and cutting parameters, such as
thrust force, torque, speed, feed rate, and detecting of bone breakthrough is
Model Predictive Control of PMSM 339
very important for an orthopaedic drilling operation. Existing orthopaedic

drills do not have many sensory capabilities. However, it is advantageous
to detect the crossings between hard to soft and vice versa for accurate
drill control. Most previous researchers have found solutions for the break-
through detection and stop the drill accordingly. This procedure of detect-
ing and stopping the drilling tool might inject some small variations and
serious irreversible changes in critical situations. Therefore, it will be very
helpful to make accurate decisions in surgery. A method that has a speed
control mechanism to control the speed of the drilling motor that measures
the external torque and indicates to the surgeon irregularities of the bone
density and automatically minimizes the errors and controls the drilling
procedure by reducing or increasing the speed accordingly will be of great
use to doctors and surgeons. The system should allow the surgeon to make
the precious decision to avoid the damages of tissues and other anatomic
parts surrounding the bone.
The predominant difficulty in orthopaedic drilling is due to the density
variation in the bones [4]. Due to the diversity of human bones, it is diffi-
cult to detect breakthrough of bones just by observing the torque of ortho-
paedic devices to avoid unwanted damages. Drilling force along the whole
depth varies in orthopaedic surgeries. With the motor being the primary
component of the drilling device, the motor selection plays a vital role in
effective controlling of torque ripples for efficient drilling application.
Brushless DC motors (BLDC) are currently used in drilling machines
due to their high-speed operations replacing the universal motors [5], but
playing a big role in motor efficiency, Hall effect sensors can significantly
affect the reliability, performance, and life-cycle of many critical applica-
tions ranging from robotics to portable medical equipment. In addition,
problems encountered during a drilling procedure are recurrent faults and
fluctuating speed of the machine on variable loads. The wear and tear of
commutators and brushes in BLDC motors also cause electromagnetic
interference fault in the system.
The purpose of this chapter is to replace a BLDC motor with a perma-
nent magnet synchronous motor (PMSM) and have an effective control
with reduced torque ripple and current harmonics in drilling applica-
tions, along with reduced noise [6]. The aim of effective control of PMSM
is established by implementing the emerging efficient control technique
and model predictive control (MPC). The theory of MPC is to predict the
future behavior of the system based on model of the system and is evalu-
ated using a cost function to select a suitable voltage vector that minimizes
the cost function. A conventional MPC has errors of torque and flux in
its cost function. As designing of cost function plays an important role in
effective MPC of PMSM, in the proposed MPC, cost function is divided

into four components for tracking the torque, current, limiting current,
and for reducing switching frequency, respectively.
The simulation is carried out in a MATLAB/Simulink environment.
The performance of the proposed MPC in a steady state and dynamic state
compared with conventional MPC proves the effectiveness of the proposed
MPC. The waveforms and quantitative comparisons shows that proposed
MPC gives a reduced torque ripple and flux ripple compared to that of con-
ventional MPC. Thus, the proposed MPC provides a reduced torque ripple
and better transient performance [7].
The PMSM motor drive is controlled using the proposed MPC tech-
nique. As precision is a major concern for drilling applications, the con-
trolled torque and reduced torque ripple in the proposed MPC technique
will play a vital role in reducing the mechanical vibrations, resulting in a
more accurate drilling procedure. The reduced current harmonics increase
the performance of the system and also enhance the efficiency of the sys-
tem. The steady state of the system is maintained in spite of introduced
external load disturbances. The system thrives to maintain the steady state
and tracks the speed in very less time even before the technician or the
patient can realize the change in the load. This minimizes the variations
while drilling and reduces unexpected burr formations in the bone. The
acoustic noise is reduced in the proposed MPC technique, which reduces
the noise of the drilling apparatus, providing a noiseless environment
during the drilling procedure. However, the main concern about the MPC
technique is deciding the value of the weighting factor. Weighting factor is
a term used in the cost function to eliminate the parameter variations in
the cost function as usage of two variables of different nature in the cost
function is not an advisable task. Due to the lack of theoretical guidelines,
the tuning of the weighting factor is a nontrivial process done mostly by
empirical methods. This decision on the weighting factor value of the cost
function does take time, but this calculation of weighting factor is carried
out only once. When considering the advantages of the proposed MPC
technique for the PMSM drive, this calculation of weighting factor cannot
be considered as a demerit.
Further verification is carried out in a real-time simulation environ-
ment in OPAL Real Time Lab to validate the possibility of real-time
implementation. This chapter suggests that PMSM with the proposed
MPC control technique is an efficient alternative for orthopaedic drilling
applications.
11.2 Role of Motor in Orthopaedic Drilling

Applications
The main component in any drilling device is the motor unit. Proper selec-
tion of the drilling motor assures efficient delivery of the purpose. Just as
selecting a motor for a drill is important, selecting a perfect specification of
motor for orthopaedic drilling application is very crucial as even a minute
error can cause death of the bone which is completely irreversible.
11.2.1 BLDC Motors

BLDC motors are noiseless and efficient motors. BLDC motors are finding
applications due to their lesser maintenance and higher efficient behav-
ior, but the main drawback of these motors is the requirement of complex
wiring and the need for electronic drive circuits to operate. The electronic
drives need Hall effect sensors for monitoring the position of the rotor. The
electrical cycle of the BLDC rotor is divided into six sectors and the control
method of BLDC motors, known as the six-step method, can be imple-
mented by detecting the rotor position to generate gating signals to control
the six solid state switches of the three phase inverter. The most common
position sensor used in BLDC motors is the Hall element or switching
Hall sensor. Compared with the other rotating position sensors, such as
encoder, resolver, or linear Hall sensors, the Hall elements are cheaper and
more robust. However, they can only produce low resolution feedback.
This continuous monitoring challenges the reliability of the system, which
is the main parameter in designing biomedical instrumentation systems.
Also, a minute time delay exists in sensing the speed transient. In ortho-
paedic applications, a small time delay can cause a serious injury.
11.2.2 Permanent Magnet Synchronous Motors

The main drawback of BLDC is the usage of Hall-effect sensors that ques-
tion the reliability of the system, which is completely eliminated when
BLDC is replaced by PMSM. For the same specification, the size of PMSM
is reduced compared to BLDC, which will help in easy operation with
reduced weight of the drilling machine. Additionally, it is known that
PMSM has less noise during operation due to significantly fewer current
harmonics because of the sinusoidal current waveform compared to the
trapezoidal current waveform in BLDC. This validates the idea behind the
chapter of replacing BLDC with PMSM in orthopaedic applications that

will provide an improved efficient drilling procedure.
11.2.2.1 PMSM Machine Equations

A surface mounted PMSM is tested for the MPC techniques. For PMSM,
all the parameters are constant in the rotor synchronous coordinates and
Led and Leq are equal. The mathematical machine equations of PMSM in a
synchronous frame are given as [8]:
d
uts = Rts its + ψ ts + jω ts ψ ts (11.1)
dt
ψts = (Ledied + ψfp) + jLeqieq (11.2)
3
Tet = pψ ts × its (11.3)
2
died
ued = Rtsied + Led − ω ts Leqieq (11.4)
dt
dieq
ueq = Rtsieq + Leq + ω ts Ledied + ω ts ψ fp (11.5)
dt
where Rts is the stator resistance, Led and Leq are the d-axis and q-axis induc-
tance, ψfp is the permanent magnet flux, ψts is the stator flux vector, uts, ued,
and ueq are the stator voltage vector, d-axis, and q-axis component, its, ied,
and ieq are the stator current vector, d-axis, and q-axis component, p is the
ied Rts ωtsψfp ieq Rts ωtsψfp

iedt ieqt
iedi ieqi
ued Ri Ri
Led ueq Led
(a) (b)
Figure 11.1 Equivalent circuit of PMSM in (a) d-axis and (b) q-axis.
number of pole pairs, ωts is the rotor speed, and Tet is the electromagnetic
torque. The equivalent circuit of PMSM in the d-axis and q-axis is shown
in Figure 11.1.
11.2.3 Control Methods of PMSM

A Permanent Magnet Synchronous Machine (PMSM) is a synchronous
motor that uses permanent magnets rather than windings in the rotor.
PMSMs offer high efficiency, high power factor, high torque-to-weight
ratio, faster response times, rugged composition, are fairly easy to control,
and easy to maintain.
PMSMs are highly preferred for efficient performance motor drives as
their control is categorized by even rotation for the complete speed range,
effective torque control in nil speed, and dynamic acceleration and deceler-
ation. Permanent magnet (PM) machines are the most efficient of all types
of electrical machines due to the use of permanent magnets for excitation,
which consumes no power. Other merits of PM machines include simple
control technique, high power density, and ease of cooling. However, PM
machines also suffer from some disadvantages, such as narrow constant
power speed range, possible demagnetization, and high cost. Two vec-
tor control methods used for effective PMSM control are Field Oriented
Control (FOC) and Direct Torque Control (DTC).
In FOC, proposed by Hasse and Blaschke [9], the machine expressions
are modified into coordinate systems that rotate synchronously with the
rotor flux. Many literatures are available in FOC that include modern non-
linear control, feedback linearization control, multi-scalar models, and
passivity based models. The main advantage of FOC is decoupling of the
torque and flux control similar to a separately excited DC machine, provid-
ing better control. It is a basic technique to control the Alternating Current
machines by effectively transforming their dynamic structure into that of
Direct Current machines. This vector control method was developed based
on the park transformation and introduces the design and model of syn-
chronous machines. The control principle is to decouple the stator current
into its flux producing and torque producing components and allows inde-
pendent control of the field and torque of the machine by employing the
corresponding field oriented parameters. This system adapts to any load
disturbances and operates as fast as DC machines. Though this method
provided good control of the synchronous machines, the transformation
process of the machine equations was a tedious procedure.
Due to this drawback, FOC was replaced by DTC, introduced by
Depenbrock and Takahashi-Noguchi [10] in the mid 1980s for induction
motors, differing from that of FOC. The tedious transformation process

was completely eliminated and a concept of look up table was used in DTC.
Due to the advantages of DTC, this control was adapted for PMSM also.
The DTC method is predominantly used in variable frequency drives to
directly control the torque and flux of a three-phase AC electric machine
[11]. This control is effectively executed by proper selection of voltage vec-
tors using an optimum lookup table. DTC uses two comparators: the hys-
teresis comparator and torque comparator, to calculate the flux and torque
errors and select a voltage vector that satisfies the error constraints. The
block diagram of a DTC is as shown in Figure 11.2.
In DTC, the sectors are divided into six. DTC uses a predefined lookup
table by which it selects the voltage vector to be applied for a sector. The
main advantages of DTC compared to FOC are elimination of the current
control loop, tedious transformation is avoided, and no separate voltage
pulse width modulator is needed. DTC is advantageous due to less parame-
ter dependence and faster torque response when compared with the torque
control via FOC control. The switching state of the inverter is updated once
only in every sampling interval and it does not change until the output of
the hysteresis controller changes states. Therefore, the ripples in torque and
flux are relatively high when compared with those of the vector control
drive system. Although a smaller hysteresis bandwidth may result in less
torque ripples, the switching loss of the inverter will dramatically increase.
Three phase AC supply
Rectifier
Teref ∆Tc dTc

N*r
PI (V0 – V7)
Switching
Tc VSI PMSM
Nr table
∆фs
фsref dфs
фs
θ
Vs
Torque and Flux
Estimation is
Figure 11.2 Control circuit diagram of DTC.

Furthermore, the switching frequency of the inverter is not constant. The

switching action only depends on the observed torque and flux linkage
values. Therefore, the inverter switching frequency varies against the rotor
speed, load torque, and the bandwidth of the two hysteresis controllers.
The drawbacks of the DTC are the torque and flux ripple, variable switch-
ing frequency, and acoustic noise. Furthermore, DTC makes use of the
hysteresis controller which leads to a variable computation frequency and
variable switching frequency [12].
Many schemes have been proposed to improve the DTC scheme to
achieve better performance like hysteresis controllers being replaced by a
fuzzy logic controller, which considers not only the sign of the error, but
also the amplitude. A neural network is used to select the vector. These
proposed strategies focus on a direct regulation of two outputs, namely
torque and flux amplitude. These strategies are based on the minimization
of a weighted function of quadratic or absolute value functions of the out-
put errors. A 3-level inverter fed DTC scheme with a modified switching
table is proposed to improve performance at low speeds. However, it failed
to consider other problems such as neutral point balance and voltage jump.
Duty ratio of the selected vector is obtained by solving the optimal value
which will lead to minimum torque ripple RMS during one period. The
duty of the active vector in one period can also be obtained from a fuzzy
logic controller. A band-constrained technique is proposed, which aims
at limiting the torque ripple to the hysteresis band, not the minimal RMS
of torque ripple. A completely different approach to achieve better results
by replacing the hysteresis torque and flux controllers with proportional–
integral (PI) regulators and voltage modulators was proposed. Though
such variations are used to improve the performance of DTC techniques,
performance improvement is quite limited and it reduces the simplicity
of the classic DTC scheme. To overcome the disadvantages of DTC, other
control techniques such as space vector modulation (SVM), matrix con-
verter, multi-level converter, incorporating duty cycle, model predictive
control (MPC), etc. are discussed in the literature. The merits and demerits
of various control methods for PMSM are tabulated in Table 11.1.
In the above mentioned strategies, Model Predictive Control is recently
introduced as an effective alternative to the conventional DTC. In MPC,
the heuristic lookup table is replaced by an accurate system model. It pre-
dicts the evaluation of the machine variables such as torque and flux. Also,
MPC allows the controller to include nonlinear control variables.
Table 11.1 Merits and demerits of various control methods for PMSM.
Method Merits Demerits
FOC • Decoupling of the torque • The transformation
and flux control similar process of the machine
to a separately excited DC equations was a
machine, providing better tedious procedure
control
DTC • Effectively executed by • The ripples in torque
proper selection of voltage and flux are relatively
vectors using an optimum high when compared
lookup table with those of the
• Elimination of the current vector control drive
control loop, tedious system
transformation is avoided, • The switching loss
and no separate voltage pulse of the inverter will
width modulator is needed dramatically increase
DTC with • Considers not only the sign • Performance
Fuzzy Logic of the error, but also the improvement is quite
Controller amplitude limited and it reduces
• These proposed strategies the simplicity of the
focus on a direct regulation of classic DTC scheme
two outputs, namely torque
and flux amplitude
3-level • Modified switching table • It failed to consider
Inverter improves the performance at other problems, such as
Fed DTC low speed neutral point balance
Scheme and voltage jump
Band- • Aims at limiting the torque • Performance
constrained ripple to the hysteresis band, improvement is quite
Technique not the minimal RMS of limited and it reduces
torque ripple the simplicity of the
• A completely different classic DTC scheme.
approach to achieve better
results by replacing the
hysteresis torque and flux
controllers with proportional–
integral (PI) regulators and
voltage modulators
MPC • Reduced torque ripple and • Calculation of
current harmonics weighting factor is an
empirical method
11.3 Model Predictive Control

For decades, Model Predictive Control has found its applications in many
engineering practices like the chemical and manufacturing industries. The
advancements in the field of microcontrollers has paved the way for faster
computation and MPC techniques are now finding applications in power
electronics drives [13]. Easy concepts, quick response, and high flexibil-
ity in incorporating various constraints are the main advantages of MPC.
Figure 11.3 shows the general block diagram of MPC. The process of MPC
can be summarized in the following points:
• Reference measurement of some variable x*(m) like torque

or current
• Predict the values of the controlled variable for the next
instant, x(m+1) for all the possible voltage vectors of the
inverter using x*(m) along with the present values of x(m)
from the load
• These predicted values are evaluated using a cost function
• The voltage vector that gives the minimal cost function is
opted as the optimal voltage vector for the next sampling
period
Different from the employment of hysteresis comparators and the

switching table in conventional DTC, the principle of vector selection in
MPC is based on evaluating a defined cost function. The selected voltage
vector from the conventional switching table in DTC may not necessar-
ily be the best one for the purposes of torque and flux ripple reduction.
Since there are limited discrete voltage vectors in the two-level inverter-fed
Converter Load
x*(m) Minimization of Switching

cost function States
x(m+1)
x(m)
Predictive Model
Figure 11.3 Block diagram of model predictive control.

PMSM drives, it is possible to evaluate the effects of each voltage vector

and select the one minimizing the cost function. The key technology of
MPC lies in the definition of the cost function, which is related to the con-
trol objectives. The greatest concern of PMSM drive applications are the
torque and stator flux, and thus, the cost function has to be defined in such
a way that both the torque and stator flux at the end of the control period
are as close as possible to the reference values.
11.3.1 Structure of MPC

The structure of MPC explains the general working of the control tech-
nique. MPC consists of two elements: the optimizer which determines
optimal future control actions and the model of the system to be con-
trolled. The model is used to predict the future system behavior. The total
response, which is the sum of the forced and the free response, is calcu-
lated until the prediction horizon. The cost function is used to evaluate
the total system response [13]. Finally, an optimizer determines the best
set of future controls u (t + j). The choice of the cost function depends
on the demands of the process to be controlled and not the controller. As
the future control set is decided by the cost function, MPC can handle
non-linear systems and multiple input multiple output systems (MIMO).
The use of the Receding Horizon method of selecting the future control
set makes MPC a real closed loop feedback control system in which only
the first member of the set u(t) is transmitted to the controlled system and
the whole operation of prediction, optimization, and control is repeated
for each control set. MPC is more like a day to day human behavior, for
example driving a car.
MPC mainly takes the system mathematical model to interpret the
future behavior of the system. Analogous to FOC and DTC, MPC is clas-
sified into two techniques: continuous MPC and finite control set MPC
(FCSMPC), as shown in Figure 11.4 [14, 15]. Resembling FOC, the contin-
uous MPC requires PWM or a duty cycle to predict the future that misses
to evaluate the discrete nature of the converter. FCSMPC, in contrast, eval-
uates for each possible voltage vector and the one that minimizes the error
between the reference and the feedback value is selected. FCSMPC is sim-
ilar to DTC in that they both directly select one and only one voltage vec-
tor during one control period. Due to the advantages, FCSMPC has been
widely studied and applied in motor drives. According to the predictive
horizon, FCSMPC is classified into two: with a predictive horizon N = 1,
evaluation hurdles are relatively minimized and can be easily implemented;
Model Predictive
Control (MPC)
Continuous reference
Surpasses deadbeat.
voltage vectors is
Nonlinearities and system
constraints control capability Finite Control Set Continuous Control Set calculated
PWM required to
More computational efforts MPC MPC generate the gate signals
are needed.
(FCS-MPC) (CCS-MPC)
Reduced torque Good performance and
ripples. high robustness
Notable current Predictive Torque Generalized Predictive Complex
harmonics. Control Control implementation
Better current Calculates the ideal voltage

quality vectors in a direct manner.
Slight higher
Predictive Current Deadbeat Control of nonlinearities
torque ripples Control MPC and other constraints are
difficult to be realized
Figure 11.4 Model predictive controller classification.
with long predictive horizon N > 1, computation increases. In this chapter,

the predictive horizon is taken as N = 1.
11.3.2 Cost Function

Application of MPC to control the motor drives is considered an effec-
tive alternative for DTC. MPC uses an online optimization to replace the
lookup table of DTC, thus selecting a more appropriate voltage vector to
maintain the torque and flux within the bounds. The performance of MPC
is analyzed by a performance optimizer -- the cost function. The key fea-
tures of the MPC control technique are the cost function and the model
of the system. The cost function plays an important role in predicting the
appropriate voltage vector, signifying that the cost function equation must
be framed efficiently to make the MPC more accurate. The cost function
is calculated for all the voltage vectors and the one with least cost function
value is selected as the best voltage vector, confirming that MPC is more
accurate than conventional DTC [14].
The cost function is an important performance analyzing parameter
in MPC. It plays an important role in deciding the voltage vector, which
proves that the cost function equation must be framed efficiently to make
the MPC more accurate. The most important point to be noted here is that
MPC has the flexibility of incorporating various constraints. To achieve
simultaneous control of the included various constraints, the cost function
should have a well-designed weighting factor, as it plays a major role in the
performance of the system. Weighting factor is a term used in the cost func-
tion to eliminate the parameter variations in the cost function, as usage of
two variables of different nature in the cost function is not an advisable task.
Due to the lack of theoretical guidelines, the tuning of weighting factors is

a nontrivial process, done mostly by empirical methods.
One of main considerations in MPC is the time delay for digital control
based real time applications. As the application of the optimal voltage vec-
tor cannot be achieve in the same sampling period when it is calculated,
one step prediction is usually employed to solve the time conflicts [15–18].
11.4 Predictive Control Techniques for PMSM

11.4.1 Conventional Model Predictive Torque Control (MPC)
The control objective of the MPC is to directly control the torque and flux
of the PMSM. The MPC that involves the cost function composed of the
errors between the reference and the predicted values of torque and flux
is termed as model predictive torque control MPC [19–21]. The simpli-
fied control circuit of conventional MPC is shown in Figure 11.5. It is
comprised of the torque, flux estimation, and prediction block where the
torque and flux are calculated for the present instant and predicted for the
next instant considering the one step delay, followed by the cost function
minimization block in which the optimal voltage vector that minimizes
the cost function is selected to be applied to the Voltage Source Inverter
(VSI) [22]. The control strategy of the conventional MPC, the cost func-
tion, takes into consideration the flux and torque errors for predicting the
voltage vectors to be applied in the subsequent sampling instant.
The dynamic equations of PMSM in (11.4) and (11.5) are adopted to
predict the value of the stator current itsm+1 for the subsequent sampling
instant (m + 1) based on the stator voltage utsm and the measured current
Tteref
ωstref PI
Cost Function uopt 2-level
PMSM
ωstm ref
Minimization VSI
ψst
ustm
m+2
Tte
Torque/Flux istm
Estimation and
ψstm+2 Prediction
ωstm
Figure 11.5 Control circuit of conventional MPC.

itsm at the present sampling instant, given by Equations (11.6) and (11.7).
From the value of the calculated stator current itsm+1 , the flux and torque are
predicted for the next sampling instant using Equations (11.8) and (11.9).
1
m+1
ied m
= ied +
Led
( − Rtsiedm + ω tsm Leqieqm + uedm )Tspl (11.6)
1
ieqm+1 = ieqm +
Leq
( − Rtsieqm − ω tsm Ledied
m m
+ ueq − ω tsmψ fp )Tspl (11.7)
ψ tsm+1 = ( Lediedm+1 +ψ fp ) + jLeqieqm+1 (11.8)
3 m+1 m+1
Tetm+1 = pψ ts its (11.9)
2
m+1
where ied and ieqm+1 are the d-axis and q-axis current vectors at the (m + 1)
instant, ψ ts is the stator flux at the (m + 1)th instant, Tstm+1 is the torque at
m+1
the (m + 1) instant, and Tspl is the sampling time.

The predicted values of torque and flux at the next instant (m + 1) are
used to calculate the cost function. As the control objectives are stator flux
and torque, they are reflected in the cost function and it is designed so
that the flux and torque at the end of a sampling period is proximate to the
reference value. Based on this reason, the cost function takes the absolute
error difference between the predicted values of the torque and the flux
with their reference values respectively.
Thus, the designed cost function to control the flux and torque errors in
conventional MPC considering the one step delay, is given as:
C MPTC = Tetref − Tetm+2 + w f |ψ tsref | − |ψ tsm+2| (11.10)
T rated
where, w f is the weighting factor [23, 24] given by w f = rated , and
|ψ stref |
ψ
are the reference electromagnetic torque and stator flux, respectively, and
Tetm+2 and |ψ tsm+2| are the predictive torque and flux at the (m + 2) instant.
For the calculation of the values of Tetm+2 ,|ψ tsm+2| in Equation (11.10) with
the consideration of the one step delay and the value of itsm+1 obtained
from Equations (11.6) and (11.7) are used as initial values for the pre-
dictions of the next instant (m + 2). The torque reference is calculated
by a PI controller and the flux reference is taken as a constant value. The
Tetm+2 ,|ψ tsm+2|, and cost function are predicted for all eight voltage vectors.
The voltage vector that minimizes the cost function is chosen as the opti-
mal voltage vector.
The usage of two variables of different nature, torque error, and flux
error in the cost function is not an advisable task. To eliminate this fact,
the weighting factor wf is multiplied with the flux error to match the unit
variation of the parameters in the cost function. The calculation of this
weighting factor is an empirical process. The application of MPC for the
power converters has been kept back because by this weighting factor tun-
ing, it is a challenge for MPC to build an efficient strategy for weighting
factor calculation to improve the effectiveness of the tuning process [25].
11.4.2 Proposed MPC Technique

A variation to the standard MPC to effectively improve the controlling of
PMSM for the orthopaedic drilling application and the merit of MPC are
considered in the proposed work. The basic block diagram of the proposed
MPC is as shown in Figure 11.6.
The merit of including various constraints in the cost function is pro-
posed in this chapter. Thus, the improved cost function includes four
control constraints that aim in minimizing the torque ripple along with
Torque and Flux Cost Function

Inverter & Load
Reference Calculation Minimization block
Torque, Flux and

Current Predition
Block
Figure 11.6 Basic block diagram of proposed MPC.

reduced current harmonics, switching frequency, and limiting the current

from exceeding the maximum value [25–30]. The reduced current har-
monics in turn reduce the flux ripples, the reduced switching frequency
will reduce the switching losses, and the current limiting factor will ensure
that the current value in the device will not exceed the maximum specified
value of the device, thus protecting the patient and the clinical technicians
from power line interferences and other short circuits. The proposed cost
function incorporating the four constraints is shown in equation:
2
 m+2 Led − Leq m+22 m+22 
C=
prop (Tetref − Tetm+2 )2 + w c  ied + (ied − ieq )  + w mCcc (m + 2) + LSwx
 ψ fp 
(11.11)
where wc and wm are the weighting factors, Ccc (m + 2) [31–33] is the cur-
rent limitation constraint, and LSw x is the switching frequency reduction
constraint. In the current limitation constraint, the value of current is con-
tinuously monitored so it does not increase the specified value. If the spec-
ified value is crossed, that term becomes zero, thus minimizing the current
value. The switching frequency reduction constraint does not allow the
changes in two consecutive switching states to be more than one. When
the changes in the switching state exceeds one, that term becomes infinity,
thus the value of cost function for that voltage vector becomes infinity and
that vector will not be selected as the optimal vector. The control circuit of
the proposed MPC is shown in Figure 11.7 [34, 35].
Tetref
ωstref PI uopt
Cost Function 2-level
PMSM
ωtsm Minimization VSI
ref
ψts
m+2
utsm
Tts
Torque/Flux and itsm

ψtsm+2 Current Estimation
and Prediction
itsm+2 ωtsm
Figure 11.7 Control circuit of proposed MPC.

The flow of work in the proposed MPC is occurs as follows: the refer-
ence torque is initialized with a value and the flux reference is calculated
from equation (11.12) [32]. The flux reference calculated using the max-
imum torque per ampere (MTPA) principle improves system efficiency.
2
ref  Leq Tteref 
|ψ | = ψ +  2 (11.12)
ts fp
3 
 pψ fp 
2
From the values received from the PMSM motor, the current, torque,
and flux are predictively computed for the (m + 2) instant. In the proposed
MPC, the acquired stator current from the motor is fed to the cost function
block since the error between the reference and acquired current is the
secondary component in the calculation of the cost function. This concept
of introducing the MTPA technique in current error calculation minimizes
the losses due to increased current in the system [36–38].
The current limitation constraint in the cost function limits the motor
current within the specified values. The cost function is computed for the
eight switching states present in the two-level voltage source inverter and
the voltage vector that gives the lowest cost function value is selected as the
optimal voltage vector and is applied in the next sampling instant. On the
application of the optimal voltage vector, the torque ripple is minimized
in the proposed MPC that in turn minimizes the vibrations of the drilling
unit, thus providing ease of use for the doctors and the technicians and
comfort to the patients [39]. The validation of the proposed MPC with the
claim of reduced torque ripple and minimized current harmonics is imple-
mented in a simulation environment.
11.5 Implementation and Results

The effectiveness of the proposed MPC is compared with the conventional
MPC that uses torque error and flux error in its cost function as shown in
Equation (11.10). The validation is carried in the MATLAB/Simulink envi-
ronment. The system parameters of the motor taken into consideration are
the same as in [7]. A fair comparison is made by designing the external PI
controllers with the same parameters.
11.5.1 Comparative Study of Steady State Performance

of Proposed MPC and Conventional MPC
under Loaded Condition
Figure 11.8 presents the response waveforms for conventional MPC and pro-
posed MPC at 1000 rpm under the load condition of 3 Nm applied at 0.1 sec-
ond. From top to bottom, the waveforms are current, torque, stator flux, and
speed, respectively. The quantitative evaluation of the average switching fre-
quency, RMS value of torque ripple and flux ripple are shown in Table 11.2.
The RMS torque ripple and flux ripple are calculated using the formula [40]:
1 N
K ripple = ∑i=1 ( K e (i ) − K av )2 (11.13)
N
where K = Tte and ψts while calculating torque and flux ripples, respectively,
and N is the number of sampling periods.
10 10
Current (A)
5
Current (A)
5
0
0
–5
–5
4
Torque (Nm)
4
Torque (Nm)
2
2
0 0
0.2 0.2
Flux (Wb)
Flux (Wb)
0.15 0.15
0.1
0.1
1000
Speed (rpm)
1000
Speed (rpm)
500 500
0 0
0.1 0.2 0.3 0.4 0.5 0.1 0.2 0.3 0.4 0.5
Time (second) Time (seconds)
(a) (b)
Figure 11.8 Response of current, torque, stator flux, and speed at 1000 rpm with sudden
load change for (a) conventional MPC and (b) proposed MPC.
Table 11.2 Quantitative comparison between conventional MPC and proposed

MPC.
Method fav(Hz) Flux ripple (Wb) T_ripple(Nm)
Conventional MPC 5.36 0.0066 0.2004
Proposed MPC 3.58 0.0028 0.0859
The waveforms prove that in a very short period, speed of the proposed
MPC settles quickly due to fast torque response. A quantitative compari-
son of the conventional MPC and proposed MPC is shown in Table 11.2.
From the table, it is understood that the proposed MPC gives a torque
ripple of 42.86% and flux ripple of 42.42% of conventional MPC. Thus,
the proposed MPC provides reduced torque ripple and better transient
performance.
11.5.2 Steady State Performance at 50% Rated Speed

Figure 11.9 shows the steady state response of the conventional MPC and
proposed MPC at 50% of the rated speed. The torque and flux waveforms
depict the significant difference between conventional MPC and proposed
MPC. The high torque and flux ripple difference can be seen in the wave-
forms. The main drawback of the DTC drive is more torque ripple and
flux ripple at lower speed, hence the proposed MPC presents overall better
performance.
1 1
Torque (Nm)
0.5
Torque (Nm)
0 0
–0.5
–1
–1
–1.5
0.12
0.12
0.11
Flux (Wb)
Flux (Wb)
0.1 0.1
0.09
0.08
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
Time (second) Time (second)
(a) (b)
Figure 11.9 Steady state response at 50% rated speed for (a) conventional MPC and
(b) proposed MPC.
11.5.3 Steady State Performance at 100% Rated Speed

The steady state response at 100% rated speed for conventional MPC and
proposed MPC are presented in Figure 11.10. From the figure, it can be
seen that the torque and flux ripple are lower in the proposed MPC than
the conventional MPC. The performance of the proposed MPC in terms
of torque ripple and flux ripple is better than the conventional MPC. The
lesser torque ripples in MPC shows the effectiveness of the proposed MPC.
11.5.4 Real-Time Simulation Result Analysis

with OPAL-RT Lab
The minimization in the torque ripple, current harmonics, and flux ripple
of the proposed MPC was validated and the superiority of the proposed
MPC over the conventional MPC was justified in the MATLAB/Simulink
environment. Further validation of the same is executed in the real time
environment in OPAL-RT Lab. OPAL-RT Lab is a real time simulator that
replicates the simulation results similar to the real time environment. It is
completely compatible with the MATLAB/Simulink environment. Hence,
the real time implementation of the proposed MPC and conventional MPC
were performed to further justify the claims of the proposed MPC and val-
idate its implementation in the orthopaedic drilling applications [41–44].
As the real-time simulator performs the simulation considering the
dynamic real time conditions, it gives similar results as implementing the
system in real-time hardware and economically saves time. The real-time
1 1
0.5
Torque (Nm)
0.5
0
Torque (Nm)
0
–0.5
–0.5
–1
–1
–1.5
–1.5
0.12 0.12
0.11 0.11
Flux (Wb)
Flux (Wb)
0.1 0.1
0.09
0.09
0.08
0.1 0.2 0.3 0.4 0.5 0.1 0.2 0.3 0.4 0.5
Time (second) Time (second)
(a) (b)
Figure 11.10 Steady state response at 100% rated speed for (a) conventional MPC and
(b) proposed MPC.
Figure 11.11 Real-time simulator set up.
simulator is widely used and the proposed work is validated in the RT-Lab
environment. The real-time simulator set up is shown in Figure 11.11.
11.5.4.1 Steady-State Response

The steady state response in the real-time simulation of the conventional
MPC and the proposed MPC from standstill to 1000rpm are depicted in
Figure 11.12. In Figure 11.12, the waveforms from top to bottom represent
torque, one phase abc current, and speed. Externally, a sudden torque of
3Nm is introduced in the system. A fall in the speed curve of the proposed
1 5.00V/ 2 5.00V/ 3 20.0V/ 4 50.00ms/ 0.0s Stop 1 5.00V/ 2 5.00V/ 3 20.0V/ 4 50.00ms/ 0.0s Stop
Torque [5Nm/div]
Torque [5Nm/div]
1
Current [10A/div]
Current [10A/div]
2 2
Speed [1000rpm/div]
Speed [1000rpm/div]
3
(a) (b)
Figure 11.12 Steady state response in real-time simulation from standstill to 1000rpm of
(a) conventional MPC and (b) proposed MPC.
1 5.00V/ 2 5.00V/ 3 20.0V/ 4 50.00ms/ 0.0s Stop 1 5.00V/ 2 5.00V/ 3 20.0V/ 4 50.00ms/ 0.0s Stop
Torque [5Nm/div] Torque [5Nm/div]

T
1 1T
Current [10A/div]
Current [10A/div]
2 2
Speed [1000rpm/div] Speed [1000rpm/div]
(a) (b)
Figure 11.13 Start-up responses of (a) conventional MPC (b) proposed MPC.
MPC is seen in the waveform and the system immediately tracks its speed,
revealing robustness in external disturbances. Comparing the conven-
tional MPC and the proposed MPC, the waveforms validate the steady-
state performance of the proposed MPC with reduced torque ripples and
current harmonics.
11.5.4.2 Start-Up Response

The start-up responses of the conventional MPC and the proposed MPC
are presented in Figure 11.13. The waveforms in Figure 11.13 are in order as
torque, current, and speed. The figure shows the start-up responses under
the no-load condition when the motor accelerates from zero to 1000rpm.
The time taken for the proposed MPC to settle at the recommended speed
is lesser than the time taken by the conventional MPC. This validates that
the proposed MPC is suitable for variable speed applications.
11.6 Implementation Analysis

The validation of the simulated and the real time simulated results show
many similarities to the claim of improved performance in the proposed
MPC. Comparing the steady state response of both the results for the pro-
posed MPC, as shown in Figure 11.14, both show a similar resemblance in
proving the effectiveness of the proposed MPC technique. On the intro-
duction of external disturbance, in the real-time simulation response, the
system tracks the speed in no time that the waveform is almost a straight
line, thus depicting the improved performance of the proposed MPC.
The discussed conventional MPC and proposed MPC methods are sim-
ulated and compared and the results are analyzed in the paper. This section
4
Torque (Nm)
2 1 5.00V/ 2 5.00V/ 3 20.0V/ 4 50.00ms/ 0.0s Stop
0
Torque [5Nm/div]
10
Current (A)
Current [10A/div]
5
2
0
Speed [1000rpm/div]
–5
3
Speed (rpm)
1000
500
(b)
0
0.1 0.2 0.3 0.4 0.5
Time (second)
(a)
Figure 11.14 Steady state responses of (a) simulation and (b) real-time simulation.
will analyze the results and it is presented in Table 11.3. Both the methods
belong to the FCS-MPC and have straight forward implementation and
instinctive concepts when compared to conventional control methods like
FOC or DTC. These methods are simple and do not need an inner current
PI controller and an absence of modulators leads to quick dynamics but
variable switching frequencies. The main advantage of these methods is
the cost function and the merit of the model predictive control scheme,
which can flexibly include system constraints easily. Table 11.3 provides
a quick picture on the advantages of the proposed MPC over the conven-
tional MPC.
A quantified explanation of the parameters discussed in Table 11.3 are:
the dynamic simulation response describes the lag of the conventional
MPC to track the speed on introducing the external torque, whereas in the
proposed MPC, the system tracks the speed in less than 0.1 seconds. The
torque ripple values given in Table 11.2 depict the performance improve-
ment in the proposed MPC over the conventional MPC with reduced
torque ripple. The current harmonics values given in Table 11.2 are also
reduced for the proposed MPC when compared with the conventional
MPC. Thus, the effectiveness of the proposed MPC technique is clearly
depicted from Tables 11.2 and 11.3.
Table 11.3 shows a detailed picture about the conventional MPC and
the proposed MPC. From the simulated responses, it can be observed that
the waveforms that the conventional MPC produces higher torque ripples,
Table 11.3 General comparison on conventional MPC and proposed MPC.

Features Conventional MPC Proposed MPC
Dynamic Response of Lags Quick
Torque
Steady State Behaviour Low torque ripple Better response of
for Torque, Stator torque and current
Flux, and Current
Start-up Responses Takes longer time to Settles quickly
settle
External Disturbances Variations are sensed Variations are sensed
in torque ripple and but settle quickly so
take time to settle that the vibration will
that will produce not be felt during the
sudden vibrations drilling application
during drilling
Current THD Higher Lower
Regulators Torque and flux Torque as primary and
regulators current as secondary
regulator
Parameter Sensitivity Stator inductance, Neither
rotor inductance
Control Tuning Cost function which Cost function that
minimises the minimizes the torque
torque error and error and considers
the flux error MTPA for optimal
voltage selection
Merits Much preferred in Preferred in systems
high power control that need improved
overall efficiency
whereas the proposed MPC shows good torque and current response. As
the main comparison validates the claim of reduced torque ripple and the
vibrations in orthopaedic drilling applications, the proposed MPC pro-
vides effective control of the torque ripple as the system settles quickly
even after the external disturbance. As the drilling of bones is prone to
various external disturbances, the system should settle instantly so that the
disturbances should not affect the technicians and also the patients, as even
a small deviation can result in huge complications for the patient.
11.7 Conclusion
Many types of control strategies have been designed by the sustained
research and experimental validations in the area of power electronics for
different electrical machines in the past three decades. MPC stands above
all the conventional control strategies of electrical drive systems due to
its dynamic performance and strong, robust characters. MPC, meritori-
ous of its intuitive concept of design, fast dynamics, and torque response,
is becoming the trend of electrical drive systems in the upcoming years.
The steady state and dynamic performances of the conventional MPC and
the proposed MPC schemes are analyzed. From the simulated results, it is
evident that the proposed MPC have better performances in both steady
and dynamic conditions than the conventional MPC. Maximum torque
per ampere tracking is obtained in the proposed MPC technique, leading
to high electrical efficiency. The speed and the dynamic state simulations
also reveal the quick settling of the system after the transients. Thus, for
drilling applications that need higher precision and efficiency for applica-
tions that deal with lighter bones with precision, the proposed MPC con-
trolled PMSM can be considered as an effective drilling technique. This
paper contributes a suggestion of effective MPC controlled PMSM for the
drilling electrical drive systems.
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drives. Journal of Vibration and Control, 2020.
12
High Precision Drives for
Piezoelectric Actuators Based
Motion Control Microsystems
D. V. Sabarianand* and P. Karthikeyan
Department of Production Technology, Madras Institute of Technology,

Abstract
Piezoelectric actuators (PEA’s) are progressively used for their inborn qualities
of dependability and high accuracy execution. Piezo-based motors were used in
nanoliter infusion pumps and optical-position systems. These motors needed to
arrange a nanometer objective with step rates in MHz reach and inconceivable
detail in an appealing motor approach. The power of these motors can go from
nanonewtons to around one newton (1N), however, a few motors can accomplish
several newtons and motor weight, for small ones, is in the under 10g territory.
These are by and large not “high-power” motors; however, they should be used
for objective applications. Piezo motors are regularly worked as a strain check
during a criticism circle for the extra exactness that controls a shut circle circuit.
Not exclusively are the essential material science of the Piezo motors, altogether
different from that of attractive motors, as the drive prerequisites are additionally
extraordinary. An electrical circuit makes acoustic or ultrasonic vibrations in the
Piezoelectric material, which produces direct or revolving movement. The Piezo
material needs an electric field provided by a voltage differential over the mate-
rial. Contingent upon the size of the motors, this voltage can be as low as 50 V
or as high as 1000 V or more basic Piezo ringers and vibrators ordinarily require
just around 25–30 V. There are a few difficulties in the planning of the driver cir-
cuits. They are conceivably hurtful high voltages, utilization of proper protection,
and wire steering, just as in the killjoy attributes. In contrast to the MOSFET/
IGBT changes used to the stream of current in attractive motors, Piezo motors
are typically determined by a standard operational speaker helped by high-voltage
367
semiconductors on their yields or application in explicit to high voltage operation

amps. At that point, the attractive motors have an exceptionally inductive burden,
so the drive circuit must handle the current in a surge, inductive kicks, and other
inductive burden ascribes. While the Piezo motor is profoundly capacitive, the
driver operation amp must be fit for giving the required voltage into a heap of 1000
pF (picofarads) or the more yet, stay stable, which requires a unique yield stage
configuration regardless of whether the operation amp can undoubtedly show the
high voltage.
Keywords: Power drives, Piezo motor, switching methods and voltage regulator
12.1 Introduction
Piezoelectric motors (PM) are commonly used in the field of miniature/
nanopositioning systems [1–3], complaint mechanisms [4–6], miniature
fluidic applications, miniature valves [7], and miniature pumps [8–10]
for biological applications. PEA are the appropriate decisions for these
applications because of the accompanying qualities, for example, actua-
tors comprise material viable with cryogenic conditions and furthermore,
Piezoelectric impacts do not meddle with attractive fields. The impedi-
ments of piezo motors (PM) are the natural nondirect qualities, for exam-
ple, hysteresis wonder shows the multi-esteemed planning esteems and for
a given information signal, the yield are unique if the set of experiences
yield states.
The hysteresis nonlinearity initiates a serious open-circle situating mis-
take as high as 10-15% of the stage travel range [11–15]. At that point, the
Piezoelectric (PZT) materials show a killjoy impact, i.e., the material keeps
on extending for quite a while after charging. Correspondingly, the mate-
rial does not quickly revisit the underlying strain level after release [16–20].
The contemplations for driving the Piezo motors is speaker transmission
capacity, current and force constraints, recurrence reach, and information
signal voltages for low and superior applications [21]. The impediments
of utilizing transfer speed while driving the Piezo motors (PM) utilizing
Piezoelectric drives involves high yield impedance, the presence of a post
in the voltage-input circle because of yield impedance and burden capac-
itance, inadequate flow limit because of intensity scattering and high link,
and connector inductance [22, 23]. In this section, the various types of
Piezo motors dependent on the working rule and inward setup and appro-
priate drivers to drive such motors are examined.
The Piezo motors (PM) can be grouped as dependent on the movement
type, input recurrence, stator and rotor coupling, and scale. At that point,
Drives for Piezoelectric Actuators 369
again rotational and straight motors can be arranged dependent on the

working rule, revolving Piezo motors as ultrasonic motors with contact and
non-contact type motors. The contact type motors can be named as large
scale and miniature motors. The direct motors have a working standard
of semi-static motors with operational system types, for example, ventur-
ing and inertial moving. At that point, dependent on the stator setup and
development, the motor is sorted as a plate, ring, chamber, square cylinder,
bolt cinched, reinforced, or non-fortified [24]. At that point, the heading
of pivot is unidirectional or bidirectional. The excitation conditions were
single actuator and twofold actuator. At that point, the actuator vibration
modes, are exam twisting, longitudinal, torsional, and mixture. The infor-
mation signal wave-type is a standing wave or continuous wave. The PZT
material sorts either as a Piezoceramic or the single precious stone. The
Piezoelectric (PZT) material setup is either mass, slender film sandwich,
or langewin [25].
12.2 Driving Methods of PEA

The various electronic drivers were used to drive the PEA based on the
internal configuration and physical principles of the actuator. An intelli-
gent driver is normally used for driving the PEA-based complaint mech-
anism and micro/nano positioning systems. Table 12.1 listed the Piezo
Drives and controller which are widely used to drive the piezoelectric
motors in various high-power applications. The disadvantage of this type
of driver is that the input signal bandwidth is quite high. The challenging
task is the reduction of noise that occurs to the driver during operation
time.
12.3 Driver Circuits for Driving PEA in High Voltage

Applications
The driver circuits for driving the different kinds of the Piezoelectric actu-
ator are Piezo benders, ultrasonic, direct, and rotating.
MAS6240 is a Piezo driver IC intended to make a multi-tone sound
dependent on a charge. It is a high proficiency, simple to utilize, and min-
imal effort IC ideal for battery-driven gear or other low voltage applica-
tions where a high immediate sound weight is required. MAS6240 can
drive yields up to 18 VP-P from a single 3 V flexibly voltage, as shown in
Figure 12.1. An information voltage enhancement factor can be chosen
Table 12.1 Various types of drives for driving Piezoelectric actuators.

Max Max
Actuator Precision voltage frequency
S. no. type Driver (Microns) (V) (Hz)
1 Linear & Piezo 5 48 2500
Rotary Controller
2 Linear & Motion 5 48 2500
Rotary Controller
3 Linear & Piezo 5 48 1500
Rotary Controller
4 Linear Piezo Mike 5 24 2500
Piezo Driver
Actuator
5 Linear Piezo Driver 12 24 1300
Piezo
6 Linear & Piezo Driver 5 24 60
Rotary
7 Linear Low Noise 2 150 180 kHz
Piezo Driver
8 Linear Piezo 2 in closed 150 180 kHz
Controller loop
with Strain
Gauge
Feedback
9 Linear & BD Dual 5 150 20 kHz
Rotary Channel
Driver
10 Linear Miniature High 5 100 200 kHz
Voltage
Amplifier
11 Linear & High 5 200 200 kHz
Rotary Performance
Piezo Driver
12 Rotary Miniature 5 60 20 kHz
Piezo Driver
13 Linear Micro Piezo 5 100 20 kHz
Driver
0.1uF 0.1uF
CP1 CN1 CP2 CN2
VIN (3V)
VOUT
1x/2x/3x Charge Pump
0.1uF Oscillator 0.1uF
1MHz
EN1
Short Circuit
Control Protection
EN2
Logic
DIN VO1 1kΩ...2kΩ

Output
Protection
900k (optional)
Pull Down PIEZO
Resistor SOUNDER
VO2
MAS6240C2
GND
Figure 12.1 Driver circuit of MAS6240C2 [26].
as 1, 2, or 3. The yield is regularly a single-mode or differential mode

[27]. The inductor-less plan causes essentially less unsettling influence
on the encompassing circuits, settling on an ideal decision for pulse
screens and other sensitive designs. Only four small value capacitors
are required notwithstanding a sound component. The usage of small
capacitors likewise makes this arrangement more solid, in contrast with
an inductive arrangement utilizing a hefty curl that can slow down if
the gear is dropped. MAS6240 can additionally can be used in different
applications [28].
The highlights of this IC were low force inductor, less arrangement, low
voltage activity of at least 2.4 V, low current utilization, three-stage volume
change, one wire sound and closure control, high productivity and low
outside part control. The uses of such drivers are pulse screens, driving
PCs, energy metres, smoke alarms, remote sensors, electronic paper, and
caution frameworks [29].
The double full extension Piezo driver is broadly utilized for the pro-
grammable control of the straight or rotating actuators. The LT3572 might
be an exceptionally incorporated double Piezo motor driver equipped
to drive driving two Piezo motors at up to 40V from a 5V gracefully, as
shown in Figure 12.2. Each Piezo driver is regularly autonomously turned
on or off close by with the lift converter. The lift controller includes a del-
icate beginning ability that restricts the inrush current at fire up. The lift
10µH VOUT
VIN
30 V
3V to 5V 576k 50mA
100k VIN SW VOUT
15pF 10µF
SHON
FB
SHONA
SHONB OUT
4.7k PWMA A
LT3572 OUTA
PWMB
SYNC
PGOOD
OUTB
RT
OUTB
SS
42.2k GND
10nF
Figure 12.2 Dual full bridge Piezo driver [30].
controller exchanging recurrence is about by an outside resistor or the

recurrence and is frequently synchronised by an outer clock [31]. A
PGOOD pin shows when the yield of the lift converter is in guideline and
thusly, the Piezo drivers are permitted to begin to exchange. The highlights
of the LT3572 Piezo driver are 2.7 V to 10 V Input Voltage Range, 900mA
lift converter, double full-connect Piezo drivers, programmable changing
recurrence from 500 kHz to 2.25 MHz, synchronise up to 2.5 MHz, deli-
cate beginning, separate empowerment for each Piezo driver, and a boost
converter. The applications of a dual full bridge Piezo driver for a linear
or rotary Piezo motor, ultrasonic Piezo motor, and Piezo based actuation
mechanism [32].
The LT3469 is a transconductance (gm) speaker, which will drive yields
up to 33V from a 5V or 12V flexibly. An inner exchanging controller pro-
duces a supported graceful voltage for the gm enhancer. The enhancer can
drive capacitive burdens inside the scope of 5nF to 300nF. The slew rate is
restricted simply by the greatest yield current. The 35V yield voltage ability
of the exchanging controller, close to the high flexible voltage of the speaker
joins to allow the wide yield voltage range expected to drive a piezoceramic
microactuator, as shown in Figure 12.3. The LT3469 exchanging control-
ler switches at 1.3MHz, permitting the usage of small segments. The yield
capacitor can be as little as 0.22µF, sparing space and cost versus elective
arrangements. The apparatus of this driver are Piezo speakers, Piezo micro-
actuators, and varactor inclination [33].
47µH
5V or
12 V 1µF 3 5
16V VIN SW 6
VCC
453k
FB 2 0.47µF
50V
16.5k
4
9.09k GND
7
+IN
+ 1
8 OUT VOUT
OUTPUT –IN 1V to 33V
0V to 3V
PIEZO
– 10k
ACTUATOR
5nF < C < 300nF
100k
Figure 12.3 Piezo microactuator driver [30].
The highlights of the microactuator driver are the momentum limit

at ±40mA ordinarily, input regular mode range: 0 V to 10 V, yield
voltage range: 1V to (Vcc – 1V), differential increase stage with high
impedance yield (gm stage), quiet ebb and flow (from Vcc), 2ma and
emptied increases to 30,000 normally. At that point, the exchanging
controller creates Vcc up to 35 V, a wide working graceful range of 2.5
V to 16 V, high exchange recurrence of 1.3MHz, inside Schottky diode,
small outside parts, and a current mode switcher with interior remu-
neration [34].
A disadvantage of Piezo-based haptics has by and large been the
unusualness of the course of action. Ordinary Piezo-based plans have
used discrete fragments to execute the total material input framework
and the extra discrete segments incorporate a microcontroller, flyback
lift or charge-siphon microcircuit, flyback transformer or inductor,
random resistors, capacitors, diodes, and semiconductors, as shown in
Figure 12.4.
Differentiation and DC motor-based haptics require least or no external
portions. A single chip strong haptic course of action just like the MAX11835
has a couple of central focuses over the more settled discrete plans: more
unobtrusive printed circuit board (PCB) impression, lower power, lower
bill-of-materials (BOM) cost, and programming tasks. Couple this with
DIGITAL ANALOG BOOST

POWER POWER POWER
T1 D1
DVDD AVDD BVDD
PIEZO
LOADS
SCL SW
SEC
SDA
R1
FB
MAX11835
APPLICATIONS IRQB R2
PROCESSOR
G1
TRIGB M1
S1
RESETB DGND
R3
AGND
Figure 12.4 Monolithic high-voltage haptic actuator control driver [35, 36].
the situation of wellbeing overseen by Piezos and likewise, the MAX11835

transforms into a superior response for flexible handheld devices.
The DRV8662 is a Piezo chip haptic driver with a 105 V switch
empowered with a power diode and a totally differential intensifier,
as shown in Figure 12.5. This adaptable device is helpful for driving
both high-voltage and low-voltage Piezo haptic actuators. The data is
reliable for differential and single-wrapped up. The DRV8662 supports
four GPIO-controlled developments: 28.8 dB, 34.8 dB, 38.4 dB, and 40.7
dB. The boost up voltage is related with using two external resistors and
as necessity appears to the lift current is reducing through programma-
ble through the REXT resistor. The boost up converter arranging will
not allow the interest on the deftly current to beat the limit set by the
REXT resistor and along these lines, the DRV8662 is proper for indus-
trial application [28].
The features of DRV8662 are drives up to 100 nF at 200 VPP and 300
Hz, drives up to 150 nF at 150 VPP and 300 Hz, drives up to 330 nF at 100
VPP and 300 Hz, and drives up to 680 nF at 50 V and 300 Hz with differ-
ential yields. A boost up converter having features of adaptable boost up
voltage, adaptable repeating design cut-off, joined power FET and diodes,
no transformer required, an energetic beginning season of 1.5 ms, wide
effectively voltage level of 3.0 V to 5.5 V, 1.8 V practical progressed sticks,
and warm security.
VBAT
L1
CBOOST
Boost
Converter R1
CPUMP
REXT
DRV8662
R2
IN+ + Piezo
Gain
– Actuator
IN-
EN
GAIN0
GAIN1
Figure 12.5 Piezo haptic driver with boost converter [21, 29].
A standard starts up a period of 1.5 ms makes the DRV8662 an ideal

Piezo driver for rapid haptic responses. Warm over-burden assertion
shields the contraption from being hurt when overdriven. The employ-
ments of the DRV8862 are PDAs, tablets, obliging PCs, consoles, mice,
and contact associated with contraptions. Piezoelectric motors might be
a straight motor with a bidirectional new turn of events. It used to scour
to hold the armature while a voltage is skewed to turn the Piezoelectric
material and move the armature. The voltage by then is immediately taken
out considering the way that the material springs back and it breaks far off
from the armature and re-appearances of its zero position, the armature a
few micrometers further along its track. Rehash this at a kilohertz rate and
for an astonishing number of limits. While the total of the movements is
little, following a couple of moments you may see that the armature has
moved in the event that you look circumspectly.
There are two drive waveforms, one for forward and in this way, the
other talks a saw tooth waveform with a moderate direct rising followed by
a fiery fall and its improvement with a fast trip and moderate straight fall,
as shown in Figure 12.6. This was finished utilizing a movement amp tri-
angle-wave oscillator at 1 kHz, with diodes exchanged to stimulate either
R2 R3 +200 V
499k 499k
R4
16.5k
C1 +200 V
C2 10 pF R5
10 pF 16.5k Q1
ZVN4525G
R6 R8 Piezo
+12 V 16.5k D1 D2 49.9 element
V+ 0 to
R7 +12 V 150 V
– SMAZ16-13-F
1.5k
Input + IC1 Q3 Q2
0 to 10 V AD8065AR ZVN4525GTA ZVP4525G
R1
66.5k
Figure 12.6 Piezoelectric motor using Low-Voltage Op Amp [37].
the rising or falling edges for about 5% of the cycle. The driver’s significant
data transmission is just 10 to 15 kHz. The issue is the voltage. Luckily, it
is unipolar. Shockingly, it is +150 V (top). The destined current is minute.
It should be crucial enough to charge and move the 20-nF Piezo part. An
evaluation utilizing charge move (Q) as follows
Q = It = CV (12.1)
where t = 1 ms, C = 20 nF, yield voltage V = 150 V, and in like way,
I = CV/t = 3 mA (12.2)
A 600-mW help converter is regularly used to switch the +12 V up

to +200 V with a 3-mA load need. The direct circuit is used as move-
ment amp reviewed at any rate to 200 V. While some advancement amps
are unguarded with this voltage rating, they are normal for high-current
applications and are rich. The circuit inside the figure is clearly more
moderate and kept up on an ordinary improvement amp utilized as a
non-upsetting intensifier. The purpose of union of the circuit is the cur-
rent impression of R7, N-channel FET Q3, and plan related R4, R5, and
R6. (The explanation behind utilizing three resistors in the course of
action is clarified underneath). The voltage at the lower segment of R4 to
R6 (the Q3 channel) starting now has the predefined voltage swing at any
rate of high impedance. Several free FETs go about as lovers to separate

the yield impedance and lift current yield. The negative information is
given by procedures for R2 and R3, close by the information transmis-
sion restricting C1.
There are two or three subtleties to the circuit. If something happened to
the Piezo engines, similar to the client shorting it, Zener diodes D1 and D2
would ensure the FET areas. The current-reflect high-side check given by R4
through R6 is parted into three certain contraptions to deal with the force
levels so that surface-mount (SMT) resistors are once in a while utilized. The
information obstruction made out of R2 and R3 is major for two gadgets to
scale back the voltage coefficient of a square. This is reliably a truly powerless
impact, where a piece’s check genuinely changes somewhat at higher volt-
ages. There is a little evaluation capacitor direct on the action amp to give
unwaveringness. Without it, the parasitic capacitances (most unmistakably
the Miller capacitances Cdg and in a like way the Piezo’s capacitance) would
cause enough stage movement for the action amp to influence. Another issue
would be the colossal post accomplished by an absolutely capacitive Piezo
part. By taking the appraisal plainly from the wellsprings of Q1 and Q2,
resistor R8 would add a more deterministic post to the store and enhances
circuit safety. These are a pattern of the undeniable ICs is used in driving
the Piezo actuator shutdown and preventive circuit. It relies on the voltage
rating, load limit, and driver IC. These are a bit of the driving circuits for
driving the Piezoelectric incitation based structures used for the industrial
applications [23, 38].
12.4 Different Types of Power Supply Used

for Driving the Piezo Driver
Two trails that need a force flexibly and the two of them have an alternate
prerequisite that should be met. SiC needs a controller that brings down the
voltage starting from the battery to 10 V and piezomotors requires a higher
voltage, from the battery level to 48 V to run their motors. Understanding
the prerequisite is key to ensuring that the force flexibility is working appro-
priately and does not influence different examinations on the satellite.
The prerequisite from SiC are:
1. 10 V yield
2. 10 mA yield
3. Keep its voltage in any event when the temperature is rising
and when the converter is influenced by radiation
4. Stable yield and quick responses to minor departure from

the information and yield
5. Have the option to kill on and the controller utilizing a
microcontroller
The 10 V and 10 mA yields are for providing enough capacity to the

electrical hardware so the trial begins. The 10 V power line will be used
for the semiconductors to begin so they can be estimated so the informa-
tion can be sent back to earth. The low contrast between the battery and
controller makes this a decent contender to use a straight advance down
converter. It is imperative to take safety efforts with the goal that no other
hardware get influenced by the converters. For instance, if the converter
quits working, the investigation will quit working. EMI will influence the
hardware, thusly it is significant that the converter will not change its con-
duct from these burdens. Ensuring that the yield is steady and not get-
ting huge variety is essential for this application so that there are no huge
changes in the hardware around the semiconductors. This may influence
the solidness of the entire hardware. Without this steadiness, the force flex-
ibility can get flimsy and harm the hardware of the investigation or more
regrettable, the satellite. The tests have explicit occasions when they should
be dynamic. This will be constrained by the on-board PC by closing down
the force flexibility. Piezo LEGS motors have prerequisites are:
1. 48 V yield
2. 15 mA yield
3. Safety effort as a circuit on the info
4. Ready to kill on and the controller used a microcontroller
5. Yield wave ought not to be higher than 0.3 V
The voltage and current rating 48 V and 15 mA are expected to control

the motors. There is a need to ensure that the force flexibility does not
influence the motors with current/voltage spikes so the motors get pulver-
ized and similarly, as with SiC, you ought to have the option to close down
the controller. The wave should have been as low as could reasonably be
expected so the current is as near a DC current, in any case, the far-reach-
ing influence can deliver shakiness in the circuit [21, 23, 26].
A. Choosing the SiC in Space DC-DC Linear Converter

In view of the necessity, a direct controller is most appropriate as the
force gracefully for SiC as the progression down is low, simpler to con-
struct, is steadier, and has a similar closure highlight as the exchanging
converter. Looking for the converters is done at Texas Instruments and

Linear Technology as they are probably the greatest makers of coordi-
nated circuits by Kista [24]. Utilizing LTspice, the circuits were repro-
duced to ensure that the yield is right and that the circuit is steady and
is functioning as expected. The straight converter is more proficient
as the progression down levels are lower, which improves it to make it
appropriate for this application. The most extreme contribution from
the battery on the satellite is 16 V and the effectiveness of the battery
is given by
Vout 10
= = 0.625 = 62.5% (12.3)
Vin 16
The exchanging converter has a superior proficiency, however as the exe-

cution of the trial is in space, fixes are not possible if something is fizzling.
Keeping the commotion on the circuit is a higher need so a straight con-
verter is a superior decision. So, the direct converter is a vastly improved
methodology as long as the warmth dispersal is worthy. The circuit board
that is being used on CubeSat is small so it is significant that the converters
are small. Additionally, the SiC tries to need space for their test circuits.
As the direct converter needs not many outer segments, this will bring
about a more modest space utilized on the circuit board contrasted and the
exchanging converter that needs more outside segments for making the
circuit steady and filling in as expected. In view of the prerequisite, looks
for the correct force supplies started at the greatest electronic organiza-
tions, Texas Instrument and Linear Technology [39].
With the known sources of info and yields, these were placed in around 10
direct controllers at every site that could be used. However, checking against
different necessities just 2-3 met those. At long last, the necessity that had the
most noteworthy need was the means by which enormous force gracefully
was as the objective is to have a small converter as could be expected under
the circumstances. The converter that in the end was chosen was the LT3062
from Linear Technology as it was small and had low peaceful current. The
subsequent stage was to check the circuit with determined qualities on the
electrical parts from the datasheet and with those qualities reproduce how
the converter acts [22, 23, 38].
B. Choosing the Piezo LEGS DC-DC Boost Converter

Choosing the right boost converter relies upon factors, for example, volt-
age input, voltage/current yields, the security of the circuit, attributes of
the converter, and the proficiency of the converter. Making a point to meet
the prerequisite of every one of these factors is basic for picking the right
converter. As the direct converter is generally used as a Buck converter,
the Boost converter should be an exchange converter. Both SiC and MIST
request that the converter should have the option to close down so the bat-
tery will not get released or to spare force. The closure highlight is expected
to close down the investigation, if necessary, for instance, the examinations
comes up short [40]. At that point, the OBC (On-Board Computer) must
have the option to close down the investigation if this happens. Another
component is to have the option to have both Boost and single finished
essential inductor converter (SEPIC) design so both the arrangements of
the converter can be tried to explore what setup is most appropriate for
the Piezo motors with respect to security and solidness. Sepic is a more
sheltered design of a Boost converter on the grounds that there is a capac-
itor between the inductor and diode. Sepic design is more secure as the
capacitor stops the information voltage to arrive at the yield when the con-
verter is closed down. The proportion of information versus yield voltage
is so high and that the Piezo try needs a Boost converter and it would be
prescribed to use an exchanging controller. In a field application, motors
from Linear Technology found that the most appropriate Boost converter
was the LT8570. It was little enough to fit the board and was additionally
suggested by the Piezolegs group and had all the essential attributes for
their necessity [30].
12.5 Different Types of Voltage Regulator Used

for Driving the Piezo Driver
Different types of voltage controllers were used in the piezo drivers, rely-
ing on the application for driving the piezoelectric activation-based instru-
ment and frameworks. Small DC motors are being tested by a scaled-down
Piezoelectric motor said to have numerous focal points over electromag-
netic machines. The Elliptic motors, created by a Siemens, turn off and
are supposed to be more modest, all the more remarkable, less difficult,
calmer, simpler to control, and possibly less expensive than ordinary DC
motors. Albeit Piezoelectric motors are not new, past plans have required
exactness development and high working voltages, making them costly.
The new motors (above) work from a 3-6 V DC flexibly, have a less difficult
development with only three moving parts, do not need basic resistances,
and are considerably less expensive [41].
A piezoelectric part makes vibrations at up to 100 kHz that move a

bar or turn a wheel. According to Elliptic, the motor checks one-twelfth
as much as an equivalent electromagnetic motor and is one-fifth of the
size. It need not waste time with a gearbox, as its speed is controlled
electronically using a third similar number of electronic portions as
a customary small DC motor controller. Elliptic cases that the devel-
opment control is indistinguishable from that of all more exorbitant
stepper motors. The fundamental motor creates straight development
at speeds up to 30cm/s and forces of up to 1 N or higher if a couple
of motors are used together. To achieve a rotational turn of events,
the motor creates direct development at the edge of a wheel with the
rpm worth and power spoke by the wheel’s separation over. From the
start, the motor will have a relative expense to customised DC motors.
Applications are cooling vents, and PC sections. The motors are likely
going to be particularly appealing where space is confined, where dis-
turbance is an issue, or where moderate or especially controlled devel-
opment is required [22, 42].
The voltage guideline assumes an essential function in driving the piezo-
electric incitation based components and frameworks. There are different
strategies to consolidate the various kinds of voltage guideline methods.
The piezoelectric component resembles a capacitive burden (once more,
as opposed to the inductive heap of motors and its loops), so the voltage
driver must be intended for supporting capacitive burdens without wor-
rying about for wavering or solidness issues. This heap may run as high
as 1000 nF. Piezo actuators offer special and convincing points of interest
in nanometer goal and rapid applications. To get the most extreme execu-
tion while keeping away from issues, in any case, Piezoelectric qualities
should be thought of. Pulling, shear, and torsional powers can harm the
PZT fired. Standard PZT pottery is restricted to the most extreme working
temperature of 150°C PZT and earthenware production must be shielded
from stickiness or liquid tainting like other electric materials and actuators
[34, 43–46].
The high-voltage support yield voltage Vbst is used to effortlessly
support the Programmable Current-mode Output Stage and the Level
Shifter. This Level Shifter gives a second, lower level power deftly Vls.
The information signal FPZ picks about the trading repeat of the driving
voltage and thusly, the evacuation heading of the piezoelectric actuator.
In the authorized Dual-Polarity Clamp, the deviation among Vbst and
Vls describes the voltage levels made to drive the piezoelectric actuator,
given by
Vls − Vbst FPZ > 0

Vdrive =  (12.4)
 Vbst FPZ = 0
An after integrator produces a normal incline mistake dependent on the

individual slant blunders during a few exchanging periods. This strategy
guarantees high mechanical strain security and overemphasizes into the
Piezoelectric actuator [5, 21]. There are different types of voltage regulators
used for the Piezo drivers, including linear voltage regulators and switch-
ing voltage regulators.
A. Linear Voltage Regulator

Linear voltage controllers utilize the standards of voltage dividers to change
the voltage at their contribution to the ideal voltage at their yield. They
utilize a criticism circle that naturally changes the opposition in the frame-
work to counter the impact of variation in the heap impedance and input
voltage, all to guarantee the yield voltage is kept constant. Typical usage of
direct voltage controllers includes the utilization of FETs as one side of a
voltage divider with an input circle associated with the door of the semi-
conductor, driving it as needed to guarantee consistency in the yield volt-
age. While this utilization of semiconductors as resistors helps rearrange
the plan and usage of direct controllers, it contributes to a great extent to
the shortcomings related to the controllers. The explanation behind this is
that the semiconductors convert the overabundance of electrical energy
(voltage distinction between the information voltage and the yield voltage)
to warm, prompting power misfortune because of warming in the semi-
conductors [47].
In circumstances where the voltage at the info or the heap current at
the yield is excessively high, the controllers could produce heat levels that
may prompt its breakdown. To moderate this, fashioners typically utilize
heat sinks whose size is controlled by the measure of current (capacity)
to be drawn through the controller. Another point worth discussing for
straight controllers is the requirement for the voltage at the contribution
to be more noteworthy than the voltage at the yield by a base worth called
the drop-out voltage. This voltage esteem (ordinarily around 2 V) fluctu-
ates among controllers and is at times a significant wellspring of worry for
creators chipping away at low force applications because of intensity mis-
fortune. As a path around this, utilization of a kind of straight voltage con-
troller called an LDO (low-dropout) controller, occurs as they are planned
with the capacity to work with as low as 100 mV distinction between the
information and yield voltage. Some famous instances of direct voltage

controllers incorporate the 78xx (e.g., L7805 (5v), L7809 (9V)) arrange-
ment of voltage controllers [48].
B. Switching Voltage Regulator

Despite the fact that they include a more unpredictable plan and require
more partner segments to work, exchanging voltage controllers are
super-proficient controllers used in situations where power misfortune,
as in straight controllers, cannot be overlooked. The voltage guideline
system in exchanging voltage controllers includes quickly exchanging a
component associated in arrangement with an energy stockpiling segment
(capacitor or inductor) to occasionally intrude on the progression of the
current and change the voltage from one incentive to the next. How this is
done relies upon the control signal from an input system like the one used
in the controllers [49].
Dissimilar to straight voltage controllers, the exchanging component is
either in a completely directing or turned off state. It disperses no force
and permits the controller to achieve a significant level of proficiency past
that of the direct controllers. A fundamental execution of exchanging a
voltage controller utilizes a “pass semiconductor” worked either at its cut
off or soaked state as the exchanging component. At the point when the
pass semiconductor is at its cut off point, no current courses through it,
as such no force is dispersed, yet when it is in the immersed express an
insignificant voltage drop shows up across it joined by the scattering of
a modest quantity of intensity with the greatest current being sent to the
heap. Because of the exchanging activity and the energy spared during the
cut off express, the proficiency of an exchanged controller is typically of
70%. The exchanging and PWM-based control give a considerable amount
of adaptability that permits changing voltage controllers to work in various
modes and exist in different kinds, including:
• Buck Switching controllers

• Boost Switching controllers
• Buck/Boost Switching Regulators
B.1. Buck Switching Voltage Controllers

Buck switching controllers, otherwise called venture down controllers,
convert the high voltage at their information terminals to a lower volt-
age at their yield terminal. This activity resembles that of direct controllers
apart from the way that the buck controllers work at a more serious level
of effectiveness. A picture delineating the game plan of segments in buck

controllers is given underneath.
B.2. Lift Switching Voltage Controllers

Lift switching controllers, otherwise called venture up controllers, can
change low voltages at their contribution over to a higher voltage at their
yield. The design is one of the significant contrasts between direct control-
lers and exchanging controllers, as no guideline is experienced if the volt-
age at the contribution of straight voltage controllers is more prominent
than the voltage needed at their yield. A circuit showing help exchanging
voltage controllers is given beneath.
B.3. Buck/Support Exchanging Voltage Controller

A buck/support controller consolidates the qualities of the two controllers
above. It can give a fixed yield voltage independent of the distinction (+ or
-) between the information and yield voltage. They are valuable in battery
applications where the voltage at the information, which might be higher
than the yield voltage towards the start, diminishes to a level beneath the
yield voltage after some time.
C. Selecting the Correct Voltage Controller

Choosing the correct voltage controller for your undertaking is typically
not an issue of choosing between direct or exchanging voltage controllers.
Picking between the two should be possible by essentially considering their
advantages and disadvantages and choosing which one best suits you. In
any case, other explicit properties of the controller (either exchanging or
direct) should be checked to guarantee it is an ideal fit for your task.
C.1. Yield Voltage (or Voltage Range)

This is likely the primary thing to pay special mind to in a controller.
Guarantee the yield voltage (or voltage scope) of the controller coordinates
the necessary incentive for your application. For certain controllers, outer
segments might be needed to hold the yield voltage consistently at your
ideal voltage level. The entirety of this ought to be affirmed before elastic
stepping a controller for your undertaking.
C.2. Yield Current

Voltage controllers are planned in view of explicit current appraisals.
Interfacing them to a heap with current prerequisites that are more note-
worthy than their present rating could prompt the controller being harmed
or the heap failing. This is significantly more significant on account of
straight voltage controllers since the current directly affects the force mis-
fortune. Continuously guarantee your controller of decision can withstand
the forthcoming burden current.
C.3. Input Voltage Range

This alludes to the passable scope of information voltages upheld by
the controller. It is normally determined inside the datasheet and as an
originator, it is essential to guarantee that the conceivable information
voltage for your application falls inside the reach. One mix-up most
junior originators make around this is to zero is on the greatest infor-
mation voltage, just overlooking that, the input voltage underneath
the predefined least voltage could prompt guideline blunders, partic-
ularly on account of straight controllers. Realizing these qualities will
assist you with assessing the conditions under which the controller will
flop either because of inordinate warmth being created on account of
straight controllers.
C.4. Working Temperature Range

Characterized in many datasheets as the surrounding temperature (Ta)
or the intersection temperature, the working temperature range is the
scope of temperature inside which the controller capacities appropriately.
In more explicit terms, the intersection temperature, for the most part,
alludes to the most noteworthy working temperature of the semiconductor.
Interestingly, the encompassing temperature alludes to the temperature of
the climate around the gadget. The two esteems are significant, particularly
for straight controllers, as they add the way towards choosing the ideal
warmth sink for the controller [22, 28, 50, 51].
12.6 Conclusions
This chapter discusses the various drivers for the piezoelectric actuator with
their illustrated circuit diagrams. Then, the different types of power supply
for the Piezoelectric actuators with their performance were discussed. The
various voltage regulators for the Piezo driver with their functionality were
explained. In this chapter, the different types of high precision drivers for
piezoelectric actuators were discussed in detail and it can be understable
to complete the circuit for the drivers. This is significant while choosing
direct voltage controllers. As clarified before, the drop-out voltage alludes
to the sum by which the input voltage must be more noteworthy than the
yield voltage for guidelines to happen. While this may not be a significant
thought for most applications, for applications where effectiveness and low
force contemplations are significant, it bodes well to utilize voltage control-
lers with low drop-out voltage.
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13
Design and Analysis of 31-Level
Asymmetrical Multilevel Inverter
Topology for R, RL, & Motor Load
E. Duraimurugan1, R. S. Jeevitha1, S. Dillirani1, L. Vijayaraja2*
and S. Ganesh Kumar1
1
DEEE, CEG Campus, Anna University, Tamilnadu, Chennai, India
2
Department of EEE, Sri Sairam Institute of Technology, Chennai, India
Abstract
This venture presents an asymmetrical multilevel inverter topology constructed
with a fewer number of switches for dynamic load, with a greater number of out-
put voltage levels. Initially, the working of the proposed inverter with thirty-one
levels is studied with the R and RL load. Then, it is extended to a motor load
of power rating 0.25 HP using MATLAB/Simulink. The validations of results are
done by simulation work and the results are presented.
Keywords: Asymmetric, multilevel inverter, symmetric, voltage sources
13.1 Introduction
The history of multilevel inverters began in the mid-1970s, when the first
patent describing an inverter topology capable of producing multilevel
voltage from various DC voltage sources was published by Baker and
Bannister (1975). The basic multilevel inverter is from three levels. Based
on the three level inverters, further topologies have been developed over
the years. A few of the topologies used are series H-bridge design, diode
clamped inverter, and the flying capacitor inverter system. Every topology
is equipped with different mechanisms with respect to the voltage level [1].
391
Multilevel inverters find their applications in various high voltage and

high power usages. Multilevel inverters have several other advantages
like less electromagnetic impedance and higher power handling capacity
[2]. The proposed topology has fewer switches than that of in-symmetric
topologies [3]. An MLI finds merit compared to a 2-level inverter using
high frequency switch PWM [4].
13.2 Incorporation of Multilevel Inverters

in Various Applications
Multilevel inverters have drawn enough interest in the power sector as they
are very appropriate in reactive power compensation. To produce a high
power, this may be the right choice because of its structure and the device
voltage stresses controlled in the multilevel structure [5].
In [6], the various aspects of multilevel inverters in terms of reduction in
switch count and application were discussed. Further, the different types of
multilevel inverter topologies are studied quantitatively in order to reduce
the size of the inverter and also the installation area.
In [7], it is observed that the THD reduces when the number of levels
increases from nine to fifteen, twenty seven, thirty three, and thirty nine
levels. This unequal source voltage step increment improves the output
voltage staircase waveform shape to as close as a sinusoidal shape as possi-
ble and thus reduces the % of THD.
In [8], a five level inverter is designed with minimum quantity of device
count. This design used a half bridge to generate the alternating current.
In [9], the proposed design was checked with both resistive and reac-
tive loads and the results were found with lower order harmonic content.
Hence, the overall dimension of the inverter decreases and helps in reduc-
ing the expenses.
The harmonic content analyzed from the twenty seven level inverter
within the range of IEEE specifications is found in [10].
The various designs of multilevel inverters in terms of reduced compo-
nents counts, techniques incorporated to reduce the harmonic presence in
the output waveform, and usage of MLI designs in different applications
are presented [11–19].
The need of multilevel converters is to give power with reduced total
harmonic distortions. The multilevel inverter comprises of a few switches,
diodes, capacitors and sources. In the multi-level inverter, the course of
action switch edges are vital. Multilevel voltage source converters regularly
31 Level Inverter for Motor Load 393
Multilevel
Inverters
Flying Diode Cascaded

Hybrid
Capacitor Clamped H-Bridge
Inverters
Inverter Inverter Inverters
Symmetrical Asymmetrical Symmetrical Asymmetrical
Figure 13.1 Various topologies of multilevel inverter.
integrate the staircase voltage wave from a few levels of DC capacitor volt-
ages. The various topologies of multilevel inverters are shown in Figure 13.1.
The different multilevel inverter structures being used in the power sec-
tor are
ØØ Cascaded H-bridge converter with separate DC sources

ØØ Diode clamped
ØØ Flying capacitors
It should be noted that the term multilevel converter is utilized to refer

to a power electronic circuit that could operate in an inverter or rectifier
mode. Besides the three basic multilevel inverter topologies discussed ear-
lier, other multilevel converter topologies have been proposed. However,
most of these are “hybrid” circuits are combinations of two of the basic
multilevel topologies or slight variations to them.
There is considerable interest in applying voltage source inverters in
high power applications, such as in utility systems for controlled sources
of reactive power. In the steady-state operation, an inverter will produce a
reactive current which functions as a VAR and STATCOM.
Multilevel converters have slowly started to penetrate some applica-
tions still dominated by thyristor based load commutated inverters and
cyclo-converters (grinding mills, ship propulsion, hydro-pumped storage,
very large fans, etc.). It is expected that this trend will continue in the next
decade.
Multilevel converters facilitate the use of voltage source converters in
high power application like:
ØØ Variable frequency drives

ØØ Electric vehicles
ØØ HVDC
ØØ FACT
ØØ Active power filters
ØØ Hybridization of renewable energy sources
13.3 Modeling of 31-Level Asymmetric Inverter

The inverter mentioned in the chapter is configured by using ten power
MOSFET switches and six input voltage sources which are asymmetric in
magnitude. The design work shown in Figure 13.3 uses a controlled num-
ber of switches to achieve greater quantity of voltages at the output. The
cost of design and space conception is less because of its limited number of
switches and voltage sources.
The 31-level inverter is configured with the use of four bidirectional
and six unidirectional switches. If the switches conduct in one direction,
they are called unidirectional switches and if the switches conduct in both
directions, then they are called as bidirectional switches. U1, U2, U3, and
U4 are bidirection switches and V1, V2, V3, V4, U5, and U6 are the unidi-
rection switches, as shown in Figure 13.2.
Voltage sources are selected as variable in nature to obtain the maxi-
mum number of voltage levels at the output with the minimum number
of circuit components. This reduces the circuit complexity and cost of the
inverter. A framework is obtained to find the amplitude of voltage sources.
A calculation is required to build the inverter structure and arrive at the
number of voltage sources, amplitude of the voltage sources, and finally the
number of switches for designing the proposed inverter.
Single MOSFET: current can flow

from Source to Drain via body diode
Dual MOSFETs: current cannot flow
through opposing body diodes
Drain Source
Gate
Figure 13.2 Unidirectional and bidirectional configuration of switches.

13.3.1 Mathematical Modeling of 31-Level Inverter

Due to the disadvantages existing in the higher magnitude of variable DC
voltage sources, lower value variable DC voltages are opted in designing
the proposed structure. The calculations are illustrated below:
E1 = Edc (13.1)
Voltage sources E2 and E3 are obtained as:
E1 = E2 = E3 = Edc (13.2)
The magnitude of source voltage E4 is given as:
E4 = (bs) ∗ Edc (13.3)
where ‘bs’ is the quantity of the bidirectional switch in Figure 13.3. The
amplitude of sources E5 and E6 are presented in Equation 13.4.
U5
+ –
E1 E4
– V1 V3 +
U1 U3
Load
+ –
E2 E5
– +
U2 U4
+ V4 V2 –
E3 E6
– +
U6
Figure 13.3 Asymmetric 31-level inverter [20].

E4 = E5 = E6 = (bs) ∗ Edc (13.4)
Peak voltage at the load is obtained as:
 bs 
=  + 1  ∗ (E1 + E4)
E peak (13.5)
 2 
Maximum voltage levels (Nlm) achieved from Figure 13.3 are given in
Equation 13.6.
Nlm = [bs ∗ (2n−1)] − 1 (13.6)
Ns is the quantity of switches and Nso is the volume of DC voltage sources

used in the presented topology and they are given in Equations 13.7 and
13.8.
Ns = 2(bs – 1)+4 (13.7)
Nso = bs+2 (13.8)
Based on the above design parameters, Table 13.1 shows the switching
configuration of the proposed structure. It is obvious that the number of
switches during each conduction is three and hence a minimum of three
switches are used to get the desired output level. The input voltage of the
proposed topology is given by E1 = E2 = E3 = 20 V and E4 = E5 = E6 = 80 V.
13.3.2 Modes of Operation

Figures 13.4, 13.5, and 13.6 generate multilevels in the output and the DC
sources are connected to the load step by step at the different instances of
time, explained as follows.
Various modes of operation can be achieved by operating a suitable
combination of switches in the multilevel inverter. In the first mode of
operation, the switches U5, V1, and V3 are closed and the others are open,
making the output voltage across the load zero, as shown in Figure 13.4.
In the sixteenth mode of operation, the switches U6, V1, and V3 are
closed while the others are open. The voltage across the load in this mode
of operation is (E1+E2+E3+E4+E5+E6) and it is shown in Figure 13.5.
U5
V1 V3
U5
+ –
Load
+ –
E1 E4
– V1 V3 +
U1 U3
Load
+ –
E2 – E5
+
U2 U4
+ V4 V2 –
E3 E6
– +
U6
Figure 13.4 Generation of level 1 (0 volt).
–
E1 + + E4
–
V1 V3
+ Load –
–
2 + + E5
–
U5
+ – –
E1 E4
– V1 V3 + 3 + + E6
–
U1 U3
Load
+ – U6
E2 E5
– +
U2 U4
+ V4 V2 –
E3 E6
– +
U6
Figure 13.5 Generation of level 16 (+300 volt).

U5
–
+ E4
E1 +
–
Load
–
+ E5
E2 +
– + –
–
+ E6
E3 +
– V4 V2
U5
+ –
E1 E4
– V1 V3 +
U1 U3
Load
E2 + –
E5
– +
U2 U4
+ –
E3 V4 V2 + E6
–
U6
Figure 13.6 Generation of level 31 (-300 volt).
In the thirty first mode of operation, the switches U5, V4, and V2 are
closed while the others are open. The voltage across the load in this mode
of operation is (E1+E2+E3+E4+E5+E6) and it shown in Figure 13.6.
13.3.3 Switching Principle of 31-Level Inverter

The theory of switching is explained in Table 13.1. The pulses for the
switches are generated as per the sequence provided in the Table 13.1. A
31-level at the output is achieved using the switch pattern. Once the pulses
are generated using the control logic circuit as per the sequence, then it is
given to the switches to generate inversion output by utilizing the variable
DC sources. The inverted output is fed to load and it is shown in Figure
13.7.
Table 13.1 Switching configuration to generate 31-level.

Voltage levels U1 U2 U3 U4 V1 V2 V3 V4 U5 U6
0 ό ό ό ό Ϟ ό Ϟ ό Ϟ ό
E3 ό Ϟ ό ό ό Ϟ ό ό ό Ϟ
E3+E2 Ϟ ό ό ό ό Ϟ ό ό ό Ϟ
E1+E2+E3 ό ό ό ό Ϟ Ϟ ό ό ό Ϟ
: : : : : : : : : : :
: : : : : : : : : : :
E6+E5+E4+E3+E2+E1 ό ό ό ό Ϟ ό Ϟ ό ό Ϟ
0 ό ό ό ό Ϟ ό Ϟ ό Ϟ ό
-E1 Ϟ ό ό ό ό ό Ϟ ό Ϟ ό
-(E1+E2) ό Ϟ ό ό ό ό Ϟ ό Ϟ ό
-(E1+E2+E3) ό ό ό ό ό ό Ϟ Ϟ Ϟ ό
: : : : : : : : : : :
: : : : : : : : : : :
-(E1+E2+E3+E4+E5+E6) ό ό ό ό ό Ϟ ό Ϟ Ϟ ό
where ‘Ϟ’ and ‘ό’ represent the on and off state of switches, respectively.
Multilevel
DC Sources Load
Inverter
Pulse
Generation
Logic and Curcuit
Figure 13.7 Block diagram of proposed 31-level inverter with control logic circuit.
13.4 Simulation Circuit and Result Discussions

The proposed structure of a 31-level inverter is shown in Figure 13.3 and
it is analyzed in the terms of performance of the circuit and optimizing
the harmonic distortion. Highly rated switches are used which operate at
fundamental frequency. Proposed structure with various load parameters
is simulated using MATLAB/Simulink.
13.4.1 Block Diagram for Pulse Generation

In order to generate multilevels in the output voltage, it needs to control
pulse generation for the switches. Figure 13.8 shows the block diagram of
generation of pulses which is achieved by examining constant voltage with
a sinusoidal signal. If the sinusoidal signal lies between the 0th level and 1st
level, then the state of the switching becomes one. To generate 31-levels, the
reference value varies from 0 to 1 to build a positive 16 levels and the same
procedure is followed for negative also. Summer will sum all the switch
states created and it will function as an input to trigger the corresponding
switching sequence via a multiport switch. To distribute the pulses for the
inverter, a demultiplexer is used.
13.4.2 Simulation of 31-Level Inverter with R Load

The source voltages E1 = E2 = E3 and E4 = E5 = E6 are selected as 20V and
80V, respectively. 50Hz is the frequency of the output voltage assumed for
Sine (ith)
Wave level
Compa
rator
AND Gain
Multiport
Adder Demux To Switch
Switch
(ith + 1)
level Compa
rator
Switching
Sequence
Figure 13.8 Concept of pulse generation for proposed MLI.

the switching sequence given in Table 13.2. R = 10Ω is load value consid-
ered to test the inverter design. As per the IEEE recommended practices
and requirements for harmonic control in Electric Power Systems (IEEE
519), the THD of the inverter output voltage is found as 3.18% and it is
found to be as per the standard. The peak to peak output voltage value
Table 13.2 Parameters for R-load tested in MATLAB/

Simulink.
S. no. Parameter Values
1 E1, E2, E3 20V
2 E4, E5, E6 80V
3 Output Frequency 50Hz
4 Connected Load - R Load 10 Ohm
Simulated Output Voltage Waveform (21 Loyal) R Load

Voltage Measurement
300
200
Output Voltage (R Load)
100
-100
-200
-300
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.015 0.02
Time (seconds)
Figure 13.9 31-level output voltage waveform for R load.
Current Waveform (R Load)
Current Measurement
30
20
Output Current (R Load)
10
-10
-20
-30
0.002 0.004 0.006 0.008 0.01

Time (seconds)
0.012 0.014 0.016 0.015 0.02

Figure 13.10 31-level output current waveform for R load.
Signal
Selected signal: 3 cycles. FFT window (in red): 1 cycles

300
200
Signal mag.
100
0
–100
–200
–300
0 0.01 0.02 0.03 0.04 0.05 0.06
Time (s)
FFT analysis
Fundamental (50Hz) = 305.8, THD = 3.01%
4.5
3.5
3
Mag
2.5
1.5
0.5
0
0 2 4 6 8 10 12 14 16 18 20
Harmonic order
Figure 13.11 THD for 31-level inverter with R load measured for output voltage.
achieved from the proposed structure is +300 V and it is shown in Figure

13.9. The performance of a 31-level inverter is tested for the specifications
given in Table 13.2.
The proposed structure generates an output current of +30 A as the peak
to peak value and it is shown in Figure 13.10.
Total harmonic distortion (THD) is calculated by using a Fast Fourier
transform for the output voltage and it is shown Figure 13.11. THD for the
output voltage is 3.01%.
13.4.3 Simulation of 31-Level Inverter with RL Load

The source voltages E1 = E2 =E3 and E4 = E5 = E6 are selected as 20V and
80V, respectively. 50Hz is the frequency of the output voltage assumed for
the switching sequence given in Table 13.3. R=10Ω and L=2mH are the
load values considered to test the inverter design. The peak to peak output
voltage value achieved from the proposed structure is +300 V and current
are +30A, it is shown in Figure 13.12 and Figure 13.13 respectively. The
performance of a 31-level inverter is tested for the specification given in
Table 13.2. As per the IEEE recommended practices and requirements for
Table 13.3 Parameters for R-load tested in MATLAB/

Simulink.
S. no. Parameter Values
1 E1, E2, E3 20V
2 E4, E5, E6 80V
3 Output Frequency 50Hz
4 Connected Load -R Load 10 Ohm
5 Connected Load -L Load 2mH
Simulated Output Voltage Waveform (31 Level) RL Load
Voltage Measurement
300
200
100
-100
-200
-300
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.015 0.02
Time (seconds)
Figure 13.12 31-level impedance load voltage waveform.
Current Waveform (RL Load)
Current Measurement
30
20
10
-10
-20
-30
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.015 0.02
Time (seconds)
Figure 13.13 31-level impedance load current waveform.

Signal

300
200
Signal mag.
100
0
–100
–200
–300
0 0.01 0.02 0.03 0.04 0.05 0.06
Time (s)
FFT analysis
4.5
3.5
3
Mag
2.5
1.5
0.5
0
0 2 4 6 8 10 12 14 16 18 20
Harmonic order
Figure 13.14 Output voltages FFT of 31-level inverter fed by RL load.
Signal
20
Signal mag.
–20
0 0.01 0.02 0.03 0.04 0.05 0.06

Time (s)
FFT analysis
0.4
0.35
0.3
0.25
Mag
0.2
0.15
0.1
0.05
0
0 2 4 6 8 10 12 14 16 18 20
Harmonic order
Figure 13.15 THD for 31-level inverter with RL load measured for output current.
harmonic control in Electric Power Systems (IEEE 519), the THD of the
inverter output voltage is found less than 5% and it is 3.23 % shown in
Figure 13.14.
The harmonic content in output current measured as 1.93%. The cur-
rent THD is reduced due to inductance added in the load and better cur-
rent waveform with a few phase swifts occurring due to inductance and
it is shown in Figure 13.15. Selection of R and L is done as per the below
condition.
13.4.4 Simulation of 31-Level Inverter Fed with 1φ Induction

Motor
The proposed design is able to generate a 31-level output with a peak to
peak voltage of +300V at the output. The output voltage is used to feed a
single phase induction motor with the specifications shown in Table 13.4.
The motor is supplied by a 31-level MLI output and the speed of the
motor is studied using MATLAB/Simulink. The speed of the motor fed by
a 31-level proposed inverter is shown in Figure 13.16. For no load torque,
the speed of the motor settles at an average speed of 1510rpm, but it actu-
ally swings to above and below the average speed in the range of two to
three rpm, as shown in Figure 13.16.
Electromagnetic torque achieved from a single phase induction motor
connected with a 31-level inverter is presented in Figure 13.17. The torque
gets stabilized after 0.8 seconds and the mean value obtained is 0.95Nm.
The change in torque can view from 0.75 N-m to 1.48 N-m. The equation
for different loading conditions of single phase induction motors are given
as:
Full load (Amperes) = (P [kW] × 1000) / (V × cos ϕ) (13.9)
Table 13.4 Specification of induction motor fed 31-level MLI.

S. no. Motor details Values
1 Supply Frequency 50 Hz
2 Rated Speed 1500 Rpm
3 Rated Power 0.25 Hp
4 Rated Supply Voltage 230 V
Motor Load
Gain
1600
1550
Speed (RRM)
1500
X axis – Time – 1 unit = 0.5 milli seconds

1450 Y axis – Speed – 1 unit = 50 rpm (starts from 1400 rpm)
1400
0 0.5 1 1.5 2 2.5 3

Time
Figure 13.16 Revolutions per minute of 31-level Inverter from 1-φ IM.
<Electromagnetic torque Te (N*m or pu)>
<Electromagnetic torque Te (N*m or pu)>
80
60
40
20
–20
0 0.5 1 1.5 2 2.5 3

Time (seconds)
Figure 13.17 Electromagnetic torque of 31-level inverter fed single phase induction motor.
Half load (Amperes) = (P [kW] × 1000) / 2 × (V × cos ϕ) (13.10)
The comparison of THD for R and RL loads are given in Table 13.5 and
Table 13.5 Comparison of THD for R and RL load.

Output voltage Output current
S. no. Load - THD % - THD %
1 R= 10 ohm 3.01% 3.01%
2 R=20 ohm, L= 3.23% 1.93%
2 mH
R = 10 ohm R = 20 ohm, L = 2 mH
3.23%
3.01%
3.01%
1.93%
THD % Output Voltage

THD % Output Current
Figure 13.18 Presence of harmonics in output load voltage and current for various loads.
13.5 Conclusion
By using reduced circuit components, a 31-level inverter is designed. This
31-level inverter utilizes asymmetric voltage sources with 4 bidirectional and
6 unidirectional switches respectively. The inverter design produces 31 volt-
age levels with minimum THD (3.23 %) at the output for the R load. The size
of inverter circuit is reduced and thus, reduced cost inverter can be achieved.
The design work of a 31-level inverter is carried out using MATLAB/
SIMULINK and results were analyzed for R and RL load. Also, the design
topology is tested with a single phase induction motor and the speed and
electromagnetic torque waveforms were presented.
Acknowledgement
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14
Permanent Magnet Assisted Synchronous
Reluctance Motor: Analysis and Design
with Rare Earth Free Hybrid Magnets
P. Ramesh1, D. Pradhap1 and N. C. Lenin2*
1
School of Electrical Engineering, VIT, Chennai, India
2
Electric Vehicles Incubation and Testing Division, VIT, Chennai, India
Abstract
The traction machine is one of the prime components of electric vehicles. Due to
the high power density and efficiency, permanent magnet machines are largely
preferred for traction. In this paper, the usage of hybrid rare earth-free magnet
materials (Alnico and Ferrite) in a 1.5 kW synchronous reluctance machine are
studied and compared with the conventional permanent magnet assisted synchro-
nous reluctance machine. The no-load characteristics like air gap flux and back
EMF are analyzed initially and the dynamic performances are discussed later. The
simulation results show that the usage of hybrid magnet materials helps to reduce
the active material requirement by 24% over the conventional ferrite magnets.
Compared to conventional machines, the field weakening can be improved effec-
tively by preferring hybrid magnets and the active material cost can be reduced
by 29%.
Keywords: Synchronous reluctance machine, electric two-wheeler, ferrite magnet,

alnico magnet, hybrid magnets
14.1 Introduction
In today’s world, transportation is gradually moving towards electric
vehicles. These electric vehicles use electric motors for traction purposes.
411
Certain electric motor configurations generally suitable for traction appli-

cation are the induction motor, permeant magnet synchronous motors,
(PMSM) and reluctance motors [1].
The key issue that has attracted both the industry and researchers
towards PMSM is the huge remanence flux density processed by rare-earth
magnets such as NdFeB and SmCo [2]. These rare-earth magnets, when
used in PMSM, enhance their performance to deliver higher power den-
sity, torque density, and efficiency and make it suitable for traction appli-
cation [3]. Due to the issue of cogging torque present in the SPMSM [4],
in IPMSM torque production involves both the contribution of magnet
and reluctance offered by permanent magnets and structural saliency [11].
This makes way for the IPMSM to operate at much higher speeds than the
SPMSM.
These permanent magnet synchronous motors are more dependent on
rare earth magnets which are very costly and are available only in very lim-
ited quantities. In such cases, rare-earth free magnet assisted Synchronous
Reluctance Motors prove as another alternative for electric traction. The
rare-earth free magnet assisted Synchronous Reluctance Motor has the
merits of both the PMSM and Synchronous Reluctance Motors. These
motors provide both improved power density as well as wide operating at
a comparatively cheaper cost [5, 6].
Magnet Motors free from rare-earth magnets generally use only two
kinds of magnets, namely ferrite and AlNico. But, the high input power
requirement and reduced power density of Ferrite Magnet SynRM cre-
ate a gap to use it practically in electric vehicles [7–9]. To reduce this
gap, the usage of hybrid magnet materials in synchronous reluctance
machines is analyzed in this paper and compared with conventional
single magnet materials using the finite element software Simcenter
MAGNET.
The construction and torque production of a permanent magnet-
assisted synchronous reluctance machine (PMa-SynRM) is explained in
Section 14.2. In Section 14.3, the machine topologies based on magnet
materials are discussed with the specifications of the designed machine.
The no-load characteristics of the designed machines are analyzed and
compared in Section 14.4. The performance of the designed machines
for various operating regions is investigated in Section 14.5. Finally,
Section 14.6 summarizes the performance comparison of various
machine topologies to view the amount of gap reduced due to hybrid
magnet materials.
Analysis and Design of SynRM 413
14.2 Literature Survey

The technology of SynRM assisted with permanent magnets has under-
gone numerous developments over the past decade. An overview of the
same is provided in this section.
In this paper, a 5 kW PM assisted synchronous reluctance motor with
less usage of rare earth magnets has been proposed with a combination of
rare earth NdFeB and ferrite permanent magnets [10]. By keeping the high
saliency, the reluctance torque plays a predominant role of about 64.1%.
Even with a lesser amount of rare earth permanent magnet, the PM torque
contributes 35.9% in total torque [10]. Also, the improved demagneti-
zation performance in overload conditions has been proved in the pro-
posed motor. The irreversible demagnetization of ferrite magnets has been
reduced by implementing the hybrid magnet topology with a combination
of ferrite and NdFeB magnets [10].
The low-cost rare earth-free magnet has been inserted in the rotor bar-
rier to make the synchronous reluctance suitable for automotive appli-
cation by providing improved efficiency and power density [11]. It also
proves better field weakening performance and power factor. The output
power has been increased by increasing the stack length and the torque
ripple has been studied for short pitch winding, rotor skewing, and adding
dips on the surface of the rotor [11].
The main objective of inserting permanent magnets into synchronous
reluctance motor rotor barriers is improving torque density and power fac-
tor [12]. When compared to the synchronous reluctance motor, the low
cost non-rare earth ferrite assisted synchronous reluctance motor provides
a 7% increment in torque and about 10% and 6% improvement in the
power factor at lower currents and higher currents, respectively [12]. Due
to the irreversible demagnetization characteristic of ferrite magnet, the
overload capacity of ferrite assisted SynRM is finite [12]. So, the SynRM
motor is the choice for high overload capacity requirement applications
like traction due to the absence of permanent magnets in rotor barriers.
In this paper, the performance of 10 kW PM assisted SynRM is studied
by changing the position and size of the permanent magnet [10]. It has
been seen that the torque, inductance, and power factor are affected by
changing the width and thickness of the permanent magnet [10]. The flux
linkage of the permanent magnet is increased by increasing the thickness
of the permanent magnet and creates a saturation along the q-axis. This
leads to an increase in a small amount of torque and power factor [10].
To study the effect of changing the permanent magnet width, the width
of the magnet is varied and compared and the permanent magnet torque
component is increased by increasing the magnet width, thereby increas-
ing the total torque component [10].
A novel rotor has been proposed in this paper [17] by shifting the mag-
net axis of the rotor. The asymmetrical arrangement of the magnet causes
the magnet axis shift of hybrid PMSM. The asymmetrical arrangement can
be done by placing the NdFeB and ferrite magnets on each side of the del-
ta-shaped rotor barrier [13]. In general, IPM gets maximum reluctance
torque and permanent magnet torque at different current angles. Due to
a shift in the magnet axis, the difference between current angles of maxi-
mum reluctance torque and permanent magnet torque has been reduced
[18]. By that, total torque has been improved. The performance of the
proposed machine had been compared with BMW i3 IPM [19]. The total
torque and back EMF have improved by 7.81% and 53.54%, respectively.
The torque ripple of the machine is greatly reduced by 55.99%. There is an
increase in back EMF due to an increase in flux linkage of the proposed
hybrid magnet IPM.
PM assisted SynRM with both the ferrite and NdFeB has been proposed
in this paper [20]. The performance of the machine is analyzed by chang-
ing the magnet ratio of rare earth and ferrite magnets. The performance of
power factor, cogging torque, torque ripple, and flux density has been stud-
ied for magnet ratios 0, 0.2, 0.4, 0.6, 0.8, and 1 in the proposed machine
[21]. It is to be noted that by increasing the magnet ratio, the flux density
is increased. The maximum torque ripple of 22.3% was obtained by a mag-
net ratio of 1 and a minimum of 13.8% by a ratio of zero. The irrevers-
ible demagnetization is studied at a temperature of -40oC. The maximum
power factor is achieved by a magnet ratio of 1 [22].
The PM assisted synchronous reluctance motor lags in power factor
even though it has characteristics like better output power and average
torque comparison with conventional SynRM [23]. In this paper, the char-
acteristics of PM assisted SynRM with four flux barriers and eight pieces
of the magnet have been studied. The results are carried by a machine with
two different permanent magnets, namely ferrite and NdFeB. The power
factor calculated from the machine with ferrite and NdFeB is 0.68 and 0.89,
respectively. It is evident that the machine NdFeB magnets are 30% higher
than ferrite magnet assisted machines.
In general, the power factor and power speed range of PM assisted
SynRM is improved by inserting a permanent magnet in a rotor barrier
against the q-axis, but this arrangement leads to the demagnetization of
the permanent magnet. In this paper, the steps towards reducing the above
problem with permanent magnets are arranged in such a way that they
crosses the flux barriers, are investigated [24]. Both the flux barriers and
inset permanent magnets are shifted with respect to the rotor direction of
rotation. It has been studied that the proposed machine reduces the irre-
versible demagnetization risk and torque ripple.
The permanent magnet assisted SynRM with a different permanent
magnet like NdFeB, SmCo, AlNiCo, and ferrite has been investigated in
this paper. It is found that a machine with NdFeB provides better torque
performance. The machine with ferrite magnets gives reasonable torque
performance and it is suitable for applications like light electric traction.
The permanent magnet assisted synchronous reluctance motor exhib-
its characteristics like low power factor and low power density due to the
absence of field excitation in the machine rotor. To overcome the above
issue, SynRM with an AlNiCo magnet has been proposed in this paper.
Comparison of the proposed AlNiCo magnet machine with a conventional
SynRM machine has been studied. The AlNiCo magnet is comparatively
higher in the value of remanence flux density and lowers coercive field
intensity of the ferrite magnets. From the analysis, machines with AlNiCo
magnets give a better power factor and power density compared to base
SynRM machines.
14.3 Construction and Torque Equation

The stator of PMa-SynRM is similar to the conventional AC machine sta-
tor with three phase windings. The rotor of this machine has multiple flux
barriers to create structural saliency. In the flux barriers, the permanent
magnets are inserted, as shown in Figure 14.1.
In this machine, the torque is produced due to two components, as given
in Equation 14.1 [11–13]. The primary component is due to the structural
saliency of the rotor, which is generally termed as reluctance torque. This
reluctance torque is produced by the change in inductance with respect
to rotor position. Stator flux tries to flow in a minimum reluctance path.
In an unaligned position, the rotor will rotate to get minimum reluctance
position and the interaction between the permanent magnet flux and sta-
tor current creates the secondary component, which is commonly called
magnet torque. In a reluctance motor, the axis along with the minimum
reluctance path is called the d-axis. Similarly, the axis along with the high
reluctance path is called the q-axis. The magnitude of the d-axis and q-axis
inductances are based on the rotor geometry. In order to get better saliency,
q-axis
Stator back iron d-axis
Windings
Flux carrier
Rotor back iron
Magnet
Flux barrier
Stator teeth
Figure 14.1 PMa-SynRM.
the d-axis inductance should be high and the q-axis inductance should be
at a minimum.
The magnet should be oriented in such a way to aid the reluctance
torque. The permanent magnet flux linkage (ψm) opposes the q-axis flux
linkage (ψq), which brings the total flux linkage (ψ) into the fourth quad-
rant, as shown in Figure 14.2. Due to this, the voltage vector (V) comes
closer to the current vector (Is), which improves the power factor.
T = (Ld – Lq)idiq + ψmid
where
T – Torque
Ld – d-axis inductance
Lq – q-axis inductance
id – d-axis current
iq – q-axis current
ψm – Permanent magnet flux linkage
The maximum current given by the inverter is Ip. Therefore, the id and iq
can be defined as [13]:
id = Ip cos β
q-axis
ωψm
–ωLqiq jωLdid V
iq Is jLqiq
Ldid
ld d-axis
−jψm
ψ
Figure 14.2 Phasor diagram of PMa-SynRM.
iq = Ip sin β
where β is current advancement angle with respect to d-axis.

The saliency ratio ξ can be defined as:
Ld
ξ=
Lq
By substituting the above equations in torque equation, we can get the

torque equation in terms of current advancement angle β. The maximum
torque achieved by the current angle β is given by:
 −ψ m + ψ m2 + 8 I max
2
(ξ − 1)2 L2q 
β = cos −1  
 4(ξ − 1)Lq Im ax 
14.4 Design Specifications and Machine Topologies

The specifications of the designed machines for e2Ws are specified in Table
14.1. Initially, Machine 1 has been designed using ferrite magnets with an
Table 14.1 Design specifications.

Parameter Value
Supply Voltage 48 V
Rated Power 1.5 kW
Rated Speed 2500 rpm
Rated Torque 5.7 Nm
Peak Torque 13 Nm
Maximum Speed 8000 rpm
7 2
6
1.6
Output power (kW)

5
Torque (Nm)
4 1.2
3 0.8
2
0.4
1
0 0
2 3 4 5
Number of barriers
Figure 14.3 Choice of number of barriers.
7 1.6
6
Output power (kW)
1.2
5
Torque (Nm)
4
0.8
3
2
0.4
1
0 0
2 4 6 8
Number of poles
Figure 14.4 Choice of number of poles.

outer diameter of 140 mm. The performance of the designed machine is

analyzed for various number of barriers, as shown in Figure 14.3.
Even though five barriers provide 5.2 % higher output power than three
barriers, considering the rotor stress, eccentricity, and manufacturing fea-
sibility, three barriers are selected. Further, various pole configurations are
Start
Selection of main dimensions
Design of stator geometry and windings
Rotor geometry design with ferrite magnets

(initially keep the number of barriers (B) as 2)
Yes
Analyze the performance and B++ Whether

B<6
No
Sensitivity analysis for number of pole pairs (P), initially P=1
No
Analyze the performance and P++ Whether P>4
Yes
Save Machine 1 Select the number of poles with better performance
Replace the magnet material with Alnico 9
Analyze the performance
Save Machine 2 Vary the stack length to obtain the required power
Keep hybrid magnet materials (Ferrite and Alnico)
Analyze the performance
Vary the stack length to obtain the required power

Save Machine 3
Stop
Figure 14.5 Design.

analyzed. At the rated operating condition, the six pole machine provides
5.8 Nm torque with an output power of 1.52 kW, as shown in Figure 14.4.
The designed Machine 1 has 36 slots with a 6 pole configuration, as
shown in Figure 14.1. The design process is explained in Figure 14.5. The
magnets are then fully replaced with Alnico magnets for Machine 2 and
partially replaced for Machine 3, as shown in Figure 14.6. In order to obtain
Ferrite Alnico
(a) Machine 1
(b) Machine 2
(c) Machine 3
Figure 14.6 Machine topologies.

Table 14.2 Main dimensions and materials used.

Parameter Machine 1 Machine 2 Machine 3
Stator Outer Diameter (mm) 140 140 140
Stack Length (mm) 58 55 44
Machine Length (including 112 106 96
end windings (mm))
Core Material M-36 Silicon Steel (29 Gauge)
Magnet Material Ceramic 10 Alnico 9 Both Ceramic
10 and
Alnico 9
the required output power in Machine 2 and Machine 3, the stack length
is varied accordingly. The input current is kept constant at 28 A (RMS) for
all three machines to make a reasonable comparison. The main dimensions
and materials used are mentioned in Table 14.2 and the material properties
are adopted from [14–17]. The no-load characteristics of these machines
are discussed in the next section.
14.5 No-Load Characteristics

Initially, the no-load characteristics of the designed machines are analyzed.
Figure 14.7 shows the spatial distribution of flux in the air gap for one pole
pair. Compared to Machine 1, Machine 3 has a 42% higher flux density.
Machine 3 has a peak flux density of 0.44 T in the air gap. The back EMF
induced in these machines is portrayed in Figure 14.8.
Figure 14.9(a) shows phase back EMF at 2500 rpm. It is observed that
the peak value of the back EMF for Machine I, Machine II, and Machine
III are 8.9 V, 10.4, and 12.3 V, respectively.
Fast Fourier transform (FFT) is performed to analyze harmonic content
in back EMF. Figure 14.9(b) shows the harmonic component of the back
EMF for Machine 1, Machine 2, and Machine 3.
The cogging torque at 2500 rpm is shown in Figure 14.10. Cogging
torque results from variations in air gap permeance due to the interac-
tion between permanent magnet and stator teeth. Machine 2 has a peak
of 0.0835 Nm. Machine 1 has minimal cogging torque which is 40% lower
than Machine 2 and 28% lower than Machine 3.
0.5
Machine 1
0.4
Machine 2
0.3
Machine 3
0.2
Flux density (T)
0.1
0
0 20 40 60 80 100 120
-0.1
-0.2
-0.3
-0.4
-0.5
Rotor position (deg.)
Figure 14.7 Air gap flux density of one pole pair.
Machine 1 Machine 2 Machine 3

30
20
10
Back EMF (V)
0
0 20 40 60 80 100 120
-10
-20
-30
Rotor position (deg.)
Figure 14.8 Back EMF for one pole pair.


15
10
5
Back EMF (V)
-5
-10
-15
0 5 10 15
Time (ms)
(a)
4.5
Phase Back EMF (% of fundamental)
4
3.5
3
2.5
2
1.5
1
0.5
0
2 3 4 5 6 7
Harmonics
(b)
Figure 14.9 (a) Phase Back EMF, (b) Harmonic component of back EMF.

0.1
0.08
0.06
0.04
Cogging torque (Nm)
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
0 2 4 6 8 10
Rotor Position (mechanical deg.)
Figure 14.10 Cogging torque.
14.6 Performance at Various Operating Regions

After analyzing the no-load performance, the performance of the designed
machines at various operating conditions are examined. Initially, the
torque obtained at the rated condition for various current angles is stud-
ied. Figure 14.11 shows that the maximum torque can be obtained at the
current advancement angle of 50 degrees.
Figure 14.12 shows the torque with respect to rotor position with a cur-
rent angle of 50 degrees for Machine 1, Machine 2, and Machine 3.
From Figure 14.13, which shows the ratio of reluctance torque and
magnet torque component in total torque, it is evident that the reluctance
torque component plays a leading role in total torque. The magnet torque
component of Machine 2 is 43% higher than Machine 1 and 21% higher
than Machine 3. This is because the remanence flux density of alnico is
higher than that of ferrite. Hence, Machine 2 has better permanent magnet
flux linkage when compared to Machine 1 and Machine 3. For the current
angle of 50 degrees, the reluctance torque ratio of Machine 1, Machine 2,
and Machine 3 is 84%, 77%, and 81%, respectively. This variation reluctance
torque ratio is due to the effect of different permanent magnet material in
the rotor barrier structure.
The d-axis inductance (Ld) and q-axis inductance (Lq) for different cur-
rent values are depicted in Figure 14.14. The permanent magnet placed

7
5
Torque (Nm)
0
0 10 20 30 40 50 60 70 80 90
Current angle (deg.)
Figure 14.11 Torque for various current angles.
in the rotor barriers not only opposes q-axis flux, but also aids the d-axis
flux. These magnets saturate the iron bridges by blocking the q-axis flux
and increases the saliency ratio. At rated current 28 A, the saliency ratio
of Machine 3 is 4.1%, 4% higher than that of Machine 1 and Machine 2,
respectively. From this, we conclude that Machine 3 has better saliency
performance among the others.
The hysteresis and eddy current losses of the designed machines at the
rated load condition are depicted in Figure 14.15. Machine 3 has 16%
reduced hysteresis loss over Machine 1. Compared to other machines,
Machine 3 has the lowest core losses with 23 W hysteresis loss and 7 W
eddy current loss.
The torque speed characteristics of Machine 1 are shown in Figure 14.16.
Up to the rated speed of 2500 rpm, all the machines are delivering the
required torque of 5.8 Nm. At the maximum speed of 8000 rpm, Machine
1 delivers the torque of 1 Nm with an output power of 0.84 kW. The torque
and output power characteristics of Machine 2 and Machine 3 are depicted
in Figures 14.12 and 14.13. Compared to Machine 2, Machine 3 has twice
the torque at the maximum speed of 8000 rpm, with an output power of
1.2 kW.
Figure 14.17 shows the efficiency of designed machines at the rated
and maximum speeds. At the rated speed of 2500 rpm, Machine 3 has a
Machine 1 5.8 Nm
8
7
Torque (Nm)
4
0 20 40 60 80 100 120
Rotor Position (deg.)
(a)
Machine 2 5.9 Nm
8
7
Torque (Nm)
4
0 20 40 60 80 100 120
(b)
Machine 3 6 Nm
8
7
Torque (Nm)
4
0 20 40 60 80 100 120
(c)
Figure 14.12 Torque vs Rotor Position for (a) Machine 1, (b) Machine 2,
and (c) Machine 3.
2% higher efficiency than Machine 1 and a 1.5% higher efficiency than

Machine 2. Similarly, Machine 3 is 92% efficient at the maximum speed of
8000 rpm.
Reluctance Torque Magnet Torque
100
90
80
70
60
Ratio (%)
50
40
30
20
10
0
10 20 30 40 50 60 70 80
(a)

100
90
80
70
60
Ratio (%)
50
40
30
20
10
0
10 20 30 40 50 60 70 80
(b)

90
80
70
60
Ratio (%)
50
40
30
20
10
0
10 20 30 40 50 60 70 80
(c)
Figure 14.13 Reluctance torque and magnet torque ratio of (a) Machine 1, (b) Machine 2,
and (c) Machine 3.
Ld Lq
1
0.9
Inductance (mH) 0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 10 20 30 40
Current (A)
(a)
Ld Lq
0.9
0.8
Inductance (mH)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 10 20 30 40
Current (A)
(b)
Ld Lq
1
0.9
0.8
Inductance (mH)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 10 20 30 40
Current (A)
(c)
Figure 14.14 d-axis and q-axis Inductance vs Current for (a) Machine 1, (b) Machine 2,
and (c) Machine 3.
30
Hysteresis loss (W) Eddy current loss (W)
25
20
Losses (W)
15
10
0
Figure 14.15 Core losses at rated load.
Machine 3 is operating with a power factor of 0.8 at the rated load, which
is 4% higher than Machine 2 and 5% higher than Machine 1. The power
factor and specific power of the designed machines are depicted in Figure
14.18. Machine 3 has a specific power of 0.31 kW/kg, whereas Machine 1
and 2 have 27% and 21% lesser specific power than Machine 3.
14.7 Conclusion
In this paper, the performance of synchronous reluctance machines with
conventional single magnet materials (Machine 1 and Machine 2) and
hybrid magnet materials (Machine 3) are compared. From the compari-
son, the following conclusions are made:
• Using hybrid magnet materials (Machine 3), the stack length

of the machine can be reduced by 24% over the conventional
single ferrite magnets (Machine 1).
• At the rated load, Machine 3 has 16% and 11% reduced core
losses over Machine 1 and Machine 2.
• Machine 3 helps to reduce the weight of the active materials
by 24% over Machine 1, as given in Table 14.3.
• This also helps to reduce the cost by 29%.
• At the rated speed, Machine 3 is 2% more efficient than
machine 1 and 1.5% more efficient than Machine 2.
7 2
6
1.6
Output power (kW)

Torque (Nm) 5
4 1.2
3 0.8
2
0.4
1
0 0
0 2000 4000 6000 8000
Speed (rpm)
(a)
7 2
6
1.6
Output power (kW)

5
Torque (Nm)
4 1.2
3 0.8
2
0.4
1
0 0
0 2000 4000 6000 8000
Speed (rpm)
(b)
7 2
6
1.6
Output power (kW)
5
Torque (Nm)
4 1.2
3 0.8
2
0.4
1
0 0
0 2000 4000 6000 8000
Speed (rpm)
(c)
Figure 14.16 Torque and output power characteristics for (a) Machine 1, (b) Machine 2,
and (c) Machine 3.
92
90
Efficiency (%)
88
86
84
82
at rated speed (2500 rpm) at maximum speed (8000 rpm)
Figure 14.17 Efficiency at rated speed and maximum speed.
0.90
Power factor kW/kg
0.80
0.70
0.60
Losses (W)
0.50
0.40
0.30
0.20
0.10
0.00
Figure 14.18 Power factor and specific power at rated load condition.
Table 14.3 Weight and cost of active materials.
Approx. cost per Weight Weight Cost Weight Cost

Component unit (Rs./kg) (kg) Cost (Rs.) (kg) (Rs.) (kg) (Rs.)
Stator Core 120 [25] 2.41 289.2 2.05 245.8 1.64 196.7
Stator Winding 630 [26] 2.23 1404.9 1.90 1194.2 1.52 955.3
Rotor Core 120 [25] 1.65 198.0 1.40 168.3 1.12 134.6
Rotor Magnets 100 [27, 28] 0.40 39.6 0.99 99.0 0.79 79.2
Total - 6.69 1931.7 6.34 1707.3 5.07 1365.8
• Usage of hybrid magnet materials helps to improve the

torque at the maximum speed, nearly twice that of Machine
2.
• Machine 3 delivers an output power of 1.2 kW with an effi-
ciency of 92% at the maximum speed, which is 1.5% higher
than Machine 1 and 3% higher than Machine 2.
• Machine 3 is operating with the specific power of 0.31 kW/
kg, which is 36% higher than Machine 1 and 27% higher
than Machine 2.
Acknowledgment
We sincerely thank Non-Ferrous Materials Technology Development
Centre (NFTDC), Hyderabad, India for their funding and support for the
project (NFTDC/DIR/9070P07/2018).
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15
Design of Bidirectional DC – DC
Converters and Controllers for Hybrid
Energy Sources in Electric Vehicles
R. Chandrasekaran, M. Satish Kumar Reddy, K. Selvajyothi* and B. Raja
Indian Institute of Information Technology Design and Manufacturing,

Kancheepuram (IIITDM Kancheepuram), Chennai, Tamil Nadu, India
Abstract
The bidirectional converters become an integral part of Hybrid Energy Management
Systems (HEMS) which can transfer power both in forward and reverse direc-
tions. This chapter examines the control strategy for HEMS through different bidi-
rectional converters such as Boost converters, Interleaved Boost converters (IBC),
combined SEPIC Luo converters, and Dual Boost Converters (DBC). The HEMS
requires the energy transfer among various sources and the drivetrain of the
Electric Vehicle (EV) and vice versa. The features of each bidirectional converter
fed from the battery and supercapacitor to drive a PMDC motor are discussed to
validate the control strategy used for the Hybrid Energy Storage System (HESS).
This study provides a performance level comparison of various converters and
helps to realize the appropriate converter topology and specification.
Keywords: Bidirectional converters, Hybrid Energy Storage Systems (HESS),

Hybrid Energy Management System (HEMS), batteries, super-capacitors,
PMDC motor
15.1 Introduction
The Bidirectional converter regulates the energy transfer within the battery
and the power train inverter of an Electric Vehicle (EV). The Bidirectional
Converters (BDC) are categorized by input sources as current fed or
437
voltage fed converters. They are further classified into buck (step down)
and boost (step up) converters based on the employment of an additional
energy source. In the former, an energy source is placed on the higher
potential side and in the latter, on the lower potential side. To establish the
bidirectional power flow, the switching devices must carry the load current
in both the directions and the feature is available in power MOSFET and
IGBT, which contains a diode (or body diode) in parallel with the main
switch. The two basic types of BDC topologies [1] are namely (a) isolated
and (b) non-isolated, as shown in Figure 15.1.
The converter topology and control objectives decide the choice of
BDC’s control scheme [2]. The control scheme regulates and route energy
transfer among the energy storage devices and the load. The type of control
schemes for BDC in Figure 15.2 must ensure the continuous transition
between the different modes of stable and efficient operation. The oper-
ational changeovers in bidirectional converters are shifting from the low
BDC
Topologies
Non – Isolated Isolated

Topologies Topologies
Buck/ Buck - SEPIC/ Cuk/

Cuk Flyback Push-Pull Forward
Boost Boost Zeta SEPIC
Switched- Dual Dual Half Half-Full

Cascaded Interleaved Multilevel Multi-Port
Capacitor Active Bridge Bridge
Figure 15.1 Classification of BDC power converters.
Control
Strategies
General Switching
Control Schemes Strategies
Sliding Dynamic
PID SPS PWM - SPS PWM
Mode Evolution
Boundary Fuzzy ANN DPS TPS MCPWM
Figure 15.2 Classification of control strategies.

Bidirectional DC-DC converters for HES 439
voltage side to the high voltage side and vice versa. The voltage levels of
source and load are the stimulus for the controller. The classical control
strategies use the State of Charge (SoC) while charging and discharging
of the energy sources, which stimulates the controller and causes large
transients during the transition from low voltage control to high voltage
control. To mitigate this, Pulse Width Modulation (PWM) based control
schemes are provided for continuous power flow within the load and the
sources. The transition of bidirectional energy flow is another major con-
trol issue in BDC.
15.2 Need For Hybrid Energy Management Systems

in EV
Lead Acid (LA), Nickel-Metal Hydride (NMH), and Lithium-ion (Li-ion)
are major types of chemistries available for EV traction [3, 4], but Li-ion
batteries are the most preferable for energy storage systems in EVs due
to their light weight compared to rest of the two. The necessary precau-
tions need to be taken during charging and discharging due to its chemical
instability. In 1991, Sony Corporation introduced the commercial ver-
sion of the Li-ion battery, which is suitable for rechargeable applications.
Although having many advantages, Li-ion batteries have noticeable draw-
backs along with their brittle nature. The careful management of Li-ion
batteries with a sufficient protective arrangement provides the safer oper-
ation at each cell of EV battery pack. The circuit which has a protective
arrangement is called a Battery Management System (BMS) [5, 6], which
monitors cell temperature, voltage, and current during EV charging and
working. The performance parameters that are used to analyze the Li-ion
batteries are cell temperature and voltage. Operating above its safety limit
(2.5 V - 4.2 V) may be permanently damage the cell. Lithium plating and
overheating is caused due to overcharge and progressive break down of the
electrode due to over discharge and rest period of them for a long time.
The proposed configuration is designed to manage the power flow among
three main energy sources such as battery packs, SC, and electric motors.
Stochastic rules for control strategy are framed based on load torque for
power flow exchanging between the battery pack and motor. Additionally,
the system is sensitive to A high starting current and sudden acceleration
of the vehicle. It is necessary to include the aging factor of the battery in the
sense of converter dynamics to enhance the battery life and the reliability
of continuous operation. The bidirectional power flow management and
battery pack performance while charging and discharging are non-linear

functions and require the averaging of the converter at various operating
modes. The specific power energy density and time constant of the battery
also need to be considered while choosing the appropriate control strategy.
The load current of the motor decides the operating mode for energy
management. The control strategy of the EV decides the power for accel-
erating the EV by the output voltage and SoC. The battery SoC should be
regulated at its reference value via its power with a controller for supplying
the required current for the load, which needs enough capacity for braking
energy. The battery slew rate is limited by the rate limiter to smoothen the
battery power which is adjusted by the controller. The output power and
the battery power decide the charging and discharging modes of the bat-
tery with the controller.
15.3 Hybrid Energy Storage System (HESS)

The Hybrid Energy Storage System (HESS) for EVs shown in Figure 15.3
depicts that the battery pack is dedicated to supply the average power and
the Super-Capacitor (SC) supplies the peak power requirement during
starting and acceleration. The SC will handle the peak power requirement
until it reaches the lower voltage limit. If the energy available in the auxil-
iary source is less than the specified limit, then it is recharged by the battery
pack until the vehicle is moving. The regenerative power available during
SUPER PSC
PEAK
CAPACITOR POWER
Power Balance Policy OPPORTUNITY

PLOAD
PLOAD = PSC + PBATT CHARGING
PBATT
CONTINUOUS
BATTERY
POWER
Figure 15.3 Hybrid energy storage system.

braking and deceleration is used to recharge the SC. In the proposed meth-
odology, the following configuration of HESS is analysed.
1. Passive Parallel HESS

2. Parallel converter HESS
15.3.1 Passive Parallel HESS

The block diagram representation of passive parallel HESS is shown in
Figure 15.4. In this method, the battery and SC are connected in parallel,
so the final voltage of the battery is always the same as the SC voltage. Here,
the SC is not delivering any power during peak power requirement and
it only absorbs the regenerative power during braking and deceleration,
resulting in faster discharge of the battery. Thus, the high-power handling
characteristics of the SC are not completely utilized.
15.3.2 Parallel Converter HESS

Figure 15.5 shows the block diagram of a parallel converter HESS. In this
method, the battery and SC deliver the power to the motor by dedicated
converters connected in parallel. Here, a constant current is allowed to
discharge from the battery by considering its safety limit. Energy sources
with individual converters decouple the power, supplying paths and source
voltages that are maintained the same as DC link voltage by PWM con-
trol. This method gives higher flexibility in operation of energy sources,
improves efficiency, and provides stable operation in different modes of
operations. The dedicated converter reduces the stress on the battery, but it
slightly increases the weight of the power converters when more than two
sources are hybridized.
Batteries SC
Bi-directional Inverter
DC/DC Converter
Figure 15.4 Passive parallel HESS.

Bi-directional
DC/DC Converter
Primary
Source M
Batteries
Inverter
Auxiliary
Source
UC
Bi-directional
DC/DC
Figure 15.5 Parallel converter HESS.
In this chapter, the following converter topologies are considered for

validating the proposed control strategy for different operating conditions.
1. Boost converter with and without auxiliary storage system

2. Interleaved Boost converter with and without auxiliary stor-
age system
3. SEPIC-Luo converter with auxiliary storage system
4. Dual boost converter auxiliary storage system.
15.4 Bidirectional DC-DC Converters (BDC)

The majority of the BDC [7] are designed with bidirectional switches which
are power IGBTs, along with parallel diode or power MOSFETs with cur-
rent fed or voltage fed. BDCs are categorized as buck type and boost type
powered by HESS. The HESS is located in higher and lower potential sides
according to the converter topology. The BDCs which carry double power
flow are realized with switch cells which carry the current in both direc-
tions. Typically, BDCs are two types, which are non-isolated and isolated
[7, 8]. The scope of this chapter is only on the non-isolated converters.
Generally, boost type and buck type converters are used for transformers
less than non-isolated power conversion systems. For high power opera-
tion, isolation is required between the HESS and drive train, which can
be attained with a high frequency transformer, but non-isolated type con-

verters are attracted for their high efficiency, compact size, less weight, and
cost. Hence, transformer-less converters are preferred in systems where
weight and size form the major concerns.
A) Boost Converter
The circuit topology of the Boost Converter (BC) is given in Figure 15.6.
It is assumed that the circuit is operating under a steady state condition
and the input voltage is an ideal source. The operation of the converter
[9, 10] is as follows: when switch S is closed and the current in diode D
is reversed, now the voltage across the inductor VL starts to increase and
becomes equal to the source (VIN). Then, when S is off, energy accumu-
lated during the ON period in the inductance is discharged through the
capacitor C and the inductor voltage VL = VIN − VOUT. This process transfers
the energy from source to load with an output voltage VOUT higher than
the VIN. This type of converter is required in an electric power train [8] to
regulate the energy between the low voltage battery pack to the traction
inverter, which is operating with a voltage greater than the source volt-
age. Over the time period ‘T’, the average value of VL is equal to 0 under
steady-state operation. From (15.1), the transformation ratio between VIN
and VOUT in the steady state is given by relation (15.2), where D is the duty
cycle of gate pulse applied to S1.
1 DT T

VL = 
T ∫0
VIN DT +
∫
DT
VIN − VOUT DT  = 0

(15.1)
VIN = (1 − D) VOUT (15.2)
The conversion ratio of current in the boost converter under steady state
is given by:
i
L
iOUT
+ VL - FD
U +
S C VOUT R
Vin -
Figure 15.6 Boost converter.

iL1
L1 D1
+ VL1 -
iL2 iOUT
L2 D2
+
+ VL2 -
C VOUT R
Vin U U’ -
S1 S2
Figure 15.7 Interleaved boost converter.
IOUT = (1 − D) IN (15.3)
B) Interleaved Boost Converter

Figure 15.7 shows the topology for 2-phase Interleaved Boost Converter
(IBC). The circuit [11] contains two switches (S1 & S2) and two diodes (D1
& D2). The power semiconductor switches and diodes are connected in
analogous for each phase. To bring down the size and weight of filter com-
ponents, a suitable phase-shift control strategy needed to be implemented
[12]. The duration of each gate pulse can be obtained from T / (P × Q)
where T is time period of the switching pulse, P refers the levels of phases,
and Q refers the switches required in each phase.
C) SEPIC-Luo Converter
The combined SEPIC (Single Ended Primary Inductor Converter) Luo
converter [13] shown in Figure 15.8 has two inductors, L1 and L2. L1 is con-
nected in series and L2 is connected in parallel with the source. The load
current and output voltage ripples are very low, which improves the con-
verter power factor [14]. In SEPIC, the output voltage (VOUT) is less than
the source voltage (VIN) whereas the Luo converter is used for traction. A
combined SEPIC-Luo is working the same as the conventional buck-boost
converter and it has many advantages compared to other converters such
as having non-inverted output and isolation between its input and output.
The converter operates in true shutdown mode when the pulse is removed,
which makes output voltage zero.
D) Dual Boost Converter

The circuit topology of the Dual Boost Converter (DBC) is given in Figure
15.9. The design consists of two converters connected with a battery pack
L1 C1 S2
iOUT
+ VL1 -
+ +
VOUT R
U L2 VL2 C2
Vin S1 - -
Figure 15.8 Combined SEPIC-Luo converter.
i
L1
+ VL1 - FD1
U1
S1 C1 iOUT
BAT
+
i R
L2 VOUT
-
+ VL2 - FD2
U2
S2 C2
SC
Figure 15.9 Dual boost converter.
and SC separately [15]. The operation of the converter is as follows: when

switch S1 is closed and the current in diode FD1 is reversed, now the voltage
across the inductor VL1 starts to increase and becomes equal to the source
(VBAT). Then, when S1 is off, energy accumulated during the ON period
in the inductance is discharged through the capacitor C1 and the voltage
across the inductor is VL1 = VBAT − VOUT. This process transfers the energy
from the battery pack to the load with an output voltage VOUT higher than
the VBAT. This converter is operated when the electric power train draws
a current less than the threshold value. When S2 is closed, FD2 is reversed
and now the voltage across the inductor VL2 starts to increase and becomes
equal to the source (VSC). Then, when S2 is off, energy accumulated during
the ON period in the inductance is discharged through the capacitor C2
and the voltage across the inductor is VL2 = VSC − VOUT. This operation is
carried out during the current drawn by the power train is higher than the
threshold values and the suitable control strategy is required for regener-
ative braking.
15.5 Specifications of DC-DC Converters

The design procedure for these converters is available in many literature
and the design equations are tabulated as in Table 15.1. The optimal design
of components is chosen based on the operating conditions like input and
output specifications. The following requirements are considered critical
[16] while designing DC/DC converter circuits for any application:
• Stable operation
• Efficiency
• Low output ripple
• Converter dynamics
These properties can be improved to some extent by changing the DC/

DC converter modules and their auxiliary parts. The circuit parameters of
selected DC-DC converter topologies for EV battery fast charging appli-
cations is presented in Table 15.2 with a continuous conduction mode of
operation. These design values are the essential components for experi-
mental validation of DC-DC converters.
Table 15.1 Design equations for DC – DC converters.

Converter Inductance (H) Capacitance (F) Duty cycle
Boost DC-DC Vin D DIout Vin
L= C= D= 1 −
Converter ∆i L f s fs Vout Vout
Interleaved Vin D DIout Vin

L phase = C= D= 1 −
2-Phase Boost ∆i L f s fs Vout Vout
DC-DC
Converter
SEPIC-Luo Vin D i L2 Vin
L1 = C1 = D= 1 −
DC-DC ∆i L f s ∆VC1f s Vout
Converter
Vin (1 − D) Iin − Iout (1 − D)
L2 = C2 =
∆i L f s ∆VC2 f s
Table 15.2 Specification of components and parameters used in DC-DC

converters under study.
Symbols Parameters BC IBC SEPIC Luo
Vin Input Voltage (V) 120 120 120
Vout Output Voltage (V) 240 240 240
fsw Switching Frequency (kHz) 20 20 20
ILmax Inductor Current (A) 160 160 160
∆IL Ripple Current requirements 8 8 8
(A)
∆Vout Output Ripple (V) 6 6 6
N Number of Phases 1 2 1
P Rated Power (kW) 52 52 52
D Duty Cycle of operation <0.6 <0.6 <0.5
L Inductor (µH) 120 120 375
C Capacitor (µF) 40 40 20.8
15.6 Control Strategy

The controller for the HESS hybrids the power flow between the battery
pack, SC (auxiliary storage system), and the tractive system is depicted in
Figure 15.10. The controller was designed to ensure the following operat-
ing conditions:
1. The energy required for the tractive motor should always

meets the size of the battery pack.
2. The optimum energy should be drawn from the battery pack
in all operating modes.
3. The hybridization of an auxiliary storage system with its
specified limits.
Whenever the acceleration or brake command is given to the traction

system, the required power (Preq, Ireq) is drawn from the energy storage
system which is developed by the motor for traction. The tractive power
required from the battery pack can be expressed as:
Preq
Pin = (15.5)
ηm
where ηm is the efficiency of the motor drive. When the brake command is
applied, the traction system behaves as a generator and here the regenera-
tive power is needed to utilize and store back to any of the feasible energy
storage in the vehicle. The auxiliary energy storage system and battery pack
are hybridized optimally to supply the required tractive power. The modes
of operations of the power train and its associated power flow control
methods are further discussed in detail.
Standstill Mode
The auxiliary system and the battery pack do not supply power to the trac-
tion system.
Driving
Brake Power
Command Command
Required Power,
Current (Preq, Ireq)
Yes
If Preq < 0 Brake
Traction No
Yes
PSC = PSCrated
If Ireq > Ibat_rated PBAT= Pcomm - PSC
Hybrid
traction
No
Yes No
PSC = 0
If Ireq < Ibat_rated If EBAT < Emin PBAT = Preq
Yes
No
Preq = PBAT + PSC
IL = ISC
If IL < 0 PSC = Pregen
Figure 15.10 Control strategy for HESS.

Hybrid Energy Bidirectional

Storage System DC-DC PMDC
(HESS) Converter MOTOR
Gate
Pulses
V
I
Controller
SoC
Figure 15.11 Closed loop control of HESS.
Braking Mode
The energy drawn from/supplied to the battery pack is suspended and the
SC receives the power available during regeneration.
Traction Mode
1. If the Preq and Ireq are greater than the rating of the battery pack, then the
hybrid traction mode is enabled in which the battery pack is discharged at
its maximum rated current and the remaining current is supplied by the
SC.
2. If the Preq, Ireq is greater than the rating of the battery pack and the %SoC
level of the SC is less than the required value, then the battery pack is oper-
ating at its maximum rated power and the power drawn from the battery is
supplied to the drive train and the SC.
3. If the %SoC level of the SC is maximum, then the battery pack alone sup-
plies Preq and Ireq. In this case, the SC is dedicated to supply only the peak
power requirement during acceleration.
Figure 15.11 shows the block diagram to illustrate the closed loop con-
figuration of the Proposed Hybrid Energy Management System. Based on
the load current of the drive during various modes as mentioned above,
the controller will provide the required gating signals to the bidirectional
converters to utilize the energy sources according to the proposed strategy.
15.7 Results and Discussion

The proposed HEMS is validated using a HESS comprising battery pack
and SC pack feeding a BDC. The converter output drives a PMDC motor
whose specifications are given in Table 15.3. The simulation study is carried
out using MATLAB-Simulink with varying torque for the motor required
for traction, as shown in Figure 15.12. Also, various converters are consid-
ered with different HESS configurations to identify the best suitable con-
figuration and topology for the BDC.
The tractive torque requirement for the study is shown in Figure 15.12
by considering modes of operation as follows:
1. Starting Mode (0 – 2 seconds)

In this mode, the vehicle requires high starting torque and
thus draws more current from the HESS.
2. Cruise Mode (2 – 4 seconds)
The vehicle requires a constant torque during this mode and
draws constant current from the battery.
3. Acceleration Mode (4 – 6 seconds)
If the vehicle needs to overtake, then load torque require-
ment increases and draws more current from the HESS.
4. Brake Mode (6-8 seconds)
During braking, the torque reduces zero by diverting the
energy stored in the motor to SC.
5. Regenerative Mode (8 -10 seconds)
If the vehicle moves down in slope, then the speed of the
traction motor is above the rated speed and the potential
energy stored as the inertia of the vehicle is converted into
regenerative power and is absorbed by the SC.
A) Battery fed Boost Converter

The Simulink model of the battery fed Boost Converter is shown in Figure
15.13. The performance of the battery for various modes of operation is
shown in Figure 15.14. The motor drive requires high starting torque and
hence, high starting current is drawn from the battery. It is observed that
in regenerative mode. the battery current is negative, i.e., the battery is
charged by the regenerative power developed by the traction system. The
specific power density of the battery is low and it takes more time to absorb
the regenerative power, which can be observed from the SoC characteristic
Table 15.3 Specification of traction motor.

S. no. Parameter Value
1 Maximum Battery Voltage 300 V/110 V
2 Peak Power (@ 6500 rpm) 52 kW
3 Continuous Power 30 kW
4 Peak Torque 90 Nm
5 Continuous Torque 50 Nm
Motor Torque (N-m)

100
50
Torque (N-m)
STARTING CRUISE ACCELERATION BRAKING REGENERATION
-50
0 1 2 3 4 5 6 7 8 9 10
Times (S)
Figure 15.12 Motor torque required by drive train.
Controller
Discrete
5e-05 s.
a [A]
S2 [IA] u
[A] fcn
D
S d [D]
g
L1 [U1]
SOC (%) a
[U2]
A- Speed.wm (rad/s)
Current (A) +
g
D
C1 S1 C2 Armature current ia (A)
Voltage (V) – A+ Electrical torque Te (n m)

S
PMDC MOTOR
Battery Pack [IA]
120V, 400Ah
Gate Pulses
[U1]
u1
D [D]
u2
[U2]
Figure 15.13 Simulink model for battery fed boost converter.

BIDIRECTIONAL BOOST CONVERTER WITHOUT SUPER CAPACITOR RESPONSE

100 SoC (%)
SoC (%)
99.5
99
400
Current (A)
Current (A)
200
0
150
Voltage (V)
Voltage (V)
100
50
0
6
Power (W)
Power (W)
4
2 REGENERATION
0 STARTING CRUISE ACCELERATION BRAKING
0 1 2 3 4 5 6 7 8 9 10
Times (S)
Figure 15.14 Performance of battery in battery fed bidirectional boost converter.
B) HESS fed Boost Converter

The Simulink model of the HESS fed boost converter is shown in Figure
15.15. The voltage, current, and SoC of the battery and SC are shown in
Figure 15.16 and Figure 15.17, respectively. The motor drive requires high
starting torque to accelerate the traction system and hence, draws a high
starting current of 468A from the battery pack. While in cruising and
accelerating modes, the average current drawn from the HESS reduces
to 190 A and 200A, respectively, which is also supplied by the battery, as
shown in Figure 15.16. During braking, the controller hybridizes the SC to
Controller
a [A]
S2 [IA] u b [B]
[A] fcn
D
S
g d [D]
L1
SOC (%) a
[U1]
[U2]
A- Speed.wm (rad/s)
Current (A) +
g
D
C2 Armature current ia (A)

C1 S1
A+ Electrical torque Te (n m)
Voltage (V) –
S
PMDC MOTOR
Battery Pack [IA]
120V, 400Ah
[B] Gate Pulses

[U1]
u1
D [D]
u2
SOC (%) b
[U2]
Current (A) +
Voltage (V) –
Ultra Capacitor Bank

120V, 33F
Figure 15.15 Simulink model for HESS fed boost converter.

BIDIRECTIONAL BOOST CONVERTER – BATTERY RESPONSE

100 SoC (%)
SoC (%)
99.5
99
0 1 2 3 4 5 6 7 8 9 10
Current (A)
400 Current (A)
200
0
0 1 2 3 4 5 6 7 8 9 10
150
Voltage (V)
100 Voltage (V)
50
0
0 1 2 3 4 5 6 7 8 9 10
Times (S)
Figure 15.16 Performance of battery in HESS fed bidirectional boost converter.
BIDIRECTIONAL BOOST CONVERTER – SUPER CAPACITOR RESPONSE

14 SoC (%)
12
SoC (%)
10
8
6
0 1 2 3 4 5 6 7 8 9 10
0 Current (A)
Current (A)
-100
-200
-300
-400
0 1 2 3 4 5 6 7 8 9 10
20 Voltage (V)
Voltage (V)
15
10
0 1 2 3 4 5 6 7 8 9 10
Times (S)
Figure 15.17 Performance of SC in HESS fed bidirectional boost converter.
absorb the regenerative power instantaneously. The role of the SC in this

mode is only for collecting the regenerative power and hence, the current
drawn from the battery is zero as illustrated in Figure 15.17.
C) Battery fed Interleaved Boost Converter

The Simulink model of a battery fed Interleaved Boost Converter is shown
in Figure 15.18. The performance of the battery is shown in Figure 15.19,
which consists of the SoC, current, voltage and power of the battery. The
motor drive requires high starting torque to accelerate the traction system,
hence a high starting current of 195 A is drawn from the battery which
S4 Controller
D
S
g [A]
a
L2
S2 [U1] [IA] u
[A] fcn
D
S d
g
[D]
L1
[U1] [U2]
[U2]
SOC (%) a
A- Speed.wm (rad/s)
g
D
Armature current ia (A)
g
D
Current (A) + C1 S1 S3 C2 A+ Electrical torque Te (n m)
S
Voltage (V) –
PMDC MOTOR [IA]
Battery Pack
120V, 400Ah
Gate Pulses
[U1]
u1
D [D]
u2
[U2]
Figure 15.18 Simulink model for battery fed interleaved boost converter.
BIDIRECTIONAL BOOST CONVERTER WITHOUT SUPER CAPACITOR RESPONSE

100 SoC (%)
SoC (%)
99.5
99
400 Current (A)
Current (A)
200
0
150
Voltage (V)
Power (W) Voltage (V)
100
50
0
6 Power (W)
4
2 REGENERATION
0 STARTING CRUISE ACCELERATION BRAKING
0 1 2 3 4 5 6 7 8 9 10
Times (S)
Figure 15.19 Performance of battery in battery fed bidirectional inter leaved boost
converter.
is half compared to that drawn by the Boost converter. In cruise mode,

the current drawn from the battery is 1/3rd of the starting current and the
current required for accelerating mode also reduced to 40% of its start-
ing current due to reduction in current ripples. The SoC of the battery
pack during braking is found to be higher than that with boost converter.
During braking and regenerative modes, the controller enables the battery
pack to absorb the power, as illustrated in Figure 15.19.
D) HESS fed Interleaved Boost Converter

The Simulink model of the HESS fed interleaved boost converter is shown
in Figure 15.20. The SC in the HESS absorbs the power developed during
regenerative and braking mode. The drive current requirements are the
S4 Controller
D
S
g a [A]
L2
S2 [U1] [IA] u b [B]
[A] fcn
D
Battery Pack S
g d [D]
120V, 400Ah L1 [U1] [U2]
[U2]
SOC (%) a
A- Speed.wm (rad/s)
g
D
g
D
Current (A) + C1 S1
S3 C2 A+ Electrical torque Te (n m)
S
Voltage (V) –
PMDC MOTOR [IA]
[B]
SOC (%) a Gate Pulses

[U1]
u1
D [D]
Current (A) + u2
[U1]
Voltage (V) –

120V, 33F
Figure 15.20 Simulink model of HESS fed interleaved boost converter.
same as in the previous case. The performance of the SC is shown in Figure

15.21 and Figure 15.22. It is observed that during various modes of opera-
tion of the drive, the current drawn from the battery reduces and the peak
current handled by the SC is also reduced during starting and braking.
Hence, the SoC of the SC is raised from 6.5% to 8.5% unlike in the boost
converter.
INTERLEAVED BPPST CONVERTER – BATTERY RESPONSE

100 SoC (%)
SoC (%)
99.9
99.8
200 Current (A)

Current (A)
150
100
50
0
150
Voltage (V)
Voltage (V)
100
50
0
0 1 2 3 4 5 6 7 8 9 10
Times (S)
Figure 15.21 Performance of battery in HESS fed bidirectional inter leaved boost
converter.
INTERLEAVED BOOST CONVERTER – SUPER CAPACITOR REPONSE

8.5 SoC (%)
8
SoC (%)
7.5
7
6.5
0 Current (A)
Current (A)
-100
-200
-300
Voltage (V)
10 Voltage (V)
5
0
0 1 2 3 4 5 6 7 8 9 10
Times (S)
Figure 15.22 Performance of SC in HESS fed bidirectional inter leaved boost converter.
E) HESS fed SEPIC-Luo Converter

The Simulink model of a HESS fed SEPIC-Luo converter is shown in Figure
15.23. The battery and SC performance are shown in Figure 15.24 and
Figure 15.25. This converter reduces the starting current by 15% as com-
pared to an interleaved boost converter, but the current drawn for cruising
is increased three times as compared to the interleaved boost converter.
During cruise mode, the output current ripples in the SEPIC converter is
high and hence, increases the current drawn from the battery. The SoC of
the battery pack during braking is found to be slightly inferior to HESS fed
IBC.
Controller
a [A]
[IA] u b [B]
S2 fcn
[A]
D
Battery Pack S
g d [D]
120V, 400Ah L1 [U1] C1
[U2]
SOC (%) a
A- Speed.wm (rad/s)
g
D
Current (A) + Cin S1 L2 C2 Armature current ia (A)

S
Voltage (V) –
PMDC MOTOR [IA]
[B]
Gate Pulses
SOC (%) a
[U1]
u1
D [D]
Current (A) + u2
[U2]
Voltage (V) –

120V, 33F
Figure 15.23 Simulink model of the HESS fed SEPIC-Luo converter.

SEPIC-LUO CONVERTER BATTERY RESPONSE

100
SoC (%)
99.8
SoC (%)
99.6
99.4
200 Current (A)

Current (A)
150
100
50
0
136
Voltage (V)
Voltage (V)
134
132
130 STARTING CRUISE ACCELERATION BRAKING REGENERATION
130
0 1 2 3 4 5 6 7 8 9 10
Times (S)
Figure 15.24 Performance of battery in HESS fed bidirectional SEPIC-Luo converter.
SEPIC-LUO CONVERTER – SUPER CAPACITOR RESPONSE

8 SoC (%)
SoC (%)
7.5
7
6.5
0 Current (A)
Current (A)
-50
-100
-150
-200
18
Voltage (V)
Voltage (V)
16
14
12
10
0 1 2 3 4 5 6 7 8 9 10
Figure 15.25 Performance of SC in HESS fed Bidirectional SEPIC-Luo converter.
F) HESS fed Dual Boost Converter

The Simulink model of a HESS fed Dual Boost Converter (DBC) based on
parallel converter configuration is shown in Figure 15.26. The performance
characteristics such as SoC, current, and voltage of the battery and SC for
the HESS fed DBC is shown in Figure 15.27 and Figure 15.28, respec-
tively. In this configuration, the controller enables the SC at peak power
requirement and charges when the peak current varies above and below
the threshold value of the battery discharge current. It reduces the impact
of the peak current and enhances the life span of the battery. Whenever the
motor current exceeds the threshold current value, the controller hybrid-
izes the SC to supply the peak current. In this method, the demand sup-
plied by the battery is reduced compared to other methods and thus, it
reduces the size of the battery pack required.
Controller
a [A]
[A]
S2 [IA] u
fcn
b [B]
D
S
Battery Pack g d [D]
120V, 400Ah L1 [U1]
[U2]
SOC (%) a
A- Speed.wm (rad/s)
g
D

Current (A) + C1 S1 C2
S
Voltage (V) –
3.3kW, 240V, 1500epm [IA]
PMDC MOTOR
Gate Pulses - Converter 1

[U1]
S4 u1
[B] D D [D]
S u2
g
[U2]
SOC (%) a L2
L2 [U1]
[U2]
Gate Pulses - Converter 2
Current (A) + [U3]
g
D
u1
C3 S3 C4 u2
D [D]
Voltage (V) – [U4]
S

120V, 33F
Figure 15.26 Simulink model of HESS fed dual boost converter.
BOOST CONVERTER – BATTERY PERFORMANCE

100 SoC (%)
99.95
SoC (%)
99.9
99.85
99.8
Current (A)
150
Current (A)
100
50
0
140
Voltage (V)
Voltage (V)
138
136
134 STARTING CRUISE ACCELERATION BRAKING REGENERATION
132
0 1 2 3 4 5 6 7 8 9 10
Times (S)
Figure 15.27 Performance of battery in HESS fed dual boost converter.

BOOST CONVERTER – SUPER CAPACITOR RESPONSE

96 SoC (%)
99.95
SoC (%)
95
94.5
94
93.5
150 Current (A)
Current (A)
100
50
0
-50
120
Voltage (V)
118 Voltage (V)
116
114
0 1 2 3 4 5 6 7 8 9 10
Times (S)
Figure 15.28 Performance of SC in HESS fed dual boost converter.
15.8 Conclusions
In this chapter, the design and analysis of various bidirectional converters
for HESS in EV has been discussed in detail. The average and peak power
requirement of the drive train is supplied by the Battery and SC, respec-
tively. Passive parallel configuration of HESS is verified using various
converters such as BC, Sepic-Luo, and IBC. The parallel converter config-
uration of HESS is verified using DBC. Even though the SEPIC-Luo con-
verter reduces the peak power requirement of the battery pack compared
to IBC, the average current drawn by the SEPIC-Luo converter during
the cruise mode is not under the specified limits. It is observed that the
IBC topology is desirable compared to other topologies in passive parallel
HESS. As DBC uses parallel converter topology, it provides the decoupling
between the sources and reduces the stress on the switching devices. The
use of SC in the proposed HESS helps in reducing the peak power require-
ment of the battery from 58.96 to 15.07 kW with DBC as shown in Table
15.4. This strategy shall give a new hope to the EV industries for design
with small size storage systems.
Table 15.4 Peak power requirement of battery pack for different converters.
Terminal
voltage
Starting at peak Peak Average
current current power power
S. no. Converter (A) (V) (kW) (kW)
1. Boost Converter 468 126 58.96 24.7
(BC)
2. Interleaved Boost 195 146 28.47 7.5
Converter
(IBC)
3. SEPIC-Luo 168 136 22.85 23.28
Converter
4. Dual Boost 110 137 15.07 6.9
Converter
(DBC)
References
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16
Design of Rare Earth Magnet
Free Traction Motor
Akhila K. and K. Selvajyothi*
Indian Institute of Information Technology Design and Manufacturing,

Kancheepuram (IIITDM Kancheepuram), Chennai, Tamil Nadu, India
Abstract
The global climatic scenario is confronting a highly alarming state which has
pressed the countries around the globe to implement thoughtful actions in this
regard. Transportation sector, being the major contributors to environmental pol-
lution has witnessed a radical revamp. The greenhouse gases present in the tail
pipe emissions from the internal combustion engine (ICE) powered vehicles is one
among the root causes for global warming. Additionally, the availability of fossil
fuels is also limited which has posed a serious threat to the future of ICE powered
vehicles. This has marked a resurgence in the automotive industry-electrification
of vehicles.
Traction motor forms the main constituent in electric vehicle. Commercially
speaking the motor should be efficient, light weight and less costly so that the
large-scale manufacturing turns out to be viable and successful. The key candi-
dates that are being utilized in market as traction motor are: Interior permanent
magnet synchronous motor (IPMSM) and Induction motor (IM). Reluctance
motors are the less popular contenders. Although IPMSM’s possess higher torque
density, efficiency when compared to other motors the drastic increase in cost of
rare earth magnets have paved the way for using rare earth magnet free traction
motor. IM’s are limited by the reduced efficiency which lead to excessive heating
and lower bearing life.
This chapter highlights the significance of switching to a rare earth mag-
net free traction motor and a brief comparison among the motor choices is
also presented. Since in this machine the torque produced entirely depends
463
on the reluctance mechanism, the appropriate design of the rotor is essential.

Electromagnetic design of SynRM with different parameters influencing the
design is described in detail. Electromagnetic analysis is performed by using
finite element analysis (FEA) tool ANSYS Maxwell 2D. An overview of liter-
ature discussing the design aspects, torque ripple minimization is also high-
lighted. The complete performance curves of the machine along the entire
speed range helps in visualizing the machine features. ANSYS Motor-CAD is
utilized for obtaining the torque speed curve. The essential outcome from the
chapter is that the design presented meets the efficiency target of 95%. The
costing analysis presented along with the efficiency clearly depicts that SynRM
proves to be a promising and strong competitor with reference to IPMSM’s.
The conclusion gives a comprehensive overview of the motor along with the
advantages, disadvantages and the measures that can be utilized further to
alleviate the demerits.
Keywords: Anisotropy, drive cycle, flux density, flux linkage, global warming,
reluctance, rotor, torque ripple
16.1 Introduction
The global climatic scenario is in an alarming condition which has

pressed all the nations around the globe to implement thoughtful
actions in this regard. The transportation sector has witnessed a major
revamp as it is one of the significant contributors to environmental
pollution. Conventionally, the vehicles are powered by internal com-
bustion engines (ICEs) whose prime source of energy is derived from
fossil fuels. The greenhouse gases present in the tail pipe emissions
from these vehicles are the root cause for global warming which has
worsened the state of the environment. Additionally, the availability of
fossil fuels is also limited which has posed a serious threat to ICE pow-
ered vehicles. This has marked a new era in the automotive industry’s
electrification of vehicles.
Electric vehicles possess the following advantages when compared to
ICEs:
• Higher efficiency
• Eco-friendly
• Lesser maintenance
• Better performance
Design of Rare Earth Magnet Free Traction Motor 465
Classification of Electric Vehicles

Electric vehicles can be classified under two main heads: hybrid electric
vehicles (HEV) and all electric vehicles (AEV) [1]. HEVs utilize a combi-
nation of ICEs as well as electric motors as the propulsion sources, whereas
AEVs make use of motors alone. This advancement in the transportation
sector is given in Figure 16.1.
The hybrid electric vehicles use a combination of ICE along with a motor
or generator and a battery pack, bringing a multidisciplinary approach into
picture. The hybridization factor (HF) is a significant index as far as an
HEV is concerned. It gives the ratio of power produced by the motor with
respect to the total power requirement.
PEM P
HF = = EM
PEM + PICE PHEV
where PEM is the maximum power produced by the motor and PHEV is the
total power contributed both by the motor and ICE. Based on HF, the
hybrid vehicles can be classified as: micro hybrid vehicles (hybridization
factor < 0.1), mild hybrid vehicles (0.1< hybridization factor < 0.25), power
assisted (0.25 < hybridization factor < 0.5), and plug-in hybrid vehicles
(hybridization factor > 0.5).
Fuel Battery Fuel

Battery
Motor/ Engine
Engine Generator Motor/Generator
Transmission Transmission
Transmission
ICE HEV AEV
Figure 16.1 Resurgence of electrification in automotive industry.

The three major classifications in hybrid electric vehicle power train

architecture are:
• Series configuration: The wheels receive the required energy

from the motor alone, as given in Figure 16.2. The role of
ICE here is solely to recharge the battery through the gen-
erator. This system demands a larger battery pack and a
higher power rating motor which increases the investment
requirement for the system. The series configuration is used
by Mercedes Citaro bus and MAN-Lions City Hybrid bus,
TEMSA Avenue Hybrid bus, and Tesla ultra-light rail [1].
• Parallel Configuration: It uses the power from both electric
motors and ICE to put the wheels in motion via a conven-
tional transmission, as given in Figure 16.3. The battery will
be recharged by the generator that is driven by ICE and also
from regenerative braking mode. This configuration finds
its applications in Honda Insight, Ford Escape Hybrid SUV,
and Lexus Hybrid SUV [1].
Power
Engine Generator Motor
Convertor
Differential
Battery Gear
Figure 16.2 Series configuration: HEV.
Engine
Regenerative
braking
Power Motor/Generator
Battery
Convertor Differential
Gear
Figure 16.3 Parallel configuration: HEV.

Engine
Planetary
Generator Gear
Power Motor/
Battery
Convertor Generator
Differential
Gear
Figure 16.4 Series/parallel configuration: HEV.
• Series/Parallel: A series/parallel configuration incorporates

the characteristics of a series, as well as parallel configu-
rations, and decoupling of power is also achieved here as
given in Figure 16.4. The planetary gears are provided which
connect both the ICE and motor. This mode is used by the
Toyota Prius and is being experimented in Nissan and Fiat
[1].
The major goal of this chapter is to design a traction motor for an AEV.
The main subsystems of an AEV are [3]:
• Electric propulsion subsystem

• Battery management subsystem
• Auxiliary equipment subsystem
The electric propulsion system consists of an electric motor playing the

role of a propeller which is excited by a power electronics converter in
accordance with the traction requirements. The power electronic converter
operates based on the control algorithm implemented in the controller,
which in turn receives the real time inputs from the driver such as signals
from the accelerator and brake. The energy management system or battery
management system is another important part which monitors the battery
pack and its status, including details like: state of charge, discharge current,
and terminal voltage. The auxiliary subsystem takes care of the additional
amenities in the vehicle including the ventilation and air conditioning.
So, fundamentally it is an interplay of power electronics and mechanical
transmission which delivers power from the motor to the driving wheels
as depicted in Figure 16.5.
Electric propulsion subsystem
Vehicle Power Mechanical

Accelerator Motor
controller controller transmission
Brake
Auxiliary Power
power steering
Battery unit
Battery supply unit
management
system
Ventilation & Auxiliary
Battery Management Air subsystem
system conditioning
unit
Figure 16.5 Subsystem composition of AEV.
16.2 Comparison Among Traction Motor Choices

With the electric motor being the key player in the propulsion subsystem
of electric vehicles, choosing the appropriate motor is of prime importance.
Following are the major requirements for a traction motor [4]:
• Maintaining high efficiency over entire speed range

• High torque or power density
• Capability to produce high torque for meeting starting
requirements
• High speed capability
• Good dynamic performance
• Cost effective
• Low torque ripple
• Rugged and robust
The performance of electric vehicles is quantified by parameters like

gradeability, maximum vehicle speed, and acceleration time. Gradeability
shows the capability of the vehicle for hill climbing or, in other words, a
given slope angle. Acceleration time tells about the dynamic behavior in
terms of the time consumed by the vehicle to deliver the required torque.
This not only depends on the motor specifications but also relies on the
controller characteristics. The highest speed achievable that can be attained

by the vehicle has direct relation to the motor speed range. The torque
speed characteristics for traction purposes is given below in Figure 16.6.
An increase in speed of the supply voltage to the motor also rises until
base speed. The region until the base speed is known as the constant torque
zone or low speed zone and is used to meet the vehicle starting as well as
the gradient climbing requirements. Once the motor attains base speed,
the supply voltage reaches its maximum limits. Beyond the base speed, the
motor is operated by flux weakening so that the voltage limits can always be
maintained. This region is known as the constant power zone or high speed
zone. A significant figure of merit concerning the torque-speed character-
istics of motors is the ratio of maximum speed to the base speed, known as
the constant power speed ratio (CPSR). The traction torque-speed graph in
Figure 16.6 clearly depicts the need of increased torque in the region close
to zero speed and higher power in the maximum speed zone. The motor
chosen should have a wide efficiency region, zero tail pipe emissions, and
lesser noise when compared to ICE powered vehicles [3].
The electromagnetic design of the traction motor should be such that it
satisfies three important criteria: higher efficiency, lower cost, and light in
weight. This section gives a brief insight into the different motors that are
being used commercially, weighing their merits and demerits. The traction
choices adopted by the automotive companies are given in Table 16.1 [5]
in chronological order.
Torque (p.u.) High torque

1
0.8
High power
0.6
0.4
High efficiency High speed

0.2
zone
1 2 3 4 5 Speed (p.u.)
Base speed
Figure 16.6 Torque-speed requirement of electric vehicles.

Table 16.1 Traction motor choices of commercial automotive companies.

Companies/model Year Electric motor used
All EV Models From 1839-1989 DCM
Lucas 1983 DCM
Conceptor G Van 1989 DCM
VW City Stormer 1989 PMSM
Fiat Panda Elettra 1990 DCM
Bertone Blitz 1992 DCM
Peugeot/Berlingo-Saxo 1992 DCM
BMW325 1992 PMSM
BMW316i 1995 PMSM
Toyota Prius 1997-2004 & 2010-2011 PMSM
Honda EV Plus 1997 PMSM
Peugeot 106-Partner 1999 DCM
Honda Insight 2000 PMSM
Reva EV 2001 DCM
Honda Civic HEV 2003-2013 PMSM
Ford Escape 2005 PMSM
Kewet Buddy 2007 DCM
Tesla Roadster 2008 IM
Mitsubishi i-MiEV 2009 PMSM
Chrysler Aspen 2009 PMSM
Volvo P70 PHEV 2009 PMSM
Mini E 2009 IM
Micro Vett Fiat 500 2009 IM
Ford Focus EV 2010 IM
(Continued)
Table 16.1 Traction motor choices of commercial automotive companies.

(Continued)
Companies/model Year Electric motor used
REVA NXR 2011 IM
Audi A8 2012 PMSM
Volkswagen Jetta 2013 PMSM
Chevrolet Malibu Eco 2013 IM
Volkswagen Jetta 2013 PMSM
Audi E-Tron 2019 IM
Jaguar I-Pace 2020 PMSM
TATA NEXON EV 2020 PMSM
Hyundai KONA Electric 2020 PMSM
Direct current (DC) machines were deployed as traction motors in the

early twentieth century. The separately excited DC motors were the popu-
larly used DC motors for traction purposes. They possess advantages like
technological maturity and simple control due to the inherent orthogo-
nality between armature and field windings [1]. Despite of the aforesaid
merits, their popularity has reduced over the period of time due to the
requirement of commutator and brushes, which is a bottleneck as far as
compactness and higher efficiency are concerned.
Induction machines (IM) were the next widely used choice as a traction
motor which is a magnet free motor [2, 3]. The salient features for IMs are
ruggedness, robustness, low cost, simple open loop control, free from com-
mutator, and ability to operate in an aggressive environment. The widely
used induction motor choice is the squirrel cage induction motor. By reg-
ulating the flux in the machine, it can be designed to operate with higher
efficiency in a wide operating range. The IMs were overpowered by the
very popular permanent magnet synchronous motors (PMSMs) because
of their higher efficiency, power density, and power factor.
Another popular candidate among the traction motors is the switched
reluctance motor (SRM) which has the feature of double saliency. Torque
is caused due to the reluctance phenomenon. Similar to IM, the reluctance
motors are also rugged and free from rare earth magnets. Unlike other
machines, the reluctance principle is utilized here for the production of

torque. The stator windings are excited in sequence, which demands a
complex rotor position mechanism at low speeds. The excitation method
followed gives rise to a higher torque ripple and acoustic noise. The con-
centrated winding is adopted in stator and the feasible slot pole combina-
tions for stator and rotor are less in number.
All the above choices were surpassed by the permanent magnet syn-
chronous motors (PMSMs), which are more efficient and power dense
than all the other choices. The presence of rare earth magnets is the
major reason behind the dominance of PMSMs [6]. Depending upon the
placement of the magnets, PMSMs are classified into two types: surface
mounted (SPMSM) and interior (IPMSM). SPMSMs have limited over
load torque capability and higher permanent magnet losses at high speed.
IPMSMs have better overload torque capability and flux weakening perfor-
mance if designed with higher saliency. Demagnetization is an important
issue which should be taken care in these motors. China, being the sole
producer of rare earth magnets, has the monopoly in the supply of this
material [7]. The geo-political concerns have caused a sharp spike in the
cost of rare earth magnetic materials which has reduced the overwhelming
popularity of PMSM.
Since cost is one of the major criteria in the design of traction motors,
it becomes highly significant that motor design should be cost effective
so that large-scale production will be viable and economical. It is in this
context that researchers have started probing for a rare earth magnet free
solution which will reduce the cost aspect of the traction motor. This sce-
nario has paved the way for increased usage of reluctance and induction
motors as traction choice. Synchronous reluctance motors come under
the category of reluctance motors where torque production is by reluc-
tance mechanism. Although synchronous reluctance motors (SynRM)
came into existence by 1929, these motors were not that widely used for
traction applications. The absence of windings and cage in the rotor has
reduced the rotor losses compared to an induction motor. Consequently,
the rotor will be at lower temperatures, enhancing the bearing life. The
magnets are also absent in SynRM [2], which has made the motor safe
from a demagnetization standpoint. Irrespective of these advantages, the
motor is limited by reduced power factor and increased torque ripple. The
succeeding section will derive the power required for the traction motor
from a vehicle dynamics perspective which will be followed by in detail
design methodology.
16.3 Motor Peak Power Calculation Based on Vehicle

Dynamics
The various forces acting on the vehicle while travelling on the road are
considered for calculating the peak power of the traction motor. Here, the
forces are first described briefly and then calculations are provided. Figure
16.7 indicates the various forces acting on the vehicle [3].
• Rolling Resistance: It arises from hysteresis present in tire

material. The rolling resistance coefficient is decided by the
nature of the surface of the road, tire temperature, tire pres-
sure, and so on.
Frr, rolling resistance force = μrr ∗ m ∗ g (16.1)
where μrr is the rolling resistance coefficient, m (kg) is the

mass of the vehicle, and g (m/s2) is the acceleration due to
gravity.
• Aerodynamic Drag: The force experienced by the vehicle
when it traverses at a particular speed on the road. This is
due to the pressure difference created because of the vehi-
cle movement. This force is composed of two components:
shape drag and skin force. The shape drag is because of the
pressure difference created due to the vehicle movement.
Skin force is because of the difference in the velocity of the
Direction of
motion
Fad
Tractive force, Ft
Frr
Fg
m*g*cosα
m*g α Frr
Figure 16.7 Forces acting on vehicle moving on slope.

air molecules in the close proximity of the vehicle and away

from it. The aerodynamic drag coefficient varies with the
shape of vehicle body.
Fad, aerodynamic drag = 0.5 ∗ Cd ∗ ρ ∗ A ∗ (V + Vw)2 (16.2)
where Cd is the aerodynamic drag coefficient, which is a

signature of the shape of vehicle, ρ (kg/m3) stands for the
air density, A (m2) is the frontal area of the vehicle, V (m/s)
is the vehicle velocity, and Vw (m/s) is the element of wind
speed in the direction of vehicle movement.
• Grading Resistance: It arises from the weight component
of the vehicle when it is climbing uphill or downhill. This
force opposes the vehicle motion when travelling uphill and
favors the motion when travelling downhill.
Fg, grading resistance = m ∗ g ∗ sinα (16.3)
where α (deg) is the gradient angle.
Table 16.2 Vehicle parameter used for peak power calculation of motor.
Parameter Unit Value
Wheel Diameter Inches 19
Gross Vehicle Weight kg 1521
Acceleration Due to Gravity m/s 2
9.81
Vehicle Speed at Slope km/hr 49.85
Rolling Resistance Coefficient Constant 0.007
Aerodynamic Drag Coefficient Constant 0.28
Slope of Ramp Degree 22
Number of Powered Wheels Number 4
Density of Air kg/m3 1.22
Transmission Efficiency Percentage (%) 95
Gear Ratio NA 7.938
Consolidating all the above forces, the total tractive force which has to
be overcome by the vehicle can be determined. The vehicle parameters for a
four wheel passenger car were chosen from [8] and tabulated in Table 16.2.
Using (16.1), (16.2), and (16.3), the rolling resistance, aerodynamic drag,
and grading resistance are calculated as given by (16.4), (16.5), and (16.6).
Rolling resistance = 96.84 N (16.4)
Aerodynamic drag = 75.12 N (16.5)
Grading resistance = 5589.51 N (16.6)
From (16.4), (16.5), and (16.6), the total traction force is obtained as
5761.47 N.
Hence,
Power required = Total traction force * vehicle velocity = 79.780 kW

(16.7)
Torque to be developed by the motor to overcome these resistive forces

as discussed above can be obtained from the total traction force.
Peak torque from motor = (Total traction force*radius of tire)/

Gear ratio (16.8)
= (5761.47*0.24)/7.938 = 175.98 N m
So, as a design target, the peak torque for the motor is assigned as 200
Nm, which is 14% higher than the actual peak torque calculated. This will
act as a buffer in case any increment in the starting torque requirements
occur.
16.4 Operating Principle of SynRM

& Basic Terminologies
The following section will deep dive into synchronous reluctance motors
(SynRM), their operating principle, characteristics, and design method-
ology. In 1923 Kostko [9] tried to establish the basic theory of reluctance
motors by introducing barriers along a quadrature axis. Although these
motors came into existence by 1920’s, the absence of self-starting torque

and lower damping has restricted their usage. Later, in 1990’s, with the
advent of inverter controlled drives, research progressed in field oriented
control and direct torque control of SynRMs, which was initiated by
A. Vagati. For understanding this machine, it is inevitable that the term
anisotropy needs to be familiarized. Construction wise, the stator is com-
prised of distributed windings placed in the inner periphery of the slots
and the rotor has to be designed to bring in anisotropy. The whole idea is
to create a difference in inductances along two axes, the direct (direct axis)
and quadrature (quadrature axis), by varying the flux linkage. The direct
axis is the axis of maximum flux linkage and the quadrature axis is the axis
of minimum flux linkage. For lucid understanding, an illustration is given
in Figure 16.8. Object a is a structure with equal reluctance in any direction
with respect to the magnetic field (Ѱ). As shown, object b has dissimilar
dimensions along the d and q axes resulting in different reluctances along
both these axes. The object has a tendency to always align in the path of
minimum reluctance or, in other words, along the direct axis. If the direct
axis maintains a constant angular displacement with the field direction,
called load angle δ, then torque production becomes possible.
From the above description it is understood that a high saliency ratio,
which is the ratio of direct axis inductance to quadrature axis inductance,
is the most important term related to torque production. In this section
the equivalent circuit and basic terminologies are introduced. The stator
winding used in SynRM is similar to the conventional distributed wind-
ing used in PMSM as well as IM. The basic Park’s Transformations can be
ψ, Magnetic field
q axis
d axis
δ
Object b
Object a
Figure 16.8 Illustration of reluctance principle.

Rs Lsl is im
ics
em
v Rcms Lm Rcmr dλm/dt
Figure 16.9 Equivalent circuit of SynRM.
used to explain the operation of the motor. The difference in the d and q
equations when compared to PMSM or IMs d, q model is that SynRM does
not use field windings and a rotor cage. The machine can be operated from
a standstill by controlling an inverter. The equivalent circuit of SynRM is
provided in Figure 16.9 [10].
From the equivalent circuit [11], the terminal voltage is
v = em+ Rsis + jωLslis (16.9)
The induced voltage can be calculated as:
dλm
em = + jωλm (16.10)
dt
v is the terminal voltage vector = vd + jvq (16.11)
λm is the air gap linkage flux = λdm + jλqm (16.12)
Lsl is the total winding leakage inductance.

Rs is the phase winding resistance.
is = isd + jisq where isd and isq are the d,q components of stator current.
ω is the electrical angular velocity of the reference frame.
dλm
Considering a steady state condition, = 0, so from (16.10), em = jω
λm = jω (λdm + jλqm). dt
The direct axis flux is not only dependent on the stator current along the
direct, axis but also on the quadrature axis component. The quadrature
axis flux can be considered as dependent on the quadrature axis current
alone with reasonable accuracy. The flux linkages are functions of the rotor
position as well.
λdm= f(λdm, λqm, Υ) (16.13)
λqm= f(λdm, λqm, Υ) where Υ is the rotor position. (16.14)
Electromagnetic torque is a resulting force caused due to the inter-

play between air gap flux and magnetizing current. Hence, torque can be
derived with the help of a vector diagram, as shown in Figure 16.10.
3 P
= T = ⋅ Eλm im ) (16.15)
2 2
3 P
= ⋅ (| λm || im | )sinβ (16.16)
2 2
3 P
= ⋅ (λdmiqm − λqmidm ) (16.17)
2 2
3 P
= . .( Ldm − Lqm )idmiqm (16.18)
2 2
3 P
= . .( Ldm − Lqm )Im2 sin2θ (16.19)
2 2
where Ldm is the magnetizing direct axis inductance, Lqm is the quadrature
axis inductance, β is the angle between λm and im, θ is the angle between im
and direct axis (current angle) (Figure 16.10), and P is the number of poles.
(16.19) shows that the torque produced depends upon the saliency ratio
for a given current and current angle, θ.
Internal power factor is calculated as:
π 
IPF = cos(ψ i ) = cos +δ −θ (16.20)
2 
jωλm Vq
V
Rsis
em is ics
iq
im
δ
ψi
λ
λq
θ β
λm
λqm
δ
Vd id λdm λd
d
Figure 16.10 Vector diagram of SynRM.
 π  (16.21)
= cos  tan −1 tan + δ −θ 
  2 
Using the trigonometric relations, tan (a-b) = (tan a – tan b)/(1+tan a*

π 
tan b) and tan + δ = − cot δ
2 
= cos (tan−1((ξcotθ + tanθ)/ (ξ − 1) (Using cot δ = ξ/ tan θ)
(16.22)
  ξ −1    1 
= cos  cos −1  metry identity ,tan −1 x = cos −1 
   Using trigonom 
  ξ 2
1    1 + x 2 
 +

  sin2θ cos 2θ   (16.23)
sin(2θ )
= (ξ-1) (16.24)
2(tanθ + ξ 2 cotθ )
Ldm
where ξ = is the saliency ratio and ψi is the angle between im and em
Lqm
and δ is the angle between λm and direct axis, as shown in Figure 16.10.
Similarly, all the other important parameters of SynRM can be derived.
All the relations depict the significance of designing the motor with higher
saliency ratio. (16.19) and (16.20) shows the dependence of torque as well
as the internal power factor on the saliency ratio. SynRM can have a com-
parable performance with respect to the induction motor if it is designed
with the saliency ratio in the range of 7 to 8 [12]. To have an in-depth
understanding about the production of torque, it is mandatory to know
about the air gap flux linkages. The stator leakage inductance and resis-
tance are considered as constant lumped elements. The dynamic and deci-
sive quantities are the flux linkages in direct and quadrature axes.
SynRM is a highly nonlinear motor due to the following aspects:
• Saturation
• Cross coupling
• Slotting
The phenomenon of saturation is very well evident in direct axis flux

linkage, whereas it is not that prominent along the quadrature axis. This is
due to the presence of barriers along the quadrature axis. The ribs are the
ones which give rise to saturation in the quadrature axis. The plots showing
the magnetization along the d and q-axes is given in Figure 16.11, which
λd, λq [Vsec]
0,6
λd (id, iq = 0)
0,5
0,4
0,3
0,2 λd (id, iq = 0)
0,1
id, iq [A]
0
2 4 6 8 10 12 14
Figure 16.11 Flux linkages along d and q-axes showing saturation [12].
demonstrates the magnetization characteristics of SynRM with 10 A exci-

tation current [12].
It can be concluded that saturation affects the direct axis magnetization
significantly when compared to the quadrature axis.
Cross coupling or cross magnetization is another phenomenon which
reduces the flux linkage along the direct axis due to the quadrature axis cur-
rent and similarly, the quadrature axis linkage because of direct axis flux.
This is caused by the common iron part between the d and q axis. Figure
16.12 given below very well depicts the aforesaid phenomenon [13].
The reluctance variation caused due to slotting is depicted in Figure
16.13. As the rotor rotates, the direct axis is subjected to varying reluc-
tance because of the slotted structure in stator (including the stator and
teeth). It can be inferred from the figure below that the direct axis initially
aligned with one stator teeth, on rotation faces slot, and gradually aligns
0.6
λ [Vs]
0.5
λd (id, 0)
0.4
λd (id, 90 A)
0.3
λq (0, iq)
0.2
0.1 λq (90 A, iq)
i [A]
0
0 10 20 30 40 50 60 70 80 90
Figure 16.12 Flux linkage along d and q-axes showing cross coupling [13].
d d d d
Central segment
q q q q
(a) (b) (c) (d)
Figure 16.13 Reluctance variation - slotting effect [14].

with the adjacent teeth. This variation in reluctance causes a flux change
inside the rotor and leads to increased torque ripple. Figure 16.13 shows
the effect of rotor position on flux linkage.
16.5 SynRM Design Concepts: Effect of Design

Parameters on Performance
This section will give in detail explanation on the different parameters
affecting the design of SynRM from a performance perspective. This will
help in providing the prerequisite knowledge before moving to the analyt-
ical design.
a. Number of Poles (P)

The direct axis inductance, Ldm can be considered comparable to the
magnetizing inductance of an induction motor [15]. The quadrature axis
inductance, Lqm, is composed of two terms: one is the inductance caused
due to circulating component of flux, Lqc, and the other arises from flow
through the component, Lqf . The flux components along quadrature axis
are very well captured in Figure 16.14 given below.
The expressions connecting the inductances are given below [15]:
Lqc Π2
The circulating component is = (16.25)
Ldm 12 ∗ nr2
ξk
fk sin ξ
ξk+1
rk
0 ξk ξk+1
Figure 16.14 Components of quadrature axis flux [14].

where nr is the number of segments per pole. It can be understood that Lqc
is not dependent on pole pair number but has inverse proportionality with
the number of segments per pole.
As far as the flowing component, Lqf, is concerned, it has linear depen-
dence on the pole pair number and an inverse relation with barrier length
along quadrature axis, la.
Lqf  1
= constant*P*g*   (16.26)
Ldm  la 
where g is the air gap. So, to achieve a higher saliency ratio, the suitable
combination is to have a higher number of segments per pole along with a
lower pole number.
b. Number of Barriers or Layers (nr)

The number of barriers or layers has a significant impact on the saliency
ratio. As the number of layers increases, there is profound impact on
quadrature axis inductance and no significant impact is observed on direct
axis inductance [16]. The Figure 16.15 clearly shows the impact.
c. Insulation Ratio (kwq)

The insulation ratio, defined as ratio of insulation width to iron width, is
another key parameter in further optimizing the performance of SynRM
[11]. There is an optimum range for the insulation ratio which will give a
higher saliency ratio. Figure 16.16 shows that the difference between direct
and quadrature axes inductance is maximized when the insulation ratio is
in the range of 0.2 to 0.6.
d. Tangential and Radial Rib Width

The impact of tangential and radial ribs was investigated in [17]. With an
increase in rib width the direct axis inductance decreases due to the cross
magnetization effect of the quadrature axis. More importantly, the width
is decided by the structural strength of the iron in ribs when the motor
rotates at higher speeds. Figure 16.17 gives the variation of inductance ver-
sus the rib width.
e. Air Gap Length

When the air gap is decreased, the direct axis inductance increases and
quadrature axis inductance reduces. The direct axis inductance increases
because of the reduction in reluctance and quadrature axis inductance
1.2
0.8
Ld, mH × 1.0e2
0.4
0
0 0.75 1.50 2.25 3.00
Number of layers × 1.0e1
(a)
1.6
Lq, mH × 1.0e1
1.2
0.8
0.4
0
0 0.75 1.50 2.25 3.00
Number of layers × 1.0e1
(b)
Figure 16.15 Impact of number of layers on d and quadrature axis inductance [16].
1
Lmd, Lmq and Lmd – Lmq (p.u.)
Lmd
0.8
Lmd – Lmq
0.6
0.4
Lmq
0.2
0
0 0.2 0.4 0.6 0.8 1
Kw
Figure 16.16 Impact of insulation ratio on d and quadrature axis inductance [11].
95 9
80 8
× × × × × × × ×
65 7
inductance ratio, Ld/Lq

inductance, mH
50 6
35 5
20 4
5 3
0·2 0·4 0·6 0·8 1 1·2 1·4 1·6 1·8 2 2·2
rotor web width, mm
Effect of web width on inductances of RSM

Id = 10 A; Iq = 17.4 A; actual web width = 2.0 mm
Ld
× × Ld – Lq
Ld/Lq
Lq
Figure 16.17 Impact of tangential and radial ribs on d and q–axis inductance [17].
reduces due to the cross magnetization effect of direct axis flux on the
quadrature axis [17]. So, to obtain a higher saliency ratio, a lower air
gap length is recommended. But, the minimum air gap that can be used
depends upon the manufacturing tolerances. The effect of variation in air
gap length is given below in Figure 16.18.
f. Control Aspects of SynRM

To completely understand SynRM along with the design concepts some
knowledge is required in the control aspect too. Maximum torque per
ampere (MTPA) is the control method used here wherein the utmost torque
can be achieved with a given value of current. Hence, MTPA becomes the
optimum method for excitation. The electromagnetic analysis is carried
out by using a current source so that the current angle can be exactly con-
trolled. The relation between current angle and electromagnetic torque
is given in (16.19). The equation shows that the torque attains its maxi-
mum value at a current angle of 450 [18, 19]. Saturation is a serious issue in
SynRM. So, to compensate for the saturation present, the current angle has
100 9
85 8
×
×
inductance ratio, Ld/Lq

70 × 7
×
inductance, mH
×
×
55 × 6
×
40 5
25 4
10 3
0 0·1 0·2 0·3 0·4 0·5 0·6 0·7 0·8 0·9
air-gap length, mm
Effect of air-gap length on inductances of RSM

Id = 10 A; lq = 17.4 A; actual air-gap length = 0.35 mm
Ld
× × Ld – Lq
Ld/Lq
Lq
Figure 16.18 Impact of air gap length on d and quadrature axis inductance [17].
to be made higher than 450 which will aid in tapping the maximum torque
from the given rotor structure. This is implemented by exciting with higher
negative demagnetizing current.
16.6 Analytical Design of SynRM

The motor peak power and torque for a four wheeler are computed in
Section 16.3. The specifications derived using Section 16.3 which are
required for the study are tabulated in Table 16.3.
16.6.1 Stator & Winding Design

The stator and windings used in SynRM are akin to that of a conventional
induction machine. The number of stator slots is decided depending on
the breakdown torque, starting current, and the cooling requirements.
With a very high number of slots the leakage reactance will be low and the
Table 16.3 Specifications used to design traction motor.

Parameter Unit Value
Application NA Four Wheeler
DC Voltage Available V 240 to 403
Peak Power kW 80
Peak Torque Nm 200
Base Speed rpm 3858
Continuous Torque Nm 100
breakdown torque will be high. Hence, the number of slots is chosen as 36

which is also dependent on space availability. The type of conductor used
is random wound round wire. The stator is designed in the conventional
method utilizing distributed winding with slots per pole per phase as 3.
The stator yoke and teeth are designed ensuring that the flux density is
within the saturation limit of the electrical steel used. The following key
points were addressed to make the designed motor on par with the indus-
trial standards for prototyping:
1. Keeping the slot fill factor within limits, maximum possible

is 85%
2. Core material used is the commercially available grade
3. Manufacturing tolerances were considered
The flow chart for designing the machine from a given torque speed
curve for traction applications is given below in Figure 16.19.
From the flow chart, the important steps involved in the design process
are listed below:
• Designing the stator core maintaining the flux density limits

• Checking the induced voltage in the stator windings is
within the limits of DC voltage
• Designing the rotor for minimum torque ripple
For obtaining the optimum performance from any electrical machine

it is highly significant that there should be a well maintained balance
between magnetic loading and electric loading. Magnetic loading is a term
which shows the utilization index of electrical steel as it is the carrier of
Start
Peak torque, base

speed (T-N curve)
Sizing of motor with

minimum envelope,
selection of optimum turns
per phase
Design of rotor for

minimum torque ripple No
Checking
Finite element analysis of back emf,
model flux
density
Yes
Check
No
torque,
torque
ripple
Yes
Stop
Figure 16.19 Flow chart for electromagnetic design of traction motor.
flux lines. Saturation flux density is one of the important parameters that
is checked for in the electromagnetic design of any machine because if it
exceeds the limit, the torque per ampere capability of the motor decreases
rapidly, which will have detrimental effects. This will be manifested as
lower efficiency and higher heat generation. Torque per ampere capability
talks about the torque that can be generated from the machine for a given
current. Electric loading shows the ampere turns per meter around the cir-
cumference of the motor which is related to the current carrying capability.
It also points towards the required cooling mechanism to be implemented.
As the heat dissipation capability of the cooling method adopted increases,
the current carrying capacity and hence the torque production ability
also increases. Keeping these two important parameters as a precursor,

the electromagnetic design of SynRM was carried out. Since it is a singly
excited machine, the whole torque production depends up on the winding
or, in other words, the number of turns and its length. Optimum number
of turns and length has to be determined for attaining the required torque
maintaining the limits of source voltage. The important equations involved
in determining the rotor’s outer diameter and length is highlighted below
which is similar to a conventional induction machine.
L
Here, = 0.32 where L is the stack length and D is the rotor outer
diameter. D
Assumptions: Magnetic loading, Bg =1 T
Electric loading, ac = 65,000 ampere conductors per
meter (Corresponding to peak rating)
Winding factor, Kw = 0.93
By using Lenz’s law:
Induced voltage per phase, Eph =
4.44 ∗ π ∗ B ∗ D ∗ L ∗ f ∗ N ph ∗ K w =
 240 + 403  1 = 131V
 ∗ (16.27)
P  2  2∗ 3
3 ∗ 2 ∗ N ph ∗ I l
ac = (16.28)
π ∗D
where f is the operating frequency, Nph is the number of turns per phase,
and Kw is the winding factor. By using (16.27) and (16.28), the rotor outer
diameter, length, and turns per phase are computed. The stator outer diam-
eter is decided depending on the flux density distribution in the machine.
The calculated dimensions are tabulated as given in Table 16.4.
Table 16.4 Major dimensions of designed SynRM.

Description Value (in mm)
Stator Outer Diameter, SOD 362
Rotor Outer Diameter, D 210
Stack Length, L 68
Air Gap Length, g 0.35
In SynRM, the sole reason for production of torque is the difference

in reluctance along the d and q axis, which brings the whole focus on the
design of rotor. Explaining the principle governing SynRM again, when
the stator windings distributed in space by 1200 are fed with a three
phase supply displaced in time by 1200, a rotating magnetic field is gen-
erated in the air gap. The rotor is constructed so that there will be min-
imum reluctance along the direct axis and maximum reluctance along
the quadrature axis. This is implemented with the help of flux carriers
(iron segments) and barriers (air). The flux carriers will provide a low
reluctance path and barriers forming a high reluctance path. In other
words, the direct axis flux has to flow through the minimum reluctance
path increasing the inductance along the direct axis. The quadrature axis
flux needs to be minimized to minimize quadrature axis inductance.
Finally, this will result in a high anisotropy structure. The rotor will
always try to align in the path of minimum reluctance, conserving the
net energy in the system. This explains the torque production by the
reluctance mechanism.
16.6.2 Rotor Design

Rotor is the key geometrical component which has to be designed with
utmost importance since the torque production solely relies on the induc-
tance difference between the direct and quadrature axes. The direct and
quadrature axes components of mmf will be used in designing the rotor.
Recalling some of the concepts discussed earlier, the direct axis mmf causes
direct axis inductance (Ldm) and the quadrature axis mmf gives rise to two
components of inductances: circulating (Lqc) and flow through component
(Lqf).
In this section, the widths of segments and barriers are determined from
the variation of mmf with respect to barrier end angles, which is clearly
depicted in Figure 16.20. The image given below shows one of the four
rotor poles with different design parameters indicated in it.
The following are the assumptions adopted:
• Stator slotting effect is disregarded

• Saturation effect is neglected
The parameters which will be analytically calculated in this section [19]

are given as follows:
• Barrier end angle, αm

~β
(k)
(3)
Si+1
Si (B)
(2)
S3 ~αm
(1)
~αm
S2
~αm
S1
+α
~αm
π
2p ~αm/2
(A) d
Figure 16.20 Rotor structure with barrier end angle distribution [20].
• Segment width, Si, where i=1,2…k+1; k stands for the num-

ber of barriers
• Barrier width along quadrature axis, W1i, where i= 1,2….k
16.6.2.1 Determining Barrier End Angle, αm

Barrier end angle determines the torque ripple as it has a direct effect on
the interconnection between rotor barriers and stator slots. In the calcula-
tion of the barrier end angle an extra angle, β is considered which acts as a
variable to study the impact on torque ripple [21].
π
−β
αm = 2∗ P = 8.330 , here β = 0.9*α m = 7.50 (16.29)
k + 0.5
16.6.2.2 Determining Segment Width, Si

The segment width and barrier width are important in deciding the rotor
anisotropy as it will directly impact the reluctance along the d and quadrature
axis. With regard to determining the segment width, the insulation ratio,
kwq, along the quadrature axis will be utilized. An optimum value of insu-
lation ratio has to be used. An initial estimate of 0.5 is used for calculation.
The segment width should be designed so that it is linearly proportional
to the direct axis mmf passing through each segment. The per unit (p.u.)
direct axis mmf along each segment is calculated by taking the average mmf
between the end points of each segment. The variation of direct axis mmf
with respect to the barrier end angle is provided in Figure 16.21.
The calculation for p.u. direct axis mmf is given by the equations below
[20, 22]:
(2 h −1)α m
∫ (2h−23)α m cos( pα )dα  (2h − 1)α m   (2h − 3)α m 
sin  P
  − sin  P 
fdh = 2
= 2 2 where h = 1,2…k
αm P ∗α m
(16.30)
Π
∫ 2P
cos( pα )dα  (2k − 1)α m 
(2 k −1)α m 1 − sin P
 2 
fd( k+1) = 2
= (16.31)
αm + β P(α m + β )
d, mmf4
fd1 fd2
fd3
fd4
cos(pα)
fdi
fdi+1
S1 S2 S3 Si Si+1
αm 3αm 5αm (2k−1)αm (2k+1)αm π +α

0
2 2 2 2 2 2p
(A) 1 2 3
αm β
k (B)
Figure 16.21 Direct axis mmf distribution with respect to barrier end angle [22].
Since the segment width is proportional to the mmf in the correspond-

ing segment, the equation given below is valid:
2 ∗ S1 fd1
= (16.32)
S2 fd2
Sh fdh
= ; h=2,3…k (16.33)
Sh+1 fdh+1
The designed values of per unit direct axis mmf for five segments are as
follows:
fd1 = 0.9964
fd2 = 0.954d6
fd3 = 0.8326
fd4 = 0.6407
fd5 = 0.2698
The sum total of segment width is obtained as:
D Dshaft
− −g
Stotal = ∑hk+=11 Sh = 2 2 = 43.1 mm (16.34)
1 + kwq
where D and Dshaft are the rotor outer and shaft outer diameter and g is the
air gap length. With (k+1) equations and (k+1) unknowns, the segment
widths can be determined. As per the design mentioned above the segment
widths are obtained as tabulated in Table 16.5.
16.6.2.3 Determining Barrier Width, W1i

The barrier width along the quadrature axis can be obtained by consider-
ing the quadrature axis excitation. With current given in the quadrature
axis, the rotor barriers attain different magnetic potential. The quadrature
axis mmf distribution with respect to barrier end angle is given in Figure
16.22. The difference of mmf across each barrier, Δf k, can be determined to
find out the barrier width.
Table 16.5 Calculated degment width of SynRM.

Segment number Width (in mm)
S1 6.718
S2 12.873
S3 11.228
S4 8.64
S5 3.638
d, mmf4 q
fqi+1
∆fi
sin(pα)
fqi
∆fi+1
fq3
∆f3
fq2
∆f2
S1
fq1
∆f1 S1 S2 Si Si+1
αm 3αm 5αm (2k−1)αm (2k+1)αm π +α

0
2 2 2 2 2 2p
(A) 1 2 3
αm β
k (B)
Figure 16.22 Quadrature axis mmf distribution with respect to barrier end angle [22].
fq1 = 0 (16.35)
(2 h−1)α m
∫ (2h−23)α m sin(pα )dα  (2h − 3)α m   (2h − 1)α m 
cos  P
  − cos  P 
fqh = 2
= 2 2 ;h=12,3…k
αm P ∗α m
(16.36)
Π
∫ 2P
sin(pα )dα  (2k − 1)α m 
(2 k −1)α m cos P
 2 
fq( k+1) = 2
= (16.37)
αm + β P(α m + β )
Δfqh−1 = fqh − fqh−1; h=2,3…k (16.38)
Δf k = fqk+1 – fqk (16.39)
The difference of mmf computed across each barrier is given below:
Δf1 = 0.2856
Δf2 = 0.2617
Δf3 = 0.2158
Δf4 = 0.1875
For optimal distribution the constant permeance relation is used.
W1h ∆fqh 2
= ; h=1,2…(k-1) (16.40)
W1h+1 ∆fqh+1
The sum total of barrier width along the quadrature axis is calculated as:
D Dshaft
− −g
∑hk+=11 W1h = 2 2 = 21.55 mm (16.41)
1 + (1/kwq )
The barrier widths are obtained as tabulated in Table 16.6.
Table 16.6 Calculated barrier widths of SynRM.

Barrier number Width (in mm)
W11 7.582
W12 6.367
W13 4.329
W14 3.270
The tangential ribs provide a pathway for the flux lines to pass through
in the quadrature axis. The advantage related to the structural strength of
the rotor related to the ribs was already highlighted. In this design, the
tangential rib and radial rib are given a width of 0.7 and 1mm, respectively.
16.7 Electromagnetic Analysis –Results & Discussion

As mentioned earlier, current source excitation is used along with the con-
trol of current angle. Initially, the performance of the machine is checked
with peak excitation current as it determines the vehicle performance in
standstill condition. Then, the performance of the machine is checked
with continuous current which will determine the vehicle characteristics
in cruise mode. This part deals with the effect of a few design parameters
that are checked and the associated results are provided.
Figure 16.23 below gives the 2D design of an SynRM built by using the
dimensions calculated in Section 16.6. The design is developed in ANSYS
Electronic Desktop 2020R1, which is a finite element analysis (FEA) soft-
ware. Since the machine has nonlinear characteristics it is inevitable that
the machine be designed by using an FEA tool. The mesh defined is shown
in Figure 16.24 wherein a refined mesh is provided for rotor core and air
gap as field variations are predominant in those regions.
Once the 2D design is completed as per the calculated dimensions, the
next major step is to assign excitation. The excitation is given by a pure
sinusoidal current with the current angle being controlled. Since saturation
Z X
Time = -1 0 150 300 (mm)
Figure 16.23 2d model of SynRM.

Time = 77.92000us Z X
Speed = 0.000000rpm
Position = 55.000000deg
0 50 100 (mm)
Figure 16.24 Mesh defined in 2d model of SynRM.
is highly prominent in this motor, the ideal value of current angle as per
(16.19) will not meet the required torque. So, to reduce the impact of sat-
uration, the current angle is made greater than 450. Due to this, the direct
axis component of the stator current is decreased which will reduce the sat-
uration in the flux path resulting in the required torque. Once the analysis
is completed, there are few check points as far as the traction motor design
is considered which will be highlighted in this section along with the major
performance parameters. The flux lines with direct axis and quadrature
axis excitation are given below in Figures 16.25 and 16.26 which clearly
A [Wb/m]
0.0849
Y
0.0679
0.0577
0.0475
0.0374
0.0272
0.0170
0.0068
–0.0034
–0.0136
–0.0238
–0.0340
–0.0441
–0.0543
–0.0645 Z X
–0.0747
–0.0849
Time = 77.92000us
Speed = 0.000000rpm
0 150 300 (mm)
Figure 16.25 Direct axis flux lines.

A [Wb/m]
0.0359
Y
0.0288
0.0244
0.0201
0.0158
0.0115
0.0072
0.0029
–0.0014
–0.0058
–0.0101
–0.0144
–0.0187
–0.0230
–0.0273
–0.0316
Z X
–0.0359
Time = 194.80000us
Speed = 0.000000rpm
0 150 300 (mm)
Figure 16.26 Quadrature axis flux lines.
show the flux path along direct axis and quadrature axis. With direct axis
excitation, the flux line travels through the stator core, air gap, and rotor
core sweeping the direct axis path (low reluctance path). With quadrature
axis excitation, the flux line travels through the stator core, air gap, and
rotor core sweeping the quadrature axis (high reluctance path). The flux
lines clearly show the anisotropic behavior of the rotor structure.
The entire simulation study is performed at a constant shaft speed con-
sidering the steady state analyzed under two operating points: peak and
continuous rating. This will aid in understanding how the machine behaves
in these conditions. The input current value to be assigned for checking the
performance is calculated from the peak power as shown below.
The output power equation for any motor is:
Output power, P= 3 ∗VL ∗ I L ∗ cos∅∗η (16.42)
where VL is the line voltage, IL is the line current, cos∅ is the power factor,
and η is the efficiency.
Assuming an efficiency of 0.94 and power factor of 0.77, the peak line
current is obtained as 296.98 A. The peak performance was checked with
a current angle of 87°.
Flux density distribution with peak current as input is given in Figure
16.27 which depicts the saturation phenomenon in the machine. It can be
observed that the flux density in the rotor core is higher than the saturation
flux density of steel material, as expected. In stator core, the flux density is
B [Wb/m]
2.0000
Y
1.8667
1.7334
1.6000
1.4667
1.3334
1.2001
1.0668
0.9334
0.8001
0.6668
0.5335
0.4002
0.2668
0.1335
Z X
0.0002
Time = 155.84000us
Speed = 3850.000000rpm
0 150 300 (mm)
Figure 16.27 Flux density plot.
maintained at 1.5 T whereas in teeth it goes to 1.9 T. The stator teeth width
has been determined taking into account the slot fill factor limitation while
ensuring that all the flux lines have the minimum width for its passage.
Phase induced voltage waveform is provided in Figure 16.28. It clearly
indicates that the number of turns chosen, length, and the air gap flux does
not exceed the source voltage. The rms value of induced voltage is obtained
as 124V. This value is well within the limits of available DC voltage even
Winding Plot 4 peakunskew_0.5 ANSYS

300.00 Curve Info rms
InducedVoltage(PhaseA)
124.8782
Setup1: Transient
200.00
InducedVoltage(PhaseB)
124.8480
Phase induced voltage: V
Setup1: Transient
100.00 InducedVoltage(PhaseC)
Setup1: Transient 124.9564
0.00
–100.00
–200.00
–300.00
75.00 100.00 125.00 150.00 175.00 200.00 225.00 250.00
Moving 1.Position [deg]
Figure 16.28 Phase induced voltage waveform.

Torque Plot 1 peakunskew_0.5 ANSYS

300.00 avg
Curve Info pk2pk
Moving1.Torque
275.00 Setup1: Transient 196.9931 66.9197
Moving1.Torque [NewtonMeter]
250.00
225.00
200.00
175.00
150.00
125.00
100.00
75.00 100.00 125.00 150.00 175.00 200.00 225.00 250.00
Figure 16.29 Electromagnetic torque.
after subtracting the resistance drop (the per phase AC rms voltage avail-
able is 131 V, from (16.24)). The induced voltage waveform shows the pres-
ence of higher order harmonics visibly. The harmonic contents that were
present are the following: 17,19, 35, and 37.
The electromagnetic torque produced is 197 Nm, at a shaft speed of
3850 rpm, giving an output power of 79 kW. The result for electromagnetic
torque is given in Figure 16.29. The torque ripple is obtained as 34%, which
can be attributed to the action between stator slots and the anisotropic
rotor structure.
16.8 Investigation on Impact of Different Parameters

The parameters which affect the design of SynRM have been discussed in
Section 16.5. Here, an investigation is presented showing the influence of
various parameters on the performance of SynRM.
• Effect of Insulation Ratio

There is an optimum distribution of iron and air which will result in the
maximum torque production. The optimum distribution as discussed
before is given by the term insulation ratio, kwq. In this section, the effect
of insulation ratio on the motor is explained. With kwq = 0.7, the calculated
rotor dimensions are given in Table 16.7.
Table 16.7 Calculated segment and barrier widths.

Segment number Width (in mm)
S1 5.928
S2 11.359
S3 9.907
S4 7.623
S5 3.2104
Barrier number Width (in mm)
W11 9.366
W12 7.865
W13 5.348
W14 4.039
The 2D design obtained by using these dimensions is given in Figure

16.30.
The following paragraph will give an insight into the performance
obtained from the rotor by using higher insulation ratio. When compared
to the results obtained by using kwq = 0.5, improvement is observed in the
Z X
Time = -1 0 150 300 (mm)
Figure 16.30 2D design of SynRM with kwq = 0.7.

torque produced, which is captured in Figure 16.31. The torque waveform

obtained from the rotor designed using kwq = 0.5 is also provided in Figure
16.31 for comparison purposes.
The increase in torque can be accounted for due to the reduction in
quadrature axis inductance happening because of the increase in bar-
rier width. This reduction in quadrature axis inductance also decreases
the cross magnetizing effect on direct axis inductance, thereby slightly
boosting the direct axis inductance. Table 16.8 below summarizes the
comparison.
With further increase in insulation ratio, the effective utilization of
steel will not happen, so the insulation ratio of 0.7 is chosen for further
iterations.
• Effect of Current Angle

Another important aspect associated with SynRM is finding out the opti-
mum current angle. In (16.19), the ideal value of current angle is 45° for
Torque Plot 4 peakunskew_0.7 ANSYS

350.00 Curve Info avg pk2pk
Moving1.Torque
Setup1: Transient 200.0518 80.5847
300.00
Moving1.Torque_1
Imported 196.9931 66.9197
Torque [NewtonMeter]
250.00
200.00
150.00
100.00
50.00
50.00 100.00 150.00 200.00 250.00 300.00
Table 16.8 Comparison of different insulation ratios.

Description With kwq = 0.5 With kwq = 0.7
Number of Barriers 4 4
Torque Obtained 196.9 N m 200 N m
Torque Ripple 33.9 % 40 %
maximum torque production, but as discussed earlier, accounting for satu-

ration, the angle will be greater than 45°. The graph given below in Figure
16.32 shows the variation of average torque with current angle.
The optimum value depends upon the rotor structure and the input cur-
rent as well [19]. A parametric study is implemented with the finalized
rotor structure and it is noted that the torque attains the maximum value
at a current angle of 87°.
• Effect of Barrier Fillet Radius

The impact of barrier fillet radius on the torque ripple was studied in [23].
The variation in radius will change the length of barrier and the reluctance
of the flux path will be affected. After performing a parametric study on
fillet radius, it is observed that there is only a minor reduction in peak to
peak torque amplitude for radius variation from 0 to 1mm. Variation from
1mm to 2.5mm had no effect on the ripple content in torque. The results
are depicted in Figure 16.33.
The effect of different parameters was studied and the rotor is almost
fine-tuned with respect to the torque ripple as well as the flux density. The
next major design aspect is to understand the effect of rotor skew.
• Effect of Rotor Skew

All the analysis performed until now was without rotor skewing and the
ripple content in torque was very well evident. Torque ripple is one of the
serious issues as far as SynRM is concerned because of the interaction
Torque Plot 3 Curve Info avg

ANSYS
300.00
avg(Moving1.Torque)
Setup1: Transient -0.0308
250.00 angl=’0dcg’
avg(Moving1.Torque) [NewtonMeter]
avg(Moving1.Torque)
angl=’4dcg’
200.00 avg(Moving1.Torque)
angl=’8dcg’
angl=’10dcg’
100.00
avg(Moving1.Torque)
angl=’12dcg’
angl=’16dcg’
0.00
-50.00
25.00 50.00 75.00 100.00 125.00 150.00 175.00 200.00
Currentangle [deg]
Figure 16.32 Electromagnetic torque versus current angle.

Torque Plot 3 filletradpara ANSYS

Moving1.Torque
275.00 Setup1: Transient 200.3236 57.4671
ra=’0mm’
250.00 Moving1.Torque
ra=’0.5mm’
225.00
Moving1.Torque
200.00 ra=’1mm’
Moving1.Torque
175.00
ra=’1.5mm’
150.00 Moving1.Torque
ra=’2mm’
125.00
100.00
0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00
Time [ms]
Figure 16.33 Electromagnetic torque variation with respect to barrier fillet radius.
between stator slots and rotor anisotropic structure. Short chording the
winding has specifically no impact on torque ripple but will help in reduc-
ing the end winding length. The best choice is to skew the rotor by one slot
which will help in reducing the ripple, simultaneously decreasing the aver-
age torque and consequently, the power output of the machine [24]. Figure
16.34 gives the torque waveform with a continuous skew of 100 introduced
in the rotor.
From Figure 16.34 it can be comprehended that the ripple in torque
has reduced to 13%, which was 40% without skew and the average value
of torque has reduced from 200 Nm to 196.9 Nm (from Table 16.8). Since
Torque Plot 4 peakskew ANSYS

Moving1.Torque 196.6659
275.00 Setup1: Transient 26.9100
250.00
225.00
200.00
175.00
150.00
125.00
100.00
60.00 100.00 150.00 200.00 250.00
Figure 16.34 Electromagnetic torque with rotor skew.

torque ripple is one of the major drawbacks, ripple reduction is one among
the most widely researched topics in SynRM. A significant contribution is
made by Nichola Bianci, proposing the Romeo & Julie (R&J) kind of rotor
laminations with two different barrier shapes introduced in the same lam-
ination which will help in eliminating some of the harmonic contents [25,
26]. A detailed study of dependence of torque harmonics on rotor struc-
ture is presented in [27, 28].
The output power is obtained as 79.3 kW, which is given in Figure 16.35.
The phase induced voltage is given in Figure 16.36. The induced voltage is
within the voltage limits.
Output Variables Plot 4 peakskew ANSYS

100.00 Curve Info avg
Outputpower
95.00 Setup1: Transi... 79.2900
90.00
Outputpower(kW)
85.00
80.00
75.00
70.00
65.00
60.00
60.00 100.00 150.00 200.00 250.00
Figure 16.35 Output power.
Winding Plot 2 peakskew ANSYS

200.00
InducedVoltage(PhaseC)
Phase induced voltage [V]

100.00 InducedVoltage(PhaseA)
0.00
-100.00
-200.00
-300.00
60.00 100.00 150.00 200.00 250.00
Figure 16.36 Phase induced voltage.

The air gap flux density, as well as power factor, was also checked to
check its concurrence with the initial assumptions. The waveform is given
below in Figure 16.37. The rms value is displayed as 0.96 T, whereas the
assumption is 1 T, which is almost in close proximity with the obtained
value.
The power factor was also obtained as 0.73 by measuring the phase angle
difference between input voltage and winding current, which is slightly
lesser than the assumed power factor. This can be due to the effect of rotor
structure.
Next, the results obtained with excitation corresponding to continuous
rating are given for the finalized rotor structure with rotor skew. The flux
density waveform given in Figure 16.38 reports a lower value of flux den-
sity when compared to the peak rating. The flux density in stator teeth
has been reduced to 1.7 T and the highest magnitude of flux density in
the rotor core is 1.8 T. The phase induced voltage is given in Figure 16.39.
The torque waveform with an average value of 91.48 Nm is given in Figure
16.40. The output power is given in Figure 16.41 with an average value of
36.7 kW.
16.8.1 Torque-Speed Curve

To estimate and evaluate the performance of the motor over the entire speed
range, ANSYS Motor-CAD was utilized and the torque-speed curves are
given in this section incorporating the efficiency maps. Studying the perfor-
mance throughout the speed range will provide a complete understanding
Calculator Expressions Plot 1 Maxwell2DDesign1 ANSYS

2.00 Curve Info rms
brad
1.50 Setup1: Transient 0.9614
Time=’1870080...
1.00
0.50
brad
0.00
-0.50
-1.00
-1.50
-2.00
0.00 50.00 100.00 150.00 200.00 250.00 300.00 350.00
Distance [mm]
Figure 16.37 Air gap flux density of SynRM.

B [tesla]
2.000
Y
1.8667
1.7333
1.6000
1.4667
1.3334
1.2000
1.0667
0.9334
0.8001
0.6667
0.5334
0.4001
0.2668
0.1334
0.0001
Z X
Time = 7.77920ms
Speed = 3850.000000rpm
0 150 300 (mm)
Figure 16.38 Flux density plot.
Winding Plot 3 peakskew ANSYS

InducedVoltage(PhaseA)
200.00
Setup1: Transient
Phase induced voltage [V]
101.7865
100.00
InducedVoltage(PhaseC)
0.00
-100.00
-200.00
-300.00
60.00 100.00 150.00 200.00 250.00
Figure 16.39 Phase induced voltage waveform.
of the machine. The current variation and voltage profile are marked in the
torque-speed curve with a maximum torque per ampere algorithm being
utilized in the control circuit. Figure 16.42 gives the torque-speed curve
including the efficiency map. Although the efficiency contour covering the
maximum speed range is 92%, the machine is still able to deliver a higher
efficiency of 97% too.
Torque Plot 4 contskew ANSYS

Moving1.Torque
Setup: Transient 91.4847 16.6850
Moving.Torque [NetworkMeter]
125.00
100.00
75.00
50.00
60.00 100.00 150.00 200.00 250.00
Output Variables Plot 5 contskew ANSYS

50.00 Curve Info avg
Outputpower
Setup1: Transi... 36.8840
45.00
40.00
Outputpower(kW)
35.00
30.00
25.00
20.00
60.00 100.00 150.00 200.00 250.00
Figure 16.41 Output power.
Figure 16.43 gives the power speed curve with efficiency superimposed.
The machine does not exhibit a good constant power zone beyond the
base speed, which is due to the higher quadrature axis inductance than the
required value. This is an inherent drawback by virtue of its construction
and the quadrature axis flux in the ribs worsens this condition.
200 98
92
86
96
150 94
Shaft Torque (Nm)
92
93
90
Efficiency (%)
88 87 83
89
97
100 90
95
88
50 86
95
94 84
91
84
0 0
0 2000 4000 6000 8000 10000
Speed (rpm)
Figure 16.42 Efficiency map with torque-speed curve.
1e5
98
96
0.8
95 94
Shaft Power (W)
0.6 92
Efficiency (%)
97
90
0.4
88
95
86
94
0.2
90 86
93
92
91 84
89
64
0.0 0
0 2000 4000 6000 8000 10000
Speed (rpm)
Figure 16.43 Efficiency map with power speed curve.
Figure 16.44 gives the torque speed curves with current variation and the
torque variation with current variation can be very well understood here.
Figure 16.45 provides the curve with voltage variation. It is inferred that
the voltage is maintained at the specified voltage limit.
This software also allows the drive cycle to be superimposed on the
obtained torque-speed curve to understand the frequently operating
points and the performance of the machine in these zones with respect
to a given drive cycle. The drive cycle utilized here is the US06 and its
velocity versus time variation is given below in Figure 16.46. By using the
vehicle parameters discussed in Section 16.3, the torque required was also
calculated, which is shown in Figure 16.47. This torque calculation is used
200 480
420
Stator Current Phase Peak (Apeak)

150 360
Shaft Torque (Nm)
300
100 240
180
50 120
60
0 0
0 2000 4000 6000 8000 10000
Speed (rpm)
Figure 16.44 Torque-speed curve with current variation.
200
315
270
150
Voltage Line Peak (Vpeak)

225
Shaft Torque (Nm)
180
100
135
50 90
45
0 0
0 2000 4000 6000 8000 10000
Speed (rpm)
Figure 16.45 Torque-speed curve with voltage variation.
in superimposing the duty cycle on the torque speed curve as depicted in

Figure 16.48. From the duty cycle analysis, it is calculated that the average
efficiency of the machine is 94%.
16.9 Summary
The entire chapter provides a holistic way of understanding machine
SynRM along with its design fundamentals. The significance of moving to
10000
8000
6000
Speed (rpm)
4000
2000
0
0 100 200 300 400 500 600
Time (secs)
Figure 16.46 Duty cycle definition-US06.
250
150
200
100
Shaft Torque (Nm)
50
–50
100
–150
–200
0 100 200 300 400 500 600
Time (secs)
Figure 16.47 Torque versus time-duty cycle calculation.
a rare earth free motor as a traction choice is very high in the present sce-
nario wherein there is a radical increase in the price of rare earth magnets.
A complete comparison between the different traction choices has been
presented. Size, cost, and efficiency are three key factors in the design of
any traction machine. The comparison presented is considering all these
aspects. Since the motor designed is to be used for traction, it is inevitable
that the motor should be capable of overcoming the forces acting on the
vehicle. A brief overview on the peak power calculation is presented from
the vehicle dynamics perspective. The rudimentary principle of SynRM
98
200
92
91
86
96
94
90
93
100
89
97
95
88
96
Shaft Torque (Nm)
82
Efficiency (%)
80
0
95
96 88
88
91
100 95 86
97
84
92
87
93
94
90
200 0
0 2000 4000 6000 8000 10000
Speed (rpm)
Figure 16.48 Torque-speed curve with duty cycle superimposed.
and all its associated equivalent circuits, phasor diagrams, and equations
has been highlighted. The main sources of non-linearities were discussed.
The history of development of SynRM was provided covering the major
milestones in rotor structure evolution starting from 1929. Moving into
the design concepts, the major findings in classic literature were stated
and the graphical relations have been illustrated. Analytical design of
the rotor, which will calculating the barrier width and segment widths, is
described clearly explaining the manufacturing constraints. The next sec-
tion describes the discussion of the results obtained from the aforesaid cal-
culations. Insulation ratio was one important design parameter, the impact
of which has been presented. The control aspect has also been touched
here describing the significance of current angle and the optimum current
angle has been determined from parametric analysis. Another parameter
looked into was the barrier fillet radius. Its impact on torque ripple has
been recorded. Rotor skewing, one of the popular methods in reduction
of torque ripple has been studied. The continuous rating performance has
been verified and the results are presented. Finally, the performance of the
machine over the entire speed range is given by torque speed curve, includ-
ing the efficiency maps. The drive cycle analysis has also been presented by
utilizing the US06 duty cycle. The drive cycle has been superimposed on
the torque-speed curve of the motor designed.
While comparing with its counterpart PMSM, SynRM has higher torque
per volume and power density, but from an expenditure point of view, it
surpasses PMSM. SynRM is able to meet the requirements, but withs the
limitations of higher torque ripple and lower power factor. The maximum
efficiency zone is slightly lesser when compared to PMSM, but considering
the lower cost aspect, a slight depreciation in performance is acceptable.
16.10 Future Work

The chapter has been streamlined towards the electromagnetics aspect
with the current angle input considered in simulation. The different
parameters effecting the design have been highlighted and the simulation
results depicting the effect of a few parameters have been given. Although a
rotor structure design methodology has been described, there is still room
for improvement from the saliency ratio standpoint. The torque ripple
achieved with the current structure by adopting rotor skewing was 13%
which can be further reduced. Further work and analysis have to be imple-
mented in the direction of reducing the torque ripple.
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for Torque Ripple Reduction in Synchronous Reluctance and PM-Assisted
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for torque ripple reduction in synchronous reluctance motors,” Conference
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Annual Meeting, Tampa, FL, 2006, pp. 1193-1200.
17
Implementation of Automatic Unmanned
Battery Charging System
for Electric Cars
Shefali Jagwani *
Department of Electrical and Electronics Engineering, Nitte Meenakshi Institute

of Technology, Bangalore, India
Abstract
Electric cars are gaining popularity all over the world. The Government of India
has planned to make these electric cars mandatory by 2030. According to the
recent guidelines given by the Indian Government, a charging station for an
electric vehicle should be present every 25km along a road or a highway. Thus, a
charging station is proposed here for automatic charging of a 48V battery electric
car using solar power. This charging station can be located at any of the public
places like hotels, hospitals, offices, airports, colleges, malls, etc.
In this proposed work, a solar panel of 54V is used during the daytime and
grid power is used during night time to charge the vehicle. A DC-DC Buck-Boost
converter is designed to give a constant supply of 48V for charging the vehicle. In
addition, the RFID card is used which has the information of the vehicle and its
owner. As soon as the RFID card is inserted in the RFID slot, the charging dura-
tion is asked from the vehicle owner. Arduino Nano is programmed for reading
the RFID tag. According to the requirement of the customer, the information is
sent to the manager for monitoring of the charging station through the cloud. This
cloud computing, using the ThingSpeak platform, enables the owner to get the
information of all the cars coming to the charging station. A voltage indicator is
used in the vehicle to show the level of charge left in the vehicle and the distance
it can cover with the remaining charge. LCD is used to display the charging sta-
tus of the vehicle. This proposed work is implemented through MATLAB simula-
tion. Thus, an automatic unmanned battery charging system for electric cars using
hybrid power is proposed which will help move us one step closer to achieving the
target of the Government of India.
*Email: [email protected]
517
Keywords: Automatic car charging station, unmanned battery car charging,

electric vehicle, solar charging, hybrid power
17.1 Introduction
In the current scenario, energy is the first concern for nations that have a
huge reliance on imported non-renewable energy sources. Electric Vehicles
(EV) appear to be one of the most promising solutions which can reduce
energy consumption by fossil fuels. Many researchers, along with the gov-
ernment bodies, are involved in research to make EVs more efficient com-
pared to internal combustion engine vehicles. As per the report by Global
EV Outlook 2019, the transportation segment is going to convert 30% of
vehicles into electric vehicles by 2030 [1]. In addition, it says that in 2019
the sales of electric cars have topped all the previous records. Pointing to
an improvement of energy productivity, revolution in the transportation
division is in progress. Advances in electric drives have empowered com-
mercialization of EVs. However, forecasting the future demand for EVs
is highly dependent on the costumer’s willingness to adapt EV. There are
many challenges for the EV industry like charging infrastructure, charging
time, economic considerations, etc. which need to be addressed. Charging
time is one of the major issues being faced by the researchers.
Various authors have worked in the domain of electric vehicles, a few of
which are discussed in this section. In papers [2–4], a survey of EVs is pre-
sented in detail with a focus on its commercialization, implementation of bat-
tery chargers (on-board and off-board), charging levels, and infrastructure
for plug-in EV. The major issues and challenges are addressed with respect
to EV technology. The willingness to pay is estimated considering a range of
EVs, charging time, fuel cost, environmental aspects, and performance.
In general, the classification of charging levels is based on the rates of
power charging. Level I charging indicates slow charging for long hours,
which is generally overnight charging at 120 V (single phase onboard
charging) in the power range of 1 to 1.5 kW. Level-II charging is used in the
range of 4 to 6.6 kW at 240 V (single phase onboard charging) and takes
3-6 hours. However, Level III charging uses a three phase off board charger
which allows fast charging in the range of 50 to 75 kW. These three charging
levels have their own advantages, limitations, and various effects on grid.
For instance, Level I charging is considered as a better charging tech-
nique in terms of battery life, but night long charging is a constraint which
also affects the distribution of transformers in the utility grid. In Level II
charging, time is still a constraint along with voltage sags and higher power
Unmanned BCS for Electric Cars 519
losses in the grid. Though, the Level III charging takes less time, it requires
an extremely high demand from the grid which ultimately will lead to an
increase in system cost. Therefore, a solution is required for charging the
EV efficiently with minimum impact on the grid. Renewable energy is one
of the probable solutions to this problem. Solar energy has become one
of the most popular sources among all the renewable sources. Indeed, a
ton of household, mechanical, or business applications utilize sun powered
energy. Also, this is an important source to encounter reduction of carbon
discharges. Paper [5] proposes EV charging with solar energy and pres-
ents a particle swarm optimization based control of charging stations. A
multiport converter is presented for integrating the solar panels, chargers,
and batteries with the grid system. For the control of bidirectional flow
between the generating sources and the loads, an intelligent system is pro-
posed which is capable of fast and efficient switching between the sources.
In [6], the design of isolated Romanian Solar based EV charging is inves-
tigated. The optimal configuration of solar charging is obtained with the
help of improved Hybrid Optimization by Genetic Algorithms (iHOGA)
and the results are shown for 1 year of operation.
In [7], the author proposes an AC charging station with additional life
Li-Ion batteries, mixing solar PV with wind energy. The charging station is
solar as well as grid connected, which allows the charging of electric vehi-
cles from both ways. Mainly, the battery charging system works on solar
panels if there is any fault in the solar panel and during the rainy season,
sometimes the electric vehicle will be charged using the grid. However,
automation is not described in detail.
In paper [8], the usage of solar power was described by J. Y. Yong et al.
where a system is coordinated with a specialist controller, sensors, and an
input interface. A cadmium sulphide light delicate resistor is utilized. To
accomplish ideal solar tracking, a calculation is presented. A field pro-
grammable gate array is used to structure the controller with the goal that
the solar cells consistently face the sun in the daytime. Paper [9] presents a
fully integrated battery charger which does not require the support of any
external mechanisms.
Paper [10–13] shows the solar based charging systems with empha-
sis on battery charging techniques. The various methods used for wire-
less charging of EV batteries are presented in the literature [14, 15].
Static EV charging (which uses inductive and capacitive methods) and
dynamic EV charging (which uses only inductive circuits) are presented.
The compensation circuits, cores for magnetic coupled inductors, vari-
ous converters, and controllers used for wireless charging are discussed
[14]. Magnetic resonant coupling is used instead of inductive coupling for
wireless charging of the battery. An LC tuned circuit is used to maintain

the resonant frequency of the receiver coil [15]. Though wireless charging
circuits are in demand for the future systems, they involve a lot of power
loss. Therefore, due to reduced efficiency, they are still not very popular.
The authors in paper [16] present a solar charger in an integrated cir-
cuit without any external components for Nickel-based (NiCd or NiMH)
batteries. The various power electronic converter circuits for electric vehi-
cles are discussed in [17]. Paper [18] presents an educational project for
this system for charging the batteries of portable devices. This charger
can be operated at all AC voltages between 90 V to 270 V and is suitable
for various battery types and an unknown number of cells. Paper [19, 20]
presents the RFID based solar charging systems, however, the automation
system using the cloud is not presented in the literature. The authors in
[21] present a smart application to connect the EV with the grid. The user
can supply additional power to the grid. Paper [22] presents the idea of a
coin based mobile charging system, which is replaced with an RFID system
in the present work. The basic ideas of a solar based charging station are
presented in [23, 24]. A detailed analysis is given in [24] for charging of the
electric rickshaw. The modified design of a charging station is presented
with the concept of battery swapping.
Some of the papers available in the literature present the grid connec-
tion of EV. In [25], the challenge of an increase in load for the grid due to
EV charging is addressed. In [26], coordinated charging is presented to
reduce the power losses and to increase the grid load factor. The impact
of a fast charging station on the grid is studied using a stochastic model
[27]. The pros and cons of both fast and slow charging are explored in [28].
Papers [29, 30] discuss the infrastructure requirement for charging of elec-
tric vehicles. The survey on this grid connected technology, the possibili-
ties of implementation, the cost, and other factors are explored [31]. The
possibility for EV charging as a part of an integrated electric system with
the capability of adapting to varying conditions is discussed in the work by
Dickerman [32].
A good number of authors have presented their work in this domain.
However, automation is not given much attention in the available liter-
ature. In this paper, we propose an automatic RFID based system which
can be used in parkways, provincial zones, uneven regions, universities,
shopping centres, etc. The vehicle battery charging booth can be quickly
and smoothly introduced outside any commercial premises. RFID is used
to get to the details of the vehicle and the owner before charging the vehi-
cle. According to the requirements of the owner, the charging level is fixed
and starts charging. The details of all the vehicles coming to the charging
station will be given to the charging manager and the station owner through
the cloud. Thus, it is desirable to utilize solar energy to charge these elec-
tric vehicles by building up unmanned automatic electric charger booths,
which is the fundamental thought of this work. Thus, this paper presents
automatic unmanned battery charging which can help in modernization of
electric charging stations.
17.2 Proposed System

This work proposes an automatic unmanned battery charging system using
both solar panels and the grid. For this, the proposed system is presented
with various parts like input (through RFID) controllers (microcontroller),
output and display, power, etc. This section describes all these components
in detail. The complete block diagram of the proposed system containing
the EV charging system is shown in Figure 17.1.
For the input, an RFID is inserted in the insertion slot at the input point,
which will ask the time of charging from the vehicle owner. The time will
be presented on the LCD display for the user to guarantee the correct RFID
insertion. If some other RFID is inserted in the slot, it will be not detected.
If the right RFID is inserted, it will automatically generate a pulse to the
control unit, approving the start of charging of the vehicle battery asso-
ciated with the device. Then, the battery charging starts for the specific
period decided by the software of the microcontroller [16]. Arduino Nano
is programmed for reading the RFID tag and according to the requirement
of the customer, it controls and sends information to cloud computing for
monitoring and controlling this charging station. Figure 17.2 shows the
flowchart for the input.
The controller processes the information signal sent by the sensor cir-
cuit. The signal from the RFID can be acknowledged or dismissed, depend-
ing on the RFID sensor. This commands the microcontroller along with
the LCD interface and shows the choice of the vehicle owner. If a vehicle
is chosen for charging, the related routine is actuated and it charges the
vehicle for the chosen duration. The LCD presents all the data to the vehi-
cle owner when necessary. During charging, it shows “Charging” and at
the finish of charging it shows “Charge finished”. It has many terminals for
interfacing various vehicle batteries. Figure 17.3 shows the block diagram
of the EV controller.
The money for charging the vehicle is directly deducted from the vehi-
cle owner’s RFID card as soon as the owner sets the time for charging the
vehicle. In addition, the monitoring of the charging station can be done
Ac to Dc
12 V SOLAR Electric
converter
PANEL grid
12V
CLOUD COMPUTING
LCD
DC TO DC DISPLAY
CONVERTER
12V
CHARGER MULTIPLE
BATTERY DRIVER CHARGER
Arduino nano CONNECTOR
5 Volt Power
Supply
VOICE Vehicle
MEMORY battery
CHIP
Key board
SPEAKER
WiFi
Camera
Solar Power WiFi

Reader ESP 8266
Battery Power
Reader
RF ID Reader
Unit
Figure 17.1 Block diagram of proposed EV charging station.
by the owner of the charging station through cloud computing, using the
ThingSpeak platform. The information of the owners of all the vehicles can
be obtained by the RFID card. The LCD at the charging station gives the
charging status of the vehicle and the speaker at the charging station gives
the information after completion of charging of the vehicle.
The major work of the vehicle battery charger is that it takes power from
the solar energy throughout the day time for charging the battery. For uti-
lizing solar power, an inverter can also be used to supply this power to the
grid.
START
SWIPE YOUR RFID

CARD
NO IS THE CARD
VALID RFID
YES
ENTER THE
TIME FOR
CHARGING
AMOUNT
AVAILABLE IN
YES
CONNECT THE NO
CHARGING PORT
DISPLAYS “CHARGING
COMPLETE”, AFTER
CHARGING FOR THE
ENTERED TIME
END
Figure 17.2 Flowchart for input.
17.3 MATLAB Simulation

17.3.1 Mathematical Modelling
Throughout the day, the intensity of sunlight is not constant so a Buck-
Boost converter is used to get a constant output of 48V. When the sunlight
intensity is less than 48V, it will boost it to 48V to charge the EV and if the
intensity is above 48V, it will reduce to 48V to charge the EV. For illustra-
tion purposes, we have simulated a 12V battery.
LCD
DISPLAY
Voltage
sensor
Arduino Nano
WIFI
Key board ESP B266
48 VOLT
POWER
SUPPLY
Figure 17.3 Block diagram of EV controller.
Mathematical modeling can be done using following equations [33]:
• Duty Ratio:
Vin
D = 1- (17.1)
Vout
• Inductor Value:
D ∗ (1 − D) ∗ 2R
L min = (17.2)
2f
Vs
IL = (17.3)
(1 − D)2R
• Inductor Current Ripple:
Vin ∗ D ∗ T
∆ IL = (17.4)
2L
• Capacitor Value:
D∗V
C= (17.5)
R ∗ Vo ∗ f
where D = Duty Ratio; R = Resistance; L = Inductor value; C = Capacitance

value
Vin = Input Voltage; Vout = Output Voltage; Vs = Supply Voltage; f =
Frequency; Lmin = Min. value of inductor; IL = Current across Inductor.
Using the above mentioned equations, the buck-boost converter model
is shown in Figure 17.4 and its simulation result of output voltage is shown
in Figure 17.5.
Figure 17.4 Simulink model of the converter.

Figure 17.5 Simulation results.
17.3.2 Simulation and Analysis of Battery Discharging

at EV Charging Station
There are various types of batteries available in the market such as the lead-
acid battery, lithium-ion (Li-ion) battery, nickel cadmium (Ni-Cd) battery,
and nickel-metal hydride (Ni-Mh) battery. Out of these all types of batteries
we chose to use the lead-acid battery in this paper because the lead-acid bat-
tery is easily available and the cost of this battery is low. Therefore, the dis-
charging status of the battery is simulated as shown in Figure 17.6. The two
waveforms are observed in Figure 17.7: (i) graph between state of charging
(SOC) vs time and (ii) the graph between voltage vs time. The other graph
which is presented in Figure 17.8 is the nominal discharge characteristics
of the lead-acid battery. The graph of nominal discharge characteristics is
divided into three types of areas: exponential, plateau and cut-off area.
(i) The exponential area is the region where the voltage falls
exponentially. It happens at the initial stage of discharging.
(ii) In the plateau region, voltage drops slowly in the discharg-
ing process and in this region rate of chemical reaction is
stable.
(iii) The last region is the cut-off region. In this region, the
voltage of the battery drops rapidly because the voltage
of polarization increases rapidly. Cut-off voltage and total
discharging capacity is measured in this region.
Figure 17.6 Simulation of lead-acid battery.
Figure 17.7 Result for lead-acid battery.

Figure 17.8 Nominal discharge characteristics.
Thus, the simulation results with the help of a RFID tag and Aurdino
nano will help in implementing an automatic unmanned charging station
with hybrid power. The table (Table 17.1) below shows the specifications of
the components considered for software simulation.
Table 17.1 Components specification.

Components
Name Model Value
Lead-acid battery - 48 V
ARDUINO NANO ATMEGA 328P 5V
Speaker ic APR 9600 -
RFID Tag - -
RFID Reader EM-18 -
LCD 16×2 1602A -
LEDs - 1.7~3.3 V
Capacitors - 1000 μF
Resistors - 220 Ω
Voltage regulators LM317T, MC7805 -
Potentiometer - 10K
Solar panel - 54 V
Bridge rectifier W06 -
17.4 Conclusion
This work proposes a reasonable solution for charging EVs using solar
power and grid power. The solar power is used during the daytime and
the grid is used at night time or during winters when sunlight is not
powerful enough to supply the required amount of voltage. The sim-
ulation shows how the DC-DC Buck-Boost converter gives a constant
supply of 12V for charging the vehicle. For fast charging, modified
converters can be used. The RFID card stores the information of the
vehicle and its owner. The money required for charging the vehicle is
directly deducted from the vehicle owner’s RFID card as soon as the
owner sets the time for charging the vehicle. In addition, the monitor-
ing of the charging station can be done by the owner of the charging
station through cloud computing using the ThingSpeak platform. The
information of the owners of all the vehicles can be obtained by the
RFID card. The LCD at the charging station gives the charging status of
the vehicle and the speaker at the charging station gives the information
after completion of charging of the vehicle. The discharge characteris-
tics of a 48V battery are studied through simulation and shown in the
results. In addition, GPS tracking can be installed in EVs to track the
nearest charging booths. If standardization of batteries can be incorpo-
rated all over the country, it will be beneficial for both the public and
government. Thus, the planned model will be suitable for application
in the countries where a large number of Electric Vehicles can be used
to reduce the fuel consumption significantly.
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18
Improved Dual Output DC-DC Converter
for Electric Vehicle Charging Application
R. Latha *
Department of EEE, PSG College of Technology, Coimbatore, India
Abstract
The power-electronic converters are considered as the key elements used to inter-
face the power system to the electric vehicle. To adapt the output voltage and
current levels with high power quality, highly efficient DC/DC and DC/AC con-
verters are required. High gain DC-DC step-up converters are considered as an
important part of an electric vehicle system. In an electric vehicle, rapid charging
is supported only by the batteries with a high current rating. However, when using
conventional methods, the charging process requires an expensive high current
grid interface. When a large number of electric vehicles are connected to the grid
nearly at the same time, this may cause a problem of charging electric vehicles. The
work introduces an improved DC-DC converter topology based on the concept of
the conventional quadratic boost converter to support the mass charging of vehi-
cles. The proposed DC-DC converter aims to deliver power to both the AC grid
and the battery daily and also to meet the demand of the AC grid. The converter’s
first power stage is to step up the voltage to the grid integration and the converter’s
second stage is to step down the voltage for the Electric Vehicle charging applica-
tion. The performance of the proposed converter is investigated through MATLAB
simulation. Furthermore, an experimental prototype is designed to demonstrate
the satisfactory performance of the topology. The switching pulses for the control
circuit are generated using an Arduino UNO Microcontroller. The prototype of
dual output quadratic boost converter is implemented and observed dual output
voltages. The proposed topology facilitates simultaneous charging of the two types
of electric vehicles with improved efficiency and reduced components.
Keywords: DC-DC converter, incremental conductance, electric vehicle,

dual output, quadratic boost converter
*Email: [email protected]
533
18.1 Introduction
In India, the transport sector is the fastest-growing carbon emitter.
According to the Global Carbon Project projection, India is one of the
top four carbon emitters, followed by China, the US, and the European
Union. To minimize carbon emissions in the transport sector, the auto-
motive industry is moving towards electric vehicles. The recent upsurge in
the growth of Electrical Vehicles (EVs) has led to improvements in power
system reliability and the power quality of the electrical grid, but a small
panic has been arising in the market about how we are going to charge all
these vehicles. Currently, the charging infrastructure is one of the biggest
barriers to EV technology. When a large number of electric vehicles are
connected to the grid nearly at the same time, the grid should support the
additional demand. The disadvantages of electric vehicle battery charging
technology include the high cost of the battery, limited driving range, and
more charging time. Also, major problems will arise for charging electric
vehicles in rural areas where there are a lot of limitations like from the
provision of charging infrastructure. Therefore, to achieve sustainable
mobility, there is a need to move towards standalone off-grid stations for
charging the EV with the integration of renewable energy sources.
But, the output power of these sources frequently changes according
to environmental conditions. Such fluctuating output power generated by
wind and solar-based renewable energy sources is not advisable to inter-
connect with the utility grid. Therefore, the commercial success of Electric
Vehicles (EVs) will demand on advanced power management integra-
tion and advanced power converters for exploiting energy from renew-
able energy sources. An integral part of any modern-day electric vehicle
is a Power Electronic Circuit (PECs) comprising of DC-AC inverters and
DC-DC converters. To integrate solar PV to charge the battery, a DC-DC
converter is required to convert the variable AC to fixed a DC voltage.
Multiport converters have been an attractive research topic over the past
decade in integrating several renewable energy sources into a single power
processing unit. An overview of many new topologies of DC-DC convert-
ers such as isolated, non-isolated, half-bridge, full-bridge, unidirectional,
and bidirectional topologies and their applications in electric vehicles are
discussed in the literature [1–6]. The multi-input bidirectional DC to DC
converter depends on the phenomenon of backing up regenerated power
during braking. The lack of energy supply to electric vehicles due to insuf-
ficient charging stations can be satisfied with a DC-DC converter [7, 8]. An
integral DC/DC converter topology to control the bidirectional operation
Improved DC-DC Converter for EV Charging 535
to recover energy during regenerative braking and the stability of the topol-
ogy is analyzed for hybrid electric vehicle application [9]. A bidirectional
power conversion with simple and unified bidirectional control, modular
architecture, low common-mode currents, low ripple, efficient storage ele-
ment use, and low voltage switch stress are some of the important features
required for a Vehicle to Grid (V2G) integrated system. The circuit config-
uration of the converter incorporates all the bottlenecks of conventional
DC-DC converters, such as an increase in cost, a number of components,
and a slow conversion rate [10]. An innovative dual-input dual-output
(DIDO) DC-DC converter to power the connected loads even when one
of the input sources is not available proved that converter efficiency has
improved with fewer component counts and low voltage stresses [11]. For
medium voltage applications, an integrated topology of 3-Level buck and
boost converters are used to regulate the output voltage [12]. It has been
analyzed that the single-input multiple-output (SIMO) DC-DC converter
topologies have similar dynamic behavior as individual buck and boost
converters by replacing the boost converter topology control switch with
series-connected switches and using the additional switch nodes to gener-
ate step-down DC outputs [13].
In recent years, researchers have developed many new topologies for
boost converters. The cascaded converter topologies result in a quadratic
boost converter (QBC) to improve stability and control performance of the
conventional boost converter. A new quadratic boost converter topology
to increase the voltage gain of the converter using the voltage lift tech-
nique is proposed. It has a higher step-up ratio but increases the total losses
on the diodes during operations [14]. An observer-based switched linear
control law is designed for output voltage regulation of quadratic-boost
converters which is based on a min-type switching strategy [15]. Electric
vehicles are charged at home at night when lower off-peak rates may apply.
A pilot project has demonstrated the viability of providing renewable
energy charging services for electric vehicles in railway station parking lots
for commuters during the day. The power needed to feed the charging sta-
tion comes from a photovoltaic system, as well as regeneration [16]. Fast
chargers for Li-Ion batteries (LIBs) are now required for many applications
such as electric vehicles (EVs), cell phones, laptops, and tablets. In electric
charging stations (EVCSs), fast charging requires high power converters to
inject high currents during the constant current mode. It results in a high
voltage drop in the internal resistance and polarization parameters at the
end of the constant current charging process. High charging current can
also reduce battery life, so the charging process must be precisely controlled
[17]. To minimize carbon emissions in the transport sector, the automotive
industry is moving towards electric vehicles. Electric battery vehicles can

reduce greenhouse gas emissions if they are powered by renewable energy.
Solar-powered charging stations could significantly contribute to the elec-
tric vehicle charging system. PV microgrid architecture for the efficient
recharging of plug-in EVs from theoretical and numerical aspects based on
both low frequency (LF) and high frequency (HF) isolation requirements
as described in [18]. A study analyzed the feasibility of PV powered EVs
(PV-EVs), taking into account their technological and economic aspects.
Four models of power supply systems were evaluated and PV powered EVs
will be considered the most promising model soon [19]. EV charging is
classified into four types: Level-1, Level-2, Level-3, and Level-4 charging
depending on the charging time and power level of the battery. Most EV
charging that can take place at home is Level-1 (slow) charging. Level-2
charging is typically described as the primary method for both private
and public facilities which require an outlet of 240V. Level-3 and Level-4
charging are considered as fast charging and can charge the battery with
lesser time [20].
Nowadays, EV charging stations are equipped with Level-1 and Level-2
based charging schemes that take more time to charge an EV and it also
occupies more space and area. So far, no invention provides charging for
one or more energy storage devices using a single input multi-output
DC-DC converter. Single input dual output (SIDO) converters are one
such innovation compared to the conventional single input single out-
put (SISO) converter. Many researchers are doing their research on SIDO
converters based on advanced hybrid technologies. A combination of two
or more Single Input Single Output (SISO) converters can be converted
into Single Input Dual Output Converter or Dual Input Single Output.
Occasionally, DISO converters are used in the renewable energy sector
in combining solar and wind into a common power source for efficient
operation. The main drawbacks of the converters which are included in
the literature are having two separate high gain DC-DC converters that
are needed to integrate solar power to the grid, which has increased the
number of switching elements and requires more space. Also, the existing
topology contains two SISO converters and very high voltage should be
maintained at the DC link [1–6]. The challenging issues have been over-
come by the proposed topology of the SIDO converter. The work presents
a modified quadratic boost converter integrated with the buck converter to
form a single input and dual output converter for the electric vehicle bat-
tery charging application. Energy stored in the inductor can be effectively
delivered to produce buck and boost outputs. Implementing this method-
ology can reduce the charging time of the vehicle and occupies less space
to integrate. The topology presented facilitates the fast charging and a con-
ventional quadratic boost converter is combined with the buck converter
to form a single input and dual output converter.
18.2 Proposed Dual Output Quadratic Boost

Converter
Figure 18.1 shows the block diagram of the PV-fed dual output DC-DC
converter system.
The proposed system consists of a photovoltaic module, a dual output
DC-DC converter, and a three-phase inverter. The input to the proposed
converter is fed from the solar PV system. The DC-DC converter divides
the solar panel’s single input into two power output stages. The first power
stage of the converter is used for supplying the grid through a 3-phase
inverter for the entire conduction time of the converter and the second
stage of the converter is used for battery charging during commutation
instants of the converter. Compared to a conventional quadratic boost con-
verter, it has a higher voltage conversion ratio.
18.2.1 Solar PV System

18.2.1.1 Mathematical Modeling of PV System
Figure 18.2 illustrates an electrical equivalent modeling of a solar PV mod-
ule. In view of simplification, by ignoring the effects of series resistance Rs
V(PV)
MPPT
I(PV)
D
DC-Link
Three Three
Output - 1 Phase Phase
Inverter Grid
Dual Output
PV - Module DC-DC Converter
Gate Pulse
PWM
Bat Output - 2
Figure 18.1 Block diagram of proposed system.

Rs
Ii D Rsh
Figure 18.2 Equivalent circuit of solar PV module.
and parallel resistance Rsh, mathematically the output current of the PV

panel [21] can be expressed in Equation (18.1).
I = n I − n I (e )
q(V−IL R s )
p i p o
AkTns
−1 (18.1)
where
I and V - solar cell output current and voltage respectively,
Ii - photo generated current,
I0 - dark saturation current,
q - charge of an electron,
A - quality factor of the diode,
k - Boltzmann constant,
T - absolute temperature,
Rs and Rsh - series and shunt resistances of the solar cell,
np and ns - number of series and parallel solar cells.
18.2.2 Switching Methodology

To control the duty cycle of the proposed converter and for extracting the
maximum power from the solar PV module, an Incremental Conductance
(IC) algorithm is explored in this research. The dynamic performance of the
IC method overcomes the drawback of the perturb and observation-based
maximum power point tracking (MPPT) technique and tracks the peak
power even in rapidly varying environmental conditions. This algorithm
exploits the fact that the slope of the power-voltage (P-V) curve of a PV
array is equal to zero at the MPP. This method checks whether the maxi-
mum power point has been reached or not. When it reaches MPP, it stops
perturbing the operating point. If the condition is not satisfied, the direc-
tion in which the maximum power operating point must be perturbed can
Start
Measure Ipv and Vpv
dVpv=V(n)-V(n-1) & dIpv=I(n)-I(n-1)
No Yes
dVpv=0
Yes Yes
dIpv/dVpv=
dIpv=0
-I/V
No No
Yes No Yes No
dIpv/dVpv> dIpv/dVpv>
-I/V -I/V
Increase Decrease Increase Decrease
Voltage Voltage Voltage Voltage
Return
Figure 18.3 Flow chart of incremental conductance algorithm.
be calculated using the relationship between dl/dV and -I/V. In the P-V
curve, the slope is positive to the left of the maximum power point and
negative to the right of the maximum power point [22–24]. Figure 18.3
illustrates the flowchart of the Incremental Conductance algorithm.
18.2.2.1 Topology of Proposed Converter

For the same input voltage and duty cycle, the proposed converter is capa-
ble of producing a regulated output voltage. Consider, in continuous mode,
QBC is assumed to be operated in two modes such as mode 1 and mode 2.
A modified topology of the improved quadratic boost converter with dual
output is shown in Figure 18.4.
Mode 1: As shown in Figure 18.5, during this mode when S1 is turned ON

at a time t, the diode D2 is forward biased and diodes D1 and D3 are reverse
biased, so the input current rises and flows through inductor L1 and diode
D2 to switch S1 and through inductor L2 to capacitor C1. The current flowing
D2
L1 D1 L2 D3
S1
L3
Vin C1
C2
R1
D R2
C3
Figure 18.4 Dual output quadratic boost converter with single switch.
D2
L1 L2
L3
Vin C1
C2
R1
R2
D C3
Figure 18.5 Proposed topology when S1 is turned ON.
through inductor iL1 and iL2 is increasing. The diode D3 blocks the current
flowing and so load current remains constant, which is being supplied by
discharging of capacitor C2. During this mode, the inductor L3 gets charged
through the supply voltage and stores the energy. At mode 1, the following
Equations (18.2)-(18.7) are obtained.
During this mode, inductor current iL1, iL2, and iL3 are changed as repre-
sented in Equations (18.2)-(18.4).
diL1on VindT
= (18.2)
dt L1
diL 2on VC1dT

= (18.3)
dt L2
diL 3on (Vin + VC1 )dT

= (18.4)
dt L3
where diL1on , diL 2on , and diL 3on are the amount of increase in current of
dt dt dt
iL1, iL2, and iL3 respectively, d is a duty cycle of switch S1, and T is a switching
period. The capacitor currents iC1, iC2, and iC3 are expressed by Equations
(18.5), (18.6), and (18.7), respectively is the current across load resistor R1.
iC1 = −iL2 (18.5)
V01
i c2 = − = −I01 (18.6)
R1
ic3 = iL3 (18.7)
Mode 2: As shown in Figure 18.6, during this mode when switch S1 is

turned OFF, diodes D1 and D3 are forward biased, whereas D2 is reverse
biased. When the transistor in S1 is switched off at time t1, the energy accu-
mulated in the inductor L1 discharged to charge capacitor C1 through D1
and inductor L2 is discharged to charge the capacitor C2 through D3. The
load current remains constant throughout the operation which is being
supplied by energy stored in inductor L3. In this schematic, the diode D is
the freewheeling diode, which provides a path for the current through the
filter inductor when S1 is turned off. At mode 2, the following Equations
(18.8)-(18.12) are obtained.
L1 D1 L2 D3
L3
Vin C1
C2
R1
D R2
C3
Figure 18.6 Proposed topology when S1 is turned OFF.
During this mode, inductor current iL1, iL2, and iL3 are changed as repre-
sented in Equations (18.8)-(18.10).
diL1off (Vin − VC1 )(1 − d)T

= (18.8)
dt L1
diL 2off (VC1 − V01 )(1 − d)T

= (18.9)
dt L2
diL 3on VC3 (1 − d)T

= (18.10)
dt L3
diL1off diL 2off diL 3off

where , , and are the amount of increase in the cur-
dt dt dt
rent of iL1, iL2, and iL3. The capacitor currents iC1 and iC2 are expressed by
Equations (18.11) and (18.12), respectively. I01 is the current across load
resistor R1.
iC1 = iL1 – iL2 (18.11)
ic2 = iL2 – i01 (18.12)

18.2.3 Estimation of Parameters of Proposed SIDO Converter

The proposed SIDO has been designed to work in CCM mode. The switch-
ing frequency, fs = 10 kHz, is chosen to operate the proposed converter.
For designing the passive components, the inductor current and capaci-
tor voltage ripples have been considered as 20% and 5%, respectively, at
the rated power. The inductors and capacitors are selected to satisfy the
above ripple requirements. The duty ratio and various parameter values
are calculated as given in Equations (18.13)-(18.22). For the input volt-
age range of 30V to 40V, the output voltage for power stage-1 is expected
as 230V to 260V (boost voltage), the output voltage for power stage-2 is
expected as 12V to 24V (buck voltage), and the required duty cycle is D =
0.6. For a quadratic boost converter, the capacitance and inductance can
be calculated as given in Equations (18.13), (18.14), (18.15), and (18.16),
respectively [25, 26].
Iod
C1 = (18.13)
∆Vc2 fs
Iod
C2 = (18.14)
(1 − d)∆Vc1fs
Vind(1 − d)2 (18.15)

L1 =
2I0 f s
Vind
L2 = (18.16)
2I0 f s
where ΔVc1 and ΔVc2 are the change of capacitor voltages. For a quadratic
boost converter, based on the ripple requirements and the capacitor volt-
ages, the inductor currents are calculated as given in Equations (18.17),
(18.18), (18.19), and (18.20), respectively.
Vin
Vc1 = (18.17)
(1 − d)
Vin
Vc2 = (18.18)
(1 − d)2
Vin
IL1 = (18.19)
R 1 (1 − d)4
Vin
IL2 = (18.20)
R 2 (1 − d)3
For a buck converter based on the ripple requirements, the change in

current and value of inductor L3 and value of capacitor C3 are calculated as
given in Equations (18.21), (18.22), and (18.23), respectively.
(Vin − V0 )d
∆IL3 = (18.21)
Lfs
V0 (Vin − V0 )
L3 = (18.22)
IL3f s Vin
∆IL3
C3 = (18.23)
8fs ∆V0
18.2.3.1 Design Example

To design a 250W, 40 V converter, the design parameters are considered as
given in Table 18.1. To design the passive components, the allowable ripple
current is considered as 20% of the load current.
Table 18.1 Design parameter specifications.

Parameters Specifications
Input Voltage 30 V - 44 V
Frequency 10 kHz
Output Voltage at Power Stage-1 80 V - 260 V
Output Voltage at Power Stage-2 12 V - 24 V
The duty ratio of the converter is obtained using Equation (18.24)
Vg
D = 1− 2 = 66.1% (18.24)
V
The ripple factor for continuous current mode is expressed in Equation

(18.25).
∆Vo
r= = 0.039 (18.25)
Vo
18.3 Simulation of the Proposed Converter

A detailed simulation of the proposed SIDO converter is carried out in
MATLAB/SIMULINK to validate the two stages of output voltages devel-
oped across the loads for the given duty ratio.
As mentioned earlier, the proposed converter has two output power
stages. Stage one of the converter is supplied to the grid via a three-phase
inverter, where stage two of the converter is to charge a battery in the elec-
tric vehicle.
Figure 18.7(a) shows the input voltage waveform of the proposed
converter from the solar panel. The input voltage is around 40V. Figures
18.7(b) and (c) depict the output voltages obtained during boost operation
and buck operation as 255V and 13.2V, respectively. Figure 18.8(a) shows
the input current of the dual output converter. Figure 18.8(b) and (c) con-
firm that the proposed converter produces the two stages of output current
during boost operation and buck operation as 13A and 1.3A, respectively.
The obtained voltage is fed to the three-phase inverter for grid integration.
Figure 18.9 and Figure 18.10 show the grid voltage and grid current of the
converter, respectively.
18.4 Experimental Results

The proposed model is implemented as a prototype to validate its perfor-
mance. The proposed system’s hardware model is shown in Figure 18.11.
The hardware model includes a Personal Computer or Laptop with a
50
Voltage (V)
25
0
0 0.2 0.4 0.6 0.8 1
Time (secs)
(a)
400
Voltage (V)
200
0
0 0.2 0.4 0.6 0.8 1
Time (secs)
(b)
15
Voltage (V)bat
10
0
0 0.2 0.4 0.6 0.8 1
Time (secs)
(c)
Figure 18.7 Voltage waveforms of proposed converter: (a) Input voltage; (b) Output
voltage for boost operation; (c) Output voltage for buck operation.
specific IDE, Microcontroller, Gate Driver, Digital Signal Oscilloscope,

and DC-DC Converter.
The hardware model of the proposed converter and its experimental
implementation is presented in Figure 18.12 and Figure 18.13, respectively.
The Arduino UNO Microcontroller of 5V is used to generate a 1kHz PWM
pulse. The voltage is then amplified to 15V by employing the gate driver
circuit to turn on the switches of the converter. The wave forms such as
source voltage and output voltages of boost operation and buck operation
are observed using a digital storage oscilloscope (DSO) and are shown in
Figure 18.14, Figure 18.15, and Figure 18.16, respectively.
10
Current (A)
0
0 0.2 0.4 0.6 0.8 1
Time (secs)
(a)
20
Current (A)
10
0
0 0.2 0.4 0.6 0.8 1
Time (secs)
(b)
2
Current (Abat)
0
0 0.2 0.4 0.6 0.8 1
Time (secs)
(c)
Figure 18.8 Current waveforms of proposed converter: (a) Input current; (b) Output
current for boost operation; (c) Output current for buck operation.
500
Voltage (V)
-500
0 0.05 0.1 0.15 0.2
Time (secs)
Figure 18.9 Grid voltage.

50
Current (A)
-50
0 0.05 0.1 0.15 0.2
Time (secs)
Figure 18.10 Grid current.
15 V DC
Supply Power Supply
Proposed Digital Storage

Dual Output Oscilloscope
DC-DC (QBC)
PC Microcontroller Gate Driver
Converter
Figure 18.11 Block diagram of hardware model.
Dual Output
Input
(DC) Stage-1
(DC)
Stage-2
(DC)
Figure 18.12 Hardware of proposed converter.
Regulated
Supply
DSO
A PC with IDE
Arduino with Proposed

Microcontroller Converter
Gate Driver
Figure 18.13 Experimental setup of proposed converter.

DS0-X 2002A, MY53481721: Tue Mar 12 18:51:38 2019

µ
1 2.00V/ 2 0.0s 200.0s/ Auto? 1 2.07V
Agilent
Acquisition
Normal
25.0MSa/s
Channels
DC 1.00:1
DC 1.00:1
Measurements
Max(1):
5.23V
Freq(1):
Low Signal
Period(1):
T
Low Signal
+Width(1):
1 Low Signal
Save to file = scope_28
Save Recall Default/Erase Press to
Save
Figure 18.14 Experimental results of input voltage waveform.
DS0-X 2002A, MY53481721: Tue Mar 12 18:52:29 2019

1 500nV/ 2 0.0s 200.0sµ/ Stop 1 6.64V
Agilent
Acquisition
Normal
25.0MSa/s
Channels
DC 1.00:1
DC 1.00:1
T
Measurements
Max(1):
6.38V
Freq(1):
986.78Hz
Period(1):
1.0134ms
+Width(1):
1 547.80us
Autoscale Menu
Undo Fast Debug Channels Acq Mode
Autoscale Displayed Normal
Figure 18.15 Experimental results of output voltage waveform of power stage-1.

DS0-X 2002A, MY53481721: Tue Mar 12 18:53:17 2019

µ
1 2.00V/ 2 0.0s 200.0s/ Auto 1 2.20V
Agilent
Acquisition
Normal
25.0MSa/s
Channels
DC 1.00:1
DC 1.00:1
Measurements
Max(1):
3.80V
Freq(1):
985.92Hz
Period(1):
T
1.0143ms
+Width(1):
1 576.84us
Autoscale Menu
Undo Fast Debug Channels Acq Mode
Autoscale Displayed Normal
Figure 18.16 Experimental results of output voltage waveform of power stage-2.
From the experimental results, it has been observed that for the input
voltage of 5.2V DC, a corresponding output voltage of Stage-1 is 6.4V and
the output voltage at Stage-2 is 3.8V. That is for the input voltage range of 5V
to 8V, the proposed quadratic boost converter produces the dual outputs in
the range 4V to 7V and 1.3V to 3.8V at power stage-1 and power stage-2,
respectively. The proposed topology facilitates simultaneous charging of
the two different types of electric vehicles with improved efficiency and
with reduced components.
18.5 Conclusion
As multiple EVs are connected to a single charging unit, at the same time,
they may cause a problem in charging electric vehicles. Nowadays, EV
charging stations are equipped with Level-1 and Level-2 based charging
methodology. Level-1 and Level-2 based charging schemes take more time
to charge an EV. It also occupies more space and area. Two or more convert-
ers are needed to integrate the dual output charging port. Hence, the pro-
posed method is equipped with Level-3 (DC Fast Charging methodology)
based charging with reduced charging time. The proposed converter has
two states of operation based on the conducting state of the switches. The
performance of the proposed converter is investigated through MATLAB
simulation. Furthermore, an experimental prototype has been designed to

demonstrate the satisfactory performance of the topology. The overall per-
formance validates the effectiveness of the faster charging of electric vehi-
cles with the proposed topology. The proposed single circuit dual-input
dual-output DC-DC converter satisfies the problem of charging a number
electrical vehicles at the same time.
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Power Generation, 12, pp. 1640-1650, 2018.
19
DFIG Based Wind Energy Conversion
Using Direct Matrix Converter
Vineet Dahiya *
K R Mangalam University, Gurugram, India
Abstract
In modern years, among various renewable energy sources, the Wind Energy
Conversion System (WECS) has been considered one of the most rapidly growing
energy sources and has gained enormous admiration. There are several techniques
by which we can extract power efficiently from wind turbines which are to be com-
municated to the grid. A variable speed WECS that allows variable speed opera-
tion over a large, but still restricted, range is a Doubly Fed Induction Generator
(DFIG) with the stator windings connected directly to the three-phase constant–
frequency grid and the rotor windings connected to a partial scale back-to-back
converter. The generated power is transported by AC-AC transmission by using a
Direct Matrix Converter (DMC) instead of AC-DC-AC transmission which was
used previously as later reduces the cost of converters and is reliable also. There
are various control and modulation techniques used in Matrix converter which
controls the switching of power electronics devices during commutation. IGBT is
mainly used by switch nowadays in Matrix Converter.
Keywords: Wind energy conversion system, direct matrix converter, doubly fed
induction generator, predictive current control
*
553
Chapter-I
Introduction
In today’s world due to increase in demand of power and fast deplet-
ing resources, there is need of alternative power sources which not only
meet existing power demand but also are environment friendly. There
are numerous renewable sources available for example Solar, Wind,
Geothermal, Tidal etc. Out of all these sources Wind Energy is emerging as
an established technology which provides a bright, stable & limitless cause
of energy for maintaining the endlessly rising power necessities of human
race. Wind Energy Conversion System is also a power technology that has
made vast progression from the last two decades with the development in
wind power technologies and its control and modulation techniques.
The Wind Energy Conversion System (WECS) is considered as one of
the fast-growing energy sources among various renewable energy sources
available in India. In recent times majority of wind turbines are being
erected in large wind farms which are located in the areas which are not
connected to grid and have large storage system through batteries. Also,
there is WECS that is linked to grid and power is fed to the grid. There are
various techniques by which we can extract power efficiently from wind
turbines which is to be transmitted to the grid.
In year 2017 the overall capacity of wind reached 539291 MW, inter-
nationally. Many of the countries have achieved soaring intensity of wind
manufacture by the end of 2017 such as China produces 18839235 MW
of wind energy which is 35% of total worldwide production followed by
USA and Germany which produces 89077 MW and 56132 MW which is
17% and 10% of total worldwide production respectively. India is ranked
fourth with 32848 MW which is 6% of total worldwide production and
is expected to add additional 2.5-3 GW in financial year 2019. Figure
19.1 shows current wind energy production scenario in India with Tamil
Nadu having 44.23% of the total wind produced share in India followed
by Maharashtra and Gujarat with 20.10% and 14.42% respectively. Now a
days onshore production of wind is there as there is plenty of wind blowing
in the middle of the sea as compared to offshore wind installations where
wind speed is less and is not so strong as compared to On shore wind.
Due to advancements in WECS technologies wind turbines are installed
at both on and off shore locations. As there is improvement in new tech-
niques in design of wind turbines, power electronics devices, protection
devices and machine drives that no a days there are several methods by
DFIG Based WECS Using Matrix Converter 555
West Bengal Andhra

Others
Pradesh
0.02% 0.01%
1.45% Gujarat
14.42%
Tamil Nadu Karnataka
44.23% 11.84%
Kerala
Maharasthra 0.12%
Rajasthan 20.10%
6.23% Madhya
Pradesh
1.44%
Figure 19.1 Present day scenario of wind energy in India.
which we can extract power efficiently from wind turbines which is to

be communicated to the grid. The three kinds of WECS that are pres-
ent worldwide that uses large wind turbines these are (i) Squirrel Cage
Induction Generator (SCIG) that operates at fixed speed and can be con-
tracted around the range of about nearly the synchronous speed, when
linked right to the grid. Most of the fixed speed WECS with (SCIG) is out-
fitted with multi-stage gear box, easy starter & capacitor bank. The robust
nature, economical, low maintenance & simplicity of SCIG can be utilized
effectively in several WECS There are numerous cons of the SCIG like high
mechanical & fatigue stress, negligible optimization of aerodynamic effi-
cacy, need for large gear box & has absolutely nil voltage support to grid
etc. Another type is DFIG (Doubly Feb Induction Generator) [5, 6]. It is
known to be a WECS variable speed, as it permits varying speed over a
small and wide range. The stator windings of WECS using DFIG are linked
with the 3 phase constant frequency grid which is then connected to end-
to-end PWM converters using their rotor windings. In such type of drive
a multi-stage gear box is used. To achieve maximum power one can use
DFIG in WECS and can get smoother grid connection, high controllabil-
ity and It is considered to be a WECS variable speed, since it allows for a
wide variety of speeds [14, 19, 36, 37, 40]. A turbine pitch control is used
to adjust speed which maximizes the power which is generated at a given
wind speed. Another important factor is that a small percentage of the
total system power is possessed by the power convertor if the rotor current
is tried to control by using field-oriented control by having double-sided
PWM inverters. The three-stage gearbox DFIG is considered the lightest,
low-cost solution with standard equipment. Refer to Figure 19.2 this type
of arrangement have been used, in this type of WECS in such a way that
Grid
RSC GSC
Transformer
DFIG
RSC Controller GSC Controller
Figure 19.2 Doubly fed induction generator. (https://ieeexplore.ieee.org/

document/6136175).
DFIG is connected to the stator windings to the perpetual frequency which

is having three-phase supply consisting of stand-alone or grid connected
network. The windings of the rotor are connected to end-to-end converter
with a fractional scale. The advantage of such type of generator is that it
offers high controllability along with flatter grid connection. By using
end-to-end power converters with rating of approx. 30% of the generator’s
capacity, it also allows maximum extraction of power along with reactive
power compensation. The DFIG can be integrated with Matrix Converters
which uses predictive current control & modulation technique for the
smooth operation of the system from generation side to the grid side [13].
The rotor of DFIG consumes energy when it is at sub synchronous
speed and it can operate in super synchronous speed it generates power.
The main characteristic of DFIG is that in accordance with the speed of the
rotor frequency, by which current is produced or consumed, varies in the
rotor. In order to rectify this behavior a bi-directional power electronic
converter is used and that can be variable source or load in rotor circuit.
The third one which is also gaining popularity now days by using fully
controlled power converter that uses full capacity of the generator is vari-
able speed WECS It can be made operational by using only a synchronous
generator. If broadly classified synchronous generator are of two types
(i) Electrically Excited Synchronous Generator (E.E.S.G.) and (ii) Permanent
Magnet Synchronous Generator (PMSG). These are shown in Figure
19.3. As in todays world there is need of the high efficiency which can be
obtained by using alternative generators namely PMSG The efficiency can
also be increased by the use of large number of poles so that the need of
Frequency
Converter
Grid
SG
Figure 19.3 Permanent Magnet Synchronous Generator (PMSG).
the gear box can be eliminated. With the above said benefits there are some
disadvantages of PMSG based WECS [3, 26, 39]. These problems are faced
during start-up, synchronization and voltage regulation.
Back in 1970’s the Wind Energy Conversion System used Direct-in line
Adjustable Speed Generators (ASG) which has poor efficiency and high
cost of filters. The later was substituted by Doubly Fed Induction Generator
which has many benefits as related to Direct in Line ASG. DFIG uses
Insulated Gate Bipolar Transistors (IGBT) connected to rotor windings
that works as 4 quadrant AC-TO-AC converter. Due to advancement in
power electronics technology since 1980s most of the WECS are fitted with
DFIG. The aim is to offer variable speed wind turbines that offer most effi-
cient configurations for conservation of wind energy.
The capacity of wind turbine is increasing and as a result wind tech-
nology is continuously evolving. The doubly Fed Induction machine lost
its importance and was considered as a redundant by the mid 1990’s, as
it used expensive drives with very slight future prospects. Thanks to
advances in power converter technology by the end of the 1990’s, the wind
industry had a good success with the implementation of a power con-
verter for erratic speed service. In April 1996, the German company Tacke
Windtechnik (now known as GE) launched a DFIG model with regulated
variable speeds.
After few months 500 KW DE wind (now Daewoo) prototype was
introduced followed by many prototypes of DFIG. As in earlier years when
power electronics techniques were not there, the rotor of DFIG was often
fitted with extra resistor capacity so that variable speed operation can be
achieved as starting torque was increased and starting current was reduced,
but it proved to be rather insufficient solution.
The generator field brushes that supply power to the generator rotor
have a three-four-month life span that is relatively shorter than PMSG. As
the new technology evolved the life span gradually improved to 6 months
and longer. An estimate of 30,000 or more wind turbines fitted with DFIG
have varied power ratings. The dynamic control of DFIG has the control
systems that have capacity to excerpt complete power from the wind.
The power generated by the wind turbine is dependent on the speed
of the generator. “By connecting the maximum Cp points of each curve,
which allows the system to keep turbine on this curve as the wind varies,
it can be explained using a curve.” DFIG rotor is connected to the power
electronic convertor where maximum control is there [14, 19].
The Grid side converter helps to control DC link voltage and reactive
power flow between converter and grid. To ensure system stability and
optimum control over DFIG, the following variables can be controlled:
torque, active and reactive power of Grid Side Converter variables such as
reactive power and DC bus voltage. These problems can be overcome by
evaluating both sides of the back-to-back converter voltage and therefore
DFIG can achieve the aforementioned reference values of the controlled
system.
19.1 Introduction to Matrix Converters

The power generated by DFIG has to be transmitted from generator side
to the grid side. Earlier, there were two methods to transfer power from
generator side to the grid side namely ac-dc-ac conversion (HVDC) and
AC-AC (Direct Matrix Converter) conversion. The HVDC scheme are seg-
regated into line commutated converter (LCC - HVDC) and voltage source
converter (VSC - HVDC). Out of these the most commonly used technique
is Modular Multilevel VSC – HVDC which is mostly used for wind farm
integration. Now a days there is requirement for high power which can
be achieved by the introduction of Modular multilevel converter HVDC
(MMC - HVDC) technology which is suitable for high power application.
The above said method involves large storage elements which increased
the weight and size of the converters so to overcome this issue a new tech-
nology named as Direct Matrix Converter (D.M.C.) was introduced which
simple and compact circuit is allowing transmission of power from gen-
erating side to grid side without using AC-DC-AC link [1, 2, 4, 8, 20, 28,
30, 35, 38]. This technique will have benefits of varying amplitude and
frequency as it is possible to have AC-AC transmission. Sinusoidal input

and output waveforms can also be provided with a unit power factor and
four quadrant converter operations are possible. Matrix converter tech-
nique uses Maximum Power Point Tracking controller while using DFIG
in WECS to control the operation of power conversion. Wind speed is
variable during day time that requires the machine with large speed varia-
tion which is possible by having the interface between generator and grid
side based on the configuration of DFIG based WECS via Direct Matrix
Converter (DMC) which helps in integration of generating side to the grid
side.
19.2 Introduction to Control and Modulation

Techniques in Matrix Convertor
The most challenging part when using Matrix Converter was the switch-
ing of bi-directional switches during converter service [7, 18, 45]. Yet new
multi-step commutation techniques have been developed with advances in
the field of power electronics technology. These techniques resulted in con-
stant and fast growth that is related to the development of new topologies
in matrix convertor which are beneficial in industrial applications. There
are various modulations and control techniques available in the literature
and in industry also.
The common techniques that were used earlier are as follows:
i. Space Vector Modulation (SVM)

ii. Direct Torque Ccontrol (DTC)
iii. Venturini Carrier Based Pulse with Modulation (CB-PWM)
Apart from the above-mentioned methods techniques such as Fuzzy

Control, Neural Networks and Genetic Algorithms were used. These were
time consuming and complex. Out of various control and modulation
techniques as depicted above the researcher has used Predictive current
control scheme as it nearly brings the measured variables to the closest
relevant references at the end of the sampling period, thus future value of
currents can be determined by utilizing the converter and load models.
This method uses distinct characteristics of power converters and easy exe-
cution and spontaneous approach [41, 42, 50, 51].
Figure 19.4 depicts types of modulation and control methods used in
matrix converters.
Modulation and Control Methods

for Matrix Converters
Scalar Pulse Width Direct Torque Model

Direct Power Other
Techniques Modulation Control Predictive
Control [16, 17]
Control
Direct Career Space Vector

Transfer Scalar (Roy) Predictive Predictive Predictive Unity
Based PWM Modulation Predictive
Function Current Control Torque Control Power Control Voltage Control Transfer
Figure 19.4 Different control & modulation methods for matrix converters.
High and stable output power can be achieved by this method which
has new and unique arrangements and configurations of generators & con-
vertors. In recent times the most of the wind turbines are being erected in
big wind farms which are located in the areas which are not connected to
grid and have large storage system through batteries. Apart from stand-
alone systems there are grid connected systems also by which WECS is
connected to grid and power is fed to grid and trough this technique power
can be extracted competently from wind turbines and then it will be trans-
mitted to the grid [12].
The matrix converter (MC) is power circuit that is simple and compact
power circuit. It attaches the acsource directly without the need for large
storage elements with an ac load circuit. With this converter there is no
need to convert power from ac-dc-ac for transmission.
With varied amplitude and frequency, sinusoidal input and output
power waveforms with unit power factors and regenerative energy, out-
put voltage production is easily achieved. The Model Predictive Control
(MPC) technique examines the discreet and non-linear approach of con-
verters and drives in power electronics. This chapter discusses the appli-
cation of Predictive Control Schemes projected for different topologies
of MCs. As compared to other conventional and popular techniques like
Venturi, carrier-based pulse width modulation (CB-PWM), Space vec-
tor modulation, Predictive Current Control, Predictive power control,
Predictive voltage control and direct torque control (DTC) are also some
of the methods in control and modulation of matrix converters. A highly
interesting solution for MCs command has been shown by the Predictive
Control Scheme. The use of multi-phase commutation techniques and new
technologies in control elements has solved the problem of bidirectional
switches switching [15–18].
Predictive control can be seen as a desirable regulatory approach
[20–25]. With real power conversions and drives, it offers benefits such as
mobility, durability and efficiency. In order to avoid variable frequency and
vibration shifts, the advantages of predictive monitoring can be improved
by switching strategies. Other numerical integration algorithms can be
used on the digital platform to solve sampling time constraints.
The integration of DFIG with Predictive Current control technique for
generation and transmission of power from generation side to grid side is
better option as it improves overall performance of the system.
19.3 Introduction to Predictive Control Techniques

There are various control and modulation techniques. The predictive strat-
egy is considered a propitious substitute of control matrix converters as it
includes extra aspects in the control which makes it simple and flexible.
The implementation of this strategy can be useful in renewable energy, grid
interconnection, multi-drive systems control etc. Study of the proposal for
predictive control for matrix converters and other acquired topologies in
conjunction with cascades in various industrial applications, including
renewable energies and the multi-drive system. Different control strate-
gies and applications are discussed in this paper that implement predic-
tive control techniques. There have been debates on the Model Predictive
Control (MPC), which provides a robust and superior solution for the con-
trol of electric energy. The new approach takes account of the discreet and
non-linear design of power converters and drives and shows an efficient
effect on power electronics operation in the near prospect.
Chapter-II
Concept and System Description: Doubly Fed

Induction Generator (DFIG) in Wind Energy
Conversion System
This chapter addresses fundamental aspects of the wind and working use
of the Doubly Fed Induction Generator used in wind energy conversion
systems. there is need for clean and efficient production of energy. Wind
energy is emerging as the fastest growing technology by means of which
power is generated due to advancement in power electronics technology.
There are many generators available in the market which generates power
from wind turbine but DFIG has edge over other generations due to its
robust construction, operation at variable speeds and efficient operation
when integrated with the grid [40].
In India most of the erection of wind farms is offshore installations which
require variable speed operation as wind is not constant during entire day,
so the biggest challenge is to extract maximum power from the variable
wind speed which is possible only by using DFIG as the stator winding of
it is connected to the grid directly and rotor is connected via back to back
converters which allows operation of generator with variable frequency.
The three-phase phase induction generator in which three-phase AC

signal is fed on both rotor and stator is called Doubly Fed Induction
Generator (DFIG). In DFIG a multiphase windings are used on the sta-
tor as well as rotor bodies. It also contains multiphase slip ring assembly
which transfers power to the rotor. Wind turbine rotates when gust of wind
falls on them and electricity is generated by DFIG. The most widely used
renewable sources now a day is wind energy. There are large number of big
wind turbines which rotates in accordance with the wind speed and from
this procedure electricity is generated [8, 14, 19].
Typical wind turbine power output is shown in Figure 19.5. When there
is no wind, turbine refuses to start but as wind gradually builds up the
turbine starts moving. To move turbine for the first time minimum wind
speed is essential by the generator to produce the required power which
is sufficient to transfer that power to the grid. The speed at which turbine
moves for the first time is called Cut-in speed and is normally between
3-4m/s.
Gradually, as the speed of the wind exceeds cut-in speed then the tur-
bine starts moving faster. The output power also increases and it touches
the maximum limit, at which generator is capable of generating power
Power (kilowatts)
Rated output speed Cut-out speed
Rated output power
Cut-in speed
3.5 14 25
Steady wind speed (metres/second)
Typical wind turbine power output with steady wind speed
Figure 19.5 Wind power output curve (Source: https://ieeexplore.ieee.org/

document/5986703).
called as Rated Output Power. On the other hand Rated Output Speed is
the speed at which it is achieved which is usually 17-18 m/s. The develop-
ment of the turbine is designed in such a way that energy is limited to the
peak rate when wind speed is reached at lower levels and there is no change
in output power, which also relies on changing the blade angles for usually
large turbines.
When the speed of the turbine rise above rated output wind speed then
there are chances that it may damage the rotor of the generator due to rise
in forces on the turbine structure. Normally this speed is called Cut-Out
speed and is 25m/s. To bring rotor to standstill and overcome the above
said problem Braking System is applied.
There is a theoretical limit on the extraction of wind energy from wind
turbines which is called as Betz limit and it is usually 59m/s.
The kinetic energy is transformed into mechanical energy, WECS works
on this principle. The air that has kinetic energy which is transformed into
mechanical energy by creating a torque. And the turbine pulls out the
resulting power. Quality is primarily defined by the analysis of how energy
differs with wind speed. The amount of power extracted depends upon the
air density and speed of the wind.
The wind power that is produced by the turbine is represented by the
given equation (19.1):
Wind Turbine Cp Characteristic (pitch angle increases by step of 2 deg.)

0.6
0.5 Pitch angle 0 degree
0.4
0.3
Cp
0.2
0.1
0
0 5 10 15 20 25
Lambda
Figure 19.6 Wind turbine characteristics.

1
P = CP ρ AV 3 (19.1)
2
In the above said equation CP denotes wind power coefficient whereas
ρ represents air density (equal to 1.225kg/m3 at sea level at temperature
T=288K), the area of the turbine is denoted by A in m3 and wind velocity
is represented by V in m/sec. The wind turbine changes portion of kinetic
energy into mechanical energy and it is denoted power coefficient CP .
‘β’ is the function of blade pitch angle, ‘λ’ is TSR ‘Tip Speed Ratio’ (TSR)
is Cp.
The ratio of turbine blade linear speed and wind speed is called TSR
denoted by:
Rω
λ= (19.2)
V
Substituting (19.2) in (19.1), we have:

3
1 R
P = C p (λ)ρ A   ω 3 (19.3)
2 λ
The corresponding output torque of the wind turbine is given by:
1
Tturbine = ρCP V λ (19.4)
2
Here, R is the radius of the wind turbine rotor (m). The power coefficient is
maximum at a specific value of tip speed ratio. By working the turbine at flex-
ible speed, wind turbine can excerpt maximum power. Figure 19.5 shows the
turbine CP curve which follows cubic relationship. In Figure 19.6 one can see
values of turbine power, tip speed ratio (λ) and CP. “The wind speed is taken
as 15m/s, the turbine output power is 1 pu of its rated power, the pitch angle
is 8.7 degree and the generator speed is 1.2 pu.” The variable speed induction
generator gives flexible rotor speed characteristics which is advantageous over
synchronous generator which gives constant speed characteristics [36, 37].
The term Doubly nourished implies that there exists 2 three-stage wind-
ings. In which one is stationary and other is turning. Both the windings
are associated independently to the contraption outside the generator. The
stationary winding is associated with the generator and generates 3-stage
AC control at the ideal network recurrence. The subsequent winding is
Wind Turbine Characteristics (w = 1.2 pu, pitch angle increases by step of 2 deg.)
1.5
1
P (pu)
0.5
0
0 5 10 15 20 25 30 35
20
10
Lambda
0
0 5 10 15 20 25 30 35
0.6
0.5
0.4
0.3
Cp
0.2
0.1
0
0 5 10 15 20 25 30 35
Wind Speed (m/s)
Figure 19.7 Turbine power, tip speed ratio and CP curves.
appended to the rotor, which is associated to3-stage AC control at variable

recurrence. The info vitality is utilized in recurrence and stage to represent
the turbine’s speed contrasts.
DFIG is an injury rotor Induction Machine wherein stator and rotor
voltages are not rise to, because of its change proportion. In DFIG the
consecutive converter is situated on the rotor circuit and stator is related
to network. While filling in as generator, this machine can work in both
sub and too synchronous rates. Due to above said quality breeze turbine is
equipped to work in a wide scope of speeds from 60% to 110% of appraised
speed with high productivity. AC to DC to AC converter is required to
adjust the frequency and phase which is constructed from very large IGBT
semiconductors. For this bi-directional convertor is used that can permit
power in any direction. Power can flow from both the winding.
As mentioned earlier there are 3 types of induction generators in WECS:
i) Squirrel cage induction generator (SCIG),

ii) Wound rotor induction generator (WRIG),
iii) Doubly fed Induction generator (DFIG).
The fixed speed operation is carried out by SCIG which accounts for less
efficiency and in case of WRIG, there is external resistor is dynamically
varied which is connected to the rotor side using connection of power elec-
tronics switches. To understand the use of WECS, the operation of DFIG
and its converter plays an important role in better understanding of the
above said technique. When induction generator is running above syn-
chronous speed, power is generated. Figure 19.8 shows that when machine
operates below the synchronous speed then it acts as a motor and when
the induction machine is running above the synchronous speed then it
behaves as a generator.
The frequency of rotor currents is given by equation:
N rotor ∗ N poles
Frotor = f bus - (19.5)
120
If a 6 pole machine operates in sub synchronous speed for eg at 800

r.p.m., then as per the Equation 19.5. The frequency of rotor currents is
20Hz that is induced in the machine.
If the machine operates at synchronous speed for example, If the
machine rotates at 1200 r.p.m, using the equation, the frequency of rotor
currents induced in the machine is calculated as 0 Hz. On the other hand
if the machine operates at super synchronous speed for example, If the
machine rotates at 1600 r.p.m., then using the equation one can calcu-
late the frequency of rotor currents induced in the machine which will be
-20 Hz.
power cabinet
stator contractor stator circuit breaker
gearbox
brake slip ring

wind turbine converter
generator
(up to 2000 grid
rpm) transformer
generator- grid-side
side medium voltage
switchgear
rotor bearing pitch
converter control converter
drive contactor
wind turbine
control
Figure 19.8 Block diagram of DFIG in WECS.

From the above calculations it is proved that power is carried from the sta-
tor of the machine only while rotor absorbs the power at sub-synchronous
speed. On the other hand at synchronous speed no power is absorbed or
distributed from the rotor side of the machine and in the stator side power
is delivered and lastly when machine is operating in super-synchronous
mode, the power is deliveredfrom the stator side and rotor side of machine
as well.
There are different types of DFIG
1) Cascaded DFIG-As the name suggests in this type of gener-

ator two DFIG’s having wound rotor are connected mechan-
ically as well as electrically.
2) Single Frame Cascaded DFIG- In this type the two genera-
tors are enclosed in the same frame.
3) Brushless DFIG- This will be those a large portion custom-
ary kind for generator. In this the stator winding will be
associated straightforwardly of the grid inasmuch as those
rotor is associated with those control electronic converter.
4) Doubly-fed reluctance Machine: In this type of generator,
the definition of the stator is based on the brushlee DFIG,
where the law of resistance is known as the rotor.
Figure 19.9 indicates the essential model about DFIG wherein energy is
transported from wind of the electric grid. In this model portrayed in this
DFIG TRANSFO
Wind
GEARBOX PARTIAL SCALE CONV
AC/DC DC/AC LOW

WT
CONV CONV PASS LOAD OR
FILTER GRID
CONTROL
Figure 19.9 DFIG model.

research, the stator of the wound rotor incitement engine will be joined with
grids which are located far from the generation side. On the different side,
those rotor will be associated again on over should PWM voltage sourball
inverters which need an alternate dc association. It administers the control
stream parity between the AC side and the dc side of the grid converter. Rotor
excitation is provided by a motor aspect power converter which helps with
active and reactive power management on each side of the stator coil and
rotor. DFIG can also be used as a generator or motor at sub and super-syn-
chronous speeds. As a result, four possible operating modes are required, but
only two quadrants are required in WECS as shown in Figure 19.10.
By the use of DFIG there are various advantages as compared to other
generators used in wind energy conversion system which are explained as
ØØ The grid can take continuous frequency output signal

regardless having adjustable speed of the rotor.
ØØ As the above said generator works in variable speed opera-
tion, it is easier to have maximum power tracking.
ØØ The power is fed to both stator and rotor then independent
active and reactive power controls can be achieved.
ØØ In the event of failure of converter it can be made to run as
SCIG also.
ØØ For different speed operation it is possible to keep constant
DC-link voltage.
Tm
Vs
DFIG
Lg Grid
3~ =
Vdc
= 3~
Rotor Side Grid Side
Converter Converter
Figure 19.10 Wind turbine driven DFIG.

ØØ There is reduced mechanical stress and almost negligible

rotor torque variations in DFIG.
ØØ As there is tremendous improvement in power electronics
technology, the converters require low power rating thus
enabling the low overall cost of control system.
ØØ As explained earlier due to operation at sub synchronous
and super synchronous mode power factor can be main-
tained at unity.
ØØ The electric power can be generated even at low wind speeds
in case of DFIG.
ØØ Apart from low cost the fraction of total load that accounts
for 20-30% is handled by power electronic converter which
is not possible in other generators used in wind energy con-
version system.
In this work, the model of the wind farm is designed to have six 1.5 MW
of wind with a total capacity of 9 MW of turbines. These turbines need aid
associated with a 25KV appropriation framework that transmits force with
a 120 KV grid through a 30Km 25KV feeder. Those DFIG-installed wind
turbines hold numerous wound rotor incitement generators, Furthermore
PWM convertor based AC/DC/AC IGBT. The DFIG stator winding will be
straightforwardly related with the 50Hz grid and the rotor may be nour-
ished through the variable recurrence AC/DC/AC converter. The DFIG
methodology derives full energy from the wind by raising the frequency
of the turbine. For low wind speeds, as the mechanical pressure on the
turbine is reduced during a sudden steep w-rush.
The constant wind speed is taken as 15m/s in this example. Speed of
turbine is kept at 1.2 p u by using Torque controller in the control system.
The reactive power created by the wind turbine is kept at 0 MVAr.
The power output from back-to-back PWM convertors through com-
mon DC link is feed to the grid. The convertor connected to induction
generator side acts as a PWM rectifier. The one connected to grid side acts
as PWM invertor as DFIG works in super synchronous mode. It rectifier
converts variable voltage and frequency at machine rotor terminals to DC
voltage.
The output voltage is given by Equation (19.6):
 3 2 3
Vr =  V n (19.6)
 π   2  ds i
This chapter shows that DFIG is well suited for operations where vari-
able speed is required as compared to other generators due to its design
and reliable function under different operating conditions. DFIG can work
as both standalone system as well as grid connected system. By the use of
DFIG Maximum power point tracking of wind is possible which gives bet-
ter result and improves the overall efficiency of the system as compared to
other generators used in wind energy conversion system.
This chapter concludes with the fact that due to design of the DFIG, it
has the ability to work in sub synchronous and super synchronous speeds
which help in extraction of wind power at low speeds also which help in
keeping the performance of the whole system stable, efficient with opera-
tion with unity power factor.
Chapter–III
Modeling and Simulation of DFIG in MATLAB

In this chapter the simulation model of a wind firm using DFIG in
MATLAB is shown. A wind farm is designed consisting of six 1.5 MW
and has the total capacity of 9 MW. The values of different variables such
as active, reactive power, frequency etc. are chosen on the basis of previ-
ous research and modified these values and results are compared with the
previous result.
LC filter is connected in DC link so as to get smooth DC output voltage.
The DC link capacitor is used to provide isolation between the two conver-
tors as shown in Figure 19.11.
The design shown in Figure 19.11 provides a detailed example of IGBT
electronic power converters. The design must be discretized at a minor
time for approximately 5 microseconds to achieve acceptable precision at
1620 Hz and 2700 Hz interchangeable frequencies. The above design is
(COMBINATION
TRANSMISSION CONNECTED
9 MW OF 6 X 1.5 MW
LINE SET UP LOAD
WIND UNITS) SCOPE AND
FARM STEP-UP STEP- COMPARING
TRANSFORMER POWER GUI, PARAMETERS
DOWN UNIT
DC MICRO GRID – DFIG FEEDER SET
BUS
WIND TURBINE UP
Figure 19.11 DFIG wind farm model.

ideal for tracking harmonics and complex output of the control system
over hundreds of milliseconds to one second.
Using the initial state vector, this example starts the simulation from a
stable state.
Figure 19.12 shows “the active power P (MW), the reactive power Q
(MVAr), the DC voltage (VDC), the wind speed Wr (pu)” when a remote
fault occurs on the 120 kV system. In this example, the simulation starts
at steady state by initializing all states as due to turbine time inertia if the
initial state is not set, then the time constant Figure 19.12 shows “Active
power P (MW), reactive power as Q (MVAr), DC voltage denoted by
(VDC), wind speed is represented by Wr (pu)” when steady state is reached
and fault is cleared.
In this research an example is taken in which there is a remote fault
which occurs on the 120 kV system and at 0.03 seconds 0.5 pu voltage drop
is formulated and stable state and dynamic response of the system due to
voltage sag is examined. Wind farm initially produced 9 MW and the speed
of turbine is retained at 1.2 pu of the generator synchronous speed. The DC
voltage and the reactive power is kept at 1150V and 0 MVAr respectively.
All of a sudden the positive sequence voltage crumbles to 0.5 pu at time
duration t=0.03s. It produces oscillation on the DC bus voltage as well as on
the output power of DFIG As control system in a bid to adjust the voltage on
DC bus at its fixed value of 1150 V and reactive power bus at its fixed value
of 0 MVAR which occurs during voltage sag, then it takes approximately 4
cycles for a system to recover from a fault that occurred in 12kV line.
2
Vabc_B575 (pu)
0
-2
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
2
labc_B575 (pu)
0
-2
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
15
P(MW)
10
5
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
5 Q(Mvar)
0
-5
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
1300
Vdc (V)
1200
1100
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
wr (pu)
1.25
1.2
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
2 Vabc_B25 (pu)
0
-2
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
labc_B25 (pu)
2
0
-2
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Figure 19.12 P (MW), Q (MVAr), DC voltage (VDC), Wr (pu) when a remote fault on the
120-kV system occurs.
Vabc_B575 (pu)
2
-2
labc_B575 (pu)
5
-5
P (MW)
20
-20
Q (mvar)
0
-5
-10
Vdc (V)
1300
1200
1100
wr (pu)
1.3
1.2
1.1
Vabc_B25 (pu)
2
-2
labc_B25 (pu)
5
-5
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Figure 19.13 P (MW), Q (MVAr), DC voltage (VDC), Wr (pu) when steady state is reached
and fault is cleared.
This chapter also shows the fault clearing time of Doubly Fed Induction
with parameters remaining constant in both the cases when a remote fault
occurs in the system. The reactive power is restorted to 1.2 p.u in 4 cycles
and reactive power approaches to zero. The DC voltage is maintained at
1150V.
Chapter-IV
The Matrix Converter and Predictive Control

Technique
In this chapter concept of Matrix converter, various control and modu-
lation of matrix converter and mathematical modeling of predictive cur-
rent control technique is shown. The power generated is transmitted to
the grid by various methods but by the use of direct matrix converter it is
communicated in reliable and efficient manner by using power electron-
ics switches and transfer of power is AC-AC transmission as compared to
AC-DC-AC transmission [43]. To control the operation of these power
electronic switches there are various control and modulation techniques
by which smooth operation of switches will be possible for different cycles
and sampling period.
MC power topology is shown in Figure 19.14 consisting of bidirectional
switches attaching the input side with no dc-link storage component. On
the input side of the converter, an input filter is attached to prevent over-
voltage due to the short circuit and to remove harmonics in the input
current.
VsA
Rf Lf
isA iA
SAa SAb SAc

vsB Cf VA
isB iB
SBa SBb SBc

N VB
VsC
isC iC
SCa SCb SCc

VC
Va Vb VC
ia ib iC
AC
Motor
Figure 19.14 Direct matrix converter’s topology.

Equation (19.7) and (19.8) gives the relation amid the input and output
variables of the matrix converter as:
Vo = T(Sij)vi (19.7)
Ii = T(Sij)Tio (19.8)
Here, ‘T’ represents instantaneous transfer matrix and can be defined as:
SAa SBa SCa 

T(Sij ) = SAb SBb SCb  (19.9)
SAc SBc SCc 
dAj + dBj + dCj = 1 (19.10)
where, dij = duty cycle of the switch Sij.

Equation (19.9) <1 indicates an open circuit source and
Equation (19.9) >1 shows a short-circuit of the voltage source
Equations (19.9) and (19.10) signify the switching function T of the
matrix converter for the output voltage and the input currents
Vout = T × Vin (19.11)
Va  SAa SAb SAc  VA 

 =  
Vb  SBa SBb SBc  × VB  (19.12)
Vc  SCa SCb SCc  VC 
where,
Va  SAa SAb SAc  VA 

 , T =    
Vout = Vb  SBa SBb SBc  and Vin = VB  (19.13)
Vc  SCa
 SCb SCc  VC 
lin = TT × lout (19.14)

 I A  SAa SAb SAc   I a 

 =  
 I B  SBa SBb SBc  ×  Ib  (19.15)
 IC  SCa SCb SCc   I c 
where,
I A  SAa SAb SAc  Ia 

 , T =    
Iin =  I B  T SBa SBb SBc  and I out =  Ib  (19.16)
 IC  SCa
 SCb SCc   I c 
and VA, VB, VC and Va, Vb, Vc are the input and the output phase voltages
and IA, IB, IC and Ia, Ib, Ic are the input and the output currents
Suitable combinations of on and off switches can be obtained from
equations (19.13) and (19.16) so as to achieve the desired output voltages
can be achieved for proper control and modulation scheme.
The identification of direct AC-to-AC transformers in three separate
topological approaches is shown in Figure 19.15. The first solution is to
change the frequency of the AC waveform by the AC voltage regulator.
“The second approach is the cyclo-converter when the right output
speed” is considerably below the input frequency [34, 51]. “The third
approach is the most robust matrix converter without limits of performance
and amplitude. In other words, input may be AC and DC, both in DC and
AC” [38, 39].
Input in 3 phases. Therefore, the topology of the matrix converter
promises to transform universal power, including “AC-to-DC, DC-to-AC,
DC-to-DC and AC-to-AC”. The matrix converter provides many import-
ant benefits, including the variable power factor, quadrant control, high
quality waveforms for input and output, and a high power density. As a
standby for conventional AC-DC-AC converters for mutable voltage and
VF AC drive applications, it received extensive research focus.
“The matrix converter is the force-commutated version of cyclo-
converters, which overcomes the disadvantage of conventional cyclo-
converters such as frequency conversion limitations, rich output voltage
harmonics and increased switch numbers”. “They can be categorized as
matrix converters, direct and indirect. Figure 19.15 shows a set of 3 bidi-
rectional switches with a direct or conventional matrix converter (CMC).
The cascade of the operated rectifier and the inverter topologies is an indi-
rect or sparse matrix converter without the associated DC”.
AC-to-AC
Converter topologies
Direct AC-to-AC AC-to-DC-to-AC

Converter topologies Converter topologies
Conversion type
(Frequency & Amplitude)
AC Voltage Regulator
Converstion type
(Amplitude)
Cyclo-Converter
Conversion type
(Frequency & Amplitude) Matrix Converter
Conversion type
(Frequency & Amplitude)
Conventional Matrix Converter

Indirect Matrix Converter
(CMC)
(IMC)
Direct (3x3) - nine switch type
Many topologies with reduced
number of switches
Figure 19.15 AC-to-AC converter topologies.
Both Topologies are linked at different frequencies with two indepen-

dent, multi-phase voltage systems. CMC topology is chosen and analyzed
using different pulse width modulation methods (PWM) for changes
across topology [29].
The more important modulation and control approaches useful to MCs
are sketched in Figure 19.15.
With the advancement of the electronic power field, Pulse Width
Modulation (PWM) technique was developed which is the simplest and
easiest approach to MC modulation, space vector modulation (S.V.M.) and
direct torque control (D.T.C.) are the most effective, but not instinctive,
drive control methods in engineering [24, 33, 41].
Figure 19.16 displays the layout of the three critical circuits (i) power cir-
cuit functional matrix converter, (ii) Input Filter circuit and (iii) the clamp
circuit.
Nine bidirectional switches with 27 possible switching states are shown
in Figure 19.16. Nevertheless, because of the power circuit limitations of
the Equation, only 27 switching states were used.
Clamp circuit protects the switches from the surge coming from the
input AC line as well as from the surge on the output side that would be
otherwise produced whenever an emergency shut-down of the converter is
required. As a matter of fact, in the latter case, when the inductive currents
Power Circuit
LA SAa SAb SAc

VA CA
LB SBa SBb SBc

VB CB
SCa SCb SCc

VC LC
CC
Input Filter
Circuit
Va Vb Vc
LLa LLb LLc

Clamp Circuit
RLa RLb RLc
Figure 19.16 Structure of the conventional matrix converter.
of the motor are interrupted, the energy stored in the load is transferred
to the clamp capacitor and no critical overvoltage is caused if the capacitor
is large enough. Furthermore, the clamp circuit prevents output voltage
spikes caused during switches commutation by the parasitic inductance of
the power switch matrix and by the unavoidable timing inaccuracies.
“To reduce the harmonics in the system, the input filter is required, the
input filter of LA, LB, LC and CA, CB, CC sources shows in Figure 19.16.
During switches, an inductive power interruption causes high voltage
spikes through switches. “These high-voltage spikes damage the switches,
requiring an induction energy storage circuit shown in Figure 19.16”.
When there is turning OFF process initiation of converter then the induc-
tive energy is transferred from the load to the clamp condenser through
clamp circuit.
Figures 19.17 to 19.20 contains 4 quadrant bi-directional switches to
implement the matrix converter. Since there are no semiconductors capa-
ble of operating in 4 quadrants, two double-quadrant switches are used to
build a four-quadrant switch.
The main benefit of the diode-integrated switch is: its simple design as
compared to other two-directional systems. It has disadvantage too that
is its high conductivity loss. There are smaller losses than the integrated
diode switch in other configurations. The IGBT reverse blocking is often
not used as a bidirectional switch because I. G. B. T. has weak reverse
recovery functionalities that increase the loss of switching and reduce

overall performance.
For high-power applications, the transmitter is usually used.While
high-power applications do not prefer a small number of one-hour power
supplies to generate switching signals.
As shown in Equations (19.7 and 19.8), the limitations on the matrix
converter suggest, even during the switching cycle, that the output stage
of the matrix converter needs to contribute to a single input step. As there
is no intrinsic freewheeling direction for the matrix converter, it is much
easier to toggle their two-way switches than to switch to an inverter.
Figure 19.17 Diode-embedded switches.
Figure 19.18 Reverse blocking IGBT.

Figure 19.19 Common IGBT emitter.
Figure 19.20 Common IGBT collector.
There are various techniques available to convert matrix converters:
a) toggle dead-time
b) soft switch
c) multi-step power switch
d) multi-step voltage switch.
Using dead-time switching in matrix converters causes inductive cur-

rents instability because there is no freewheeling path. “In matrix convert-
ers, snubber circuits are required to provide an alternative path to inductive
currents, increasing the complexity and breadth of converters.”
Many converter topologies used soft switching techniques to reduce
switching losses [18]. “According to advances in technology and load
requirements there is requirement of introduction of soft switching tech-
niques in matrix converters which results in more number of converter
elements and also increases complexity. Some common commutation
methods are multi-stage and multi-stage voltage switches [46].
To test the sequence, this method depends on the load path. The incom-
ing BS is known as the bidirectional switch (BS), known as the outgoing
B. S. and the B. S. after the switch. Via BS, two switches, S+ and S-, show
the current flow path of the switch. All outgoing BS switches S+, S are
ON before the switching process begins. With this condition, the BS’ safe
sequence of switching is explained below to shift load from one process to
another as shown in Figure 19.21.
BS → S1
o o
S1+ S1- lL
LA
VA
CA
o o
S2 -
LB S2+
VB
CB
RL - Load
BS → S1
Figure 19.21 Direct matrix convertor block diagram.

Phase 1: The current direction is used when shifting to the incoming BS

to determine the outgoing non-conducting BS change. Then this switch is
turned off.
Phase 2: Incoming BS switch is turned on to run the current in the same
direction. The purpose is to create a load current direction to keep flowing
when the next B. S. switch is turned on or when the B. S. is switched off.
Phase 3: The outgoing BS conductive switch can now be safely turned on,
while the existing channel is now opened in a new direction as in Step 2.
Phase 4: The BS switch is finally switched on and the sequence of the switch
is ended.
For eg, “when iL >0, (i) Switch S1-is switched OFF, (ii) Switch S2 + is
switched ON, (iii) Switch S1 + is switched OFF, and (iv) Switch S2-it is
switched ON.”
ac
Source
Vs
Filter
Vi
SAa... SCc
Cost Matrix
Function Converter
Minimization
p
i o (k + 1)
io
Predictive
Model Vo
Ro
Load
Lo
Figure 19.22 Predictive current control strategy.

MPC is a comparatively a latest and modern control technique used

for power converters. This method uses controlled process computational
model to predict their behavior at k+1. A cost function is specified to select
the optimum power converter state. This feature has numerous restric-
tions and controls. This usually includes variations between averages and
expected values in controlled variables. Many other constituents of this
function indicate specific limitations, like frequency restriction or other
non-linearities [11, 15, 17, 48].
For example, DMC predictive current control (PCC) is implemented
here Figure 19.22 displays the PCC. The switching state range of the con-
verter is being displayed by this technique and at the end of each sampling
peiod it provides the value which is nearest to the reference value. A basic
and indicative load model can be explained as follows to predict future
currents:
di0 1 R
= vo − o io (19.17)
dt Lo Lo
The future load current is predicted by
T v (k + 1) + Loio (k)
io (k + 1) =s o (19.18)
Lo + RoTs
A cost function is used to find out the error between the current refer-
ences i0* and their respective predicted reference iop :
=g io(k + 1) + Aqs(k + 1)
g (k + 1) =ia* − iap + ib* − ibp + ic* − icp (19.19)
19.4 Topologies of Matrix Converters

and Use of Predictive Control
MCs have a number of topologies. The main differences are the number
of switches, specifications and operational constraints. The main benefits
of these extensions are: enhancing the control of voltage and increasing
harmonics, losses and different voltage mode. The DMC, shown in the
Figure 19.23, is the topology with predictive control that is most common
idc
Sr1 Sr3 Sr5 Si1 Si3 Si5
iA ia
iB ib
Vdc > 0
iC ic
Sr4 Sr6 Sr2 Si4 Si6 Si2
Figure 19.23 Common collector indirect matrix convertor (Source: https://ieeexplore.

ieee.org/document/6786857).
and used. The protected switching of nine switches and their very complex
modulation (total eighteen IGBTs) is one challenge for this converter. A
serious challenge encountered in the process of a DMC with predictive
control was also the high sampling rate, but the technological advances in
fast and powerful microcontrollers solved this issue.
This device along with control method was used for a variety of pur-
poses by several researchers.
To pick one that minimizes cost function, 27 different sample switching
states must be checked for this converter. One need to study the problem
of current control on the converter’s output side, especially for motor driv-
ing applications and grid interconnection. The DMC command provides
input current amplitude and phase control for system operation, capacitive
or inductive power factor. Another important issue for predictive control
research, given the DMC’s safe operation, is the reduction of input distor-
tion currents due to switching and several ac-supply disorders caused by
input filter resonances. Some researchers have been looking at converter
efficiency gains through increased switching losses and speed owing to the
great number of power semiconductors in DMC.
In all of our predictive control work, the most important contribution is
that DMC is easy to operate safely, avoiding the complicated transforma-
tions and modulations needed throughout PWM and SVM techniques and
using all available converter switching vectors that are not possible with
traditional techniques. Two single-stage MC (SPMCs), topological con-

trols for certain industrial applications, such as coal mining microwaves,
medical imaging, the television transmission and the resonant chain test,
the HF transformer and the DC input diode bridge [31, 32].
The next step is to implement the conventional (direct) matrix (CMC)
converter topology and assess changing conditions in the IMC-CMC ratio.
Three Stadium-ac chopper circuits are also known as Matrix Converters
(MCs) that define detailed MC topologies, including three forms of hybrid
MCs. This offers a common knowledge base for each topology of converters.
For high-power cascade installations connected to an AC source, a can
multi pulse transformer is proposed. Recent work on managing SPMC
has been published in order to investigate the possible application of con-
verters in grid communication systems involving media frequency trans-
formers for different grids. Predictive 3-to-5-leg DMC command, which
prevents the predictive load and source structure from complex modula-
tions and 3-dimensional transformations. The biggest challenge for predic-
tive control is the large number of switches that require consideration and
high computational costs (243 valid switching countries). The next step is
to implement the conventional (direct) matrix (CMC) converter topology
and assess changing conditions in the IMC-CMC ratio. Three Stadium-ac
chopper circuits are also known as Matrix Converters (MCs) that define
detailed MC topologies, including three forms of hybrid MCs. This offers a
common knowledge base for each topology of converters.
In comparison to the DMC, the IMC provides a simpler, so-called zero
dc-link current strategy for modulation and switching to help reduce
switching losses and thus increase converter performance.
The key challenge in input side variable operations in this topology
is maintaining positive dc-link voltages. For this converter, there are 72
appropriate switching states in each sampling cycle, nine per side of the
rectifier and eight per side of the inversor. Since at any point only pos-
itive dc-link voltage is available, only three appropriate corrector-side
switching statements are working at any time. It reduces the total number
of cost-effective countries to 24. The IMC’s predictive control of military,
aerospace and renewable energy drives is significant compared to DMC.
Resonance changes in the input filter as a result of AC origin disruptions
and switching toggles were considered. In where P-Q theory generates ref-
erence currents, A shunting active power filter IMC was recommended
which works under a predictive current control approach. One important
aspect was that the prediction controller reacted swiftly to nearly sinusoi-
dal current sources to reduce the effect of nonlinear load currents. Several
topologies with few switches and switching states for specific applications
are obtained from IMC. A sparse matrix (SMC) or ultra-sparse matrix

(USMC) converter or shift extension, such as the 4-and-6-legged and an
indirect hybrid matrix converter (HIMC) is used to control all of the topol-
ogies shown in Figure 19.23.
There are 12 IGBTs and 30 diodes used by SMC. This shift reduction
makes it similar to traditional IMC to a simpler topology. Again, high volt-
age generation within the dc connection while preserving sinusoidal cur-
rents and input power factor are the main tests for this harmless operation
of the converter. This converter needs to be given special attention because
it is important to synchronize rectifying switches and inverter switches like
the IMC. In the dc-link, the inverter must be changed on a free wheel to
zero.
In predictive technique, a fixed frequency vector pulse (SVPWM) var-
ies. In this particular application, the predictive controller only controls
the load current without the use of lined current controllers. Because the
predictive algorithm only regulates load currents, in the cost function only
8 true switching states are evaluated, so that the optimally chosen switching
vector produces the modulator reference voltage. The PWM code ensures
input side operation of the system power factor and the voltage relation-
ship is established by the predictive controller.
The main difference between this new topology and the old USMC is the
two-way design transition that enables energy transfer from the DC-Link
and vice versa. Through regulating fuel flow, the researchers used predic-
tive control to regulate the micro-turbine grid’s electrical power and were
highly effective for both small steps and enormous casual changes. A 4-leg
indirect matrix converter (4L-IMC) has been introduced as a predictive
control. The control objectives are to monitor load current and to mini-
mize instant input or voltage control with a LC filter output side. As with
the topologies of the previously studied indirect matrix converters, it is
necessary to toggle both rectification and inverter phases. In addition, the
wide variety of IGBTs and therefore the large number of switching states
make it difficult to monitor this converter and require very complex and
intuitive 3D modulation techniques. Simplicity and intuitive explanation
are important aspects of predictive control, so that the topologies of those
power converters can be controlled easily. As shown in these papers, with
all control targets integrated into one cost factor, the predictive strategy
works well in constant and transient states, using only the converter and
load mathematical model.
For multi-driving predictive control two induction machines fed by six-
leg IMC were suggested. For today’s air, exploration and military applica-
tions, multi-drive systems are useful. These systems typically have equal
load numbers (usually Ac engines), but recent multi-phase matrix conver-

sions have been introduced to multiple induction machines that reduce
weight and size of a multi-drive system with a single converter [9, 27].
Multi-phase matrix converters’ main challenge is to increase the avail-
able switching conditions that can be applied to the converter, taking into
account the optimization algorithm’s sampling time. However, ensuring
the converter’s synchronization is correct is also very important. We know
that predictive controls require a high sampling frequency. Nonetheless,
the sampling rate that aggravates the control behavior must be reduced
to determine all appropriate switching conditions during each sampling
period. Some recent studies find multiple redundancies in developing and
changing states to reduce the number of countries evaluated to address
these issues.
The viability of the application of this control strategy has been shown
to achieve operational management of both IMs at the same frequency, but
at different load torque. Recent IMC based topology work often revisits the
legal status of the rectifier side, either by reducing the total number of valid
switching states assessed for the cost feature to two thirds or by allowing
a maximum dc-link voltage at any particular time. The MC offers a range
of advantages in size and weight for working sinusoidal origin and load
currents, regeneration, etc. as defined by this document.
A hybrid power converter was proposed to solve this problem, which
links an supporting voltage source into the DC-Link of the IMC, and pro-
vides unit voltage transmission capabilities with significant voltage distor-
tions as illustrated in Figure. 19.24. “The main encounters in this topology
were to control the entry side, to turn on the corrective side, to control the
auxiliary circuit connected to the dc connection, and to control the output
side of the converter.”
This method proposes a PCC approach to connect the auxiliary voltage
source to a linear PI controller, which generates the pulses pulse width
duty cycle. This predictive controller and the model suggested provide sta-
ble power for the converter and unit voltage.
Ultimately, predictive control in all previous cases established excellent
performance as it was a very modest method of application. Predictable
controls have been applied in numerous MC topologies to tackle the dis-
comfort of the MC system by 2 stage DC-Link Back-to-Back (V-BBC)
transformers, demonstrate a highly versatile and useful technology and
release a promising new solution for electrical conversion models of low
voltage and low-powered (100 kW).
The new method takes account of the distinct and non-linear design of
power converters and drives and is aimed at having a significant effect in
ir ii
Sх4
Sr1 Sr3 Sr5
Si1 Si3 Si5
iA ia
Sх3
iB ib
Vi
Vr Sх2
iC LхRх ic
D5
Sr4 Sr6 Sr2
Sх1 Cх
Si4 Si6 Si2
Figure 19.24 Hybrid indirect matrix convertor.
the near future on power control. The digital signal processor technologies
available can easily implement these methods.
This chapter shows that power generated through wind turbine is
efficiently transferred to the grid side by using AC-AC transmission by
the use of direct matrix converter consisting of I.G.B.T switches. A 3x3
matrix is taken in which there are 9 bidirectional switches which have 27
switching states. To control the operation of these switches i.e. opening
and closing time of switches various control and modulation techniques
are there. The researcher has used predictive current control technique
out of all the techniques as it is simple and uses cost function to deter-
mine the future value of current. The mathematical modelling of the
above said technique suggest that it is much simpler, less complex, less
use of filters, high sampling frequency, high switching frequency, very
nice dynamic response.
19.5 Conclusion
In the last four decades numerous studies have been carried out to provide
clean and green energy source in order to protect natural resources that are
non-renewable in nature. Wind energy emerged as one of the alternatives
as it is considered environment friendly and cost effective. The wind energy

gained popularity due to advancement in design of generators and power
electronics technology.
In this study for wind speed of less than 6.5m/s variable speed wind tur-
bines DFIG was used instead of PMSG. DFIG handled larger range of wind
speeds and had less Third harmonic distortion (THD). The fault clearing
time of DFIG was also less as compared to PMSG.
Matrix Converter was used to achieve minimum transmission losses,
unity power factor, instead of using VSC Back to back converter. To control
the opening and closing of power electronics converters model predictive
control technique was used.
A major contribution to the research is that all 27 possible switching sta-
tus is used in each of the sample periods for the estimation of the expected
load and input current values, enabling the assessment of feature g. After
that, for the next modulation cycle the appropriate switching status pro-
ducing the minimum g value is chosen. The introduction of cost function
g also helps to control the input and output (source and load) currents with
waveforms at the same time [10, 44, 47, 49].
Predictive control strategy allows the reactive power flowing from the
rotor to the grid to be minimized. That can be achieved by increasing the
value of the weighting factor A = 1. This new control strategy virtually
eliminates the input filter resonance.
The integration of DFIG with Predictive Current control technique for
generation and transmission of power from generation side to grid side is
better option as it improves overall performance of the system.
19.6 Scope for Future Work

Wind Energy is fast evolving as an alternative form of energy as it can
produce clean and affordable power. As there are advancement in tech-
nology in the field of power electronics there are various new technol-
ogies that are evolving which can play a big role in replacing existing
technologies to have better, cheap and efficient performance of the
system.
There are generators which can efficiently generate power using wind
turbine apart from DFIG Permanent Magnet Synchronous Generator
(PMSG) is also evolving as an alternative power generating source with
advanced performance aspects especially in On shore applications.
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Part III
TRENDS IN CONTROL METHODS
20
Microgrid: Recent Trends and Control
S. Monesha* and S. Ganesh Kumar
DEEE, CEG Campus, Anna University, Chennai, Tamil Nadu, India
Abstract
Electric energy demand has increased in recent years, implying a rise in electricity
output. Distributed Generation (DG) is gaining popularity due to its high reliabil-
ity, power quality, performance, decreased emissions, increased protection, and
effective load management. The microgrid concept is gaining interest as a more
straightforward way to utilise the benefits and possibilities of distributed gener-
ation. Microgrids connect Distributed Energy Resources (DERs) to the electri-
cal grid and energy storage. This is the Smart Grid of the future, which serves as
a central electricity provider while lowering energy expenditures. As a result, in
order to improve performance, energy consumption must be reduced by prop-
erly utilising available resources, lowering total expenses. This chapter covers a
variety of microgrid topics. To maximise the electricity shared with the grid pro-
file, an energy management plan must be developed. The modern approach to
resource management must be strengthened and redesigned. The various microg-
rid structures are detailed, including AC, DC, Hybrid, Urban DC, and Ceiling DC
Microgrids. Many forms of microgrid control mechanisms are briefly explained.
This chapter also discusses energy management strategies, microgrid innova-
tions, and microgrid difficulties. Microgrid systems’ benefits, drawbacks, and
various uses are depicted using interactive figures. Different control systems are
also addressed in order to monitor various factors including voltage, current, and
power. In addition, IEEE and IEC standards are covered, which aid in the imple-
mentation of a faultless microgrid system.
Keywords: Distributed energy resources, distributed generation, energy

management, energy storage, microgrid, standards
597
20.1 Introduction
Renewable resources reduce environmental impact. This increases the pen-
etration of the Distributed Generator (DG) into the grid. It discusses the
issues of the sustainability of energy, greenhouse gas emissions, energy effi-
ciency, etc. The integration, control, and scheduling of Distributed Energy
Resources (DERs) have been investigated under grid-connected mode and
stand-alone mode of operation in [1–6]. Integration of DG is a challenging
factor that creates attraction in the field of Microgrid (MG). MG architec-
ture is discussed in [1, 7, 8]. MG architecture, challenges, and issues are
clearly explained in [6]. The AC and DC technologies in MG are deeply
discussed in [9]. Further, challenges in using DC power are addressed in
[10]. In 2017, a modified particle swarm optimization method was used in
the real microgrid of the Federal University of Pariba [11]. The evolution of
MG testbeds around the world are reviewed in [12–14]. Similarly, several
projects are carried out around the world on the design, control, manage-
ment, and operation of MGs.
The objectives of an energy management system (EMS) in an MG are
to minimize maintenance operating and fuel costs. To regulate the volt-
age and frequency of the device, energy management is important. Energy
management systems are the essential control of monitoring for the proper
functioning of MG.
The operation and control of the MG is challenging. The great challenges
of the MG are its control and protection. Various control strategies for an
islanded mode operation of MG have been investigated in [15]. Different
control strategies and control algorithms for the stable operation of MG
are discussed in [16–18]. An improved control strategy for energy man-
agement with energy storage and PV active power control are discussed in
[19]. An overview of control strategies is discussed in [20–22].
A review of inverter-based MG control is done in [23–25]. The modeling
and classification of control strategies are discussed in [26–34]. The advanced
control architectures and algorithms for intelligent MGs and integrated
scheduling are discussed in [35–37]. The different types of control methods
like droop control [38], direct Lyapunov control [39], model predictive con-
trol [40], potential-function based control [41], and passivity-based control
[42–48] are discussed. A communication study between DG units is given in
[49]. Making the entire smart grid system automated with wireless commu-
nication is presented in [50]. The possibilities of using particle swarm opti-
mization for MG performance improvement are given in [51]. This chapter
presents the study of different methodologies of MG EMS and control. This
study was done with the latest literature in comparison with [1].
Microgrid: Recent Trends and Control 599
This chapter is organized as follows. The microgrid concept and classi-

fication are explained in Section 20.1. This section provides an overview of
the basic concepts and different structures of the microgrid. The microgrid
control layer is discussed in Section 20.2. This section provides an out-
line of the microgrid control layer. Functional requirements of microgrid
energy management and different microgrid energy management controls
are given in Section 20.3. This section deals with the design issues of the
Energy Management System and the different types of microgrid energy
management control. Interfacing converter control methods are explained
in Section 20.4. The interfacing converter of the microgrid’s main draw-
back is predicting the availability of renewable energy sources and some
of the energy storage systems are discussed. Interfacing converter control
techniques are given in Section 20.5. This section provides an overview of
the different DG interfacing converter topologies. IEEE and IEC standards
are explained in Section 20.6. Challenges and future trends are explained
in Section 20.7. This section discusses the various challenges of microgrid
control and future trends in microgrid.
20.2 MG Concept
MGs are defined as the integrated DERs and energy storage systems (ESS)
which create a grid that feeds different distributed loads on a low voltage
network that can operate either in grid-connected mode or in stand-alone
mode [6, 8, 20, 21]. The basic MG architecture is shown in Figure 20.1. It
comprises of two DG sources, an energy storage system, both AC and DC
loads and a Plug-in Hybrid Electric Vehicle (PHEV).
The MG has two buses:
• DC bus in which the DG sources, storage device, and the

DC loads are connected.
• AC bus in which the AC loads and the utility grid are
connected.
The following are other infrastructures required by the MG:
• Renewable energy sources/diesel generators

• Power Conversion Systems
• Distribution Lines
• Monitoring devices and instruments
• Proper controller under different modes of operation
Grid
Wind
Turbine
Energy
AC PV Storage
Loads
DC DC Plug in
Loads Loads Vehicle
Figure 20.1 Basic MG architecture [2].
MG must be protected from circuit faults like short circuit currents and
excessively high or low voltage due to abnormal conditions. For proper
protection, protective relays must be installed for detecting the abnormal
conditions and circuit breakers must be initiated to isolate the portion in
which the fault has occurred.
20.2.1 Different Structures of MG

MG may be categorized as DC MG, AC MG, Hybrid MG, Urban DC MG,
or Ceiling MG depending on the DG units and the loads connected.
20.2.1.1 AC MG
In AC MG, local loads may use power or excess power can be pumped into
the grid [6, 9, 37]. AC MG’s primary advantage is the use of transformers.
Synchronization is necessary for the proper operation of the MG. AC MG

is used for applications requiring high energy.
The most popular and widely used structure for microgrid studies and
implementations is AC distribution. Generation, delivery, and loads are
in AC form within this architecture. The distributed sources and energy
storage devices are interconnected through inverters with the AC distri-
bution. Through using the current infrastructure of the AC network, it is
simpler to build and execute AC MGs. They are also based on technology
that is tested and reliable. Based on this definition, various microgrid proj-
ects have been developed worldwide. The microgrid based Consortium for
Electric Reliability Technology Solutions (CERTS) was first conceived in
1998 as a micro-generator and storage cluster with the capacity to smoothly
detach and isolate itself from the utility with little or no-load disruption.
20.2.1.2 DC MG
In comparison with AC, DC MG produces low energy loss and MG shows
the structure of MG that operates at different DC voltages and a typical
DC bus voltage. Because there is no reactive power, it is only necessary to
regulate the voltage amplitude to link the DC sources to the DC bus and
the operation of the control becomes simple. DG MG prevents conversions
to AC-DC. For the DC voltages and the security devices for efficient oper-
ation, proper operating ranges are necessary. With the aid of the voltage
regulator, utilization can be easily carried out. It is used for applications
with low voltage levels.
The key benefits of the use of DC MG are the following [6]:
• The absence of synchronization of phase and frequency.

• Reduced conversion stages of electricity.
• It can be used directly for DC loads and AC loads with the
conversion.
• The compactness of the DC bus structure improves the
efficiency of plug-in hybrid electric vehicles and electric
vehicles.
By reducing energy conversion stages for DC-based generations and

energy storage components, DC delivery provides performance enhance-
ment. Furthermore, in a DC distribution system, there are less stability
problems and voltage control is less complex. Additionally, because con-
verters are used for generations and loads, the architecture allows for wider
voltage variations. Synchronization and reactive regulation of power are

not required. The need for AC/DC conversion for AC sources and at the
connection point to the grid is one major drawback of this method. Other
problems include the safety of over-current and short-circuits and the need
for new DC distribution lines. Where the predominant loads in the system
are in DC, the DC principle is more advantageous.
20.2.1.3 Hybrid AC/DC MG

This MG is a mixture of AC MG and DC MG. The AC MG is directly con-
nected to the utility grid and the DC MG is connected through an inter-
connecting converter, considering the power flow, various types of loads,
reliability and cost, and the design of this type of grid [26, 31, 50]. Higher
reliability, performance, and versatility are achieved due to the advance-
ment of electronic power devices and their controllers.
A fully integrated and reconfigurable MG testbed of hybrid energy sour
ces spread is the Tianjin University MG Testbed (TUMT). Compensation,
topology, and equipment used by the TUMT are discussed in [14].
To maximize performance, hybrid microgrids try to use the advantages
of both AC and DC principles. With specific generations and loads, they
have both AC and DC parts. To prevent conversion loss, energy transfer
between AC and DC parts is minimized. The interconnecting converters
are used to provide all parts with active power support and the AC system
with reactive power support.
20.2.1.4 Urban DC MG
Urban DC MG is located in urban buildings that functions both as produc-
ers and consumers [52]. Using an adaptive controller, various Urban DC
MG parameters are controlled and different MG modes can be easily han-
dled by this controller via static switches. Also, this controller optimizes
the penetration of the new generating sources distributed.
20.2.1.5 Ceiling DC MG
Due to the direct use of DC from rooftop PV panels without multiple
conversions, Ceiling DC MG is common. The external proportional-
integral controller is used in [53] to regulate the DC voltage, while
the internal three hysteresis controllers are used to force the input
current to be in phase with input voltage and thus, to increase the
power factor.
20.3 MG Control Layer

There are three control layers for the entire control operation of the MG
[6, 21, 25, 26]. The general structure of the MG control system is explained
as follows:
• Primary Control (Field Level): It is the lower level and it con-

tains the local controller. It is responsible for the control
of DERs, local load, and the storage systems using power
converters in different modes. The key points associated
with this control are the sharing of load between convert-
ers, improving device efficiency and stability, and regulating
output frequency and voltage magnitude and often uses the
droop control method. To provide proper output imped-
ance, it may also provide a virtual impedance control loop.
To perform droop-control system calculations, it only uses
local output voltage and current.
• Secondary Control (Management Level): It is the MG cen-
tral control. Its main function is frequency and voltage res-
toration, synchronism between the microgrid and the grid
when it changes from islanded mode to grid-connected
mode, and load shedding and optimization of the produc-
tion of the microgrid. It is also used for power quality control,
voltage unbalance, and harmonic compensation. It removes
any steady-state error caused by droop control, makes use of
communication with low bandwidth, and has more global
duties. To conduct droop-control system calculations, it uses
only local output voltage and local output current.
• Tertiary Control (Grid Level): The buying and selling of
energy between consumers are facilitated in this upper
management area. Intelligence for the whole system intro-
duced in this level is optimized. A market operator (MO) is
incorporated in the distribution network operator (DNO)
control which is situated in the main grid. It is responsi-
ble for economic-emission reliability dispatch. As the MG
links with the utility grid, this degree often comes into play.
The key points of this control are that it controls the trans-
fer of energy between MG and the power grid, sends refer-
ences to the secondary control frequency and voltage, may
detect islanding or minimize harmonic voltage, and can also
enhance PCC power quality.
20.4 Functional Requirements of MG Management

The design issues of the EMS are discussed in this section. EMS is used for
emerging MGs. They are functional requirements and engineering chal-
lenges [54]. An MG EMS is used for optimal operation by monitoring and
controlling the DERs and the load. The utility information and weather fore-
cast are collected when they interact with various DERs, loads, and external
systems. The following factors are the functional requirements of EMS:
20.4.1 Forecast
Forecasting is a challenging requirement in an MG setting due to the
inherent intermittency and variability of DER and the uncertainty in
controllable loads. The historical data and other inputs are used by the
EMS to forecast the DERs, the loads, and the market on different time
scales. These data are used as the input for optimization. Weather fore-
casting and renewable energy forecasting must be done. This forecast is
used as the input for real-time optimization. As the generation, storage,
and consumption of energy in a microgrid becomes more dynamic and
complex, for energy balance it is important to accurately predict such
activities. Forecasting is carried out on various time scales (e.g., hour-
ahead, day-ahead, etc.) and expected data is fed into a microgrid opera-
tions optimization process.
20.4.2 Real-Time Optimization

Real-time Optimization is the brain of the EMS. It ensures continu-
ity of the load supply and decreases the overall cost of energy produc-
tion. To optimize power flows, an EMS must be able to make control
decisions by changing the imported/exported power from/to the grid,
the controllable loads, and the dispatchable DERs. Different optimiza-
tion techniques are followed for different applications which are typ-
ically formulated as non-linear optimization problems with different
objectives. Extensive algorithms are proposed for various functions
like energy management, DR (Demand Response), coordinated EV
charging, and V2G in MGs.
20.4.3 Data Analysis and Communication

The data of the DERs, loads, and market are used for analyzing EMS. The
data analysis provides a better understanding of the characteristics of the
DERs, the loads, and the market. This can be utilized for adjusting the fore-
cast and the optimization models for better performance and are also used
for designing control policies for new applications.
20.4.4 Human Machine Interface

Further, the MG operator interacts with the other modules in the EMS
using the Human Machine Interface (HMI). The unified communication
interface is used by the system to manage the devices without the knowl-
edge of protocols and technologies used for achieving interoperability and
extensibility. An MG consists of heterogeneous types of energy resources.
The EMS interaction must be in an interoperable manner for interoperat-
ing with the external systems outside the MG. The information delivered
from the external system must be translated to the internal semantics and
protocols using EMS.
The communication interface must be extensible for supporting the
energizing functionalities. In [52], advanced metering infrastructure is
designed for improving the speed of the messages.
20.5 Energy Management Schemes

In both the grid-connected mode and islanded mode, EMSs are very
important for the proper operation of MG. These EMS define each DG
source’s output powers and/or output voltages that are then fed as refer-
ences for control monitoring to the interface converter control system.
They are generally regarded as systems that are communication-based and
communication-less [27, 29].
20.5.1 Communication-Based Energy Management

Device information is transmitted in this scheme to assess the operational
point of each DG in the MG. In order to assess the output power of each
DG, these schemes take full advantage of intelligence in the application of
computer and communication technologies. When taking into account the
distances from power sources, the degree of power protection, expense,
and accessible technology, the best contact approach is used such as
fiber-optics, microwave, infrared, PLC, and/or wireless radio networks. In
these systems, the fusion of Internet Protocol (IP) with existing industry
protocols and grid connectivity standards is used. It is classified into cen-
tralized and decentralized systems for energy management.
(i) Centralized Energy Management System

This scheme is a supervisory EMS. In this scheme, the decisions are made
by one control center to determine the operating points of DGs. It is shown
in Figure 20.2. The measured signals are received and the operating points
of DGs are set based on the objectives and constraints for minimizing the
system service, cost of maintenance, effects on the environment, and max-
imization of system effectiveness, etc.
Objective functions of this kind and constraints will clash and it is often
difficult to solve these problems. The local control of the DG is realized
primarily by regulating the power electronics converters of the DG.
After making decisions, the DG control systems send control signals
that the calculated microgrid data transmit to the central computer and
the center controller’s objective function is to ensure high load power
efficiency. The value of this unified control scheme is that all unit data is
Main
Grid
Loads
PCC
DG source 1 DG source 2 DG source n
Control and
Energy Power Power Power
Management Controller Controller Controller
System
Energy Management Supervision
Loads Loads Loads
Figure 20.2 Centralized energy management system [2].

gathered by the central system and therefore, the multi-objective energy

management system can achieve global optimization based on the avai-
lable details. The main drawbacks of this scheme are heavy computation
burden and communication failure which may collapse the system.
(ii) Decentralized Energy Management System (DEMS)

Via a communication bus, all the controllers are linked and data among the
DG controllers are exchanged using this bus in the system. All the loads are
also connected with all the local controllers. This EMS is shown in Figure 20.3.
Every local control system knows the operating points of other convert-
ers in this scheme. The operating points of DG are determined using this
information [35]. Intelligent algorithms have also been used in these sys-
tems to find the optimum operating point. The advantage of this scheme
over the above scheme is it is easy to expand the control system to newly
Main
Grid
Loads
PCC
DG Unit 1 DG Unit 2 DG Unit n
Power Power Power

Controller Controller Controller
Control and Energy Management System
Loads Loads Loads
Figure 20.3 Decentralized energy management system [2].

installed power sources with a plug-and-play feature. The necessity for

computing is lowered. Furthermore, the system’s redundancy and mod-
ularity are strengthened. Malfunction of the communication connection,
however, can still cause device problems. Also, this approach is still con-
cerned with the possible difficulty of its communication system.
For large and complex microgrids, these methods are also used and
techniques based on artificial intelligence such as fuzzy systems and neural
networks that are used to evaluate the operating point of each DG while
improving the overall microgrid performance.
A mixture of the above two schemes would create a hybrid centralized
and decentralized scheme. DGs are split into categories in this hybrid
approach. A unified scheme is used in each group and is responsible for
local optimization within the group. DEMS are used for global optimi-
zation by various classes. Such a hybrid approach could be ideal for large
integrated microgrid networks where centralized management of each
microgrid and decentralized microgrid communication could boost the
system’s efficiency and durability. A mixed centralized and decentralized
energy management system can be used as the newly introduced hierar-
chical energy management scheme.
20.5.2 The Communication-Less Energy Management System

Any DG device needs to be able to work independently when connectivity
is too complicated or expensive. Without communication connections with
the other controllers, each energy supply has its own controller, as shown
in Figure 20.4. The advantages are there is no communication requirement
and the control system is expandable and more flexible for both linear and
non-linear loads with different control frequencies.
There are some possible complications however. First, nonlinear loads
are not considered in this process, and nonlinear current sharing between
DG units cannot be explicitly addressed. Besides, the high R/X line imped-
ance ratio can lead to problems with real and reactive power coupling and
stability in low voltage microgrid systems. Also, mismatched DG perfor-
mance can create an error in power-sharing. However, with the commu-
nication-less based control approach, optimum operation of the microgrid
device is still difficult without a central control/optimization algorithm.
Energy Storage System for MG

It is well known that different types of DGs and customers build and demand
varying active and reactive power profiles within an implemented microg-
rid that may challenge the system’s stability. Thus, energy storage systems
Main
Grid
Loads
PCC
DG Unit 1 DG Unit 2 DG Unit n
Control and
Energy
Power Power Power Management
Controller Controller Controller System
Loads Loads Loads
Figure 20.4 Communication-less energy management scheme [2].
play a critical role in stabilizing microgrid voltage and frequency for both
short-term and long-term applications. For small-scale applications, e.g.,
renewable energy ramp-rate management, energy storage units may either
be dispersed or centralized as utility-scale applications, e.g., utility frequency
control. In addition to effectively managing and monitoring the functions of
the storage devices to provide local loads with power support, the distributed
energy storage system often seeks to optimize its life, performance, and pro-
tection. To perform other advanced activities, it also communicates to the
upper layer control unit, such as the supervisory control unit.
In a microgrid, where vital facilities are involved, a centralized energy
storage system is usually observed. In the event of a bulk grid black-out,
it normally works similarly to the main back-up power source. To sustain
the entire system from a few minutes to hours, a higher energy and power
level is required.
Currently, energy storage is a tradeoff between power and energy den-
sity. Although ultracapacitors and hybrid batteries offer higher power den-
sity, their capacity (in Ah) and energy density are nowhere close to those
of batteries. They can release a large amount of power but only for a few
Table 20.1 Energy storage systems.

Type of energy storage Examples
Electrochemical • Secondary batteries (NiCd, lead-acid, NaS, etc.)
• Super capacitors
• Flow batteries (hybrid flow, redox flow)
Mechanical • Flywheel
• Compressed air
• Pumped Hydro
Electrical • Super conducting Magnetic Energy Storage
Chemical • Fuel cell
Thermal systems • Heat Storage
Table 20.2 Types of energy storage systems.

Energy to
power Discharge time
Type ratio specification Examples
Quick <1 Seconds to • Flywheels
Discharge Minutes • Capacitor banks
Time • Superconducting
magnetic energy
storage
Moderate Between 1 Minutes to • Sodium-sulfur (NaS)
Discharge and 10 Hours batteries
Time • Lead-acid batteries
• FlyWheel energy
storage
• Lithium-ion batteries
High Discharge >10 Days to Months • Redox batteries
Time • Synthetic natural gas
• Hydrogen (H2)
• Pumped hydro
storage
seconds. On the other hand, fuel cells are capable of storing a vast amount
of energy but are limited in the peak output power. Based on the avail-
able technologies, batteries are the best choice to provide both power and
energy densities. There are several types of batteries currently in use for
industrial applications. Among all of the different types of energy storage
currently available commercially, Li-ion batteries offer the best solution for
high-power and high-energy applications.
Predicting the availability of renewable energy sources is the key down-
side of MG. For instance, both at night and on a cloudy day one should
not expect solar power. Therefore, in MG [19, 31, 37, 55], energy storage
becomes critical. The efficiency of MG service is improved by integrating
energy storage systems. Some of the storage systems for energy are listed
in Table 20.1.
Energy storage systems can be categorized based on energy discharge
times [37] and are listed in Table 20.2.
20.6 Overview of MG Control

The MG control strategies are aimed to achieve efficient and stable opera-
tion during grid-connected and islanded modes. Single-phase energy con-
version in DG with suitable control configuration makes the entire system
more flexible to operate in an islanding mode. The modes of operation and
the type of load (linear or non-linear) play a vital role in the designing of a
controller which makes MG operate either in an islanding mode or normal
mode. This section discusses the different types of control paradigms.
20.6.1 Power Flow Control by Current Regulation

In a closed-loop manner, all active and reactive powers are tracked. The
true power control loop generates the synchronous frame’s d-axis refer-
ence current and the q-axis reference current is generated during the reac-
tive power control loop. Note that an energy saving scheme might be the
real power link or an MPPT system. The DG output current can then be
regulated with these reference currents in the synchronous frame or the
stationary ab-frame [30]. The Phase-locked-loop (PLL) grid voltage angle
information is used in this control technique to synchronize the output
current of the inverter with the grid voltage.
DC link voltage control can also be used to produce the d-axis reference
current. In other words, the real output power of the inverter is controlled
to control the voltage of the DC link where the energy difference between
the input phase and the output of the inverter may be used to charge the
DC link capacitor or discharge it.
The CCM-based power flow regulation solution is usually used in
grid-connected operating mode where the frequency and voltage of the
AC bus are regulated by the grid. However, in the stand-alone application
of a microgrid, the CCM-based approach does not specifically regulate the
microgrid voltage and frequency, so the VCM control technique for at least
one or more large DG units require microgrid energy storage units.
20.6.2 Power Flow Control by Voltage Regulation

In this control technique, to control the output power of the DG, the out-
put voltage of the DG is controlled and the DG acts like a synchronous
generator. The real power flow is regulated using the voltage phase angle
(δ). The reactive power flow can be regulated by Vl─Vg, where Vl is the
DG voltage, Vg is the point of common coupling (PCC) voltage, and δ is
the phase angle difference between Vl and Vg. Integral control is included
in the reactive power controller to improve the accuracy of the reactive
power control [34]. This voltage regulation is more sensitive than the cur-
rent regulation.
This control system can be applied to microgrids in both grid-connected
and stand-alone operating modes. The references to active and reactive
power are given by techniques for power management. In this technique,
the phase angle of the output voltage is determined by the active power
control and the reactive power controller regulates the amplitude of the
output voltage. Three-phase DG output voltages are regulated based on
their reference values using a closed-loop control framework. The voltage
closed-loop control device will provide an internal current loop for the
benefit of transient output and stability in this method. For the realization
of active power-frequency drop and reactive power-voltage magnitude
drop in this controller unit, proportional controllers may be real and reac-
tive power controllers.
Compared to CCM-based control, the main advantage of VCM-based
control is that it can be used in both grid-connected and stand-alone oper-
ating modes, which makes the transition to operation mode fast and seam-
less. Potential issues are mainly related to the lack of direct control of the
DG output current when this device is used, especially during a fault or
disruption of the grid voltage. Applying virtual impedance regulation at
the DG output will prevent these problems. The line impedance between
the DG and the PCC is more vulnerable to power control through voltage
regulation than current regulation.
20.6.3 Agent-Based Control

MG agents were developed using the Java Agent Development Framework
(JADE) and it has several functionalities. The MGCC includes a pull-
ing agent, curtailment agent, database agent, shifting agent, and control
agent. The micro source controller includes a bid agent, generator agent,
and schedule agent. The load controller (LC) includes a switch agent, load
agent, and status agent which are present in the MG agent platform. It inte-
grates several functionalities and is adaptable to the complex microgrid.
It integrates multiple agents in an environment that communicates
with each other. Agents are organizations that have their own agendas,
communication skills, and a certain degree of autonomy. For power sys-
tems, the agent-based method is ideal, where the necessary information
is often accessible locally and several interacting agents are involved. The
agent-based framework can be used for the monitoring and management
of microgrids [34]. Agent-based techniques have become common, in
which intelligent agents use peer-to-peer communication methods to try
to achieve a goal using neighbouring data.
20.6.4 Multi-Agent System (MAS) Based Distributed Control

In this type of control, utilization of MAS technology is done. A fully
decentralized approach is adopted using three distinguished control levels.
Autonomous computational agents make decisions within an environment
based on objectives and transmit knowledge to other autonomous agents
about their objective achievement.
The medium voltage level of the Distribution Network Operator (DNO)
and Market Operator (MO) is not a microgrid operator. DNO applies to
the system’s operating roles and is accountable for the technical operation
of one or more microgrids, whereas the market functions of the area are
the responsibility of one or more MOs.
The main interface between DNO/MO and the microgrid is the
Microgrid Central Controller (MGCC). Its primary purpose is to optimize
and organize local controllers with microgrid operations.
The DG, manufacturing, distribution, and some local loads are con-
trolled at the lower level by Load Controllers (LC) [34].
The system model is obtained in detail using MAS technology and each
agent uses the exact piece of information he wants, leaving the techni-
cal specifics in the organizational map for the agents below. This control
requires three forms of agents. A control agent that directly controls the
system’s physical units, a management agent who handles and makes the
choices of the microgrid, and an ancillary agent that performs tasks such
as data communication and storage.
20.6.5 PQ Control
It provides the optimal power factor with active and reactive power. The
reference values for the power are specified by the LC or MGCC and this
control scheme can be implemented as a voltage-controlled source of cur-
rent or a current-controlled source of voltage [34]. Direct (Id or Vd) and
quadrature (Iq or Vq) current or voltage components with inverter ter-
minal voltage are calculated on a method-based basis. For controlling the
active power, the direct current component (Id) is used and the quadra-
ture component (Iq) is used to control the reactive power. The output
power is controlled by changing the firing angle to a suitable level. Park’s
Transformation is used for SPWM control in the overall operation, which
is a closed loop control system. This type of control scheme is appropriate
for distributed sources with inverters.
20.6.6 VSI Control

The inverter is controlled to feed the load with predefined values of volt-
age and frequency. In this control, the inverter emulates the behaviour of
the synchronous machine [34]. It is also possible to incorporate the same
scheme for frequency control in smart micro-grids. Voltage is linked to
reactive power (V − Q) in VSI control, while frequency/phase shift is
linked to active power (f − P). The active power droops determine the out-
put voltage frequency ‘f ’ and the reactive power droops determine the volt-
age magnitude. The output voltage is the reference signal that regulates the
switching sequence of the VSI. The important thing to note here is that VSI
uses local measurements at its terminals and responds easily to any device
disruptions, so it does not need any connectivity facilities. However, for
optimum management, there would be a communication infrastructure
within the DG.
20.6.7 Central Control

With the available communication information, monitoring and control
of the whole MG was achieved. To ensure the accuracy between the syn-
chronizing signal and the output voltage frequency, this control uses a
Phase-locked Loop (PLL) circuit. The current reference for each module
is specified by the modules currently shared. This is highly dependent on
coordination and a centralized controller, which decreases the system’s

reliability. The calculated data of all DG units is obtained by a centralized
controller based on which the control variable of each unit is controlled
[56]. The use of simple control methods in the power converters is one of
the benefits of this approach. However, the most important disadvantage
of this approach is the high cost of building communication infrastructure.
Furthermore, when supervising the system command and communication
lines, one monitoring unit should be considered. As a result, when this
procedure is used in heavily distributed or large systems, it causes issues
with system design.
20.6.8 Master/Slave Control

Initially, an automatic program setting or mode selection switch is used to
start the parallel-connected module, which lets the inverter act as the mas-
ter, and is used to determine the current reference and control the output
voltage. A fair distribution of the current is done by the slave units that
track the current relation from the master power, but the whole system will
malfunction when the master unit fails. Without PLL using this control
[56], better power-sharing can be achieved.
There is one master controller in this control approach and others serve
as slave controllers which operate via a communication connection on the
instructions given by the master controller. There is no need for frequency
control in the grid-connected mode and only microgrid PQ control is
used. In island mode, along with power balance, the master controller
maintains the system’s voltage and frequency. If the master controller uses
voltage-frequency control, it can be divided into two groups, i.e., single
master and multi-master controls (with only one large capacity micro-
source). If an effective step master control micro source utilizes V/f control
in multi-master control, then the output of the previous step master con-
trol micro source uses P-Q control. This technique has a major drawback
in that it is reliant on a high-bandwidth communication link.
20.6.9 Distributed Control

Each inverter has an individual control circuit in this control and there is
no need for a central controller. There is a need for an additional loop for
current control given by the current shared bus to track the same average
reference current. It can be quickly disabled if there is a malfunction in
either module and the rest of the units can normally be run in parallel
[56]. Distributed controls assign monitoring tasks and their interaction to
various DGs. These control tasks are based on various time frame opera-
tions and constitute a hierarchy of controls. In a network, distributed con-
trol is difficult as the number of units increases, unless a control hierarchy
is defined. The distributed approaches seek to solve the underlying problem
of optimization in a distributed way with minimal communication. Recent
interest in distributed control strategy research demonstrates microgrid
island operation and control while maintaining privacy and shielding the
infrastructure from cyberattacks.
20.6.10 Droop Control

The synchronous generator operation is emulated by this method where
with the true and reactive power of the DG output, the voltage and fre-
quency vary. Droop control is based on the premise that the main induc-
tive impedance of DG output is regulated by the droop voltage amplitude
and frequency characteristics of each DG. The microgrid voltage ampli-
tude and frequency are, in other words, the interactive contact connection
here. The frequency and voltage variations are governed by linear rota-
tional transformation.
Active and reactive power sharing is done using P-f droop control and
Q-V droop control. Reactive power-sharing is dependent on the imped-
ance of the power line in an islanded mode. The equivalent transmission
line impedance could be unequal due to the varying distances among the
DERs interface converters. The Q-V droop control overcomes the effect
of line impedance on the reactive power flow [38]. It is used to enhance
cooperation between power electronic inverters to improve voltage regu-
lation and load dispatch. This technique can be used with traditional syn-
chronous generators (DGs) where mechanical power is regulated to keep
the frequency constant. This method has the advantage of providing fre-
quency stability for overloaded systems, as well as allowing power sharing
in high-voltage multi-microgrids at high voltage levels. Fault rate in per-
manent voltage and power fluctuations and fluctuation in frequency and
voltage values based on load and failure in reactive power sharing are all
disadvantages of this technique.
20.6.11 Control Design Based on Transfer Function

This control design is adopted from the classical feedback control approach.
A three-phase PLL provides the reference angle. The load voltage compo-
nent of q is set to zero and the component of d is set to the desired peak
value. A reference signal relationship rules Vd and the fault is transferred
to the controller. The controller then provides inputs to the VSC Gating
Signal Generator. This oscillator’s purpose is to control the frequency in an
open-loop manner. In addition to the non-conservative robustness limita-
tion, the robust servomechanism controller was developed using parame-
ter optimization methods [34].
20.6.12 Direct Lyapunov Control (DLC)

For the activity of DGs, the Direct Lyapunov Control provides a secure
area. During grid integration, DLC provides reliable operation by con-
stantly injecting full active power from the DG sources to the grid at a basic
frequency, compensating for both reactive power and harmonic current
nonlinear load elements [39]. This method ensures the global asymptotic
stability for the DG units.
20.6.13 Passivity Based Control (PBC)

This control is used for the stabilized operation of DG units during inte-
gration and power-sharing with loads and/or power grid. This control
provides active, reactive, and harmonic current compensation of loads
in grid-connected mode. Majid Mehrasa et al. implemented an energy
shaping damping injection methodology for MG stable operation which
involves state computation [31, 33].
Energy-based control, i.e., PBC, is favoured in [1–3, 42–48] for the sta-
ble operation of the MG. The strategy of energy-shaping is the core of the
PBC technique. PBCs are generally synthesized with a stabilization goal in
mind for power electronic circuits, i.e., to attain a constant output voltage
or a constant current in the branches of the circuit. In a variety of struc-
tures, PBC exhibits consistency and robustness. Consequently, PBC sees
its uses in devices such as green energy systems, electric drives, bilateral
teleoperation systems, flexible manipulators, flight control systems, con-
stantly stirring tank reactors, and automatic aircraft landing systems. In
PBC, in terms of conservative forces, disruptive forces, and energy acquisi-
tion, both systems are modelled. The PBC control function for any system
is derived in such a manner that the energy error satisfies the stability of
Lyapunov.
Two distinct control methods are used in PBC, namely Exact
Monitoring Error Dynamics Passive Performance Feedback (ETEDPOF)
and Energy Shaping and Damping Injection (ESDI). In the implementa-
tion of ETEDPOF, when the condition of Lyapunov is not met, the LaSalle
Theorem can be used to test the stability analysis. The system can be
asymptotically stable semi-globally due to the limited existence of control

inputs in power electronic converters.
20.6.14 Model Predictive Control (MPC)

The goal of predictive control of the development model is to minimize the
forecast error for accurate current monitoring. Attractive characteristics of
model predictive control are the management of general constraints and
non-linearities of a system with several inputs and outputs in a scalable
control scheme. To predict the future behavior of the controlled variables,
this technique uses control actions of the present states. The controller
selects the best switching states according to the cost function employed as
a criterion. The method’s mathematical based approach shows its vulnera-
bility to changes in parameters [40].
In industry, this control is widely used for managing large process
plants. The MPC approach is used to deliver many features in the power
system community for the following reasons:
• Resilient to uncertainty
• It is possible to manage device constraints
• Tuning is simple to do
• Used in multivariable applications for power
In the MPC control strategy, the system’s future evolution control

sequence is calculated by minimizing a cost function based on the system
model. The cost function is obtained by minimizing the variance over the
forecast horizon from set points. There are three basic steps in model pre-
dictive control: performance prediction, estimation of control, and closing
the feedback loop.
The advantages and disadvantages of the different control methods are
discussed in Table 20.3.
The classification techniques presented in this chapter will aid research-
ers in choosing suitable control methods for microgrid transient stability
such as voltage and frequency fluctuation, voltage collapse, phase differ-
ence fault, and error in both grid-connected mode and islanded mode.
As a result, the control method helps to ensure precise microgrid tran-
sient stability. Each method’s stability, fast dynamic response, harmonic
distortion, dynamic behavior, connection type, transient response, energy
source type, voltage–frequency control, voltage level, and behavior in non-
linear loads are all periodically scrutinized. As a result, conducting research
on control methods used in microgrid transient stability is beneficial.
Table 20.3 Advantages and disadvantages of different control methods.

Control
method Advantages Disadvantages
Agent-based The control theory is based on It is reliant on connectivity
Control decision-making as well as and is vulnerable
artificial intelligence to breakdowns of
communication.
Multi-Agent Agent independence, reducing Modelling MASs is a time-
Systems the need for information consuming process
(MAS) manipulation, plug and play since many agents must
based capability, increasing the operate in parallel.
Distributed reliability and robustness
Control of the control system, and
agent learning are the
benefits of the MAS control
method over other control
methods.
Central It is a simple control technique Installation of
Control used by the power communication
converters. This technique networks are at a high
guarantees that the current cost. If used in large
distribution between the or highly distributed
DGs is right at all times, environments, it causes
including transient times. issues with system
design and development
as it has only one
monitoring unit.
Master/Slave Only the master unit has a This technique is reliant
Control voltage controller and it on a high-bandwidth
is this unit that controls communication
the output voltage and channel.
calculates the reference
current for each inverter.
Since there is no central
controller in this system, the
master unit, which serves
as a current source inverter,
distributes current fixed-
point values to slave DGs.
(Continued)
Table 20.3 Advantages and disadvantages of different control methods.

(Continued)
Control
method Advantages Disadvantages
Distributed It assists in proper load Deviation in bus voltage,
Control sharing in order to retain dynamic analytic
a constant grid voltage. behaviour, and power
This control system monitoring error
combines the benefits of are among the main
both a centralised and a disadvantages.
decentralised controller.
Droop It is used to reduce or remove Inability to keep to a fixed
Control the circulatory current schedule, and nonlinear
between converters when loads are unsuitable for
there is no communication. this content. Inability
It is easy to use and low cost. to reliably monitor
power-sharing in the
face of instability.
In areas where RES
penetration is high, the
output is poor. Transient
characteristics are bad.
Direct The continuous injection of Implementation of this
Lyapunov maximal active power in method is complex.
Control the fundamental frequency
(DLC) from DG sources to
the grid, compensating
both reactive power
and harmonic current
components of nonlinear
loads, provides a stable area
for the operation of DGs
during grid integration.
Model This method is widely used in the It is not possible to tune
Predictive control system environment offline and it cannot be
Control and it has many advantages utilized in uncertain
(MPC) such as being immune to systems.
instability, can accommodate
device constraints, is simple
to implement in multivariable
control applications, and
tuning is easy.
This research on the benefits and drawbacks of control and optimization

algorithms for microgrid transient stability may lead to new ideas for
research and applications.
20.7 IEEE and IEC Standards

The IEEE Standards have been established to deal with the implementa-
tion of MGs and safe and efficient power systems [57]. Figure 20.5 demon-
strates several MG-related IEEE standards and IEC standards.
IEEE 1547 gives the specifications for the interconnection of distrib-
uted generation capacity with the power grid. The additional parameters
are structured to expand and justify the initial standard and are seen in
Figure 20.6. [57] provides commonly used microgrid technology require-
ments and realistic reviews of these criteria prior to introducing an indus-
try standard for microgrid technology. Requirements for communications
networks, safety of the Internet, security of data and communications,
deployment and security of remote generators and energy storage devices,
electronic control interfaces for distributed energy supplies, and the inter-
connection of microgrids with electrical power systems are addressed.
Practical assessments are required for the above criteria to be performed by
the Institute of Nuclear Energy Research, Taiwan, on a low-voltage (380 V)
AC microgrid testbed. In the proposed standard studies, microgrid config-
urations, installation of distributed generators and energy storage systems,
microgrid operating conditions, microgrid energy management and con-
trol systems, and microgrid protection are listed. The key contributions of
IEEE
IEEE 446 IEEE 1547 IEEE P1547 IEEE 519

& IEEE 929
Emergency and Interconnecting Harmonic DG Installation

standby power DR with Electric Analysis Regulation
systems practice Power system and voltage
flicker Limit curve
definition
Figure 20.5 IEEE standards for MGs.

IEEE 1547.1 Conformance test Procedures

Standard for Interconnection of Distributed Resources and Electric Power Systems
IEEE 1547.2 Application guide
IEEE 1547.3 Monitoring, Information Exchange, and Control
IEEE 1547.4 Design, Operation and Integration

IEEE 1547
IEEE 1547.5 Interconnection of power sources > 10 MVA
IEEE 1547.6 Draft recommended practice
IEEE 1547.7 Conducting Distributed Impact Studies Guide
IEEE 1547.8 Implementation, Strategies, Methods and Procedures
Figure 20.6 IEEE 1547.
this section are (i) to review and evaluate common microgrid standards,
(ii) to present Taiwanese research work to establish a microgrid standard
for industry applications, and (iii) to suggest realistic tests of essential
microgrid standards and how these tests can be performed at a low-voltage
AC microgrid in Taiwan in real-time.
The international non-governmental, non-profit norm body is the
International Electrotechnical Commission. Relevant standards for all
relevant electrical and mechanical technology are prepared and issued by
the IEC [57]. Technical specifications and guidelines for the development,
management, and design of renewable energy and hybrid rural electrifica-
tion systems are provided by IEC TS 62257 (Figure 20.7).
IEC TS 62257-1 Rural Electrification General Introduction

Recommendation for small Renewable Energy and Hybrid System for Rural Electrification
From Requirements to a range of Electrification

IEC TS 62257-2
System
IEC TS 62257-3 Project Development and Management
IEC TS 62257-4 System Design and Selection

IEC TS 62257
IEC TS 62257-5 Protection against Electrical Hazards
IEC TS 62257-6 Acceptance, Operation, Maintenance and
IEC TS 62257-7 Generators
IEC TS 62257-8 Selection of Batteries and its Management Systems
IEC TS 62257-9-1 Micropower Systems
IEC TS 62257-9-2 Microgrids
Figure 20.7 IEC TS 62257.
20.8 Challenges of MG Controls

There will be a significant rise in MG installations and integration in LV
distribution systems in the future. Therefore, distribution systems will be
more significant with a greater number of MGs and differ in characteristics
from the current conventional distribution systems for which the design
of suitable control strategies must be done for anticipating the difference.
The aim of MG controls is optimizing production and consumption of
heat, gas, and electricity for improving the overall efficiency. There is a pos-
sibility of conflicting requirements and limited communication for con-
trolling a large number of small-scale RES with different characteristics,
which will be challenging. When it comes to linear and nonlinear loads in

the same bus connection under normal and islanding modes of bus con-
nection, electricity distribution will become critical.
The challenging part in the decentralized or centralized controller is the
required control action with the loss of input parameters. Large mismatches
may be caused between generation and loads during transitions from grid-con-
nected mode to an islanded mode, which causes severe frequency and voltage
control problems. The connection and disconnection process involves a larger
number of micro sources at the same time. Thus, the “plug-and-play” capa-
bility creates a serious problem. Operating in the same control frequency for
different types of loads is typical and maintaining the stability in such a system
during the operation becomes more critical and quite challenging.
20.8.1 Future Trends

The development of power converters remains a challenge. The analysis
of these is performed but has not been thoroughly studied under MG sce-
narios. The plug-and-play capability must be studied. Modularization of
power converters must be included in the designing process to improve
performance. Further research must be done in reactive power-sharing,
frequency, and voltage deviations. Multiple MG management control tech-
niques have to be improved for the enhancement of efficiency, reliability,
and stability analysis. Studies in energy management strategies must be
developed for controlling the flow of energy.
MG reduces fossil fuel dependency and increases the overall efficiency,
reliability, and power quality of the electric grid. The important aspects of
MG are grid integration and energy management schemes for proper opera-
tion. An overview of MG control and different energy management schemes
has been reviewed for improved and stable operation of the MG and opti-
mizing the use of renewable energy resources. The challenges of MG control
and the future trends of the MG are also discussed in this chapter.
Acknowledgement
The authors thank AICTE for the financial support through MODROB
scheme.
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21
Control Techniques in
Sustainable Applications
R. Dhanasekar1*, L. Vijayaraja1 and S. Ganesh Kumar2
DEEE, Sri Sairam Institute of Technology, Chennai, Tamil Nadu, India

1
2
DEEE, College of Engineering Guindy, Anna Univeristy, Chennai, Tamil Nadu, India
Abstract
In recent years, renewable energy sources (RES) have played a vital role to meet the
power demand with the quality of power. In RES, the power electronic convert-
ers are effective for changing characteristics of voltage and current. The introduc-
tion of control system techniques in the engineering field has made development
in various renewable energy applications. The control techniques has the ability
to give robust performance and is insensitive to parameter variations. Recently,
sliding mode controls have become attractive due their robust performance. In
variable structure systems, a sliding mode control is an efficient tool for complex
non-linear multi-variable plants. In recent years, Passivity-based Control (PBC)
has been adopted in RES due to its robustness against parameter uncertainties.
The system which comprises PBC achieves the desired control parameters with
no peak overshoots and oscillations. Model Predictive Control (MPC) has been a
likely control technique for power electronic converters because of its quick reac-
tion and high control data transfer capacity. This chapter deals with the concepts
of Sliding Mode Control, Passivity-based Control and Model Predictive Control
in Sustainable Applications.
Keywords: Renewable energy sources, sliding mode control, passivity-based

control, model predictive control
631
21.1 Introduction
Nowadays, control methodologies play a major role in renewable energy
system integration with the grid. A non-linear Sliding Mode Controller
(SMC) is implemented in various power conversion stages in grid inte-
gration. In SMC, relay function, signum function, Hysteresis function,
and equivalent control are presented to regulate the flow of active and
reactive power in the grid, load, and converters. During improper loaded
conditions in the non-linear loads, the Sliding Mode Controllers dimin-
ish the total harmonic distortion and maintain the unity power factor [1].
The dead time effects introduce voltage distortion in the output voltage of
the inverter. The dead time effects in the inverter output eliminated the
super twisting second order Sliding Mode Technique in the three phase
grid integrated renewable energy systems. The proposed algorithm reduces
the chattering and fast response in the frequency variations on the grid
side. The super twisting second order sliding mode algorithm is compared
with a PI controller to validate the performance [2]. The maximum power
is extracted by the Maximum Power Point Tracking (MPPT) technique
in a Photovoltaic (PV) system. To extract the maximum power, a non-
linear back stepping sliding mode (BSSM) MPPT algorithm is proposed.
The proposed BSSM MPPT algorithm gives robust output, low steady state
error, fast speed tracking, eliminates the peak overshoot, and provides sta-
ble response under load and environmental variations [3]. In renewable
energy systems, wind energy plays a vital role in industrial development.
The voltage fluctuations occur due to the uncertain parameters and distur-
bance on the load side. So, a novel control methodology called the adap-
tive sliding mode controller and sliding mode observer is proposed in the
converter located at the load side to enhance the stability of the overall sys-
tem. The reactive power is compensated by the adaptive sliding mode con-
troller in the static compensator interconnected in a wind-diesel hybrid
system [4]. The active power control and maximum power extraction and
two sliding mode controllers is proposed for the variable speed wind tur-
bine integrated with a Double-fed Induction generator. The Proportional
Integral SMC and Supertwisting Second Order SMC are implemented in
rotor side converters to eliminate the chattering effect and enhance the
tracking [5].
The power is controlled in doubly fed induction generators by an adap-
tive sliding mode neuro-fuzzy controller. The proposed sliding mode con-
trol algorithm is used to train the online parameters for the type-2 fuzzy
membership functions. The time derivative of active and reactive power is
Control Techniques in Sustainable Applications 633
regulated by type-2 fuzzy membership functions. The simulation results

of the proposed controller are compared with the classical proportional
integral controller [6].
Interconnection and Damping Assignment-Passivity Based Controls
(IDA-PBC) are proposed for the enhancement of energy management and
damping improvement. The DC-DC converters are the gateway between
the renewable energy system and DC microgrid. The proposed controller
is implemented for the inverter in the grid side and DC-DC converters
which are connected with fuel cells and battery backup. Depending on the
battery state and the availability of the grid parameters, the IDA-PBC is
tuned. The integral term is added with IDA-PBC to eliminate the steady
state error [7]. A capacitive coupled grid connected inverter (CGCI) is the
gateway between the distribution grid and renewable energy sources. A
non-liner passivity based controller is designed to achieve asymptotic sta-
bility for tracking the current in GGCI with fast response [8]. A passiv-
ity controller based on a perturbation observer is designed for a voltage
source converter with multi-terminal direct current systems. The observer
is designed to estimate the no linear effects, faults in the grid, and variation
of output power. The estimated parameters are fully compensated by the
passivity based controller. The output DC voltage and reactive power in the
rectifier side and the output AC voltage and active power in the inverter
side is regulated by the proposed controller [9]. In PV systems, the DC-DC
converters are used as a gateway between the solar panels and the load. A
passivity based controller is implemented to regulate the load variations
[10]. A non-linear passivity based controller is proposed to extract the
maximum power from the windmill to regulate the DC link voltage and
power factor in the grid [11].
In a hydro-turbine governing system, an Adaptive Model Predictive
Controller is proposed as a load/frequency controller. The proposed con-
troller is validated in both load control mode and frequency control mode.
The controller is implemented using Hildreth’s algorithm as a quadratic
programming solver [12]. In recent years, integrated renewable energy
sources with the power grid have emerged. Model Predictive Controller
(MPC) is proposed to attain optimal power in predicting the generation
of renewable energy. MPC is designed by the combination of genetic algo-
rithm with a state space model [13]. In large multi-connected systems, the
Model Predictive Controller is implemented for load frequency control.
The desired output is achieved and the interconnected system comprises of
six power plants with renewable energy sources under load variations [14].
Due to the presence of inverters in storage systems, frequency regula-
tion is the major challenge. The future behavior of the system is predicted
by the new virtual inertia emulator-based model predictive control. The

control technique is compared with a proportional and proportional inte-
gral controller [15].
Section 21.2 describes the sliding mode control techniques in sustain-
able applications. Section 21.3 describes the Passivity-based Control (PBC)
in sustainable applications to improve the performance of voltage stability
and Section 21.4 describes the Model Predictive Control (MPC) in sustain-
able applications.
21.2 Sliding Mode Control Techniques in Sustainable

Applications
Nowadays, renewable energy systems play a vital role in the generation
of electric power. A multi-input single output DC to DC converter is
used to utilize the energy resources with different voltage and power lev-
els to achieve the desired output voltages. The DC to DC converters are
non-linear in nature because of their characteristics. Due to the switch-
ing sequence of converter, the control structure is a challenging one. To
improve the control point of view, many researchers used various non-
linear controllers to achieve the voltage levels in the output. Recently, the
Sliding Mode Controller (SMC) is attractive due to its robustness and
uncertainty to parameter variations. To attain the desired output, the SMC
forces the trajectory in the exact location by using a high speed switching
technique. A double input single output DC to DC converter is presented
in [16] with sliding mode control. Figure 21.1 shows the renewable energy
system in the hybrid using the sliding mode control technique.
Figure 21.2 shows the dual input single output DC-DC converter. The
voltages V1 and V2 are sources from wind and solar PV array. The con-
verter consists of two switches, Q1 and Q2, and the DC link capacitor. The
two sources V1 and V2 are interconnected with capacitor C.
The sliding surface is given in Equation (21.1).
n−1
d 
S= +λ e(t ) (21.1)
 dt 
where λ is a positive constant.

Diode
PMS Bridge Double Input
G Rectifier Single Output
DC-DC
converter
Wind Turbine Load
PV array
Battery
Sliding Mode
Controller
Figure 21.1 Renewable energy system in hybrid using sliding mode control technique.
L1 D1
V1 Q1
+
–
C R
L2
Q2
V2
+
–
D2
Figure 21.2 Dual input single output converter.

The error is given in Equation (21.2).
e(t) = vref – vactual (21.2)
The control input consists of equivalent control Ueq and switching con-
trol Usw and is given in Equation (21.3).
U = Ueq + Usw (21.3)
The equivalent control regulates the nature of the system and the switch-
ing control reduces the system uncertainties. Figure 21.3 shows SMC with
a Dual Input single output converter. The controller contains two loops.
The inner loop contains current control and outer loop contains voltage
control.
Table 21.1 shows the effectiveness of SMC in A Multi Input DC-DC
Converter [16].
Input Voltage
DC-DC
Converter
Actual
Inductor current Voltage
Control Input
U
+
Current PI Voltage
Controller CONTROLLER Controller
Reference
Voltage
Figure 21.3 SMC with dual input single output converter.
Table 21.1 Performance of SMC.

Parameters SMC performance
Settling Time 0.135 sec
Chattering 0.2V
Transients No overshoots
In [17], for a hybrid standalone system, an advanced power manage-

ment system is presented. The hybrid system consists of a PV panel, fuel
cell, and battery system. The output from the PV panel, fuel cell, and battery
system is connected commonly in a DC bus through DC-DC converters.
The PV panel is connected to a DC bus by a boost converter which adopted
the Maximum Power Point Technique. The second order SMC is adopted
for MPPT control. The battery system is connected to DC bus through
a Bidirectional Buck-Boost Converter. Figure 21.4 shows the structure of
hybrid system.
Figure 21.5 shows the Second Order SMC for a Boost Converter. The
actual voltage Vac is compared with the reference voltage Vref generated
DC Bus
PV Boost
Panel Converter
MPPT
DC-AC
Converter Load
Buck Boost
Battery
Converter
SMC
Super
Capacitor
Figure 21.4 Structure of hybrid system.
Boost
Converter Vac
Vpv IL
MPPT Second
Algorithm Order SMC
Vref
Figure 21.5 Second order SMC for boost converter.

from the MPPT algorithm. VPV and IL are the panel output voltage and
inductor current on the boost converter. Consider X1 = IL and X2 = Vout.
The sliding surface is given as in Equation (21.4).
∫
S = e + K edt (21.4)
where error e = (x2 – x2)

The second order SMC is expressed as in Equation (21.5)
2
S = (e + Ke ) (21.5)
The region of the control input is in between 0 and 1.

The super twisting algorithm is expressed as:
u = u1 + u2 (21.6)
where
u1 = −k1 sgn(s)
0.5
u2 = − k2 S sgn(s )
K1〉0 and K2〉0
The results in [17] show that the second order SMC prevents the battery
from overcharge during heavy loads and very bad weather conditions. It
increases the efficiency of the overall system by disconnecting critical loads
under heavy loaded conditions.
The efficiency of the solar system is attained by an MPPT algorithm.
In [18], for the standalone solar PV system, a fractional integral termi-
nal sliding mode MPPT algorithm is adopted for the maximum extraction
of solar power. For DC to DC conversion, a Buck Boost Converter is
used. To generate the reference voltage, a Radial Basis Function Neural
Network (RBFNN) is trained. The proposed controller is compared with
the Proportional Integral Derivative Controller and Perturb and Observe
algorithm. Figure 21.6 shows the structure of the Fractional Order Integral
Terminal SMC Algorithm with a PV panel.
RBFNN is trained to provide the reference voltage Vref . The irradiance
and temperature is input to the network and the three neurons are used in
the hidden layer. Figure 21.7 shows the structure of a Radial Basis Function
Neural Network (RBFNN).
IPV
Buck
PV
VPV Boost Load
Panel
Converter
Vref +
Radial Basis Fractional Order
Function Neural Integral Terminal
Network - SMC Algorithm
Figure 21.6 Fractional order integral terminal SMC algorithm with PV panel.
Hidden Layer
H-1
Input Layer
Irradiance
Output Layer
H-2 Vref
Temperature
H-3
Figure 21.7 Structure of radial basis function neural network (RBFNN).
The modeling of a Buck-Boost Converter is given as in Equation (21.7).
dv pv i pv iL
= − u
dt c1 c1
diL v pv v
= u − 0 (1 − u)
dt L L
dvc 2 iL v
= (1 − u) − 0 (21.7)
dt c2 Rc 2
where Vpv, ipv, iL, V0, c1, c2, and u are the PV panel array output voltage, PV
panel array output current, inductor current, output voltage, input capaci-
tor voltage, output capacitor voltage, and the control input.
The state space model is given as in Equation (21.8).
i pv x 2
x 1 = − φ
c1 c1
− x (x + x )
x 2 = 3 + 1 3 φ (21.8)
L L
x x x
x 3 = 2 − 3 − 2 φ
c 2 Rc 2 c 2
where x1, x2, x3, and ϕ are the average values of PV panel array output volt-
age, PV panel array output current, output voltage, and control input.
The sliding surface is given as in Equation (21.9).
S = e + Ke1 (21.9)
Error e = x1 – x1ref
m
where e1 = e n sgn(e )
m
The region of is bound between 0 and 1.
n
The equivalent control is defined as:
.
 m 
c1  I pv
φeq = − x1ref + Ke sgn(e )
n (21.10)
x 2  c 2 
The fractional order terminal SMC is given as:
ϕc =ϕeq + ϕsw
Where ϕsw = λ1(S) + λ2 sgn(S)

Where λ1 and λ2 are positive values
The proposed controller is compared with a PID controller and PO
algorithm for various resistive loads and climatic conditions. The proposed
controller is investigated under the parameters such as error, overshoot,

and settling time.
Fast terminal sliding mode control with direct power control is designed
for the maximum power extraction from the PV panel. The system consists
of two cascaded loops. Perturb and Observe (PO) algorithms acted as an
inner loop in which the PV panel voltage Vpv and current Ipv are the input
parameters. The Perturb and Observe (PO) algorithm generates the refer-
ence active power. The reference active power and actual active power are
compared and the error signal is given to the fast terminal SMC. The fast
terminal sliding mode control acted as an outer loop in which the active
power error and reactive power error are the input parameters. A sinu-
soidal pulse width modulation technique is adopted for the generation of
gate pulses. The gate pulses from the sinusoidal pulse width modulator are
given to the inverter. Figure 21.8 shows the structure of the grid connected
PV panel with fast terminal SMC [19].
The sliding surfaces are chosen with active and reactive power, as given
in Equation (21.11).
S = [ S p Sq ]
T
∫ ∫
e p dt + δ p  e p dt 
l
Sp = e p + γ p
 
r
∫ ∫
eq dt + δ q  eq dt 
l
Sq = eq + γ q (21.11)
 
The active and reactive powers are given as Equation (21.12).
1
P=−
2
( v gα i gα + v g β i g β )
1
Q = − ( v g β i gα + v gα i g β ) (21.12)
2
The final control law is the combination of equivalent control and

switching control (discontinuous control). The final control law is given to
the sinusoidal pulse width modulator. The sinusoidal pulse width modula-
tor generates appropriate pulses to the inverter. The stability of the control
T1 T3 R L
PV
C Grid
Panel
T4 T2
Pref
PO
Fast Control
Algorithm
Terminal Signal
SMC
P
Qref
Figure 21.8 Grid connected PV panel with fast terminal SMC.
law is analyzed by Lyapunov Stability Theorem. The tuning parameters in

the sliding surface are properly selected to attain minimum settling time
and steady state error. The simulation is carried out in MATLAB for both
steady state and transient conditions. From the results, the fast terminal
sliding mode control performs better results in converging time. Even
in the presence of disturbances, the active and reactive power are inde-
pendently controlled. Due to controller robustness, the Total Harmonic
Distortion (THD) is 3-5% for the grid current [19].
A voltage mode second order sliding mode controller is proposed to
extract the maximum power from the wind energy conversion systems.
Sensorless maximum power point tracking is implemented to track the
optimum voltages. A PID sliding surface is chosen and the control law is
generated in the second order [20].
Figure 21.9 shows the wind energy conversion system with a second
order PID sliding surface. The PMSG is connected to the wind turbine
without gearbox arrangements. PMSG is connected to the load through a
rectifier and boost converter. The reference voltage is generated from the
MPPT technique and the generated voltage given to the second order SMC.
The control system variables are given as:
X1 = Vref – Vin
Wind Uncontrolled Boost Resistive

PMSG
Turbine Rectifier Converter Load
Vin
Io
Second Order
MPPT Driver
PID Sliding
Vref Circuit
Mode Controller u
Vo
Vo
Figure 21.9 Wind energy conversion system with second order SMC.
X 2 = X 1
The PID sliding surface is defined as in Equation (21.13)

t
∫
S = PX1 + I X1 dt + D X 1
0
(21.13)
The control signal is given as in Equation (21.14).
LC   1 P βλ  I β 
u = 1+  X 2  − + −  − X1 − X 2 
D(Vo − Vref + X1 ) RC D D D D 
(21.14)
Table 21.2 shows the comparison of classical SMC and second order
SMC. From Table 21.2 it is clear that the performance of second order SMC
is good in terms of integral absolute error (IAE), integral square error (ISE),
and integral of time with absolute error (ITAE). The results are validated by
wind speed profiles from 5m/s to 12m/s. The proposed controller is com-
pared with classical SMC in terms of ripple voltage content, steady state
error, and the extraction of average power [20]. With proper change in the
switching states, the SMC changes the subsystems structures at any time.
Due to these features, SMC plays an important role in power converters
and drives. In [21], the implementation of SMC in DC drives, AC drives,
and special machines is discussed. The chattering effect in the drives is
reduced by the implementation of higher order SMC. Third order SMC is
discussed in [22] to control the speed of a permanent magnet DC motor.
Table 21.2 Comparison of classical SMC and second order SMC.

Integral Integral of Time
Non–linear Absolute Integral Square with Absolute
controller Error (IAE) Error (ISE) Error (ITAE)
Classical 22.86 274.5 95.49
Sliding Mode
Controller
Second order 15.03 226.1 63.18
Sliding Mode
Controller
21.3 Passivity-Based Control in Sustainable

Applications
A passivity based controller based on a decoupling method is proposed

for a T-Type neutral point clamped photovoltaic grid connected inverter.
First, based on the operation and basic principle Euler-Lagrange (EL)
model for T-Type neutral point clamped, a photovoltaic grid connected
inverter is designed with inductor and capacitor components. Secondly,
by damping injection method a passivity based controller is designed.
Third, a PI controller together with a passivity based control is adopted
to regulate the DC voltage. The proposed controller achieves the dynamic
decoupling current under a synchronous rotating dq coordinate system.
Also, it improves the quality of current in the grid side inverter under
T-Type Neutral 3-Phase

PV DC-DC
Point Clamped AC Grid
Panel Converter
Inverter
Passivity Based
Controller
Figure 21.10 T-Type neutral point clamped photovoltaic grid connected inverter.
disturbances. There are two types in a photovoltaic grid connected system:

one stage and two stages. Later, it developed as a DC-DC converter with
a grid side inverter, as shown in Figure 21.10. PV output voltage is given
to the DC-DC converter. The output from the DC-DC converter is given
to the grid-side inverter which is converted to AC. A T-Type neutral point
clamped is implemented due to its minimum loss, loop current in symmet-
rical path, and reliability [23].
The system is passive such that
t t
∫ T
∫
H ( x (t )) − H ( x (0)) ≤ u y dt − Q( x )dt
0 0
(21.15)
where T ≥ 0
x(t), y(t) are the input and output state vectors
The passivity based controller was proposed and implemented experi-
mentally for a 10Kw prototype which shows performance of the system for
various grid side currents [23].
For DC microgrid applications, passivity based control is presented
for wind energy conversion systems with switched reluctance generators
(SRG). The output voltage is stabilized for constant power loads. The sys-
tem operates under the maximum power point tracking technique for volt-
age stabilization. Using the Euler-Lagrange System, a switched reluctance
generator with a microgrid is modeled which improves the stability and
ripple reduction in the DC link. An adaptive technique is adopted with a
passivity based controller to deal the inductance in a time varying manner
and back EMF of SRG. The closed loop stability is analyzed by Lyapunov
Theorem. The reduction in voltage ripple and speed tracking is achieved by
the proposed controller [24].
Figure 21.11 shows a passivity based control for a wind driven system.
A Switched Reluctance Generator operates under self excited mode and it
is connected to the DC link capacitor through a boost converter. The DC
link capacitor supplies constant power loads. The battery pack consists of
lead acid batteries and is connected to a bidirectional DC-DC converter.
The bidirectional converter is used because the DC link voltage is not
always equal to the voltage across the battery at all the conditions and the
charging/discharging of batteries which creates ripples. The bidirectional
converter minimizes these problems. The proposed controller reduces the
undamped oscillations, increases the stability of the system, and minimizes
Constant
Wind SRG
SRG Power
Turbine Converter
Load
Current Bidirectional
PWM DC/DC Battery
Controller Converter
PWM
Controller
Passivity Based Controller

with Back Emf Coefficient
Calculation
Figure 21.11 Passivity based controller for wind driven system.
the destabilizing effect in constant power loads. Also, it tracks the rotor
speed and reduces the DC link voltage ripples [24].
A passivity based linear feedback control (PBFLC) is proposed in a wind
energy conversion system with a permanent magnet synchronous gener-
ator to achieve the maximum power point tracking (MPPT) at the grid
side voltage source converter and improves the fault ride through capabil-
ity in the grid side converter. To regulate the desired tracking error, linear
Generator
Side Grid Side
Multi Pole
Wind Voltage Voltage
Synchronous AC Grid
Turbine Source Source
Generator
Converter Converter
Passivity Based Linear Passivity Based Linear

feedback Control feedback Control
Figure 21.12 Multi-pole synchronous generator with passivity based linear feedback
control.
feedback control is employed with auxiliary inputs. Step changes in wind

speed, random wind speed variation, and fault ride through are analyzed
[25].
Figure 21.12 shows the structure of a synchronous generator with pas-
sivity based linear feedback control. The energy from the wind is captured
and given to PMSG. The system consists of back-to-back voltage source
converters (VSC). The generator side converter controls the active power
and reactive power. The generator side converter and grid side converter
are independently controlled and the power grid and the PMSG are decou-
pled by the DC link capacitor. The PBFLC is designed for both grid side
VSC and generator side VSC.
The contributions in the paper [25] are given as:
i) The transient response of PMSG is improved.

ii) The closed loop system is fully investigated so that the pro-
posed controller is accepted to implement both in indus-
try and academics.
iii) The performance of the controller is good and achieves
MPPT for all the desired speeds.
The passivity based control method is employed for a small hydro-

power system with a Permanent Magnet Synchronous Generator (PSMG).
The overall system is connected to the grid through the back-to-back con-
verter. In passivity based control, two methods such as standard passivity
based control and PI passivity based control are implemented. The intrin-
sic characteristic of the model is considered for this control approach. The
control law is designed to ensure stability by Lyapunov’s Theory [26].
Figure 21.13 shows a hydro system with PMSG integrated with the grid.
The system comprises of electrical, mechanical, and hydraulic compo-
nents. The PMSG is integrated with the grid through back-to-back con-
verters. The proposed controller is tested with the conventional method in
a 13.2kv feeder for a standard passivity based controller, PI passivity based
controller, and classical PI controller. The results prove that the proposed
method attains stability and good performance [26].
The Passivity-Based Control technique is presented to regulate the
output current of the buck-boost converter. The buck-boost converter is
connected in between the DC microgrid and the permanent magnet syn-
chronous generator (PMSG) for the pitch angle control, wind turbine cal-
culations, and regulation of torque in the rotor [27].
Figure 21.14 shows the integration of a wind energy conversion system
with the DC microgrid. To ensure constant torque in the generator and to
Small Hydro PMSG AC-DC DC-AC Grid

Power System Converter Converter
Standard/PI Standard/PI
Passivity Passivity
Based Based
Controller Controller
Figure 21.13 Small hydro system integrated with grid.
Wind Un Controlled Buck Boost

PMSG Load
Turbine Rectifier Converter
Pitch Angle VO
Control Passivity
Based
IL Controller
Figure 21.14 Wind energy conversion system with DC microgrid.
protect the over speed of the rotor, pitch angle control is installed. A buck-
boost converter is connected in between the rectifier and DC microgrid
through a DC link capacitor. The performance of the controller is validated
through MATLAB simulation results [27].
An Adaptive Passivity Based Control is proposed to mitigate the insta-
bility issues in a buck converter fed DC microgrid. A non-linear distur-
bance observer (NDO) is designed based on Passivity Based Control to
control the load variation and line variation. To improve the performance
of the system in disturbance, the non-linear disturbance observer is con-
nected in parallel with the Adaptive Passivity Based Controller [28].
Figure 21.15 shows the Structure of a DC microgrid system. The sources
for the system consist of a battery system and PV panels. The resistive load
and constant power load (CPL) are connected in parallel. The load bus
voltage will be in oscillating nature if the resistive load is higher than CPL.
Source Bus Load Bus
Resistive
Buck Load
PV Boost Converter
Panel Converter
CPL
DC-DC
Battery Bidirectional DC-AC AC
Converter Bidirectional Grid
Converter
Figure 21.15 Structure of DC microgrid system with PV panel and battery system.
This leads the system to be unstable. So, a non-linear control is imple-

mented to make the system in equilibrium state.
Figure 21.16 shows the control block diagram of a passivity based
controller.
The reference inductor current is generated by the given equation as
Vo P 1
I Lref = + + (Voref − Vo ) (21.2)
R Vo R
Vref ILref U
V P 1 1
ILref = O + + (Voref –Vo ) u= (Vo + R(ILref –iL ))
R VO R E
Vo
Figure 21.16 Control block diagram of passivity based controller.

The control signal is generated as
1
u= (Vo + R( I Lref − iL )) (21.3)
E
where E is the supply voltage for the buck converter, R is the load resistor,
Vo is the output voltage, Iref is the reference inductor current, iL is the actual
inductor current in a buck converter, and u is the control signal. The per-
formance of the system is compared for Passivity Based Control, Integral
Passivity Based Control, and Passivity Based Control with NDO. In distur-
bance conditions such as line variations, the Passivity Based Control with
NDO has less overshoot and fast settling [28].
21.4 Model Predictive Control in Sustainable

Applications
The Model Predictive Control (MPC) is employed for grid connected
systems which comprise of a photovoltaic (PV), wind turbine (WT), and
battery. The advantage of the proposed system is that the customers can
reduce the energy cost consumed from the grid side. The simulation result
shows the effectiveness of the proposed controller under external distur-
bances. Also, optimal power flow is achieved with reduction in cost.
Figure 21.17 shows the diagram of the Hybrid System consists of a PV
panel, wind turbine system, and battery system. The PV panel, wind turbine
system, and battery system are connected to a common DC bus through
converters. Inverters are employed to connect the DC bus and AC bus. The
output from the AC bus is given to the main grid. Nowadays, Demand Side
Management (DSM) plays an important role in hybrid renewable energy sys-
tems. Time of Use (TOU) in employed in the DSM to analyze the electricity
cost for different periods. In peak periods to pay maximum cost, in standard
periods to pay standard cost, and off peak periods to pay minimum cost [29].
The cost and savings of energy for MPC and an open loop control strat-
egy are analyzed. The analysis is shown below in Table 21.3. The cost is
analyzed for Moroccan currency for both the methods.
From the Table 21.3, it is clear that the daily electricity costs is reduced by
the TOU tariffs. By comparing the open loop and MPC methods, the MPC
approach enhances the energy management system and reduces the costs
under disturbances [29]. Figure 21.18 shows the control structure of the
plant which consists of optimizer and MPC.
DC Bus AC Bus
DC-DC
PV Array Main Grid
Converter
AC-DC DC-AC
Wind Plant
Converter Converter
AC Load
Battery DC-DC
Bank Converter
Optimal
PV, Wind, Load and Battery Power flow
MATLAB
Power
Electricity Price
Figure 21.17 Structure of hybrid system.
Table 21.3 Comparison between open loop control and model predictive
control.
Sales
Control Baseline cost Optimal cost (MAD/ Cost savings
method (MAD/Day) (MAD/Day) Day) (%)
Open Loop 265.04 198.07 27.71 25.27
Control
Model 265.04 172.72 14.40 34.83
Predictive
Control
U(t) y(t)
MPC Open Loop Plant
Cost
Optimizer Function
Constraints
Figure 21.18 Control structure of plant.
Model predictive control based MPPT technique is proposed for pho-

tovoltaic (PV) systems with high gain DC-DC converters. A high gain
DC-DC converter is proposed for utilizing maximum power from the PV
module. The voltage gain is about ten times of the input voltage obtained
from the proposed topology. Two voltage and one current sensor are
needed for the conventional MPPT technique. In the proposed topology,
only two sensors are required. The model predictive control based MPPT
technique is operated in both fixed and adaptive step changes [30].
Figure 21.19 shows that the new high gain DC-DC converter consists of
two diodes, two inductors, two switches, and one capacitor in the output
side.
The voltage gain for the proposed converter is given as in Equation
(21.4).
1+ D
= where D is the duty cycle (21.4)
1− D
The discrete time model derived for the high gain converter by the for-
ward Euler method is given as in Equation (21.5).
on  2T 
I pv (k + 1) = V (k ) + I pv (k )
 L  pv
 2T 
 L  [ pv
off
I pv (k + 1) = V (k ) − Vo ] + I pv (k ) (21.5)
D1
L1 D2
D0
V+ C1 Q1 L2
C0 R0
Q2
Figure 21.19 High gain DC-DC converter.
where T is sampling time, L is inductance, Vpv is output voltage from PV,

on
Ipv is output current from PV, I pv is predicted PV current when the switch
off
is in the OFF state, and I pv is predicted PV current when the switch is in
the ON state.
Figure 21.20 shows the control signal generation for the proposed sys-
tem. Both simulation and hardware results are analyzed for a 150W DC-DC
converter prototype and it is compared with the analytical analysis. In the
proposed algorithm, the voltage sensor at the output side is replaced with
an observer and it optimizes the cost of the system [30].
IPV(K) Adaptive I*PV(K+1)

incremental
conductance
VPV(K)
Control
Signal
Optimization
Prediction IPV(K+1)
Figure 21.20 Control signal generation for proposed system.

Due to the simplicity and fast dynamic response, model predictive con-
trol (MPC) plays a vital role in the power converters. MPC act as current
regulator for the voltage source inverter in dual mode operation. From the
PV panel, the voltage source inverter (VSI) provides the desired current to
the load in islanded mode. Also, the VSI acts as an active power filter for
reactive power compensation. Model predictive current control is applied
to the two level H-bridge converter. The two level H- bridge converter
works to compensate the reactive power and feed the voltage to the load
[31].
Figure 21.21 shows the structure of a) Islanded VSI and b) Grid con-
nected Active Power Filter. PV panels act as a power source for both
islanded and grid connected VSI.
Figure 21.22 shows the control block of the predictive current control-
ler with two level VSI. The main objective of the MPC is to control the
load current. The whole process comprises of three states. The first state
is to identify all the switching states, the second is to initialize the switch-
ing state and calculate the cost function, and the third one is to apply the
switching state. The results are validated by MATLAB/Simulink. The simu-
lation results prove that the PCC has good current tracking response [31].
Voltage
PV System Passive Load
Source
Filter
Inverter
(a)
Electric Load
Power Grid
Voltage
PV System Passive
Source
Filter
Inverter
(b)
Figure 21.21 Structure of (a) Islanded VSI and (b) Grid-connected active power filter.
Iref(k+1)
U Voltage
Minimization of cost Source
IL(k+1)
function Inverter
IL(k)
Predictive Model
Figure 21.22 Control block of predictive current controller.
21.5 Conclusion
Renewable Energy Sources are portrayed by the capacity to change fluctu-
ating environmentally friendly power into storable and changeable power.
Various non-linear control techniques are emerging to control the param-
eters in the integration of grids. In this chapter, a review of Sliding Mode
Control, Passivity-based Control, and Model Predictive Control in sus-
tainable applications and its latest trends are discussed. Recently. Sliding
Mode Control, Passivity-Based Control, and Model Predictive Control
are adopted with renewable energy sources. These control techniques pro-
vides good performance and are insensitive to variations in parameters.
The control techniques control the non-linear parameters and provide the
output with no peak overshoots and oscillations.
Acknowledgement
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22
Optimization Techniques for Minimizing
Power Loss in Radial Distribution Systems
by Placing Wind and Solar Systems
S. Angalaeswari*, D. Subbulekshmi and T. Deepa
SELECT, VIT, Chennai, India
Abstract
The scope of the naturally available sources in power system generation is inevita-
ble nowadays due to the benefits of integration of the distributed generation. The
distributed sources, for example wind and solar, have a major role in the power
system filed as they are more abundant in nature, have less pollution and a low
operation cost, and are eco-friendly. Depending on the distribution, the network
has been classified into mesh and radial. Traditional power generation, transmis-
sion, and distribution have a radial structure in general and the non-conventional
energy sources have to be placed at optimal location to increase the power gener-
ation with less loss. Based on the connected loads in the distribution network, the
incurred system has been determined for standard bus systems.
The placing of the distributed sources and their sizing has to be determined
optimally, otherwise it may give adverse effect. Identifying optimal location and
rating of the distributed sources could be efficiently done with optimization tech-
niques. These techniques may be classical, analytical, and evolutionary methods.
Each method has its own merits and drawbacks. This chapter is going to elabo-
rate on various optimization techniques for the reduction of power loss in radial
networks by placing wind/solar energy sources at optimal locations with optimal
ratings identified by the optimization algorithms.
Keywords: Radial distribution network (RDN), power loss minimization,
optimization algorithms, distributed generation
659
I. Introduction
22.1 Distribution Systems

Owing to the exhaustion of fossil fuels and awareness of the global envi-
ronment, renewable sources are occupying more space in power genera-
tion recently. Moreover, these non-conventional energy sources are freely
available in nature, cause less pollution, and are low maintenance and
user friendly. All the consumers can easily generate the power from major
resources like solar and wind that can be utilized for their own use. The
excess power could be exported to the utility grid and this way, it is more
economical. The power generation and consumption at the consumer end
itself leads to the concept of distributed generation and these sources are
called distributed generators (DGs).
Owing to the integration of the DGs into the existing grid, the reli-
ability is enhanced by reducing the losses and the quality of the supply is
improved considerably [1]. Relieved transmission and distribution capac-
ity, improved grid performance with great asset utilization, supporting
reactive power, and management of load and energy are the main advan-
tages of the DGs addition [2]. Moreover, the conventional grid is strength-
ened by sharing the peak load and enhanced voltage profile, improving
the load factor also. Integrating DGs with the utility grid improves the
system security and efficiency [3]. The commonly used renewable sources
are solar, wind, fuel cell, micro turbines, and diesel generators. These DGs
reduce the line losses, increasing the efficiency of the transmission and dis-
tribution while connecting at the consumer end. Hence, the power quality
and voltage stability are increased significantly at the consumer side.
When the power is generated and distributed at the load end, the dis-
tribution network is benefitted. Hence, the distribution network is focused
much more on the power systems. Based on the configuration, the distri-
bution is classified into a radial network, ring, or mesh network. In the
practical network, power is generated at a generating station which is the
sole entity and it is transmitted via long transmission lines in the distribu-
tion substations. The voltage level is reduced to a lower value depending on
the applications and it is supplied to the consumers using the distribution
network.
Power Loss minimization in RDS 661
22.2 Radial Distribution Network

The general structure of radial distribution network systems (RDN) is pre-
sented in Figure 22.1, in which the generated power is distributed to vari-
ous loads after lowering the voltage.
Because of the simple structure and the low initial installation cost,
RDN is more popular. The resistance to the reactance (R/X) ratio of this
RDN is very high and the generation load is also distributed, which leads
to an ill conditioned or weak system in nature. The real power loss in the
RDN can be determined by considering the system shown in Figure 22.2,
in which the power is transferred from bus i to bus j.
The power losses occurring in the line is written in Equations (22.1) and
(22.2).
Pj2 + Q 2j
Pijloss = Rij (22.1)
Vj2
Loads
Generating
station
Feeder
Step up
transformer
Loads
Figure 22.1 General structure of Radial Distribution Network (RDN).
Vi δi Vj δj
~ ~
PGi,QGI Pij , Qij Pji , Qji PGj , QGj
Zij =Rij +jXij
Pi ,Q i Pj ,Qj
Bus i Bus j
PDi ,QDi
PDj ,QDj
Figure 22.2 Two bus system with nodes.

loss Pj2 + Q 2j
Q ij = Xij (22.2)
Vj2
where Pijloss and Qijloss are considered as the active and imaginary power
losses in the distribution line, Rij is the resistance and Xij is the reactance of
the line, Pj and Qj are the active and imaginary power flowing in bus j, and
Vj is to be the magnitude of the voltage at ‘j’ bus. Consider totally N bus in
the RDN system and the active power loss ‘PL’ in kW can be determined
using the formula [4]:
PL = ∑iN=1 ∑ Nj =1 α ij ( Pi Pj + QiQ j ) + βij (Qi Pj − PQ

i j )
 (22.3)
Rij Rij
α ij = cos(δ i − δ j ) ; βij = sin(δ i − δ j ) (22.4)
VV
i j VV
i j
Zij = Rij + jXij (22.5)
where Zij is the impedance formed with resistance and reactance in the
line, Vi and Vj are the magnitudes of the voltages with the phase angles of
δi, δ, and Pi, Pj, Qi, and Qj are real and reactive powers at nodes.
The total power comprises of real and reactive power components.
Because of the high ratio of R/X in RDN, the foremost portion of the
power loss happened due to the real power loss. Hence, this plays a more
significant role in economic operation than the reactive power loss, so the
focus is narrowed down to the real power loss reduction. Reducing the real
power loss is a more challenging and important task as the power loss is
considered as a function of square of the current flowing in the circuit [4]
and the resistance. Hence, the objective is to reduce the current flowing in
the distribution line by placing the power generating devices nearer to the
loads, which reduces the current dispatched from the particular to other
loads. The system losses are reduced in this way, which improves the volt-
age profile and the efficiency.
22.3 Power Loss Minimization

There are numerous objectives considered in the RDN for improving sys-
tem performance, such as voltage stability improvement, reducing power
losses, and minimizing the fuel cost in an economical point of view. In

most of the research areas, single or multi-objectives are considered for
meeting out the desired performance, among which the real power loss
minimization is chosen in this chapter since it is the primary one from an
operational point of view. There are various methods for loss minimization
like placement of distributed generation, placing capacitors, and doing
reconfiguration in the RDN.
Since the capacitor is generating reactive power, thereby reducing the
reactance in the transmission line, it will reduce the reactive power loss
in the total loss equation [5]. Addition of shunt capacitors could be done
for the power flow control, reducing power loss for the improvement of
voltage, and improving the stable condition. Moreover, placing a capacitor
can also be implemented for the high voltage network and it deals with
only the reactive component, therefore this method is not suitable for real
power reduction in RDN.
Feeder reconfiguration and DG placement are applied for a low volt-
age distribution network. Reconfiguration could be performed by vary-
ing the switching operation for changing the loads between the feeders.
This operation has to be performed by keeping the radial network as such.
The main drawback associated with this method is its complex decision-
making process and the computation for the reconfiguration process and
the configuration of protection devices. Owing to various advantages of
DGs and considering the environmental aspects, placing DGs for active
power loss reduction is presumed to be the best method in RDN systems.
DGs are to be placed at the proper locations with correct rating to reduce
the power loss, otherwise, it will give an opposite effect. Hence, optimiza-
tion methods can be applied in the RDN for the placement of DGs along
with optimal rating. In this chapter, the various optimization methods are
going to be discussed along with their constraints.
While solving the power loss minimization of real power loss, there are
various constraints or limitations to be considered. The main parameters
in RDN are the active and reactive power and the magnitude of voltage
and its phase angle. Several constraints of equalities and inequalities are
power balance equation, voltage limits, and active and reactive power lim-
its, which are to be specified. For practical cases, transformer tapping also
is mentioned.
a) Net Power Flow Constraints
PGi − PDi = ∑ Nj =1 VV Gij cos (δ i − δ j ) + Bij sin(δ i − δ j )

i j (22.6)
QGi − QDi = ∑ Nj =1 VV Gij sin (δ i − δ j ) − Bij cos(δ i − δ j ) (22.7)

i j
where PDi and QDi are the active and reactive power demand at node i and
the conductance of the line is Gij, whereas the susceptance is Bij. The total
DG capacity is restricted to total loads of the network.
b) DG power generation constraints:
PGmin ≤ PGi ≤ PGmax (22.8)
c) The voltage constraint is
Vmin ≤ Vi ≤ Vmax (22.9)
where Vmin and Vmax are the minimum and maximum node voltage limit.
22.4 Optimization Techniques

The true power loss in RDN is assigned proportional to the power flow in
each branch. Based on the power flow results, the loss has to be allocated
among the branches [6]. The classical power flow methods are not efficient
for the distribution networks for the load flow calculations. So, dedicated
load flow methods such as forward/backward (F/B) sweep load flow are
considered in the literature.
For calculating the power, the current in each branch is determined as
follows:
Vi ∠δ i − Vj ∠δ j
Iij = (22.10)
Zij
The power loss for any RDN is calculated based on any of the load flow
methods and it is being considered as the base case results. As discussed in
the previous section, placement of DG is more preferable than other meth-
ods. Since the network is radial in nature, the loads are connected at vari-
ous feeders. The power is fed from the generating station to various loads
through the feeder. The current and the power loss in the feeder, which
have more loads, are high compared to other feeders. Hence, the DGs have
to be placed at the feeder from which more loads are connected. This is
considered as the optimal place for the DG and also, the sizing or rating of
DG should be more optimal from an economical point of view. Otherwise,
the excess power will be unutilized and not meaningful.
Hence, the objective is chosen as the reduction of the active power loss
in RDN by suitably placing DG with its optimal sizing. While doing so, if
the DGs are placed other than at the best location, this leads to an increase
in power loss in the system. The various optimization techniques are useful
in determining the ideal location and optimal rating. The count of vari-
ables in the problem is based on the selections required in the solution.
In this chapter, optimal location and rating are the two solutions needed,
hence the numbers of decision variables are considered as two.
There are various types of DGs available such as: i) real power inject-
ing DG with unity power factor, ii) reactive power injecting DGs such as
capacitors and synchronous compensators, iii) injecting both active and
reactive power, and iv) DGs observing reactive power but injecting active
power such as induction generators deployed in wind power generation.
Solar (PV) systems are becoming very popular in the renewable energy
field as they are very clean and freely available in nature [7]. The DGs con-
sidered in this chapter are wind turbines and solar systems. The modeling
of these DGs is referred from [8, 9].
In mathematical problem analysis, there are various conventional meth-
ods available for the optimization of any objective function along with its
constraints. In the literature, conventional methods like analytical and
sensitivity based evolutionary algorithms, such as naturally inspired and
non-naturally inspired intelligent algorithms and hybrid algorithms are
presented. Depending on the objective function, it may be linear program-
ming, mixed non-linear programming, newton method, quadratic and
sequential quadratic programming, index-based method, sensitivity-based
method, dynamic programming, or Eigen value-based methods. There are
modified algorithms such as simplified analytical and efficient analytical
algorithms found in the papers.
Evolutionary algorithms are mostly inspired by nature via the various
species. With the behavior of birds and insects, the particle swarm optimi-
zation (PSO) method was proposed by taking its position and velocity as
variables. Among the population called a swarm, the best particles find the
candidate solution. The shortest movement of the species to reach its des-
tination is being considered as the optimization method. Various modified
PSO algorithms such parameter improved PSO [4] and modified PSO are
proposed in the literature.
Based on survival of the fittest, species either emigrate or immigrate to

an island, which has a better habitat suitability index. These indices are
founded with the best suitability index variables which are independent.
In a particular habitat, rainfall, temperature, and geographical location
determine the suitability index. Rate of immigration and rate of emigra-
tion can be evaluated as a function of the number of species on that island.
The population on an island could be considered as the tuning parameter
for obtaining the optimum value. When both immigration and emigra-
tion rates are equal, it is called an equilibrium number of species [10]. This
kind of optimization is called bio-geography based optimization (BBO), in
which the habitats with a low index have a high immigration rate and the
habitats having a high index have a high emigration rate. Modified [11]
and improved BBO [12] algorithms are utilized in various literature for
active power loss reduction in RDN.
Based on Darwin’s theory of evolution, the genetic algorithm (GA) has
evolved in optimization algorithms. This is slowly changing the process
based on the population. The individual chromosome is called the solution
and it has a set of genes. For each individual, the fitness value is being eval-
uated and it defines the quality of the solution. Choosing the best is called
mating and the members in the mating pool are called parents. Offspring
will be generated from the parents and cross-over and mutation are applied
in this step to generate the best among the offspring by the process of
recombination. Rate of crossover and mutation has to be chosen to reduce
the number of generations. Though GA provides a list of best solutions, it
is being suffered from computational analysis and it may not converge to
the optimal solution for improper implementation. The authors [13] have
implemented GA for active power loss reduction in RDN for the selection
of DG.
The Ant-Lion algorithm (ALO) is evolved from the hunting habit of ant
lions. This is based on the random walk of the agents and its selection [14].
These ant lions form traps by digging the sand, forming a circular cone,
and hiding there. The insects which fall on this dig are swollen by these ant
lions and consumed there. The main operators in this are the random walk
of the ants, the trap, building the trap, prey catch, elitism, and rebuilding of
the pit [14]. Initially, the most preferable DG location can be chosen using
loss sensitivity factors and then this ALO is deployed for reducing the DG
location and sizing [15].
Whale optimization algorithms are formed by the shooting nature of
humpback whales, which uses the method of chasing randomly and hunt-
ing by bubble net method [16]. These whales swim around the prey and
form a circle shape or ‘9’ shape path. It uses an exclusive method called
bubble net feeding method and this technique can be utilized for solving
the economic dispatch problem, fuel consumption problem, beam design,
and pressure vessel design problems, etc. The whale’s best location at each
iteration is updated and the encircling prey is also updated. Due to its
exploitation and exploration ability, it has been applied in power loss min-
imization problems in the electrical field.
The bat algorithm (BA) for the best location and rating of DG is applied
in RDN using the varying nature of loudness and pulse rate generation of
the bats [17]. The unique nature of bats is the echolocation identification
of the bats and it emits sonar signals which hit the object and bounce back.
The delay time between emission and the echo are evaluated by the bats
to find the shortest path for reaching the objects. The velocity and posi-
tion of the bats with varying loudness and pulse rate are considered as the
variables updated at every iteration. Population, movement of bats, local
search, pulse rate, and loudness are the major variables in BA. A shuffled
bat algorithm is implemented in [18] for the addition of multiple DGs by
increasing load demand by 20%.
A shuffled frog leap algorithm (SFLA) is proposed in [19] for the recon-
figuration with DG placement. The frogs are randomly sitting on the ponds
for food and shuffling happens between the frogs sitting within the pond
and between the ponds. This behavior of the frogs has high accuracy in
searching the best solution over other methods.
Similar to jellyfishes, the salps are moving towards the front by pump-
ing the water back. Due to its unique swarming nature, it is found in deep
oceans and forms a swarm called a chain [20]. The entire inhabitants are
divided into leaders and supporters. The frontrunner is leading the salp
chain and the remaining are the members in the followers. They move to
find food in the shortest path, hence its position and velocity are presumed
as the decision variables. This algorithm is implemented in [21] for DG
location and rating, thereby reducing the true power loss and operating
cost of the utility grid. A mutated salp swarm algorithm is adopted in [22]
for the distribution of real and reactive power sources in RDN.
A bacterial forging (BFOA) optimization algorithm uses the group for-
aging of swarms of Escherichia coli bacteria which is present in human
intestines [23]. The bacterium sends signals to other bacteria for commu-
nication and it makes the decision by considering the factors. The chemo-
taxis process helps to take steps in the search space and it is more effective
than other methods. In each location, the fitness value is calculated and
analyzed. The main process involved in this algorithm is swarming, repro-
duction, chemotaxis, and dispersion and it uses the friendly movement of
the bacteria at a longer distance.
Cuckoo search follows the removal of bad eggs in a nest. A good solu-
tion is the eggs of cuckoos and it is carried to the next generation. Cuckoos
are laying their eggs in other birds’ nests and remove the eggs in that nest.
Sometimes, female cuckoos produce eggs with various patterns and colors
of the host species. To avoid loss of the eggs due to the host birds, these
cuckoos lay their eggs in the nest in which the bird simply puts in its eggs
and takes care of them. Immigration of cuckoos is chosen as the variable
for the optimization problems [24] and this algorithm is adopted in vari-
ous fields such as nurse scheduling for duty allocation, the traveling sales-
man problem for finding the shortest path, etc.
Invasive weed optimization emerges from the inspiration of weed
growth which is heavier than other plants. This growth is a harm and
threat to the other plants. These weeds have good stability and adaptability.
Attacking weeds use the sources available in the field and grow new weeds.
Based on the qualification of the value, weeds are ranked and form a colony
[25]. The plants with less rank are eliminated from the competition and the
surviving plants move to the next generation for production.
A stud krill herd algorithm is proposed by Gandomi and Alavi based on
the natural phenomenon in view of the biological process. The individual
is adopted to live in nature and it is evaluated by its movement, which is
forced by other individuals, its hunting behavior, and the unsystematic dis-
persion [26]. Based on the selection and crossover operators, the optimi-
zation is performed for obtaining the best fitness function. This has been
implemented in RDN for the DG placement to get minimum power loss.
The detailed presentation of a stud krill herd is explained in [Wang] for
various optimization problems.
The coyote optimization algorithm (COA) is based on the community
deeds of coyotes and its adjustment in nature. It differs from the grey wolf
algorithm in such a way that this COA gives the organization and com-
mon practice amongst the coyotes [27]. The improved version of COA is
implemented in [28] for the optimal installation of solar systems in RDN
for power loss reduction, reduced capacity, improved voltage profile, and
minimized harmonic distortion.
Based on hybrid optimization algorithms of salp swarm and whale algo-
rithms, multi-DG’s are placed at optimal locations with an optimal rating
in 13 and 123 node RDN. The software named OpenDSS engine has been
adopted to find the power flow parameters [29]. Reactive power dispatch
has been done optimally to minimize the real power loss, minimize the
voltage deviation, and enhance the stability of the voltage using an artificial
Bee colony algorithm in [30].
For voltage profile improvement, the optimal reconfirmation has been

proposed in [31] using the modified selective PSO, keeping various loading
situations. The algorithm is tested in an IEEE 33 system and it is observed
that this proposed modified algorithm has significant reduction in real
power loss by increasing the minimum voltage profile. In [32], the mixed
algorithm of binary PSO and shuffled frog leap has been proposed for the
power loss reduction on 33 and 69 bus systems. Reconfiguration has also
been developed with same hybrid algorithms for voltage improvement and
cost saving objectives.
Wind energy is being considered as an addition to DG in the radial
distribution networks to reduce the power loss, taking the factors of kernel
density estimation and Monte Carlo simulation, load demand and air den-
sity effect in an hourly manner, and modelling of single and multi-wake
methods [33]. The real time data is taken for the wind system data and the
various wind systems are connected for the wake losses method. This has
been done in IEEE 28 and 69 radial distribution networks.
In [34], wind farms running with doubly fed induction generators are
taken for the power loss minimization system. The losses of all the compo-
nents in the systems including generators, filters, and power converters are
also considered and the objectives are solved using the distributed optimal
reactive power control method. The alternating direction method of multi-
pliers is used for solving the control objectives. The optimal DG placement
problem has been sorted out using a new algorithm called chaotic maps
integrated stochastic fractal search in [35] implemented in 33, 69, and 118
networks which is mentioned in appendix with Figure 22.1A, Figure 22.2A
and Figure 22.3A respectively. Various constraints such as real and reactive
power balance, voltage limits, current limits, capacity limits of DGs, power
factor limits, location of the DG, and penetration levels of DG are consid-
ered for the objective function.
For the reconfiguration to reduce the power loss, the improved selective
binary PSO is proposed for 33 and 94 node distribution systems by taking
the activation function as a square of the branch current and the resistance
of the line [36]. Radiality structure has been considered as one among
the constraints. Adopting teacher learning based optimization (TLBO)
for placing the energy storage systems for enhancing the reliability of the
radial network has been proposed in [37] considering 30 and 69 bus sys-
tems. The results are being compared with other popular techniques to
prove the validity of the proposed algorithm.
The capacitor placement of multi-period based switchable has been pro-
posed in [38] for energy loss reduction and to improve the voltage profile.
The factor of number of segments is being considered for the yearly loss
calculation. The popular load flow methods such as direct load flow and
backward/forward sweep have been adopted and tested in 10 bus, 33 bus,
69 bus, and 85 bus systems. An adaptive PSO and modified gravitational
search algorithm have been implemented for the single and multi-objective
DG placement for a unity power factor and optimal power factor [39].
For compensation of the reactive power of the distribution systems,
DGs and shunt capacitors have been added in the optimal location with
optimal size in [40]. The method of mutated salp swarm algorithm has
been adopted to stray away from local minima and to increase the popula-
tion and this has been tested in 33 and 69 distribution systems. The hybrid
classical and metaheuristic algorithms of SQP and PIPSO have been imple-
mented in [41] for power loss reduction with voltage improvement. The
SQP, which runs on quadratic programming, is more sensitive to initial
value selection. Hence, parameter improved PSO has been implemented
first and the results are taken as the initial values for the SQP algorithm,
thereby the losses are reduced. Active power filters have been adopted for
harmonics reduction using an extended non-linear load position based
APF current injection algorithm in [42]. Considering three cases, the size
and cost of APF is determined using a grey wolf algorithm and tested in a
69 bus system.
In a similar way, there are many such optimization algorithms such as
harmonic search, artificial bee colony, ant colony, plant growth simulation
algorithm, differential evolution, artificial immune systems, flower polli-
nation, paddy field algorithm, fish swarm algorithm, intelligent water drop
algorithm, firefly algorithm, and fireworks that have been planned for the
loss decrease problem in RDN.
To validate the optimization algorithms in the practical case, various
test systems are being considered. Most of the algorithms have been tested
in these systems and the results are related with the results and/or other
algorithms to propose superiority over other methods. The structure and
the line details are presented at the end of the chapter for understanding
the RDN system.
22.5 MATLAB Tools for Optimization Techniques

The optimization algorithms presented in the previous section have been
implemented in MATLAB by writing the logic as coding. In order to sim-
plify the burden on the researchers, popular conventional techniques are
developed as tailor made functions and implemented in MATLAB as read-
ily available.
In MATLAB, an optimization tool is available under the APPS option.

This could be opened either by directly clicking on the optimization icon in
the tool bar or we can type ‘optimtool’ in the command window. Recently,
MATLAB has introduced an alternative for an optimization app, which
can be opened using new live script and one has to set the options about
the solver and all.
Since there are many objectives to be attained for a single optimization
problem, a multi-objective optimization problem is chosen in some cases.
In the MATLAB toolbox, the following functions are available. For all the
functions, the equality and inequality constraints have to be entered as a
matrix in A or B for inequality linear constraints and Aeq or Beq for equal-
ity linear constraints. Also, the upper and lower limits have to be speci-
fied. It is preferable to specify the initial values for the variables. For some
specific functions, the nonlinear constraints are to be given as a separate
function. The entire m file and the corresponding constraint functions are
to be saved in the same running folder.
1. fmincon – Constrained nonlinear minimization – This is for

the minimization of an objective function with constraints.
In this, various methods can be employed such as interior
point, trust region, sequential quadratic programming, and
the active set method.
2. fgoalattain - mMultiobjective goal attainment – This func-
tion is defined for solving multi-objective optimization
problems.
3. fminbnd - Single-variable nonlinear minimization with
bounds - This has a single objective function with the left
and right end points specified.
4. fminmax - Minimax optimization - It is used to find the
minimum of a set of multi-variable functions.
5. fminsearch - Unconstrained nonlinear minimization -
This function is used without constraints for nonlinear
minimization.
Similarly, there are many such defined functions available in the opti-
mization toolbox. The evolutionary algorithms such as GA and simulated
annealing are defined in this tool box. Some sample programming is given
in this chapter for understanding the function and the constraints.
Considering the linear programming with three variables x, y, and z,
Minimize f=7x-3y+8z
Subject to the inequality constraints

2x+4y≥ 5
3x-z ≤8
and equality constraints
4x-y+z=20
The solution for the above linear programming with the constraints is
60 at the 7th iteration.
Similarly, consider the given objective function chosen as
Minimize f(x) = 5x2 + 20 cos (2x)
Using genetic algorithm, one can find the fitness value using this tool-
box as -9.04 at the 5th iteration.
Since the chosen power loss minimization objective function is qua-

dratic in nature, the quadratic function is considered as follows, the value
is 0.5, and it shows that it is non-convex.
Quadratic programming
1
minimize f ( x ) = x12 − 2 x 22 + 4 x1x 2 − x1 + 3x 2
2
Subject to the constraints
x1 – 3x2 ≤ 5;
–2x1 + 4x2 ≤ 6;
H= [1 -4; -4 4]; f=[-1; 3]; A=[1 -3; -2 4]; B=[5;6];

In the same way, after identifying the objective function and the con-
straints, the values should be entered in the toolbox in the specified loca-
tions and the simulation should be run.
22.6 Conclusion
In this chapter, the concept of a radial distribution network and its asso-
ciated active power loss in the RDN is discussed. The various load flow
methods adopted in RDN are presented. The review of various methods
of power loss minimization such as capacitor placement, DG placement,
and feeder reconfiguration are referred from the literature. The need for
obtaining the best location and optimal rating is discussed in the previous
section. Conventional and evolutionary optimization algorithms and their
origins are elaborated in the chapter to get a nutshell of the algorithms. In
the last section, the optimization tools available in MATLAB are discussed
by taking some examples to understand the way of entering the functions
and the constraints with the initial values appropriately.
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Appendix
01
02
19
03
20
04 23
21 05 24
22 06 25
07
08 26
09 27
10 28
11 29
12 30
13 31
14 32
15 33
16
17
18
Figure 22.1A Single line diagram of IEEE 33 system.
39 40 41 42 43 44 45 46
38
37
36 47 48 49 50 52 67
51 66
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16
28 17
57
29 56 55 54 53 68 69 18
58
30 19
59
31 20
60 61 62 63 64 65
32 33 34 35 27 26 25 24 23 22 21
Figure 22.2A Single line diagram of IEEE 69 bus system.

12 13 14 15 16 17
10 11
18 19 20 21 22 23 24 25 26 27
2
4 5 6 7 8 9
3
30 38 39 40 41 42 43 44 45 46
28 29 31 32 33 34 35 47 48 49 50 51 52 53 54
36 37
55 56 57 58 59 60 61 62
1
96 97 98 99
89 90 91 92 93 94 95
64
63 65 66 67 68 69 70 71 72 73 74 75 76 77
78 79 80 81 82 83 84 85
86 87 88 112
100
101 102 103 104 105 106 107 108 109 110 113
111
114 115 116 117 118
Figure 22.3A Single line diagram of IEEE 118 bus system.

23
Passivity Based Control for
DC-DC Converters
Arathy Rajeev V.K. and Ganesh Kumar S.*
DEEE, CEG Campus, Anna University, Chennai, Tamil Nadu, India
Abstract
The control of an electrical drive system plays a vital role in our day to day life.
The total energy of a system is the algebraic sum of stored energy and dissipated
energy in the system. We could control the system by adjusting the dissipated
energy in the system by injecting damping to the system. This control is known
as passivity based control. The system should be passive in nature to apply this
control. On an analogous, 90% of the physical system in the world is passive. In
this chapter, we discuss how to apply passivity based control to an electrical drive
system step by step. The control law is generated for three considered cases and
sensitivity analysis is done in MATLAB for finding the sensitive parameters in a
DC drive system.
Keywords: DC-DC converters, Lyapunov’s stability, passivity based control
23.1 Introduction
Power converters are widely used for the conversion of electrical energy of
one form to another. These converters control the flow of energy [1]. The
control of converters can be effectively done by representing the system in
Euler-Lagrange form. The method of passivity based control (PBC) is an
energy-based method of control. As a sum of stored energy and dissipated
energy, the total energy of the system is expressed. This method deals with
the shaping of energy, as well as the injection and tracking of damping,
which is done via the Hamiltonian operator. Control based on passivity
681
is defined by satisfying the matching condition of dissipated energy. The

basic development of control law using PBC for DC-AC converters is dis-
cussed in this chapter. The stability of the system is physically related to the
energy storage and dissipation that occurs in the system. This energy dissi-
pated from the elements should be shaped using power converter circuits
in such a way that the system becomes stable throughout the operating
cycle. The control method which does this process is said to be dissipativ-
ity based control or passivity based control [2]. This control uses electrical
parameters as references to the controller. In this methodology, the closed
loop system is made passive and oscillations in the system are suppressed
by injecting damping constants. The rate of damping injection is based on
the nature of the load and the type of oscillation. Systems are modeled
in terms of conservative forces, dissipative forces, and elements of energy
acquisition in PBC. The error in energy satisfies Lyapunov’s stability and
dissipation matching condition for the control function of PBC for any
system [3].
Control and stability of nonlinear systems is a significant field in engi-
neering as practically all systems have nonlinearity. Hysteresis nonlinearity
is the capacity of the system to memorize the previous outputs. In electro-
mechanical systems the reverse in current in an actuator also requires an
extra current to reverse the field. This results in hysteresis loops and the
area of this loop is directly proportional to energy lost to the device. This
energy interpretation of the system can provide the maximum variation of
gain possible in a system before going unstable [3]. As energy is one of the
fundamental concepts, the control has a wide area of application. Here, we
talk about applying the control for electrical systems, mainly DC drives.
The energy shaping method is well known in mechanical systems. Here,
the nonlinearity is converted to a passive operator that controls the energy
lost by the device.
A DC motor’s feedback control is achieved through the DC-DC con-
verter’s pulse width modulation (PWM). An average small-signal model
controlling DC-DC converters supports the application of linear control
theory [4], which produces satisfactory results in many applications. In
certain cases, this approach offers minimal performance or may even fail.
During sudden load changes, such situations can involve tight monitor-
ing of the reference voltage. This kind of issue [4] would be alleviated by
passivity-based regulation. It is based on measurements of the energy in
the device. If any system’s model is converted to its energy outlook, it is
easy to enforce PBC. Based on the required reference trajectories, PBC is
designed to achieve stabilized performance trajectories.
Passivity Based Control for DC-DC Converters 683
In motorized seatbelt systems, wearable exoskeletons, robots, and bat-

tery-powered vehicles, load torque estimation of the DC motor is essential.
The torque sensor is eliminated due to the knowledge of the inversion of
the plant model and the load torque estimation is successfully completed
[5]. Estimating the load torque of the DC motor using the online alge-
braic approach is now gaining more interest because of its rapid estima-
tion without any tuning requirement and model inversion. As feedback
variables for estimating the load torque and speed, both armature current
and armature voltage are used. Torque can be estimated without a speed
sensor and therefore, the number of sensors is also reduced. Therefore, it is
proposed to implement online algebraic load torque estimation without a
speed sensor. In this scheme, speed is estimated using feedback variables,
such as armature current and armature voltage, through the correspond-
ing mathematical model. Because of the choice of the mathematical model
and its corresponding variables for speed estimation, the scheme can be
referred to as soft sensing [5], which is otherwise referred to as sensor-less.
23.2 Passivity Based Control

For power electronic circuits, passivity-based controllers are commonly
synthesized with a stability goal in mind, i.e., to achieve a constant output
voltage or a constant current in the branches of the circuit. Euler Lagrange
equations were previously used in this context to derive PBC in various
electronic power circuits and also in some mechanical systems [5]. In such
a way that the non-linear terms in the torque equations are eliminated, a
unified framework for the control of different DC motor configurations
using PBC was derived. For the switching function using PBC, fundamen-
tal equations are derived such that the tracking error can be stabilized to
zero.
Using mathematical modeling of electrical drives, the system has to
be represented by both mechanical and electrical subsystems. When the
output of a converter is connected to the machine, the number of vari-
ables that depend on the system stability increases. In other words, the
system is more complicated depending on the controllability [6]. The feed-
back decomposition of a general electrical drive system is represented in
Figures 23.1 and 23.2. The parameters controlling the physical system are
represented in the figure. Usually, the electrical parameters that control a
converter are the current in inductor and capacitor voltage. The motor is
controlled by speed which is related to input voltage and load torque which
is related to current [7].
V
Electrical Subsystem
TE
Mechanical Subsystem
θ, ω – TL
Figure 23.1 Feedback decomposition block diagram.
U1 e1 y1
H1
y2 e2 U2
H2
Figure 23.2 Passivity analysis system.
The passivity based control technique is an energy based control tech-

nique where the system should be passive in nature. The above figure rep-
resents a Lur’e type system where both outputs are products of Hamiltonian
and error, which can be mathematically expressed by the equations as
follows:
y1 = H1 ∗ e1 = H1(u1 – y2) (23.1)
y2 = H2 ∗ e2 = H2(u2 – y1) (23.2)
In the above system, if U2=0, H1 is passive and H2 is strictly passive, this

means any system is passive if it is free from external disturbance param-
eters influencing the output of the entire system. This theorem should be
verified before applying the control. In the case of power electronic con-
verters, they are strictly passive in nature [8].
For power converters, the formation considers the following behaviour
traits such as:
1. It is possible to define conservative forces by the product

of skew symmetry and state vector. In the system’s stability
consideration, the skew symmetry matrix does not arbitrate.
2. The product of a constant symmetric positive semi-definite
matrix and state vector can be defined by dissipative forces.
This force appears in the system due to the resistances and

friction of the system.
3. The control inputs can be formulated from a constant matrix
multiplying with the input vector.
4. The external forces are signified by a time varying or alterna-
tively constant vector field.
In PBC, conservative forces, dissipative forces, and energy acquisition

elements play a key role during modeling given in Figure 23.3. The energy
error should satisfy Lyapunov’s stability and dissipation matching condi-
tion for the control function of PBC for any system [9]. The passivity based
control can be accomplished by many methods like:
1) Energy shaping damping injection method (ESDI)

2) Exact tracking error dynamics passive output feedback
method (ETEDPOF)
3) Exact static error dynamics passive output feedback method
(ESEDPOF)
System selection
Flat N
?
Indirect reference
Y
profile generation
Direct reference
profile generation
PBC
PBC
Control input to plant
Control input to plant
Figure 23.3 General flowchart for PBC.

23.3 Control Law Generation Using ESDI, ESEDPOF,

ETEDPOF
23.3.1 Energy Shaping and Damping Injection (ESDI)
To verify the system stability, it should satisfy Lyapunov’s stability the-
ory. To make the system stable, the incremental energy should be zero.
To achieve the same, we inject damping to the system. This is an output
feedback dynamic controller that enhances the closed loop energy. ESDI
method is the very basic method of PBC, which is an output feedback con-
troller [2].
Considering a linear time invariant controllable single output system,
such as
Pẋ(t) = (J – R)x(t) – bu (23.3)
where J is skew symmetric and R is symmetric in nature. Now, the desired

system can be represented by
ẋ*(t) = (J − R)x*(t) + R1(x – x*) + bu (23.4)
Here, a damping factor R1 is added to the system matrix which depends

on the tracking error in the system. The damping factor injects the error
to the system to minimize or maximize the stored energy in the system to
the desired value where, R + R1 > 0. From the above equation, the control
law can be derived as
bT
u = T ( Px *(t ) − ( J − R )x *(t ) − R1 ( x − x *)) (23.5)
b b
Considering the Hamiltonian operator, the state space equation will be

modified as follows:
∂H
x (t ) = ( J − R ) − bu (23.6)
∂x
∂H
y = bT (23.7)
∂x
The control law generated from the above equation can be given as
∂H
u = −γ bT = −γ y (23.8)
∂x
From the above control law it is clear that PBC is an output feedback
controller.
23.3.2 Exact Tracking Error Dynamics Passive Output

Feedback (ETEDPOF)
In this method, the average system model differentiates the stabilization
error exact dynamic model. The energy management structure of the
error dynamics is demonstrated in a generalized Hamiltonian form. So,
the passive output is associated with the error dynamics [10]. These error
dynamics are identified by a time invariant feedback controller. If the dis-
sipation matching condition is satisfied, then the equilibrium point will be
a semi-globally asymptotically stable equilibrium for a closed loop system
[11–13].
The Hamiltonian of the physical system symbolizes the energy function
(H) and is written including the state vector ‘x’, which can be expressed as:
1
H = xMx T (23.9)
2
where M is a constant and positive definite matrix. The partial derivative of

Equation (23.9) with respect to ‘x’, gives Equation (23.10) as:
T
 ∂H 
  = Mx (23.10)
∂x 
Generally, any averaged state model can be represented as:
T
 ∂H(x) 
 = (J(u) − R)
x(t) + bu + ∈ (23.11)
 ∂ x 
Matrix J is skew-symmetric in nature, which will not affect system sta-

bility, as:
xTJ(u) x=x J(u) xT=0 (23.12)
The term ‘bu’ is the energy acquiring term. External disturbances such
as load torque, etc. are introduced in ′∈′. R is symmetric and positive
semi-definite, i.e.,
RT = R ≥ 0 (23.13)
It is possible to express the J(u) skew symmetry matrix as:
J(u) = J0 + J1u (23.14)
The desired machine profile is achieved using Bezier polynomials in

an offline fashion. For this required system profile, it is assumed that the
desired open-loop dynamics should be convinced by a state reference tra-
jectory x*(t) and it is defined by:
T
 ∂H(x*) 

x*(t) = (J(u*) − R) + bu*+ ∈* (23.15)
 ∂ x* 
The matrix J(u) is skew-symmetric, which is related to an average con-

trol input ‘u’ and it satisfies the following expansion property:
∂J(u)
J(u) = J(u*) + (u − u*) (23.16)
∂u
∂J(u)
where is a skew-symmetry constant matrix.
∂u
Under steady-state conditions, state trajectory ‘x’ will reach x* and con-
trol input ‘u’ becomes u*. Now, Equation (23.15) is customized to:
T
 ∂H(x*) 
0 = [J(u*) − R] + bu*+ ∈ (23.17)
 ∂ x* 
Errors in the system’s state trajectories should be detected to adjust the

control input in order to enforce a closed-loop process. These errors in the
trajectory of state (e) and input of control (eu) are determined as follows:
T
 ∂H(e) 
e = x − x*  (23.18)
 ∂e 
eu = u − u* (23.19)
On differentiating Equation (23.18) with respect to time ‘t’:
ė=ẋ (23.20)
Adding and subtracting the required steady-state values to Equation

(23.20) yields:
T T
 ∂H(e)   ∂H(x*) 
e = [J(u) − R] + be u + ∈+[J(u) − R] + bu* (23.21)
 ∂e   ∂ x* 
If the value for ∈ obtained from Equation (23.17) is substituted in

Equation (23.21), then the error dynamics will become:
T T
 ∂H(e)   ∂H(x*) 
e = [J(u) − R]  + be u + [J(u) − J(u*)] (23.22)
 ∂e   ∂ x* 
On using Equation (23.15) in Equation (23.22), error dynamics of the

system is modified into:
∂H(e)    ∂J(u)   ∂H(x*)   

T T

e = [J(u) − R] + b+ e
 ∂e    ∂u   ∂ x*    u
(23.23)
T T
 ∂H(e)   ∂H(e)  ∨
e = [J(u)  −R  + be u (23.24)
 ∂e   ∂e 
where
∨   ∂J(u)   ∂H(x*)  T  
b = b +      (23.25)
  ∂u   ∂ x*   
T
 ∂H(e) 
The “J(u) ” is a conservative term which will not affect the
 ∂e 
stability property of the system:
T
 ∂H(e)   ∂H(e) 
  J(u)  =0 (23.26)
∂e ∂e 
The other remaining terms exactly coincide with the tangent lineariza-
tion part of the dynamics.
The passive output tracking error is given by:
T
∨  ∂H(e) 
e y = y − y* =b T (23.27)
 ∂e 
A linear time-varying average incremental passive output feedback con-

troller is simply given by:
T
∨  ∂H(e) 
e u = −γe y = −γ bT  (23.28)
 ∂e 
When substituting Equation (23.20) in Equation (23.16), the error

dynamics of the system will become:
T T T
 ∂H(e)   ∂H(e)  ∨ ∨  ∂H(e) 
e = J(u) −R − b γ bT  (23.29)
 ∂e   ∂e   ∂e 
T T
 ∂H(e)  ∨ ∨  ∂H(e) 
e = J(u)  − (R + b γ bT ) (23.30)
 ∂e   ∂e 
Now, with the skew symmetry property of J(u), Ḣ(e) is given by:
T
 = −  ∂H(e)  R
H(e)   ∂H(e)  < 0 (23.31)
 ∂e   ∂e 
Equation (23.23) is negative definite if dissipation matching condition

(23.24) is satisfied.
 = (R + b∨ γ b∨ T )
R (23.32)
The fulfilment of the matching state of dissipation will usually be in two

ways and both forms are explained below:
Case I: R >0
This means that it is strictly satisfied with the dissipation matching con-
dition and Equation (23.26) will become a negative definite.
Case II: R  ≥0
Here, the condition of dissipation matching is not strictly met. LaSalle’s
theorem [10–12] is used in these cases to evaluate the global asymptotic
stability of the origin of the tracking error space.
According to the theorem of LaSalle, the following conclusions can be
drawn as follows:
Suppose that there is a positive definite function, H: RnàR, whose deriv-
ative satisfies the inequality Ḣ ≤ 0 and, in addition, if the largest invariant
set found in the set {x: Ḣ = 0} is equal to {0}, then the system is globally
asymptotically stable. The machine can be semi-globally asymptotically
stable due to the boundary existence of control input [0 and 1] in the power
electronic converters.
Now, the condition of dissipation matching and the average control
input are given by:
T
  ∂J(u)   ∂H(x*)  T    ∂J(u)   ∂H(x*)  T 
∨ ∨
T 
(R + b γ b ) = R = R +  b +     γ b +    
  ∂u   ∂ x*     ∂u   ∂ x*  
(23.33)
T
∨ ∂H(e)  ∨
u = u* −γ b  T
 = u* −γ bT Me (23.34)
 ∂e 
where ‘γ’ represents the coefficient of damping injection whose value can
be considered low to prevent amplification of noise.
The control input to regulate the speed of the DC motor is therefore
obtained. In Equation (23.34), the control function (u) clearly indicates the
absence of a derivative term, which simplifies the controller [4].
S L Rm Lm
i iam
Rfm
E D M
C v J
Ef
Lfm
ω* ω
i
v
u
CONTROLLER
Figure 23.4 Exact tracking error dynamics passive output feedback (ETEDPOF) control
of buck converter.
23.3.3 Exact Static Error Dynamics Passive Output Feedback

This method is comparable to the aforementioned method by which the
controller is derived by identifying the passive output static error dynam-
ics. In this method, the control law consists of no derivative terms. This
control can be implemented by systems where accuracy is not a concern.
The control law is the same as that of ETEDPOF, but the dynamic terms
become null during reference profile generation shown in Figure 23.4.
23.4 Control Law Generation Using ETEDPOF

Method for DC Drives
23.4.1 Buck Converter Fed DC Motor
The average model of the buck converter-fed DC motor is developed using
the ETEDPOF method [5] and is given in Equations (23.35)–(23.38)
di
L = − v + uE (23.35)
dt
dv
C = i − i am (23.36)
dt
di am
Lm = v − R mi am − kω (23.37)
dt
dw
J = ki am − Bω − TL (23.38)
dt
The state vector when the above equations are written in matrix form is:
x(t)T = (i, v, iam, ω) (23.39)
 −1 
 0 0 0 
 L     0 
 x 1 (t)   1 −1   x1   E   
   0 0   L   0 
 
x (t)   C C x 
2
 2 + u+  0 
 x 3 (t)  =  1 − Rm −k   x3   0  
0   


x (t)
 
L L L   x   0   −TL 
 4   m m m
  4   0   J 
k −B     
 0 0
 J J 

(23.40)
where
k—Torqueconstant (N.m/A)
L—Inductance of buck converter (henry)
C—Capacitance of buck converter (farad)
Rm—Armature resistance of motor (Ohm)
Lm—Armature inductance of motor (henry)
u—Average input for control
i—Current input (ampere)
v—Armature voltage or output converter voltage (volt)
 2πN 
ω—Angular velocity of motor 
 60 
TL—Torque produced by load (Nm)
iam—Armature current of motor (ampere)
N—Speed of the motor (RPM)
J—Inertia of motor (kg.m2)
B—Coefficient of friction (Nms)
E—Voltage input (volt)
The buck converter-fed DC motor model shown in the above equation

demonstrates that it is a system of conservative and dissipative forces for
energy management. Since ETEDPOF includes energy-based operations,
further modification of Equation (23.40) in terms of energy function is
mandatory and can be rewritten as:
T
 ∂H(x) 
 = [J − R]
x(t) + bu + ∈ (23.41)
 ∂ x 
where
T
 ∂H(x) 
  = Mx ; (23.42)
∂x 
Matrix M is given by:
 L 0 0 0 
 
0 C 0 0
M=  (23.43)
 0 0 Lm 0 
 0 0 0 J 
 
The matrices ‘b’ and ‘ϵ’ are given by:
E
bT =  , 0, 0,0  ; (23.44)
L 
−T
∈T = 0,0,0, L  (23.45)
 J 
and the matrices J and R are given by:
 −1 
 0 0 0 
 LC 
 1 −1 
 LC 0 0 
LmC
J=  (23.46)
 1 −k 
 0 LmC
0
JLm 
 
 k 
 0 0
JLm
0 
 
 0 0 0 0 
 
 0 0 0 0 
 Rm 
R= 0 0 0  (23.47)
L2m
 
 B 
0 0 0
 J2 
 
The matrix ‘J’ is independent of ‘u’ and it is of skew-symmetry in nature.

Matrix R is symmetric and positive semi-definite:
RT =R ≥ 0 (23.48)
As a result, the modified average buck converter-fed DC motor model is

achieved through fundamental principles of the system’s energy manage-
ment structure. This derived model may be used under no load and loaded
conditions in the deriving control law using the ETEDPOF control for a
buck converter-fed DC motor. ETEDPOF control is essential for speed
regulation and it is developed on the basis of error stabilization dynamics,
which are further discussed. For speed regulation, load torque estimation
is essential under loading conditions.
The primary purpose of the current work is to control the speed of a DC
motor under no-load and load conditions for a given speed profile (ω*).
In an offline method with Bezier polynomials, the desired speed profile is
acquired. The control function (u) is developed by following the procedure
discussed earlier.
γE
u = u* − (i − i*) (23.49)
L
where the constant ‘γ’ is termed as the damping injection coefficient and
must be > 0.
In this case, the dissipation matching condition is verified using
Equation (23.32). Final dissipation matching matrix 2Ř for the buck con-
verter system is specified by:
 γ E2 
 2 0 0 0 
 L 
 0 0 0 0 
R =  Rm ≥0

(23.50)
0 0 0
 L2m 
 B 
 0 0 0 
 J2 
It is realized that the Ř matrix is not strictly satisfying the dissipation

matching condition. Hence, the control law makes the origin of error space
as an asymptotically stable equilibrium point by virtue of LaSalle’s theorem
[13].
To verify the stability of the system stability using LaSalle’s theorem:
T
 = −  ∂H(e)  (R)
H(e)   ∂H(e)  (23.51)
 ∂e   ∂e 
T
 ∂H(e) 
It is known that  = Me. Substitute Equation (23.49) and
T  ∂e 
 ∂H(e) 
  in Equation (23.50), then Ḣ(e) ≤ 0. Ḣ(e) can be obtained by
∂e 
substituting the required matrices in Equation (23.50) and it is given by:
 = −( γe12 E 2 + e32R m + e 24B)

H(e) (23.52)
When Ḣ(e) = 0 and if errors e1, e3, and e4 become zero, then ė1 = ė3 = ė4 = 0.
On substituting these values in Equation (23.24), e2 = 0. Hence, the error
dynamics of the system converges to zero and the system becomes globally
asymptotically stable by virtue of LaSalle’s theorem. As the control input is

bounded in nature [i.e., 0, 1], system stability is not global.
In Equation (23.49), the inductor current plays a significant role in con-
trol operation, and hence, it can be articulated as the more sensitive variable.
This sensitive nature of the inductor current is investigated in the coming
section. Equation (23.49) points towards the control input derived using
the ETEDPOF method. This control law makes the system semi-globally
asymptotically stable for a given or desired speed profile (ω*).
23.4.2 Boost Converter Fed DC Motor

ETEDPOF implementation with ω* as the desired speed profile use the
armature voltage (v) and boost inductor current (i) as feedback signals is
shown in Figure 23.5. Using Kirchhoff ’s laws and Newton’s laws, the aver-
age model for a boost converter-fed DC motor can be obtained and is
expressed as:
di
L = −(1 − u)v + E (23.53)
dt
dv
C = (1 − u)i + i am (23.54)
dt
L D Rm Lm
i
iam
E S
M J
C v
i iam
v
u
ω*
CONTROLLER
Figure 23.5 ETEDPOF control of boost converter.

di am
Lm = v − R mi am − kω (23.55)
dt
dw
J = ki am − Bω − TL (23.56)
dt
Equations (23.53)–(23.56) can be written as below:
 −(1 − u) 
 0 0 0 
 L   E 
 x 1 (t )   (1 − u) −1   x1   L 
   0 0    
 x 2 (t )  =  C C x
 2 +  0 
 x 3 (t )   1 − Rm −k   x3   0 
   0   x   −TL 

x (t ) L L L
     4   
4 m m m
 k − B   J 
0 0  
 J J 
 
(23.57)
with the state vector
x(t)T = (i, v, iam, ω) (23.58)
where
L—Inductance of converter (H)
C—Capacitance of converter (F)
Rm—Armature resistance of motor (Ohm)
Lm—Armature inductance of motor (H)
u—Average control input
i—Current input (A)
v—Converter output voltage or Armature voltage (V)
By the Hamiltonian operator, the state space equation can be given as

follows:
T
 ∂H(x) 
 = [J(u) − R]
x(t) +∈ (23.59)
 ∂ x 
where
T
 ∂H(x) 
  = Mx ; (23.60)
∂x 
Matrix M is given by:
 L 0 0 0 
 
0 C 0 0
M=  (23.61)
 0 0 Lm 0 
 0 0 0 J 
 
The matrix ϵ is given by:
E −T
∈T =  ,0,0, L  (23.62)
L J 
and the matrices J and R are given by:
 −(1 − u) 
 0 0 0 
 LC 
 (1 − u) −1 
 LC 0 0 
LmC
J=  (23.63)
 1 −k 
 0 0 
LmC JLm
 
 k 
 0 0 0 
 JLm 
 0 0 0 0 
 
 0 0 0 0 
 Rm 
R= 0 0 0  (23.64)
L2m
 
 B 
0 0 0
 J2 
 
Thus, the average model of a boost converter-fed DC motor is changed

based on the energy management formation. By following the procedure
explained in previous Section (23.3.2), a natural feedback control law may
be written as:
u = u* − γ(iv* − vi*) (23.65)
where the constant ‘γ’ must be > 0. Here, the dissipation matching condi-
tion is strictly satisfied and the final matrix is given by:
 *2 
 γ x22 γ x1* x 2* 
− 0 0
 L LC 
 * * 2 
 − γ x1 x 2 γ x1* 
0 0
R =  LC C2 >0
 (23.66)
 Rm 
0 0 0
 L2m 
 B 
 0 0 0 
 J2 
 is a positive definite matrix.

R
Since R is positive definite whenever t ≥ 0, the origin of the error space
is asymptotically stable. As the control input is in a bounded nature of
u between 0 and 1, the result is not global [14]. When ‘u’ semi-globally
reaches to u*, output voltage, current of the boost converter, and speed of
the motor will attain stability.
23.4.3 Luo Converter Fed DC Motor

For the analysis, which is the luo converter-fed DC motor, a sixth-order
non-flat system is derived in this section. The luo converter-fed DC motor
has three relative degrees, which is less than the system order. This vali-
dates the unstable internal dynamics of the luo inductor converter current
and the voltages of the capacitor that are related to velocity. Reference tra-
jectories are therefore derived in an indirect way [15].
Figure 23.6 embodies the luo converter with a dynamic load for
ETEDPOF implementation. ETEDPOF can be realized with inductor cur-
rents (i1 and i2) capacitor voltage (v1).
For the current work, a primary positive output luo converter is taken
with the available wide variety of pump circuits. A linear average model
for a Luo converter feeding DC motor can be developed using Kirchhoff ’s
laws and Newton’s laws. Field circuit equations are absent because of the
choice of the armature control method for speed control. The linear aver-
age model that was developed is provided by:
di1 uE (1 − u)
= − v1 (23.67)
dt L1 L1
di 2 uE uv 1 v 2
= + − (23.68)
dt L 2 L 2 L 2
S C1 L2
i2 Rm Lm
iam Rfm
v1
E D C2 v2 M J
L1 Ef
l1
Lfm
ω
i2
v1
i1
ω*
u CONTROLLER
Figure 23.6 ETEDPOF control of luo converter.

dv 1 (1 − u)i1 ui 2
= − (23.69)
dt C1 C1
dv 2 i 2 i am
= − (23.70)
dt C 2 C 2
di am v 2 R m k
= − i am − ω (23.71)
dt Lm Lm Lm
dω k B T
= i am − ω − L (23.72)
dt J J J
where
i1—Input side inductor current (A)
i2—Output side Inductor current (A)
v1—Input side Capacitor voltage (V)
v2—Output side Capacitor voltage (V)
iam—Armature current of the motor (A)
u—Input control variable
E—Voltage supplied to the system (V)
Employing matrix notation with the aid of Hamiltonian system given in

Equation (23.11), with the state vector shown in Equation (23.73).
xT(t) = (i1, i2, v1, v2, iam, ω) (23.73)
and the matrices b, ∈, J(u), and R are given from Equation (23.74) to
Equation (23.77):
bT =  E L , E L , 0, 0, 0, 0  (23.74)
 1 2 
−T
∈T = 0 , 0 , 0 , 0 , 0, L  (23.75)
 J 
 −(1 − u) 
 0 0 0 0 0 
 L1C1 
 u −1 
 0 0 0 0 
 L 2C1 L 2C 2 
 (1 − u) -u 
 LC 0 0 0 0 
L 2C1
J(u) =  
1 1
 1 −1 
 0 0 0 0 
L 2C 2 L mC 2
 
 1 −k 
 0 0 0 0 
L mC 2 JL m
 
 k 
 0 0 0 0 0 
 JL m 
(23.76)
 0 0 0 0 0 0 
 
 0 0 0 0 0 0 
 0 0 0 0 0 0 
 0 0 0 0 0 0 
R=  (23.77)
 Rm 
0 0 0 0 0
 L2m 
 
 B 
0 0 0 0 0
 J2 
Matrix J is skew-symmetric in character. R is symmetric and also

positive–semi-definite, i.e.,
RT =R ≥ 0 (23.78)
The skew symmetry matrix J(u) can be given as
J(u) = J0 + J1u (23.79)

where J0 and J1 are skew symmetry constant matrices which are specified in
Equations (23.80) and (23.81)
 −1 
 0 0 0 0 0 
 L1C1 
 −1 
 0 0 0 0 0 
 L 2C 2 
 1 
 LC 0 0 0 0 0 
J0 =   (23.80)
1 1
 1 −1 
 0 0 0 0 
L 2C 2 L mC 2
 
 1 −k 
 0 0 0 0 
L mC 2 JL m
 
 k 
 0 0 0 0 0 
 JL m 
 1 
 0 0 0 0 0 
 L1C1 
 1 
 0 0 0 0 0 
 L 2C1 
J1 =  −1 −1  (23.81)
 LC 0 0 0 0 
L 2C1
 1 1 
 0 0 0 0 0 0 
 0 0 0 0 0 0 
 
 0 0 0 0 0 0 
The total stored energy of the system is prearranged as
1
H(x) = x T M x (23.82)
2
where the matrix ‘M’ is given by

 L1 0 0 0 0 0 
 
 0 L2 0 0 0 0 
 0 0 C1 0 0 0 
M=  (23.83)
 0 0 0 C2 0 0 
 0 0 0 0 Lm 0 
 
 0 0 0 0 0 J 
which is positive definite and constant. Thus, the average model of luo
converter-fed DC motor is obtained. The ETEDPOF control law can be
developed by replacing the necessary matrices in Equation (23.26) and it
is specified as follows:
u = u* + γ[v 1 i1* − v 1*i1 − v 1*i 2 + v 1 i *2 − E(i1 − i1* ) − E(i 2 − i *2 )] (23.84)
In the present scenario, the dissipation matching condition is not satis-

fied strictly and the final dissipation matching matrix is given by:
 2 2 
  E + x 3*   E + x 3*  γ ( E + x 3* )( x1* + x 2* ) 
γ  γ − 0 0 0
  L1   L1L2  L1C1 
 
  E + x 3* 
2
 E + x 3* 
2
γ ( E + x 3* )( x1* + x 2* ) 
 γ  γ − 0 0 0 
  L1L2   L2  L2C1 
 2 
 −γ ( E + x 3* )( x1* + x 2* ) γ ( E + x 3* )( x1* + x 2* )  x* + x*  
R =  − γ 1 2 0 0 0 ≥0
 L1C1 L2C1  C1  
 0 0 0 0 0 0 
 
 Rm 
0 0 0 0 0
 L2m 
 
 B 
0 0 0 0 0
 J2 
 
(23.85)
 is positive semi-definite whenever t ≥ 0, the control law (23.84)
Since R
makes the origin of error space an asymptotically stable equilibrium point
by virtue of LaSalle’s theorem.
Stability Proof of System:
Error dynamics in the luo converter and first derivative of energy can
be expressed as:
∂H(e)    ∂J(u)   ∂H(x*)   

T T

e = [J(u) − R] + b+ e
 ∂e    ∂u   ∂ x*    u
(23.86)
T
 = −  ∂H(e)  (R + b∨ γ b∨ T ) ∂H(e) 
H(e) (23.87)
 ∂e   ∂e 
and it is calculated as
 = −{γ[(E + x *3 )e1 ]2 + γ[(E + x *3 ]2 e1e 2 − 2 γ[(E + x *3 )(x1* + x *2 )e1e3 ]

H(e)
+ γ[(E + x *3 )]2 e1e 2 + γ[(E + x *3 )e 2 ]2 − γ[(E + x *3 )(x1* + x *2 )e 2e3 ]
+ γ[(x1* + x *2 )e3 ]2 + γR me5 + γBe6 } (23.88)

 = 0 and e = e = e = e = e = 0 → e = 0. This indicates that
when H(e) 1 2 3 5 6 4
LaSalle’s theorem is recognized and the origin of error space is globally
asymptotically stable. Therefore, due to the bounded nature of control
input between 0 and 1, the origin of error space is semi-globally asymp-
totically stable [15].
23.5 Sensitivity Analysis

In power systems, power electronics, and control engineering, sensitivity
analysis demonstrates an important role. Sensitivity is used in power sys-
tems to identify dominant parameters for slow oscillation generation [4].
More sensitivity provides better insights into the performance of the sys-
tem that cannot be obtained from conventional simulation [16].
Sensitivity is used in power electronics to decide the variation of the
state variable and steady-state determination [15]. In addition, sensitivity
analysis effectively calculates the tolerance region between the actual char-
acteristics and behavior acquired in a power electronic circuit through the
design process.
Sensitivity analysis is favored as a tool in the Posicast control of buck
converters and in optimal control due to the above-mentioned benefits [4].
Sensitivity is used in the continuity of this control engineering applica-
tion for the evaluation of various control techniques based on variations in
parameters. Sensitivity can be used in discrete systems in addition to these
applications to learn the local and global effects of discrete systems due to
disturbances in sampling frequency on system performance [17] and in
sampled systems.
It can be concluded from the above that sensitivity analysis is an import-
ant tool used in a variety of fields, such as power systems, power electronics,
control engineering, etc. To date, sensitivity analysis is rarely used to iden-

tify the more sensitive variables used in the control law of ETEDPOF and
the control law derived from ETEDPOF for fourth and sixth order systems
is discussed in this section. For power converters, sensitivity analysis can
be done by following the algorithm shown below.
Step 1: Recognize the output variable. In the current sce-

nario, it is the speed of the motor.
Step 2: Recognize the state variables of the physical system.
Step 3: Number of equations compulsory for analysis =
(Order of the system)-1
Step 4: Acquire the relation between output variable and
each state variable in the frequency domain. For a flat sys-
tem, developed expressions are attained in terms of con-
verter and motor parameters only. In contrast, for a partially
flat system, expressions will be in requisites of control input
in addition to converter and motor parameters.
Step 5: Discover the gain margin and phase margin values
for a range of values of load torque in the case of a flat sys-
tem. For a partially flat system, margin values get hold of
various values of load torque as well as various values of con-
trol input.
Step 6: Sensitive variables can be recognized based on the
margin values obtained through the aforementioned proce-
dure and it is discussed in the following subsections.
23.5.1 Sensitivity Analysis of Buck Converter

The order of the flat system here is four and three expressions are there-
fore developed, which are shown in Equations (23.89)-(23.91). The values
of the gain margin and phase margin are intended for transfer functions
obtained between ω(s)&iam(s), ω(s)&v(s), and ω(s)&i(s). From Equations
(23.89)-(23.91) for the load torque variations and based on the machine
specifications, both margins are obtained (Table 23.1). The negative mar-
gin values obtained for the inductor current are found to have gain and
phase margin values that make that variable more sensitive [4, 17].
i am (s) TL (23.89)
ω(s) = −
a1s + a 2 k(a1s 2 + a 2s)
708
Table 23.1 Sensitivity analysis for ETEDPOF control of buck converter-fed DC motor.
Armature voltage Armature current Inductor current
S. no. % Load torque GM (dB) PM (degrees) GM (dB) PM (degrees) GM (dB) PM (degrees)
1. 0 ∞ 9.88 ∞ 90.1 −97.4 −88.9
2. 0.1 ∞ 10.9 ∞ 90.1 −97.4 −88.9
3. 0.2 ∞ 11.9 ∞ 90.2 −97.4 −88.9
4. 0.3 ∞ 12.9 ∞ 90.2 −97.4 −88.9
5. 0.4 ∞ 13.9 ∞ 90.2 −97.4 −88.9
6. 0.5 ∞ 14.9 ∞ 90.2 −97.4 −88.9
7. 0.6 ∞ 15.9 ∞ 90.2 −97.4 −88.9
8. 0.7 ∞ 16.9 ∞ 90.2 −97.4 −88.9
9. 0.8 ∞ 17.8 ∞ 90.3 −97.4 −88.9
DC-DC Converters for Sustainable Applications
10. 0.9 ∞ 18.8 ∞ 90.3 −97.4 −88.9

11. 1.0 ∞ 19.7 ∞ 90.3 −97.4 −88.9
GM—gain margin; PM—phase margin; dB—decibel.
 R  
 TL m
 v(s)   k  
ω(s) =  2 −   (23.90)
 a 3s + a 4 s + a 5   a 3s + a 4 s + a 5 s 
3 2
  1 
 TL 
 i(s)   k 
ω(s) =  3 −   (23.91)
 a 6 s + a 7 s + a 8 s + a 2   a 6 s + a 7 s + a 8 s + a 2 s 
2 4 3 2
where
J B JL  BL m + JR m   BR m 
a1 = ; a2 = ; a3 = m ; a4 = ; a5 = +k ;
k k k  k   k 
CJL m  BL m + JR m   CBR m J
a6 = ;a 7 = C ; a8 = + Ck + .
k  k   k k
The above examination and expression (23.9) show that the inductor
current is more sensitive than other variables and that this sensitive variable
is inherently selected as a control variable in the ETEDPOF method [21].
23.5.2 Sensitivity Analysis of Boost Converter

For a flat system, previous sensitivity analysis is performed, whereas it is
complicated for a fourth-order partially flat boost converter with dynamic
load. For a partially flat system [40], both gain and phase margin values are
derived from the expressions (23.92)-(23.94) that are linked to input and
load torque control, whereas for a flat system referred to earlier, only load
torque is associated. For the specifications of the machine, margin values
are calculated along with load and controller input variations (u). It is clear
from the margin values obtained from the equations below that the sensi-
tive variable [17] is the inductor current shown in Figure 23.7.
v(s) R m TL
ω(s) = 2 − 2
(23.92)
a1bs + a 2bs + a 3b ks(a1bs + a 2bs + a 3b )
i am (s) TL
ω(s) = − (23.93)
a 4bs + a 5b ks(a 4bs + a 5b )
i(s) TL
ω(s) = −
(a 6bs + a 7bs + a 8bs + a 9b ) k(1 − u)s(a 6bs + a 7bs 2 + a 8bs + a 9b )
3 2 3
(23.94)
(a) PHASE MARGIN vs TL and u (b) GAIN MARGIN vs TL and u
0
Phase margin (degrees)
Gain margin (dB)

-10
-20
-40 -20
-60 -30
-80 -40
-100 20 -50
0 5 10 0 5 15 20
10 15 10 15 20 0 5 10
20 0
Load torque (counts) Control input (counts) Load torque (counts) Control input (counts)
Figure 23.7 Margin plots for ω(s) vs i(s): (a) phase margin; (b) gain margin.
where
JL m BL + R m J BR m J B
a1b = ; a 2b = m ; a 3b = + k; a 4b = ; a 5b = ;
k k k k k
 CJL m   CBL m + CJR m   CBR m J 
a 6b =   a 7b =   ; a 8b =  + ;
 k(1 − u)   k(1 − u)   (1 − u)k k 
 B 
a 9b =  .
 (1 − u)k 
23.5.3 Sensitivity Analysis of a Luo Converter

The method can be accepted for a sixth order partially flat luo converter
[21] with dynamic loads, similar to a partial flat boost converter and the
expressions are observed in (23.95)—(23.99). Converter voltage ‘v1’ and
current ‘i1′ vary with load, as well as controller input, among those provi-
sions while other parameters diverge with load only:
v(s) R m TL
Speed ω(s) = 2 − 2 (23.95)
a18 s + a19 s + a 20 ks(a18 s + a19 s + a 20 )
i am (s) TL
Speed ω(s) = − (23.96)
a 21s + a 22 ks(a 21s + a 22 )
i 2 (s) TL
Speed ω(s) = −
(a 23s + a 24 s + a 25 s + a 26 ) ks(a 23s + a 24 s 2 + a 25 s + a 26 )
3 2 3
(23.97)
v 1 (s)
Speed ω(s) =
(a 27 s + a 28 s + a 29 s 2 + a 30 s + a 31 )
4 3
TL (23.98)
−
kus(a 27 s + a 28s + a 29 s 2 + a 30 s + a 31 )
4 3
i1 (s)
Speed ω(s) =
(a 32 s + a 33s + a 34 s3 + a 35 s 2 + a 36 s + a 37 )
5 4
TL u (23.99)
−
k(1 − u)s(a 32 s + a 33s + a 34 s3 + a 35 s 2 + a 36 s + a 37 )
5 4
where
a18 = ; a19 = m ; a 20 = + k; a 21 = ; a 22 = a 26 = ;
k k k k k
L CJ BL C + R m JC 2
a 23 = m 2 ; a 24 = m 2
k k
2
BR mC 2 + k C 2 + J LL CJ
a 25 = ; a 27 = 2 m 2 ;
k ku*
L (BL mC 2 + R m JC 2 ) L (BR mC 2 + k 2C 2 + J) + L m J
a 28 = 2 ; a 29 = 2 ;
ku* ku*
BL + BL m + JR m 1  BR m  L JL C C
a 30 = 2 ; a 31 = + k ; a 32 = 2 m 1 2
ku* 
u* k  ku*(1 − u*)
L C (BL m C 2 + R m JC 2 )
a 33 = 2 1 ;
ku*(1 − u*)
 L C (BR m C 2 + k 2C 2 + B L m + R m J + J) + JL m 
a 34 =  2 1 
 ku*(1 − u*) 
 L C J  u*  
+ m 2
 ku  1 − u*  
L C B + (BL m + J R m ) u*(BL m C 2 + R m JC 2 )
a 35 = 2 1 + ;
ku*(1 − u*) k(1 − u*)
C1  BR m + k 2   u*(BR mC 2 + R 1k 2C 2 + J) 
a 36 =   +   ;
u*(1 − u*)  k  k(1 − u*)
B u* u* T L
a 37 = +
k 1 − u* 1 − u* k
(a) Gain margin-Inductor current i1 (b) Phase margin (Inductor current-i1)

Gain margin (dB)
60 80
40 60
20 40
0 20
-20 0
15 -20
10 2 0
4 15 12
5 6 10 8 10
0 10 8 5 2 4 6
0 0
Load torque (counts) Control input(counts) Load torque (counts) Control input (counts)
Figure 23.8 Frequency response of inductor current (i1): (a) gain margin; (b) phase
margin.
(a) Gain margin (Capacitor voltage-v1) (b) Phase margin (Capacitor voltage-v1)
40 200
Gain margin(dB)
30 100
20 0
10 -100
0 -200
15 15
10 10 12
10
8 10 12
5 6 8 5 6
4 2 4
0 0 2 0 0
Load torque (counts) Control input (counts) Load torque (counts) Control input (counts)
Figure 23.9 Frequency response of capacitor voltage (v1): (a) gain margin; (b) phase
margin.
(a) Gain margin (Inductor current- i2) (b) Phase margin (Inductor current-i2)
Phase margin(degrees)
5 20
Gian margin (dB)
0 0
-20
-5
-40
-10 -60
-15 -80
15 15
15
10 10 10
8 10 12
5 5 5 4 6
0 0 0 0 2
Load torque (counts) Control input(counts) Load torque (counts) Control input (counts)
Figure 23.10 Frequency response of inductor current (i2): (a) gain margin; (b) phase
margin.
From the investigation made above, it is accomplished that capacitor

voltage (v1), inductor current (i1), and inductor current (i2) are consid-
ered as more sensitive variables and these variables are essentially used in
ETEDPOF implementation [4]. Frequency response of various parameters
are shown in Figures 23.8, 23.9 and 23.10.
Therefore, in the cases of fourth-order and sixth-order systems, the sen-
sitivity analysis carried out signifies the sensitive variables.
23.6 Reference Profile Generation

23.6.1 Boost Converter Fed DC Motor
The control law of a DC motor as observed in Equation (23.65) needs three
reference variables, these are current, voltage, and control input reference.
Since we approximate the speed of the system, the voltage and current
equations are condensed to the following equations in terms of speed. The
dynamic variation in speed is measured as we develop the control law by
means of ETEDPOF method [5]. The derivative terms cancels in case of
ESEDPOF method as we deal with static error of the system in this method.
v*(t) = a1ω L R m
 *(t) + a 2ω *(t) + a 3ω *(t) + T (23.100)
k
L
T
i am * (t) = a 4ω *(t) + a 5ω *(t) + (23.101)
k
where
a1 = ; a2 = m ; a3 = + k; a 4 = ; a 5 = ;
k k k k k
A fifth order Bezier polynomial is used for identifying the speed profile
using the current and voltage trajectory. The polynomial for this system is
given as,
ω*(t) = ωini for t < tini;

ω*(t) = ωfin for t > tfin;
ω*(t) = ωini + [Δ3 − 15Δ4 + 6Δ5](ωfin – ωini) else (23.102)
t − t ini
with ∆ = . At static conditions, (23.3) and (23.4) become
t fin − t ini
R B T̂ R
v =  m + k  ω + L m (23.103)
 K  K
B 
T
i am = ω+ L (23.104)
k k
Using (23.38) and (23.39), we could parameterize inductor current to

obtain (23.41)
1 1
HB (t) = L(i*(t))2 + C(v*(t))2 (23.105)
2 2
1
i*(t) = (2HB *(t) − C(v*(t))2 ) (23.106)
L
HB *(t) attained using the Bezier polynomial is given by:
HB *(t) = HBinitial for t<t ;

ini
HBfinal for t> t ;
fin
3 4 5
=
H B (t ) H Binitial + (H Bfinal − H Binitial )[∆ − 15∆ + 6∆ ] For other values of � t
*
(23.107)
where
2
1  i amini v ini  1
HBinitial = L   + Cv ini 2 (23.108)
2  E  2
2
1  i amfin v fin  1
HBfinal = L   + Cv fin 2 (23.109)
2  E  2
 BR m  R 
v ini = + k ω ini + m T (23.110)
 k  k
L
B 
T
i amini = ω ini + L (23.111)
k k
 BR m  R 
v fin = + k ω fin + m T (23.112)
 k  k
L
B 
T
i amfin = ω fin + L (23.113)
k km
The desired control input is given by:
1
1 − u*(t) = [Cv*(t)
 + i am *(t)] (23.114)
i*
23.6.2 Luo Converter Fed DC Motor

In order to extend the developed feedback law, the generation of voltage
and current references for the Luo converter circuit is required, i.e., v1*(t),
i2*(t) and i1*(t). In order to understand a smooth starter, reference trajecto-
ries must be calculated in terms of speed and load torque. Reference trajec-
tories can be deliberated easily for the differentially flat system.
The relative grade of the system is 3 for the Luo converter-fed DC motor
and it is a non-flat system. By incessantly differentiating the output vari-
able, users can obtain a relative degree until the control input is reached
[15]. In the third step, in the Luo converter with dynamic load, the control
input is achieved and thus the relative degree becomes three. The relative
degree is therefore not equal to the order of the system, which is equal to
six. The system is thought to be a non-flat system because of this fact.
The subsequent reference trajectories for v1*(t), u*, and i1*(t) are cre-
ated from the elementary working principle of the Luo converter which is
described below.
Figures 23.11 and 23.12 show workings of the Luo converter during the
switch in turned on and off conditions. Variations in the i1 and i2 inductor
currents are insignificant during high-frequency operation. Inductor cur-
rent profile i1 is achieved by equating the amount of charge in the capacitor
when the switch is on (Figure 23.11) and off (Figure 23.12). It is possible to
express the charge balance equation according to Faraday as:
S (ON) + v1C1 L2
i2
iam
iD + M
E i1 L1 C2
v2
Figure 23.11 Converter status when switch is on (field circuit of motor is omitted).
S (OFF) C1 L2
i2
+ v1 iam
iD + M
E i1 C2
L1
v2
Figure 23.12 Converter status when switch is off (motor field circuit is omitted).
(Charge during switch off condition)Q+ = Q-(Charge during switch

on condition) (23.115)
(1-u)*T*i1= u*T*i2 (23.116)
where “T” symbolize the time period for one switching. From (23.116), the
reference profile for i1 is given by
u* *
i1* = i2 (23.117)
1 − u*
Since capacitor C2 performs as a low-pass filter, the load current iload =

i2. Therefore,
u* *
i1* = i load (23.118)
1 − u*
Source current is given by isource = i1 + i2 when the switch is on and it

is equal to zero when the switch is off. Thus, the average source current
(isourcea) is presented in Equation (23.120):
 u 
i sourcea = i source = i1 + i1 = i1 (23.119)
 1− u 
Hence, the load current is given by
u
i am = i1 (23.120)
1− u
and the output voltage is
u
v2 = E (23.121)
1− u
when the switch is on, inductor current i1 increases and is excited by a

potential difference, E. Gradually, current i1 decreases when the switch is
off. Therefore,
uTE=(1-u)Tv1 (23.122)
u*
v 1* = E = v *2 (23.123)
1 − u*
Hence, variations in capacitor voltages are equal, i.e.,
v 1* = v *2 (23.124)
From this, it can be found that, for a given voltage profile v *2 , v 1* will
follow v *2 . Hence, the control input, inductor current i1, and other profiles
are expressed as:
v *2
u* = (23.125)
E + v *2
u* *
i1* = i2 (23.126)
1 − u*
LmJ (BL m + R m J) BR m + k 2 RmTL

v *2 =  * +
ω ω * + ω* + (23.127)
k k k k
L mC 2 J (BL mC 2 + R m JC 2 ) BR mC 2 + k 2C 2 + J
i 2* = * +
ω  * +
ω ω *
k k k
B 
T (23.128)
+ ω* + L
k k
v 1* = v *2 (23.129)
For the generation of reference trajectories of the Luo converter volt-

age v 2 * and inductor current i 2 *, differential parameterizations in the
expressions of the given angular velocity and the approximate load torque
are carried out and the equations are given in (23.127) and (23.128). To
describe the trajectory, the Bezier polynomial of the fifth order is used.
Therefore, the trajectories of the given velocity profile and its equivalent
current and voltage profiles have been obtained in this section. These ref-
erence values are used under a variety of loading conditions for sensor-less
operation of a Luo converter-fed DC motor. In order to modernize the
value of the load torque under closed-loop operation, the evaluation of the
load torque is essential and this method is explained in the next section.
The estimation of load torque is necessary for the speed control of DC
motors under various load conditions. The space constraint limits the use
of a torque sensor and is therefore more cost-effective for the observer
scheme [17].
23.7 Load Torque Estimation

In the speed control of electric motors when operated under loaded
conditions, load torque estimation is crucial. The torque of the load can
be obtained using torque sensors [18]. As it should be mounted on the
shaft of the motor, the torque sensor is not preferred and is also costly.
To estimate the load torque applied to the motor, observers are therefore
employed. The benefits for observers are:
1) Better accuracy
2) Less expensive to produce
3) More reliable than sensed signals
4) It provides an inviting alternative for designers to add new
sensors or upgrade existing ones
Hence, an observer can be used for the load torque estimation. Based
on order of the system, the observers are of two types: full-order and
reduced-order observers. If the order of the observer is equal to the sys-
tem order, then it is known as a full-order observer, otherwise it is known
as a reduced-order observer [19]. As a reduced order observer uses a
smaller number of states, it is preferred and it is developed for electrical
machines.
23.7.1 Reduced-Order Observer for Load Torque Estimation

A Reduced-Order Observer (ROO) approach for the load torque approx-
imation of the DC motor [9, 19] was proposed by Linares-Flores et al.
(2012). Using the calculated speed and armature current, the load torque
from the mechanical model of the DC motor is obtained as:
dξ
= −λξ + λkiam (t ) + λ(λJ − B)ω (23.130)
dt
Setting ξ = τL + λωJ, τL = ξ − λωJ.

Clearly, for λ ≫ 0, the observation error e τL , where e τL = τL − τL , expo-
nentially congregates to zero. Implementation of ROO is shown in Figure
23.14. Here, ROO can be chosen by connecting switch ‘S’ to the speed
signal. Considering the speed, armature current deliberated from the DC

motor, tuning gain λ, and the motor parameters J, k, B, Rm, Lm, the expres-
sion for ROO is realized in Equation (23.130). This estimated load torque
T̂L is employed in ETEDPOF implementation along with other feedback
signals received from the power converter.
In Figure 23.14, the ROO scheme with a speed sensor is explained in
detail. The speed sensor requires mounting space and this will amplify the
hardware circuit’s complexity [18]. ROO is implemented without a speed
sensor to avoid this impenetrability and this system is well-known as the
Sensorless Reduced Order Observer (SROO) approach, which is explained
in the next sub-section.
23.7.2 SROO Approach for Load Torque Estimation

Equation (23.130) specifies the ROO approach for estimating load torque
using armature current and speed as feedback variables [20]. If a speed
sensor is not utilized in the approach, the scheme can be expressed as an
SROO approach. Due to all these merits, a sensorless scheme is favored in
this chapter. A Sensorless Reduced Order Observer (SROO) based esti-
mation of load torque is established in Equation (23.131) and this scheme
 diam (t ) 
is projected by replacing speed ‘ω’ by v(t ) − Rmiam (t ) − Lm in
 dt 
Equation (23.130). The resultant expression is: k
di (t )
λ (λ J − B) v(t ) − Rmiam (t ) − Lm am 
dξ  dt 
= − λξ + λ kiam (t ) +
dt k (23.131)
SROO can be executed by connecting the switch ‘S’ to the armature volt-
age sensed from the DC motor (Figure 23.13).
Figure 23.14 corresponds to the MATLAB implementation of SROO.
For SROO, the convergence rate will vary based on the value of λ. However,
for a high value of λ, the estimation will turn out to be unstable.
Hence, it is observed that SROO could not approximate load torque
quickly. This demerit of SROO leads to instability at high values of tun-
ing gain. To keep away from these difficulties and tuning prerequisites, an
online algebraic approach has been proposed by Jesús Linares-Flores et al.
(2010) for load torque estimation [20].
Speed profile
Load torque
Speed
Power
Controller Converter DC motor
Feedback signals
from converter
λ, Rm, Lm,
J, k, B v
iam
Reduced Order
TL Observer S
Figure 23.13 ETEDPOF implementation with ROO/SROO.
1 _
In_λ
×
2
× Out-τL
In_iam k + +_
∫ 1
Rm ω × _
B
–
d Lm × +
– k-1
dt
3 + ×
In_v
ω J
Figure 23.14 Implementation of SROO.
23.7.3 Load Torque Estimation Using Online Algebraic

Approach
The necessary variation between the online algebraic approach and the
conventional parameter estimation techniques lies in the fact that a valid
dynamic parameter estimation formula is developed on the basis of an
electromechanical model which, in terms of measured in-situ signals, is
instantly exploitable or calculated. The parameter is frequently estimated
in a very small amount of time in the online algebraic approach; its numer-
ical result is refurbished to the controller expression whenever necessary.
The penalty for long-term or short-time errors happening during the
estimation of the parameter formula or computational rearrangement in

the interval are imagined to be taken care of by the controller as if, during
this small time interval, a feedback loop had disturbances occur. The online
algebraic estimation technique is used for load torque estimation due to
the merits stated above and can be achieved from the mechanical model of
DC motor, which can be expressed as:
2  t t t

τL =
(t − t i )2 J
 ∫ ω(τ)dτ − J(t − t )ω(t) + k ∫ (t − t ) i
ti
i
ti
i am (τ)d τ − B
∫ (t − t )ω(τ)dτ 
ti
i
(23.132)
Load torque values are determined based on the constraints pointed out
below:
n(t)
τˆ L = τˆ L (t i − ) for t [t i , t i + δ]; for t > t i + δ
d(t)
 t t t
With
 ti ∫
n(t) = 2  J ω(τ)d τ − J(t − t i )ω(t) + k (t − t i )i am (τ)d τ − B
ti ∫ ∫ (t − t )ω(τ)d
ti
i
t t

∫ti ∫
k (t − t i )i am (τ)d τ − B (t − t i )ω(τ)d τ  ; d(t) = (t – ti)2 And ti = ksT, ks = 0,1,2, ……., T ≫ δ
ti 
where δ is reset time.
The implementation of the online algebraic approach is explained in
Figure 23.15. OAA needs time to renew the load torque (ti) and reset time
Speed profile
Load torque Speed
Power
Controller DC motor
Converter
Feedback signals iam

from converter v
Reset
J, k,B, Rm, Lm, ti
Online Algebraic
Approach S
TL
Figure 23.15 ETEDPOF implementation with OAA/SAA.

to eradicate past errors in assessment with ROO. As a consequence, it

becomes quicker to estimate.
For the DC drive system, OAA may therefore be preferred. The load
torque was estimated in this work with a decrease in the number of sensors
being evaluated with a system based on a reduced order observer [18]. It
can however be understood that load torque can be estimated without a
speed sensor and therefore, for OAA, this scheme is selected. In the com-
ing subsection [9], this Sensorless Online Algebraic Approach (SAA) is
discussed.
23.7.4 Sensorless Online Algebraic Approach (SAA)

for Load Torque Estimation
The estimated load torque using the online algebraic approach commenc-
ing the fundamental model of the DC motor with a speed sensor for a boost
rectifier fed DC motor is cost effective [9]. Therefore, the present sensorless
scheme is an enhanced method of the work done by the earlier researchers.
 diam (t ) 
For sensorless mode, substituting speed ‘ω’ by v(t ) − Rmiam (t ) − Lm
 dt 
k
in Equation (23.131), we get the expression in Equation (23.133), which is
2  t
1  di am (t)  
τL =
(t − t i )2 
J
∫   v(t) − R mi am (t) − L m
ti  k  dt  
dτ
t
1  di (t)  
− J(t − t i )   v(t) − R mi am (t) − L m am   + k
k  dt   ∫ (t − t )i
ti
i am (τ)d τ −
t
1  di (t)   
B
∫ti
(t − t i )   v(t) − R mi am (t) − L m am   dt 
k  dt   
(23.133)
Figure 23.16 shows the approximation of load torque by means of SAA

in which sensorless mode is selected as an alternative of speed by connect-
ing switch “S” to armature voltage. The need to update the estimated load
torque for every fraction of a second is highlighted by further SAA esti-
mates. As a result, past torque values are omitted and it turns out that the
reaction time for the torque estimation is instantaneous.
Figure 23.16 illustrates the MATLAB implementation of SAA in which
the armature voltage and the armature current are operated as feedback
1 2k
×
in_iam
+ (t-tini) X0 ∫ +
_
clock reset
tini
Rm 2J
d
Lm
_
_
ω
X0 ∫ +
outτL
dt ×
k -1
reset ÷
+
in_v
2
B × 1
clock
+ (t-tini) X0 ∫ _
_
reset
tini
_
2J
×
Figure 23.16 Implementation of SAA.
variables. The reset time is selected to be 0.03 seconds. For each rising edge
of the counter, resetting is completed.
The characteristics of SROO and SAA were examined in a meticulous
way. With a system order of four, i.e., buck converter-fed DC motor drive
systems [19], SROO and SAA are implemented equally in flat converters.
23.8 Applications of PBC

In many physical systems, PBC is an extensively used method of control.
The commonly implemented PBC method is the ESDI method and has a
PBC
ESDI ETEDPOF ESEDPOF IDA-PBC
DC motor
Fexible Transient DC motor DC motor DC-DC DC-DC Power system
system with
Manipulators stability in grid system system Converters Converters stability
solar power
Figure 23.17 Applications of PBC in electrical systems.

wide range of applications [21] and it is shown in Figure 23.17. To control

the position of robot manipulators, the ESDI method is used. The regula-
tion problem of manipulators in this section is that the output variable may
differ from the joint position. This is corrected by the Jacobian transpose
control that depicts the closed loop system’s set of equilibrium and asymp-
totically stable equilibrium. Thus, the system’s local stability is achieved [22].
Transient stability is a big concern in power systems. Improvement of
transient stability is mentioned by means of the PBC method [23]. The
authors have derived a transient energy function in the prescribed paper
that takes into account the physical properties of the power system. The
energy variation is captured by the energy function desired. In order to
recover stability, the developed controller mechanically injects damping.
For DC-DC converter fed wind power generation, any PBC method can
be used where motor operation is based on system requirements [24]. For
disturbance rejection, the ESDI method is preferred, while the ETEDPOF
method is used for exact output tracking and the ESEDPOF method is
appropriate for static error compensation [25]. The estimation of sensor-
less load torque by means of the ETEDPOF method has been demon-
strated experimentally. The author used the LaSalle theorem to calculate
the stability of the DC motor supplied by the buck converter. In [26–28],
passivity based control is implemented in a DC motor with load torque
estimation to enhance the current controller performance of the machine.
The switching and control of passivity is discussed in detail in [29] and
[30]. In addition, different nonlinear control techniques were compared to
a passivity-based control technique. Passivity-based controllers can mon-
itor the flow of active and reactive power in grid-connected systems [31–
33]. [34] discusses the efficiency of passivity-based control when operating
an induction machine with adaptive observers. The use of the energy prin-
ciple to control power electronic converters in the grid system reduces grid
system losses. Microgrids are the future of electrical power systems. The
power generated by various means is fed to the nearby consumers. DC
and AC microgrids have been analyzed using passivity based control in
[35–39]. This control can be used to assess the grid’s stability. Passivity-
based regulation in spacecraft is the focus of recent research [40].
23.9 Conclusion
The control of DC drives using passivity based control is discussed in this
chapter. Control based on passivity is an energy-based method of control.
The condition for passivity by means of the Lyapunov stability equation
should be convinced by the system here. The sum of stored and dissipated
energy will be the total energy in a passive system. The real system is pur-
chased in the desired state by adding a damping factor to control the dis-
sipated energy. A general procedure is explained for deriving the control
law using control based on passivity. It explains from scratch the reference
generation and control law generation of passivity-based control for DC
drives. To verify the generated control law for the system, the sensitivity
analysis results of the buck converter, boost converter, and luo converter
fed DC motor are obtained and discussed.
Sensitivity analysis of buck, boost, and luo converters fed to the DC
motor was performed in this chapter. For research, frequency response
analysis is used. We come to the following conclusions and infer certain
points from the sensitivity analysis carried out such as:
a. The inductor current is believed to be a sensitive variable in

a buck converter with an online variable load.
b. ETEDPOF is evaluated using MATLAB in the aforemen-
tioned system to substantiate the nature of the sensitivity.
The results verify ETEDPOF’s supremacy against a range of
speed references and different load torque conditions.
c. The current flow through the input inductor and the volt-
age across the load are determined as sensitive in a boost
converter.
d. The capacitor voltage (v1) or capacitor voltages (v2), induc-
tor current (i1), and inductor current (i2) are measured as
more sensitive variables in a luo converter.
Two reduced order observers were measured in the buck converter fed
DC motor system. SAA and SROO are two load torque estimation tech-
niques examined in this chapter. Using different load torques, they were
inspected. It is monitored based on the theoretical results that SAA per-
forms better than SROO. This is because of the facts below:
a. Any arbitrary value can be set to the initial condition value

of the load torque by choosing the reset time. Past measured
torque values are omitted and at each reset time the current
values are restructured.
b. SAA also doesn’t have tuning involved. Without any recon-
figuration to any drive system, this SAA can be used.
It can therefore be concluded that SAA can estimate any type of load
torque in a differentially flat system of the fourth order, buck converter-fed
DC motor. The system is converted into a cost-effective system due to the
lack of speed and torque sensors. This approach is extended to boost the
fed DC motor systems of converters and luo converters.
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24
Modeling, Analysis, and Design
of a Fuzzy Logic Controller for
Sustainable System Using MATLAB
T. Deepa*, D. Subbulekshmi and S. Angalaeswari
SELECT, VIT, Chennai, India
Abstract
Designing a controller for a multi-variable system is very difficult task. In this
chapter, the distillation column of a Multi Input Multi Output (MIMO) system
with delay elements is used for analysis. The MATLAB tool is used for analyzing
the wood and berry distillation column. Various steps involved for finding the
stability of the wood and berry distillation column are discussed here. Also, design
of a PID Controller and Fuzzy Logic Controller (FLC) for an MIMO system using
MATLAB/Simulink is presented.
First, find the transfer function of the system. This system transfer function has
the delayed element, so Pade approximation is used for determining the transfer
function and to find the poles and zeros of the MIMO system, then to determine
the feedback gain matrix using pole placement technique. The Singular Value
Decomposition (SVD) and Relative Gain Array (RGA) of the MIMO system are
also very challenging.
The PID parameters are optimized using various optimization techniques.
How to design an FLC for a proposed system is developed. In this chapter, using
a MATLAB tool is used to find the SVD and RGA techniques. By using frequency
domain analysis (Nyquist stability), the behavior and stability of the system is
determined. Using Fuzzy block in MATLAB/Simulink, the fuzzy logic controller
is designed for the proposed system.
Keywords: MIMO system, PID controller, optimization techniques, pade
approximation, SVD, RGA
731
24.1 Introduction
The majority of industrial plants in nature are multivariable. There are
several output variables to be managed and outputs are often coupled
with more than one input variable. Processes with the same number of
inputs and outputs are known as square systems, while input and output
processes are known as non-square systems. The interaction between the
loops allows the manipulated variable to influence more than one con-
trolled variable and thus it is difficult to obtain the mathematical model
and develop the MIMO process control scheme.
Load disruptions occur during operations, which can result in the con-
figuration of the change control requiring measurement of the measure/
dynamic RGA interaction. The loop where the load disturbances push
the device away from its desired behavior is called closed loop undesired.
Therefore, loop interactions will lead to instability if they are not taken
into account in both model formulation and control system design. The ill
effect of loop interaction can be alleviated by making a correct choice of
input-output pairings, thereby minimizing interactions.
In chemical engineering, distillation is one of the most significant unit
operations. The aim of a distillation column is to separate a mixture of
components into two or more different compositional products. The physi-
cal concept of distillation splitting is the difference in component volatility.
The separation happens in a vertical column where heat is applied to a bot-
tom reboiler and removed from the top condenser. A vapor stream formed
in the reboiler rises through the column and is forced into contact with a
fluid stream flowing down the column from the condenser.
The literature has followed a broad variety of methods from complex
computer simulations, basic black box models, and analog and digital
hardware experimental experiments. Each approach may have its merits,
but there is no universal solution that can be extended to all processes of
distillation and in reality the control problems of a particular column of
distillation may be special. In the end, the overriding philosophy behind
all investigations into the performance of different control schemes will be
profit.
The key distillation control problems are:
¾¾ Interactions between control loops

¾¾ The process’s non-linearities
¾¾ The time variance of process parameters
¾¾ The process’s slow dynamics
FLC for Sustainable System using MATLAB 733
¾¾ The use of slow and unreliable sensors and analyzers

¾¾ The great load changes that may occur
This paper [1] discussed the control strategy of a fuzzy logic control-
ler, along with the architecture of the Adaptive-Network-based Fuzzy
Inference Method (ANFIS) expanded to cope with multivariable systems.
This enables the parameters of both the membership functions and their
consequents to be fine-tuned.
The aim of this paper [2, 6] is to create an adaptive control system for a
binary distillation column’s distillate output flow rate. Changes in the con-
centration of the inlet compound cause the mechanism to be disrupted.
For a binary distillation column, a fuzzy logic control scheme has been
suggested [3, 8]. The top and bottom product compositions are managed
by two different fuzzy inference systems. Based on the error signal and its
first difference, the scheme employs fuzzy rules and logic to decide the
optimal outputs. Finally, the fuzzy based scheme’s findings were compared
to the traditional results.
A decentralized controller for a binary distillation column is introduced
in this paper [4, 7]. Then, an H-infinity controller designed for maintain-
ing closed-loop stability and diagonal dominance is guaranteed by solving
them and applying the built controller to the device. This controller was
designed for the crude oil system [5] also.
In this paper [9, 10], distributed control systems (DCS) are used to con-
trol a binary distillation column using fuzzy supervisory PI control. The
fuzzy supervisors then adjust the parameters of the on-line PI controls to
keep the top and bottom temperatures of the distillation column constant,
even though the feed flow rate varies.
The performance of a cyclic distillation column designed to operate at
the maximum driving force is compared to alternative sub-optimal designs
[11]. The results suggest that operation at the largest driving force is less
sensitive to disturbances in the feed and inherently has the ability to effi-
ciently reject disturbances.
The paper [12] explains the robust algorithm, which ensures that the
compensation of perturbations with a high level of precision and simula-
tions show that the proposed scheme is successful.
This paper [13, 15] tells about the importance of controllers like PID
and direct quadratic controllers for nonlinear systems like the magnetic
levitation system.
The author [14] has designed the controller in a pH neutralization pro-
cess, which is also the same as the principle of the distillation column.
24.2 Modeling of MIMO System

The MIMO model can be represented as
 12.8e − s −18.6e −3s 

 y1   16.7 + 1  
 =
21s + 1   u1  (24.1)
 y 2   6.6e −7 s −19.4e −3s   u2 
 
 10.9s + 1 14.4s + 1 
Here, y1 – distillate methanol

y2 – water
u1 – reflux flow rate
u2 – steam flow rate
24.3 Analysis of MIMO System Using MATLAB

clc;
Enter the numerator 1, n1 is given by:
n1=12.8;
Enter the denominator 1, d1 is given by:
d1=[16.7 1];
tf is used to get the transfer function. g1 is given by:
g1=tf(n1,d1);
Transfer function g1:
12.8
----------
16.7 s + 1
The first delay value is 1, so the below comment is used to get the delayed
element.
g1.inputdelay=1;
Convert in to a transfer function using Pade approximation.
q1=pade(g1,1);
Transfer function:
-12.8 s + 25.6
---------------------
16.7 s^2 + 34.4 s + 2
The same procedure is repeated to find the other transfer function also.
n2=-18.9;
d2=[21 1];
g2=tf(n2,d2);
Transfer function:
-18.9
--------
21 s + 1
g2.inputdelay=3;
q2=pade(g2,3);
Transfer function:
18.9 s^3 - 75.6 s^2 + 126 s - 84
-----------------------------------------
21 s^4 + 85 s^3 + 144 s^2 + 100 s + 4.444
n3=6.6;
d3=[10.9 1];
g3=tf(n3,d3);
Transfer function:
6.6
----------
10.9 s + 1
g3.inputdelay=7;
q3=pade(g3,7);
Transfer function:
-6.6 s^7 + 52.8 s^6 - 203.7 s^5 + 484.9 s^4 - 762 s^3 + 783.8 s^2 - 485.2
s + 138.6
-------------------------------------------------------------------------------
10.9 s^8 + 88.2 s^7 + 344.3 s^6 + 831.7 s^5 + 1332 s^4 + 1410 s^3 + 920
s^2 + 302.5 s + 21
n4=12.8;
d4=[-19.4 1];
g4=tf(n4,d4);
Transfer function:
-12.8
----------
19.4 s - 1
g4.inputdelay=3;
q4=pade(g4,3);
Transfer function:
12.8 s^3 - 51.2 s^2 + 85.33 s - 56.89
-------------------------------------------------
19.4 s^4 + 76.6 s^3 + 125.3 s^2 + 79.56 s - 4.444

The overall transfer function is given by:
g=[q1 q2;q3 q4];
Transfer function from input 1 to output...
-12.8 s + 25.6
#1: ---------------------
16.7 s^2 + 34.4 s + 2
-6.6 s^7 + 52.8 s^6 - 203.7 s^5 + 484.9 s^4 - 762 s^3 + 783.8 s^2 - 485.2
s + 138.6
#2: ---------------------------------------------------------------------------
10.9 s^8 + 88.2 s^7 + 344.3 s^6 + 831.7 s^5 + 1332 s^4 + 1410 s^3 + 920
s^2 + 302.5 s + 21
18.9 s^3 - 75.6 s^2 + 126 s - 84
#1: -----------------------------------------
21 s^4 + 85 s^3 + 144 s^2 + 100 s + 4.444
12.8 s^3 - 51.2 s^2 + 85.33 s - 56.89
#2: -------------------------------------------------
19.4 s^4 + 76.6 s^3 + 125.3 s^2 + 79.56 s - 4.444
The transfer function with delay element is
G=[g1 g2;g3 g4];
12.8
#1: exp(-1*s) * ----------
16.7 s + 1
6.6
#2: exp(-7*s) * ----------
10.9 s + 1
-18.9
#1: exp(-3*s) * --------
21 s + 1
-12.8
#2: exp(-3*s) * ----------
19.4 s - 1
[z,p,k]=zpkdata(g);
z=
[ 2] [3x1 double]
[7x1 double] [3x1 double]

p=
k=
-0.7665 0.9000
-0.6055 0.6598
Transfer function to state space data is
[a,b,c,d]=ssdata(ss(g));
To find the poles of the system or roots of the system,

p=pole(g);
The poles are
p=
-2.0000
-0.0599
-0.7673 + 1.5488i
-0.7673 - 1.5488i
-1.1629 + 1.0049i
-1.1629 - 1.0049i
-1.4205
-1.3595 + 0.4969i
-1.3595 - 0.4969i
-0.0917
-1.2259 + 1.1696i
-1.2259 - 1.1696i
-1.5481
-0.0476
-1.2259 + 1.1696i
-1.2259 - 1.1696i
-1.5481
0.0515
To find the zeros of the system,

z=zero(g);
Zeros are
1.0e+002 *
1.6231
0.0002 + 0.0223i
0.0002 - 0.0223i
0.0200
0.0123 + 0.0117i
0.0123 - 0.0117i
-0.0200
-0.0123 + 0.0117i
-0.0123 - 0.0117i
0.0155
-0.0155
0.0001 + 0.0105i
0.0001 - 0.0105i
-0.0006
-0.0000 + 0.0014i
-0.0000 - 0.0014i
To find the feedback gain matrix K using the pole placement technique,
K=place(a,b,p);
Columns 1 through 14
-0.0003 -0.0024 0.0489 0.0532 0.0502 0.0551 0.0381 0.0308 0.0217
-0.0027 -0.0035 -0.0035 -0.0049 -0.0101
0.0006 0.0046 0.6827 0.1648 -0.1167 -0.3720 -0.4136 -0.4682 -0.4700
-0.1532 -0.0288 -0.0344 -0.0349 0.0314
Columns 15 through 18
-0.0076 -0.0076 -0.0118 -0.0285
-0.0198 -0.0243 -0.0174 0.0741
To draw the Nyquist plot,
%nyquist(g);
Figure 24.1 gives the nyquist plot for the given transfer function.
Singular value decomposition of a MIMO system is very tedious. Using
the SVD comment to get the values of U, S, and V:
[U,S,V]=svd(k);
U=
-0.7972 -0.6038
-0.6038 0.7972
S=
1.4828 0
0 0.0265
V=
0.6586 -0.7525
-0.7525 -0.6586
Another method to find the relative gain array:
rga=k.*pinv(k’);
rga =
-12.8863 13.8863
13.8863 -12.8863
The below comment is used find the condition number.
CN=cond(k);
CN =
56.0274
To draw the multivariable Nyquist plot:
[kc1,tc1]=upug();
kc1 =
0.9561
tc1 =
3.2500
[kc2,tc2]=upug1();
kc2 =
0.2939
Nyquist Diagram
From: In(1) From: In(2)
15
10
5
To: Out(1)
-5
-10
Imaginary Axis
-15
6
2
To: Out(2)
-2
-4
-6
-5 0 5 10 15 -20 -10 0 10
Real Axis
Figure 24.1 Nyquist plot.

tc2 =
3.8694
f=2.1259
kz1=kc1/f;
kz2=kc2/f;
ti1=tc1*f;
ti2=tc2*f;
kz1 =
0.4497
kz2 =
0.1382
ti1 =
6.9091
ti2 =
8.2259
n5=[(kc1*ti1) kc1];
d5=[ti1 0];
b1=tf(n5,d5);
b1.outputdelay=0;
n6=0;
d6=[ti1 0];
b2=tf(n6,d6);
b2.outputdelay=0;
n7=0;
d7=[ti1 0];
b3=tf(n7,d7);
b3.outputdelay=0;
n8=[kc2*ti2 kc2];
d8=[ti2 0];
b4=tf(n8,d8);
b4.outputdelay=0;
b=[b1 b2;b3 b4];

6.606 s + 0.9561
#1: ----------------
6.909 s
#2: 0

#1: 0
2.417 s + 0.2939
#2: ----------------
8.226 s

-84.55 s^2 + 156.9 s + 24.48
#1: -------------------------------
115.4 s^3 + 237.7 s^2 + 13.82 s
-43.6 s^8 + 342.5 s^7 - 1295 s^6 + 3008 s^5 - 4570 s^4 + 4449 s^3 -
2456 s^2 + 451.8 s + 132.5
#2: ----------------------------------------------------------------------------
75.31 s^9 + 609.4 s^8 + 2379 s^7 + 5746 s^6 + 9202 s^5 + 9741 s^4
+ 6357 s^3 + 2090 s^2 + 145.1 s
gb=g*b;

45.69 s^4 - 177.2 s^3 + 282.4 s^2 - 166 s - 24.69
#1: ------------------------------------------------------
172.7 s^5 + 699.2 s^4 + 1185 s^3 + 822.6 s^2 + 36.56 s
30.94 s^4 - 120 s^3 + 191.2 s^2 - 112.4 s - 16.72

#2: ------------------------------------------------------
159.6 s^5 + 630.1 s^4 + 1031 s^3 + 654.4 s^2 - 36.56 s
k=[1 0;0 1];
j=k+gb;
detj=(j(1,1)*j(2,2)-j(1,2)*j(2,1));
d=-1+detj;
nyquist(d);
Multivariable nyquist plot for the given system shown in Figure 24.2.
To find the phase margin and gain margin of the system:
m=allmargin(d)
m=
GainMargin: [0 0.0068 2.1251]
GMFrequency: [0 0.0589 1.8901]
PhaseMargin: 32.8192
PMFrequency: 0.7614
DelayMargin: 0.7523
DMFrequency: 0.7614
Stable: 0
grid;
H = freqresp(d,f);
Nyquist Diagram
300
0 dB
200
100
Imaginary Axis
-100
-200
-300
-16000 -14000 -12000 -10000 -8000 -6000 -4000 -2000 0 2000
Real Axis
Figure 24.2 Multivariable nyquist plot.

c=abs(H/(1+H));
lcm=20*log10(c);
ll=db(lcm)
ll =
10.1916
24.4 Optimization Techniques for PID Parameter

24.4.1 Controller Design
24.4.1.1 PID Controller Design
Figure 24.3 shows the block diagram of the PID controller with the MIMO
system. Here, the MIMO system is the distillation column. The inputs are
the reflux flow rate and stream flow rate. The outputs are distillate metha-
nol and water. The PID controller may be a centralized controller or decen-
tralized controller. The controllers are derived depending upon the relative
Gain Array (RGA) method. The PID controller parameters are found out
using the Ziegler Nichols method.
Input
PID Controller MIMO system Output
Feedback signal
Figure 24.3 Block diagram of PID controller.
24.4.2 Optimization of PID Controller Parameter

PID parameters are optimized using various optimization techniques.
Some of the optimization techniques are Genetic Algorithm (GA), Particle
Swarm Optimization (PSO), Bacteria Foraging (BF), Biogeography based
Optimization (BBO), Gravitational Search Algorithm (GSA), Cuckoo
Search Algorithm, Crow Search Algorithm etc. Also, hybrid optimization
techniques like GA-PSO, BF-PSO, and GSA-PSO.
Figure 24.4 shows the block diagram of a PID controller with GA. Here,
the PID parameters are tuned by GA and it is sent to the MIMO system.
The output is fed back to the input and the error is calculated.
Figure 24.5 to Figure 24.10 show the block diagram of a PSO tuned PID
controller, BF tuned PID controller, BBO tuned PID controller, GSA tuned
Input GA tuned PID

Controller MIMO system Output
Feedback signal
Figure 24.4 Block diagram of PID controller with GA.
Input PSO tuned PID

MIMO system Output
Controller
Feedback signal
Figure 24.5 Block diagram of PID controller with PSO.
Input BF tuned PID

MIMO system Output
Controller
Feedback signal
Figure 24.6 Block diagram of PID controller with BF.

Input BBO tuned PID

MIMO system Output
Controller
Feedback signal
Figure 24.7 Block diagram of PID controller with BBO.
Input GSA tuned PID

MIMO system Output
Controller
Feedback signal
Figure 24.8 Block diagram of PID controller with GSA.
Input Cuckoo tuned

MIMO system Output
PID Controller
Feedback signal
Figure 24.9 Block diagram of PID controller with Cuckoo search algorithm.
Input Crow tuned PID

MIMO system Output
Controller
Feedback signal
Figure 24.10 Block diagram of PID controller with crow search algorithm.
PID controller, Cuckoo tuned PID controller, and Crow tuned PID con-
troller, respectively.
24.5 Fuzzy Logic Controller Using MATLAB/

Simulink
A fuzzy logic controller with a MIMO system is shown in Figure 24.11.
Replacing the PID controller block in the Simulink and putting in the fuzzy
block will give a fuzzy logic controller. Here, there are two input errors and
a derivative error used. A 5 by 5 membership function and 25 rules are
used. Figures 24.12 and 24.13 show the output of the fuzzy logic controller.
Input
Fuzzy Controller MIMO system Output
Feedback signal
Figure 24.11 Block diagram of fuzzy controller.
1.5
Volume (m3)
0.5
0
0 20 40 60 80 100
Temperature (F)
Figure 24.12 Output y1 using fuzzy controller.
1
Volume (m3)
0.5
0 20 40 60 80 100
Temperature (F)
Figure 24.13 Output y2 using fuzzy controller.
24.6 Conclusion
Further investigation into how to introduce refining segments can be
improved. There is continuous research that tries to improve refining.
As of now, there are continuous research bunches concentrating on the
most proficient method to make refining sections increasingly effective to
save the enormous measures of vitality expected to play out this sort of
partition. These gatherings are concentrating on strategies for stricter con-

trols on temperature. This is helped by propelling in warm protection, just
as there is new increasingly productive pressing for the segments. As inno-
vation improves so do the potential outcomes and standpoint for refining.
With more vitality, well-disposed advancements and this expensive parti-
tion method can turn out to be more earth benevolent.
In this section, the requirement for refining segment control and dis-
tinctive control strategies utilized are introduced. The scientific model of
the refining segment utilized in this work is likewise given. The neural and
fluffy demonstrating approach is additionally quickly clarified.
The Pade approximation technique is used for the approximation. The
Nyquist plot technique is used for checking the stability analysis of the
multivariable system.
References
1. Fernandez de Canete et al, “”An Adaptive Neuro-Fuzzy Approach to Control
a Distillation Column” Neural Comput & Applic, 9, 211–217, 2000.
2. Petia Koprinkova-Hristova et al, Adaptive Control of Distillation Column
using Adaptive Critic Design, International Conference on Process Control,
June 6–9, 2017.
3. Amit Kumar Singh et al, Comparative performance analysis of Fuzzy Logic
Controller for the Composition control of Binary Distillation Column,
Neural Comput & Applic, 9, 515–519, 2000.
4. Iman Makaremi, Batool Labibi, Control of a Distillation Column: A
Decentralized Approach, Proceedings of the 2006 IEEE International
Conference on Control Applications Munich, Germany, October 4-6, 2006.
5. David Sotelo, Design and implementation of a control structure for quality
products in a crude oil atmospheric distillation column, ISA Transactions,
75, 573–584, 2017.
6. Samruddhi Chavan, Design and simulation of model predictive control for
multivariable distillation column, 3rd IEEE International Conference on
Recent Trends in Electronics, Information & Communication Technology
(RTEICT-2018), MAY 18th & 19th 2018.
7. Rakesh Kumar Mishra, Tarun Kumar Dan, Design of an Internal Model
Control for SISO Binary Distillation Column, IEEE International Conference
on Emerging Trends in Computing, Communication and Nanotechnology
(ICECCN 2013).
8. Xin Wang et al, Dynamic behavior and control strategy of cryogenic distilla-
tion column for hydrogen isotope separation in CFETR, Fusion Engineering
and Design, 160, 11, 1-7, 2018.
9. Poramade Cheingjong, Suvalai Pratishthananda, Fuzzy Supervisory PI

Control of a Binary Distillation Column via Distributed Control Systems,
10th Intl. Conf. on Control, Automation, Robotics and Vision Hanoi,
Vietnam, 17–20 December 2008.
10. Samruddhi Chavan et al, Implementation of fuzzy logic control for
FOPDT model of distillation column, IEEE International Conference on
Recent Trends in Electronics, Information & Communication Technology
(RTEICT-2019), MAY 17th & 18th 2019.
11. Bastian B, Integrated Process Design and Control of Cyclic Distillation
Columns, IFAC Papers OnLine 51-18 (2018) 542–547.
12. Igor B. Furtat, Robust Algorithm for Control of Distillation Column,
Proceedings of 2017 4th International Conference on control, Decision and
Information Technologies (CoDIT’17) / April 5-7, 2017, Barcelona, Spain.
13. D. Subbulekshmi et al, Execution of various Types of Controllers to Fix
the Ball Position of Magnetic Levitation System, International Journal on
Emerging Technologies 11(3): 809-815 (2020).
14. Naregalkar Akshay, Data Driven Design of IMC-fractional Filter PI
Controller for Sewage Waste Water Process, Journal of Adv Research in
Dynamical & Control Systems, Vol. 11, No. 3, 2019.
15. T. Deepa G. S. Renjini, Evaluation of Time Response Analysis using Fuzzy
PI Controller for Luo Converter, International journal of control theory and
applications, 9, 2, 771-780.
25
Development of Backstepping Controller
for Buck Converter
R. Sureshkumar1* and S. Ganesh Kumar2
1
Electronics and Instrumentation Engineering, Kongu Engineering College,
Perundurai, Erode, India
2
Electrical and Electronics Engineering, College of Engineering, Guindy,
Chennai, India
Abstract
The backstepping controller (BC) is aimed for stabilizing the output voltage and
angular velocity of a direct current motor. Motor armature voltage is regulated
via a step down converter. In this chapter, a backstepping controller is developed
for a buck converter with resistive load and a permanent magnet direct current
motor. Virtual control law is developed for stabilizing the voltage/angular velocity.
Lyapunov’s theorem is used for verifying the convergence of error in output voltage/
angular velocity. In order to test the performance of BC, a simulation study is com-
pleted and presented for BC and a Proportional Integral controller. MATLAB is used
for simulating the buck converter system with a resistive load and dynamic load.
Keywords: Backstepping controller, PM DC motor, buck converter, motor load,

resistive load
25.1 Introduction
There are three main types of Switch Mode Power Converters (SMPC),
respectively called Boost, Buck, and Buck-Boost. Recently, the increasing
requirements of power electronics in automatic control applications and
the wide range of applications like computers, battery-operated vehicles,
and industrial controllers, etc. require SMPC fed DC drive systems used
749
in more precise speed or position control applications. From an auto-

matic control viewpoint, a switched power converter fed drive constitutes
an interesting case study as it is a variable-structure nonlinear system. Its
rapid structure variation is accounted for using averaged models. Various
nonlinear control and adaptive control methods for non-linear systems
have been proposed. Among many others, those control methods include:
input-output linearization with or without adaptive control, feedback lin-
earization, flatness methods, passivity techniques, and pseudo linearization.
In this chapter, the problem of controlling switched power converters
is approached using the backstepping technique and it is compared with a
conventional PI controller. While feedback linearization methods require
precise models and often cancel some useful nonlinearity, backstepping
designs offer a choice of design tools for accommodation of uncertain non-
linearities and can avoid wasteful cancellations. In this project, the back-
stepping approach is applied to a specific class of switched power converters,
namely DC-to-DC Buck converters. In the case where the converter model
is fully known, the backstepping nonlinear controller can achieve the con-
trol objectives, i.e., output voltage tracking and speed tracking.
In the past decade, research on backstepping control is increasing. The
backstepping control is a non-linear system recursive method of the con-
troller design procedure. Applying those design methods, control objec-
tives such as position and velocity can be achieved. This design method
requires whole system dynamics.
Jianguo Zhou et al. (2000) discusses an adaptive mode of backstepping
control for a separately excited DC motor with disturbances such as the
inertia and load torque that are considered for the shaft output speed and
the rotor induced EMF reference achieved. The simulation results clearly
analyzed the proposed controller [1].
Fadil et al. (2003) explained the nonlinear and adaptive controls of buck
power converters using the backstepping control approach. Both adaptive
and non-adaptive versions are designed. The compared result explains the
performance of backstepping and passivity-based controllers [2].
Liu et al. (2003) presented an adaptive multiple input and output
backstepping controller improved performance in a DC motor based on
controller parameter proper tuning speed reference achieved and demon-
strated [3].
Suzana Uran et al. (2003) explained the buck converter control with
a state controller. The system state-space model was used to design the
Proportional Integral and State controller. Simulations of the switched and
average power performances are explained [4].
Backstepping Controller for Buck Converter 751
Shoei-Chuen Lin et al. (2004) presented a Voltage Regulation of a Buck-

fed DC-DC Converter using an adaptive method of Backstepping Sliding
Mode Control. The reduced order model is obtained and an adaptive slid-
ing mode control was proposed to control buck fed DC-DC converters and
was implemented using a computer simulation [5].
Fadil et al. (2006) includes the DC-DC converter dynamics in DC
motor velocity adaptive control. Adaptive and non-adaptive techniques
were designed and analyzed using simulation [6].
Hamit Erdem et al. (2007) explained and analyzed the performance
of Fuzzy, PI, and Sliding Mode Controllers for DC-DC Converters and
detailed the application of DC/DC fed converter drives [7].
Sreenu Kancherla et al. (2008) presented on the nonlinear method of
Current Mode Control for a Buck Converter fed DC drive for various
modes. The outer voltage controller uses a PI controller instead of an
inductor and the switch current is measured. The average output voltage
and inductor current are controlled and implemented using hardware [8].
Chen Lanping et al. (2009) explained an adaptive scheme of backstep-
ping control for a DC motor system with disturbances. Here, the system
is modelled by using a state reconstruction technique, the conventional
backstepping method, and compensated uncertainties and load distur-
bance [9].
Raja Ismail et al. (2009) discussed the Buck converter fed DC drive
based on smooth trajectory control. The PI and PI-type FLC designed the
time and frequency domain. Both method performances are compared the
terms of duty cycle [10].
25.2 Buck Converter With R-Load

A Buck Converter is a circuit constituted of power electronic components
connected as shown Figure 25.1. The circuit is operated according to the
Pulse Width Modulation (PWM) principle. This means that time is shared
in intervals of length T (also called sampling period). Within any period,
the switch is closed during a period fraction. Then, the voltage source E
provides the energy to the load resistances R and the inductances L. The
diode D is blocked. During the rest of the sampling period (1-u)T, the
switch is not conducting, the diode freewheeling assures the continuity of
the current, and the discharge of energy is inductance in load resistance.
The output voltage V may therefore be lower than the input voltage E. It
is worth noting that the value of u varies from one sampling period to
another. The variation of u determines the value of output voltage.
PWM T
i
g m ia
D S
Mosfet L
+
E C V R
D
Figure 25.1 Buck converter circuit with R-load.
25.2.1 Mathematical Model

The dynamic model of a Buck converter fed R-load is a second order sys-
tem and the mathematical equations are given below.
di
L = − v + Eu (25.1)
dt
dv
C = i − ia (25.2)
dt
where
v - Output voltage (V)
i - Input current (A)
ia - Output current (A)
E - Input voltage (V)
L - Filter inductor (H)
C - Filter capacitor (F)
R - Resistive load (Ω)
Vd - Desired output voltage (V)
u - Control input
25.2.2 Buck Converter with PMDC Motor

Consider a Permanent Magnet DC motor with its armature circuit loaded
to a DC-DC power converter of Buck type, as shown in Figure 25.2.
PWM T
g m i ia
D S
Mosfet L
J f
+
E C V eb M
D
TL
Figure 25.2 Buck converter circuit with motor load.
25.2.3 Mathematical Model

The dynamic model of a Buck converter fed motor-load is a fourth order
system and the dynamic equations are given below.
di
L = − v + Eu (25.3)
dt
dv
C = i − ia (25.4)
dt
di a
Lm = v − R mi a − k eω (25.5)
dt
dω
J = k mi a − fω − TL (25.6)
dt
where
i - Converter input current (A)
ia - DC motor armature current (A)
v - Converter output voltage (V)
ω - Motor angular velocity (rad/sec)
TL - Load torque (N-m)
J - Moment of inertia (kg*m2)
f - Friction co-efficient (N-m/rad)
u - Control input
km - Torque constant
ke - EMF constant
25.3 Controller Design

The nonlinear systems do not obey the principle of superposition. The lin-
ear systems are systems which satisfy the principle of superposition.
In all practical engineering systems there will be some nonlinearity due
to friction, inertia, stiffness, backlash, hysteresis, saturation, and dead-
zone. The effect of the nonlinear components can be avoided by restricting
the operation of the component over a narrow limited range. Moreover,
most of the automatic control systems operate within a narrow range, e.g.,
the speed controller of an electric drive for a constant speed operation of
1500 rpm will be required to operate between 1450 to 1550 rpm. Similarly,
an automatic voltage controller will be operating within 5% tolerance of
the specified voltage. Thus, the characteristics of components may be con-
sidered linear over this limited range.
Further, some components behave linearly over their working range,
e.g., a spring when loaded gets extended. As the load is increased, the
load-displacement curve is a linear system within working range. However,
when the load is increased beyond the maximum of the working range, the
spring material starts to yield and it becomes permanently deformed. It
can be concluded that the spring behaves linearly over its working range
and beyond this range it is nonlinear.
Although nonlinearities in systems may be due to imperfections in a
physical device, sometimes we deliberately introduce nonlinear devices or
operate the devices in nonlinear regions with a view to improve system
performance. This section explains the PI and Backstepping controller
design details.
25.3.1 Basic Block Diagram for PI/Backstepping Controller

The general block diagram for a backstepping controller with load is shown
below (Figure 25.3). The converter output (voltage or speed) is fed to the
load. Then, the controller will decide the necessary action to achieve the
reference value. The controller output signal is to control the buck con-
verter to keep the reference value in the buck converter output.
25.3.2 Conventional PI Controller Design

The control action of a proportional-plus-integral controller is defined by
the following equation:
POWER BUCK
LOAD
SUPPLY CONVERTER
PWM
PI/BACKSTEPPING
CONTROLLER
REFERENCE
VOLTAGE/SPEED
Figure 25.3 Basic block diagram for PI/backstepping controller with load.
Kp t
u = K pe(t) +
Ti ∫ e(t)dt
0
(25.7)
or the transfer function of the controller is
 1 
G(s) = k p  1 +  (25.8)
 Ti s 
where
Kp-Proportional gain constant
Ti-Integral time constant
e (t)-Error value
Both Kp and Ti are adjustable. The integral time adjusts the control
action, while a change in the value of Kp affects both the proportional and
integral parts of action. The inverse of the integral time Ti is called the reset
rate. The reset rate is the number of times per minute that the proportional
part of the control action is duplicated. The reset rate is measured in terms
of repeats per minute.
The PI controller introduces a zero at s = -1/Ti and a pole at origin. Thus,
the characteristic of the PI controller is infinite gain at zero frequency. This
improves the steady-state characteristics. However, inclusion of the PI con-
trol action in the system increases the type number of the compensated
system by 1 and this causes the compensated system to be less stable or
even make the system unstable. Therefore, the values of Kp and Ti must be
chosen carefully to ensure a proper transient response. By properly design-
ing the PI controller it is possible to make the transient response to a step
input exhibit relatively small or no overshoot. The speed response, how-
ever, becomes much slower. This is because the PI controller, being a low-
pass filter, attenuates the high-frequency components of the signal.
25.3.3 Backstepping Controller Design

Backstepping is a recursive Lyapunov-based scheme proposed in the begin-
ning of the 1990s. The technique was comprehensively addressed by Krstic,
Kanellakopoulos, and Kokotovic. The idea of backstepping is to design a
controller recursively by considering some of the state variables as “virtual
controls” and designing for them intermediate control laws. Backstepping
achieves the goals of stabilization and tracking. The proof of these proper-
ties is a direct consequence of the recursive procedure because a Lyapunov
function is constructed for the entire system including the parameter esti-
mates. The control objective is to design a robust controller for achieving
desired voltage or speed. The backstepping design to achieve the voltage or
speed tracking is described with a step by step procedure.
Backstepping starts with the system equation which is the farthest from
the control input and reaches the control input at the last step. Consider an
Nth order system for the design. Backstepping design procedure starts in
output side (voltage or speed) and is derived when the intermediate control
law finally reaches the control input (duty ratio) of system. Backstepping
control design for Nth order system block diagram is shown in Figure 25.4.
1 1 1 1
s .... s s s
x3 x2 x1
u
State N state3 state2 state1 Output
control law virtual control3 virtual control2 virtual control1
Step N Step3 Step2 Step1
Figure 25.4 N-step backstepping control.

25.3.4 Backstepping Control Algorithm

Backstepping controller for Nth order system can be explained in a step by
step procedure:
1. Define all state variables.

2. Number of Backsteps = Number of state variables
3. Find the state variable to be controlled (SVC)
4. Define Virtual State Variable (VSV) = SVC-DV, where DV-
Desired Value
5. Find the virtual control law in such a way that the aug-
mented Lyapunov function for the VSV will become nega-
tive definite.
6. Repeat the steps equal to the number of state variables.
7. Find the value of control input in terms of other state vari-
ables in the last step so that the corresponding Lyapunov
function will be negative definite.
25.3.5 Controller Design for Buck Converter with R-Load

The state space models of Buck converter with R-load equations are given
below:
x 2 x1
x 1 = − (25.9)
C RC
x1 uE
x 2 = − + (25.10)
L L
where
x1-Average input current
x2 - Average output voltage
Step 1:
For the voltage tracking objective, find the tracking error
z1 = x1 – Vd (25.11)
and its derivative as:
z 1 = x 1 − Vd (25.12)
1
The first Lyapunov function is chosen as: V1 = z12 (25.13)
2
Then, the derivative of V1 is V 1 = z1 z 1

Then. (25.14)
Substituting the z 1 value in the above equation becomes
V 1 = z1 (x 1 − V d ) (25.15)
 x 2 x1  
V 1 = z1 − − Vd (25.16)
 C RC 
x
In (25.19), 2 can be viewed as the virtual control and define the fol-
C
lowing stabilizing function:
x1 
∝1 = −c1 z1 + + Vd (25.17)
RC
where c1 is the positive constant. The second regulated variable is chosen as
x2
z2 = − ∝1 (25.18)
C
V 1 = z1 z 1 = −c1z12 + z1z 2 (25.19)
When z2 = 0, then only the above Lyapunov function will be negative

definite. So, to compensate, the second regulated variable chooses the
appropriate virtual control law shown in Step 2.
Step 2: Hence, the derivative of the second regulated variable is calcu-
lated as
x 2
z 2 = x 2 −∝
1 (25.20)
C
x2 x1 
∝⋅1 = c12z1 − c1z 2 + 2 − + Vd (25.21)
RC RC
Applying the Lyapunov function to stabilize the second state:
V 2 = z1 z 1 + z 2 z 2 (25.22)
V 2 = −c1z12 − c 2z 22 + z 2 ( z1 + z 2 + c 2 z 2 ) (25.23)
LC  2 x2  1 1  d 
u=  −z1 –c 2 z 2 + c1 z1 − c1z 2 + 2 − 2 2 − x1 + V
E RC R C CL  

(25.24)
The control law is
LC  2 x2  1 1  d  .
u=  (c1 − 1)z1 –(c1 + c 2 )z 2 + 2 − 2 2 − x1 + V
E RC R C CL  

(25.25)
Controller Design for Buck Converter with PM DC Motor

The Buck converter fed DC motor is a fourth order system. Therefore, four
steps are involved in the backstepping controller design procedure. These
four steps are explained below:
f k T
x 1 = − x1 + x 2 − L (25.26)
J J J
k R x
x 2 = − x1 − m x 2 + 3 (25.27)
Lm Lm Lm
x4 x2
x 3 = − (25.28)
C C
x 3 uE
x 4 = − + (25.29)
L L
where
x1 - Average angular velocity
x2 - Average motor armature current
x3 - Converter output voltage
x4 - Converter inductor current
Step 1:
First find the Tracking error
z1 = x1 – ωr (25.30)
Take its derivative z 1 = x 1 − ω r (25.31)
f k T
z 1 = − x1 + x 2 − L − ω r (25.32)
J J J
Applying the Lyapunov function, stabilize the first state
1
V1 = z12 (25.33)
2
Take the derivative of V1:
V 1 = z1 z 1 (25.34)
V 1 = z1 z 1 = −c1z12 + c1z12 + z1 z 1 (25.35)
V 1 = −c1z12 + z1 (c1 z1 + z 1 ) (25.36)
 f k T 
V 1 = −c1z12 + z1  c1z1 − x1 + x 2 − L − ω r  (25.37)
 J J J 
k
In (25.42) x 2 can be viewed as the virtual control and define the fol-
J
lowing stabilizing function:
f T
∝1 = x1 + L + ω r − c1 z1 (25.38)
J J
where c1 is the positive constant. The second regulated variable is chosen

as:
k
z2 = x 2 − ∝1 (25.39)
J
Pr oofWhen
Proof: : When
thethe Step1negative
Step1is is negative definite
definite
 f T 
V 1 = −c1z12 + z1  c1 z1 − x1 + z 2 + ∝1 − L − ω r  (25.40)
 J J 
f T
z 1 = − x1 + z 2 + ∝1 − L − ω r = −c1z1 + z 2 (25.41)
J J
Put ∝1 in z 1
z 1 = −c1z1 + z 2 (25.42)
When z2 = 0, then only above the Lyapunov function will be negative

definite. So, we compensate the second regulated variable by choose the
appropriate virtual control law, shown in Step 2.
Step 2:
Find the next state error and find ∝.1 . We can substitute the follwing
equations and stabilize the second state using virtual variable:
k
z2 = x 2 − ∝1 (25.43)
J
k
z 2 = x 2 − ∝.1
J
Take its derivative
f
 r − c1 z 1
∝.1 = x 1 + ω (25.44)
J
f f k T 
∝.1 =  − x1 + x 2 − L  + ω
 r − c1 z 1 (25.45)
J J J J 
 f f   k k   R k  f k
z 2 =   ∗  −  ∗   x1 +   m ∗  −  ∗   x 2
  J J   J Lm     Lm J   J J  
k fT
+ x 3 + 2L − ω
 r + c1 (−c1z1 + z 2 ) (25.46)
JL m J
Applying the Lyapunov function, stabilize the second state:
V 2 = −c1z12 + z1z 2 + z1 z 2 (25.47)
V 2 = −c1z12 − c 2z 22 + z 2 (c 2z 2 + z1 + z 2 ) (25.48)
k
Then, x 3 can be viewed as the virtual control and define the follow-
JL m
ing stabilizing function.
Second state virtual control variable
 kk22 ff22  kR
kR fk fk fT
fT
∝∝22== −− 22xx11++ mm −− 22xx22−− 2L2L
JL
JLmm JJ   JL
JLmm JJ  JJ
ω
++ω r r++cc1122zz11−−cc11zz22−−cc22zz22−−zz11 (25.49)
f TL
∝2 = b1x1 + b2 x 2 − 
2 + ω r + (c1 − 1)z1 − (c1 + c 2 )z 2
2 (25.50)
J
 k2 f 2   kR fk 
where b1 =  − 2  , b2 =  m + 2  (25.51)
 JL m J   JL m J 
Step 3: Similarly, find the error variable to stabilize the state:
k
z3 = x 3 − ∝2 (25.52)
JL m
k
z 3 = x 3 − ∝.12 (25.53)
JL m
r + (c12 − 1) z 1 − (c1 + c 2 ) z 2

∝. 2 = b1 x 1 + b2 x 2 + ω (25.54)
k  x4 x2  .
z 3 = − − ∝2 (25.55)
JL m  C C 
k  x4 x2 
Z 3 = − − ( b1 x 1 + b2 x 2 + ω
r + (c12 − 1) z 1 –(c1 + c 2 ) z 2 )
JL m  C C 
(25.56)
k  x4 x2    f k T 
z 3 = − −  b1  − x1 + x 2 − L 
JL m  C C    j j J 
 k R x  
+ b2  − x1 − m x 2 + 3  + ω
r + (c12 − 1) z 1 − (c1 + c 2 ) z 2 
 Lm Lm Lm  
(25.57)
 bb kk bb ff   kk bb kk bb RR  bb kkxx
zz33 == 22 ++ 11  xx11−− ++ 11 −− 22 mm xx22 −− 22 xx33 44 −−ω
rr
ω
 LLmm JJ   JCL
JCLmm jj LLmm  LLmm JL JLmmcc
bb11 TTLL
(c1133−−cc11)z
++(c (c1122 −−cc2222 ++cc11cc22−−1)z
)z11−−(c 1)z22++(c
(c11++cc22)z
)z33++ (25.58)
JJ

Similarly, apply the Lyapunov function to stabilize the third state:
V 3 = −c1z12 − c 2z 22 − c 3z 32 + z 3 (c 3z 3 + z 2 + z 3 ) (25.59)
 b k b f b k  b fk  bk kb f 
V 3 = −c1z12 V−3c=2z−22c−
1zc
2 2 +
1 3z
−3cV  2 3 (c
2z3z2 =
2
−−c3cz31z3z32+ z(22z3z3−3c+3z2z322 + (zz313(c3zx231 +−+z 2 1+ (zx3 1 − 2 + 1  x1 −
−zz2c3+2(c
1 +
 Lm J  L m  JCL J m  LmJCL mJ 
f ( z  b21k +k b12fRmbx1k−  b2bkR2 m  b1kkxb4 2b2Rm kx 43 b2
 b3z23k+ zb21+ kx
++(zz 33 (c 3 24− c 2 2 3 2 2
 L + J  x31+ −L − J + 1 x−2−JCL x+3 x+2 − − −xω
J L
JCL m m J  L JL
J c L 3+ r+

x 21−− cω
(c
L
1 r)z − (c
+
x+31(c 1 1− c
JL c
)z2ω1+−r c+(c
1− 1c12 1− −
(c c 2c+ c11c−2 (c1 −
1 )z
m m m 
m m L m m JL mc m
m m
2 kx 4 b T  b T  b T 
ωr x+3(c+13JL− cc1 )z −r (c
− 1ω 2 −31)z
+ 1(c 1 c−2 c+12 )z
2 + (c− +
c1c1 21 (c
2
−2 c+3 22+(c+1c1+1ccL22−)z1)z
c1 2 )z
− 1)z )3 +2 +1(c1L + c) 2 )z 3 + 1 L  )
m m J  J  J 
1 TL  (25.60)
)
J 
k x4
In (25.58), can be viewed as the virtual control and define the
JL mC
following stabilizing function.
Third state virtual control variable is
 bb kk bb ff   kk bb1kk bb2RR m bb2 bb1TTL

∝33==−− 22 ++ 11 xx11++
∝ ++ 1 −− 2 m xx22++ 2 xx33−− 1 L
 LLmm JJ  JCL
JCLmm JJ LLmm  LLmm JJ
++ωrr −−(c

ω (c1133−−cc11)z (c1122−−cc2222++cc11cc22−−2)z
)z11++(c 2)z22−−(c
(c11++cc22++cc33)z
)z33 (25.61)
b bb2T b1 TL
∝3 = − b3 ∝
x13+= b−4bx32x+1 + b2 4xx32 −+ L1 xL 3+−ω
r − (c+ r − (c13 − c12)z1 +2 (c12 − c 22 + c1c 2 − 2)z 2
3ω
J 1 − c1 )z1 + (c1 − c 2 + c1c 2 − 2)z 2
Lm J
m
− + +
− (c1 + c 2 + c13 )z 3 2 c 3 )z 3
(c c (25.62)

b k bf  k bk bR 
where b3 =  2 + 1  , b4 =  + 1 − 2 m
 Lm J   JCL m J Lm 
Step 4: Similarly, find the state error variable of the next state applying
the Lyapunou function
k
z4 = x 4 −∝3 (25.63)
JCL m
k
z 4 = x 4 −∝.3 (25.64)
JCL m
k  x 3 uE  .
z 4 = − + −∝3 (25.65)
JCL m  L L 
bb
∝∝3 3==−−
. .
bb3 3x x1 1++bb4 4x x2 2++ 2 2x x3 3++ωω(4) . .
(4)−− (c(c1313−−c1c)z 1 )z
1 1
LLmm
++(c(c1212−−c c22 22++c1cc1c2 −2 −2)2)z z2 −2 −(c(c1 1++c c2 2++c c3 )3 z) z3 3 (25.66)
 ff kk TTL 
  kk RRm xx3 

∝
∝3.3 ==−−bb33−− J xx11++ J xx22 −− J L ++bb44−−L m xx11−− L mm xx22 ++L m3 
.
 J J J   Lm Lm Lm 
b x x 
++ b22  x44 −− x22  ++ω ω
. 3
. − (c1 3− c1 )z
− −
1 + (c122 + c 222 + c1c 2 − 2) z2
(c c )z 1 + (c1 + c 2 + c1c 2 − 2) z 2
(4)

LLm  CC CC   (4) 1 1
m
−−(c 
(c11++cc22 ++cc33))zz33 (25.67)
 f f kk TT    kk RR xx   bb  xx xx  
∝∝ bb3 3 −− xx1 1++ xx2 2−− L L ++bb4 4 −− xx1 1−− mmxx2 2++ 3 3 ++ 2 2  4 4−− 2 2 
.3 .3==−−
 J J JJ J J    LLmm LLmm LLmm  LLmm CC CC 
. .
++ωω(4) (c(c1313−−c1c)(
(4)−− ) +(c(c1212++c c22 22++c1cc1 c2 −2 −2)(
−−c1cz11z1++z z2 )2 +
1 )( 2)(−−c c2z2z2 +2 +z z3 )3 )
−−(c(c1 −1 −c c2 +2 +c c3 )( −−c c3z3z3 +3 +z z4 )4 )
3 )( (25.68)
k  x uE   f k T   k R x 
zz4 == k −− x33 ++ uE ++bb3 −− f xx1 ++ k xx2 −− TLL  −−bb4 −− k xx1 −− Rmm xx2 ++ x33 
4 JCL  L L  3 J 1 J 2 J 
 4 L 1 L 2 L 
JCLmm  L L   J J J   Lmm Lmm Lmm 
bb2  xx4 xx2  . 3 2 2
−− 2  4 −− 2  −−ω . + (c1 3 − c1 )( − c1z1 + z 2 ) − (c1 2 + c 22 + c1 c 2 − 2)( − c 2z 2 + z 3 )
LLm  C C  ω(4) (4) + (c1 − c1 )( − c1z1 + z 2 ) − (c1 + c 2 + c1 c 2 − 2)( − c 2z 2 + z 3 )
m C C
++(c
(c1 −−cc2 ++cc3 )(
)(−−cc3zz3 ++zz4 )) (25.69)
1 2 3 3 3 4

uE b k b f b R bk b 
z 4 = +  4 − 3  x1 +  4 m − 3 + 2  x 2
JLCL m  Lm J   Lm J L mC 
 −k b  b bT
+ − 4  x 3 − 2 x 4 − 3 L − ω (4)
.
 JLCL m L m  CL m J
+ (−c14 + c12 )z1 + (c13 + c 32 + c12c 2 + c1c 22 − 2c 2 − c1 )z 2
− (c12 + c 22 + c 32 + c1c 2 + c1c 3 + c 2c 3 − 2)z 3 + (c1 + c 2 + c 3 )z 4 (25.70)
Similarly, apply the Lyapunov function and stabilize the final state.
V 4 − c1z12 − c 2z 22 − c 3z 32 − c 4z 24 + z 4 (c 4z 4 + z 3 + z 4 ) (25.71)
Final control law is
JLCLm  b2 b T .
u=  b5 x1 − b6 x 2 + b7 x 3 + x 4 + 3 L + ω (4) − (−c14 − c12 )z1
E  CL m J
− (c13 + c 32 + c12 c 2 + c1c 22 − 2c 2 − c1 )z 2
+ (c12 + c 22 + c 32 + c1c 2 + c1c 3 + c 2c 3 − 3)z 3
−(c1 + c 2 + c 3 + c 4 )z 4 } (25.72)
 −b k b f  b R bk b   k b 
where b5 =  4 + 3  , b6 =  4 m + 3 + 2  , b7 =  + 4 .
 Lm J   Lm J L mC   JLCL m L m 
 b R b k b   k b 
b6 =  4 m + 3 + 2  , b7 =  + 4 .
 Lm J L
m C   JLCL m L m
The PI and Backstepping controller with R load and PM DC motor load

design procedures were explained.
25.4 Simulation Results

The circuit parameters for a Buck converter with R load are shown in the
Table 25.1.
The load resistance of a Buck converter with a PI/Backstepping
Controller under load variation condition is shown in Figure 25.5.
Table 25.1 Buck converter with R load circuit parameters.

S. no. Parameters Symbols Values
1 Load Resistance R 30 Ω, 40 Ω
2 Filter Inductor L 20 mH
3 Filter Capacitance C 68
4 Supply Voltage E 15V
5 Desired Voltage Vd 5V
Resistive load
60
50
Resistance (Ohms)
40
30
20
10
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (sec)
Figure 25.5 Resistive load.
The load resistance is changed from 30Ω to 40 Ω at 0.4 seconds. Then,

again, the load resistance is changed from 40Ω to 30 Ω at 0.6 Seconds.
The output voltage of a Buck converter with a PI controller is shown in
Figure 25.6. During the load variation from 30Ω to 40Ω, the output voltage
exhibits overshoot and it is settled at 0.057 sec. When the load resistance is
PI controller output voltage for Buck converter with R load

8
7
kp=1 ki=200
6
Output voltage (volts)
5
4
3
2
1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (sec)
Figure 25.6 PI controller output voltage for buck converter with R load.
Backstepping controller output voltage for Buck converter with R load

8
7
c1=100 c2=390
6
Output voltage (volts)
5
4
3
2
1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (sec)
Figure 25.7 Backstepping controller output voltage for buck converter with R load.
decreased from 40Ω to 30 Ω, the output voltage exhibits overshoot and the
settling time was 0.057 sec.
The output voltage of a Buck converter with a Backstepping controller is
shown in Figure 25.7. During the load variation periods, the settling times
were 0.0326 sec and 0.055 sec. Though the overshoot for a Backstepping
controller is more than a PI Controller, the settling time was less. These
details are mentioned in Table 25.2
The Buck converter with PM DC motor parameters is shown in Table
25.3.
The load torque of the PM DC motor with load torque variation is
shown in Figure 25.8. The load torque is changed and varies from (0.05 -
0.07) N-m at 1.5 sec. Then, again, the load torque is changed to vary from
(0.07 - 0.05) N-m at 2.5 sec.
The output speed of a PI controller with a Buck converter fed PM DC
motor is shown in Figure 25.9. During the load variation from 0.05N-m
to 0.07 N-m, the speed exhibits undershoot and the settling time for the
response is 0.550 sec. When the load torque is decreased from 0.07 N-m to
0.05 N-m, the speed exhibits overshoot and the settling time was 0.550 sec.
The output speed response of a Buck converter fed PM DC motor with a
Backstepping controller is shown in Figure 25.10. During the load torque vari-
ation profile at 1.5 seconds, the settling time was 0.062 sec and at 2.5 seconds,
the settling time was 0.062 sec. These details are mentioned in Table 25.4.
25.5 Hardware Details

The general block diagram for a closed loop control Buck converter with a
UC3524 controller with load is shown below (Figure 25.11). The converter
output (voltage) is fed to the controller UC3524. Then, the controller will
Table 25.2 R Load output comparison.

PI controller Backstepping controller
Desired Overshoot/ Settling Overshoot/ Settling
Time voltage Load undershoot time undershoot time
S. no. (sec) (V) resistance (Ω) (V) (sec) (V) (sec)
1 0.0 - 0.4 5.0 30 - 0.290 - 0.0920
2 0.4 – 0.6 5.0 40 5.48 0.057 6.18 0.0326
3 0.6 – 1.0 5.0 30 4.47 0.057 4.00 0.055
Table 25.3 Buck converter with PM DC motor load circuit

parameters.
S. no. Parameters Symbols Values
1 Filter Inductor L 20e-3 H
2 Filter Capacitor C 400e-6 F
3 Motor Constant K 0.046
4 Moment of Inertia J 7.06e-5 kg*m2
5 Friction Coefficient F 8.42e-4 N-m/rad
6 Motor Inductor Lm 2.63e-3 H
7 Motor Resistance Rm 2.0 Ω
8 Supply Coltage E 12 V
9 Load Torque TL 0.05 N-m, 0.07 N-m
10 Desired Speed ωd 50 rad/sec
PM DC Motor load
0.1
0.09
0.08
0.07
Load torque (N-m)
0.06
0.05
0.04
0.03
0.02
0.01
0
0 0.5 1 1.5 2 2.5 3 3.5 4
Time (sec)
Figure 25.8 PM DC motor load torque.
PI controller output speed for Buck converter with PM DC motor

80
70
kp=0.0072 ki=0.1
60
Load torque (N-m)
50
40
30
20
10
0
0 0.5 1 1.5 2 2.5 3 3.5 4
Time (sec)
Figure 25.9 PI controller output speed for buck converter with PM DC motor.
Backstepping controller output speed for Buck converter with PM DC motor

80
70
c1=5000 c2=7000 c3=2250 c4=100
60
Output speed (rad/sec)
50
40
30
20
10
0
0 0.5 1 1.5 2 2.5 3 3.5 4
Time (sec)
Figure 25.10 Backstepping controller output speed for buck converter with PM DC
motor.
decide the necessary action to achieve the reference value. The controller
output signal is to control the Buck converter switching period to keep the
reference value in the Buck converter output.
25.5.1 Buck Converter Specifications

The most common power converter topology is the Buck power con-
verter, sometimes called a step down power converter. Power supply
designers choose the Buck power converter because the output voltage
is always less than the input voltage in the same polarity and is not iso-
lated from the input. The Buck converter circuit diagram is shown in
Figure 25.12.
The buck regulator circuit is a switching regulator, as shown in Figure
25.11. It uses an inductor and a capacitor as energy storage elements so
that energy can be transferred from the input to the output in discrete
packets. The advantage of using switching regulators is that they offer
higher efficiency than linear regulators. The one disadvantage is noise
or ripple; the ripple will need to be minimized through careful compo-
nent selection.
To reduce output voltage ripple, the switching frequency should be
increased but this lowers efficiency. This means that the selection of the
switching devices will be an important issue. The output voltage ripple can
also be reduced by increasing the output capacitance; this means a large
capacitor in practical design.
Table 25.4 PMDC motor load output comparison.

PI controller Backstepping controller
Desired Overshoot/ Overshoot/
Time speed Load torque undershoot Settling time undershoot Settling time
S. no. (sec) (rad/sec) (N-m) (rad/sec) (sec) (rad/sec) (sec)
1 0.0 - 1.5 50.0 0.05 - 0.770 - 0.1210
2 1.5 – 2.5 50.0 0.07 45.0 0.550 - 0.0620
3 2.5 – 4.0 50.0 0.05 55.0 0.550 - 0.0620
POWER BUCK
LOAD
SUPPLY CONVERTER
PWM
UC 3524
REFERENCE
VOLTAGE
Figure 25.11 Buck converter with UC3524 controller.
main MOSFET Inductor
Vdc Control Capacitor Load

Circuit Diode
Figure 25.12 Buck converter.
The input current for a Buck power converter is discontinuous due to

the power switch and the current pulses from zero to maximum every
switching cycle. The output current for a Buck power converter is contin-
uous because the output current is supplied by the output inductor/capac-
itor combination.
The Buck converter constructed for this thesis is 1.0kW with a refer-
ence voltage of output voltage 225V and nominal input voltage of 313V.
This combination of Vout and Vin yields a steadystate duty ratio of 0.71. The
MOSFET switching frequency selected is 22kHz. The buck converter filter
inductance value is 2.15mH and filter capacitance value is 0.1µF.
25.5.2 Advanced Regulating Pulse Width Modulator

The UC3524 semiconducting device can do the operations of regulated
power supply, inverters, etc. The high power drive application controller is
designed by using UC3524. It is operated on the principle of pulse width
VREF VIN EB CB CA EA S/D COMP
16 15 14 13 12 11 10 9
REFERENCE
REGULATOR S/D
ERROR CURRENT
AMP AMP
OSCILLATOR
+
+
_
1 2 3 4 5 6 7 8
INV INPUT NON INV OSC OUT CL CL RT CT GND

INPUT SENSE(+) SENSE(--)
Figure 25.13 Advanced regulating pulse width modulator.
modulation techniques. The UC3524 analog controller connection dia-

gram is shown in Figure 25.13.
25.5.3 Principles of Operation

The UC3524 is an operating fixed frequency PWM, voltage regulator,
and control circuit. The frequency depends on a one-timing resistor (RT),
one-timing capacitor (CT), and a constant charging current for CT.
The UC3524 has an internal 5V regulator for the purpose of reference,
internal circuit control, and external interfacing. Also, a voltage divider is
used to set operating modes. Based on the feedback signal, UC3524 can
produce PWM signals so that the desired output voltage is achieved. The
oscillator frequency of UC3524 is related with RT and the CT relationship
is given below.
1.18
Frequency f = (25.73)
R TC T
where
RT – Timing resistor
CT – Timing capacitor
The hardware details of Buck converter circuit components and an

advanced regulating pulse width modulator UC3524 controller were
explained.
25.6 Hardware Results

This chapter explains the hardware results for the closed loop control of a
Buck converter with a UC3524 controller.
The Buck converter experimental setup of a closed loop control
Buck converter with a UC3524 controller is shown in Figure 25.14. The
buck converter input voltage waveform is shown in Figure 25.15. Here,
the buck converter input DC voltage is 313 volts and reference output volt-
age is 225 volts.
Figure 25.14 Buck converter with UC 3524 experimental setup.

TPS 2014 - 3:44:41 PM 3/18/2011
Figure 25.15 Buck converter DC input voltage.
Figure 25.16 represents the PWM signals for the buck converter under
unloaded conditions to achieve the corresponding output voltage shown
in Figure 25.17.
TPS 2014 - 3:27:00 PM 3/18/2011
Figure 25.16 UC3524 controller PWM output signal.

TPS 2014 - 3:22:08 PM 3/18/2011
Figure 25.17 Buck converter output voltage.
The buck converter with UC 3524 controller output voltage is shown in

Figure 25.17. Here, the reference value 225V is reached.
25.7 Conclusion
This book chapter describes the Backstepping controller design scheme for
a Buck converter with R load and a PM DC motor. Step by step control
design and stability analysis are given and the effectiveness of backstepping
controller design is demonstrated through computer simulations. In addi-
tion, PI controller performance is compared with the Backstepping con-
troller. Simulation results with R-load with load disturbance reveals that the
output voltage settling time for PI controllers is more than a Backstepping
Controller and the overshoots are higher in the backstepping controller
than in the PI controller. A simulation study with DC motor with load
disturbance indicates that the output speed settling time for the PI con-
troller is more than the Backstepping Controller. The simulation results
have clearly illustrated that the proposed backstepping controllers are quite
effective and efficient for a PM DC machine. The closed loop operation of a
Buck converter with a UC3524 controller is implemented and tested under
no-load conditions.
References
1. Jianguo Zhou, Youyi Wang and Rujing Zhou. Adaptive backstepping con-
trol of separately excited DC motor with uncertainties. IEEE International
Conference on Power System Technology, Page(s): 91 - 96 vol. 1, 2000.
2. El Fadil. H, Giri. F, Haloua. m and Ouadi. H “Nonlinear and Adaptive
Control of Buck Converters”. IEEE Conference on Decision and Control,
Hawali USA, Dec 2003.
3. Liu. Zuo Z, Luo.Fang L, and Rashid Muhammad H. “Adaptive MIMO
Backstepping Controller for High-Performance DC motor field weakening”.
Taylor & Francis on Electric Power Components and Systems, 31: 913–924,
2003.
4. Uran, S and Milanovic, M. State controller for buck converter. IEEE Region
8 Conference EUROCON 2003 , pp: 381 – 385, vol. 1, 2003.
5. Shoei-Chuen Lin and Ching-Chih Tsai. Adaptive voltage regulation of PWM
buck DC-DC converters using backstepping sliding mode control. IEEE
International Conference on Control Applications, pp: 1382 - 1387, vol. 2,
2004.
6. El Fadil and Giri.F, “Accounting of DC –DC Power converter dynamics in DC
motor velocity adaptive control”. IEEE Conference on Control, Applications,
Germany, Oct 2006.
7. Erdem, H. Comparison of fuzzy, PI and fixed frequency sliding mode con-
troller for DC-DC converters. IEEE International Aegean Conference on
Electrical Machines and Power Electronics, pp: 684 – 689, 2007.
8. Sreenu Kancherla and Tripathi. R.K. “Nonlinear Average Current Mode
Control for a DC-DC Buck Converter in Continuous and Discontinuous
conduction modes”. Tencon IEEE conference, pp: 1-6, 2008.
9. Chen Lanping, Ma Zhenghua, Duan Suolin. “Adaptive Speed Controller
Design Based on Backstepping for DC Motor System with Parameter
Uncertainities”. IEEE conference on intelligent computing and Intelligent
system, Shanghai, pp: 140-144, 2009.
10. Raja Ismail. R. M. T, Ahmad. M. A. and Ramli. M. S. “Modelling & Simulation
Speed Control of Buck-converter Driven Dc Motor Based on Smooth
Trajectory Tracking”. Third Asia International Conference, pp: 97–101, 2009.
26
Analysing Control Algorithms for
Controlling the Speed of BLDC
Motors Using Green IoT
V. Evelyn Brindha1 and X. Anitha Mary2*
Department of Electrical and Electronics Engineering, Karunya Institute of

1
Technology and Sciences, Coimbatore, Tamil Nadu, India

2
Department of Robotics Engineering, Karunya Institute of Technology and
Sciences, Coimbatore, Tamil Nadu, India
Abstract
In recent days, Brushless Direct Current (BLDC) are gaining popularity in many
fields because of its higher efficiency, noiseless operation and speed of operation
are high. One of the disadvantages of BLDC motor is that it requires sophisticated
control algorithms to control the speed. In this chapter, BLDC motor is discussed
with various control algorithms like PI, PID and artificial intelligence techniques
using MSP430 microcontroller. Later the application of Green IoT that helps in
remote controlling of motor in an energy efficient way is also discussed.
Keywords: Motor, BLDC, control algorithms, Green IoT
26.1 Introduction
Conventional DC motors, though highly efficient, are subjected to wear
and require frequent maintenance. On the other hand, Brushless Direct
Current (BLDC) motors are without brushes for commutation, which
results in less spark and maintenance cost. In a BLDC motor, the rotor is
779
made up of a permanent magnet and stator with coil windings. To know

the position of the rotor, the motor has inbuilt position sensors like photo
transistors, photodiodes, half effect devices, and incremental encoders.
The square wave generated from the motor is given to the driver module to
control the speed of the motor.
In recent days, BLDC have gained popularity in many fields such as
aerospace, consumer, medical instrumentation, and industrial automa
tion because of its higher efficiency, noiseless operation, and high speed of
operation. One of the disadvantages of the BLDC motor is that it requires
sophisticated control algorithms to control the speed. Various algorithms
like PI, PID, and other artificial intelligence techniques are used to control
the speed of the motor. In recent days Green IoT plays an important role in
remote control of motors. It not only controls the speed of the motor, but
also does it in an energy efficient way.
In this chapter, a BLDC motor is discussed with various control algo
rithms like PI, PID, and artificial intelligence techniques using an MSP430
microcontroller. Later, the application of Green IoT to help in remote con
trolling of motors in an energy efficient way is also discussed. Since BLDC
motors are weightless, reliable, and have high efficiency, they are broadly
applied in various industries. Hence, controlling the speed of the these
remotely using IoT would be very useful.
26.2 Working of BLDC Motor

As the name suggests, it is a DC motor that is brushless and has no com
mutator, but rather employs a control unit, rotary encoders, or hall sensors.
In a BLDC motor, the permanent magnets are attached to the rotor. On the
stator, the current carrying conductors or armature winding are situated.
Electrical switches are used to transform electrical energy into mechanical
energy. Figure 26.1 shows the different parts of the BLDC motor.
The main difference between brushed and brushless motor are as follows:
1. Speed range is high when compared to brushed, as BLDC

does not require brushes and commutators, thereby noise is
reduced and requires less maintenance.
2. The characteristics of speed/torque are high as mechanical
parts involved are less and thereby reduce building cost.
3. As there are no electrical and friction losses, efficiency is
higher.
Controlling the Speed of BLDC Motors Using Green IoT 781
Rotar Stator Hall effect sensor
Permanent magnet
Figure 26.1 Parts of BLDC motor (Source: [1]).
26.3 Speed Control of Motor

To know the position of the rotor and rotor movement in terms of turns,
either sensored commutation or sensorless commutations are used. The
sensored commutation uses hall sensors and sensorless commutation
analyses the back emf generated in the stator winding and has the dis
advantage of no emf generated, which produces a jerk during starting of
the motor. In order to have good starting torque, hall effect sensors are
used.
Figure 26.2 shows the different types of BLDC motor depending on the
turns as single phase, two phase, and three phases [2].
The speed controller of the BLDC motor is important to find the work
ing of motors at the desired speed, which can be controlled using vari
able DC voltage or current. There are two types of speed control: open and
closed.
(I) Open Loop Speed Control

In an open loop controller, the output is not fed back and thereby has the
advantage of simplicity and lower cost (Figure 26.3).
The control input can be analog or digital. The analog controller input
will be given in the form of a potentiometer which increases or decreases
the PWM duty cycle. The variable PWM duty cycle helps in varying the
speed of the motor. The controller used can be any microcontroller. For
implementation, an MSP430 microcontroller is used. The analog input is
fed to a 12 bit ADC which counts from 0 to 212, representing 0% to 100%.
(a) (b) (c)
Figure 26.2 Different phases of BLDC motors: (a) single phase; (b) two phase; (c) three
phase.
Open loop speed Driver BLDC

Control Input circuit
controller Motor
Figure 26.3 Open loop control.
In the case of a sensored BLDC motor, the hall sensor signal is fed to
the microcontroller through the GPIO pins. The PWM signal is fed to the
driver module for running the motor. Figure 26.4 shows the flow chart
for open loop speed control of a BLDC motor. The time taken from input
phase to the output phase is approximately 9 microseconds.
(ii) Closed Loop Control

The closed loop control uses feedback to regulate the speed of the motor to
the desired rate. It consists of an input block, closed loop controller, motor
driver feedback block, and motor or actuator (Figure 26.5).
In open loop control, the speed of the motor depends on the current
input, but in closed loop, the speed depends on the current input and feed
back (actual motor speed). Various algorithms like PI and PID control
lers can be used to control the speed by updating the PWM duty cycle.
The speed input is given to the microcontroller using a potentiometer.
START
Initializing phase:
1. Configure Microcontroller
2. Set system clock to 16 MHz
3. Connect hall sensor wires to
GPIO pins
4. Set Timer B in PWM mode
Start of Conversion
ADC by enabling ISR
Conversion process of
PWM signal
NO
End of
conversion
(return from
ISR)
YES
Digital input to the driver

module
STOP
Figure 26.4 Flowchart of open loop speed control using MSP430.
Micro-Controller
Input BLDC Driver unit Motor
(control algorithm)
Feed back control
Figure 26.5 Closed loop speed control.

The 12 bit ADC will give the counts to timer B. By varying the Kp and
Ki values, the PWM duty cycle update can be given to the driver module
through timer B. Here, Kp and Ki are the tuning parameters called propor
tional and integral constants (Figure 26.6).
For a 3 phase BLDC motor, given the number of poles to be 6, the maxi
mum speed required is 4000 rpm and the maximum electrical rotation per
second is given by Equation 26.1:
required maximumspeed noof poles

=
Maximumelectricalrotation ∗
60 2
4000 6 (26.1)
= ∗ = 200
60 2

One electrical rotation has six hall states and the maximum speed in
rpm is given by Equation 26.2.
200*6 = 1200 rpm (26.2)
The difference between expected speed and measured speed gives the
proportional error and these errors are accumulated to give the integral
error.
PI controller output = (Kp * proportional error)+ Ki* Integral error)
A PI controller can be used as a PID by inserting the Kd value.
PID duty cycle = desired duty cycle + (PI controller output)/division
factor.
Apart from PI and PID, recently algorithms like fuzzy controllers, arti
ficial neural networks, and machine learning based algorithms are used.
Shanmugasundram et al. [3] uses various controllers like fuzzy logic and
hybrid neural networks to control the speed. PID for speed control is
implemented with neural network controllers [4–7]. Optimization algo
rithms like particle swarm optimization [8], adaptive fuzzy logic [9], bio
inspired algorithms [10], and firefly algorithms [11–13] are used for tuning
the controller parameters of PID controllers.
START
Initializing phase:
Configure Microcontroller
1. Set system clock to 16 MHz
2. Connect hall sensor wires to GPIO pins
3. Set Timer B in PWM mode
4. configure Timer A as feedback timer
Start of Conversion
ADC bv enabling ISR
Conversion process of
PWM signal
NO End of
conversion
(return
from ISR)
YES
Select the value of Kp, Ki depending on the
desired PWM cycle
Execute PI controller
1. Compute errors
2. Implement controller
equations
3. Send PI controller output to
update PWM duty cycle.
Is desired
speed
achieved
STOP
Figure 26.6 Flowchart for closed loop speed control with MSP430 microcontroller.
26.4 Speed Control of BLDC Motor with FPGA

The Field Programmable Gate Array (FPGA) is the sensorless control tech
nique which uses a PWM control scheme like a microcontroller. FPGA
consists of a combinational logic block which is interconnected using
programmable horizontal and vertical channels. The logic blocks are sur
rounded by input/output blocks in order to communicate with the user.
In high speed applications, there is a problem of undesirable commuta
tion delay, which can be overcome by measuring the voltage and current
control scheme [14]. The analog input can be given to the ADC convertor
using the potentiometer. The voltage variations are fed to the FPGA for
programming control algorithms. Further, it can be given to the inverter/
driver module to the BLDC motor for controlling the speed (Figure 26.7).
26.5 Advancements in Green IoT for BLDC Motors

The Internet of Things has the potential to change the world. The world has
completely taken a different shape and we can divide into two eras: an era
before IoT and an era after IoT. Though all things and objects existed, they
were not connected before IoT. But now, each and every object and thing is
connected with each other. These things can interact, collaborate, and share
their experiences with each other. An IoT system or solution built by using
energy effectual hardware and software components in order to enable
reduction of power consumption is known as the Green Internet of Things
(GIoT). Green IoT design should concentrate on green design, green man
ufacturing, green adoption, green energy, and eventually green recycling
and/or green disposal, thus reducing its effect on the environment.
FPGA Inverter
Potentiometer ADC (Algorithm
for position
control of
rotor)
BLDC
Motor
Figure 26.7 FPGA based BLDC speed control.

BLDC uses electronics for brushes and commutators which have the
ability to operate in multiple speeds. The BLDC is otherwise called an
ECM or Electronically Commutated Motors Because of green fan technol
ogy, the materials used are lighter and thereby increase the efficiency. Solar
panels with green technology can be used for continuous power supply.
For the speed control, the microcontroller can be substituted with node
MCU which has an inbuilt Wifi module. Thus, the monitored parameters
like voltage, current, and speed can be monitored remotely either with a
mobile app or remote station.
26.6 Conclusion
The speed control of BLDC can be controlled using various algorithm
like PID and PI with a closed loop control scheme. This algorithm is pro
grammed using an MSP430 microcontroller. With advancements in green
technology, the BLDC can be fabricated with lightweight materials, higher
efficiency, and remote controlling.
References
1. Working of BLDC motor https://robu.in/brushless-dc-motor-working-
principle-construction-applications/
2. Difference between 2-phase and 3-phase https://www.bldcpump.com/diffe
rence-between-2-phase-and-3-phase/ dt June 22, 2018
3. Shanmugasundram, R.; Zakaraiah, K.M.; Yadaiah, N. Modeling, simulation
and analysis of controllers for brushless direct current motor drives. J. Vib.
Control 2013, 19, 1250–1264.
4. Arulmozhiyal, R.; Kandiban, R. Design of fuzzy PID controller for brush
less DC motor. In Proceedings of the 2012 International Conference on
Computer Communication and Informatics, Coimbatore, India, 10–12
January 2012; pp. 1–7.
5. Premkumar, K.; Manikandan, B. Adaptive neuro-fuzzy inference system
based speed controller for brushless DC motor. Neurocomputing 2014, 138,
260–270.
6. Al-Maliki, A.Y.; Iqbal, K. FLC-based PID controller tuning for sensorless
speed control of DC motor. In Proceedings of the 2018 IEEE International
Conference on Industrial Technology (ICIT), Lyon, France, 20–22 February
2018; pp. 169–174.
7. Mamadapur, A.; Mahadev, G.U. Speed Control of BLDC Motor Using
Neural Network Controller and PID Controller. In Proceedings of the 2019
2nd International Conference on Power and Embedded Drive Control

(ICPEDC), Chennai, India, 21–23 August 2019; pp. 146–151.
8. Liu, L.; Liu, Y.J.; Chen, C.P. Adaptive neural network control for a DC motor
system with dead-zone. Nonlinear Dyn. 2013, 72, 141–147.
9. Ibrahim, H.; Hassan, F.; Shomer, A.O. Optimal PID control of a brushless DC
motor using PSO and BF techniques. Ain Shams Eng. J. 2014, 5, 391–398.
10. Ramya, A.; Balaji, M.; Kamaraj, V. Adaptive MF tuned fuzzy logic speed con
troller for BLDC motor drive using ANN and PSO technique. J. Eng. 2019,
2019, 3947–3950.
11. Potnuru, D.; Mary, K.A.; Babu, C.S. Experimental implementation of Flower
Pollination Algorithm for speed controller of a BLDC motor. Ain Shams
Eng. J. 2019.
12. Wang, M.S.; Chen, S.C.; Shih, C.H. Speed control of brushless DC motor
by adaptive network-based fuzzy inference. Microsyst. Technol. 2018, 24,
33–39.
13. Templos-Santos, J.L.; Aguilar-Mejia, O.; Peralta-Sanchez, E.; Sosa-Cortez, R.
Parameter Tuning of PI Control for Speed Regulation of a PMSM Using Bio-
Inspired Algorithms. Algorithms 2019, 12, 54
14. Merugumalla, M.K.; Kumar, N.P. FFA-based speed control of BLDC motor
drive. Int. J. Intell. Eng. Inform. 2018, 6, 325–342.
Index
AC MG, 600, 601, 602 Bidirectional DC–DC Converters

Acoustic noise, 340, 345, 472 (BDC), 437, 442
Adaptive control, 602, 733, 746, 750, Bidirectional power flow control for
751, 778 MPC with HESS, 144
ADC converter, 783, 784, 785, 786 Binary equivalent, 213, 214, 215, 224,
Agent-based control, 613 227, 228, 229, 230, 248, 249, 250,
Alternate Phase Opposite Disposition 251, 252, 253, 254, 255, 256, 257,
(APOD), 208 258, 259, 260, 261, 262, 263, 264
Alternating Current (AC), 123, 126, Biogeography based optimization, 675,
343, 392 743
Analogue to Digital Converter (ADC), Bone, 337, 338, 339, 340, 341, 361, 362,
278 363, 365
Angles, 168, 183, 187, 204–215, Boost, 4, 5, 10, 12, 14, 15, 16, 17, 21,
223-230, 240, 248-264, 414, 424, 22, 23, 24, 25, 26, 27, 28, 29, 30,
425, 490, 564, 562 32, 33, 34, 35, 37, 38, 41, 42, 43,
Anisotropy, 464, 476, 490, 491 44, 48, 49, 50, 51, 53, 56, 57, 59,
Ant-Lion algorithm, 666 62, 66, 67, 58, 71, 75, 78, 80, 81,
Application of PBC, 724, 726 82, 83, 123
Armature winding, 780 Boost converter, 4, 10, 14, 15, 16, 17,
Asymmetric, 204, 248, 293, 391 443, 713
Automatic unmanned battery charging Boost/Boost-up resistance, 375
system, 517, 521 Brushless DC motor (BLDC), 337,
Average Voltage (VAVG), 274 339, 341, 342
Brushless Direct Current (BLDC)
Backlash, 754 motors, 779, 787
Backstepping controller, 749, 750, 751, Buck converter, 7, 8, 10, 15, 17, 26, 749
753, 754, 756, 757, 759, 761, 763, Buck converters, 26
765, 766, 767, 768, 769, 771, 772, Buck-boost converter, 27, 28, 30, 48,
773, 775, 777, 778 49, 50, 51, 52, 57
Bacteria foraging, 743
Bacterial forging (BFOA) optimization Carrier wave, 180, 208
algorithm, 667 Cascaded, 203, 208, 209, 210, 211, 212,
Bat algorithm, 667, 676 213, 215, 216, 217, 218, 219, 221
BBI (Buck Boost Inverter), 195 Cascaded H-bridge inverters, 293, 393
789
790 Index
CBMLI (Cascaded Bridge Multi Level Crow search algorithm, 290, 743
Inverter), 182 Crystal oscillator, 278
CB-PWM, 560 CSI (Current Source Inverter), 183
CCM (Continuous Conduction Cuckoo search, 668, 676, 744
Mode), 75, 86, 149, 155, 157, 543, Cuckoo search algorithm, 744
612 Cuk-converter, 10, 17, 29
Cdg/Miller capacitance, 377 Current harmonics, 337, 339, 340, 346,
Ceiling DC MG, 602 352, 353, 355, 357, 359, 360
Central Control, 603, 608, 614, 619 Current stress, 80, 92, 98, 110, 114,
Centralized Energy Management 115, 116, 117, 118, 119
System, 606 Current vector, 342, 351, 416
Challenges of MG control, 623, 624
Closed loop speed control, 783, 785 d axis, q axis inductance, 342, 361
Cogging, 412, 414, 421, 424, 433 Damping injection, 691, 617, 649, 682,
Communication-based energy 685, 686, 690, 696, 729
management scheme, 605, 608 Data analysis and communication,
Compact, 75, 79, 103, 105, 107, 112, 604
125, 293, 303, 304, 311, 443, 559, DC distribution, 64, 73, 74, 116, 121,
560 122, 125, 126, 601, 602
Component count, 79, 105, 112, 117, DC MG, 600, 601, 602
118 DC/Direct current, 370
Component utilisation ratio, 117, DC-DC converter, 3, 71, 72, 73, 74,
118 75, 79, 80, 84, 122, 123, 124, 176,
Configuration, 72, 73, 74, 83 540, 541, 542, 543, 544, 548, 553,
Continuous MPC, 347, 348 555, 557
Control design based on transfer DC-to-DC buck converters, 750
function, 616 Dead zone, 754
Control input, 636, 638, 640, 685, 688, Decentralized Energy Management
691, 697, 700, 707, 710–713, 718, System (DEMS), 607
752, 753, 756, 757, 781, 782 DFIG, 556, 585, 590
Control law generation, 686, 692, 727 Different structures of MG, 600
Control strategy of HESS, 447 Digital form, 225, 248
Cost function, 339, 340, 343, 346, 347, Digital Pulse Width Modulation
348, 349, 350, 351, 352, 353, 354, (DPWM), 203
360, 361, 583, 584, 585, 587, 589, Digital Switching Function (DSF), 204,
590, 618, 654 205, 215, 224, 231, 232, 234, 236,
Coupled inductor, 7, 43, 68, 71, 77, 78, 248, 265, 266
83, 101, 105, 122, 124, 125, 323, Digital Switching Pattern (DSP), 206,
344, 519 210, 231
Coupling coefficient, 94, 113, 114, 115, Diode clamped MLI, 162
117 Diode-clamped inverters, 293, 301
Coyote optimization algorithm, 668 DIR, 273
Cp/Piezo capacitance, 371 Direct Current (DC), 203, 471, 614,
Crest factor, 279, 290 633, 749, 779, 787
Index 791
Direct Lyapunov Control (DLC), 598, FACTs, 294, 296, 312

617 Faster Adoption and Manufacturing of
Direct Torque Control (DTC), 298, Electric Vehicle (FAME I), 318
343, 344, 345, 346, 347, 348, 355, FC system, 24
560, 578 Feed forward-switching angle
Distributed control, 613, 615, 616, algorithm, 203, 208, 209
733 Feedback decomposition, 683, 684
Distributed generation, 597, 659, 660, Field Oriented Control (FOC), 343,
663 344, 347, 355, 360
Distributed generator, 621, 660 Field Programmable Gate Array
Drive cycle, 464, 509, 512 (FPGA), 203, 204, 291, 292, 519,
Droop control, 616 786
Dual boost converter, 442, 444, 445, Finite Control Set MPC (FCSMPC),
457, 459 347, 348, 360
Dual In Pack (DIP) Switch, 278 Fluke Power Analyzer (FPA), 279, 289
Dual output, 533, 536, 537, 540, 545, Flux density, 412, 414, 415, 421, 422,
548, 550 464, 487, 488, 489, 498, 503, 506
DVR (Dynamic voltage restorer), 185, Flux linkage, 464, 476, 478, 480, 481,
186, 187 482
Dynamic model, 687, 752, 753 Flux ripple, 338, 340, 345, 346, 354,
356, 357
Electric vehicle, 317, 318, 319, 411, Flying capacitor inverter system, 391
540, 541, 542, 543, 552, 557 Form Factor (FF), 274
Electric Vehicle Service Equipment Forward/backward (F/B) sweep load
(EVSE), 317, 318, 320 flow, 664
Electric vehicles, 394 Fourier series, 168
EMC-Electromagnetic Compatibility, Frequency, 204, 208
176 Frequency response, 712, 713, 727
EMF constant, 753 Full load, 96, 97, 104, 106, 115
EMI-Electromagnetic Interference, Fuzzy, 731, 733, 744, 745, 751
137, 175, 176, 294 Fuzzy logic controller, 731, 733, 744
EN/Enable, 375
Energy management schemes, 605, Generation, 18, 68, 73, 121, 203
624 Genetic algorithm, 666
Energy storage system for MG, 608 Global warming, 463, 464
Equal phase-switching angle Gm/transconductance, 370
algorithm, 203, 208, 209 Gravitational search algorithm, 743
ESDI, 686 Grinding mills, 393
ETEDPOF, 687
Euler-Lagrange form, 645, 652, 681, Half equal phase-switching angle
683, 728 algorithm, 203, 208, 209, 218, 235
EV charging stations (EVCS), 317, 318, Half height-switching angle algorithm,
319, 320, 326, 536 203, 208, 209
Extreme duty ratios, 75, 76, 94 Hall effect sensors, 337, 339, 341, 781
792 Index
Hamiltonian, 681, 683, 684, 687, 698 Joint Test Action Group (JTAG)
Hard switching DC-DC converter, 4, 6 Programmer, 278
Hardware Description Language
(HDL), 203, 204, 205 LaSalle’s Theorem, 696, 697, 705, 706
Harmonic component, 168, 421, 423 LCC (Inductance Capacitance
HBI - H bridge inverter, 181 Capacitance), 136, 145, 146, 147,
H-Bridge, 204, 205, 206, 207, 208, 559
391 Leakage, 74, 78, 79, 84, 96, 114, 117,
HESS types, 441, 447, 448, 449 128, 137, 477, 480, 486
High frequency switching, 4 Lift converter, 7, 19, 68, 371, 372
High Gain Multi-Device Multi-Phase Light Emitting Diode (LED), 278
Interleaved Boost Converter Linear mode DC-DC converter, 4, 5
(HGMDMPIBC), 43 Liquid Crystal Display (LCD), 278
High voltage gain, 71, 79, 94, 104, 111, Load torque estimation, 628, 683, 695,
120, 122 719, 720, 721, 722, 723, 728, 729
High-frequency transformer (HFT), Load variation, 97, 326, 633, 648, 678,
137, 144 766, 767
HVDC, 4, 294, 312, 394, 559 Loss distribution inductance, 100, 101,
Hybrid AC/DC MG, 602, 627 111, 113, 116
Hybrid cascaded MLI, 167 Luo converter, 437, 442, 445, 456, 457,
Hybrid energy management systems, 459, 701, 710, 715, 718, 727, 728,
133, 147, 440, 437 729
Hybrid Energy Storage System (HESS), Lyapunov, 598, 617, 620, 627, 642, 645,
133, 147, 440, 437 647, 681, 682, 685, 686, 726, 749,
Hybrid power, 1, 8, 517, 518, 528, 531 756, 757, 758, 759, 761, 762, 763,
Hysteresis, 139, 333, 682, 754 766
ICPT system, 128, 129, 130, 136 Master/Slave control, 615

IEEE 33 system, 669, 679 MATLAB, 127, 136, 139, 155, 175, 180,
IEEE 69, 679 181, 183, 195, 199, 216, 231, 277,
IEEE and IEC Standards, 621 295, 297, 298, 340, 354, 357, 400,
IEEE specifications, 392 749
IGBT switches, 38, 39 MATLAB SIMULINK, 136, 139, 155,
Incremental conductance, 193, 194, 175, 180, 181, 195, 216, 231, 268,
195, 533, 538, 552 277, 295
Incremental interleaved, 71, 76, 79, 80, MATLAB/Simulink, 297, 298, 340,
82, 83, 84, 92, 95, 98, 101, 103, 354, 357, 391, 400, 405, 530, 545,
114, 116, 122 654, 731
Interleaved boost converter, 43, 44, Maximum electrical rotation, 784
444, 454, 455, 456 Maximum torque per ampere (MTPA),
Inverter, 24, 62, 63, 64, 73, 108, 130, 353, 507
136, 150, 160, 162, 173, 204, 206 Metal oxide semiconductor field effect
Isolated DC-DC full-bridge converter transistor, 206, 207, 210
(FBC), 131 MG concept, 599
Index 793
MG control layer, 603 National Electric Mobility Mission

Microgrid, 4, 18, 116, 120, 121, 122, Plan (NEMMP), 318
125, 126, 335, 461, 536, 597, 598, Negative half/cycle, 130, 231
599, 601–629, 633, 645, 647 Negative Voltage, 242
MIMO, 348, 731, 732, 734, 738, 742, NITI Aayog, 318
743, 744, 745, 778 N-Level, 205, 280
MLI, 159, 176, 160, 161–173, 203–311 Non-Inverting Buck-Boost Converters,
Model predictive control, 337, 339, 48
341, 343, 345, 346, 347, 348, 349, Non-isolated boost converter (BC),
351, 352, 353, 354, 355, 356, 357, 134
358, 359, 360, 361, 363, 364, 365, Non-isolated DC-DC converters, 4, 10,
366, 618 68, 74
Moderate, 95, 114, 117, 119, 133, 204, Non-isolated DC-DC multi-device
375, 376, 381, 382 converter (MDC), 135
Modern robotization, 17 Non-isolated interleaved boost
Modular, 68, 69, 79, 104, 112, 116, 120, converter (IBC), 134
125, 126, 147, 173, 200, 298, 301, Nonlinear controller, 634, 730, 750
302, 312, 313, 535, 551, 559, 608, Number, 79, 81, 83, 94, 105, 112, 114,
624, 675 115, 118, 707, 719, 723, 732, 739,
Modulating wave, 203, 205, 208 755, 757, 784
Modulation index, 178, 179, 208
Motor angular velocity, 753 Online algebraic approach, 683, 720,
MPP (Maximum Power Point), 192 721, 722
MPPT (Maximum Power Point OPAL-real time lab, 337, 340, 357
Tracking), 73, 80, 180, 185, 188, Open loop control, 782
189, 191, 192, 194, 195, 196, 537, Operating regions, 412, 424
538, 552, 611, 632, 637, 638, 642, Optimization, 66, 67, 68, 139, 194,
643, 646, 647, 652, 657, 658 200, 313, 314, 348, 349, 514,
MSP430 microcontroller, 779, 781, 515, 519, 555, 588, 598, 603,
785, 787 604, 607, 608, 616, 617, 621,
Multi-Agent System (MAS) Based 625, 628, 633, 639, 731, 742,
Distributed Control, 613 743
Multi-device boost converters Optimization techniques, 604, 659,
(MDBC), 33 664, 665, 670, 731, 742, 743
Multilevel inverter, 69, 159, 161, 162, Orthopaedic, 337, 338, 339, 340, 341,
173, 174, 176, 182, 183, 193, 199, 342, 351, 357, 361, 363
200, 291, 292, 294, 295, 297, 298, Output Enabled (OE), 273
299, 300 Overview of MG Control, 611
Multi-phase converter, 32, 65
Multi-phase interleaved boost P & O MPPT (Perturb and Observe
converter, 35, 37, 38, 42, 44 MPPT), 192
Multi-winding transformer, 133 P&O (Perturb & Observe), 192
794 Index
Parallel, 5, 6, 17, 33, 34, 43, 44, 57, 72, Power flow control by current
73, 74, 80, 125, 133, 146, 158, 187, regulation, 611
189, 196, 279, 292, 294, 388, 438 Power flow control by voltage
Parasitic conventional boost converter, regulation, 612
37 Power handling capacity, 79, 101, 392
Particle swarm optimization, 364, 519, Power loss minimization, 659, 662,
598, 625, 665, 675, 743, 784 663, 667, 669, 673, 674
Passivity based control, 617, 628, 633, Power rating, 3, 72, 80, 98, 199, 319,
644, 645, 646, 647, 648, 649, 650, 321, 391, 466, 558, 570
656, 681, 682, 683, 684, 685, 687, Power switching converter, 3
689, 691, 693, 695, 697, 699, 701 PQ control, 614, 615
Peak Voltage (VPEAK), 268, 290 Predictive control, 139, 337, 338, 339,
PEMFC stacks, 24, 26, 65 341, 342, 343, 345, 347, 349, 350,
Period, 75, 93, 110, 130, 143, 171, 191, 351, 353, 355, 357, 359, 360, 361,
195, 215, 225, 248 562
Permanent magnet synchronous Programmable logic controllers
motor (PMSM), 337, 339, 340, (PLCs), 17
341, 342, 343, 344, 347, 349, 351, Programmable Read Only Memory
353, 362 (PROM), 278
Phase Disposition (PD), 208 Proton exchange membrane fuel cell,
Phase Opposite Disposition (POD), 208 295
Phase shift PWM for switching, 132 Push-Pull converter, 8
Photo Voltaic (PV), 186 PV (Photovoltaic), 71, 72, 73, 74, 75,
Photovoltaic, 175, 193, 195, 199, 200, 77, 79, 81, 83, 85, 87, 89, 91, 176
201, 202, 292, 293, 296, 297 PWM (Pulse Width Modulation), 49,
PI controller, 352, 360, 588, 632, 644, 129, 131, 160, 177, 178, 203, 204,
647, 747, 750, 751, 755, 756, 767, 751
768, 769, 770, 777 PWM duty cycle, 781, 782, 784, 785
PID controller, 640, 731, 733, 742, PZT/piezoelectric, 368
743, 744, 782, 784, 787
PM/piezomotors, 368 Quadrant, 14, 204, 208, 209, 210, 213,
PMDC Motor, 437, 449, 451, 452, 454, 214, 215, 223, 224
455, 458, 466, 752, 772 Quadratic boost converter, 533, 535,
Positive half/cycle, 215, 224, 248, 265 536, 537, 539, 540, 543, 544, 546,
Positive Voltage, 206, 241 547, 550, 552
Power Conditioning System (PCS), Quasi, 147, 248, 387, 389, 551
73, 74
Power converter, 3, 71, 75, 92, 110, R1 to R7/Resistances, 368
127, 130, 145, 146, 149, 159, 173, Radial distribution network, 659, 661,
175, 191, 203, 279, 293, 317, 319, 669, 674, 675
337, 352 Real-time optimization, 604
Power converters, 21, 22, 71, 127, 130, Recursive method, 389, 750
145, 149, 159, 175, 203, 279, 293, Reduced order observer, 723, 727, 728,
317, 319, 352 729
Index 795
Reference profile generation, 713 Soft switching converters, 22

Reluctance, 463, 464, 471, 472, 475, Soft switching DC-DC converter, 4, 16
476, 482, 490, 491, 498, 503, 513, Solar charging, 519, 520, 530
514 Solar irradiation, 181, 189, 190
Reluctance torque, 414, 415, 424, 427 Space vector modulation, 345, 560,
Renewable energy sources, 120, 200, 561, 578, 591
251, 319, 322, 392, 518, 534, 553, SROO approach, 720
599, 611, 631, 655 State of dissipation, 691
RES (Renewable Energy Sources), 200 Stator resistance, 342
Resistive load, 206, 305, 690, 749, 752, Steady state, 10, 12, 31, 41, 42, 53, 54,
767 55, 56, 63, 65, 66, 151, 755
Resistive-inductive load, 209 Steady state current waveforms, 41
Resolution, 205, 210, 215, 225, 248, Step-down converter, 14
266, 268, 274, 276, 277, 278, 279, Strictly passive system, 684
280, 286, 287, 288, 290, 341 Stud krill herd algorithm, 668
REXT/Resistor, 368 Switch mode power converters, 4, 149,
R-load, 211, 401, 403, 751, 752, 753, 749
757 Switching Angle Algorithm (SAA),
Role, 16, 72, 73, 117, 130 203, 205
Root Mean Square (RMS), 203, 268 Switching frequency, 151, 153, 154,
Root Mean Square Voltage (VRMS), 268, 155, 156, 157, 158, 340, 345, 352,
274, 278 360
Rotor, 476, 477, 478, 481, 482, 485, Switching loss, 98, 101, 113, 114, 116,
486, 487, 488, 489, 490, 491, 493, 137, 150, 154, 183, 184, 205, 297,
496, 497 298, 326, 332, 344, 346, 353, 582,
RS232 port, 278 586
Switching pattern, 159, 163, 165, 203,
Scaling value, 215, 224, 248 205, 206, 210, 215, 216, 231, 241,
Selective Harmonic Elimination 265, 268, 280
(SHE), 204 Symmetric, 67, 98, 116, 124, 129, 204,
Sensitivity analysis, 419, 515, 681, 706, 248, 391, 686, 688, 695, 703
707, 708, 709, 710, 727, 729 Symmetric inverter, 293, 307, 311, 313,
Sepic converter, 12, 22, 24, 30, 31, 32, 394, 408
134, 456, 728 Synthesis, 71, 80, 83, 84, 101, 104, 110,
Series voltage controller, 5 112, 122
Shuffled frog leap algorithm, 667 Synthesized resistor transistor logic,
Sine wave, 84, 171, 196, 203, 208 279
Sliding mode controllers, 632, 751 System generator, 204, 216, 231,
SMC control for BC converter, 142 268
796 Index
THD, 159, 266, 268, 269, 270, 275, 277, Voltage level, 16, 22, 63, 72, 73, 91, 96,
290, 298, 308, 313, 361 97, 111, 119, 120, 121, 122, 133,
Topology, 31, 204, 205, 206, 222, 296, 161, 167, 169, 180, 203, 303, 311,
308, 313, 314, 323, 324, 326, 391, 384, 396, 399, 3407, 439, 618, 634,
392, 407 660
Torque, 337, 338, 339, 340, 343, 344, Voltage multiplier cell, 68, 77, 79, 124,
345, 346, 347, 348, 349, 350, 351, 125
353, 361, 362 Voltage source inverter, 199, 293, 297,
Torque equation, 415, 417, 683 311, 350, 354, 393, 654
Torque ripple, 337, 338, 339, 340, 344, Voltage sources, 27, 48, 169, 296, 303,
345, 348, 351, 353, 354, 355, 356, 305, 307, 308, 324, 391, 394, 396,
357, 359, 360, 361, 500, 502, 503, 407
504, 505, 512, 513, 515 Voltage stress, 16, 43, 78, 79, 84, 91, 92,
Total harmonic distortion, 159, 172, 93, 95, 96, 97, 109, 115, 116, 117,
175, 182, 183, 185, 199, 290 , 291, 118, 160, 162, 182, 204, 205, 300,
298, 319, 402, 632 392, 535
Triangular, 203, 205, 208 Voltage vector, 339, 342, 344, 346, 347,
Trinary Cascaded Hybrid MLI circuit, 348, 349, 350, 352, 354, 416, 417
208, 210, 223, 240, 266, 277 VSI control, 614
Turns ratio, 74, 79, 87, 91, 92, 93, 94,
110, 111, 115, 118 WECS, 553, 554, 555, 556, 557, 558,
559, 560, 564, 567, 569
UC3524 controller, 768, 773, 775, 776, Weighting factor, 340, 346, 349, 350,
777 351, 352, 353, 390
Unequal, 109, 203, 204, 206, 222, 240, Whale optimization algorithms,
294, 295, 305, 307, 392, 616 666
UPS (Uninterruptable Power Supply),
68, 121, 163, 186, 187, 199, 373, Xilinx Spartan FPGA, 273, 279
534, 615
Urban DC MG, 600, 602 Zener diodes, 377
Zero, 222, 240, 273
Very High Speed Integrated Circuit Zero current switching (ZCS), 16, 18,
Hardware Description Language 131, 150, 325, 326, 328
(VHDL), 204, 210, 280 Zero Voltage Switching (ZVS), 16, 18,
Virtual control, 749, 756, 758, 759, 130, 150, 175, 323, 324, 325, 326
761, 762, 764 ZVS, 323, 324, 325, 326
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Power Converters,

Drives and Controls for

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Library of Congress Cataloging-in-Publication Data

Front cover images supplied by WikiMedia Commons

Printed in the USA

Part I: Power Converter Topologies

2.5 DC-DC Sepic Converter 30

3.4.1 HGC with 3 CIs, Clift, and VMC 85

4.4 Design of DC-DC Converter with Integration of ICPT

7.1.3 Modelling and Simulation Analysis of Seven Level

8.3.2 Half Equal Phase Switching Angle Algorithm

9.2 Multilevel Inverters in Sustainable Applications 294

Part II: Electric Machines and Drives

11.4.1 Conventional Model Predictive Torque

13.4 Simulation Circuit and Result Discussions 400

16.3 Motor Peak Power Calculation Based

18.3 Simulation of the Proposed Converter 545

Part III: Trends in Control Methods

20.4.1 Forecast 604

22 Optimization Techniques for Minimizing Power Loss in Radial

23.7.3 Load Torque Estimation Using Online Algebraic

25.5.1 Buck Converter Specifications 771

Further, converters such as DC-DC converters, 31-level asymmetrical

Dr. Marco Rivera Abarca

Dr. S.K. Patnaik

Keywords: Static power converter, micro grid, power switching converter

*Corresponding author: [email protected]

1.2 Classifications of DC-DC Converters

i. Linear mode DC-DC converter

These converters are again subclassified based on their components and

Figure 1.1 Classification of DC-DC converter.

1.2.1 Classification of Linear Mode DC-DC Converters

Figure 1.2 Series regulators.

Figure 1.3 Parallel regulators.

1.2.1.2 Parallel Regulators

1.2.2 Classification of Hard Switching DC-DC Converter

i. Isolated DC-DC Topologies

1.2.2.1 List of Isolated DC-DC Topologies

Figure 1.4 Forward converter.

1.2.2.1.2 Flyback Converter

Figure 1.5 Flyback converter.

The exchanging component, frequently a force MOSFET or IGBT, is

1.2.2.1.3 Push-Pull Converter

Figure 1.6 Push-pull converter.

1.2.2.1.4 Half-Bridge Converter

Figure 1.7 Half-bridge converter.

1.2.2.2 Classification of Non-Isolated DC-DC Converters

Continuous Conduction Mode

VC1 = VCO = VO (1.2)

Figure 1.8 Cuk-converter.

pTVI = (1–p)T(VC–V1) (1.4)

Discontinuous Conduction Mode

∴ pTVI = (1 – p)mT(Vc – VI) (1.6)

Assuming C, C1, and CO are very large values,

1.2.2.2.2 Single-Ended Primary Inductance Converter (SEPIC)

Continuous Conduction Mode

VC1 =VC = VI (1.11)

3) Reduces device stress as there are multiple devices per