Semiconductor Memory
Organization & Addressing
Técnicas Digitales II
Dr. Agustin M. Laprovitta (
[email protected])
Introduction
Computer systems functionality aspects
Processing
– Transformation of data
– Implemented using processors
Storage
– Retention of data
– Implemented using memory
Communication
– Transfer of data between processors and memories
– Implemented using buses
– Called interfacing
* Embedded Systems Design: A Unified Hardware/Software Introduction, © 2000 Vahid/Givargis
A simple bus
rd'/wr
Processor enable (SC)
(CPU) Memory
addr[0-11]
data[0-7]
Wires: Bus structure
Uni-directional or bi-directional
One line may represent multiple wires
Bus
Set of wires with a single function
– Address bus, data bus
Or, entire collection of wires
– Address, data and control
– Associated protocol: rules for communication
* Embedded Systems Design: A Unified Hardware/Software Introduction, © 2000 Vahid/Givargis
Semiconductor Memory Classification
Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory
Random Non-Random EPROM Mask-Programmed
Access Access
E2PROM Programmable (PROM)
SRAM FIFO FLASH
DRAM LIFO
Shift Register
CACHE
* Digital Integrated Circuits 2dn – Memories (SCU 2011, PhD Shoba Krishnan)
Memory Timing: Definitions
* Digital Integrated Circuits 2dn – Memories (SCU 2011, PhD Shoba Krishnan)
Memory Organization
Memory Adress Word (8 bits) M bits
Binary Dec
0000000000 0 0 1 1 1 0 0 1 0 S0
Word 0
S1
0000000001 1 1 1 1 1 1 1 1 1 Addressed Word 1
word S2
0000000010 2 0 0 0 1 0 0 1 1 Word 2
. . . . . . . . K
. . . . . . . .
. . Storage SK
. . . . . . . . 2
Word K-2
bit cell
1111111101 1021 1 1 1 1 0 0 0 1 SK 1
Word K-1
1111111110 1022 1 1 0 0 0 0 0 0
1111111111 1023 0 0 0 0 1 1 1 1
Input - Output
(M bits)
Example organization for
1Kword x 8 bits = 8K bits memory
Memory Architecture: Decoders
M bits M bits
S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage
Word 2 A1 Word 2
cell
K N
AN- 1
SK 2
Word K-2 Word K-2
SK 1
Word K-1 Word K-1
2N=K
Input - Output Input-Output
(M bits) (M bits)
Intuitive architecture for K x M memory Decoder reduces the number of select signals
Too many select signals:
K words == K select signals
N = log2K
* Digital Integrated Circuits 2dn – Memories (SCU 2011, PhD Shoba Krishnan)
Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
* Digital Integrated Circuits 2dn – Memories (SCU 2011, PhD Shoba Krishnan)
Hierarchical Memory Architecture
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
* Digital Integrated Circuits 2dn – Memories (SCU 2011, PhD Shoba Krishnan)
Addressable Space
It´s defined as the total number of addresses
the CPU can access.
It depends on the width (number of bits) of
the address bits: n bits -> 2n addresses
Memory Addressing (data bus)
Memory Addressing (address bus)
Memory Addressing (parallel)
D15 . . . D8 D7 . . . D0
A9 . . . A0 A[0..9] 10 8 D[0..7] 16
0000000000 0 1 . 1 0 . 1 0 ADDRs DATA
D[8..15] D[0..15]
RAM
0000000001 1 1 . 1 1 . 1 1 1Kx8bits
R /W
0000000010 0 0 . 1 0 . 1 1 R/W
. . . . . . . . CS
. . . . . . . . enable
. . . . . . . .
8
1111111101 1 1 . 1 0 . 0 1 ADDRs DATA
RAM
1111111110 1 1 . 0 0 . 0 0
1Kx8bits
1111111111 0 0 . 0 1 . 1 1 R/W
CS
Example organization for
bank of 1Kword x 16 bits
from 2 x 1Kx8bits
Memory Addressing (serial)
D7 . . . D0 A[0..9] 10 8 8 D[0..7]
A11 A10 A9 . . . A0 ADDRs DATA
A[10..11]
0 0 0000000000 0 1 1 1 0 0 1 0 RAM
1Kx8bits
2 R /W
. . . . . . . . R/W
Decodif. 2x4 CS
0 0 1111111111 0 0 0 1 0 1 1 1
Q0 00
A10 Q1 01
0 1 0000000000 0 1 1 1 0 0 1 0 SEL0
A11 8
SEL1 Q2 10 ADDRs DATA
. . . . . . . . Q3 11 RAM
enable 1Kx8bits
0 1 1111111111 0 0 0 1 0 1 1 1 R/W
CS
1 0 0000000000 0 1 1 1 0 0 1 0
. . . . . . . . 8
ADDRs DATA
1 0 1111111111 0 0 0 1 0 1 1 1 RAM
1Kx8bits
1 1 0000000000 0 1 1 1 0 0 1 0 R/W
CS
. . . . . . . .
1 1 1111111111 0 0 0 1 0 1 1 1 8
ADDRs DATA
RAM
1Kx8bits
Example organization for bank of R/W
4Kword x 8 bits from 4 x 1Kx8bits CS
Example: 0xFFFFFFFF Interrupt Vector
Conventional
PC Memory map Special Funct. Reg.
Reserved
512M Slot RAM slot #3
RAM slot #2
RAM slot #1
256M DRAM
RAM slot #0
256M DRAM
0x00000000 Flash (BIOS)
