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Von Neumann Computer Architecture Worksheet

The document describes key aspects of von Neumann architecture, including the three main buses, registers used, and the seven stages of the fetch-execute cycle. It provides examples to match each bus to its description and the correct sequence of the fetch-execute cycle stages. Multiple choice and fill-in-the-blank questions are also included.

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drishti
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333 views

Von Neumann Computer Architecture Worksheet

The document describes key aspects of von Neumann architecture, including the three main buses, registers used, and the seven stages of the fetch-execute cycle. It provides examples to match each bus to its description and the correct sequence of the fetch-execute cycle stages. Multiple choice and fill-in-the-blank questions are also included.

Uploaded by

drishti
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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1 One of the key features of von Neumann computer architecture is the use of buses.

Three buses and three descriptions are shown below.

Draw a line to connect each bus to its correct description.

[3]

(b) Two features of Von Neumann architecture are the use of registers and the use of

buses. Give the names of two registers

Registers

1 .........................................................................................................................................
.......

...................................................................................................................................................

2 .........................................................................................................................................

.......

.........................................................................................................................................

..........[2]

(c) The seven stages in a von Neumann fetch-execute cycle are shown in the table below.
Put each stage in the correct sequence by writing the numbers 1 to 7 in the right hand
column. The first one has been done for you.

Sequence
Stage number

the instruction is then copied from the memory location contained in


the MAR (memory address register) and is placed in the MDR (memory
data register)

the instruction is finally decoded and is then executed

the PC (program counter) contains the address of the next instruction


to be fetched 1
the entire instruction is then copied from the MDR (memory data
register) and placed in the CIR (current instruction register)

the address contained in the PC (program counter) is copied to the MAR


(memory address register) via the address bus

the address part of the instruction, if any, is placed in the MAR (memory
address register)

the value in the PC (program counter) is then incremented so that it


points to the next instruction to be fetched

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