Introduction to Synchronous Sequential

Circuits
Circuits

1
Zvi Kohavi and Niraj K. Jha

Sequential Circuits and Finite-

Finite-state
Machines
Sequential circuit: its outputs a function of external inputs as well as stored
i f
information
ti

Finite-state machine (FSM): abstract model to describe the synchronous

sequential machine and its spatial counterpart, the iterative
network

Serial binary adder example: block diagram, addition process, state table
and state diagram

11/0
00/0 01/0
01/1 A B 10/0
10/1 11/1
00/1 2
State Assignment
Device with two states capable of storing information: delay element with
i
inputt Y and
d output
t ty
• Two states: y = 0 and y = 1
• Since the present input value Y of the delay element is equal to its next
output value: the input value is referred to as the next state of the delay
– Y(t) = y(t+1)

Example: assign state y = 0 to state A of the adder and y = 1 to B

• The value of y at ti corresponds to the value of the carry generated at ti-1
• Process of assigning the states of a physical device to the states of the
serial adder: called state assignment
• Output value y: referred to as the state variable
• Transition/output table for the serial adder: Y = x1x2 + x1y + x2y
z = x1 x2 y
x1 z
Full
x2
adder
C0
3
y Delay
Y

FSM: Definitions
FSMs: whose past histories can affect their future behavior in only a finite
number
b off ways
• Serial adder: its response to the signals at time t is only a function of
these signals and the value of the carry at t-1
– Thus,
Thus its input histories can be grouped into just two classes: those
resulting in a 1 carry and those resulting in a 0 carry at t
• Thus, every finite-state machine contains a finite number of memory
devices: which store the information regarding the past input history

4
Synchronous Sequential Machines
x1 z1
xl Combinational zm
logic

y1 Y1

y2 Y2

yk Yk

Input variables: {x1, x2, .., xl} ``Memory’’ devices

Input configuration, symbol, pattern or vector: ordered l-tuple of 0’s and 1’s
Input alphabet: set of p = 2l distinct input patterns
• Thus, input alphabet I = {I1, I2, .., Ip}
p for two variables x1 and x2
• Example:
– I = {00, 01, 10, 11}
Output variables: {z1, z2, .., zm}
Output configuration,
configuration symbol
symbol, pattern or vector: ordered m-tuple of 0’s
0 s and 1’s
1s
m
Output alphabet: set of q = 2 distinct output patterns 5
• Thus, output alphabet O = {O1, O2, .., Oq}

Synchronous Sequential Machines

(Contd.)
(Contd )
Set of state variables: {y1, y2, .., yk}

Present state: combination of values at the outputs of k memory elements

Set S of n = 2k k-tuples: entire set of states S = {S1, S2, .., Sn}

Next state: values of Y

Y’s
s

Synchronization achieved by means of clock pulses feeding the memory

devices

pp
Initial state: state of the machine before the application of an input
p
sequence to it

Final state: state of the machine after the application of the input
sequence
6
Memory Elements and Their Excitation
Functions
To generate the Y’s: memory devices must be supplied with appropriate
i
inputt values
l
• Excitation functions: switching functions that describe the impact of xi’s
and yj’s on the memory-element input
• Excitation table: its entries are the values of the memory
memory-element
element inputs

Most widely used memory elements: flip-flops, which are made of latches
• Latch: remains in one state indefinitely until an input signals directs it to do
otherwise

Set-reset of SR latch: S 1 y
R 0 y
(a) Block diagram.

R y S y

y y
S R
(b) NOR latch. (c) NAND latch. 7

SR Latch (Contd.)
Excitation characteristics and requirements:

Clocked SR latch: all state changes synchronized to clock pulses

• Restrictions placed on the length and frequency of clock pulses: so that
the circuit changes state no more than once for each clock pulse
R
S y y
C Clock
R y
y
S 8
(a) Block diagram. (b) Logic diagram.
Trigger or T Latch
Value 1 applied to its input triggers the latch to change state

Excitations requirements:

y(t+1) = Ty’(t) + T’y(t)

= T y(t)
9

The JK Latch
Unlike the SR latch, J = K = 1 is permitted: when it occurs, the latch acts
lik a ttrigger
like i and
d switches
it h tto th
the complement
l t state
t t

Excitation requirements:

10
The D Latch
The next state of the D latch is equal to its present excitation:
y(t+1) = D(t)

11

Clock Timing
Clocked latch: changes state only in synchronization with the clock pulse
andd no more th
than once d
during
i each h occurrence off th
the clock
l k pulse
l
Duration of clock pulse: determined by circuit delays and signal
propagation time through the latches
• Must be long enough to allow latch to change state, and
• Short enough so that the latch will not change state twice due to the same
excitation
Excitation of a JK latch within a sequential circuit:
• Length of the clock pulse must allow the latch to generate the y’s
• But should not be present when the values of the y’s have propagated
through the combinational circuit

12
Master--slave Flip
Master Flip--flop
Master-slave flip-flop: a type of synchronous memory element that
eliminates
li i t th the titiming
i problems
bl b
by iisolating
l ti its
it iinputs
t ffrom it
its
outputs
Master-slave SR flip-flop:

Master-slave JK flip-flop: since master-slave SR flip-flop suffers from the

problem that both its inputs cannot be 11, it can be converted to a
JK flip-flip

S y
J SR 1
Master-
K slave 0 y
R

13

Master-slave JK Flip-
Master- Flip-flop with Additional
Inputs
Direct set and clear inputs: override regular input signals and clock
• To set the slave output to 0: make set = 1 and clear = 0
• To set the slave output to 1: make set = 0 and clear = 1
• Assigning 0 to both set and clear: not allowed
• Assigning 1 to both set and clear: normal operation
• Useful in design of counters and shift registers

14
1’s Catching and 0’s Catching
SR and JK flip-flops suffer from 1’s catching and 0’s catching

S y
J SR 1
Master-
K slave
l 0 y
R

Master latch is transparent when the clock is high

• When the output of the slave latch is at 0 and the J input has a static-0
hazard (a transient glitch to 1) after the clock has gone high: then the
master latch catches this set condition
– It then passes the 1 to the slave latch when the clock goes low
• Similarly, when the output of the slave latch is at 1 and the K input has a
static-0
static 0 hazard after the clock has gone high: then the master latch
catches this reset condition
– It then passes the 0 to the slave latch when the clock goes low

15

D flip
flip--flop
Master-slave D flip-flop avoids the above problem: even when a static
h
hazardd occurs att th
the D input
i t when
h ththe clock
l k iis hi
high,
h th
the output
t t off
the master latch reverts to its old value when the glitch goes away
D J y
JK 1
Master-
slave 0 y
K

16
Edge--triggered Flip
Edge Flip--flop
Positive (negative) edge-triggered D flip-flip: stores the value at the D input
when
h ththe clock
l k makes
k a 0 ->
> 1 (1 -> > 0) ttransition
iti
• Any change at the D input after the clock has made a transition does not
have any effect on the value stored in the flip-flop

A negative edge-triggered D flip-flop:

• When the clock is high, the output of the bottommost (topmost) NOR gate
i at D’
is D (D),
(D) whereas
h the
h S-R
S R inputs
i off the
h output llatch
h are at 0
0, causing
i iit
to hold previous value
• When the clock goes low, the value from the
b tt
bottommost t (topmost)
(t t) NOR gatet gets
t transferred
t f d
as D (D’) to the S (R) input of the output latch
R y
– Thus, output latch stores the value of D
Clock
• If there
th is
i a change
h iin th
the value
l off th
the D S y
input after the clock has made its transition,
the bottommost NOR gate attains value 0
– However, this cannot change the SR
D
inputs of the output latch 17

Synthesis of Synchronous Sequential

Circuits
Main steps:
1. From a word description off the problem, form
f a state diagram or table
2. Check the table to determine if it contains any redundant states
• If so, remove them (Chapter 10)
3. Select a state assignment and determine the type of memory elements
4. Derive transition and output tables
5. Derive an excitation table and obtain excitation and output functions from their
respective
ti tables
t bl
6. Draw a circuit diagram

18
Sequence Detector
One-input/one-output sequence detector: produces output value 1 every
ti
time sequence 0101 iis d
detected,
t t d else
l 0
• Example: 010101 -> 000101

State diagram and state table:

Transition and output tables:

19

Sequence Detector (Contd.)

Excitation and output maps:

z = xy1y2’
y1 = x’y1y2 + xy1’y2 + xy1y2’
y2 = y1y2’ + x’y1’ + y1’y2

Logic diagram:

20
Sequence Detector (Contd.)
Another state assignment:

z = xy1y2
Y1 = x’y1y2’ + xy2
Y2 = x’

21

Binary Counter
One-input/one-output modulo-8 binary counter: produces output value 1 for
every eighth
i hth iinputt 1 value
l

State diagram and state table:

0/0

0/0 S0 1/0 0/0

1/1

S7 S1

1/0 1/0

0/0 S6 S2 0/0

1/0 1/0

S5 S3

1/0 S4 1/0 0/0

0/0

0/0

22
Binary Counter (Contd.)
Transition and output tables:

Excitation table for T

flip-flops and logic diagram:

T1 = x
T2 = xy1
T3 = xy1y2
z = xy1y2y3 23

Implementing the Counter with SR Flip

Flip--
flops
Transition and output tables:

Cell 1 Cell 2 Cell 3

Excitation table for SR
y1 y2 y3
flip-flops and logic diagram: S1 0 S2 0 S3 0
x
y1 y2 y3
• Trivially extensible to R1 1 R2 1 R3 1

modulo-16 counter
z

y1 y2 y3
S1 = xyy1’
R1 = xy1
S2 = xy1y2’
R2 = xy1y2
S3 = xy1y2y3’ 24
R3 = z = xy1y2y3
Parity--bit Generator
Parity
Serial parity-bit generator: receives coded messages and adds a parity bit
t every m-bit
to bit message
• Assume m = 3 and even parity

State diagram and state table:

A
0,1/0 0,1/1
0/0 1/0
B C

0/0 0/0

1/0 1/0
D E J1 = y2
0/0 0/0
K1 = y2’
J2 = y1’
1/0 1/0
F G
K2 = y1
J3 = xy1’ + xy2
K3 = x + y2’ 25
z = y2’y3

Sequential Circuit as a Control Element

Control element: streamlines computation by providing appropriate control

signals
i l

Example: digital system that computes the value of (4a + b) modulo 16

• a, b: four-bit
a four bit binary number
• X: register containing four flip-flops
• x: number stored in X
• R i t can b
Register be lloaded
d d with:
ith either
ith b or a + x
• Addition performed by: a four-bit parallel adder
• K: modulo-4 binary counter, whose output L equals 1 whenever the count
is 3 modulo 4
b
4

a ADD X (4a + b)16

4 4 4

k1 x
K 4
k2

Initiate
u Sequential circuit M z 26
 Example (Contd.)
Sequential circuit M:
• Input u: initiates computation
• Input L: gives the count of K
• Outputs:  ,  ,  , z
• When  = 1: contents of b transferred to X
• When  = 1: values of x and a added and transferred back to X
• When  = 1: count of K increased by 1
• z = 1: whenever final result available in X

b
4

a ADD X (4a + b)16

4 4 4

k1 x
K 4
k2

Initiate
u S
Sequential
ti l circuit
i it M z

27

Example (Contd.)
Sequential circuit M:
• K, u, z: initially at 0
• When u = 1: computation starts by setting  = 1
– Causes b to be loaded into X
• To add a to x: set  = 1 and  = 1 to keep track of the number of times a
has been added to x
• After four such additions: z = 1 and the computation is complete
• At thi
this point:
i t K = 0 tto be
b ready
d ffor th
the nextt computation
t ti

State diagram:
b
4
u=0
00 -/z = 1 a ADD X (4a + b)16
A 4 4 4
u=1 x
k1
K 4
B 01 D 10 k2

-/ = 1 L

C Initiate
L = 0/ = 1 11 L = 1/ = 1 u Sequential circuit M z
28
=1 =1
 Example (Contd.)
State assignment, transition table, maps and logic diagram:
u=0 PS NS
00 -/z = 1 y1y2 Y1Y2 y1 y1
A y2 y2
0 1 0 1
00 0u
u=1
0 0 0 0 u 0
01 11
B 01 D 10
11 1L 1 1 1 1 1 L
-/ = 1
10 00 Y1 Y2
C
L = 0/ = 1 11 L = 1/ = 1 (a) Transition table. (b) Maps for Y1 and Y2.
=1 =1
Y1 y1
D1 z
 = y1’y2 Clock y1

 =  = y1y2
z = y1y2’ ,

Y1 = y2
Y2 y2
Y2 = y1’y2 + uy1’ + L’y2 L D2

Cl k
Clock y2
u Clock
29
(c) Logic diagram.