INTEGRATED CIRCUITS

DATA SHEET

SAA7345
CMOS digital decoding IC with
RAM for Compact Disc
Product specification 1998 Feb 16
Supersedes data of 1996 Jan 09
File under Integrated Circuits, IC01
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

FEATURES GENERAL DESCRIPTION

• Integrated data slicer and clock regenerator The SAA7345 incorporates the CD signal processing
• Digital Phase-Locked Loop (PLL) functions of decoding and digital filtering. The device is
equipped with on-board SRAM and includes additional
• Demodulator and Eight-to-Fourteen Modulation (EFM)
features to reduce the processing required in the analog
decoding
domain.
• Subcoding microcontroller serial interface
Supply of this Compact Disc IC does not convey an implied
• Integrated programmable motor speed control license under any patent right to use this IC in any
• Error correction and concealment functions Compact Disc application.
• Embedded Static Random Access Memory (SRAM) for
de-interleave and First-In First-Out (FIFO)
• FIFO overflow concealment for rotational shock
resistance
• Digital audio interface [European Broadcasting Union
(EBU)]
• 2 to 4 times oversampling integrated digital filter
• Audio data peak level detection
• Versatile audio data serial interface
• Digital de-emphasis filter
• Kill interface for Digital-to-Analog Converter (DAC)
deactivation during digital silence
• Double speed mode
• Compact Disc Read Only Memory (CD-ROM) modes
• A single speed only version is available
(SAA7345GP/SS).

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

VDD supply voltage 3.4 5.0 5.5 V
IDD supply current − 22 50 mA
fxtal crystal frequency 8 16.9344 or 35 MHz
33.8688
Tamb operating ambient temperature −40 − +85 °C
Tstg storage temperature −55 − +125 °C

ORDERING INFORMATION

TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
SAA7345GP QFP44 plastic quad flat package; 44 leads (lead length 2.35 mm); body SOT205-1
14 × 14 × 2.2 mm

1998 Feb 16 2
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

BLOCK DIAGRAM

V VSSA VDD1 VSS1 VDD2 VSS2

DDA
11 12 15 16 44 43
HFIN 8
DIGITAL 22 MOTO1
9 PLL MOTOR
HFREF
PLL CONTROL 23 MOTO2
ISLICE 7 FRONT-
END
IREF 10 EFM
DEMODULATOR ERROR

SUBCODE
CORRECTOR
TEST1 6
33 CFLG
FLAGS
TEST2 5

CRIN 13 SRAM
AUDIO
CROUT 14 PROCESSOR

CL11 1 RAM
TIMING
ADDRESSER
CLA 29 SAA7345 EBU
INTER- 2 DOBM
CL16 17 FACE

Q - CHANNEL
CRC CHECK
21 SCLK
CL 31 Q - CHANNEL PEAK
REGISTER DETECT SERIAL 20 WCLK
MICRO- DATA
DA 30
CONTROLLER INTER- 19 DATA
INTERFACE FACE
RAB 32
VERSATILE PINS 18 MISC
INTERFACE KILL

PORE 28
3 4 26 25 24 27

V1 V2 V3 V4 V5 KILL MGA371 - 2

Fig.1 Block diagram.

1998 Feb 16 3
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

PINNING

SYMBOL PIN DESCRIPTION

CL11 1 11.2896 or 5.6448 MHz clock output (3-state); (divide-by-3)
DOBM 2 bi-phase mark output (externally buffered; 3-state)
V1 3 versatile input pin
V2 4 versatile input pin
TEST2 5 test input; this pin should be tied LOW
TEST1 6 test input; this pin should be tied LOW
ISLICE 7 current feedback output from data slicer
HFIN 8 comparator signal input
HFREF 9 comparator common-mode input
IREF 10 reference current pin (nominally 1⁄2VDD)
VDDA 11 analog supply voltage; note 1
VSSA 12 analog ground; note 1
CRIN 13 crystal/resonator input
CROUT 14 crystal/resonator output
VDD1 15 digital supply to input and output buffers; note 1
VSS1 16 digital ground to input and output buffers; note 1
CL16 17 16.9344 MHz system clock output
MISC 18 general purpose DAC output (3-state)
DATA 19 serial data output (3-state)
WCLK 20 word clock output (3-state)
SCLK 21 serial bit clock output (3-state)
MOTO1 22 motor output 1; versatile (3-state)
MOTO2 23 motor output 2; versatile (3-state)
V5 24 versatile output pin
V4 25 versatile output pin
V3 26 versatile output pin (open-drain)
KILL 27 kill output; programmable (open-drain)
PORE 28 power-on reset enable input (active LOW)
CLA 29 4.2336 MHz microcontroller clock output
DA 30 interface data I/O line
CL 31 interface clock input line
RAB 32 interface R/W and acknowledge input
CFLG 33 correction flag output (open-drain)
n.c. 34 to 42 no internal connection
VSS2 43 digital ground to internal logic; note 1
VDD2 44 digital supply voltage to internal logic; note 1

Note
1. All supply pins must be connected to the same external power supply.

1998 Feb 16 4
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

Pins 34 to 42 (inclusive)

44 V DD2

VSS2
have no internal connection

41

40

39
38

37
43

42

36
35

34
CL11 1 33 CFLG

DOBM 2 32 RAB

V1 3 31 CL

V2 4 30 DA
TEST2 5 29 CLA

TEST1 6 SAA7345 28 PORE

ISLICE 7 27 KILL

HFIN 8 26 V3
HFREF 9 25 V4

IREF 10 24 V5

VDDA 11 23 MOTO2
WCLK 20
SCLK 21

MOTO1 22
V SSA 12

CRIN 13
CROUT 14
V DD1 15
VSS1 16

CL16 17

MISC 18

DATA 19

MGA359 - 1

Fig.2 Pin configuration.

1998 Feb 16 5
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

FUNCTIONAL DESCRIPTION Regeneration of the bit clock is achieved with an internal

fully digital PLL. No external components are required and
Demodulator
the bit clock is not output. The PLL has two microcontroller
FRAME SYNC PROTECTION control registers (addresses 1000 and 1001) for
bandwidth and equalization.
This circuit will detect the frame synchronization signals.
Two synchronization counters are used in the SAA7345: For certain applications an off-track input is necessary. If
this flag is HIGH, the SAA7345 will assume that the servo
1. The coincidence counter which is used to detect the
is following on the wrong track, and will flag all incoming
coincidence of successive syncs. It generates a Sync
HF data as incorrect. The off-track is input via the V1 pin
coincidence signal if 2 syncs are 588 ±1 EFM clocks
when the versatile pins interface register (address 1100)
apart.
bit 0 is set to logic 1.
2. The main counter is used to partition the EFM signal
into 17-bit words. This counter is reset when: EFM demodulation
a) A Sync coincidence is generated.
The 14-bit EFM data and subcode words are decoded into
b) A sync is found within ±6 EFM clocks of its 8-bit symbols.
expected position.
The Sync coincidence signal is also used to generate the Subcode data processing
Lock signal which will go active HIGH when 1 Sync Q-CHANNEL PROCESSING
coincidence is found. It will reset to LOW when, during 61
consecutive frames, no Sync coincidence is found. This The 96-bit Q-channel word is accumulated in an internal
Lock signal is accessed via the status signal when the buffer. Sixteen bits are used to perform a Cyclic
status control register (address 0010) is set to X100. See Redundancy Check (CRC). If the data is good, the
section on “Microcontroller interface” . SUBQREADY-I signal will go LOW. SUBQREADY-I can
be read via the status signal when the status control
Data Slicer and Clock Regenerator register (address 0010) is set to X000 (normal reset
condition). Good Q-channel data may be read via the
The SAA7345 has an integrated slice level comparator microcontroller interface.
which is clocked by the crystal frequency clock. The slice
level is controlled by an internal current source applied to
an external capacitor under the control of the digital
phase-locked loop (DPLL).

crystal
clock

2.2 kΩ HFIN
HF
input
2.2 nF 47 pF D Q

HFREF
22 kΩ DPLL
1/2VDD
Iref
22 nF 100 µA

VSSA VSS

ISLICE
100 nF VDD
MGA368 - 1

VSSA 100 µA

Fig.3 Data slicer showing typical application components.

1998 Feb 16 6
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

OTHER SUBCODE CHANNELS Write operation sequence

Data of the other subcode channels (Q-to-W) may be read • RAB is held LOW by the microcontroller to hold the
via the V4 pin if the versatile pins interface register SAA7345 DA pin at high-impedance.
(address 1101) is set to XX01. • Microcontroller data is clocked into the internal shift
The format is similar to RS232. The subcode sync word is register on the LOW-to-HIGH clock transition CL.
formed by a pause of 200 µs minimum. Each subcode byte • Data D (3 : 0) is latched into the appropriate control
starts with a logic 1 followed by 7 bits (Q-to-W). The gap register [address bits A (3 : 0)] on the LOW-to-HIGH
between bytes is variable between 11.3 µs and 90 µs. transition of RAB with CL HIGH.
The subcode data is also available in the EBU output • If more data is clocked into SAA7345 before the
(DOBM) in a similar format. LOW-to-HIGH transition of RAB then only the last 8 bits
are used.
Microcontroller interface • If less data is clocked into SAA7345, unpredictable
The SAA7345 has a 3-line microcontroller interface which operation will result.
is compatible with the digital servo IC TDA1301. • If the LOW-to-HIGH transition of RAB occurs with CL
LOW, the command will be disregarded.
WRITING DATA TO SAA7345
The SAA7345 has thirteen 4-bit programmable
configuration registers as shown in Table 2. These can be
written to via the microcontroller interface using the
protocol shown in Fig.5.

200 µs 11.3 11.3 µs min

min µs 90 µs max
W96 1 Q1 R1 S1 T1 U1 V1 W1 1 Q2
MGA369

Fig.4 Subcode format and timing at V4 pin.

RAB
(microcontroller)

CL
(microcontroller)
DA
(microcontroller) A3 A2 A1 A0 D3 D2 D1 D0

DA (SAA7345)
high impedance
MGA379 - 1

Fig.5 Microcontroller WRITE timing.

1998 Feb 16 7
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

WRITING DATA TO SAA7345; REPEAT MODE

The same command can be repeated several times (e.g. for fade function) by applying extra RAB pulses as shown in
Fig.6.

RAB
(microcontroller)

CL
(microcontroller)
DA
(microcontroller) A3 A2 A1 A0 D3 D2 D1 D0

DA (SAA7345)
high impedance
MGA380 - 1

Note that CL must stay HIGH between RAB pulses.

Fig.6 Microcontroller WRITE timing; repeat mode.

READING STATUS INFORMATION FROM SAA7345

There are several internal status signals which can be made available on the DA line (Table 1).

Table 1 Internal status signals.

SIGNAL DESCRIPTION
SUBQREADY-I LOW if new subcode word is ready in Q-channel register.
MOTSTART1 HIGH if motor is turning at 75% or more of nominal speed.
MOTSTART2 HIGH if motor is turning at 50% or more of nominal speed.
MOTSTOP HIGH if motor is turning at 12% or less of nominal speed.
PLL Lock HIGH if Sync coincidence signals are found.
V1 Follows input on V1 pin.
V2 Follows input on V2 pin.
MOTOR-OV HIGH if the motor servo output stage saturates.

The status signal to be output is selected by status control register (address 0010). The timing for reading the status
signal is shown in Fig.7.

Status read operation sequence

• Write appropriate data to register 0010 to select required status signal.
• With RAB LOW; set CL LOW.
• Set RAB HIGH; this will instruct the SAA7345 to output status signal on DA.

1998 Feb 16 8
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

RAB
(microcontroller)

CL
(microcontroller)

DA
(microcontroller)
high impedance

DA (SAA7345) STATUS

MGA381 - 1

Fig.7 SAA7345 status READ timing.

READING Q-CHANNEL SUBCODE FROM SAA7345

To read Q-channel subcode from SAA7345, the SUBQREADY-I signal should be selected as status signal. The subcode
read timing is shown in Fig.8.

Read subcode operation sequence

• Monitor SUBQREADY-I status signal.
• When this signal is LOW, and up to 2.3 ms after its LOW-to-HIGH transition, it is permitted to read subcode.
• Set CL LOW, SAA7345 will output first subcode bit (Q1).
• After subcode read starts, the microcontroller may take as long as it wants to terminate read operation.
• SAA7345 will output consecutive subcode bits after each HIGH-to-LOW transition of CL.
• When enough subcode has been read (1 to 96 bits), stop reading by pulling RAB LOW.

RAB
(microcontroller)

CL
(microcontroller)
CRC
DA (SAA7345) OK Q1 Q2 Q3 Qn–2 Qn–1 Qn

STATUS MGA382 - 1

Fig.8 SAA7345 Q-channel subcode READ timing.

PEAK DETECTOR OUTPUT

In place of the CRC-bits (bits 81 to 96), the peak detector information is added to the Q-channel data. The peak
information corresponds to the highest audio level (absolute value) and is measured on positive peaks. Only the most
significant 8 bits of the peak level are given, in unsigned notation. Bits 81 to 88 contain the LEFT peak value
(bit 88 = MSB) and bits 89 to 96 contain the RIGHT channel (bit 96 = MSB). Value is reset after reading Q-channel data.

1998 Feb 16 9
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

BEHAVIOUR OF THE SUBQREADY-I SIGNAL SHARING THE MICROCONTROLLER INTERFACE

When the CRC of the Q-channel word is good, and no When the RAB pin is held LOW by the microcontroller, it is
subcode is being read, the SUBQREADY-I signal will react permitted to put any signal on the DA and CL lines
as shown in Fig.9. (SAA7345 will set output DA to high-impedance). Under
this circumstance these lines may be used for another
When the CRC is good and subcode is being read, the
purpose (e.g. TDA1301 microcontroller interface Data and
timing in Fig.10 applies.
Clock line, see Fig.11).
If t1 (SUBQREADY-I LOW to end of subcode read) is
below 2.6 ms, then t2 = 13.1 ms (i.e. the microcontroller
can read all subcode frames if it completes the read
operation within 2.6 ms after subcode ready).
If this criterion is not met, it is only possible to guarantee
that t3 will be below 26.2 ms (approximately).
If subcode frames with failed CRCs are present, the t2 and
t3 times will be increased by 13.1 ms for each defective
subcode frame.

RAB
(microcontroller)

CL
(microcontroller)

high
DA (SAA7345) CRC OK CRC OK
impedance

MGA373 - 1
10.8 ms 15.4 ms
2.3
ms
READ start allowed

Fig.9 SUBQREADY-I timing when no subcode is read.

t2
t1 t3

RAB
(microcontroller)

CL
(microcontroller)

DA (SAA7345) Q1 Q2 Q3 Qn

MGA374 - 1

Fig.10 SUBQREADY-I timing when subcode is being read.

1998 Feb 16 10
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

TDA1301 SAA7345

SIDA
SICL
SILD

RAB
DA
CL
I/O
O
MICROCONTROLLER O
O

MGA361 - 1

Fig.11 SAA7345 microcontroller interface application diagram.

Table 2 Command registers.

The ‘INITIAL’ column shows the power-on reset state
REGISTER ADDRESS DATA FUNCTION INITIAL
Fade and Attenuation 0000 X000 Mute Reset
X01X Attenuate
X001 Full Scale
X100 Step Down
X101 Step Up
Motor mode 0001 X000 Motor off mode Reset
X001 Motor brake mode 1
X010 Motor brake mode 2
X011 Motor start mode 1
X100 Motor start mode 2
X101 Motor jump mode
X 111 Motor play mode
X110 Motor jump mode 1
1XXX anti-windup active
0XXX anti-windup off Reset
Status control 0010 X000 status = SUBQREADY-I Reset
X001 status = MOTSTART1
X010 status = MOTSTART2
X011 status = MOTSTOP
X100 status = PLL Lock
X101 status = V1
X110 status = V2
X 111 status = MOTOR-OV
0XXX L channel first at DAC (WCLK normal) Reset
1XXX R channel first at DAC (WCLK inverted)

1998 Feb 16 11
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

REGISTER ADDRESS DATA FUNCTION INITIAL

DAC output 0011 1010 I2S CD-ROM mode
1011 EIAJ; CD-ROM mode
110X I2S; 4fs mode Reset
1111 I2S; 2fs mode
1110 I2S; fs mode
000X EIAJ; 16-bit; 4fs
0011 EIAJ; 16-bit; 2fs
0010 EIAJ; 16-bit; fs
010X EIAJ; 18-bit; 4fs
0111 EIAJ; 18-bit; 2fs
0110 EIAJ; 18-bit; fs
Motor gain 0100 X000 Motor gain G = 3.2 Reset
X001 Motor gain G = 4.0
X010 Motor gain G = 6.4
X011 Motor gain G = 8.0
X100 Motor gain G = 12.8
X101 Motor gain G = 16.0
X110 Motor gain G = 25.6
X 111 Motor gain G = 32.0
Motor bandwidth 0101 XX00 Motor f4 = 0.5 Hz Reset
XX01 Motor f4 = 0.7 Hz
XX10 Motor f4 = 1.4 Hz
XX11 Motor f4 = 2.8 Hz
00XX Motor f3 = 0.85 Hz Reset
01XX Motor f3 = 1.71 Hz
10XX Motor f3 = 3.42 Hz
Motor output configuration 0110 XX00 Motor power maximum 37% Reset
XX01 Motor power maximum 50%
XX10 Motor power maximum 75%
XX11 Motor power maximum 100%
00XX MOTO1, MOTO2 pins 3-state Reset
01XX Motor Pulse Width Modulation (PWM) mode
10XX Motor Pulse Density Modulation (PDM) mode
11XX Motor Compact Disc Video (CDV) mode

1998 Feb 16 12
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

REGISTER ADDRESS DATA FUNCTION INITIAL

Loop BW Internal BW Low-pass
(Hz) (Hz) BW (Hz)
PLL loop filter bandwidth 1000 0000 1640 525 8400
0001 3279 263 16800
0010 6560 131 33600
0100 1640 1050 8400
0101 3279 525 16800
0110 6560 263 33600
1000 1640 2101 8400
1001 3279 1050 16800 Reset
1010 6560 525 33600
1100 1640 4200 8400
1101 3279 2101 16800
1110 6560 1050 33600
PLL loop filter equalization 1001 0001 PLL 30 ns over-equalization
0010 PLL 15 ns over-equalization
0011 PLL nominal equalization Reset
0100 PLL 15 ns under-equalization
0101 PLL 30 ns under-equalization
EBU output 1010 XX00 EBU data before concealment
XX10 EBU data after concealment and fade Reset
XX11 EBU off − output LOW
X0XX Level II clock accuracy (<1000 × 10−6) Reset
X1XX Level III clock accuracy (>1000 × 10−6)
0XXX Flags in EBU off Reset
1XXX Flags in EBU on
Speed control 1011 1XXX double-speed mode
0XXX single-speed mode Reset
X0XX 33.869 MHz crystal present Reset
X1XX 16.934 MHz crystal present
XX00 standby 1: ‘CD-STOP’ mode (note 1) Reset
XX10 standby 2: ‘CD-PAUSE’ mode (note 1)
XX11 operating mode
Versatile pins interface 1100 XXX1 off-track input at V1
XXX0 no off-track input (V1 may be read via status) Reset
XX0X Kill-L at KILL output, Kill-R at V3 output
X01X V3 = 0; single Kill output Reset
X11X V3 = 1; single Kill output

1998 Feb 16 13
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

REGISTER ADDRESS DATA FUNCTION INITIAL

Versatile pins interface 1101 0000 4-line motor (using V4, V5)
XX01 Q-to-W subcode at V4
XX10 V4 = 0
XX11 V4 = 1 Reset
01XX de-emphasis signal at V5
10XX V5 = 0
11XX V5 = 1 Reset
Note
1. Standby modes = CL, DA and RAB; normal operation.
a) MISC, SCLK, WCLK, DATA, CL11 and DOBM; 3-state.
b) CRIN, CROUT, CL16 and CLA; normal operation.
c) V1, V2, V3, V4 and V5; normal operation.
d) MOTO1 and MOTO2 - in standby 2 ‘CD-PAUSE’; normal operation.
e) MOTO1 and MOTO2 - in standby 1 ‘CD-STOP’; held LOW in PWM mode; 3-state in PDM mode.

Error corrector Audio functions

The error corrector carries out t = 2, e = 0 error corrections DE-EMPHASIS AND PHASE LINEARITY
on both C1 (32 symbol) and C2 (28 symbol) frames. Four
When de-emphasis is detected in the Q-channel subcode,
symbols are used from each frame as parity symbols. The
the digital filter automatically includes a de-emphasis filter
strategy t = 2, e = 0 means that the error corrector can
section. When de-emphasis is not required, a phase
correct two erroneous symbols per frame and detect all
compensation filter section controls the phase linearity of
erroneous frames.
the digital oversampling filter to ≤ ±1° within the band
The error corrector also contains a flag controller. Flags 0 to 16 kHz.
are assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates DIGITAL OVERSAMPLING FILTER
output flags which are read (after de-interleaving) by C2,
The SAA7345 contains a 2 to 4 times oversampling filter.
to help in the generation of C2 output flags.
The filter specification of the 4 × oversampling filter is
The C2 output flags are used by the interpolator for given in Table 2 and shown in Fig.12.
concealment of non-correctable errors. They are also
These attenuations do not include the sample and hold at
output via the EBU signal (DOBM) and the MISC output
the DAC output or the DAC post filter.
with I2S for CD-ROM applications.
When using the oversampling filter, the output level is
The flags output pin CFLG provides information on the
scaled −0.5 dB down, to avoid overflow on full-scale
state of all error correction and concealment flags.
sinewave inputs (0 to 20 kHz).

1998 Feb 16 14
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

Table 3 Digital filter passband characteristics

PASSBAND ATTENUATION
0 to 19 kHz ≤ 0.001 dB
19 to 20 kHz ≤ 0.03 dB

Table 4 Digital filter stopband characteristics.

STOPBAND ATTENUATION
24 kHz ≥ 25 dB
24 to 27 kHz ≥ 38 dB
27 to 35 kHz ≥ 40 dB
35 to 64 kHz ≥ 50 dB
64 to 68 kHz ≥ 31 dB
68 kHz ≥ 35 dB
69 to 88 kHz ≥ 40 dB

MGA385
20

magnitude
(dB)

20

40

60
0 10 20 30 40 50
frequency (kHz)

Fig.12 Digital filter characteristics.

CONCEALMENT
A 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. The
erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels
have independent interpolators.
If more than one consecutive non-correctable sample is found, the last good sample is held. A 1-sample linear
interpolation is then performed before the next good sample (see Fig.13).

1998 Feb 16 15
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

Interpolation Hold Interpolation

OK Error OK Error Error Error OK OK

MGA372

Fig.13 Concealment mechanism.

MUTE, ATTENUATION AND FADE To control the fade counter in a continuous way, the
step-up and step-down commands are available (fade
A digital level controller is present on the SAA7345 which
control register data X101 and X100). They will increment
performs the functions of soft mute, attenuation and fade.
or decrement the counter by 1 for each register write
operation.
Mute and Attenuation
• When issuing more than 1 step-up or step-down
Soft mute is activated by sending the Mute command to command in sequence, the write repeat mode may be
the fade control register (address 0000, data X000). The used (see Fig.6).
signal will reduced to zero in up to 128 steps (depending
• A pause of at least 22 µs is necessary between any two
on the current position of the fade control), taking a
step-up or step-down commands.
maximum of 3 ms.
• When a step-up command is given when the fade
Attenuation (−12 dB) is activated by sending the Attenuate counter is already at its full-scale value, the counter will
command to the fade control register (data X01X). not increment.
Attenuation and mute are cancelled by sending the Full
Scale command to the fade control register (data X001). It DAC Interface
will take 3 ms to ramp the output from mute to the full-scale The SAA7345 is compatible with a wide range of
level. Digital-to-Analog Converters. Eleven formats are
supported and are shown in Table 5.
Fade
All formats are MSB first. fs is 44.1 kHz in single-speed
The audio output level is determined by the value of the mode and 88.2 kHz in double-speed mode.
internal fade counter.

counter
Level = ---------------------- × maximum level
128
• The counter is preset to 128 by the Full Scale command
if no oversampling is required.
• The counter is preset to 120 (−0.5 dB scaling) by the Full
Scale command if either 2fs or 4fs oversampling is
programmed in the DAC output register (address 0011).

• The counter is preset to 32 by the Attenuate command.

• The counter is preset to 0 by the Mute command.

1998 Feb 16 16
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

Table 5 DAC interface formats

DAC CONTROL SAMPLE
MODE BITS SCLK (MHz) FORMAT INTERPOLATION
REGISTER DATA FREQUENCY
1 1010 fs 16 2.1168 × n(1) CD-ROM (I2S) no
2 1011 fs 16 2.1168 × n(1) CD-ROM (EIAJ)(2) no
3 1110 fs 16 2.1168 × n(1) Philips I2S − 16 bits yes
4 0010 fs 16 2.1168 × n(1) EIAJ − 16 bits yes
5 0110 fs 18 2.1168 × n(1) EIAJ − 18 bits yes
6 000X 4fs 16 8.4672 × n(1) EIAJ − 16 bits yes
7 010X 4fs 18 8.4672 × n(1) EIAJ − 18 bits yes
8 110X 4fs 18 8.4672 × n(1) Philips I2S − 18 bits yes
9 0011 2fs 16 4.2336 × n(1) EIAJ − 16 bits yes
10 0111 2fs 18 4.2336 × n(1) EIAJ − 18 bits yes
11 1111 2fs 18 4.2336 × n(1) Philips I2S − 18 bits yes

Note
1. n = disc speed.
2. EIAJ is the abbreviation for: Electronic Industries Associated of Japan.

1998 Feb 16 17
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1998 Feb 16

Philips Semiconductors
Compact Disc
CMOS digital decoding IC with RAM for
SCLK

DATA 0 15 0 15
LEFT CHANNEL DATA (WCLK NORMAL POLARITY)

WCLK

MISC LSB VALID MSB VALID LSB VALID MSB VALID

CD-ROM
MGA383
MODE ONLY

Fig.14 Philips I2S data format (16-bit word length shown).

18

SCLK

DATA 0 17 0 17
LEFT CHANNEL DATA

WCLK

MISC
MGA384

Product specification
SAA7345
Fig.15 EIAJ data format (18-bit word length shown).
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

EBU interface
The biphase-mark digital output signal at pin DOBM is in accordance with the format defined by the “IEC 958”
specification.
Three different modes can be selected via the EBU output control register (address 1010).

Table 6 EBU output modes

EBU CONTROL
EBU OUTPUT AT DOBM PIN EBU VALIDITY FLAG (BIT 28)
REGISTER DATA
XX11 DOBM pin held LOW −
XX00 data taken before concealment, mute and fade HIGH if data is non-correctable
(concealment flag)
XX10 data taken after concealment, mute and fade HIGH if data is non-correctable
(concealment flag)

FORMAT
The digital audio output consists of 32-bit words (subframes) transmitted in biphase-mark code (two transitions for a
logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384 (see Table 7).

Table 7 EBU word format

WORD BITS FUNCTION

Sync 0 to 3 −
Auxiliary 4 to 7 not used; normally zero
Error flags 4 CFLG error and interpolation flags when bit 3 of EBU control
register is set to logic 1
Audio sample 8 to 27 first 4 bits not used (always zero)
Validity flag 28 valid = logic 0
User data 29 used for subcode data (Q-to-W)
Channel status 30 control bits and category code
Parity bit 31 even parity for bits 4 to 30

SYNC AUDIO SAMPLE

The sync word is formed by violation of the biphase rule Left and right samples are transmitted alternately.
and therefore does not contain any data. Its length is
equivalent to 4 data bits. The three different sync patterns VALIDITY FLAG
indicate the following situations:
Audio samples are flagged (bit 28 = logic 1) if an error has
• Sync B: been detected but was non-correctable. This flag remains
– Start of a block (384 words), word contains left the same even if data is taken after concealment.
sample.
• Sync M: USER DATA

– Word contains left sample (no block start). Subcode bits Q-to-W from the subcode section are
transmitted via the user data bit. This data is asynchronous
• Sync W:
with the block rate.
– Word contains right sample.

1998 Feb 16 19
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

CHANNEL STATUS
The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192 channel status
bits. The category code is always CD. The bit assignment is shown in Table 8.

Table 8 EBU channel status

WORD BITS FUNCTION
Control 0 to 3 copy of CRC checked Q-channel control bits 0 to 3;
bit 2 is logic 1 when copy permitted;
bit 3 is logic 1 when recording has pre-emphasis
Reserved mode 4 to 7 always zero
Category code 8 to 15 CD: bit 8 = logic 1; all other bits = logic 0
Clock accuracy 28 to 29 set by EBU control register:
00 = Level II
01 = Level III
Remaining 16 to 27 and 30 to 191 always zero

KILL circuit Several output modes are supported:

The KILL circuit detects digital silence by testing for an 1. Pulse Density, 2-line (true complement output), 1 MHz
all-zero or all-ones data word in the left or right channel sample frequency.
before the digital filter. The output is switched active LOW 2. PWM output, 2-line, 22.05 kHz modulation frequency.
when silence has been detected for at least 200 ms. Two 3. PWM-output, 4-line, 22.05 kHz modulation frequency.
modes are available, selected by the versatile pins register
(address 1100): 4. CDV motor mode.
The modes are selected via the motor output configuration
1-PIN KILL MODE register (address 0110).
Active LOW signal on KILL pin when digital silence has
been detected on both LEFT and RIGHT channels for PULSE DENSITY MODE
200 ms. In the Pulse Density mode the motor output pin MOTO1 is
the pulse density modulated motor output signal. A 50%
2-PIN KILL MODE duty cycle corresponds with the motor not actuated, higher
Independent digital silence detection for left and right duty cycles mean acceleration, lower mean braking.
channels. The KILL pin is active LOW when digital silence In this mode, the MOTO2 signal is the inverse of the
has been detected in the LEFT channel for 200 ms, and V3 MOTO1 signal. Both signals change state only on the
is active LOW when digital silence has been detected in edges of a 1 MHz internal clock signal.
the RIGHT channel for 200 ms.
Possible application diagrams are shown in Fig.16.
When MUTE is active then the KILL output is forced LOW.

Spindle motor control

The spindle motor speed is controlled by a fully integrated
digital servo. Address information from the internal
±8 frame FIFO and disc speed information are used to
calculate the motor control output signals.

1998 Feb 16 20
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

22 kΩ 22 kΩ
MOTO1 + + MOTO2
M
– –
10 nF 10 nF

VSS VSS
VDD

22 kΩ
22 kΩ
MOTO1 +
M VSS
–
22 kΩ 10 nF
22 kΩ
VSS VSS
22 kΩ
V
DD MGA363 - 1

Fig.16 Motor pulse density application diagrams.

PWM MODE, 2-LINE

In the PWM mode the motor acceleration signal is put in pulse-width modulation form on the MOTO1 output and the
motor braking signal is pulse-width modulated on the MOTO2 output.
Figure 17 shows the timing and Fig.18 a typical application diagram.

t rep = 45 µs t dead 240 ns

MOTO1

MOTO2

Accelerate Brake MGA366

Fig.17 Motor 2-line PWM mode timing.

10 Ω 100 nF

MOTO1 MOTO2

VSS MGA365 - 2

Fig.18 Motor 2-line PWM mode application diagram.

1998 Feb 16 21
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

PWM MODE, 4-LINE

Using two extra outputs from the Versatile Pins Interface, it is possible to use the SAA7345 with a 4-input motor bridge.
Figure 19 shows the timing and Fig.20 a typical application diagram.

t rep = 45 µs t dead 240 ns

MOTO1

MOTO2

V4

V5

t ovl = 240 ns MGA367 - 1

Accelerate Brake

Fig.19 Motor 4-line PWM mode timing.

V4 V5

10 Ω 100 nF

MOTO1 MOTO2

VSS MGA364 - 2

Fig.20 Motor 4-line PWM mode application diagram.

CDV MODE
In the CDV motor mode, the FIFO position will be put in pulse-width modulated form on the MOTO1 pin (carrier frequency
300 Hz) and the PLL frequency signal will be put in pulse-density modulated form on the MOTO2 pin (carrier frequency
4.23 MHz). The integrated motor servo is disabled in this mode.
Remark:
The PWM signal on MOTO1 corresponds to a total memory space of 20 frames, therefore the nominal FIFO position
(half-full) will result in a PWM output of 60%.

1998 Feb 16 22
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

OPERATION MODES
The motor servo has the operation modes as shown in Table 9 and is controlled by the motor mode register
(address 0001).

Table 9 Operation modes.

MODE DESCRIPTION
Start mode 1 Disc is accelerated by applying a positive voltage to the spindle motor. No decisions are involved
and the PLL is reset. No disc speed information is available for the microcontroller.
Start mode 2 The disc is accelerated as in Start mode 1, however the PLL will monitor the disc speed. When the
disc reaches 75% of its nominal speed, the controller will switch to Jump mode. The motor status
signals are valid (register 0010).
Jump mode Motor servo enabled but FIFO kept reset at 50%. The audio is muted but it is possible to read the
subcode.
Jump mode 1 Similar to Jump mode but motor integrator is kept at zero. Used for long jumps.
Play mode FIFO released after resetting to 50%. Audio mute released.
Stop mode 1 Disc is braked by applying a negative voltage to the motor. No decisions are involved.
Stop mode 2 The disc is braked as in Stop mode 1, but the PLL will monitor the disc speed. As soon as the disc
reaches 12% of its nominal speed, the MOTSTOP status signal will go HIGH and switch the motor
servo to off mode.
Off mode Motor not steered.

POWER LIMIT FIFO OVERFLOW

In Start mode 1, Start mode 2, Stop mode 1 and Stop If FIFO overflow occurs during Play mode (e.g. as a result
mode 2, a fixed positive or negative voltage is applied to of motor shock), the FIFO will be automatically reset
the motor. This voltage can be programmed as a to 50% and the audio interpolator is activated to minimize
percentage of the maximum possible voltage via the motor the effect of data loss.
output configuration register (address 0110) to limit
current drain during start and stop. The following power
limits are possible:
• 100% of maximum (no power limit)
• 75% of maximum
• 50% of maximum
• 37% of maximum.

LOOP CHARACTERISTICS
The gain and cross-over frequencies of the motor control
loop can be programmed via the motor gain and bandwidth
registers (addresses 0100 and 0101). The possible
parameter values are as follows:
Gain: 3.2, 4.0, 6.4, 8.0 12.8, 16, 26.6 or 32.
Cross-over frequency, f4: −0.5, −0.7, −1.4 or −2.8 Hz.
Cross-over frequency, f3: −0.85, −1.71 or −3.42 Hz.

1998 Feb 16 23
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

MGA362 - 2
G

f4 f3 BW f

Fig.21 Motor servo mode diagram.

Versatile pins interface

The SAA7345 has five pins that can be reconfigured for different applications as shown in Table 10.

Table 10 Versatile pins

CONTROL CONTROL
SYMBOL PIN TYPE REGISTER REGISTER FUNCTION
ADDRESS DATA
V1 3 input 1100 XXX1 off-track input (from digital servo)
XXX0 input may be read via status register
(address 0010 data X101)
V2 4 input − − input may be read via status register
(address 0010 data X110)
V3 26 output 1100 XX0X kill output for right channel
X01X output = logic 0
X11X output = logic 1
V4 25 output 1101 0000 4-line motor drive (using V4 and V5)
XX01 Q-to-W subcode output
XX10 output = logic 0
XX11 output = logic 1
V5 24 output 1101 01XX de-emphasis output (active HIGH)
10XX output = logic 0
11XX output = logic 1

1998 Feb 16 24
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

Flags Output (CFLG) (open drain output)

A 1-bit flag signal is available at the CFLG pin. This signal shows the status of the error corrector and interpolator and is
updated every frame (7.35 kHz).

handbook, full pagewidth 11.3

µs 45.4 µs

CFLG F1 F2 F3 F4 F5 F6 F7 F1
MGA370

Fig.22 Flags output timing.

Table 11 Meaning of flag bits.

F1 F2 F3 F4 F5 F6 F7 MEANING
0 X X X X X X no absolute time sync
1 X X X X X X absolute time sync
X 0 0 X X X X C1 frame contained no errors
X 0 1 X X X X C1 frame contained 1 error
X 1 0 X X X X C1 frame contained 2 errors
X 1 1 X X X X C1 frame non-correctable
X X X 0 0 X X C2 frame contained no errors
X X X 0 1 X X C2 frame contained 1 error
X X X 1 0 X X C2 frame contained 2 errors
X X X 1 1 X X C2 frame non-correctable
X X X X X 0 0 no interpolations
X X X X X 0 1 at least one 1-sample interpolation
X X X X X 1 0 at least one hold and no interpolations
X X X X X 1 1 at least one hold and one 1-sample interpolation

ABSOLUTE TIME SYNC Double speed mode

The first flag bit (F1) is the absolute time sync signal. It is Double speed mode is programmed via the Speed control
the FIFO-passed subcode-sync and relates the position of register (address 1011). It is possible to program double
the subcode-sync to the audio data (DAC output). speed independent of clock frequency, but optimum
performance is achieved with a 33.8688 MHz crystal or a
The flag may be used for special purposes such as
ceramic resonator.
synchronization of different players.

FLAGS AT EBU OUTPUT

The CFLG flags are available on bit 4 of the EBU data
format when bit 3 of the EBU output control register
(address 1010) is set to logic 1.

1998 Feb 16 25
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDD supply voltage note 1 −0.5 +6.5 V
VI(max) maximum input voltage −0.5 VDD + 0.5 V
VO output voltage −0.5 +6.5 V
IO output current (continuous) − ±20 mA
Tamb operating ambient temperature −40 +85 °C
Tstg storage temperature −55 +125 °C
Ves1 electrostatic handling note 2 −2000 +2000 V
Ves2 electrostatic handling note 3 −200 +200 V

Notes
1. All VDD and VSS connections must be made externally to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.

CHARACTERISTICS
VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply
VDD supply voltage 3.4 5.0 5.5 V
IDD supply current VDD = 5 V − 22 50 mA
Analog Front End (VDD = 4.5 to 5.5 V); comparator inputs HFIN and HFREF
fclk clock frequency 8 − 35 MHz
Vth switching thresholds 1.2 − VDD − 0.4 V
Analog Front End (VDD = 3.4 to 5.5 V); comparator inputs HFIN and HFREF
fclk clock frequency 8 − 20 MHz
Vtpt HFIN input voltage level − 1.0 − V
Digital inputs CL and RAB
VIL LOW level input voltage −0.3 − 0.3VDD V
VIH HIGH level input voltage 0.7VDD − VDD + 0.3 V
ILI input leakage current VI = 0 to VDD −10 − +10 µA
CI input capacitance − − 10 pF

1998 Feb 16 26
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital inputs PORE, V1 and V2
Vthr switching threshold voltage rising − − 0.8VDD V
Vthf switching threshold voltage falling 0.2VDD − − V
Vhys hysteresis voltage − 0.33VDD − V
RPU input pull-up resistance VI = 0 V − 50 − kΩ
CI input capacitance − − 10 pF
trw reset pulse width PORE only 1 − − µs
Digital outputs CL16 and CLA
VOL LOW level output voltage IOL = 1 mA 0 − 0.4 V
VOH HIGH level output voltage IOH = −1 mA VDD − 0.4 − VDD V
CL load capacitance − − 50 pF
tr output rise time CL = 20 pF; note 1 − − 15 ns
tf output fall time CL = 20 pF; note 1 − − 15 ns
Digital outputs V4 and V5
VOL LOW level output voltage VDD = 4.5 to 5.5 V; 0 − 1.0 V
IOL = 10 mA
VDD = 3.4 to 5.5 V; 0 − 1.0 V
IOL = 5 mA
VOH HIGH level output voltage VDD = 4.5 to 5.5 V; VDD − 1 − VDD V
IOH = −10 mA
VDD = 3.4 V to 5.5 V; VDD − 1 − VDD V
IOH = −5 mA
CL load capacitance − − 50 pF
tr output rise time CL = 20 pF; note 1 − − 15 ns
tf output fall time CL = 20 pF; note 1 − − 15 ns
Open-drain output CFLG
VOL LOW level output voltage IOL = 1 mA 0 − 0.4 V
IOL LOW level output current − − 2 mA
CL load capacitance − − 50 pF
tf output fall time CL = 20 pF; note 1 − − 30 ns
Open-drain outputs KILL and V3
VOL LOW level output voltage IOL = 1 mA 0 − 0.4 V
IOL LOW level output current − − 2 mA
CL load capacitance − − 50 pF
tf output fall time CL = 20 pF; note 1 − − 15 ns

1998 Feb 16 27
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

3-state outputs MISC, SCLK, WCLK, DATA and CL11
VOL LOW level output voltage IOL = 1 mA 0 − 0.4 V
VOH HIGH level output voltage IOH = −1 mA VDD − 0.4 − VDD V
CL load capacitance − − 50 pF
tr output rise time CL = 20 pF; note 1 − − 15 ns
tf output fall time CL = 20 pF; note 1 − − 15 ns
ILI 3-state leakage current VI = 0 to VDD −10 − +10 µA
3-state outputs MOTO1, MOTO2 and DOBM
VOL LOW level output voltage VDD = 4.5 to 5.5 V; 0 − 1.0 V
IOL = 10 mA
VDD = 3.4 to 5.5 V; 0 − 1.0 V
IOL = 5 mA
VOH HIGH level output voltage VDD = 4.5 to 5.5 V; VDD − 1 − VDD V
IOH = −10 mA
VDD = 3.4 to 5.5 V; VDD − 1 − VDD V
IOH = −5 mA
CL load capacitance − − 50 pF
tr output rise time CL = 20 pF; note 1 − − 10 ns
tf output fall time CL = 20 pF; note 1 − − 10 ns
ILI 3-state leakage current VI = 0 to VDD −10 − +10 µA
Digital input/output DA
VIL LOW level input voltage −0.3 − 0.3VDD V
VIH HIGH level input voltage 0.7VDD − VDD + 0.3 V
ILI 3-state leakage current VI = 0 to VDD −10 − +10 µA
CI input capacitance − − 10 pF
VOL LOW level output voltage IOL = 1 mA 0 − 0.4 V
VOH HIGH level output voltage IOH = −1 mA VDD − 0.4 − VDD V
CL load capacitance − − 50 pF
tr output rise time CL = 20 pF; note 1 − − 15 ns
tf output fall time CL = 20 pF; note 1 − − 15 ns
Crystal oscillator input CRIN (external clock)
gm mutual conductance at start-up − 4 − mS
RO output resistance at start-up − 11 − kΩ
CI input capacitance − − 10 pF
ILI input leakage current −10 − +10 µA
Crystal oscillator output CROUT (see Fig.26)
fxtal crystal frequency 8 16.9344 35 MHz
Cfb feedback capacitance − − 5 pF
CO output capacitance − − 10 pF

1998 Feb 16 28
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I2S timing
CLOCK OUTPUT SCLK (see Fig.23)
tcy output clock period sample rate = fs − 472.4 − ns
sample rate = 2fs − 236.2 − ns
sample rate = 4fs − 118.1 − ns
tH clock HIGH time sample rate = fs 166 − − ns
sample rate = 2fs 83 − − ns
sample rate = 4fs 42 − − ns
tL clock LOW time sample rate = fs 166 − − ns
sample rate = 2fs 83 − − ns
sample rate = 4fs 42 − − ns
tsu set-up time sample rate = fs 95 − − ns
sample rate = 2fs 48 − − ns
sample rate = 4fs 24 − − ns
th hold time sample rate = fs 95 − − ns
sample rate = 2fs 48 − − ns
sample rate = 4fs 24 − − ns
I2S timing (double speed)
CLOCK OUTPUT SCLK (see Fig.23)
tcy output clock period sample rate = fs − 236.2 − ns
sample rate = 2fs − 118.1 − ns
sample rate = 4fs − 59.1 − ns
tH clock HIGH time sample rate = fs 83 − − ns
sample rate = 2fs 42 − − ns
sample rate = 4fs 21 − − ns
tL clock LOW time sample rate = fs 83 − − ns
sample rate = 2fs 42 − − ns
sample rate = 4fs 21 − − ns
tsu set-up time sample rate = fs 48 − − ns
sample rate = 2fs 24 − − ns
sample rate = 4fs 12 − − ns
th hold time sample rate = fs 48 − − ns
sample rate = 2fs 24 − − ns
sample rate = 4fs 12 − − ns

1998 Feb 16 29
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Microcontroller interface timing (see Figs 24 and 25)
INPUTS CL AND RAB
tL input LOW time single speed 500 − − ns
double speed 260 − − ns
tH input HIGH time single speed 500 − − ns
double speed 260 − − ns
tr rise time single speed − − 480 ns
tf fall time double speed − − 240 ns
READ MODE
tdRD delay time RAB to DA valid 0 − 50 ns
tdRZ delay time RAB to DA 0 − 50 ns
high-impedance
tpd propagation delay CL to DA single speed 700 − 980 ns
double speed 340 − 500 ns
WRITE MODE
tsuD set-up time DA to CL single speed; note 2 −700 − − ns
double speed; note 2 −340 − − ns
thD hold time CL to DA single speed − − 980 ns
double speed − − 500 ns
tsuCR set-up time CL to RAB single speed 260 − − ns
double speed 140 − − ns
tdWZ delay time DA high-impedance 50 − − ns
to RAB
Notes
1. Timing reference voltage levels are 0.8 V and VDD − 0.8 V.
2. Negative set-up time means that data may change after clock transition.

clock period t cy
tL tH

V DD – 0.8 V
SCLK
0.8 V
t su
th

WCLK V DD – 0.8 V
DATA
MISC
0.8 V
MGA376 - 1

Fig.23 I2S timing.

1998 Feb 16 30
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

tr tf

V DD – 0.8 V
RAB
tr t
f 0.8 V
tH

V DD – 0.8 V
t dRD
CL
0.8 V t dRZ
tL
t pd

V DD – 0.8 V
DA (SAA7345)
high impedance
0.8 V
MGA377 - 1

Fig.24 Microcontroller timing; READ mode.

tr tH tf

t V – 0.8 V
suCR DD
RAB
0.8 V

t tH tr tL
f

VDD – 0.8 V
CL
0.8 V
tL t hD t dWZ
t suD

V – 0.8 V
DD
DA
(microcontroller) high impedance MGA378 - 1
0.8 V

Fig.25 Microcontroller timing; WRITE mode.

1998 Feb 16 31
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

APPLICATION INFORMATION

CRIN

33.8688 MHz
(3rd overtone) 100
3.3
CRYSTAL kΩ
µH

CROUT
2.2
1 nF 10 pF 10 pF kΩ
VDDA
VSSA

CRIN

16.9344 MHz 100

CRYSTAL kΩ

CROUT
2.2
33 pF 33 pF kΩ
VDDA
VSSA

CRIN

33.8688
CERAMIC 100
GENERATOR kΩ

CROUT

5 pF 2.2
5 pF
kΩ
VDDA
VSSA
MGA360 - 1

Fig.26 Application circuits for crystal oscillator.

1998 Feb 16 32
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

VDD
R6
2.2 Ω

C12
4.7 µF C13
X8 (63 V) 100 nF
11 MHz 44 43 42 41 40 39 38 37 36 35 34
clock output

V SS2
VDD2
1 33
CL11 CFLG
2 32
to DOBM transformer DOBM RAB
3 31 micro-
V1 CL controller
4 30 interface
V2 DA
5 29
TEST2 CLA
6 28
TEST1 SAA7345 PORE
7 27
ISLICE KILL
8 26
R2 HFIN V3
22 kΩ 9 25
C2 47 pF HFREF V4
10 24
IREF V5
CROUT

11 23
WCLK

V
V DD1

R3 MOTO2
DATA
V SS1

SCLK
MOTOR
CRIN

MISC
CL16

C4 C3 DDA
X6 2.2 kΩ INTERFACE
100 nF 22 nF (1) VSSA MOTO1
HFIN
C1 12 13 14 15 16 17 18 19 20 21 22
V
2.2 nF

R4 VDD
2.2 Ω

C6 C11
4.7 µF C7 100 to DAC
(63 V) 100 nF nF

X9
16 MHz
clock output

(2)

MGA375 - 1

(1) Diagram is for a 5 V application. For 3.4 V applications an additional resistor of 150 kΩ should be added between IREF (pin 10) and ground.
(2) For crystal oscillator circuit see Fig.26.

Fig.27 Typical SAA7345 application diagram.

1998 Feb 16 33
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm SOT205-1

33 23 A

34 22 ZE

e
E HE A2
A (A 3)
A1

wM
θ
bp Lp
pin 1 index L
44 12
detail X
1 11

ZD v M A
e wM
bp
D B
HD v M B

0 5 10 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y Z D (1) Z E (1) θ
o
0.25 2.3 0.50 0.25 14.1 14.1 19.2 19.2 2.0 2.4 2.4 7
mm 2.60 0.25 1 2.35 0.3 0.15 0.1
0.05 2.1 0.35 0.14 13.9 13.9 18.2 18.2 1.2 1.8 1.8 0o

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

95-02-04
SOT205-1 133E01A
97-08-01

1998 Feb 16 34
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

SOLDERING If wave soldering cannot be avoided, for QFP

packages with a pitch (e) larger than 0.5 mm, the
Introduction
following conditions must be observed:
There is no soldering method that is ideal for all IC • A double-wave (a turbulent wave with high upward
packages. Wave soldering is often preferred when pressure followed by a smooth laminar wave)
through-hole and surface mounted components are mixed soldering technique should be used.
on one printed-circuit board. However, wave soldering is
• The footprint must be at an angle of 45° to the board
not always suitable for surface mounted ICs, or for
direction and must incorporate solder thieves
printed-circuits with high population densities. In these
downstream and at the side corners.
situations reflow soldering is often used.
During placement and before soldering, the package must
This text gives a very brief insight to a complex technology.
be fixed with a droplet of adhesive. The adhesive can be
A more in-depth account of soldering ICs can be found in
applied by screen printing, pin transfer or syringe
our “IC Package Databook” (order code 9398 652 90011).
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Maximum permissible solder temperature is 260 °C, and
Reflow soldering techniques are suitable for all QFP
maximum duration of package immersion in solder is
packages.
10 seconds, if cooled to less than 150 °C within
The choice of heating method may be influenced by larger 6 seconds. Typical dwell time is 4 seconds at 250 °C.
plastic QFP packages (44 leads, or more). If infrared or
A mildly-activated flux will eliminate the need for removal
vapour phase heating is used and the large packages are
of corrosive residues in most applications.
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
Repairing soldered joints
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality Fix the component by first soldering two diagonally-
Reference Handbook” (order code 9397 750 00192). opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
Reflow soldering requires solder paste (a suspension of
time must be limited to 10 seconds at up to 300 °C. When
fine solder particles, flux and binding agent) to be applied
using a dedicated tool, all other leads can be soldered in
to the printed-circuit board by screen printing, stencilling or
one operation within 2 to 5 seconds between
pressure-syringe dispensing before package placement.
270 and 320 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION
Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

1998 Feb 16 35
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1998 Feb 16 36
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

NOTES

1998 Feb 16 37
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

NOTES

1998 Feb 16 38
Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345
Compact Disc

NOTES

1998 Feb 16 39
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Middle East: see Italy

For all other countries apply to: Philips Semiconductors, Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

© Philips Electronics N.V. 1998 SCA57

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.

Printed in The Netherlands 545102/00/05/pp40 Date of release: 1998 Feb 16 Document order number: 9397 750 03314