EC2002

8085 Microprocessors

Sachin Kumar Jain

PDPM-IIITDM Jabalpur
[email protected]

Teachers open the door but you must enter by yourself

---Chinese Proverb
 Microprocessor Operations
• Instruction word size
The machine codes of all the instructions are not of the
same size. For 8085, the data size is 8-bit, accordingly, an
instruction could be:
• 1-byte (For example: ADD M, MOV A,B)
• 2-byte (For example: ANI 3E, MVI A, 6C)
• 3-byte (For example: LXI H, 2300, LDA 2500)

Note: There is no direct relationship between the size of an

instruction and the number of machine cycles/T-stats
required to execute that instruction.
 Microprocessor Operations
• Control and Status Signals
ALE – It is an Address Latch Enable signal. It goes high
during first T state of a machine cycle and enables the lower
8-bits of the address, if its value is 1 otherwise data bus is
activated.
IO/M’ – It is a status signal which determines whether the
address is for input-output or memory. When it is high(1) the
address on the address bus is for input-output devices. When
it is low(0) the address on the address bus is for the memory.
SO, S1 – These are status signals. They distinguish the
various types of operations such as halt, reading, instruction
fetching or writing.
 Microprocessor Operations
• Control and Status Signals
RD’ – It is a signal to control READ operation. When it is
low the selected memory or input-output device is read.
WR’ – It is a signal to control WRITE operation. When it
goes low the data on the data bus is written into the selected
memory or I/O location.
READY – It senses whether a peripheral is ready to transfer
data or not. If READY is high(1) the peripheral is ready. If it
is low(0) the microprocessor waits till it goes high. It is
useful for interfacing low speed devices.
Microprocessor Operations
Microprocessor Operation is an activity or event that a
microprocessor performs during execution of an
instruction/set of instructions (program)/etc.
For example: Memory read operation, I/O read, etc.
These operations are performed in a synchronized manner
with the system clock. Following terms are necessary to
understand the microprocessor operations:
• T-State
• Machine cycle
• Instruction cycle
Microprocessor Operations
• T-State: A portion of an operation carried out in one
system clock period is called as T-state. It is a subdivision
of the operation performed in one clock period.
• Machine cycle: The time required to execute a complete
microprocessor operations/event is called machine cycle.
A machine cycle may need typically 3 to 6 T-states.
• Instruction cycle: The time required to execute an
instruction is called instruction cycle. It always consists of
an opcode fetch machine cycle. It may further have up to
five machine cycles to execute the instruction completely.
For example: MVI A,20H involves two machine cycles to
execute it, an opcode fetch and a memory read.
Microprocessor Operations
Cycle IO/M’ S1 S0 Control Signal

Opcode fetch 0 1 1 𝑅𝐷 = 0

Memory read 0 1 0 𝑅𝐷 = 0

Memory write 0 0 1 𝑊𝑅 = 0

I/O read 1 1 0 𝑅𝐷 = 0

I/O write 1 0 1 𝑊𝑅 = 0

Interrupt acknowledge 1 1 1 𝐼𝑁𝑇𝐴 = 0

Halt (Bus Idle) Z 0 0 𝑅𝐷 = 𝑍

𝑊𝑅 = 𝑍
Hold Z x x 𝐼𝑁𝑇𝐴 = 1
Reset Z x x
Microprocessor Operations
• Interrupt acknowledge: In response to INTR signal,
8085 executes interrupt acknowledge machine cycle to
read an instruction from the external device. Theoretically,
the external device can place any instruction on the data
bus in response to INTA.
• Halt (Bus Idle): In this condition, the machine cycles are
neither Read nor Write. There may be some internal
operations (e.g. in DAD), but the buses remain free.
Microprocessor Operations
• Hold: It indicates that another device is requesting the use
of the address and data bus. Having received HOLD
request the μP relinquishes the use of the buses as soon as
the current machine cycle is completed. Internal
processing may continue. After the removal of the HOLD
signal the processor regains the bus.
• Reset: All internal operations are suspended, the program
counter is set to zero, the buses are high-impedance mode
(tri-stated), and μP is reset.
 Microprocessor Operations
• Timing Diagram

Courtesy: https://www.bing.com/images/
 Microprocessor Operations
• Timing Diagram

Courtesy: https://www.bing.com/images/
 Microprocessor Operations
• Timing Diagram

Courtesy: https://www.bing.com/images/
 8085: Assembly Language
• Instruction
An instruction is a command /order given to the
microprocessor to perform a specified operation on given data.

• Mnemonic
Two/Three or Four letter English like short word to represent
an instruction in ALP.
• Opcode
Operation CODE is a first part of the instruction in the 8-bit
binary format that specify the task to be performed by the
instruction to the microprocessor.
• Operand
It is the data on which a particular operation is to be performed. It
can be in the form of 8/16-bit data, register, memory location, etc.
 8085: Assembly Language
• Instruction Set
Collection of the instructions that the microprocessor
is designed to execute.

Intel 8085 Instruction Set

Data Transfer Group
Arithmetic Operations Group
Logical Operations Group
Branch Control Group
Machine Control Group
 Data Transfer Group
Instructions of this group copies data from a location called
a source to another location, called a destination,
without modifying the contents of the source. Source

1. Between Registers MOV C,B

2. Any data to a register MVI D, data

3. Between Memory & Register LDA address

4. Between IO & Accumulator IN address(8-bit)

No flag is affected by execution of any data transfer instruction.

Arithmetic Operation Group
Instructions of this group performs arithmetic operations
such as addition, subtraction etc.
Addition/Subtraction
Any 8-bit number or the contents of a register or memory can be
added to the contents of the Accumulator. The result is stored in the
Accumulator. DAD is an exception that adds 16-bit data.

Increment/Decrement
The 8/16-bit contents of a register or a memory can be incremented
or decremented by 1.

All flags are affected. But in INR/DCR carry flag is not affected.
In 16bit operations (DAD) only carry flag is affected.
 Logical Operation Group
Instructions of this group performs logical operations
with the contents of the accumulator.
AND/OR/Ex-OR
Any logic operation can be performed on any 8-bit number or the contents of a register
or memory with the contents of the Accumulator. The result is stored in the Accumulator.

Rotate
Each bit in the accumulator can be shifted left or right to next position.

Complement
The contents of the accumulator can be complemented.

Compare
Any 8-bit number or the contents of a register or memory can be compared for equality,
greater than, or less than, with the contents of the Accumulator.

Instruction of this group affects all flags.

 Branch Control Group
This group of instructions alters the sequence of program
execution either conditionally or unconditionally.
Jump
These instructions tests for a certain condition and alter the program
sequence when the condition is met. Unconditional Jump is also possible.

Call/Return/Restart
These instructions change the sequence of a program either by
calling a subroutine or returning from it with/without any condition.

No reason for flags to be affected.

Machine Control Operations
These instructions control machine functions such as
Halt, Interrupt or do nothing (NOP).
Interrupt Related
EI (Enable Interrupt)

SIM (Set Interrupt Mask)

Stack Related

PUSH B (Push the contents of register pair to stack)

SPHL (Move the contents of H-L to stack pointer)

Special Instruction

NOP (No operation)

HLT (Stops the execution of program)

 Addressing Modes
The techniques for specifying operand (data) of any
instruction are called addressing modes.

Intel 8085 Addressing Modes

Direct Addressing

Register Addressing

Register Indirect Addressing

Immediate Addressing

Implicit Addressing
 8085 Instruction Set
Data Transfer Group
MOV Rd, Rs
It Copies the contents of the source register into the destination register. If one of
the operands is a memory location, it is specified by the contents of HL registers.

MVI R, data
8-bit data is stored in the register or memory (specified by HL pair).

LXI Rp, data

It loads 16-bit data in the destination register pair. Second byte of this three byte
instruction is low order byte and the third byte specifies the high-order byte.
LXI D, 1250H 11 50 12
Opcode High order byte,
stored in Reg.D
Low order byte,
D E
stored in Reg.E 12 50
 8085 Instruction Set
Data Transfer Group
To
LDA addr Memory Accumulator

The contents of a memory location, specified by a 16-bit address in the operand,

are loaded (copied) to the accumulator. Second byte of this three-byte instruction
specifies low order address, and the third byte specifies the high-order address.

To
STA addr Accumulator Memory

The contents of the accumulator are copied to a memory location, specified by

the operand. Similar as LDA above but reverse action.

LDAX(STAX) Rp
The contents of a memory location, specified by a register pair in the operand
(BC or DE), are loaded (copied) to the accumulator/vice-versa for STAX.
D E Address Data To
Accumulator
12 50 1250 25
1251 6A
1252 0D
 8085 Instruction Set
Data Transfer Group

LHLD(SHLD) addr
The instruction copies the contents of the memory location pointed out by the 16-
bit address is register L and copies the contents of the next memory location in
the register H.

H L
05 10 Address Data
LHLD 1250
1250 25
6A 25 1251 6A
1252 0D
 8085 Instruction Set
Data Transfer Group
To
In addr (8-bit) I/O Port Accumulator

The contents of the input port designated in the operand (addr) are read and
loaded into the accumulator.

To
Out addr (8-bit) Accumulator Output Port

The contents of the accumulator are copied into the output port specified by the
operand (8 bit address).

OUT 01

Accumulator Port A
To 01H
1E
Port B
11H
 8085 Instruction Set
Arithmetic Operation Group
ADD R
The contents of the operand (register or memory) are added to the contents of
the accumulator and the result is stored in the accumulator.

ADC R
The contents of the operand (register or memory) and the Carry flag are added
to the contents of the accumulator and the result is stored in the accumulator.
The contents of the operand are not altered; but, the previous CY flag is reset.
Accumulator B Carry Flag
05 10 1 + 00000101 + 00010000 = 00010110
ADC B
16 10 0 + 00010110 + 00010000 = 00100110
ADC B
26 10 0
 8085 Instruction Set
Arithmetic Operation Group
SUB R
The contents of the operand (register or memory) are subtracted from the
contents of the accumulator and the result is stored in the accumulator.

SBB R
The contents of the operand (register or memory) and the Borrow flag are
subtracted from the contents of the accumulator and the result is stored in the
accumulator. The previous Borrow flag is reset.
Accumulator D Borrow Flag
15 10 -1 + 00010101 - 00010000 = 00010110
SBB D
04 10 -0 + 00000100 - 00010000 = 11110100
SBB D
F4 10 1
 8085 Instruction Set
Arithmetic Operation Group
ADI/SUI data
The 8-bit data (operand) are added/subtracted to/from the content of the
accumulator and the result is stored in the accumulator.

ACI/SBI data
The 8-bit data (operand) and the Carry/Borrow flag are added/Subtracted to the
contents of the accumulator and the result is stored in the accumulator. The
contents of the operand are not altered; but, the previous CY flag is reset.
Accumulator Carry Flag
15 1 00010101 + 00000100 = 00011001
ACI 04H
1A 0 00011001 - 00000010 = 00010111
SUI 02H
18 0
 8085 Instruction Set
Arithmetic Operation Group
INR/DCR R
The contents of the designated register/memory are incremented/decremented by
1 and the results are store in the same place. All but carry flag are affected.

INX/DCX Rp
The contents of the designated register pair are incremented/decremented by 1
and the results are store in the same place. Contents of two registers are treated
as a 16-bit number.
B C Carry Flag
15 FE 1
INR C
15 FF 1
INX B
16 00 1
Flags are not affected
 8085 Instruction Set
Arithmetic Operation Group
DAD Rp
The 16-bit contents of the designated register pair are added to the contents of the
HL register and the sum is stored in the HL register. Only carry flag is affected.

H L B C Carry Flag
15 02 + 03 13 1
DAD B
18 15 03 A2 0

Instruction Size: 1 Byte

Instruction Cycle = 3 Machine Cycles = 10 T-states
 8085 Instruction Set
Logic Operation Group
ANA/ORA/XRA R
The contents of the accumulator are logically AND/OR/Ex-ORed with the contents
of the operand (register/memory), and the result is placed in the accumulator.
S, Z and P flags are modified to reflect the result. CY is reset in all cases, but
AC is set in AND operation but reset in OR and Ex-OR operations.

ANI/ORI/XRI data
The contents of the accumulator are logically AND/OR/Ex-ORed with the 8-bit data
(operand), and the result is placed in the accumulator.
A C S Z AC P CY
15 76 1 1 1 1 1
ANA C
14 76 0 0 1 1 0
ORI 1FH
1F 76 0 0 0 0 0
 8085 Instruction Set
Logic Operation Group
CMP R / CPI data
The contents of the operand (register/memory or immediate data) are compared
with the contents of the accumulator. Both contents are preserved and the
comparison is shown by setting the flags as follows:
❖ If (A) < (Reg/Mem): Carry flag is set and Zero flag is reset.
❖ If (A) = (Reg/Mem): Carry flag is reset and Zero flag is set.
❖ If (A) > (Reg/Mem): Both Carry flag and Zero flag are reset.

A C S Z AC P CY
11 08 1 1 1 1 1
CMP C
11 08 0 0 1 1 0
CPI 1FH
11 08 1 0 1 0 1
 8085 Instruction Set
Branch Control Group
Jump
The program sequence is transferred to the memory location specified by the 16-bit
address. The second byte specifies low order byte and third byte specifies the high
order byte of address. Following jump instructions are available in 8085:
❖ JMP addr: Unconditional Jump to the address.
❖ JC addr: Jump on Carry
❖ JNC addr: Jump on No Carry
❖ JZ addr: Jump on Zero
❖ JNZ addr: Jump on No Zero
❖ JP addr: Jump on Positive
❖ JM addr: Jump on Minus
❖ JPE addr: Jump on Even Parity
❖ JPO addr: Jump on Odd Parity
 8085 Instruction Set
Branch Control Group
Call/Return
The program sequence is transferred to the memory location specified by the 16-bit
address. Before the transfer, the address of the next instruction to CALL is pushed
on the stack. During return two top bytes of the stack are copied into the program
counter. Following Call instructions are available in 8085:
❖ CMP addr: Unconditional Call to the address.
❖ CC addr: Call on Carry
❖ CNC addr: Call on No Carry
❖ CZ addr: Call on Zero
❖ CNZ addr: Call on No Zero
❖ CP addr: Call on Positive
❖ CM addr: Call on Minus
❖ CPE addr: Call on Even Parity
❖ CPO addr: Call on Odd Parity
 8085 Instruction Set
Branch Control Group
PCHL
The contents of registers H & L are copied into the program counter. The contents
of H are placed as a high-order byte and of L as a low-order byte. This is one byte
instruction however its only machine cycle has six T-states.

This is also like Unconditional Jump instruction that change the sequence of the
program by simply loading PC with contents of HL.

H L Program Counter
21 30 2006
PCHL
21 30 2130
 8085 Instruction Set
Machine Control Group
PUSH/POP Rp
The contents of the register pair designated in the operand are copied into the stack
in the following sequence. The stack pointer register is decremented and the
contents of the high-order register are copied into that location. The stack pointer
register is decremented again and the contents of the low-order register are copied
to that location.