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C421 Combinational Logic Part2 B

The document contains a 4-input Karnaugh map with the variables A, B, C, D and the output Y. The K-map shows the minterm values for all possible combinations of the input variables. The simplified Boolean expression for the output Y is given as Y = AC + ABD + ABC + BD, which summarizes the essential information from the K-map.

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0% found this document useful (0 votes)
9 views24 pages

C421 Combinational Logic Part2 B

The document contains a 4-input Karnaugh map with the variables A, B, C, D and the output Y. The K-map shows the minterm values for all possible combinations of the input variables. The simplified Boolean expression for the output Y is given as Y = AC + ABD + ABC + BD, which summarizes the essential information from the K-map.

Uploaded by

colin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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4-Input K-Map

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1 01
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0 10
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

C421 Digital Design 22 Indiana University South Bend


4-Input K-Map

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 0 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1 01 0 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11 1 1 0 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0 10 1 1 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

C421 Digital Design 23 Indiana University South Bend


4-Input K-Map

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 0 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1 01 0 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11 1 1 0 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0 10 1 1 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0 Y = AC + ABD + ABC + BD

C421 Digital Design 24 Indiana University South Bend


K-Maps with Don’t Cares

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00
0 1 0 0 0
0 1 0 1 X
0 1 1 0 1 01
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X 10
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

C421 Digital Design 25 Indiana University South Bend


K-Maps with Don’t Cares

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 X 1
0 1 0 0 0
0 1 0 1 X
0 1 1 0 1 01 0 X X 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11 1 1 X X
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X 10 1 1 X X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

C421 Digital Design 26 Indiana University South Bend


K-Maps with Don’t Cares

A B C D Y Y
0 0 0 0 1 AB
0 0 0 1 0 CD 00 01 11 10
0 0 1 0 1
0 0 1 1 1 00 1 0 X 1
0 1 0 0 0
0 1 0 1 X
0 1 1 0 1 01 0 X X 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1 11 1 1 X X
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X 10 1 1 X X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X Y = A + BD + C

C421 Digital Design 27 Indiana University South Bend


Exercise
 Minimize the following problems using the Karnaugh maps
method

 Z = f(A,B,C) = A’B’C’ + A’B + ABC’ + AC

 Z = f(A,B,C) = A’B + BC’ + BC + AB’C’

C421 Digital Design 28 Indiana University South Bend


Combinational Building Blocks

 Multiplexers
 Decoders

C421 Digital Design 29 Indiana University South Bend


Multiplexer (Mux)
 Selects between one of N inputs to connect to output
 log2N-bit select input – control input
 Mainly used as data selectors
 Example: 2:1 Mux
S

D0 0
Y
D1 1

S D1 D0 Y S Y
0 0 0 0 0 D0
0 0 1 1 1 D1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

C421 Digital Design 30 Indiana University South Bend


Multiplexer Implementations
 Logic gates  Tristates
 Sum-of-products form – For an N-input mux, use
N tristates
Y
D0 D1
S
00 01 11 10 – Turn on exactly one to
0 0 0 1 1 select the appropriate
input
1 0 1 1 0
S
Y = D0S + D1S
D0
D0
Y

D1

S
D1

2-<31>

C421 Digital Design 31 Indiana University South Bend


Logic using Multiplexers

Using mux as a lookup table


A B Y
0 0 0
0 1 0
1 0 0
1 1 1
Y = AB
AB
00
01
10
Y
11

C421 Digital Design 32 Indiana University South Bend


Logic using Multiplexers

Use multiplexers to implement Boolean


functions

https://www.youtube.com/watch?v=Kn72
EyTrmsM

C421 Digital Design 33 Indiana University South Bend


Decoders

• N inputs, 2N outputs
• One-hot outputs: only one output HIGH at
once 2:4
Decoder
11 Y3
A1 10 Y2
A0 01 Y1
00 Y0

A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

C421 Digital Design 34 Indiana University South Bend


Decoder Implementation

A1 A0

Y3

Y2

Y1

Y0

C421 Digital Design 35 Indiana University South Bend


Logic Using Decoders

OR minterms
2:4
Decoder Minterm
11 AB
A 10 AB
B 01 AB
00 AB

Y = AB + AB
= A  B Y

C421 Digital Design 36 Indiana University South Bend


Timing

• Delay: time between input change and


output changing
• How to build fast circuits?
A Y

delay

Time

C421 Digital Design 37 Indiana University South Bend


Propagation & Contamination Delay

• Propagation delay: tpd = max delay from input to


output
• Contamination delay: tcd = min delay from input
to output
A Y

tpd

tcd

Time

C421 Digital Design 38 Indiana University South Bend


Propagation & Contamination Delay

• Delay is caused by
– Capacitance and resistance in a circuit
– Speed of light limitation
• Reasons why tpd and tcd may be
different:
– Different rising and falling delays
– Multiple inputs and outputs, some of which
are faster than others
– Circuits slow down when hot and speed up
when cold

C421 Digital Design 39 Indiana University South Bend


Critical (Long) & Short Path Paths

Critical Path

A n1
B
n2
C
D Y

Short Path

Critical (Long) Path: tpd = 2tpd_AND + tpd_OR


Short Path: tcd = tcd_AND

C421 Digital Design 40 Indiana University South Bend


Glitches

• When a single input change causes an


output to change multiple times

C421 Digital Design 41 Indiana University South Bend


Glitch Example

• What happens when A = 0, C = 1, B


falls? A
B
Y

Y
AB
00 01 11 10
C
0 1 0 0 0

1 1 1 1 0

Y = AB + BC

C421 Digital Design 42 Indiana University South Bend


Glitch Example (cont.)
Critical Path
A=0 0 1
B=1 0 n1
Y=1 0 1
n2
C=1 1 0

Short Path

n2

n1

Y glitch

Time

C421 Digital Design 43 Indiana University South Bend


Fixing the Glitch

Y
AB
00 01 11 10
C
0 1 0 0 0

1 1 1 1 0

AC Y = AB + BC + AC

A=0
B=1 0
Y=1

C=1

C421 Digital Design 44 Indiana University South Bend


Why Understand Glitches?

• Can’t get rid of all glitches –


simultaneous transitions on multiple
inputs can also cause glitches
• It is important to be aware that they
exist
• It’s important to recognize a glitch: in
simulations or on oscilloscope

C421 Digital Design 45 Indiana University South Bend

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