0% found this document useful (0 votes)

66 views189 pages

STMicroelectronics 8165

Uploaded by

Александр Шевель

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

66 views189 pages

STMicroelectronics 8165

Uploaded by

Александр Шевель

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 189

PRODUCT/PROCESS

® CHANGE NOTIFICATION
PCN MMS-MMY/13/8165
Dated 14 Oct 2013

M95010, M95020, M95040, M95080, M95160 1-Kbit, 2-Kbit,

4-Kbit, 8-Kbit, 16-Kbit SPI bus EEPROM / Industrial
grade Redesign and upgrade to the CMOSF8H

1/192
PCN MMS-MMY/13/8165 - Dated 14 Oct 2013

Table 1. Change Implementation Schedule

Forecasted implementation date for 07-Oct-2013
change

Forecasted availability date of samples 07-Oct-2013

for customer

Forecasted date for STMicroelectronics

change Qualification Plan results availability 07-Oct-2013

Estimated date of changed product first 13-Jan-2014

shipment

Table 2. Change Identification

Product Identification 1, 2, 4, 8, 16-Kbit SPI bus EEPROM indus. grade
(Product Family/Commercial Product)

Type of change Waferfab technology change

Reason for change Line up to state-of-the-art of process

Description of the change Redesign and upgrade to the new CMOSF8H Process technology.

Change Product Identification Proc. techno identifier "K" for SO8N

Manufacturing Location(s)

® 2/192
PCN MMS-MMY/13/8165 - Dated 14 Oct 2013

DOCUMENT APPROVAL

Name Function

Leduc, Hubert Marketing Manager

Rodrigues, Benoit Product Manager

Pavano, Rita Q.A. Manager

® 4/192
PRODUCT / PROCESS
CHANGE NOTIFICATION

M95010, M95020, M95040, M95080, M95160

1-Kbit, 2-Kbit, 4-Kbit, 8-Kbit, 16-Kbit
SPI bus EEPROM / Industrial grade
Redesign and upgrade to the CMOSF8H process technology

What is the change?

The M95010, M95020, M95040, M95080 and M95160, 1-Kbit, 2-Kbit, 4-Kbit, 8-Kbit and 16-Kbit SPI
bus EEPROM product families for Industrial grade, currently produced using the CMOSF6SP 36%
process technology at ST Ang Mo Kio (Singapore) 6” or at GLOBALFOUNDRIES (Singapore) 8” wafer
diffusion plants, have been redesigned and will be upgraded to the CMOSF8H process technology at
ST Rousset (France) 8” wafer diffusion plant.

This upgraded version in CMOSF8H allows offering:

- 1.7 V / 5.5 V (“-F”) Vcc range over industrial temperature range -40 / +85°C
- Enhanced cycling and data retention performances:
4 million cycles
200 years data retention

The new M95010, M95020 and M95040 in CMOSF8H version are functionally compatible with the
current CMOSF6SP 36% version as per common datasheet rev. 11 – May 2013, attached.
The new M95080 in CMOSF8H version is functionally compatible with the current CMOSF6SP 36%
version as per datasheet rev. 1 – March 2012 attached.
The new M95160 in CMOSF8H version is functionally compatible with the current CMOSF6SP 36%
version as per datasheet rev. 3 – January 2013 attached.

Differences from current datasheets:

DC characteristic: ICC1 standby supply current:
- Max 2 µA at VCC = 2.5 V
- Max 3 µA at VCC = 5.5 V

Concurrent to this change, the new M95010, M95020, M95040, M95080 and M95160 in CMOSF8H will
be assembled with 0.8 mil Copper wire when packaged in SO8N or in UFDFPN8 (MLP8).

Why?
The strategy of STMicroelectronics Memory Division is to support our customers on a long-term basis.
In line with this commitment, the qualification of the M95010, M95020, M95040, M95080 and M95160
in the new CMOSF8H process technology will increase the production capacity throughput and
consequently improve the service to our customers.

When?
The production of the upgraded new M95010, M95020, M95040, M95080 and M95160 with the new
CMOSF8H will ramp up from December 2013 and shipments can start from January 2014 onward (or
earlier upon customer approval).
M95010, M95020, M95040, M95080, M95160
1-Kbit, 2-Kbit, 4-Kbit, 8-Kbit, 16-Kbit
SPI bus EEPROM / Industrial grade
Redesign and upgrade to the CMOSF8H process technology

How will the change be qualified?

The new version of the new M95010, M95020, M95040, M95080 and M95160 in CMOSF8H will be
qualified using the standard ST Microelectronics Corporate Procedures for Quality & Reliability.

The Qualification Reports are available and included inside this document:
- QRMMY1316 for M95020
- QRMMY1315 for M95040
- QRMMY1314 for M95080
- QRMMY1205 for M95160

The Qualification report QRMMY1324 for M95010 will be available Week 50.

What is the impact of the change?

- Form: Marking change (see Device marking paragraph)

- Fit: No change

- Function: DC characteristic: ICC1 standby supply current:

- Max 2 µA at VCC = 2.5 V
- Max 3 µA at VCC = 5.5 V

2
M95010, M95020, M95040, M95080, M95160
1-Kbit, 2-Kbit, 4-Kbit, 8-Kbit, 16-Kbit
SPI bus EEPROM / Industrial grade
Redesign and upgrade to the CMOSF8H process technology

How can the change be seen?

- BOX LABEL MARKING

On the BOX LABEL MARKING, the difference is visible inside the Finished Good Part Number:
the process technology identifier is “K” for the upgraded version in CMOSF8H, this identifier
being “G” or “S” for the current version in CMOSF6SP 36%.

Example for M95080-WMN6TP

Manufactured under patents or patents pending

Country Of Origin: XXXX
Pb-free 2nd Level Interconnect
MSL: 1 NOT MOISTURE SENSITIVE

Trace Codes PPYWWLLL WX TF

Marking 95080WP

Bulk ID X0X00XXX0000

Please provide the bulk ID for any inquiry

3
M95010, M95020, M95040, M95080, M95160
1-Kbit, 2-Kbit, 4-Kbit, 8-Kbit, 16-Kbit
SPI bus EEPROM / Industrial grade
Redesign and upgrade to the CMOSF8H process technology

How can the change be seen?

- DEVICE MARKING

For the SO8N package, the difference is visible inside the trace code (PYWWT) where the last
digit T for process technology is “K” for the upgraded version in CMOSF8H, this digit being
“Q” for current version.

Upgraded Current
CMOSF8H CMOSF6SP 36%
(ST Rousset) (ST Ang Mo Kio
or
GLOBALFOUNDRIES)

SO8N 95080WP 95080WP

Example:
M95080-WMN6TP PYWWK PYWWQ

For the TSSOP8 package, the difference is visible inside the product name where the last digit is
“K” for the upgraded version in CMOSF8H, this digit being “P” for current version.

Upgraded Current
CMOSF8H CMOSF6SP 36%
(ST Rousset) (ST Ang Mo Kio
or
GLOBALFOUNDRIES)

TSSOP8 O 508WK O 508WP

Example:
M95080-WDW6TP PYWW PYWW

For the UFDFPN8 package, the difference is visible inside the product name: upgraded version
in CMOSF8H is 5DRK, current version is 516R.

Upgraded Current
CMOSF8H CMOSF6SP 36%
(ST Rousset) (ST Ang Mo Kio
or
GLOBALFOUNDRIES)

UFDFPN8 O 5DRK O 516R

Example: PYWW PYWW
M95160-RMC6TG

4
M95010, M95020, M95040, M95080, M95160
1-Kbit, 2-Kbit, 4-Kbit, 8-Kbit, 16-Kbit
SPI bus EEPROM / Industrial grade
Redesign and upgrade to the CMOSF8H process technology

Appendix A- Product Change Information

Product family / Commercial products: 1-Kbit, 2-Kbit, 4-Kbit, 8-Kbit, 16-Kbit SPI bus
EEPROM / Industrial grade

Customer(s): All

Type of change: Wafer fab process technology change

Reason for the change: Line up to state-of-the-art of process

Description of the change: Redesign and upgrade to the new CMOSF8H

Process technology.
Forecast date of the change: Week 41 / 2013
(Notification to customer)

Forecast date of
Qualification samples availability for
customer(s): See details in APPENDIX B

Forecast date for the internal

STMicroelectronics change, The Qualification Reports are available and
Qualification Report availability: included inside this document.

The Qualification report QRMMY1324 for

M95010 will be available Week 50.)

Marking to identify the changed product: Process Technology identifier “K”

for CMOSF8H for SO8N.
Description of the qualification program: Standard ST Microelectronics Corporate
Procedures for Quality and Reliability
Product Line(s) and/or Part Number(s): See Appendix B

Manufacturing location: Rousset 8 inch wafer fab

Estimated date of first shipment: Week 02 / 2014

5
M95010, M95020, M95040, M95080, M95160
1-Kbit, 2-Kbit, 4-Kbit, 8-Kbit, 16-Kbit
SPI bus EEPROM / Industrial grade
Redesign and upgrade to the CMOSF8H process technology

Appendix B: Concerned Commercial Part Numbers:

Commercial Package Samples

Part Numbers availability
M95010-RDW6TP TSSOP8 December 2013
M95010-RMN6TP SO8N December 2013
M95010-WDW6TP TSSOP8 December 2013
M95010-WMN6P SO8N December 2013
M95010-WMN6TP SO8N December 2013
M95020-RDW6TP TSSOP8 November 2013
M95020-RMN6TP SO8N November 2013
M95020-WDW6TP TSSOP8 November 2013
M95020-WMN6P SO8N November 2013
M95020-WMN6TP SO8N November 2013
5C.P2A02.013 SO8N October 2013
M95040-RDW6TP TSSOP8 October 2013
M95040-RMC6TG UFDFPN8 October 2013
M95040-RMN6TP SO8N October 2013
M95040-WDW6TP TSSOP8 October 2013
M95040-WMN6P SO8N October 2013
M95040-WMN6TP SO8N October 2013
M95080-RDW6TP TSSOP8 October 2013
M95080-RMC6TG UFDFPN8 October 2013
M95080-WDW6TP TSSOP8 October 2013
M95080-WMN6P SO8N October 2013
M95080-WMN6TP SO8N October 2013
M95160-RDW6TP TSSOP8 October 2013
M95160-RMC6TG UFDFPN8 October 2013
M95160-RMN6TP SO8N October 2013
M95160-WDW6TP TSSOP8 October 2013
M95160-WMN6P SO8N October 2013
M95160-WMN6TP SO8N October 2013

6
M95010, M95020, M95040, M95080, M95160
1-Kbit, 2-Kbit, 4-Kbit, 8-Kbit, 16-Kbit
SPI bus EEPROM / Industrial grade
Redesign and upgrade to the CMOSF8H process technology

Appendix C: Qualification Reports:

See following pages

7
QRMMY1316
Qualification report
New design / M95020-R M95020-W M95020-A125 M95020-A145
using the CMOSF8H technology in the Rousset 8” Fab

Table 1. Product information

General information

M95020-RMN6TP
M95020-RDW6TP
Commercial product M95020-WDW6TP
M95020-WMN6P
M95020-WMN6TP
Product description 2 Kbit serial SPI bus EEPROMs with high-speed clock
Product group MMS
Product division MMY - Memory
Silicon process technology CMOSF8H
Wafer fabrication location RS8F - ST Rousset 8”, France
ST Rousset, France
Electrical Wafer Sort test plant location ST Toa Payoh, Singapore
Subcontractor Ardentec, Singapore

Table 2. Package description

Package description Assembly plant location Final test plant location

ST Shenzhen, China ST Shenzhen, China

SO8N
Subcontractor Amkor, Philippines Subcontractor Amkor, Philippines
ST Shenzhen, China ST Shenzhen, China
TSSOP8
Subcontractor Amkor, Philippines Subcontractor Amkor, Philippines

UFDFPN8 (MLP8) ST Calamba, Philippines ST Calamba, Philippines

2 x 3 mm Subcontractor Amkor, Philippines Subcontractor Amkor, Philippines

Reliability / Qualification assessment: PASS

September 2013 Rev 1 1/13

www.st.com
Reliability evaluation overview QRMMY1316

1 Reliability evaluation overview

1.1 Objectives
This qualification report summarizes the results of the reliability trials that were performed to
qualify the new design M95020-W, M95020-R, M95020-A125 and M95020-A145 using the
CMOSF8H silicon process technology in the ST Rousset 8” diffusion fab.
The CMOSF8H is a new advanced silicon process technology that is already qualified in the
ST Rousset 8” fab, and in production for M24M02/M95M02, M24M01/M95M01,
M24512/M95512, M24256/M95256, M24128/M95128, M24C64/M95640, M24C32/M95320,
M95160, M95080 and M95040 EEPROM general purpose products.
The CMOSF8H technology is also qualified for automotive grade using M95640-A125 and
M95640-A145 as driver products.
This document serves for the qualification of the named product using the named silicon
process technology in the named diffusion fab.
The voltage and temperature ranges covered by this document are:
• 2.5 to 5.5 V at –40 to 85 °C for M95020-W devices
• 1.8 to 5.5 V at –40 to 85 °C for M95020-R devices
• 1.8 to 5.5 V at –40 to 125 °C for M95020-A125 devices (automotive grade 1)
• 2.5 to 5.5 V at –40 to 145 °C for M95020-A145 devices (automotive grade 0)

1.2 Conclusion
The new design M95020-W, M95020-R using the CMOSF8H silicon process technology in
the ST Rousset 8” diffusion fab have passed all the reliability requirements and all products
described in Table 1 are qualified.
Refer to Section 3: Reliability test results for details.
The reliability test results apply also to M95020-A125 and M95020-A145 devices which are
forecasted to be fully qualified at completion of 2000 hours stress (Week 47’2013).

2/13 Rev 1
QRMMY1316 Device characteristics

2 Device characteristics

The new design M95020-W, M95020-R, M95020-A125 and M95020-A145 are electrically
erasable programmable memory (EEPROM) devices based on advanced true EEPROM
technology.
The M95020-W, M95020-R, M95020-A125 and M95020-A145 are byte-alterable memories
(256 × 8 bits) organized as 16 pages of 16 bytes in which the data integrity is significantly
improved with an embedded Error Correction Code logic.
The devices are accessed by a simple serial SPI compatible interface.
The M95020 devices can operate with a supply range from 1.8 V up to 5.5 V, and are
guaranteed over the -40 °C/+85 °C temperature range.
The M95020-A125 and M95020-A145 are 2-Kbit serial EEPROM Automotive grade devices
operating up to 125 °C and 145 °C respectively. They are compliant with the very high level
of reliability defined by the Automotive standard AEC-Q100 grade 0.
Refer to the product datasheet for more details.

Rev 1 3/13
13
Reliability test results QRMMY1316

3 Reliability test results

This section contains a general description of the reliability evaluation strategy. The named
products are qualified using the standard STMicroelectronics corporate procedures for
quality and reliability.
The CMOSF8H process technology and EEPROM new design core have been qualified for
Automotive products on 3 lots using the driver product M95640 (refer to qualification report
QREE0921).
The M95020 is designed with the same technology and similar architecture as the driver
product M95640/M95160.
The product vehicle used for the die qualification is presented in Table 3.

Table 3. Product vehicles used for die qualification

Silicon process Wafer fabrication Package Assembly plant
Product
technology location description location

M95020 /
CMOSF8H ST Rousset 8” CDIP8 Engineering assy (1)
M95160
1. CDIP8 is a engineering ceramic package used only for die-oriented reliability trials.

The product vehicles used for package qualification are presented in Table 4.

Table 4. Product vehicles used for package qualification

Silicon process Wafer fabrication Assembly plant
Product Package description
technology location location

M95020 / SO8N ST Shenzhen

CMOSF8H ST Rousset 8”
M95160 (1)(2) TSSOP8 ST Shenzhen
SO8N ST Shenzhen
M95640 (2) CMOSF8H ST Rousset 8”
TSSOP8 ST Shenzhen
ST Shenzhen /
SO8N
subcon Amkor
ST Shenzhen /
M24C64 (2) CMOSF8H ST Rousset 8” TSSOP8
subcon Amkor
UFDFPN8 (MLP8) ST Calamba /
2 x 3 mm subcon Amkor
1. Qualification on 3 lots using the product driver M95640 - Qualification of M95160/M95020 benefits of the
family approach (1 lot).
2. Larger memory array using the same silicon process technology in the same diffusion fab. Package
qualification results of M95640/M24C64/M95160 are applicable to M95020.

4/13 Rev 1
QRMMY1316 Reliability test results

3.1 Reliability test plan and result summary

The reliability test plan and the result summary are presented as follows:
• in Table 5 for die-oriented tests
• in Table 6 for SO8N ST Shenzhen package-oriented tests
• in Table 7 for TSSOP8 ST Shenzhen package-oriented tests
• in Table 8 for UFDFPN8 (MLP8) 2 x 3 mm ST Calamba package-oriented tests

Table 5. Die-oriented reliability test plan and result summary (CDIP8 / Engineering
package)(1)
Test short description

Results fail / sample size

Test Sample No.
Method Conditions size / of Duration M95020
lots lots
Lot 1 Lot 2 Lot 3

High temperature operating life after endurance

168 hrs 0/80 0/80 0/80
504 hrs 0/80 0/80 0/80
AEC-Q100- 400K E/W cycles at 150 °C then: Results
80 3 1008 hrs 0/80 0/80
005 HTOL 150 °C, 6 V W41
Results
2008 hrs 0/80 0/80
W47
EDR
Data retention after endurance
168 hrs 0/80 0/80 0/80
504 hrs 0/80 0/80 0/80
AEC-Q100- 400K E/W cycles at 150 °C then: Results
80 3 1008 hrs 0/80 0/80
005 HTSL at 150 °C W41
Results Results
2008 hrs 0/80
W39 W47
Low temperature operating life
168 hrs 0/80 0/80 0/80
504 hrs 0/80 0/80 0/80
LTOL JESD22-
–40 °C, 6 V 80 3 Results
A108 1008 hrs 0/80 0/80
W41
Results Results
2008 hrs 0/80
W39 W47

Rev 1 5/13
13
Reliability test results QRMMY1316

Table 5. Die-oriented reliability test plan and result summary (CDIP8 / Engineering
package)(1) (continued)
Test short description

Results fail / sample size

Test Sample No.
Method Conditions size / of Duration M95020
lots lots
Lot 1 Lot 2 Lot 3

High temperature storage life

168 hrs 0/80 0/80 0/80
504 hrs 0/80 0/80 0/80
HTSL AEC-Q100-
005 Retention bake at 200 °C 80 3 Results Results
1008 hrs 0/80
JESD22-A103 W39 W41
Results Results
2008 hrs 0/80
W46 W47
Program/erase endurance cycling + bake
5 Million E/W cycles at 25 °C
WEB 5 Million
then:
Internal spec. 80 3 cycles / 0/80 (2) 0/80 (2) 0/80 (2)
Retention bake at 200 °C /
48 hrs
48 hours
Electrostatic discharge (human body model)
ESD AEC-Q100-
HBM Pass Pass Pass
002 C = 100 pF, R= 1500 Ω 27 3 N/A
4000 V 4000 V 4000 V
JESD22-A114
Electrostatic discharge (machine model)
ESD AEC-Q100-
MM Pass Pass Pass
003 C = 200 pF, R = 0 Ω 12 3 N/A
400 V 400 V 400 V
JESD22-A115
Latch-up (current injection and overvoltage stress)

LU AEC-Q100- Class II Class II Class II

At maximum operating
004 6 3 N/A - - -
temperature (150 °C)
JESD78B Level A Level A Level A
1. See Table 9: List of terms for a definition of abbreviations.
2. First rejects after 10 million E/W cycles + bake.

6/13 Rev 1
QRMMY1316 Reliability test results

Table 6. Package-oriented reliability test plan and result summary (SO8N / ST Shenzhen)(1)
Test short description

Results fail / sample size

Test Sample No.
M95160
Method Conditions size / of Duration M95640 (2)(3)
lots lots
Lot1 Lot2 Lot3 Lot1

Preconditioning: moisture sensitivity level 1

PC MSL1, peak
JESD22-A113 temperature at 1280 1 N/A 0/1280 0/1280 0/1280 0/1280
J-STD-020D
260 °C, 3 IReflow
Temperature humidity bias
THB
(4) AEC-Q100- 85 °C, 85% RH, 1008 hrs 0/80 0/80 0/80 0/80
80 1
JESD22-A101 bias 5.6 V 2008 hrs 0/80 0/80 0/80 0/80
Temperature cycling
TC
(4) AEC-Q100- 1000
–65 °C / +175 °C 80 1 0/80 0/80 0/80 0/80
JESD22-A104 cycles
Thermal shocks
TMSK
(4) 200
JESD22-A106 –55 °C / +125 °C 80 1 0/80 0/80 0/80 0/80
shocks
Autoclave (pressure pot)
AC
(4) AEC-Q100- 121 °C, 100% RH
80 1 240 hrs 0/80 0/80 0/80 0/80
JESD22-A102 at 2 ATM
High temperature storage life
HTSL
(4) AEC-Q100- Retention bake 1008 hrs 0/80 0/80 0/80 0/80
80 1
JESD22-A103 at 150 °C 2008 hrs 0/80 0/80 0/80 0/80
High temperature operating life
HTOL 1008 hrs 0/80 0/80 0/80 0/80
(4) AEC-Q100-
HTOL 150 °C, 6 V 80 1 Results
JESD22-A108 2008 hrs 0/80 0/80 0/80
W41

ELFR Early life failure rate

(4)
AEC-Q100-008 HTOL 150 °C, 6 V 800 1 48 hrs 0/800 0/800 0/800 0/800
Electrostatic discharge (charge device model)
ESD
CDM AEC-Q100-011 Field induced Pass Pass
18 1 N/A - -
JESD22-C101 charging method >1500 V >1500 V
1. See Table 9: List of terms for a definition of abbreviations.
2. Qualification on 3 lots using the product driver M95640 - Qualification of M95160 benefits of the family approach (1 lot).
3. Larger memory array using the same silicon process technology in the same diffusion fab. Package qualification results of
M95160 are applicable to M95020.
4. THB-, TC-, TMSK-, AC-, HTSL-, HTOL- and ELFR- dedicated parts are first subject to preconditioning flow.

Rev 1 7/13
13
Reliability test results QRMMY1316

Table 7. Package-oriented reliability test plan and result summary (TSSOP8 / ST Shenzhen)(1)
Test short description

Results fail / sample size

Test Sample No.
M95160
Method Conditions size / of Duration M95640 (2)(3)
lots lots
Lot1 Lot2 Lot3 Lot1

Preconditioning: moisture sensitivity level 1

PC MSL1, peak
JESD22-A113
temperature at 1280 1 N/A 0/1280 0/1280 0/1280 0/1280
J-STD-020D
260 °C, 3 IReflow
Temperature humidity bias
THB 1008 hrs 0/80 0/80 0/80 0/80
(4) AEC-Q100- 85 °C, 85% RH,
80 1 Results
JESD22-A101 bias 5.6 V 2008 hrs 0/80 0/80 0/80
W39
Temperature cycling
TC
(4) AEC-Q100- 1000
–65 °C / +175 °C 80 1 0/80 0/80 0/80 0/80
JESD22-A104 cycles
Thermal shocks
TMSK
(4) 200
JESD22-A106 –55 °C / +125 °C 80 1 0/80 0/80 0/80 0/80
shocks
Autoclave (pressure pot)
AC
(4) AEC-Q100- 121 °C, 100% RH
80 1 240 hrs 0/80 0/80 0/80 0/80
JESD22-A102 at 2 ATM
High temperature storage life
HTSL 1008 hrs 0/80 0/80 0/80 0/80
(4) AEC-Q100- Retention bake
80 1 Results
JESD22-A103 at 150 °C 2008 hrs 0/80 0/80 0/80
W39
High temperature operating life
HTOL 1008 hrs 0/80 0/80 0/80 0/80
(4) AEC-Q100-
HTOL 150 °C, 6 V 80 1 Results
JESD22-A108 2008 hrs 0/80 0/80 0/80
W41

ELFR Early life failure rate

8/13 Rev 1
QRMMY1316 Reliability test results

Table 8. Package-oriented reliability test plan and result summary (UFDFPN8 (MLP8) 2 x 3 mm
/ ST Calamba) (1)
Test short description

Results fail / sample size

Test Sample No.
Method Conditions size / of Duration M24C64 (2) M95020
lots lots
Lot1 Lot2 Lot3 Lot1

Preconditioning: moisture sensitivity level 1

PC JESD22-A113 MSL1, peak temperature
1200 3 N/A 0/1200 0/1200 0/1200 -
J-STD-020D at 260 °C, 3 IReflow
Temperature humidity bias

THB 168 hrs 0/80 0/80 0/80 -

(3) AEC-Q100- 85 °C, 85% RH,
80 3 504 hrs 0/80 0/80 0/80 -
JESD22-A101 bias 5.5 V
1008 hrs 0/80 0/80 0/80 -
Temperature cycling
100
0/80 0/80 0/80 -
cycles
500
80 3 0/80 0/80 0/80 -
TC (3) AEC-Q100- cycles
–65 °C / +175 °C
JESD22-A104 1000
0/80 0/80 0/80 -
cycles
200
800 3 0/800 0/800 0/800 -
cycles
Thermal shocks
TMSK
(3) 200
JESD22-A106 –55 °C / +125 °C 80 3 0/80 0/80 0/80 -
shocks
Autoclave (pressure pot)
AC (3) AEC-Q100- 121 °C, 100% RH at 2
80 3 168 hrs 0/80 0/80 0/80 -
JESD22-A102 ATM
High temperature storage life

HTSL 168 hrs 0/80 0/80 0/80 -

(3) AEC-Q100-
Retention bake at 150 °C 80 3 504 hrs 0/80 0/80 0/80 -
JESD22-A103
1008 hrs 0/80 0/80 0/80 -
Electrostatic discharge (charge device model)
ESD
CDM AEC-Q100- Field induced charging Pass Results
18 1 N/A - -
JESD22-C101 method >1500 V W45
1. See Table 9: List of terms for a definition of abbreviations.
2. Larger memory array using the same silicon process technology in the same diffusion fab. Package qualification results of
M24C64 are applicable to M95020.
3. THB-, TC-, TMSK-, AC- and HTSL- dedicated parts are first subject to preconditioning flow.

Rev 1 9/13
13
Applicable and reference documents QRMMY1316

4 Applicable and reference documents

• AEC-Q100: Stress test qualification for integrated circuits

• SOP 2.6.10: General product qualification procedure
• SOP 2.6.11: Program management for product qualification
• SOP 2.6.12: Design criteria for product qualification
• SOP 2.6.14: Reliability requirements for product qualification
• SOP 2.6.19: Process maturity level
• SOP 2.6.2: Process qualification and transfer management
• SOP 2.6.20: New process / New product qualification
• SOP 2.6.7: Product maturity level
• SOP 2.6.9: Package and process maturity management in Back End
• SOP 2.7.5: Automotive products definition and status
• JESD22-A101: Steady state temperature humidity bias life test
• JESD22-A102: Accelerated moisture resistance - unbiased autoclave
• JESD22-A103: High temperature storage life
• JESD22-A104: Temperature cycling
• JESD22-A106: Thermal shock
• JESD22-A108: Temperature, bias, and operating life
• JESD22-A113: Preconditioning of nonhermetic surface mount devices prior to reliability
testing
• JESD22-A114: Electrostatic discharge (ESD) sensitivity testing human body model
(HBM)
• JESD22-A115: Electrostatic discharge (ESD) sensitivity testing machine model (MM)
• JESD78: IC Latch-up test
• J-STD-020D: Moisture/reflow sensitivity classification for nonhermetic solid state
surface mount devices

10/13 Rev 1
QRMMY1316 Glossary

5 Glossary

Table 9. List of terms

Terms Description

EDR NVM endurance, data retention and operational life

HTOL High temperature operating life
LTOL Low temperature operating life
HTB High temperature bake
WEB Program/Erase endurance cycling + bake
ESD HBM Electrostatic discharge (human body model)
ESD MM Electrostatic discharge (machine model)
LU Latch-up
PC Preconditioning (solder simulation)
THB Temperature humidity bias
TC Temperature cycling
TMSK Thermal shocks
AC Autoclave (pressure pot)
HTSL High temperature storage life
ELFR Early life failure rate
ESD CDM Electrostatic discharge (charge device model)

Rev 1 11/13
13
Revision history QRMMY1316

6 Revision history

Table 10. Document revision history

Date Revision Changes

17-Sep-2013 1 Initial release.

12/13 Rev 1
QRMMY1315
Qualification report
New design / M95040-R M95040-W M95040-DF M95040-A125
M95040-A145 using the CMOSF8H technology in the Rousset 8” Fab

Table 1. Product information

General information

M95040-DFDW6TP
M95040-DFMN6TP
M95040-RMN6TP
Commercial product M95040-RDW6TP
M95040-WDW6TP
M95040-WMN6P
M95040-WMN6TP
Product description 4 Kbit serial SPI bus EEPROMs with high-speed clock
Product group MMS
Product division MMY - Memory
Silicon process technology CMOSF8H
Wafer fabrication location RS8F - ST Rousset 8”, France
ST Rousset, France
Electrical Wafer Sort test plant location ST Toa Payoh, Singapore
Subcontractor Ardentec, Singapore

Table 2. Package description

Package description Assembly plant location Final test plant location

ST Shenzhen, China ST Shenzhen, China

SO8N
Subcontractor Amkor, Philippines Subcontractor Amkor, Philippines
ST Shenzhen, China ST Shenzhen, China
TSSOP8
Subcontractor Amkor, Philippines Subcontractor Amkor, Philippines

UFDFPN8 (MLP8) ST Calamba, Philippines ST Calamba, Philippines

2 x 3 mm Subcontractor Amkor, Philippines Subcontractor Amkor, Philippines

Reliability / Qualification assessment: PASS

September 2013 Rev 1 1/13

www.st.com
Reliability evaluation overview QRMMY1315

1 Reliability evaluation overview

1.1 Objectives
This qualification report summarizes the results of the reliability trials that were performed to
qualify the new design M95040-W, M95040-R, M95040-DF, M95040-A125 and M95040-
A145 using the CMOSF8H silicon process technology in the ST Rousset 8” diffusion fab.
The CMOSF8H is a new advanced silicon process technology that is already qualified in the
ST Rousset 8” fab, and in production for M24M02/M95M02, M24M01/M95M01,
M24512/M95512, M24256/M95256, M24128/M95128, M24C64/M95640, M24C32/M95320,
M95160 and M95080 EEPROM general purpose products.
The CMOSF8H technology is also qualified for automotive grade using M95640-A125 and
M95640-A145 as driver products.
This document serves for the qualification of the named product using the named silicon
process technology in the named diffusion fab.
The voltage and temperature ranges covered by this document are:
 2.5 to 5.5 V at –40 to 85 °C for M95040-W devices
 1.8 to 5.5 V at –40 to 85 °C for M95040-R devices
 1.7 to 5.5 V at –40 to 85 °C for M95040-DF devices
 1.8 to 5.5 V at –40 to 125 °C for M95040-A125 devices (automotive grade 1)
 2.5 to 5.5 V at –40 to 145 °C for M95040-A145 devices (automotive grade 0)

1.2 Conclusion
The new design M95040-W, M95040-R, M95040-DF using the CMOSF8H silicon process
technology in the ST Rousset 8” diffusion fab have passed all the reliability requirements
and all products described in Table 1 are qualified.
Refer to Section 3: Reliability test results for details.
The reliability test results apply also to M95040-A125 and M95040-A145 devices which are
forecasted to be fully qualified at completion of 2000 hours stress (Week 47’2013).

2/13 Rev 1
QRMMY1315 Device characteristics

2 Device characteristics

The new design M95040-W, M95040-R, M95040-DF, M95040-A125 and M95040-A145 are
electrically erasable programmable memory (EEPROM) devices based on advanced true
EEPROM technology.
The M95040-W, M95040-R, M95040-DF, M95040-A125 and M95040-A145 are byte-
alterable memories (512 × 8 bits) organized as 32 pages of 16 bytes in which the data
integrity is significantly improved with an embedded Error Correction Code logic.
The devices are accessed by a simple serial SPI compatible interface.
The M95040 devices can operate with a supply range from 1.7 V up to 5.5 V, and are
guaranteed over the -40 °C/+85 °C temperature range.
The M95040-DF offers an additional page, named the identification page (16 bytes). The
identification page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
The M95040-A125 and M95040-A145 are 4-Kbit serial EEPROM Automotive grade devices
operating up to 125 °C and 145 °C respectively. They are compliant with the very high level
of reliability defined by the Automotive standard AEC-Q100 grade 0.
Refer to the product datasheet for more details.

Rev 1 3/13
13
Reliability test results QRMMY1315

3 Reliability test results

This section contains a general description of the reliability evaluation strategy. The named
products are qualified using the standard STMicroelectronics corporate procedures for
quality and reliability.
The CMOSF8H process technology and EEPROM new design core have been qualified for
Automotive products on 3 lots using the driver product M95640 (refer to qualification report
QREE0921).
The M95040 is designed with the same technology and similar architecture as the driver
product M95640/M95160.
The product vehicle used for the die qualification is presented in Table 3.

Table 3. Product vehicles used for die qualification

Silicon process Wafer fabrication Package Assembly plant
Product
technology location description location

M95040 /
CMOSF8H ST Rousset 8” CDIP8 Engineering assy (1)
M95160
1. CDIP8 is a engineering ceramic package used only for die-oriented reliability trials.

The product vehicles used for package qualification are presented in Table 4.

Table 4. Product vehicles used for package qualification

Silicon process Wafer fabrication Assembly plant
Product Package description
technology location location

M95040 / SO8N ST Shenzhen

CMOSF8H ST Rousset 8”
M95160 (1)(2) TSSOP8 ST Shenzhen
SO8N ST Shenzhen
M95640 (2) CMOSF8H ST Rousset 8”
TSSOP8 ST Shenzhen
ST Shenzhen /
SO8N
subcon Amkor
ST Shenzhen /
M24C64 (2) CMOSF8H ST Rousset 8” TSSOP8
subcon Amkor
UFDFPN8 (MLP8) ST Calamba /
2 x 3 mm subcon Amkor
1. Qualification on 3 lots using the product driver M95640 - Qualification of M95160/M95040 benefits of the
family approach (1 lot).
2. Larger memory array using the same silicon process technology in the same diffusion fab. Package
qualification results of M95640/M24C64/M95160 are applicable to M95040.

4/13 Rev 1
QRMMY1315 Reliability test results

3.1 Reliability test plan and result summary

The reliability test plan and the result summary are presented as follows:
 in Table 5 for die-oriented tests
 in Table 6 for SO8N ST Shenzhen package-oriented tests
 in Table 7 for TSSOP8 ST Shenzhen package-oriented tests
 in Table 8 for UFDFPN8 (MLP8) 2 x 3 mm ST Calamba package-oriented tests

Table 5. Die-oriented reliability test plan and result summary (CDIP8 / Engineering
package)(1)
Test short description

Results fail / sample size

Test Sample No.
Method Conditions size / of Duration M95040
lots lots
Lot 1 Lot 2 Lot 3

High temperature operating life after endurance

Rev 1 5/13
13
Reliability test results QRMMY1315

Table 5. Die-oriented reliability test plan and result summary (CDIP8 / Engineering
package)(1) (continued)
Test short description

Results fail / sample size

Test Sample No.
Method Conditions size / of Duration M95040
lots lots
Lot 1 Lot 2 Lot 3

High temperature storage life

168 hrs 0/80 0/80 0/80
504 hrs 0/80 0/80 0/80
HTSL AEC-Q100-
005 Retention bake at 200 °C 80 3 Results Results
1008 hrs 0/80
JESD22-A103 W39 W41
Results Results
2008 hrs 0/80
W46 W47
Program/erase endurance cycling + bake
5 Million E/W cycles at 25 °C
WEB 5 Million
then:
Internal spec. 80 3 cycles / 0/80 (2) 0/80 (2) 0/80 (2)
Retention bake at 200 °C /
48 hrs
48 hours
Electrostatic discharge (human body model)
ESD AEC-Q100-
HBM Pass Pass Pass
002 C = 100 pF, R= 1500  27 3 N/A
4000 V 4000 V 4000 V
JESD22-A114
Electrostatic discharge (machine model)
ESD AEC-Q100-
MM Pass Pass Pass
003 C = 200 pF, R = 0  12 3 N/A
400 V 400 V 400 V
JESD22-A115
Latch-up (current injection and overvoltage stress)

LU AEC-Q100- Class II Class II Class II

6/13 Rev 1
QRMMY1315 Reliability test results

Table 6. Package-oriented reliability test plan and result summary (SO8N / ST Shenzhen)(1)
Test short description

Results fail / sample size

Test Sample No.
M95160
Method Conditions size / of Duration M95640 (2)(3)
lots lots
Lot1 Lot2 Lot3 Lot1

Preconditioning: moisture sensitivity level 1

ELFR Early life failure rate

(4)
AEC-Q100-008 HTOL 150 °C, 6 V 800 1 48 hrs 0/800 0/800 0/800 0/800
Electrostatic discharge (charge device model)
ESD
CDM AEC-Q100-011 Field induced Pass Pass
18 1 N/A - -
JESD22-C101 charging method >1500 V >1500 V
1. See Table 9: List of terms for a definition of abbreviations.
2. Qualification on 3 lots using the product driver M95640 - Qualification of M95160 benefits of the family approach (1 lot).
3. Larger memory array using the same silicon process technology in the same diffusion fab. Package qualification results of
M95160 are applicable to M95040.
4. THB-, TC-, TMSK-, AC-, HTSL-, HTOL- and ELFR- dedicated parts are first subject to preconditioning flow.

Rev 1 7/13
13
Reliability test results QRMMY1315

Table 7. Package-oriented reliability test plan and result summary (TSSOP8 / ST Shenzhen)(1)
Test short description

Results fail / sample size

Test Sample No.
M95160
Method Conditions size / of Duration M95640 (2)(3)
lots lots
Lot1 Lot2 Lot3 Lot1

Preconditioning: moisture sensitivity level 1

ELFR Early life failure rate

(4)
AEC-Q100-008 HTOL 150 °C, 6 V 800 1 48 hrs 0/800 0/800 0/800 0/800
Electrostatic discharge (charge device model)
ESD
CDM AEC-Q100-011 Field induced Pass Pass
18 1 N/A - -
JESD22-C101 charging method >1500 V >1500 V
1. See Table 9: List of terms for a definition of abbreviations.
2. Qualification on 3 lots using the product driver M95640 - Qualification of M95160 benefits of the family approach (1 lot).
3. Larger memory array using the same silicon process technology in the same diffusion fab. Package qualification results of
M95160 are applicable to M95040.
4. THB-, TC-, TMSK-, AC-, HTSL-, HTOL- and ELFR- dedicated parts are first subject to preconditioning flow.

8/13 Rev 1
QRMMY1315 Reliability test results

Table 8. Package-oriented reliability test plan and result summary (UFDFPN8 (MLP8) 2 x 3 mm
/ ST Calamba) (1)
Test short description

Results fail / sample size

Test Sample No.
Method Conditions size / of Duration M24C64 (2) M95040
lots lots
Lot1 Lot2 Lot3 Lot1

Preconditioning: moisture sensitivity level 1

PC JESD22-A113 MSL1, peak temperature
1200 3 N/A 0/1200 0/1200 0/1200 -
J-STD-020D at 260 °C, 3 IReflow
Temperature humidity bias

THB 168 hrs 0/80 0/80 0/80 -

HTSL 168 hrs 0/80 0/80 0/80 -

(3) AEC-Q100-
Retention bake at 150 °C 80 3 504 hrs 0/80 0/80 0/80 -
JESD22-A103
1008 hrs 0/80 0/80 0/80 -
Electrostatic discharge (charge device model)
ESD
CDM AEC-Q100- Field induced charging Pass Results
18 1 N/A - -
JESD22-C101 method >1500 V W45
1. See Table 9: List of terms for a definition of abbreviations.
2. Larger memory array using the same silicon process technology in the same diffusion fab. Package qualification results of
M24C64 are applicable to M95040.
3. THB-, TC-, TMSK-, AC- and HTSL- dedicated parts are first subject to preconditioning flow.

Rev 1 9/13
13
Applicable and reference documents QRMMY1315

4 Applicable and reference documents

 AEC-Q100: Stress test qualification for integrated circuits

 SOP 2.6.10: General product qualification procedure
 SOP 2.6.11: Program management for product qualification
 SOP 2.6.12: Design criteria for product qualification
 SOP 2.6.14: Reliability requirements for product qualification
 SOP 2.6.19: Process maturity level
 SOP 2.6.2: Process qualification and transfer management
 SOP 2.6.20: New process / New product qualification
 SOP 2.6.7: Product maturity level
 SOP 2.6.9: Package and process maturity management in Back End
 SOP 2.7.5: Automotive products definition and status
 JESD22-A101: Steady state temperature humidity bias life test
 JESD22-A102: Accelerated moisture resistance - unbiased autoclave
 JESD22-A103: High temperature storage life
 JESD22-A104: Temperature cycling
 JESD22-A106: Thermal shock
 JESD22-A108: Temperature, bias, and operating life
 JESD22-A113: Preconditioning of nonhermetic surface mount devices prior to reliability
testing
 JESD22-A114: Electrostatic discharge (ESD) sensitivity testing human body model
(HBM)
 JESD22-A115: Electrostatic discharge (ESD) sensitivity testing machine model (MM)
 JESD78: IC Latch-up test
 J-STD-020D: Moisture/reflow sensitivity classification for nonhermetic solid state
surface mount devices

10/13 Rev 1
QRMMY1315 Glossary

5 Glossary

Table 9. List of terms

Terms Description

EDR NVM endurance, data retention and operational life

Rev 1 11/13
13
Revision history QRMMY1315

6 Revision history

Table 10. Document revision history

Date Revision Changes

19-Sep-2013 1 Initial release.

12/13 Rev 1
QRMMY1314
Qualification report
New design / M95080-R M95080-W M95080-DF M95080-A125
M95080-A145 using the CMOSF8H technology in the Rousset 8” Fab

Table 1. Product information

General information

M95080-DFDW6TP
M95080-DFMN6TP
M95080-RMN6TP
Commercial product M95080-RDW6TP
M95080-WDW6TP
M95080-WMN6P
M95080-WMN6TP
Product description 8 Kbit serial SPI bus EEPROMs with high-speed clock
Product group MMS
Product division MMY - Memory
Silicon process technology CMOSF8H
Wafer fabrication location RS8F - ST Rousset 8”, France
ST Rousset, France
Electrical Wafer Sort test plant location ST Toa Payoh, Singapore
Subcontractor Ardentec, Singapore

Table 2. Package description

Package description Assembly plant location Final test plant location

ST Shenzhen, China ST Shenzhen, China

SO8N
Subcontractor Amkor, Philippines Subcontractor Amkor, Philippines
ST Shenzhen, China ST Shenzhen, China
TSSOP8
Subcontractor Amkor, Philippines Subcontractor Amkor, Philippines

UFDFPN8 (MLP8) ST Calamba, Philippines ST Calamba, Philippines

2 x 3 mm Subcontractor Amkor, Philippines Subcontractor Amkor, Philippines

Reliability / Qualification assessment: PASS

September 2013 Rev 1 1/13

www.st.com
Reliability evaluation overview QRMMY1314

1 Reliability evaluation overview

1.1 Objectives
This qualification report summarizes the results of the reliability trials that were performed to
qualify the new design M95080-W, M95080-R, M95080-DF, M95080-A125 and M95080-
A145 using the CMOSF8H silicon process technology in the ST Rousset 8” diffusion fab.
The CMOSF8H is a new advanced silicon process technology that is already qualified in the
ST Rousset 8” fab, and in production for M24M02/M95M02, M24M01/M95M01,
M24512/M95512, M24256/M95256, M24128/M95128, M24C64/M95640, M24C32/M95320
and M95160 EEPROM general purpose products.
The CMOSF8H technology is also qualified for automotive grade using M95640-A125 and
M95640-A145 as driver products.
This document serves for the qualification of the named product using the named silicon
process technology in the named diffusion fab.
The voltage and temperature ranges covered by this document are:
• 2.5 to 5.5 V at –40 to 85 °C for M95080-W devices
• 1.8 to 5.5 V at –40 to 85 °C for M95080-R devices
• 1.7 to 5.5 V at –40 to 85 °C for M95080-DF devices
• 1.8 to 5.5 V at –40 to 125 °C for M95080-A125 devices (automotive grade 1)
• 2.5 to 5.5 V at –40 to 145 °C for M95080-A145 devices (automotive grade 0)

1.2 Conclusion
The new design M95080-W, M95080-R, M95080-DF using the CMOSF8H silicon process
technology in the ST Rousset 8” diffusion fab have passed all the reliability requirements
and all products described in Table 1 are qualified.
Refer to Section 3: Reliability test results for details.
The reliability test results apply also to M95080-A125 and M95080-A145 devices which are
forecasted to be fully qualified at completion of 2000 hours stress (Week 47’2013).

2/13 Rev 1
QRMMY1314 Device characteristics

2 Device characteristics

The new design M95080-W, M95080-R, M95080-DF, M95080-A125 and M95080-A145 are
electrically erasable programmable memory (EEPROM) devices based on advanced true
EEPROM technology.
The M95080-W, M95080-R, M95080-DF, M95080-A125 and M95080-A145 are byte-
alterable memories (1024 × 8 bits) organized as 32 pages of 32 bytes in which the data
integrity is significantly improved with an embedded Error Correction Code logic.
The devices are accessed by a simple serial SPI compatible interface.
The M95080 devices can operate with a supply range from 1.7 V up to 5.5 V, and are
guaranteed over the -40 °C/+85 °C temperature range.
The M95080-DF offers an additional page, named the identification page (32 bytes). The
identification page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
The M95080-A125 and M95080-A145 are 8-Kbit serial EEPROM Automotive grade devices
operating up to 125 °C and 145 °C respectively. They are compliant with the very high level
of reliability defined by the Automotive standard AEC-Q100 grade 0.
Refer to the product datasheet for more details.

Rev 1 3/13
13
Reliability test results QRMMY1314

3 Reliability test results

This section contains a general description of the reliability evaluation strategy. The named
products are qualified using the standard STMicroelectronics corporate procedures for
quality and reliability.
The CMOSF8H process technology and EEPROM new design core have been qualified for
Automotive products on 3 lots using the driver product M95640 (refer to qualification report
QREE0921).
The M95080 is designed with the same technology and similar architecture as the driver
product M95640/M95160.
The product vehicle used for the die qualification is presented in Table 3.

Table 3. Product vehicles used for die qualification

Silicon process Wafer fabrication Package Assembly plant
Product
technology location description location

M95080 /
CMOSF8H ST Rousset 8” CDIP8 Engineering assy (1)
M95160
1. CDIP8 is a engineering ceramic package used only for die-oriented reliability trials.

The product vehicles used for package qualification are presented in Table 4.

Table 4. Product vehicles used for package qualification

Silicon process Wafer fabrication Assembly plant
Product Package description
technology location location

M95080 / SO8N ST Shenzhen

CMOSF8H ST Rousset 8”
M95160 (1)(2) TSSOP8 ST Shenzhen
SO8N ST Shenzhen
M95640 (2) CMOSF8H ST Rousset 8”
TSSOP8 ST Shenzhen
ST Shenzhen /
SO8N
subcon Amkor
ST Shenzhen /
M24C64 (2) CMOSF8H ST Rousset 8” TSSOP8
subcon Amkor
UFDFPN8 (MLP8) ST Calamba /
2 x 3 mm subcon Amkor
1. Qualification on 3 lots using the product driver M95640 - Qualification of M95160/M95080 benefits of the
family approach (1 lot).
2. Larger memory array using the same silicon process technology in the same diffusion fab. Package
qualification results of M95640/M24C64/M95160 are applicable to M95080.

4/13 Rev 1
QRMMY1314 Reliability test results

3.1 Reliability test plan and result summary

Table 5. Die-oriented reliability test plan and result summary (CDIP8 / Engineering
package)(1)
Test short description

Results fail / sample size

Test Sample No.
Method Conditions size / of Duration M95080
lots lots
Lot 1 Lot 2 Lot 3

High temperature operating life after endurance

Rev 1 5/13
13
Reliability test results QRMMY1314

Table 5. Die-oriented reliability test plan and result summary (CDIP8 / Engineering
package)(1) (continued)
Test short description

Results fail / sample size

Test Sample No.
Method Conditions size / of Duration M95080
lots lots
Lot 1 Lot 2 Lot 3

High temperature storage life

LU AEC-Q100- Class II Class II Class II

6/13 Rev 1
QRMMY1314 Reliability test results

Table 6. Package-oriented reliability test plan and result summary (SO8N / ST Shenzhen)(1)
Test short description

Results fail / sample size

Test Sample No.
M95160
Method Conditions size / of Duration M95640 (2)(3)
lots lots
Lot1 Lot2 Lot3 Lot1

Preconditioning: moisture sensitivity level 1

ELFR Early life failure rate

(4)
AEC-Q100-008 HTOL 150 °C, 6 V 800 1 48 hrs 0/800 0/800 0/800 0/800
Electrostatic discharge (charge device model)
ESD
CDM AEC-Q100-011 Field induced Pass Pass
18 1 N/A - -
JESD22-C101 charging method >1500 V >1500 V
1. See Table 9: List of terms for a definition of abbreviations.
2. Qualification on 3 lots using the product driver M95640 - Qualification of M95160 benefits of the family approach (1 lot).
3. Larger memory array using the same silicon process technology in the same diffusion fab. Package qualification results of
M95160 are applicable to M95080.
4. THB-, TC-, TMSK-, AC-, HTSL-, HTOL- and ELFR- dedicated parts are first subject to preconditioning flow.

Rev 1 7/13
13
Reliability test results QRMMY1314

Table 7. Package-oriented reliability test plan and result summary (TSSOP8 / ST Shenzhen)(1)
Test short description

Results fail / sample size

Test Sample No.
M95160
Method Conditions size / of Duration M95640 (2)(3)
lots lots
Lot1 Lot2 Lot3 Lot1

Preconditioning: moisture sensitivity level 1

ELFR Early life failure rate

(4)
AEC-Q100-008 HTOL 150 °C, 6 V 800 1 48 hrs 0/800 0/800 0/800 0/800
Electrostatic discharge (charge device model)
ESD
CDM AEC-Q100-011 Field induced Pass Pass
18 1 N/A - -
JESD22-C101 charging method >1500 V >1500 V
1. See Table 9: List of terms for a definition of abbreviations.
2. Qualification on 3 lots using the product driver M95640 - Qualification of M95160 benefits of the family approach (1 lot).
3. Larger memory array using the same silicon process technology in the same diffusion fab. Package qualification results of
M95160 are applicable to M95080.
4. THB-, TC-, TMSK-, AC-, HTSL-, HTOL- and ELFR- dedicated parts are first subject to preconditioning flow.

8/13 Rev 1
QRMMY1314 Reliability test results

Table 8. Package-oriented reliability test plan and result summary (UFDFPN8 (MLP8) 2 x 3 mm
/ ST Calamba) (1)
Test short description

Results fail / sample size

Test Sample No.
Method Conditions size / of Duration M24C64 (2) M95080
lots lots
Lot1 Lot2 Lot3 Lot1

Preconditioning: moisture sensitivity level 1

PC JESD22-A113 MSL1, peak temperature
1200 3 N/A 0/1200 0/1200 0/1200 -
J-STD-020D at 260 °C, 3 IReflow
Temperature humidity bias

THB 168 hrs 0/80 0/80 0/80 -

HTSL 168 hrs 0/80 0/80 0/80 -

(3) AEC-Q100-
Retention bake at 150 °C 80 3 504 hrs 0/80 0/80 0/80 -
JESD22-A103
1008 hrs 0/80 0/80 0/80 -
Electrostatic discharge (charge device model)
ESD
CDM AEC-Q100- Field induced charging Pass Results
18 1 N/A - -
JESD22-C101 method >1500 V W45
1. See Table 9: List of terms for a definition of abbreviations.
2. Larger memory array using the same silicon process technology in the same diffusion fab. Package qualification results of
M24C64 are applicable to M95080.
3. THB-, TC-, TMSK-, AC- and HTSL- dedicated parts are first subject to preconditioning flow.

Rev 1 9/13
13
Applicable and reference documents QRMMY1314

4 Applicable and reference documents

• AEC-Q100: Stress test qualification for integrated circuits

10/13 Rev 1
QRMMY1314 Glossary

5 Glossary

Table 9. List of terms

Terms Description

EDR NVM endurance, data retention and operational life

Rev 1 11/13
13
Revision history QRMMY1314

6 Revision history

Table 10. Document revision history

Date Revision Changes

17-Sep-2013 1 Initial release.

12/13 Rev 1
QRMMY1205
Qualification report
New design / M95160-R M95160-W M95160-DF M95160-A125
M95160-A145 using the CMOSF8H technology in the Rousset 8” Fab

Table 1. Product information

General information

M95160-DFDW6TP
M95160-DFMN6TP
M95160-RMN6TP
Commercial product M95160-RDW6TP
M95160-WDW6TP
M95160-WMN6P
M95160-WMN6TP
Product description 16 Kbit serial SPI bus EEPROMs with high-speed clock
Product group MMS
Product division MMY - Memory
Silicon process technology CMOSF8H
Wafer fabrication location RS8F - ST Rousset 8”, France
ST Rousset, France
Electrical Wafer Sort test plant location ST Toa Payoh, Singapore
Subcontractor Ardentec, Singapore

Table 2. Package description

Package description Assembly plant location Final test plant location

ST Shenzhen, China ST Shenzhen, China

SO8N
Subcontractor Amkor, Philippines Subcontractor Amkor, Philippines
ST Shenzhen, China ST Shenzhen, China
TSSOP8
Subcontractor Amkor, Philippines Subcontractor Amkor, Philippines

UFDFPN8 (MLP8) ST Calamba, Philippines ST Calamba, Philippines

2 x 3 mm Subcontractor Amkor, Philippines Subcontractor Amkor, Philippines

Reliability / Qualification assessment: PASS

September 2013 Rev 1 1/13

www.st.com
Reliability evaluation overview QRMMY1205

1 Reliability evaluation overview

1.1 Objectives
This qualification report summarizes the results of the reliability trials that were performed to
qualify the new design M95160-W, M95160-R, M95160-DF, M95160-A125 and M95160-
A145 using the CMOSF8H silicon process technology in the ST Rousset 8” diffusion fab.
The CMOSF8H is a new advanced silicon process technology that is already qualified in the
ST Rousset 8” fab, and in production for M24M02/M95M02, M24M01/M95M01,
M24512/M95512, M24256/M95256, M24128/M95128, M24C64/M95640 and
M24C32/M95320 EEPROM general purpose products.
The CMOSF8H technology is also qualified for automotive grade using M95640-A125 and
M95640-A145 as driver products.
This document serves for the qualification of the named product using the named silicon
process technology in the named diffusion fab.
The voltage and temperature ranges covered by this document are:
• 2.5 to 5.5 V at –40 to 85 °C for M95160-W devices
• 1.8 to 5.5 V at –40 to 85 °C for M95160-R devices
• 1.7 to 5.5 V at –40 to 85 °C for M95160-DF devices
• 1.8 to 5.5 V at –40 to 125 °C for M95160-A125 devices (automotive grade 1)
• 2.5 to 5.5 V at –40 to 145 °C for M95160-A145 devices (automotive grade 0)

1.2 Conclusion
The new design M95160-W, M95160-R, M95160-DF using the CMOSF8H silicon process
technology in the ST Rousset 8” diffusion fab have passed all the reliability requirements
and all products described in Table 1 are qualified.
Refer to Section 3: Reliability test results for details.
The reliability test results apply also to M95160-A125 and M95160-A145 devices which are
forecasted to be fully qualified at completion of 2000 hours stress (Week 47’2013).

2/13 Rev 1
QRMMY1205 Device characteristics

2 Device characteristics

The new design M95160-W, M95160-R, M95160-DF, M95160-A125 and M95160-A145 are
electrically erasable programmable memory (EEPROM) devices based on advanced true
EEPROM technology.
The M95160-W, M95160-R, M95160-DF, M95160-A125 and M95160-A145 are byte-
alterable memories (2048 × 8 bits) organized as 64 pages of 32 bytes in which the data
integrity is significantly improved with an embedded Error Correction Code logic.
The devices are accessed by a simple serial SPI compatible interface.
The M95160 devices can operate with a supply range from 1.7 V up to 5.5 V, and are
guaranteed over the -40 °C/+85 °C temperature range.
The M95160-DF offers an additional page, named the identification page (32 bytes). The
identification page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
The M95160-A125 and M95160-A145 are 16-Kbit serial EEPROM Automotive grade
devices operating up to 125 °C and 145 °C respectively. They are compliant with the very
high level of reliability defined by the Automotive standard AEC-Q100 grade 0.
Refer to the product datasheet for more details.

Rev 1 3/13
13
Reliability test results QRMMY1205

3 Reliability test results

This section contains a general description of the reliability evaluation strategy. The named
products are qualified using the standard STMicroelectronics corporate procedures for
quality and reliability.
The CMOSF8H process technology and EEPROM new design core have been qualified for
Automotive products on 3 lots using the driver product M95640 (refer to qualification report
QREE0921).
The M95160, driver product for SPI low densities EEPROM, is designed with the same
technology and similar architecture as the driver product M95640.
The product vehicle used for the die qualification is presented in Table 3.

Table 3. Product vehicles used for die qualification

Silicon process Wafer fabrication Package Assembly plant
Product
technology location description location

M95160 CMOSF8H ST Rousset 8” CDIP8 Engineering assy (1)

1. CDIP8 is a engineering ceramic package used only for die-oriented reliability trials.

The product vehicles used for package qualification are presented in Table 4.

Table 4. Product vehicles used for package qualification

Silicon process Wafer fabrication Assembly plant
Product Package description
technology location location

SO8N ST Shenzhen
M95160 (1) CMOSF8H ST Rousset 8”
TSSOP8 ST Shenzhen
SO8N ST Shenzhen
M95640 (2) CMOSF8H ST Rousset 8”
TSSOP8 ST Shenzhen
ST Shenzhen /
SO8N
subcon Amkor
ST Shenzhen /
M24C64 (2) CMOSF8H ST Rousset 8” TSSOP8
subcon Amkor
UFDFPN8 (MLP8) ST Calamba /
2 x 3 mm subcon Amkor
1. Qualification on 3 lots using the driver product M95640 - Qualification of M95160 benefits of the family
approach (1 lot).
2. Larger memory array using the same silicon process technology in the same diffusion fab. Package
qualification results of M95640/M24C64 are applicable to M95160.

4/13 Rev 1
QRMMY1205 Reliability test results

3.1 Reliability test plan and result summary

Table 5. Die-oriented reliability test plan and result summary (CDIP8 / Engineering
package)(1)
Test short description

Results fail / sample size

Test Sample No.
Method Conditions size / of Duration M95160
lots lots
Lot 1 Lot 2 Lot 3

High temperature operating life after endurance

Rev 1 5/13
13
Reliability test results QRMMY1205

Table 5. Die-oriented reliability test plan and result summary (CDIP8 / Engineering
package)(1) (continued)
Test short description

Results fail / sample size

Test Sample No.
Method Conditions size / of Duration M95160
lots lots
Lot 1 Lot 2 Lot 3

High temperature storage life

LU AEC-Q100- Class II Class II Class II

6/13 Rev 1
QRMMY1205 Reliability test results

Table 6. Package-oriented reliability test plan and result summary (SO8N / ST Shenzhen)(1)
Test short description

Results fail / sample size

Test Sample No.
M95160
Method Conditions size / of Duration M95640 (2)
lots lots
Lot1 Lot2 Lot3 Lot1

Preconditioning: moisture sensitivity level 1

PC MSL1, peak
JESD22-A113 temperature at 1280 1 N/A 0/1280 0/1280 0/1280 0/1280
J-STD-020D
260 °C, 3 IReflow
Temperature humidity bias
THB
(3) AEC-Q100- 85 °C, 85% RH, 1008 hrs 0/80 0/80 0/80 0/80
80 1
JESD22-A101 bias 5.6 V 2008 hrs 0/80 0/80 0/80 0/80
Temperature cycling
TC
(3) AEC-Q100- 1000
–65 °C / +175 °C 80 1 0/80 0/80 0/80 0/80
JESD22-A104 cycles
Thermal shocks
TMSK
(3) 200
JESD22-A106 –55 °C / +125 °C 80 1 0/80 0/80 0/80 0/80
shocks
Autoclave (pressure pot)
AC
(3) AEC-Q100- 121 °C, 100% RH
80 1 240 hrs 0/80 0/80 0/80 0/80
JESD22-A102 at 2 ATM
High temperature storage life
HTSL
(3) AEC-Q100- Retention bake 1008 hrs 0/80 0/80 0/80 0/80
80 1
JESD22-A103 at 150 °C 2008 hrs 0/80 0/80 0/80 0/80
High temperature operating life
HTOL 1008 hrs 0/80 0/80 0/80 0/80
(3) AEC-Q100-
HTOL 150 °C, 6 V 80 1 Results
JESD22-A108 2008 hrs 0/80 0/80 0/80
W41

ELFR Early life failure rate

(3)
AEC-Q100-008 HTOL 150 °C, 6 V 800 1 48 hrs 0/800 0/800 0/800 0/800
Electrostatic discharge (charge device model)
ESD
CDM AEC-Q100-011 Field induced Pass Pass
18 1 N/A - -
JESD22-C101 charging method >1500 V >1500 V
1. See Table 9: List of terms for a definition of abbreviations.
2. Qualification on 3 lots using the driver product M95640 - Qualification of M95160 benefits of the family approach (1 lot).
3. THB-, TC-, TMSK-, AC-, HTSL-, HTOL- and ELFR- dedicated parts are first subject to preconditioning flow.

Rev 1 7/13
13
Reliability test results QRMMY1205

Table 7. Package-oriented reliability test plan and result summary (TSSOP8 / ST Shenzhen)(1)
Test short description

Results fail / sample size

Test Sample No.
M95160
Method Conditions size / of Duration M95640 (2)
lots lots
Lot1 Lot2 Lot3 Lot1

Preconditioning: moisture sensitivity level 1

PC MSL1, peak
JESD22-A113
temperature at 1280 1 N/A 0/1280 0/1280 0/1280 0/1280
J-STD-020D
260 °C, 3 IReflow
Temperature humidity bias
THB 1008 hrs 0/80 0/80 0/80 0/80
(3) AEC-Q100- 85 °C, 85% RH,
80 1 Results
JESD22-A101 bias 5.6 V 2008 hrs 0/80 0/80 0/80
W39
Temperature cycling
TC
(3) AEC-Q100- 1000
–65 °C / +175 °C 80 1 0/80 0/80 0/80 0/80
JESD22-A104 cycles
Thermal shocks
TMSK
(3) 200
JESD22-A106 –55 °C / +125 °C 80 1 0/80 0/80 0/80 0/80
shocks
Autoclave (pressure pot)
AC
(3) AEC-Q100- 121 °C, 100% RH
80 1 240 hrs 0/80 0/80 0/80 0/80
JESD22-A102 at 2 ATM
High temperature storage life
HTSL 1008 hrs 0/80 0/80 0/80 0/80
(3) AEC-Q100- Retention bake
80 1 Results
JESD22-A103 at 150 °C 2008 hrs 0/80 0/80 0/80
W39
High temperature operating life
HTOL 1008 hrs 0/80 0/80 0/80 0/80
(3) AEC-Q100-
HTOL 150 °C, 6 V 80 1 Results
JESD22-A108 2008 hrs 0/80 0/80 0/80
W41

ELFR Early life failure rate

8/13 Rev 1
QRMMY1205 Reliability test results

Table 8. Package-oriented reliability test plan and result summary (UFDFPN8 (MLP8) 2 x 3 mm
/ ST Calamba) (1)
Test short description

Results fail / sample size

Test Sample No.
Method Conditions size / of Duration M24C64 (2) M95160
lots lots
Lot1 Lot2 Lot3 Lot1

Preconditioning: moisture sensitivity level 1

PC JESD22-A113 MSL1, peak temperature
1200 3 N/A 0/1200 0/1200 0/1200 -
J-STD-020D at 260 °C, 3 IReflow
Temperature humidity bias

THB 168 hrs 0/80 0/80 0/80 -

HTSL 168 hrs 0/80 0/80 0/80 -

(3) AEC-Q100-
Retention bake at 150 °C 80 3 504 hrs 0/80 0/80 0/80 -
JESD22-A103
1008 hrs 0/80 0/80 0/80 -
Electrostatic discharge (charge device model)
ESD
CDM AEC-Q100- Field induced charging Pass Results
18 1 N/A - -
JESD22-C101 method >1500 V W45
1. See Table 9: List of terms for a definition of abbreviations.
2. Larger memory array using the same silicon process technology in the same diffusion fab. Package qualification results of
M24C64 are applicable to M95160.
3. THB-, TC-, TMSK-, AC- and HTSL- dedicated parts are first subject to preconditioning flow.

Rev 1 9/13
13
Applicable and reference documents QRMMY1205

4 Applicable and reference documents

• AEC-Q100: Stress test qualification for integrated circuits

10/13 Rev 1
QRMMY1205 Glossary

5 Glossary

Table 9. List of terms

Terms Description

EDR NVM endurance, data retention and operational life

Rev 1 11/13
13
Revision history QRMMY1205

6 Revision history

Table 10. Document revision history

Date Revision Changes

13-Sep-2013 1 Initial release.

12/13 Rev 1
QRMMY1205

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

© 2013 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com

Rev 1 13/13
13
M95160 M95160-W
M95160-R M95160-F
16-Kbit serial SPI bus EEPROM
with high-speed clock
Datasheet − production data

Features
■ Compatible with the Serial Peripheral Interface
(SPI) bus
■ Memory array
– 16 Kb (2 Kbytes) of EEPROM SO8 (MN)
– Page size: 32 bytes 150 mil width

■ Write
– Byte Write within 5 ms
– Page Write within 5 ms
■ Write Protect: quarter, half or whole memory
array
TSSOP8 (DW)
■ High-speed clock: 10 MHz 169 mil width
■ Single supply voltage:
– 4.5 V to 5.5 V for M95160
– 2.5 V to 5.5 V for M95160-W
– 1.8 V to 5.5 V for M95160-R
– 1.7 V to 5.5 V for M95160-F
■ Operating temperature range: from -40°C up to UFDFPN8 (MC)
+85°C 2 x 3 mm (MLP)
■ Enhanced ESD protection
■ More than 1 million Write cycles
■ More than 40-year data retention WLCSP (CS)
■ Packages (preliminary data)
– RoHS compliant and halogen-free
(ECOPACK®)

January 2013 Doc ID 022580 Rev 3 1/46

This is information on a product in full production. www.st.com 1
Contents M95160 M95160-W M95160-R M95160-F

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Contents

6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Doc ID 022580 Rev 3 3/46

List of tables M95160 M95160-W M95160-R M95160-F

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Operating conditions (M95160, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. Operating conditions (M95160-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Operating conditions (M95160-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Operating conditions (M95160-F, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15. DC characteristics (M95160, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 16. DC characteristics (M95160-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 17. DC characteristics (M95160-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. DC characteristics (M95160-F, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. AC characteristics (M95160-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 20. AC characteristics (M95160-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21. AC characteristics (M95160-F, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 22. AC characteristics (M95160, device grade 6)
End of life products: these values apply only to M95160-MN6TP/S devices . . . . . . . . . . . 36
Table 23. AC characteristics (M95160-W, device grade 6)
End of life products: these values apply only to M95160-WMN6TP/S
and M95160-WDW6TP/S devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 24. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 40
Table 25. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 41
Table 26. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 27. WLCSP-R – 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package mechanical
data (preliminary data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 28. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 29. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . . 7
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 17. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 18. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 19. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 40
Figure 20. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 21. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline. . . . . . . 42
Figure 22. WLCSP-R – 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package outline . . . . . . . . . . . . . . 43

Doc ID 022580 Rev 3 5/46

Description M95160 M95160-W M95160-R M95160-F

1 Description

The M95160 devices are Electrically Erasable PROgrammable Memories (EEPROMs)

organized as 2048 x 8 bits, accessed through the SPI bus.
The M95160 can operate with a supply voltage from 4.5 V to 5.5 V, the M95160-W can
operate with a supply voltage from 2.5 V to 5.5 V, the M95160-R can operate with a supply
voltage from 1.8 V to 5.5 V, and the M95160-F can operate with a supply voltage from 1.7 V
to 5.5 V, over an ambient temperature range of -40 °C / +85 °C.

Figure 1. Logic diagram

VCC

D Q

S M95xxx

HOLD

VSS
AI01789C

The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is
selected when Chip Select (S) is driven low. Communications with the device can be
interrupted when the HOLD is driven low.

Table 1. Signal names

Signal name Function Direction

C Serial Clock Input

D Serial Data Input Input
Q Serial Data Output Output
S Chip Select Input
W Write Protect Input
HOLD Hold Input
VCC Supply voltage
VSS Ground

6/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Description

Figure 2. 8-pin package connections (top view)

M95xxx

S 1 8 VCC
Q 2 7 HOLD
W 3 6 C
VSS 4 5 D
AI01790D

1. See Section 10: Package mechanical data section for package dimensions, and how to identify pin 1.

Figure 3. WLCSP connections (top view, marking side, with balls on the underside)

Q VSS W

S D

HOLD VCC C

Orientation reference
ai15166

Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by
STMicroelectronics must never be exposed to UV light.

Doc ID 022580 Rev 3 7/46

Memory organization M95160 M95160-W M95160-R M95160-F

2 Memory organization

The memory is organized as shown in the following figure.

Figure 4. Block diagram

HOLD
High voltage
W Control logic generator
S

D
I/O shift register
Q

Address register Data

and counter register

Status
Register Size of the
read-only
EEPROM
area
Y decoder

1 page

X decoder

AI01272d

8/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Signal description

3 Signal description

During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held high or low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are
described next.

3.1 Serial Data Output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).

3.2 Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).

3.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) change from the falling edge of Serial Clock (C).

3.4 Chip Select (S)

When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. The device is in the Standby Power mode, unless an internal Write cycle is in
progress. Driving Chip Select (S) low selects the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.

3.5 Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.

Doc ID 022580 Rev 3 9/46

Signal description M95160 M95160-W M95160-R M95160-F

3.6 Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.

3.7 VCC supply voltage

VCC is the supply voltage.

3.8 VSS ground

VSS is the reference for all signals, including the VCC supply voltage.

10/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Connecting to the SPI bus

4 Connecting to the SPI bus

Figure 5. Bus master and memory devices on the SPI bus

VSS

VCC

SDO
SPI Interface with
SDI
(CPOL, CPHA) =
(0, 0) or (1, 1) SCK

C Q D VCC C Q D VCC C Q D VCC

SPI Bus Master VSS VSS VSS

R SPI Memory R SPI Memory R SPI Memory

Device Device Device
CS3 CS2 CS1

S W HOLD S W HOLD S W HOLD

AI12836b

1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 5 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 5) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the
tSHCH requirement is met. The typical value of R is 100 kΩ..

Doc ID 022580 Rev 3 11/46

Connecting to the SPI bus M95160 M95160-W M95160-R M95160-F

4.1 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 6, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)
● C remains at 1 for (CPOL=1, CPHA=1)

Figure 6. SPI modes supported

CPOL CPHA

0 0 C

1 1 C

D MSB

Q MSB

AI01438B

12/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Operating features

5 Operating features

5.1 Supply voltage (VCC)

5.1.1 Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 9: DC and AC parameters). This voltage must remain stable and valid until the
end of the transmission of the instruction and, for a Write instruction, until the completion of
the internal write cycle (tW). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10 nF to 100 nF) close to the VCC/VSS device pins.

5.1.2 Device reset

In order to prevent erroneous instruction decoding and inadvertent Write operations during
power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not
respond to any instruction until VCC reaches the POR threshold voltage. This threshold is
lower than the minimum VCC operating voltage (see Operating conditions in Section 9: DC
and AC parameters).
At power-up, when VCC passes over the POR threshold, the device is reset and is in the
following state:
● in Standby Power mode,
● deselected,
● Status Register values:
– The Write Enable Latch (WEL) bit is reset to 0.
– The Write In Progress (WIP) bit is reset to 0.
– The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until VCC reaches a valid and
stable level within the specified [VCC(min), VCC(max)] range, as defined under Operating
conditions in Section 9: DC and AC parameters.

5.1.3 Power-up conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 5).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.

Doc ID 022580 Rev 3 13/46

Operating features M95160 M95160-W M95160-R M95160-F

5.1.4 Power-down
During power-down (continuous decrease of the VCC supply voltage below the minimum
VCC operating voltage defined under Operating conditions in Section 9: DC and AC
parameters), the device must be:
● deselected (Chip Select S should be allowed to follow the voltage applied on VCC),
● in Standby Power mode (there should not be any internal write cycle in progress).

5.2 Active Power and Standby Power modes

When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes ICC.
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to ICC1, as specified in DC characteristics (see Section 9: DC and AC parameters).

5.3 Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial
Data Input (D) and the Serial Clock (C) are Don’t Care.
Normally, the device is kept selected for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if required to reset any processes that had
been in progress.(a)(b)

Figure 7. Hold condition activation

HOLD

Hold Hold
condition condition

ai02029E

The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 7).

a. This resets the internal logic, except the WEL and WIP bits of the Status Register.
b. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.

14/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Operating features

The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)
is already low.
Figure 7 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.

5.4 Status Register

The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.

5.5 Data protection and protocol control

The device features the following data protection mechanisms:
● Before accepting the execution of the Write and Write Status Register instructions, the
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight.
● All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit.
● The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of
the memory as read-only.
● The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points should be noted in the previous sentence:
● The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
● The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.

Table 2. Write-protected block size

Status Register bits
Protected block Protected array addresses
BP1 BP0

0 0 none none
0 1 Upper quarter 0600h - 07FFh
1 0 Upper half 0400h - 07FFh
1 1 Whole memory 0000h - 07FFh

Doc ID 022580 Rev 3 15/46

Instructions M95160 M95160-W M95160-R M95160-F

6 Instructions

Each instruction starts with a single-byte code, as summarized in Table 3.

If an invalid instruction is sent (one not contained in Table 3), the device automatically
deselects itself.

Table 3. Instruction set

Instruction Description Instruction format

WREN Write Enable 0000 0110

WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010

Table 4. Address range bits

Address significant bits A10-A0(1)
1. Upper MSBs are Don’t Care.

16/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Instructions

6.1 Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.

Figure 8. Write Enable (WREN) sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance
Q
AI02281E

6.2 Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
● Power-up
● WRDI instruction execution
● WRSR instruction completion
● WRITE instruction completion.

Doc ID 022580 Rev 3 17/46

Instructions M95160 M95160-W M95160-R M95160-F

Figure 9. Write Disable (WRDI) sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance
Q
AI03750D

6.3 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 10.

Figure 10. Read Status Register (RDSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

Status Register Out Status Register Out

High Impedance
Q 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

AI02031E

The status and control bits of the Status Register are as follows:

6.3.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.

18/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Instructions

6.3.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
● Power-up
● Write Disable (WRDI) instruction completion
● Write Status Register (WRSR) instruction completion
● Write (WRITE) instruction completion

6.3.3 BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in Table 2) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.

6.3.4 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.

Table 5. Status Register format

b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP

Status Register Write Protect

Block Protect bits
Write Enable Latch bit
Write In Progress bit

Doc ID 022580 Rev 3 19/46

Instructions M95160 M95160-W M95160-R M95160-F

6.4 Write Status Register (WRSR)

The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 11.

Figure 11. Write Status Register (WRSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction Status
Register In

D 7 6 5 4 3 2 1 0

High Impedance MSB

Q
AI02282D

Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed Write cycle that takes tW to complete (as specified in AC tables under Section 9: DC
and AC parameters).
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle tW, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
also reset at the end of the Write cycle tW.
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
● The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in Table 2.
● The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in Table 6. When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the tW Write cycle.
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.

20/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Instructions

Table 6. Protection modes

Memory content
W SRWD Write protection of the
Mode
signal bit Status Register
Protected area(1) Unprotected area(1)

1 0 Status Register is
writable (if the WREN
0 0
Software- instruction has set the
Ready to accept
protected WEL bit). Write-protected
Write instructions
(SPM) The values in the BP1
1 1
and BP0 bits can be
changed.
Status Register is
Hardware write-
Hardware-
protected. Ready to accept
0 1 protected Write-protected
The values in the BP1 Write instructions
(HPM)
and BP0 bits cannot be
changed.
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2.

The protection features of the device are summarized in Table 6.

When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W) input pin:
● If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction).
● If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
● either setting the SRWD bit after driving the Write Protect (W) input pin low,
● or driving the Write Protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.

Doc ID 022580 Rev 3 21/46

Instructions M95160 M95160-W M95160-R M95160-F

6.5 Read from Memory Array (READ)

As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).

Figure 12. Read from Memory Array (READ) sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

Instruction 16-Bit Address

D 15 14 13 3 2 1 0
MSB
Data Out 1 Data Out 2
High Impedance
Q 7 6 5 4 3 2 1 0 7
MSB

AI01793D

1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

6.6 Write to Memory Array (WRITE)

As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period tW (as specified in AC characteristics in Section 9: DC and AC parameters), at the
end of which the Write in Progress (WIP) bit is reset to 0.

22/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Instructions

Figure 13. Byte Write (WRITE) sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

Instruction 16-Bit Address Data Byte

D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

High Impedance
Q

AI01795D

1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
In the case of Figure 13, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in Figure 14, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If more bytes are sent than will fit up to the end of the page, a
condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size
are overwritten from location 0 of the same page.
The instruction is not accepted, and is not executed, under the following conditions:
● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
● if a Write cycle is already in progress,
● if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
● if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Note: The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.

Doc ID 022580 Rev 3 23/46

Instructions M95160 M95160-W M95160-R M95160-F

Figure 14. Page Write (WRITE) sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

Instruction 16-Bit Address Data Byte 1

D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Data Byte 2 Data Byte 3 Data Byte N

D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0

AI01796D

1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.

24/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Power-up and delivery state

7 Power-up and delivery state

7.1 Power-up state

After power-up, the device is in the following state:
● Standby power mode,
● deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started),
● not in the Hold condition,
● the Write Enable Latch (WEL) is reset to 0,
● Write In Progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).

7.2 Initial delivery state

The device is delivered with the memory array bits and identification page bits set to all 1s
(each byte = FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and
BP0) bits are initialized to 0.

Doc ID 022580 Rev 3 25/46

Maximum rating M95160 M95160-W M95160-R M95160-F

8 Maximum rating

Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Table 7. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

Ambient operating temperature –40 130 °C

TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering See note (1) °C
VO Output voltage –0.50 VCC+0.6 V
VI Input voltage –0.50 6.5 V
VCC Supply voltage –0.50 6.5 V
IOL DC output current (Q = 0) 5 mA
IOH DC output current (Q = 1) 5 mA
VESD Electrostatic discharge voltage (human body model)(2) 4000 V
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), with the ST ECOPACK®
7191395 specification, and with the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-
Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).

26/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F DC and AC parameters

9 DC and AC parameters

This section summarizes the operating conditions and the DC/AC characteristics of the
device.

Table 8. Operating conditions (M95160, device grade 6)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 4.5 5.5 V

TA Ambient operating temperature –40 85 °C

Table 9. Operating conditions (M95160-W, device grade 6)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 2.5 5.5 V

TA Ambient operating temperature –40 85 °C

Table 10. Operating conditions (M95160-R, device grade 6)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 1.8 5.5 V

TA Ambient operating temperature –40 85 °C

Table 11. Operating conditions (M95160-F, device grade 6)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 1.7 5.5 V

TA Ambient operating temperature –40 85 °C

Table 12. AC measurement conditions

Symbol Parameter Min. Max. Unit

CL Load capacitance 30 pF
Input rise and fall times 50 ns
Input pulse voltages 0.2 VCC to 0.8 VCC V
Input and output timing reference voltages 0.3 VCC to 0.7 VCC V

Doc ID 022580 Rev 3 27/46

DC and AC parameters M95160 M95160-W M95160-R M95160-F

Figure 15. AC measurement I/O waveform

)NPUT VOLTAGE LEVELS )NPUT AND OUTPUT
TIMING REFERENCE LEVELS
6##
6##

6##
6##

!)#

28/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F DC and AC parameters

Table 13. Capacitance

Symbol Parameter Test conditions(1) Min. Max. Unit

COUT Output capacitance (Q) VOUT = 0 V 8 pF

Input capacitance (D) VIN = 0 V 8 pF
CIN
Input capacitance (other pins) VIN = 0 V 6 pF
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.

Table 14. Memory cell data retention

Parameter Test conditions Min. Unit

Data retention(1) TA = 55 °C 40 Year

Cycling TA = 25 °C 1 million Cycle
1. The data retention behavior is checked in production. The 40-year limit is defined from characterization and
qualification results.

Table 15. DC characteristics (M95160, device grade 6)

Test conditions in addition to
Symbol Parameter those defined in Table 8 and Min. Max. Unit
Table 12

ILI Input leakage current VIN = VSS or VCC ±2 µA

ILO Output leakage current S = VCC, VOUT = VSS or VCC ±2 µA
C = 0.1 VCC/0.9 VCC at 10 MHz,
ICC Supply current (Read) 5 mA
VCC = 5 V, Q = open
Supply current S = VCC, VCC = 5 V,
ICC1 2 µA
(Standby) VIN = VSS or VCC
VIL Input low voltage –0.45 0.3 VCC V
VIH Input high voltage 0.7 VCC VCC+1 V
VOL(1) Output low voltage IOL = 2 mA, VCC = 5 V 0.4 V
VOH (1)
Output high voltage IOH = –2 mA, VCC = 5 V 0.8 VCC V
Internal reset threshold
VRES(2) 2.5 3.5 V
voltage
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Characterized only, not tested in production.

Doc ID 022580 Rev 3 29/46

DC and AC parameters M95160 M95160-W M95160-R M95160-F

Table 16. DC characteristics (M95160-W, device grade 6)

Test conditions in addition to those
Symbol Parameter Min. Max. Unit
defined in Table 9 and Table 12

Input leakage
ILI VIN = VSS or VCC ±2 µA
current
Output leakage
ILO S = VCC, VOUT = VSS or VCC ±2 µA
current
C = 0.1 VCC/0.9 VCC at 5 MHz,
2
Supply current VCC = 2.5 V, Q = open
ICC mA
(Read) C = 0.1 VCC/0.9 VCC at 10 MHz,
5
VCC = 2.5 V, Q = open
Supply current
S = VCC, 2.5 V <VCC < 5.5 V
ICC1 (Standby Power 2 µA
VIN = VSS or VCC
mode)
VIL Input low voltage –0.45 0.3 VCC V
VIH Input high voltage 0.7 VCC VCC+1 V
VOL Output low voltage IOL = 1.5 mA, VCC = 2.5 V 0.4 V
VOH Output high voltage IOH = –0.4 mA, VCC = 2.5 V 0.8 VCC V
Internal reset
VRES(1) 1.0 1.65 V
threshold voltage
1. Characterized only, not tested in production.

30/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F DC and AC parameters

Table 17. DC characteristics (M95160-R, device grade 6)

Test conditions in addition to those
Symbol Parameter Min. Max. Unit
defined in Table 10 and Table 12(1)

Input leakage
ILI VIN = VSS or VCC ±2 µA
current
Output leakage
ILO S = VCC, voltage applied on Q = VSS or VCC ±2 µA
current
VCC = 1.8 V, C = 0.1 VCC or 0.9 VCC
2
Supply current fC = 5 MHz, Q = open
ICCR mA
(Read) VCC = 2.5 V, C = 0.1 VCC or 0.9 VCC,
3
fC = 5 MHz, Q = open
VCC = 5.0 V, S = VCC, VIN = VSS or VCC 2
Supply current
ICC1 VCC = 2.5 V, S = VCC, VIN = VSS or VCC 1 µA
(Standby)
VCC = 1.8 V, S = VCC, VIN = VSS or VCC 1
2.5 V < VCC < 5.5 V –0.45 0.3 VCC
VIL Input low voltage V
1.8 V < VCC < 2.5 V –0.45 0.25 VCC
2.5 V < VCC < 5.5 V 0.7 VCC VCC+1
VIH Input high voltage V
1.8 V < VCC < 2.5 V 0.75 VCC VCC+1
VCC = 2.5 V, IOL = 1.5 mA,
0.2 VCC
VOL Output low voltage or VCC = 5.5 V, IOL = 2 mA V
VCC = 1.8 V, IOL = 0.15 mA 0.3
VCC = 2.5 V, IOH = –0.4 mA,
VOH Output high voltage or VCC = 5.5 V, IOH = –2 mA, 0.8 VCC V
or VCC = 1.8 V, IOH = –0.1 mA
Internal reset
VRES(2) 1.0 1.65 V
threshold voltage
1. If the application uses the M95160-R device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please refer to Table 16:
DC characteristics (M95160-W, device grade 6), rather than to the above table.
2. Characterized only, not tested in production.

Doc ID 022580 Rev 3 31/46

DC and AC parameters M95160 M95160-W M95160-R M95160-F

Table 18. DC characteristics (M95160-F, device grade 6)

Test conditions in addition to those
Symbol Parameter Min. Max. Unit
defined in Table 11 and Table 12(1)

ILI Input leakage current VIN = VSS or VCC ±2 µA

ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC ±2 µA
VCC = 2.5 V, C = 0.1 VCC or 0.9 VCC,
3 mA
fC = 5 MHz, Q = open
ICCR Supply current (Read)
VCC = 1.7 V, C = 0.1 VCC or 0.9VCC
2 mA
fC = 3.5 MHz, Q = open
VCC = 5.0 V, S = VCC, VIN = VSS or VCC 2 µA
ICC1 Supply current (Standby) VCC = 2.5 V, S = VCC, VIN = VSS or VCC 1 µA
VCC = 1.7 V, S = VCC, VIN = VSS or VCC 1 µA
2.5 V < VCC < 5.5 V –0.45 0.3 VCC V
VIL Input low voltage 1.8 < VCC < 2.5 V –0.45 0.25 VCC V
1.7 V < VCC < 1.8 V –0.45 0.2 VCC V
2.5 V < VCC < 5.5 V 0.7 VCC VCC+1 V
VIH Input high voltage
1.7 V < VCC < 2.5 V 0.75 VCC VCC+1 V
VCC = 2.5 V, IOL = 1.5 mA,
0.2 VCC V
VOL Output low voltage or VCC = 5.5 V, IOL = 2 mA
VCC = 1.7 V, IOL = 0.15 mA 0.2 V
VCC = 2.5 V, IOH = –0.4 mA,
VOH Output high voltage or VCC = 5.5 V, IOH = –2 mA, 0.8 VCC V
or VCC = 1.7 V, IOH = –0.1 mA
Internal reset threshold
VRES(2) 1.0 1.65 V
voltage
1. If the application uses the M95160-F device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please refer to Table 16:
DC characteristics (M95160-W, device grade 6), rather than to the above table.
2. Characterized only, not tested in production.

32/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F DC and AC parameters

Table 19. AC characteristics (M95160-W, device grade 6)

Test conditions specified in Table 9 and Table 12

Symbol Alt. Parameter Min. Max. Unit

fC fSCK Clock frequency D.C. 10 MHz

tSLCH tCSS1 S active setup time 30 ns
tSHCH tCSS2 S not active setup time 30 ns
tSHSL tCS S deselect time 40 ns
tCHSH tCSH S active hold time 30 ns
tCHSL S not active hold time 30 ns
tCH(1) tCLH Clock high time 40 ns
tCL(1) tCLL Clock low time 40 ns
(2)
tCLCH tRC Clock rise time 2 µs
tCHCL (2) tFC Clock fall time 2 µs
tDVCH tDSU Data in setup time 10 ns
tCHDX tDH Data in hold time 10 ns
tHHCH Clock low hold time after HOLD not active 30 ns
tHLCH Clock low hold time after HOLD active 30 ns
tCLHL Clock low set-up time before HOLD active 0 ns
Clock low set-up time before HOLD not
tCLHH 0 ns
active
tSHQZ(2) tDIS Output disable time 40 ns
tCLQV tV Clock low to output valid 40 ns
tCLQX tHO Output hold time 0 ns
tQLQH(2) tRO Output rise time 40 ns
tQHQL(2) tFO Output fall time 40 ns
tHHQV tLZ HOLD high to output valid 40 ns
tHLQZ(2) tHZ HOLD low to output high-Z 40 ns
tW tWC Write time 5 ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.

Doc ID 022580 Rev 3 33/46

DC and AC parameters M95160 M95160-W M95160-R M95160-F

Table 20. AC characteristics (M95160-R, device grade 6)

Test conditions specified in Table 10 and Table 12

Symbol Alt. Parameter Min. Max. Unit

fC fSCK Clock frequency D.C. 5 MHz

tSLCH tCSS1 S active setup time 60 ns
tSHCH tCSS2 S not active setup time 60 ns
tSHSL tCS S deselect time 90 ns
tCHSH tCSH S active hold time 60 ns
tCHSL S not active hold time 60 ns
tCH(1) tCLH Clock high time 80 ns
(1)
tCL tCLL Clock low time 80 ns
(2)
tCLCH tRC Clock rise time 2 µs
tCHCL (2) tFC Clock fall time 2 µs
tDVCH tDSU Data in setup time 20 ns
tCHDX tDH Data in hold time 20 ns
tHHCH Clock low hold time after HOLD not active 60 ns
tHLCH Clock low hold time after HOLD active 60 ns
tCLHL Clock low set-up time before HOLD active 0 ns
tCLHH Clock low set-up time before HOLD not active 0 ns
(2)
tSHQZ tDIS Output disable time 80 ns
tCLQV tV Clock low to output valid 80 ns
tCLQX tHO Output hold time 0 ns
tQLQH(2) tRO Output rise time 80 ns
tQHQL(2) tFO Output fall time 80 ns
tHHQV tLZ HOLD high to output valid 80 ns
tHLQZ(2) tHZ HOLD low to output high-Z 80 ns
tW tWC Write time 5 ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.

34/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F DC and AC parameters

Table 21. AC characteristics (M95160-F, device grade 6)

Test conditions specified in Table 11 and Table 12

Symbol Alt. Parameter Min. Max. Unit

fC fSCK Clock frequency D.C. 3.5 MHz

tSLCH tCSS1 S active setup time 85 ns
tSHCH tCSS2 S not active setup time 85 ns
tSHSL tCS S deselect time 120 ns
tCHSH tCSH S active hold time 85 ns
tCHSL S not active hold time 85 ns
tCH(1) tCLH Clock high time 110 ns
(1)
tCL tCLL Clock low time 110 ns
(2)
tCLCH tRC Clock rise time 2 µs
tCHCL (2) tFC Clock fall time 2 µs
tDVCH tDSU Data in setup time 30 ns
tCHDX tDH Data in hold time 30 ns
tHHCH Clock low hold time after HOLD not active 85 ns
tHLCH Clock low hold time after HOLD active 85 ns
tCLHL Clock low set-up time before HOLD active 0 0
tCLHH Clock low set-up time before HOLD not active 0 0
(2)
tSHQZ tDIS Output disable time 120 ns
tCLQV tV Clock low to output valid 120 ns
tCLQX tHO Output hold time 0 ns
tQLQH(2) tRO Output rise time 100 ns
tQHQL(2) tFO Output fall time 100 ns
tHHQV tLZ HOLD high to output valid 110 ns
tHLQZ(2) tHZ HOLD low to output high-Z 110 ns
tW tWC Write time 5 ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.

Doc ID 022580 Rev 3 35/46

DC and AC parameters M95160 M95160-W M95160-R M95160-F

The values in the following table must not be considered for any new design.

Table 22. AC characteristics (M95160, device grade 6)

End of life products: these values apply only to M95160-MN6TP/S devices
Test conditions specified in Table 8 and Table 12

Symbol Alt. Parameter Min. Max. Unit

fC fSCK Clock frequency D.C. 10 MHz

tSLCH tCSS1 S active setup time 15 ns
tSHCH tCSS2 S not active setup time 15 ns
tSHSL tCS S deselect time 40 ns
tCHSH tCSH S active hold time 25 ns
tCHSL S not active hold time 15 ns
(1)
tCH tCLH Clock high time 40 ns
tCL (1) tCLL Clock low time 40 ns
tCLCH(2) tRC Clock rise time 1 µs
tCHCL (2) tFC Clock fall time 1 µs
tDVCH tDSU Data in setup time 15 ns
tCHDX tDH Data in hold time 15 ns
tHHCH Clock low hold time after HOLD not active 15 ns
tHLCH Clock low hold time after HOLD active 20 ns
tCLHL Clock low set-up time before HOLD active 0 ns
tCLHH Clock low set-up time before HOLD not active 0 ns
tSHQZ(2) tDIS Output disable time 25 ns
tCLQV tV Clock low to output valid 35 ns
tCLQX tHO Output hold time 0 ns
tQLQH(2) tRO Output rise time 20 ns
tQHQL(2) tFO Output fall time 20 ns
tHHQV tLZ HOLD high to output valid 25 ns
tHLQZ(2) tHZ HOLD low to output high-Z 35 ns
tW tWC Write Time 5 ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.

36/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F DC and AC parameters

The values in the following table must not be considered for any new design.

Table 23. AC characteristics (M95160-W, device grade 6)

End of life products: these values apply only to M95160-WMN6TP/S
and M95160-WDW6TP/S devices)
Test conditions specified in Table 9 and Table 12

Symbol Alt. Parameter Min. Max. Unit

fC fSCK Clock frequency D.C. 5 MHz

tSLCH tCSS1 S active setup time 90 ns
tSHCH tCSS2 S not active setup time 90 ns
tSHSL tCS S deselect time 100 ns
tCHSH tCSH S active hold time 90 ns
tCHSL S not active hold time 90 ns
tCH(1) tCLH Clock high time 90 ns
tCL(1) tCLL Clock low time 90 ns
tCLCH(2) tRC Clock rise time 1 µs
tCHCL (2) tFC Clock fall time 1 µs
tDVCH tDSU Data in setup time 20 ns
tCHDX tDH Data in hold time 30 ns
tHHCH Clock low hold time after HOLD not active 70 ns
tHLCH Clock low hold time after HOLD active 40 ns
tCLHL Clock low set-up time before HOLD active 0 ns
tCLHH Clock low set-up time before HOLD not active 0 ns
tSHQZ(2) tDIS Output disable time 100 ns
tCLQV tV Clock low to output valid 60 ns
tCLQX tHO Output hold time 0 ns
tQLQH (2) tRO Output rise time 50 ns
tQHQL(2) tFO Output fall time 50 ns
tHHQV tLZ HOLD high to output valid 50 ns
(2)
tHLQZ tHZ HOLD low to output high-Z 100 ns
tW tWC Write time 5 ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.

Doc ID 022580 Rev 3 37/46

DC and AC parameters M95160 M95160-W M95160-R M95160-F

Figure 16. Serial input timing

tSHSL

tCHSL tSLCH tCH tCHSH tSHCH

tDVCH tCHCL tCL tCLCH

tCHDX

D MSB IN LSB IN

High impedance
Q

AI01447d

Figure 17. Hold timing

tHLCH

tCLHL tHHCH

tCLHH

tHLQZ tHHQV

HOLD

AI01448c

38/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F DC and AC parameters

Figure 18. Serial output timing

tCH tSHSL

tCLQV tCLCH tCHCL tCL tSHQZ

tCLQX

tQLQH
tQHQL

ADDR
D LSB IN

AI01449f

Doc ID 022580 Rev 3 39/46

Package mechanical data M95160 M95160-W M95160-R M95160-F

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 19. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚

A2 A
c
ccc
b
e

0.25 mm
D GAUGE PLANE

k
8

E1 E
1 L
A1
L1

SO-A

1. Drawing is not to scale.

Table 24. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data
millimeters inches(1)
Symbol
Typ Min Max Typ Min Max

A 1.750 0.0689
A1 0.100 0.250 0.0039 0.0098
A2 1.250 0.0492
b 0.280 0.480 0.0110 0.0189
c 0.170 0.230 0.0067 0.0091
ccc 0.100 0.0039
D 4.900 4.800 5.000 0.1929 0.1890 0.1969
E 6.000 5.800 6.200 0.2362 0.2283 0.2441
E1 3.900 3.800 4.000 0.1535 0.1496 0.1575
e 1.270 - - 0.0500 - -
h 0.250 0.500 0.0098 0.0197
k 0° 8° 0° 8°
L 0.400 1.270 0.0157 0.0500
L1 1.040 0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.

40/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Package mechanical data

Figure 20. TSSOP8 – 8-lead thin shrink small outline, package outline
D

8 5
c

E1 E

1 4

A1 L
A A2
CP L1

b e
TSSOP8AM

1. Drawing is not to scale.

Table 25. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters inches(1)
Symbol
Typ Min Max Typ Min Max

A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 - - 0.0256 - -
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α 0° 8° 0° 8°
N 8 8
1. Values in inches are converted from mm and rounded to four decimal digits.

Doc ID 022580 Rev 3 41/46

Package mechanical data M95160 M95160-W M95160-R M95160-F

Figure 21. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package
outline

$ E B

,
,

0IN
% %

+
,
!

$
EEE
! :7?-%E6

1. Drawing is not to scale.

2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.

Table 26. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
millimeters inches(1)
Symbol
Typ Min Max Typ Min Max

A 0.550 0.450 0.600 0.0217 0.0177 0.0236

A1 0.020 0.000 0.050 0.0008 0.0000 0.0020
b 0.250 0.200 0.300 0.0098 0.0079 0.0118
D 2.000 1.900 2.100 0.0787 0.0748 0.0827
D2 (rev MC) 1.200 1.600 0.0472 0.0630
E 3.000 2.900 3.100 0.1181 0.1142 0.1220
E2 (rev MC) 1.200 1.600 0.0472 0.0630
e 0.500 0.0197
K (rev MC) 0.300 0.0118
L 0.300 0.500 0.0118 0.0197
L1 0.150 0.0059
L3 0.300 0.0118
eee(2) 0.080 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.

42/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Package mechanical data

Figure 22. WLCSP-R – 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package outline
e1 G
D e

C
Detail A e
E B e1
Orientation
reference
A

Orientation aaa F
3 2 1
reference Wafer back side (×4) A Bump side
A2
Side view
Bump

A1
eee Z

Z
b
Detail A Seating plane
Rotated 90˚ (see note 1) 1C_ME

1. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
2. Drawing is not to scale.
3. Preliminary data.

Table 27. WLCSP-R – 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package mechanical
data (preliminary data)
millimeters inches(1)
Symbol
Typ Min Max Typ Min Max

A 0.545 0.490 0.600 0.0193 0.0215 0.0236

A1 0.190 0.0075
A2 0.355 0.014
b(2) 0.270 0.240 0.300 0.0106 0.0094 0.0118
D 1.350 1.475 0.0531 0.0581
E 1.365 1.490 0.0537 0.0587
e 0.400 0.0157
e1 0.800 0.0315
F 0.282 0.0111
G 0.275 0.0108
N (total number of
8 8
terminals)
aaa 0.110 0.0043
eee 0.060 0.0024
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

Doc ID 022580 Rev 3 43/46

Part numbering M95160 M95160-W M95160-R M95160-F

11 Part numbering

Table 28. Ordering information scheme

Example: M95160 W MN 6 T P /S
Device type
M95 = SPI serial access EEPROM

Device function
160 = 16 Kbit (2048 x 8)

Operating voltage
blank = VCC = 4.5 to 5.5 V
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
F = VCC = 1.7 to 5.5 V

Package(1)
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MC = UFDFPN8 (MLP8)
CS = WLCSP

Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow

Option
blank = Standard packing
T = Tape and reel packing

Plating technology
G or P = RoHS compliant and halogen-free
(ECOPACK®)

Process(2)
/G or /S= Manufacturing technology code
1. All packages are ECOPACK2® (RoHS compliant and halogen-free).
2. The process letters apply to WLCSP devices only. The process letters appear on the device package
(marking) and on the shipment box. Please contact your nearest ST Sales Office for further information.

44/46 Doc ID 022580 Rev 3

M95160 M95160-W M95160-R M95160-F Revision history

12 Revision history

Table 29. Document revision history

Date Revision Changes

22-Mar-2012 1 Initial release.

Updated:
– All information about package UFDFPN8
17-Dec-2012 2
– Introduction of Description
– Section 7.2: Initial delivery state
08-Jan-2013 3 Updated plating technology in Section 11: Part numbering.

Doc ID 022580 Rev 3 45/46

M95160 M95160-W M95160-R M95160-F

Please Read Carefully:

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

© 2013 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

46/46 Doc ID 022580 Rev 3

M95080 M95080-W M95080-R

8-Kbit serial SPI bus EEPROM with high-speed clock

Datasheet − production data

Features
■ Compatible with the Serial Peripheral Interface
(SPI) bus
■ Memory array
– 8 Kb (1 Kbyte) of EEPROM SO8 (MN)
– Page size: 32 bytes 150 mil width
■ Write
– Byte Write within 5 ms
– Page Write within 5 ms
■ Write Protect: quarter, half or whole memory
array
■ High-speed clock: 10 MHz TSSOP8 (DW)
169 mil width
■ Single supply voltage:
– 4.5 V to 5.5 V for M95080
– 2.5 V to 5.5 V for M95080-W
– 1.8 V to 5.5 V for M95080-R
■ Operating temperature range: from -40°C up to
+85°C UFDFPN8 (MB, MC)
■ Enhanced ESD protection 2 × 3 mm (MLP)

■ More than 1 million Write cycles

■ More than 40-year data retention
■ Packages
– RoHS compliant and halogen-free
(ECOPACK®)

March 2012 Doc ID 022540 Rev 1 1/42

This is information on a product in full production. www.st.com 1
Contents M95080 M95080-W M95080-R

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Contents

6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Doc ID 022540 Rev 1 3/42

List of tables M95080 M95080-W M95080-R

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Operating conditions (M95080, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. Operating conditions (M95080-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Operating conditions (M95080-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. DC characteristics (M95080, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14. DC characteristics (M95080-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15. DC characteristics (M95080-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 16. AC characteristics (M95080-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17. AC characteristics (M95080-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 18. AC characteristics (M95080, device grade 6)
End of life products: these values apply only to M95080-MN6TP/S devices . . . . . . . . . . . 33
Table 19. AC characteristics (M95080-W, device grade 6)
End of life products: these values apply only to M95080-WMN6TP/S
and M95080-WDW6TP/S devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 20. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 37
Table 21. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 22. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 39
Table 23. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 24. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 16. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 37
Figure 19. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 39

Doc ID 022540 Rev 1 5/42

Description M95080 M95080-W M95080-R

1 Description

The M95080 devices are Electrically Erasable PROgrammable Memories (EEPROMs)

organized as 1024 x 8 bits, accessed through the SPI bus.
The M95080 devices can operate with a supply range from 1.8 V up to 5.5 V, and are
guaranteed over the -40 °C/+85 °C temperature range.

Figure 1. Logic diagram

VCC

D Q

S M95xxx

HOLD

VSS
AI01789C

Table 1. Signal names

Signal name Function Direction

C Serial Clock Input

D Serial Data Input Input
Q Serial Data Output Output
S Chip Select Input
W Write Protect Input
HOLD Hold Input
VCC Supply voltage
VSS Ground

6/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Description

Figure 2. 8-pin package connections (top view)

M95xxx

S 1 8 VCC
Q 2 7 HOLD
W 3 6 C
VSS 4 5 D
AI01790D

1. See Section 10: Package mechanical data section for package dimensions, and how to identify pin 1.

Doc ID 022540 Rev 1 7/42

Memory organization M95080 M95080-W M95080-R

2 Memory organization

The memory is organized as shown in the following figure.

Figure 3. Block diagram

HOLD
High voltage
W Control logic generator
S

D
I/O shift register
Q

Address register Data

and counter register

Status
Register Size of the
read-only
EEPROM
area
Y decoder

1 page

X decoder

AI01272d

8/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Signal description

3 Signal description

3.1 Serial Data Output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).

3.2 Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).

3.3 Serial Clock (C)

3.4 Chip Select (S)

3.5 Hold (HOLD)

Doc ID 022540 Rev 1 9/42

Signal description M95080 M95080-W M95080-R

3.6 Write Protect (W)

3.7 VCC supply voltage

VCC is the supply voltage.

3.8 VSS ground

VSS is the reference for all signals, including the VCC supply voltage.

10/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Connecting to the SPI bus

4 Connecting to the SPI bus

Figure 4. Bus master and memory devices on the SPI bus

VSS

VCC

SDO
SPI Interface with
SDI
(CPOL, CPHA) =
(0, 0) or (1, 1) SCK

C Q D VCC C Q D VCC C Q D VCC

SPI Bus Master VSS VSS VSS

R SPI Memory R SPI Memory R SPI Memory

Device Device Device
CS3 CS2 CS1

S W HOLD S W HOLD S W HOLD

AI12836b

1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 4 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the
tSHCH requirement is met. The typical value of R is 100 kΩ..

Doc ID 022540 Rev 1 11/42

Connecting to the SPI bus M95080 M95080-W M95080-R

4.1 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)
● C remains at 1 for (CPOL=1, CPHA=1)

Figure 5. SPI modes supported

CPOL CPHA

0 0 C

1 1 C

D MSB

Q MSB

AI01438B

12/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Operating features

5 Operating features

5.1 Supply voltage (VCC)

5.1.1 Operating supply voltage VCC

5.1.2 Device reset

5.1.3 Power-up conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 4).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.

Doc ID 022540 Rev 1 13/42

Operating features M95080 M95080-W M95080-R

5.2 Active Power and Standby Power modes

5.3 Hold condition

Figure 6. Hold condition activation

HOLD

Hold Hold
Condition Condition

AI02029D

The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 6).

14/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Operating features

The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)
is already low.
Figure 6 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.

5.4 Status Register

5.5 Data protection and protocol control

Table 2. Write-protected block size

Status Register bits
Protected block Protected array addresses
BP1 BP0

0 0 none none
0 1 Upper quarter 0300h - 03FFh
1 0 Upper half 0200h - 03FFh
1 1 Whole memory 0000h - 03FFh

Doc ID 022540 Rev 1 15/42

Instructions M95080 M95080-W M95080-R

6 Instructions

Each instruction starts with a single-byte code, as summarized in Table 3.

If an invalid instruction is sent (one not contained in Table 3), the device automatically
deselects itself.

Table 3. Instruction set

Instruction Description Instruction format

WREN Write Enable 0000 0110

WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010

Table 4. Address range bits

Address significant bits A9-A0(1)
1. Upper MSBs are Don’t Care.

6.1 Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.

Figure 7. Write Enable (WREN) sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance
Q
AI02281E

16/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Instructions

6.2 Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
● Power-up
● WRDI instruction execution
● WRSR instruction completion
● WRITE instruction completion.

Figure 8. Write Disable (WRDI) sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance
Q
AI03750D

Doc ID 022540 Rev 1 17/42

Instructions M95080 M95080-W M95080-R

6.3 Read Status Register (RDSR)

Figure 9. Read Status Register (RDSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

Status Register Out Status Register Out

High Impedance
Q 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

AI02031E

The status and control bits of the Status Register are as follows:

6.3.1 WIP bit

6.3.2 WEL bit

6.3.3 BP1, BP0 bits

18/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Instructions

6.3.4 SRWD bit

Table 5. Status Register format

b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP

Status Register Write Protect

Block Protect bits
Write Enable Latch bit
Write In Progress bit

Doc ID 022540 Rev 1 19/42

Instructions M95080 M95080-W M95080-R

6.4 Write Status Register (WRSR)

Figure 10. Write Status Register (WRSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction Status
Register In

D 7 6 5 4 3 2 1 0

High Impedance MSB

Q
AI02282D

20/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Instructions

Table 6. Protection modes

Memory content
W SRWD Write protection of the
Mode
signal bit Status Register
Protected area(1) Unprotected area(1)

The protection features of the device are summarized in Table 6.

Doc ID 022540 Rev 1 21/42

Instructions M95080 M95080-W M95080-R

6.5 Read from Memory Array (READ)

As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).

Figure 11. Read from Memory Array (READ) sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

Instruction 16-Bit Address

D 15 14 13 3 2 1 0
MSB
Data Out 1 Data Out 2
High Impedance
Q 7 6 5 4 3 2 1 0 7
MSB

AI01793D

22/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Instructions

6.6 Write to Memory Array (WRITE)

As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period tW (as specified in AC characteristics in Section 9: DC and AC parameters), at the
end of which the Write in Progress (WIP) bit is reset to 0.

Figure 12. Byte Write (WRITE) sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

Instruction 16-Bit Address Data Byte

D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

High Impedance
Q

AI01795D

1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
In the case of Figure 12, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in Figure 13, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
● if a Write cycle is already in progress,
● if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
● if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Note: The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.

Doc ID 022540 Rev 1 23/42

Instructions M95080 M95080-W M95080-R

Figure 13. Page Write (WRITE) sequence

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31

Instruction 16-Bit Address Data Byte 1

D 15 14 13 3 2 1 0 7 6 5 4 3 2 1 0

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Data Byte 2 Data Byte 3 Data Byte N

D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0

AI01796D

1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.

24/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Power-up and delivery state

7 Power-up and delivery state

7.1 Power-up state

7.2 Initial delivery state

The device is delivered with the memory array set to all 1s (each byte = FFh). The Status
Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.

Doc ID 022540 Rev 1 25/42

Maximum rating M95080 M95080-W M95080-R

8 Maximum rating

Table 7. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

Ambient operating temperature –40 130 °C

TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering See note (1) °C
VO Output voltage –0.50 VCC+0.6 V
VI Input voltage –0.50 6.5 V
VCC Supply voltage –0.50 6.5 V
IOL DC output current (Q = 0) 5 mA
IOH DC output current (Q = 1) 5 mA
VESD Electrostatic discharge voltage (human body model)(2) 4000 V
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), with the ST ECOPACK®
7191395 specification, and with the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with JEDEC Std
JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).

26/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R DC and AC parameters

9 DC and AC parameters

This section summarizes the operating conditions and the DC/AC characteristics of the
device.

Table 8. Operating conditions (M95080, device grade 6)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 4.5 5.5 V

TA Ambient operating temperature –40 85 °C

Table 9. Operating conditions (M95080-W, device grade 6)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 2.5 5.5 V

TA Ambient operating temperature –40 85 °C

Table 10. Operating conditions (M95080-R, device grade 6)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 1.8 5.5 V

TA Ambient operating temperature –40 85 °C

Table 11. AC measurement conditions

Symbol Parameter Min. Max. Unit

CL Load capacitance 30 pF
Input rise and fall times 50 ns
Input pulse voltages 0.2 VCC to 0.8 VCC V
Input and output timing reference voltages 0.3 VCC to 0.7 VCC V

Figure 14. AC measurement I/O waveform

)NPUT VOLTAGE LEVELS )NPUT AND OUTPUT
TIMING REFERENCE LEVELS
6##
6##

6##
6##

!)#

Doc ID 022540 Rev 1 27/42

DC and AC parameters M95080 M95080-W M95080-R

Table 12. Capacitance

Symbol Parameter Test conditions(1) Min. Max. Unit

COUT Output capacitance (Q) VOUT = 0 V 8 pF

Input capacitance (D) VIN = 0 V 8 pF
CIN
Input capacitance (other pins) VIN = 0 V 6 pF
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.

Table 13. DC characteristics (M95080, device grade 6)

Symbol Parameter Test conditions Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC ±2 µA

ILO Output leakage current S = VCC, VOUT = VSS or VCC ±2 µA
C = 0.1 VCC/0.9 VCC at 10 MHz,
ICC Supply current (Read) 5 mA
VCC = 5 V, Q = open
Supply current S = VCC, VCC = 5 V,
ICC1 2 µA
(Standby) VIN = VSS or VCC
VIL Input low voltage –0.45 0.3 VCC V
VIH Input high voltage 0.7 VCC VCC+1 V
VOL(1) Output low voltage IOL = 2 mA, VCC = 5 V 0.4 V
(1)
VOH Output high voltage IOH = –2 mA, VCC = 5 V 0.8 VCC V
Internal reset threshold
VRES(2) 2.5 3.5 V
voltage
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Characterized only, not tested in production.

28/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R DC and AC parameters

Table 14. DC characteristics (M95080-W, device grade 6)

Symbol Parameter Test conditions Min. Max. Unit

Input leakage
ILI VIN = VSS or VCC ±2 µA
current
Output leakage
ILO S = VCC, VOUT = VSS or VCC ±2 µA
current
C = 0.1 VCC/0.9 VCC at 5 MHz,
2
Supply current VCC = 2.5 V, Q = open
ICC mA
(Read) C = 0.1 VCC/0.9 VCC at 10 MHz,
5
VCC = 2.5 V, Q = open
Supply current S = VCC, 2.5 V <VCC < 5.5 V
ICC1 2 µA
(Standby) VIN = VSS or VCC
VIL Input low voltage –0.45 0.3 VCC V
VIH Input high voltage 0.7 VCC VCC+1 V
VOL Output low voltage IOL = 1.5 mA, VCC = 2.5 V 0.4 V
VOH Output high voltage IOH = –0.4 mA, VCC = 2.5 V 0.8 VCC V
Internal reset
VRES(1) 1.0 1.65 V
threshold voltage
1. Characterized only, not tested in production.

Doc ID 022540 Rev 1 29/42

DC and AC parameters M95080 M95080-W M95080-R

Table 15. DC characteristics (M95080-R, device grade 6)

Symbol Parameter Test conditions Min. Max. Unit

Input leakage
ILI VIN = VSS or VCC ±2 µA
current
Output leakage
ILO S = VCC, voltage applied on Q = VSS or VCC ±2 µA
current
VCC = 1.8 V, C = 0.1 VCC or 0.9 VCC
2
fC = 5 MHz, Q = open
Supply current VCC = 2.5 V, C = 0.1 VCC or 0.9 VCC,
ICCR 3 mA
(Read) fC = 5 MHz, Q = open
VCC ≥ 2.5 V, C = 0.1 VCC or 0.9 VCC,
5
fC = 10 MHz, Q = open
VCC = 5.0 V, S = VCC, VIN = VSS or VCC 2
Supply current
ICC1 VCC = 2.5 V, S = VCC, VIN = VSS or VCC 1 µA
(Standby)
VCC = 1.8 V, S = VCC, VIN = VSS or VCC 1
2.5 V < VCC < 5.5 V –0.45 0.3 VCC
VIL Input low voltage V
1.8 V < VCC < 2.5 V –0.45 0.25 VCC
2.5 V < VCC < 5.5 V 0.7 VCC VCC+1
VIH Input high voltage V
1.8 V < VCC < 2.5 V 0.75 VCC VCC+1
VCC = 2.5 V, IOL = 1.5 mA,
0.2 VCC
VOL Output low voltage or VCC = 5.5 V, IOL = 2 mA V
VCC = 1.8 V, IOL = 0.15 mA 0.3
VCC = 2.5 V, IOH = –0.4 mA,
VOH Output high voltage or VCC = 5.5 V, IOH = –2 mA, 0.8 VCC V
or VCC = 1.8 V, IOH = –0.1 mA
Internal reset
VRES(1) 1.0 1.65 V
threshold voltage
1. Characterized only, not tested in production.

30/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R DC and AC parameters

Table 16. AC characteristics (M95080-W, device grade 6)

Test conditions specified in Table 9 and Table 11

Symbol Alt. Parameter Min. Max. Unit

fC fSCK Clock frequency D.C. 10 MHz

Doc ID 022540 Rev 1 31/42

DC and AC parameters M95080 M95080-W M95080-R

Table 17. AC characteristics (M95080-R, device grade 6)

Test conditions specified in Table 10 and Table 11

Symbol Alt. Parameter Min. Max. Unit

fC fSCK Clock frequency D.C. 5 MHz

32/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R DC and AC parameters

The values in the following table must not be considered for any new design.

Table 18. AC characteristics (M95080, device grade 6)

End of life products: these values apply only to M95080-MN6TP/S devices
Test conditions specified in Table 8 and Table 11

Symbol Alt. Parameter Min. Max. Unit

fC fSCK Clock frequency D.C. 10 MHz

Doc ID 022540 Rev 1 33/42

DC and AC parameters M95080 M95080-W M95080-R

The values in the following table must not be considered for any new design.

Table 19. AC characteristics (M95080-W, device grade 6)

End of life products: these values apply only to M95080-WMN6TP/S
and M95080-WDW6TP/S devices)
Test conditions specified in Table 9 and Table 11

Symbol Alt. Parameter Min. Max. Unit

fC fSCK Clock frequency D.C. 5 MHz

34/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R DC and AC parameters

Figure 15. Serial input timing

tSHSL

tCHSL tSLCH tCH tCHSH tSHCH

tDVCH tCHCL tCL tCLCH

tCHDX

D MSB IN LSB IN

High impedance
Q

AI01447d

Figure 16. Hold timing

tHLCH

tCLHL tHHCH

tCLHH

tHLQZ tHHQV

HOLD

AI01448c

Doc ID 022540 Rev 1 35/42

DC and AC parameters M95080 M95080-W M95080-R

Figure 17. Serial output timing

tCH tSHSL

tCLQV tCLCH tCHCL tCL tSHQZ

tCLQX

tQLQH
tQHQL

ADDR
D LSB IN

AI01449f

36/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Package mechanical data

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 18. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚

A2 A
c
ccc
b
e

0.25 mm
D GAUGE PLANE

k
8

E1 E
1 L
A1
L1

SO-A

1. Drawing is not to scale.

Table 20. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data
millimeters inches(1)
Symbol
Typ Min Max Typ Min Max

Doc ID 022540 Rev 1 37/42

Package mechanical data M95080 M95080-W M95080-R

Figure 19. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline
-" -#

$ E B E B

, ,
, ,

0IN
% % %

+
+
, ,
!

$ $
EEE
! :7?-%E

1. Drawing is not to scale.

2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.

Table 21. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
millimeters inches(1)
Symbol
Typ Min Max Typ Min Max

A 0.550 0.450 0.600 0.0217 0.0177 0.0236

A1 0.020 0.000 0.050 0.0008 0.0000 0.0020
b 0.250 0.200 0.300 0.0098 0.0079 0.0118
D 2.000 1.900 2.100 0.0787 0.0748 0.0827
D2 (rev MB) 1.600 1.500 1.700 0.0630 0.0591 0.0669
D2 (rev MC) 1.200 1.600 0.0472 0.0630
E 3.000 2.900 3.100 0.1181 0.1142 0.1220
E2 (rev MB) 0.200 0.100 0.300 0.0079 0.0039 0.0118
E2 (rev MC) 1.200 1.600 0.0472 0.0630
e 0.500 0.0197
K (rev MB) 0.800 0.0315
K (rev MC) 0.300 0.0118
L 0.300 0.500 0.0118 0.0197
L1 0.150 0.0059
L3 0.300 0.0118
(2)
eee 0.080 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.

38/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Package mechanical data

Figure 20. TSSOP8 – 8-lead thin shrink small outline, package outline
D

8 5
c

E1 E

1 4

A1 L
A A2
CP L1

b e
TSSOP8AM

1. Drawing is not to scale.

Table 22. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters inches(1)
Symbol
Typ Min Max Typ Min Max

Doc ID 022540 Rev 1 39/42

Part numbering M95080 M95080-W M95080-R

11 Part numbering

Table 23. Ordering information scheme

Example: M95080 W MN 6 T P /S

Device type
M95 = SPI serial access EEPROM

Device function
080 = 8 Kbit (1024 x 8)

Operating voltage
blank = VCC = 4.5 to 5.5 V
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V

Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MB or MC = UFDFPN8 (MLP8)

Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow

Option
blank = Standard packing
T = Tape and reel packing

Plating technology
G or P = RoHS compliant and halogen-free
(ECOPACK®)

Process(1)
/G or /S = Manufacturing technology code
1. The process letters appear on the device package (marking) and on the shipment box. Please contact your
nearest ST Sales Office.

40/42 Doc ID 022540 Rev 1

M95080 M95080-W M95080-R Revision history

12 Revision history

Table 24. Document revision history

Date Revision Changes

22-Mar-2012 1 Initial release.

Doc ID 022540 Rev 1 41/42

M95080 M95080-W M95080-R

Please Read Carefully:

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

42/42 Doc ID 022540 Rev 1

M950x0-W M950x0-R

4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM

with high-speed clock
Datasheet - production data

Features
• Compatible with SPI bus serial interface
(Positive clock SPI modes)
• Single supply voltage:
– 2.5 V to 5.5 V for M950x0-W
– 1.8 V to 5.5 V for M950x0-R
• High speed 10 MHz clock rate, 5 ms write time
• Status register
SO8 (MN)
150 mil width • Byte and Page Write (up to 16 bytes)
• Self-timed programming cycle
• Adjustable size read-only EEPROM area
• Enhanced ESD protection
• More than 1 million write cycles
TSSOP8 (DW) • More than 40-year data retention
169 mil width • Packages RoHS-compliant and Halogen-free
(ECOPACK2®)

Table 1. Device summary

Reference Part number

M95040-W
UFDFPN8 (MC)
M950x0-W M95020-W
2 x 3 mm
M95010-W
M95040-R
M950x0-R M95020-R
M95010-R

May 2013 DocID6512 Rev 11 1/39

This is information on a product in full production. www.st.com 1
Contents M950x0-W M950x0-R

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2/39 DocID6512 Rev 11

M950x0-W M950x0-R Contents

6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Power-up and delivery states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DocID6512 Rev 11 3/39

List of tables M950x0-W M950x0-R

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Operating conditions (M950x0-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Operating conditions (M950x0-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. DC characteristics (M950x0-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13. DC characteristics (M950x0-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. AC characteristics (M950x0-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 15. AC characteristics (M950x0-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 16. SO8N 8-lead plastic small outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 17. TSSOP8 8-lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . . . . 33
Table 18. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 19. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4/39 DocID6512 Rev 11

M950x0-W M950x0-R List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. AC test measurement I/O waveform(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. SO8N 8-lead plastic small outline 150 mils body width, package outline . . . . . . . . . . . . . . 32
Figure 19. TSSOP8 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

DocID6512 Rev 11 5/39

Description M950x0-W M950x0-R

1 Description

The M95010/ M95020/M95040 devices (M950x0) are electrically erasable programmable

memories (EEPROMs) organized as 128/256/512 x 8 bits respectively, accessed through
the SPI bus.
The M950x0 can operate over an ambient temperature range of -40 °C / +85 °C. and with
the following supply voltage range: M950x0-W: 2.5 V to 5.5 V, and M950x0-R: 1.8 V to 5.5 V.

Figure 1. Logic diagram

VCC

D Q

S M95xxx

HOLD

VSS
AI01789C

Figure 2. 8-pin package connections

M95xxx

S 1 8 VCC
Q 2 7 HOLD
W 3 6 C
VSS 4 5 D
AI01790D

1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.

6/39 DocID6512 Rev 11

M950x0-W M950x0-R Description

Table 2. Signal names

Signal name Function

C Serial Clock
D Serial Data input
Q Serial Data output
S Chip Select
W Write Protect
HOLD Hold
VCC Supply voltage
VSS Ground

DocID6512 Rev 11 7/39

Signal description M950x0-W M950x0-R

2 Signal description

During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals can be held high or low (according to voltages of VIH, VOH,
VIL or VOL, as specified in Table 12: DC characteristics (M950x0-W, device grade 6) and
Table 13: DC characteristics (M950x0-R, device grade 6). These signals are described next.

2.1 Serial Data Output (Q)

This output signal transfers data serially out of the device. Data is shifted out on the falling
edge of Serial Clock (C).

2.2 Serial Data Input (D)

This input signal transfers data serially into the device. It receives instructions, addresses,
and the data to be written. Values are latched on the rising edge of Serial Clock (C).

2.3 Serial Clock (C)

2.4 Chip Select (S)

When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.

2.5 Hold (HOLD)

8/39 DocID6512 Rev 11

M950x0-W M950x0-R Signal description

2.6 Write Protect (W)

This input signal controls whether the memory is write protected. When Write Protect (W) is
held low, writes to the memory are disabled, but other operations remain enabled.
Write Protect (W) must either be driven high or low, but must not be left floating.

2.7 VSS ground

VSS is the reference for the VCC supply voltage.

2.8 Supply voltage (VCC)

2.8.1 Operating supply voltage (VCC)

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 8: Operating
conditions (M950x0-W) and Table 9: Operating conditions (M950x0-R)). This voltage must
remain stable and valid until the end of the transmission of the instruction and, for a Write
instruction, until the completion of the internal write cycle (tW).
In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line
with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS
package pins.

2.8.2 Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until VCC
reaches the internal reset threshold voltage (this threshold is defined in Table 8: Operating
conditions (M950x0-W) and Table 9: Operating conditions (M950x0-R) as VRES).
When VCC passes over the POR threshold, the device is reset and is in the following state:
• Standby Power mode
• Deselected (note that, to be executed, an instruction must be preceded by a falling
edge on Chip Select (S))
• Status register value:
– Write Enable Latch (WEL) is reset to 0
– Write In Progress (WIP) is reset to 0
– SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
When the device is in the above state, it must not be accessed until VCC reaches a valid and
stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 8:
Operating conditions (M950x0-W) and Table 9: Operating conditions (M950x0-R).

DocID6512 Rev 11 9/39

Signal description M950x0-W M950x0-R

2.8.3 Power-up conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 3: Bus master and memory devices on the SPI bus).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Table 8: Operating conditions (M950x0-W) and Table 9: Operating conditions
(M950x0-R) and the rise time must not vary faster than 1 V/µs.

2.8.4 Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum
VCC operating voltage defined in Table 8: Operating conditions (M950x0-W) and Table 9:
Operating conditions (M950x0-R)), the device must be:
• Deselected (Chip Select S should be allowed to follow the voltage applied on VCC)
• In Standby Power mode (there should not be any internal write cycle in progress).

10/39 DocID6512 Rev 11

M950x0-W M950x0-R Connecting to the SPI bus

3 Connecting to the SPI bus

The device is fully compatible with the SPI protocol.

All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 3: Bus master and memory devices on the SPI bus shows an example of three
memory devices connected to an MCU, on an SPI bus. Only one memory device is selected
at a time, so only one memory device drives the Serial Data output (Q) line at a time, the
other memory devices are high impedance.
The pull-up resistor R (represented in Figure 3: Bus master and memory devices on the SPI
bus) ensures that a device is not selected if the bus master leaves the S line in the high
impedance state.
In applications where the bus master might enter a state where all SPI bus inputs/outputs
would be in high impedance at the same time (for example, if the bus master is reset during
the transmission of an Instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high): this ensures that S and C do not become high at the same
time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ..

Figure 3. Bus master and memory devices on the SPI bus

VSS

VCC

SDO
SPI Interface with
SDI
(CPOL, CPHA) =
(0, 0) or (1, 1) SCK

C Q D VCC C Q D VCC C Q D VCC

Bus master VSS VSS VSS

R SPI mmory R SPI memory R SPI memory

device device device
CS3 CS2 CS1

S W HOLD S W HOLD S W HOLD

AI12304b

1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.

DocID6512 Rev 11 11/39

Connecting to the SPI bus M950x0-W M950x0-R

3.1 SPI modes

The device can be driven by a microcontroller with its SPI peripheral running in either of the
following modes:
• CPOL=0, CPHA=0
• CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4: SPI modes supported, is the
clock polarity when the bus master is in Stand-by mode and not transferring data:
• C remains at 0 for (CPOL=0, CPHA=0)
• C remains at 1 for (CPOL=1, CPHA=1)

Figure 4. SPI modes supported

CPOL CPHA

0 0 C

1 1 C

D MSB

Q MSB

AI01438B

12/39 DocID6512 Rev 11

M950x0-W M950x0-R Operating features

4 Operating features

4.1 Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in Figure 5: Hold condition activation).
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 5: Hold condition activation also shows what happens if the rising and falling edges
are not timed to coincide with Serial Clock (C) being low.

Figure 5. Hold condition activation

HOLD

Hold Hold
Condition Condition

AI02029D

4.2 Status register

Figure 6: Block diagram shows the position of the Status register in the control logic of the
device. This register contains a number of control bits and status bits, as shown in Table 5:
Status register format and as detailed in Section 6.3: Read Status Register (RDSR).

DocID6512 Rev 11 13/39

Operating features M950x0-W M950x0-R

4.3 Data protection and protocol control

To help protect the device from data corruption in noisy or poorly controlled environments, a
number of safety features have been built in to the device. The main security measures can
be summarized as follows:
• WEL bit is reset at power-up.
• Chip Select (S) must rise after the eighth clock count (or multiple thereof) in order to
start a non-volatile Write cycle (in the memory array or in the Status register).
• Accesses to the memory array are ignored during the non-volatile programming cycle,
and the programming cycle continues unaffected.
• Invalid Chip Select (S) and Hold (HOLD) transitions are ignored.
For any instruction to be accepted and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) that latches the last bit of the instruction, and before the
next rising edge of Serial Clock (C).
For this, “the last bit of the instruction” can be the eighth bit of the instruction code, or the
eighth bit of a data byte, depending on the instruction (except in the case of RDSR and
READ instructions). Moreover, the “next rising edge of CLOCK” might (or might not) be the
next bus transaction for some other device on the bus.
When a Write cycle is in progress, the device protects it against external interruption by
ignoring any subsequent READ, WRITE or WRSR instruction until the present cycle is
complete.

Table 3. Write-protected block size

Status register bits Protected array addresses
Protected block
BP1 BP0 M95040 M95020 M95010

0 0 none none none none

0 1 Upper quarter 180h - 1FFh C0h - FFh 60h - 7Fh
1 0 Upper half 100h - 1FFh 80h - FFh 40h - 7Fh
1 1 Whole memory 000h - 1FFh 00h - FFh 00h - 7Fh

14/39 DocID6512 Rev 11

M950x0-W M950x0-R Memory organization

5 Memory organization

The memory is organized as shown in Figure 6: Block diagram.

Figure 6. Block diagram

HOLD
High Voltage
W Control Logic Generator
S

D
I/O Shift Register
Q

Address Register Data

and Counter Register

Status
Register Size of the
Read only
EEPROM
area
Y Decoder

1 Page

X Decoder

AI01272C

DocID6512 Rev 11 15/39

Instructions M950x0-W M950x0-R

6 Instructions

Each instruction starts with a single-byte code, as summarized in Table 4: Instruction set.
If an invalid instruction is sent (one not contained in Table 4: Instruction set), the device
automatically deselects itself.

Table 4. Instruction set

Instruction Description Instruction Format

WREN Write Enable 0000 X110(1)

WRDI Write Disable 0000 X100(1)
RDSR Read Status Register 0000 X101(1)
WRSR Write Status Register 0000 X001(1)
READ Read from Memory Array 0000 A8011(2)
WRITE Write to Memory Array 0000 A8010(2)
1. X = Don’t Care.
2. A8 = 1 for the upper half of the memory array of the M95040, and 0 for the lower half, and is
Don’t Care for other devices.

6.1 Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7: Write Enable (WREN) sequence, to send this instruction to the
device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on
Serial Data Input (D). The device then enters a wait state. It waits for a the device to be
deselected, by Chip Select (S) being driven high.

Figure 7. Write Enable (WREN) sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance
Q
AI01441D

16/39 DocID6512 Rev 11

M950x0-W M950x0-R Instructions

6.2 Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device. As shown in Figure 8: Write Disable (WRDI) sequence, to send this instruction
to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in,
on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be
deselected, by Chip Select (S) being driven high.
The Write Enable Latch (WEL) bit is reset by any of the following events:
• Power-up
• WRDI instruction execution
• WRSR instruction completion
• WRITE instruction completion
• Write Protect (W) line being held low.

Figure 8. Write Disable (WRDI) sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance
Q
AI03790D

DocID6512 Rev 11 17/39

Instructions M950x0-W M950x0-R

6.3 Read Status Register (RDSR)

The Read Status Register instruction is used to read the Status Register.
As shown in Figure 9, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte are then shifted in, on Serial Data Input (D). The current
state of the bits in the Status register is shifted out, on Serial Data Out (Q). The Read Cycle
is terminated by driving Chip Select (S) high.
The Status Register is always readable, even if a Write or Write Status Register cycle is in
progress. During a Write Status Register cycle, the values of the non-volatile bits (BP0,
BP1) become available when a new RDSR instruction is executed, after completion of the
Write cycle. On the other hand, the two read-only bits (Write Enable Latch (WEL), Write In
Progress (WIP)) are dynamically updated during the ongoing Write cycle.
It is possible to read the Status Register contents continuously, as described in Figure 9.
Bits b7, b6, b5 and b4 are always read as 1. The status and control bits of the Status register
are as follows:

Table 5. Status register format

b7 b0
1 1 1 1 BP1 BP0 WEL WIP

Block Protect bits

Write Enable Latch bit
Write In Progress bit

6.3.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.

6.3.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.

6.3.3 BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 3: Write-protected block size) becomes
protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set.

18/39 DocID6512 Rev 11

M950x0-W M950x0-R Instructions

Figure 9. Read Status Register (RDSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

Status Register Out Status Register Out

High Impedance
Q 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

AI01444D

DocID6512 Rev 11 19/39

Instructions M950x0-W M950x0-R

6.4 Write Status Register (WRSR)

A Write Status Register (WRSR) instruction allows new values to be written to the Status
register. Before it can be accepted, a Write Enable (WREN) instruction must previously have
been executed.
The WRSR instruction is entered by driving Chip Select (S) low, sending the instruction
code followed by the data byte on Serial Data input (D), and driving the Chip Select (S)
signal high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the WRSR instruction is not executed.
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed write cycle that takes tW to complete (as specified in Table 12: DC characteristics
(M950x0-W, device grade 6) to Table 15: AC characteristics (M950x0-R, device grade 6)).
The instruction sequence is shown in Figure 10: Write Status Register (WRSR) sequence.
While the Write Status Register cycle is in progress, the Status register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write
cycle tW, and, 0 when the write cycle is complete. The WEL bit (Write enable latch) is also
reset at the end of the write cycle tW.
The WRSR instruction allows the user to change the values of the BP1, BP0 bits which
define the size of the area that is to be treated as read only, as defined in Table 3: Write-
protected block size. The contents of the BP1, BP0 bits are updated after the completion of
the WRSR instruction, including the tW write cycle.
The WRSR instruction has no effect on the b7, b6, b5, b4, b1 and b0 bits in the Status
register which are always read as 0.

Figure 10. Write Status Register (WRSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction Status
Register In

D 7 6 5 4 3 2 1 0

High Impedance MSB

Q
AI01445B

The WRSR instruction is not accepted, and is not executed, under the following conditions:
• if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
• if a write cycle is already in progress
• if the device has not been deselected, by Chip Select (S) being driven high, after the
eighth bit, b0, of the data byte has been latched in
• if Write Protect (W) is low during the WRSR command (instruction, address and data)

20/39 DocID6512 Rev 11

M950x0-W M950x0-R Instructions

6.5 Read from Memory Array (READ)

As shown in Figure 11: Read from Memory Array (READ) sequence, to send this instruction
to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address
byte are then shifted in, on Serial Data Input (D). For the M95040, the most significant
address bit, A8, is incorporated as bit b3 of the instruction byte, as shown in Table 4:
Instruction set. The address is loaded into an internal address register, and the byte of data
at that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven low, an internal bit-pointer is automatically
incremented at each clock cycle, and the corresponding data bit is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

Table 6. Address range bits

Device M95040 M95020 M95010

Address Bits A8-A0 A7-A0 A6-A0

Figure 11. Read from Memory Array (READ) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Instruction Byte Address

D A8 A7 A6 A5 A4 A3 A2 A1 A0

Data Out
High Impedance
Q 7 6 5 4 3 2 1 0

AI01440E

1. Depending on the memory size, as shown in Table 6: Address range bits, the most significant address bits
are Don’t Care.

DocID6512 Rev 11 21/39

Instructions M950x0-W M950x0-R

6.6 Write to Memory Array (WRITE)

As shown in Figure 12: Byte Write (WRITE) sequence, to send this instruction to the device,
Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least
one data byte are then shifted in, on Serial Data input (D). The instruction is terminated by
driving Chip Select (S) high at a byte boundary of the input data. The self-timed Write cycle,
triggered by the rising edge of Chip Select (S), continues for a period tW (as specified in
Table 12: DC characteristics (M950x0-W, device grade 6) to Table 15: AC characteristics
(M950x0-R, device grade 6)). After this time, the Write in Progress (WIP) bit is reset to 0.
In the case of Figure 12: Byte Write (WRITE) sequence, Chip Select (S) is driven high after
the eighth bit of the data byte has been latched in, indicating that the instruction is being
used to write a single byte. If, though, Chip Select (S) continues to be driven low, as shown
in Figure 13: Page Write (WRITE) sequence, the next byte of input data is shifted in, so that
more than a single byte, starting from the given address towards the end of the same page,
can be written in a single internal Write cycle. If Chip Select (S) still continues to be driven
low, the next byte of input data is shifted in, and used to overwrite the byte at the start of the
current page.
The instruction is not accepted, and is not executed, under the following conditions:
• if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
• if a Write cycle is already in progress
• if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the rising edge of Serial Clock (C) that latches the last data bit, and
before the next rising edge of Serial Clock (C) occurs anywhere on the bus)
• if Write Protect (W) is low or if the addressed page is in the area protected by the Block
Protect (BP1 and BP0) bits
Note: The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit
is read as “0” and a programmed bit is read as “1”.

Figure 12. Byte Write (WRITE) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Instruction Byte Address Data Byte

D A8 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0

High Impedance
Q

AI01442D

1. Depending on the memory size, as shown in Table 6: Address range bits, the most significant address bits
are Don’t Care.

22/39 DocID6512 Rev 11

M950x0-W M950x0-R Instructions

Figure 13. Page Write (WRITE) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Instruction Byte Address Data Byte 1

D A8 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0 7

10+8N
11+8N
12+8N
13+8N
14+8N
15+8N
8+8N
9+8N

136
137
138
139
140
141
142
143
24 25 26 27 28 29 30 31

Data Byte 2 Data Byte N Data Byte 16

D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

AI01443D

1. Depending on the memory size, as shown in Table 6: Address range bits, the most significant address bits
are Don’t Care.

DocID6512 Rev 11 23/39

Power-up and delivery states M950x0-W M950x0-R

7 Power-up and delivery states

7.1 Power-up state

After Power-up, the device is in the following state:
• Low power Standby Power mode
• Deselected (after Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started)
• Not in Hold Condition
• Write Enable Latch (WEL) is reset to 0
• Write In Progress (WIP) is reset to 0
The BP1 and BP0 bits of the Status register are unchanged from the previous power-down
(they are non-volatile bits).

7.2 Initial delivery state

The device is delivered with the memory array set at all 1s (FFh).
The Block Protect (BP1 and BP0) bits are initialized to 0.

24/39 DocID6512 Rev 11

M950x0-W M950x0-R Maximum rating

8 Maximum rating

Stressing the device outside the ratings listed in Table 7: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these, or any other conditions outside those indicated in the operating sections of
this specification, is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Table 7. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

Ambient operating temperature –40 130 °C

TSTG Storage temperature –65 150 °C
TLEAD (1)
Lead temperature during soldering see note °C
VO Output voltage –0.50 VCC+0.6 V
VI Input voltage –0.50 VCC+1.0 V
IOL DC output current (Q = 0) - 5 mA
IIH DC output current (Q = 1) - 5 mA
VCC Supply voltage –0.50 6.5 V
VESD Electrostatic pulse (Human Body Model) voltage(2) - 4000 V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous
Substances (RoHS) 2011/65/EU.
2. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant
with JEDEC Std JESD22-A114, C1=100pF, R1=1500 Ω, R2=500 Ω).

DocID6512 Rev 11 25/39

DC and AC parameters M950x0-W M950x0-R

9 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.

Table 8. Operating conditions (M950x0-W)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 2.5 5.5 V

TA Ambient operating temperature (device grade 6) –40 85 °C

Table 9. Operating conditions (M950x0-R)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 1.8 5.5 V

TA Ambient operating temperature –40 85 °C

Table 10. AC test measurement conditions

Symbol Parameter Min. Max. Unit

CL Load capacitance 30 pF
Input rise and fall times - 50 ns
Input pulse voltages 0.2VCC to 0.8VCC V
Input and output timing reference voltages 0.3VCC to 0.7VCC V

Figure 14. AC test measurement I/O waveform(1)

Input Levels Input and Output
Timing Reference Levels
0.8VCC
0.7VCC

0.3VCC
0.2VCC
AI00825B

1. Output Hi-Z is defined as the point where data out is no longer driven.

Table 11. Capacitance (1)

Symbol Parameter Test condition Min. Max. Unit

COUT Output capacitance (Q) VOUT = 0 V - 8 pF

Input capacitance (D) VIN = 0 V - 8 pF
CIN
Input capacitance (other pins) VIN = 0 V - 6 pF
1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 5 MHz

26/39 DocID6512 Rev 11

M950x0-W M950x0-R DC and AC parameters

Table 12. DC characteristics (M950x0-W, device grade 6)

Symbol Parameter Test condition Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC - ±2 µA

ILO Output leakage current S = VCC, VOUT = VSS or VCC - ±2 µA
C = 0.1VCC/0.9VCC at 5 MHz,
ICC Supply current - 2 mA
VCC = 2.5 V, Q = open
Supply current S = VCC, VIN = VSS or VCC
ICC1 - 1 µA
(Standby Power mode) VCC = 2.5 V
VIL Input low voltage –0.45 0.3 VCC V
VIH Input high voltage 0.7 VCC VCC+1 V
VOL Output low voltage IOL = 1.5 mA, VCC = 2.5 V - 0.4 V
VOH Output high voltage IOH = –0.4 mA, VCC = 2.5 V 0.8 VCC - V
Internal reset threshold
VRES(1) 1.0 1.65 V
voltage
1. Characterized only, not 100% tested.

Table 13. DC characteristics (M950x0-R, device grade 6)

Symbol Parameter Test condition Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC - ±2 µA

Output leakage S = VCC, voltage applied on Q = VSS or
ILO - ±2 µA
current VCC
VCC = 2.5 V, C = 0.1 VCC or 0.9VCC,
- 3 mA
Supply current fC = 5 MHz, Q = open
ICCR
(Read) VCC = 1.8 V, C = 0.1VCC or 0.9VCC at
- 2 mA
max clock frequency, Q = open
VCC = 5.0 V, S = VCC, VIN = VSS or VCC - 2 µA
Supply current
ICC1 VCC = 2.5 V, S = VCC, VIN = VSS or VCC - 1 µA
(Standby)
VCC = 1.8 V, S = VCC, VIN = VSS or VCC - 1 µA
2.5 V < VCC < 5.5 V –0.45 0.3VCC V
VIL Input low voltage
1.8 V < VCC < 2.5 V –0.45 0.25VCC V
2.5 V < VCC < 5.5 V 0.7VCC VCC+1 V
VIH Input high voltage
1.8 V < VCC < 2.5 V 0.75VCC VCC+1 V
VCC = 2.5 V, IOL = 1.5 mA,
- 0.2VCC V
VOL Output low voltage or VCC = 5.5 V, IOL = 2 mA
VCC = 1.8 V, IOL = 0.15 mA - 0.3 V
VCC = 2.5 V, IOH = –0.4 mA,
VOH Output high voltage or VCC = 5.5 V, IOH = –2 mA, 0.8VCC - V
or VCC = 1.8 V, IOH = –0.1 mA
Internal reset
VRES(1) 1.0 1.65 V
threshold voltage
1. Characterized only, not 100% tested.

DocID6512 Rev 11 27/39

DC and AC parameters M950x0-W M950x0-R

Table 14. AC characteristics (M950x0-W, device grade 6)

Test conditions specified in Table 10 and Table 8

Symbol Alt. Parameter Min. Max. Unit

fC fSCK Clock frequency D.C. 10 MHz

tSLCH tCSS1 S active setup time 15 - ns
tSHCH tCSS2 S not active setup time 15 - ns
tSHSL tCS S deselect time 40 - ns
tCHSH tCSH S active hold time 25 - ns
tCHSL S not active hold time 15 - ns
tCH(1) tCLH Clock high time 40 - ns
(1)
tCL tCLL Clock low time 40 - ns
tCLCH(2) tRC Clock rise time - 1 µs
tCHCL(2) tFC Clock fall time - 1 µs
tDVCH tDSU Data in setup time 15 - ns
tCHDX tDH Data in hold time 15 - ns
tHHCH Clock low hold time after HOLD not active 15 - ns
tHLCH Clock low hold time after HOLD active 20 - ns
tCLHL Clock low setup time before HOLD active 0 - ns
tCLHH Clock low setup time before HOLD not active 0 - ns
(2)
tSHQZ tDIS Output disable time - 25 ns
tCLQV tV Clock low to output valid - 35 ns
tCLQX tHO Output hold time 0 - ns
tQLQH(2) tRO Output rise time - 20 ns
tQHQL (2) tFO Output fall time - 20 ns
tHHQV tLZ HOLD high to output valid - 25 ns
tHLQZ(2) tHZ HOLD low to output high-Z - 35 ns
tW tWC Write time - 5 ms
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not 100% tested in production.

28/39 DocID6512 Rev 11

M950x0-W M950x0-R DC and AC parameters

Table 15. AC characteristics (M950x0-R, device grade 6)

Test conditions specified in Table 10 and Table 9(1)

Symbol Alt. Parameter Min. Max. Unit

fC fSCK Clock frequency D.C. 5 MHz

tSLCH tCSS1 S active setup time 90 - ns
tSHCH tCSS2 S not active setup time 90 - ns
tSHSL tCS S deselect time 100 - ns
tCHSH tCSH S active hold time 90 - ns
tCHSL S not active hold time 90 - ns
tCH(2) tCLH Clock high time 90 - ns
(1)
tCL tCLL Clock low time 90 - ns
tCLCH(3) tRC Clock rise time - 1 µs
tCHCL(2) tFC Clock fall time - 1 µs
tDVCH tDSU Data in setup time 20 - ns
tCHDX tDH Data in hold time 30 - ns
tHHCH Clock low hold time after HOLD not active 70 - ns
tHLCH Clock low hold time after HOLD active 40 - ns
tCLHL Clock low setup time before HOLD active 0 - ns
tCLHH Clock low setup time before HOLD not active 0 - ns
(2)
tSHQZ tDIS Output disable time - 100 ns
tCLQV tV Clock low to output valid - 80 ns
tCLQX tHO Output hold time 0 - ns
tQLQH(2) tRO Output rise time - 50 ns
tQHQL (2) tFO Output fall time - 50 ns
tHHQV tLZ HOLD high to output valid - 50 ns
tHLQZ(2) tHZ HOLD low to output high-Z - 100 ns
tW tWC Write time - 5 ms
1. The test flow guarantees the AC parameter values defined in this table (when VCC = 1.8 V) and
the AC parameter values defined in Table 14: AC characteristics (M950x0-W, device grade 6)
(when VCC = 2.5 or when VCC = 5.0 V).
2. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
3. Value guaranteed by characterization, not 100% tested in production.

DocID6512 Rev 11 29/39

DC and AC parameters M950x0-W M950x0-R

Figure 15. Serial input timing

tSHSL

tCHSL tSLCH tCH tCHSH tSHCH

tDVCH tCHCL tCL tCLCH

tCHDX

D MSB IN LSB IN

High impedance
Q

AI01447d

Figure 16. Hold timing

tHLCH

tCLHL tHHCH

tCLHH

tHLQZ tHHQV

HOLD

AI01448c

30/39 DocID6512 Rev 11

M950x0-W M950x0-R DC and AC parameters

Figure 17. Serial output timing

tCH tSHSL

tCLQV tCLCH tCHCL tCL tSHQZ

tCLQX

tQLQH
tQHQL

ADDR
D LSB IN

AI01449f

DocID6512 Rev 11 31/39

Package mechanical data M950x0-W M950x0-R

10 Package mechanical data

In order to meet environmental requirements, ST offers the device in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 18. SO8N 8-lead plastic small outline 150 mils body width, package outline
h x 45°

A2 A
c
ccc
b
e

0.25 mm
D GAUGE PLANE

k
8

E1 E
1 L
A1
L1

SO-A

1. Drawing is not to scale.

Table 16. SO8N 8-lead plastic small outline, 150 mils body width, package
mechanical data
Millimeters Inches(1)
Symbol
Typ. Min. Max. Typ. Min. Max.

A - - 1.75 - - 0.0689
A1 - 0.1 0.25 - 0.0039 0.0098
A2 - 1.25 - - 0.0492 -
b - 0.28 0.48 - 0.011 0.0189
c - 0.17 0.23 - 0.0067 0.0091
ccc - - 0.1 - - 0.0039
D 4.9 4.8 5 0.1929 0.189 0.1969
E 6 5.8 6.2 0.2362 0.2283 0.2441
E1 3.9 3.8 4 0.1535 0.1496 0.1575
e 1.27 - - 0.05 - -
h - 0.25 0.5 - 0.0098 0.0197
k - 0° 8° - 0° 8°
L - 0.4 1.27 - 0.0157 0.05
L1 1.04 - - 0.0409 - -
1. Values in inches are converted from mm and rounded to 4 decimal digits.

32/39 DocID6512 Rev 11

M950x0-W M950x0-R Package mechanical data

Figure 19. TSSOP8 8-lead thin shrink small outline, package outline
D

8 5
c

E1 E

1 4

A1 L
A A2
CP L1

b e
TSSOP8AM

1. Drawing is not to scale.

Table 17. TSSOP8 8-lead thin shrink small outline, package mechanical data
Millimeters Inches(1)
Symbol
Typ. Min. Max. Typ. Min. Max.

A - - 1.2 - - 0.0472
A1 - 0.05 0.15 - 0.002 0.0059
A2 1 0.8 1.05 0.0394 0.0315 0.0413
b - 0.19 0.3 - 0.0075 0.0118
c - 0.09 0.2 - 0.0035 0.0079
CP - - 0.1 - - 0.0039
D 3 2.9 3.1 0.1181 0.1142 0.122
e 0.65 - - 0.0256 - -
E 6.4 6.2 6.6 0.252 0.2441 0.2598
E1 4.4 4.3 4.5 0.1732 0.1693 0.1772
L 0.6 0.45 0.75 0.0236 0.0177 0.0295
L1 1 - - 0.0394 - -
α - 0° 8° - 0° 8°
N (number of leads) 8 8
1. Values in inches are converted from mm and rounded to 4 decimal digits.

DocID6512 Rev 11 33/39

Package mechanical data M950x0-W M950x0-R

Figure 20. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, outline
D e b

L1
L3

Pin 1
E E2

K
L
A

D2
eee
A1 ZW_MEeV2

1. Drawing is not to scale.

2. The central pad (area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed
to be connected to any other voltage or signal line on the PCB, for example during the soldering process.
3. The circle in the top view of the package indicates the position of pin 1.

Table 18. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, data
Millimeters Inches(1)
Symbol
Typ. Min. Max. Typ. Min. Max.

A 0.550 0.450 0.600 0.0217 0.0177 0.0236

A1 0.020 0.000 0.050 0.0008 0.0000 0.0020
b 0.250 0.200 0.300 0.0098 0.0079 0.0118
D 2.000 1.900 2.100 0.0787 0.0748 0.0827
D2 (rev MC) - 1.200 1.600 - 0.0472 0.0630
E 3.000 2.900 3.100 0.1181 0.1142 0.1220
E2 (rev MC) - 1.200 1.600 - 0.0472 0.0630
e 0.500 - - 0.0197 - -
K (rev MC) - 0.300 - - 0.0118 -
L - 0.300 0.500 - 0.0118 0.0197
L1 - - 0.150 - - 0.0059
L3 - 0.300 - - 0.0118 -
(2)
eee - 0.080 - - 0.0031 -
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle
from measuring.

34/39 DocID6512 Rev 11

M950x0-W M950x0-R Part numbering

11 Part numbering

Table 19. Ordering information scheme

Example: M95040 – W MN 6 T P

Device type
M95 = SPI serial access EEPROM

Device function
040 = 4 Kbit (512 x 8)
020 = 2 Kbit (256 x 8)
010 = 1 Kbit (128 x 8)

Operating voltage
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V

Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MC = UFDFPN8 (MLP8) 2 × 3mm

Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow

Option
blank = Standard packing
T = Tape and reel packing

Plating technology
P or G = ECOPACK® (RoHS compliant)

DocID6512 Rev 11 35/39

Revision history M950x0-W M950x0-R

12 Revision history

Table 20. Document revision history

Date Version Changes

s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the Byte
10-May-2000 2.2
Write Operation
Human Body Model meets JEDEC std (Table 2). Minor adjustments to
Figs 7,9,10,11 & Tab 9. Wording changes, according to the standard
16-Mar-2001 2.3 glossary
Illustrations and Package Mechanical data updated
Temperature range ‘3’ added to the -W supply voltage range in DC and
19-Jul-2001 2.4
AC characteristics
11-Oct-2001 3.0 Document reformatted using the new template
26-Feb-2002 3.1 Description of chip deselect after 8th clock pulse made more explicit
Position of A8 in Read Instruction Sequence Figure corrected. Load
27-Sep-2002 3.2
Capacitance CL changed
24-Oct-2002 3.3 Minimum values for tCHHL and tCHHH changed.
Description of Read from Memory Array (READ) instruction corrected,
24-Feb-2003 3.4
and clarified
28-May-2003 3.5 New products, identified by the process letter W, added
Correction to current products, identified by the process letter K not L.
ICC changed in DC characteristics, and tCHHL, tCHHH substituted in AC
characteristics
25-Jun-2003 3.6
Voltage range -S upgraded by removing it, and adding the -R voltage
range in its place
Temperature range 5 removed.
21-Nov-2003 4.0 Table of contents, and Pb-free options added. VIL(min) improved to -0.45V
02-Feb-2004 4.1 VIL(max) and tCLQV(max) changed
Absolute Maximum Ratings for VIO(min) and VCC(min) improved.
Soldering temperature information clarified for RoHS compliant devices.
01-Mar-2004 5.0 New 5V and 2.5V devices, with process letter W, promoted from
preliminary data to full data. Device Grade 3 clarified, with reference to
HRCF and automotive environments
Product List summary table added. Process identification letter “G”
information added. Order information for Tape and Reel changed to T.
AEC-Q100-002 compliance. Device Grade information clarified. tHHQX
05-Oct-2004 6.0 corrected to tHHQV. Signal Description updated.
10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint
clarified

36/39 DocID6512 Rev 11

M950x0-W M950x0-R Revision history

Table 20. Document revision history

Date Version Changes

Document converted to new template, Table 5: Status register format

moved to below Section 6.3: Read Status Register (RDSR).
PDIP package removed. UFDFPN8 (MB) package added (see Figure 20
and Table 18) and SO8N package specifications updated (see Figure 18
and Table 16). Packages are ECOPACK® compliant.
Section 6.7: Cycling added. Section 2.8: Supply voltage (VCC) added and
information removed below Section 4: Operating features.
Figure 3: Bus master and memory devices on the SPI bus modified.
TLEAD parameter modified, Note 1 changed, and TA added to Table 7:
06-Nov-2006 7 Absolute maximum ratings.
Characteristics of previous product identified by process letter K removed.
CL modified in Table 10: AC test measurement conditions. Note removed
below Table 13.
Information in Table 13 is no longer Preliminary data, ICC, ICC1 and VIL
modified. End timing line of tSHQZ moved in Figure 17.
tCHHL and tCHHH changed to tCLHL and tCLHH, respectively in Figure 16,
Table 18, Table 17, Table 14, Table 19 and Table 15.
Plating technology and Process updated in Table 19: Ordering information
scheme.
Section 2.8: Supply voltage (VCC) updated.
Section 3: Connecting to the SPI bus modified.
Section 6.6: Write to Memory Array (WRITE) modified.
Device grade 6 removed in the 4.5 to 5.5 V VCC range (seeTable 8).
Table 13: DC characteristics (M950x0-R, device grade 6) modified.
Table 14: AC characteristics (M950x0-W, device grade 6) modified:
frequency changed from 5 MHz to 10 MHz.
20-Mar-2008 8 Table 15: AC characteristics (M950x0-R, device grade 6) modified:
frequency changed from 2 MHz to 5 MHz.
Section 10: Package mechanical data:
– Inches are calculated from millimeters and rounded to the third decimal
digit.
– UFDFPN8 package specifications modified.
Blank option removed below Plating technology in Table 19: Ordering
information scheme. Table 25, Table 26 and Table 27 added.
Section 2.8: Supply voltage (VCC) and Section 6.4: Write Status Register
(WRSR) updated.
Section 6.6: Write to Memory Array (WRITE) clarified.
IOL and IOH added to Table 7: Absolute maximum ratings.
VRES added to DC characteristics tables 13, 12, 15 and 13. tCLQV
modified in Figure 15: AC characteristics (M950x0-R, device grade 6).
24-Sep-2009 9 Note added to Table 15: AC characteristics (M950x0-R, device grade 6).
Figure 15: Serial input timing, Figure 16: Hold timing and Figure 17: Serial
output timing updated.
Note added below Figure 20: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch
dual flat package no lead 2 × 3mm, outline.
/W process option removed from Table 19: Ordering information scheme.
ECOPACK text updated. Small text changes.

DocID6512 Rev 11 37/39

Revision history M950x0-W M950x0-R

Table 20. Document revision history

Date Version Changes

Document renamed from “M95040 M95020 M95010” to “M950x0

M950x0-W M950x0-R”
Silhouette of UDFPN8 (MB or MC) on the cover page updated.
Section 6.3: Read Status Register (RDSR) updated.
Text modified in Section 6.3.1: WIP bit.
02-Feb-2012 10 Table 7: Absolute maximum ratings updated.
Figure 20: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package
no lead 2 × 3mm, outline modified.
Table 18: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package
no lead 2 × 3mm, data updated.
Removed tables of available products from Section 11: Part numbering.
Document renamed from “M95040 M95020 M95010” to “M950x0-W
M950x0-R”.
Silhouette of UDFPN8 (MB or MC) on the cover page updated.
Section 6.3: Read Status Register (RDSR) updated.
Text modified in Section 6.3.1: WIP bit.
Table 7: Absolute maximum ratings updated.
24-May-2013 11
Tables 8, 13, 15, 17, 19 removed.
Figure 20: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package
no lead 2 × 3mm, outline modified.
Table 18: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package
no lead 2 × 3mm, data updated.
Removed tables of available products from Section 11: Part numbering.

38/39 DocID6512 Rev 11

M950x0-W M950x0-R

Please Read Carefully:

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT AUTHORIZED FOR USE IN WEAPONS. NOR ARE ST PRODUCTS DESIGNED OR AUTHORIZED FOR USE
IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH
PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR
ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED
FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN
WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE,
AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS.
PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE
CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

DocID6512 Rev 11 39/39

PCN MMS-MMY/13/8165 - Dated 14 Oct 2013

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries(‘‘ST’’) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.

UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS ‘‘AUTOMOTIVE
GRADE’’ MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners

STMicroelectronics group of companies

® 192/192
Public Products List
®

PCN Title : M95010, M95020, M95040, M95080, M95160 1-Kbit, 2-Kbit, 4-Kbit, 8-Kbit, 16-Kbit SPI bus EEPROM / Industrial grade Redesign and
PCN Reference : MMS-MMY/13/8165
PCN Created on : 07-OCT-2013

Subject : Public Products List

Dear Customer,

Please find below the Standard Public Products List impacted by the change:

ST COMMERCIAL PRODUCT

M95010-RDW6TP M95010-RMN6TP M95010-WDW6TP

M95010-WMN6TP M95020-RDW6TP M95020-RMN6TP
M95020-WDW6TP M95020-WMN6TP M95040-RDW6TP
M95040-RMC6TG M95040-RMN6TP M95040-WDW6TP
M95040-WMN6TP M95080-RDW6TP M95080-RMC6TG
M95080-WDW6TP M95080-WMN6TP M95160-RDW6TP
M95160-RMC6TG M95160-RMN6TP M95160-WDW6TP
M95160-WMN6TP

1/1
Please Read Carefully:

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners

STMicroelectronics group of companies

PIC18F87K90
No ratings yet
PIC18F87K90
566 pages
Pic18f67k22 PDF
No ratings yet
Pic18f67k22 PDF
550 pages
Pic18F85J90 Family Data Sheet: 64/80-Pin, High-Performance Microcontrollers With LCD Driver and Nanowatt Technology
No ratings yet
Pic18F85J90 Family Data Sheet: 64/80-Pin, High-Performance Microcontrollers With LCD Driver and Nanowatt Technology
411 pages
Hoja de Datos Pic 16f877a Completo PDF
No ratings yet
Hoja de Datos Pic 16f877a Completo PDF
234 pages
PIC16F87XA Data Sheet: 28/40/44-Pin Enhanced Flash Microcontrollers
No ratings yet
PIC16F87XA Data Sheet: 28/40/44-Pin Enhanced Flash Microcontrollers
150 pages
Pic18f66k90t I PTRSL
No ratings yet
Pic18f66k90t I PTRSL
570 pages
MC9S08GT60ACFBE
No ratings yet
MC9S08GT60ACFBE
304 pages
PIC16F882/883/884/886/887
No ratings yet
PIC16F882/883/884/886/887
50 pages
Getting Started With Customization
No ratings yet
Getting Started With Customization
14 pages
PIC16F882/883/884/886/887 Data Sheet
No ratings yet
PIC16F882/883/884/886/887 Data Sheet
328 pages
PIC12F529T39A: 14-Pin, 8-Bit Flash Microcontroller
No ratings yet
PIC12F529T39A: 14-Pin, 8-Bit Flash Microcontroller
98 pages
Pic16F883/884/886/887 Data Sheet: 28/40/44-Pin Enhanced Flash-Based, 8-Bit Cmos Microcontrollers With Nanowatt Technology
No ratings yet
Pic16F883/884/886/887 Data Sheet: 28/40/44-Pin Enhanced Flash-Based, 8-Bit Cmos Microcontrollers With Nanowatt Technology
288 pages
Sprs 523 K
No ratings yet
Sprs 523 K
138 pages
PIC16F887
No ratings yet
PIC16F887
328 pages
MSM8909 MSM8609 MSM8209 MSM8208 Hardware Migration Guide
No ratings yet
MSM8909 MSM8609 MSM8209 MSM8208 Hardware Migration Guide
37 pages
PIC18F2455/2550/4455/4550 Data Sheet
No ratings yet
PIC18F2455/2550/4455/4550 Data Sheet
110 pages
MC9S08JM16 PDF
No ratings yet
MC9S08JM16 PDF
388 pages
Datasheet 16F887
No ratings yet
Datasheet 16F887
288 pages
Features: CMOS 16-Bit Microprocessor
No ratings yet
Features: CMOS 16-Bit Microprocessor
39 pages
PIC16F87XA Data Sheet: 28/40-Pin Enhanced FLASH Microcontrollers
No ratings yet
PIC16F87XA Data Sheet: 28/40-Pin Enhanced FLASH Microcontrollers
222 pages
PIC16F887
No ratings yet
PIC16F887
288 pages
Emerging ICT Technologies and Cybersecurity: Kutub Thakur Al-Sakib Khan Pathan Sadia Ismat
No ratings yet
Emerging ICT Technologies and Cybersecurity: Kutub Thakur Al-Sakib Khan Pathan Sadia Ismat
291 pages
Pic 16f877a Microcontroller
No ratings yet
Pic 16f877a Microcontroller
222 pages
PIC18F4321
No ratings yet
PIC18F4321
402 pages
ReactJS PDF
No ratings yet
ReactJS PDF
403 pages
DS02 PDF
No ratings yet
DS02 PDF
224 pages
MC9S08JM60 PDF
No ratings yet
MC9S08JM60 PDF
390 pages
Universal Serial Bus Micro-USB Cables and Connectors Specification
No ratings yet
Universal Serial Bus Micro-USB Cables and Connectors Specification
36 pages
PIC 16f877a Data Sheet
No ratings yet
PIC 16f877a Data Sheet
321 pages
Datasheet
No ratings yet
Datasheet
19 pages
STC8H1K08 Features
No ratings yet
STC8H1K08 Features
10 pages
PIC16F87XA Data Sheet: 28/40/44-Pin Enhanced Flash Microcontrollers
No ratings yet
PIC16F87XA Data Sheet: 28/40/44-Pin Enhanced Flash Microcontrollers
5 pages
Mrf89Xam8A Data Sheet: 868 MHZ Ultra-Low Power Sub-Ghz Transceiver Module
No ratings yet
Mrf89Xam8A Data Sheet: 868 MHZ Ultra-Low Power Sub-Ghz Transceiver Module
34 pages
PIC16F882/883/884/886/887 Data Sheet
No ratings yet
PIC16F882/883/884/886/887 Data Sheet
22 pages
R2023-AIML-Curriculum and Syllabus
No ratings yet
R2023-AIML-Curriculum and Syllabus
59 pages
Product/Process Change Notification: PCN MPG-EEP/04/578
No ratings yet
Product/Process Change Notification: PCN MPG-EEP/04/578
7 pages
CMOS Priority Interrupt Controller: Features
No ratings yet
CMOS Priority Interrupt Controller: Features
24 pages
Hydro (1) (1) 1
No ratings yet
Hydro (1) (1) 1
47 pages
868Mhz +10dbm MRF89XAM8A Modul Microchip 70651A
No ratings yet
868Mhz +10dbm MRF89XAM8A Modul Microchip 70651A
34 pages
TELSMITH Rotary Drum Scrubber New
100% (4)
TELSMITH Rotary Drum Scrubber New
7 pages
Natural Science and History Museum
No ratings yet
Natural Science and History Museum
24 pages
MB90F546GS Datasheet
No ratings yet
MB90F546GS Datasheet
67 pages
PIC18F2585/2680/4585/4680 Data Sheet
No ratings yet
PIC18F2585/2680/4585/4680 Data Sheet
18 pages
16F87x-16F87xA MIGRATION
No ratings yet
16F87x-16F87xA MIGRATION
4 pages
Syncmos Technologies Inc. Sm8951A/8952A
No ratings yet
Syncmos Technologies Inc. Sm8951A/8952A
17 pages
MB89635R
No ratings yet
MB89635R
59 pages
PIC16F627
No ratings yet
PIC16F627
6 pages
LM Chart Cast Alloys Aluminum
0% (1)
LM Chart Cast Alloys Aluminum
2 pages
Compliance Under Case-B'.: Notes
No ratings yet
Compliance Under Case-B'.: Notes
10 pages
Filmdropwise
No ratings yet
Filmdropwise
26 pages
21 22
No ratings yet
21 22
14 pages
Macine Design
No ratings yet
Macine Design
40 pages
Characteristics of P-Channel SOI LDMOS Transistor With Tapered Field Oxides
No ratings yet
Characteristics of P-Channel SOI LDMOS Transistor With Tapered Field Oxides
7 pages
Activo PD503 004
No ratings yet
Activo PD503 004
4 pages
Serial EEPROM Cross Reference Guide
No ratings yet
Serial EEPROM Cross Reference Guide
6 pages
Mescab Catalogue - Compressed
No ratings yet
Mescab Catalogue - Compressed
7 pages
InDesign 100 Real Shortcuts Hinglish
No ratings yet
InDesign 100 Real Shortcuts Hinglish
3 pages
Building Mental Models
No ratings yet
Building Mental Models
32 pages
Realtime Festival Overview
No ratings yet
Realtime Festival Overview
28 pages
PCworth Product Pricelist
No ratings yet
PCworth Product Pricelist
22 pages
Running Head: DATA STRUCTURES 1: Course: Project Name: Student Name: Date
No ratings yet
Running Head: DATA STRUCTURES 1: Course: Project Name: Student Name: Date
7 pages
Option 1 Project Management Issues and Concerns About The Project Timeline
No ratings yet
Option 1 Project Management Issues and Concerns About The Project Timeline
8 pages
Swe-Spp-001-P-Dc-061 - DC String Cable Sizing - R3
No ratings yet
Swe-Spp-001-P-Dc-061 - DC String Cable Sizing - R3
9 pages
6 BSTs and AVL Trees
No ratings yet
6 BSTs and AVL Trees
12 pages
Handwriting Recognition Software
No ratings yet
Handwriting Recognition Software
10 pages
Database Administration Level IV Theory Exam 6
No ratings yet
Database Administration Level IV Theory Exam 6
5 pages
3.1 Critical Thinking Rubric
No ratings yet
3.1 Critical Thinking Rubric
1 page
Bcs-41 Jadi Buti
No ratings yet
Bcs-41 Jadi Buti
3 pages
JP-Finance Officer
No ratings yet
JP-Finance Officer
2 pages
Sai Kumar Modified Resume
No ratings yet
Sai Kumar Modified Resume
1 page
Motioneering - Damping Solutions
No ratings yet
Motioneering - Damping Solutions
1 page

STMicroelectronics 8165

Uploaded by

STMicroelectronics 8165

Uploaded by

PRODUCT/PROCESS

M95010, M95020, M95040, M95080, M95160 1-Kbit, 2-Kbit,

Table 1. Change Implementation Schedule

Forecasted availability date of samples 07-Oct-2013

Forecasted date for STMicroelectronics

Estimated date of changed product first 13-Jan-2014

Table 2. Change Identification

Type of change Waferfab technology change

Reason for change Line up to state-of-the-art of process

Change Product Identification Proc. techno identifier "K" for SO8N

Leduc, Hubert Marketing Manager

Rodrigues, Benoit Product Manager

Pavano, Rita Q.A. Manager

M95010, M95020, M95040, M95080, M95160

What is the change?

This upgraded version in CMOSF8H allows offering:

Differences from current datasheets:

How will the change be qualified?

What is the impact of the change?

- Form: Marking change (see Device marking paragraph)

- Function: DC characteristic: ICC1 standby supply current:

How can the change be seen?

- BOX LABEL MARKING

Example for M95080-WMN6TP

Manufactured under patents or patents pending

PBT: 260 °C Category: e4 ECOPACK2/ROHS

Trace Codes PPYWWLLL WX TF

Please provide the bulk ID for any inquiry

How can the change be seen?

SO8N 95080WP 95080WP

TSSOP8 O 508WK O 508WP

UFDFPN8 O 5DRK O 516R

Appendix A- Product Change Information

Type of change: Wafer fab process technology change

Reason for the change: Line up to state-of-the-art of process

Description of the change: Redesign and upgrade to the new CMOSF8H

Forecast date for the internal

The Qualification report QRMMY1324 for

Marking to identify the changed product: Process Technology identifier “K”

Manufacturing location: Rousset 8 inch wafer fab

Estimated date of first shipment: Week 02 / 2014

Appendix B: Concerned Commercial Part Numbers:

Commercial Package Samples

Appendix C: Qualification Reports:

See following pages

Table 1. Product information

Table 2. Package description

ST Shenzhen, China ST Shenzhen, China

UFDFPN8 (MLP8) ST Calamba, Philippines ST Calamba, Philippines

Reliability / Qualification assessment: PASS

September 2013 Rev 1 1/13

1 Reliability evaluation overview

3 Reliability test results

Table 3. Product vehicles used for die qualification

Table 4. Product vehicles used for package qualification

M95020 / SO8N ST Shenzhen

3.1 Reliability test plan and result summary

Results fail / sample size

High temperature operating life after endurance

Results fail / sample size

High temperature storage life

LU AEC-Q100- Class II Class II Class II

Results fail / sample size

Preconditioning: moisture sensitivity level 1

ELFR Early life failure rate

Results fail / sample size

Preconditioning: moisture sensitivity level 1

ELFR Early life failure rate

Results fail / sample size

Preconditioning: moisture sensitivity level 1

THB 168 hrs 0/80 0/80 0/80 -

HTSL 168 hrs 0/80 0/80 0/80 -

4 Applicable and reference documents

• AEC-Q100: Stress test qualification for integrated circuits

Table 9. List of terms

EDR NVM endurance, data retention and operational life