ECED3204: Microprocessor

Part III--Clock, I/O and Interrupt

Jason J. Gu
Department of Electrical and Computer Engineering
Dalhousie University

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 Outline

i. Part III.1 System Clock Configuration

ii. Part III.2 Parallel I/O
iii. Part III.3 Interrupt Handling, Resets,
and Power Management
iv. Part III.4 Advanced Parallel I/O

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Part III.1 System Clock Configuration

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 Outline

i. Overview of System Clock Generation

ii. The Clock System of the AVR Mega Devices
iii. System Clock Prescaler

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 Overview of System Clock Generation

 Clock signal
 Time delays are dependent on accurate system clock
frequency
 MCU includes complex circuitry that generates and
distributes clock signals to every peripheral module
 Devices used to generate clock signal: ceramic
resonators, crystal oscillators, and RC circuits
 Frequency division: using count down counter
 Frequency multiplication: phase lock loop (PLL)

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 The Clock System of the AVR Mega Devices
 Clock distribution of AVR Mega devices:
illustrated in Figure

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 Clock Distribution of AVR Mega Devices
(cont’d.)
 CPU clock(clk_CPU): used with AVR core operation
 I/O clock(clk_I/o): used with I/O modules
 Flash clock(clk_FLASH): controls flash memory
interface
 Asynchronous clock (clk_ASY): allows asynchronous
timer/counter to be clocked directly from an external
clock or an external 32 kHz clock crystal
 ADC (clk_ADC) clock: provides an operation clock
required by the ADC module

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The Clock System of the AVR Mega
Devices (cont’d.)

Table 7.1 Mega device clocking options select

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The Clock System of the AVR Mega
Devices (cont’d.)

 Default clock source: calibrated internal RC

oscillator
 1.0 MHz system clock
 External clock: used to generate clock signals
required by all the modules
 Square wave with stable frequency
 When as external clock source is used, it is
connected to XTAL1, XTAL2 is unconnected.

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The Clock System of the AVR Mega Devices
(cont’d.)
 Watchdog oscillator: circuit used to detect
software errors; derived from the on-chip 128
kHz RC oscillator
 Low-frequency oscillator: 32.768 kHz watch
oscillator that can serve as the clock source
 The crystal should be connected as shown in
figure

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 The Clock System of the AVR Mega
Devices (cont’d.)
 Timer/counter oscillator: can be operated from an
external 32.768 kHz watch crystal or an external
clock source
 System clock prescaler
 Clock source selected by the clock multiplexer: further
divided by the system clock prescaler

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 System Clock Prescaler (cont’d.)
 Possible prescaling factor: chosen by the CLKPR register
 CKDIV8 fuse determines the initial value of the CLKPS bits
 CKDIV8 unprogrammed, CLKPS=0000, otherwise 0011
 CKDIV8 : can be programmed using AVR Studio IDE

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Part III.2 Parallel I/O

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 Outline

i. Introduction to I/O PORTs

ii. I/O Pin Driving Circuit Structure
iii. Electrical Characteristic Consideration for I/O
Interfacing
iv. Overview of the AVR Mega Parallel PORTs
v. Simple I/O Devices
vi. Interfacing with a D/A Converter

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 I/O Introduction to I/O PORTs

 I/O Port: consists of a group of pins and a set of

registers including data registers (or latch), data
direction register, and control register(s)
(optional)
 I/O addressing issue: shared or distinct from
memory components
 Address space: currently I/O devices and memory
components share the same address space.
 Addressing modes and instructions

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 I/O Introduction to I/O PORTs

AVR Mega devices have dedicated I/O space that

contains 64 locations from 0x20 to 0x5F
using following instructions:

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 I/O Introduction to I/O PORTs

AVR Mega640 has more than 64 I/O

An extended I/O space from 0x60 to 0x1FF is
added. only accessed using LD/LDS/LDD and
ST/STS/STD

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 I/O Introduction to I/O PORTs (cont’d.)

 I/O synchronization: communication with

peripheral devices via interface chips
 Synchronization between the processor and the
interface chip
 Synchronization between interface chip and peripheral
devices
 Synchronization issue for parallel PORTs
 Not an issue for today’s microcontrollers

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 I/O Introduction to I/O PORTs (cont’d.)

 Synchronization issue for serial interface

 Polling or the interrupt method used to make sure that
the new I/O operation can be started
 Achieved by following certain data transfer protocols
 USART,SPI,I2C, will be covered later.

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 I/O Pin Driving Circuit Structure
 Totem pole: pin is driven high or low, according
to the corresponding bit setting in the OUT
register
 Totem pole
with pull-down
 Totem pole
with pull-up

Figure 8.1 Totem pole block diagram

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I/O Pin Driving Circuit Structure

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I/O Pin Driving Circuit Structure (cont’d.)
 Bus keeper
 Pin is kept at its logic level when the pin is no
longer driven to any logic state

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 I/O Pin Driving Circuit Structure (cont’d.)
 Wired-OR
 Pin is driven high when the corresponding bit in the OUT
register is written to 1
 When OUT register is set to 0, corresponding pin is not
driven and can be pulled low with the internal or an external
pull-resistor

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 I/O Pin Driving Circuit Structure (cont’d.)
 Wired-AND
 Pin is driven low when the corresponding bit in the OUT
register is written to 0
 When OUTn is set to 1, the Pn pin is released, allowing the
pin to be pulled high

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 Electrical Characteristic Consideration for
I/O Interfacing
 Voltage-level compatibility: due to differing IC
technologies
 Input high voltage (VIH)
 Input low voltage (VIL)
 Output high voltage (VOH)
 Output low voltage (VOL)
 For X to drive Y
 VOHX>=VIHY
 VOLX<=VILY

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Electrical Characteristic Consideration for
I/O Interfacing

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 Electrical Characteristic Consideration for
I/O Interfacing (cont’d.)

 Current drive capability

 Whether the microcontroller can supply (when the
output voltage is high, also called source) or sink
(when the output voltage is low) the current needed by
the I/O devices that it interfaces with
 Input high current (IIH), flowing in, input V high
 Input low current (IIL), flowing out, input V low
 Output high current (IOH), flowing out, output V high
 Output low current (IOL), flowing in, output V low

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 Electrical Characteristic Consideration for
I/O Interfacing (cont’d.)
 Timing compatibility
 Main consideration is that the setup- and hold-time
requirements for all latches and flip-flops in a digital
system must be satisfied

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 Overview of the AVR Mega Parallel
PORTs

 AVR Mega MCU may have 11 parallel ports

 Note: No PORT I

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 Overview of the AVR Mega Parallel
PORTs
 Configuring the mega I/O pins
 DDxn bit in the DDRx register selects the direction of
the Pxn pin
 Toggling the mega I/O pin
 SBI instruction can be used to perform this operation

Input register PINx

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 Overview of the AVR Mega Parallel
PORTs

 example: Instruction sequence to output the

value 0x53 to Port A.
ldi r16,0xFF ; configure Port A for output
out DDRA,r16 ; “
ldi r16,0x53 ; output the value of 0x53 to Port A
out PORTA,r16; “

// C code
DDRA = 0xFF; configure Port A for output
PORTA = 0x53; output the value of 0x53 to Port A

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 Overview of the AVR Mega Parallel
PORTs (cont’d.)

 Reading the pin value

 PORT pin can be read through the PINxn bit of the
PINx register
 Unconnected pins
 Simplest method to ensure a defined level of an
unused pin is to enable the internal pull-up
 Alternate PORT functions
 Refer to Tables 8.4 through 8.15

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 Overview of the AVR Mega Parallel
PORTs

 example: Instruction sequence to input the

value to Port A, store in r20
ldi r16,0x00 ; configure Port A for input
out DDRA,r16 ; “
in r20, PINA ; input the value from port A to r20

// C code
DDRA = 0x00; configure Port A for input
r20 = PINA; input the value from port A to r20

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 Overview of the AVR Mega Parallel
PORTs (cont’d.)
 Alternate PORT functions
 Refer to Tables 8.4 through 8.14

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 Overview of the AVR Mega Parallel
PORTs (cont’d.)
 Alternate PORT functions
 Refer to Tables 8.4 through 8.14

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 Overview of the AVR Mega Parallel
PORTs (cont’d.)
 Alternate PORT functions
 Refer to Tables 8.4 through 8.14

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 Overview of the AVR Mega Parallel
PORTs (cont’d.)
 Alternate PORT functions
 Refer to Tables 8.4 through 8.14

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 Overview of the AVR Mega Parallel
PORTs (cont’d.)
 Alternate PORT functions
 Refer to Tables 8.4 through 8.14

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 Overview of the AVR Mega Parallel
PORTs (cont’d.)
 Alternate PORT functions
 Refer to Tables 8.4 through 8.14

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 Overview of the AVR Mega Parallel
PORTs (cont’d.)
 Alternate PORT functions
 Refer to Tables 8.4 through 8.14

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 Overview of the AVR Mega Parallel
PORTs (cont’d.)
 Alternate PORT functions
 Refer to Tables 8.4 through 8.14

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 Overview of the AVR Mega Parallel
PORTs (cont’d.)
 Alternate PORT functions
 Refer to Tables 8.4 through 8.14

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 Overview of the AVR Mega Parallel
PORTs (cont’d.)
 Alternate PORT functions
 Refer to Tables 8.4 through 8.14

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 Overview of the AVR Mega Parallel
PORTs (cont’d.)
 Alternate PORT functions
 Refer to Tables 8.4 through 8.14

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Overview of the AVR Mega Parallel
PORTs (cont’d.)

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 Simple I/O Devices
 Interfacing with LEDs: indicates the system
operation mode

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 Simple I/O Devices
 Interfacing with LEDs: indicates the system
operation mode
 example: flash all led for every 500ms
#include <avr/io.h>
#include <util/delay.h>
int main(void)
{
DDRK = 0XFF<<0;

while(1)
{
PORTK = 0x00;
_delay_ms(500);
PORTK = 0xFF;
_delay_ms(500);
}
}

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 Simple I/O Devices
 Interfacing with seven-segment displays: used
for decimal digits and a small subset of letters

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 Simple I/O Devices
 Interfacing with seven-segment displays:
decoder

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 Simple I/O Devices
 Interfacing with seven-segment displays: used
for decimal digits and a small subset of letters
 Display #5 to 0 following
pattern for 600ms
repeated:
 123456
 234567
 345678
 456789
 567890
 678901
 789012
 890123
 901234
 012345

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Seven Segment Display Example
.include "atxmega128A1def.inc"
.def rowCnt = r26
.def digCnt = r27
.def repCnt = r28
.cseg
.org 0x00
rjmp start
.org 0xF6
start: ldi r16,low(RAMEND)
out CPU_SPL,r16 ; SPL for MEGA
ldi r16,high(RAMEND)
out CPU_SPH,r16 ; SPH for MEGA
call setCPUClkto32Mwith16MCrystal
ldi r16, 0xFF
sts PORTA_DIR, r16
sts PORTB_DIR,r16
forever: ldi ZL,low(segTable << 1)
ldi ZH,high(segTable << 1)
ldi rowCnt,10 ; there are ten rows in segTable
rowLp: ldi repCnt,100 ; a row in segTable must be repeated for 100 times
repLp: ldi digCnt,6 ; each row has six digits

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Seven Segment Display Example

digLp: lpm r16,z+

sts PORTA_OUT,r16 ; output segment pattern
lpm r16,z+
sts PORTB_OUT,r16 ; output digit select
ldi r16,1
call delayby1ms
dec digCnt
brne digLp ; reach the end of a sequence?
subi ZL,12 ; reset segment pattern pointer to the start of a sequence
sbci ZH,0 ; "
dec repCnt ; repeat 100 times?
brne repLp
dec rowCnt
brne rowLp
jmp forever

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Seven Segment Display Example

. segTable: .db 0x30,0xDF,0x6D,0xEF,0x79,0xF7,0x33,0xFB,0x5B,0xFD,0x5F,0xFE

.db 0x6D,0xDF,0x79,0xEF,0x33,0xF7,0x5B,0xFB,0x5F,0xFD,0x70,0xFE
.db 0x79,0xDF,0x33,0xEF,0x5B,0xF7,0x5F,0xFB,0x70,0xFD,0x7F,0xFE
.db 0x33,0xDF,0x5B,0xEF,0x5F,0xF7,0x70,0xFB,0x7F,0xFD,0x7B,0xFE
.db 0x5B,0xDF,0x5F,0xEF,0x70,0xF7,0x7F,0xFB,0x7B,0xFD,0x7E,0xFE
.db 0x5F,0xDF,0x70,0xEF,0x7F,0xF7,0x7B,0xFB,0x7E,0xFD,0x30,0xFE
.db 0x70,0xDF,0x7F,0xEF,0x7B,0xF7,0x7E,0xFB,0x30,0xFD,0x6D,0xFE
.db 0x7F,0xDF,0x7B,0xEF,0x7E,0xF7,0x30,0xFB,0x6D,0xFD,0x79,0xFE
.db 0x7B,0xDF,0x7E,0xEF,0x30,0xF7,0x6D,0xFB,0x79,0xFD,0x33,0xFE
.db 0x7E,0xDF,0x30,0xEF,0x6D,0xF7,0x79,0xFB,0x33,0xFD,0x5B,0xFE
.include "sysClock_xmega.asm"
.include "delays_xmega.asm"

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Seven Segment Display Example

The C language version of the program is as follows:

#include <avr/io.h>
#include "delays_xmega.h"
#include "sysClock_xmega.h"
#define ROWS 10
#define REPCNT 100
#define DIGITS 6
unsigned char segTable[10][12] = {
{0x30,0xDF,0x6D,0xEF,0x79,0xF7,0x33,0xFB,0x5B,0xFD,0x5F,0xFE},
{0x6D,0xDF,0x79,0xEF,0x33,0xF7,0x5B,0xFB,0x5F,0xFD,0x70,0xFE},

{0x79,0xDF,0x33,0xEF,0x5B,0xF7,0x5F,0xFB,0x70,0xFD,0x7F,0xFE},
{0x33,0xDF,0x5B,0xEF,0x5F,0xF7,0x70,0xFB,0x7F,0xFD,0x7B,0xFE},
{0x5B,0xDF,0x5F,0xEF,0x70,0xF7,0x7F,0xFB,0x7B,0xFD,0x7E,0xFE},
{0x5F,0xDF,0x70,0xEF,0x7F,0xF7,0x7B,0xFB,0x7E,0xFD,0x30,0xFE},
{0x70,0xDF,0x7F,0xEF,0x7B,0xF7,0x7E,0xFB,0x30,0xFD,0x6D,0xFE},
{0x7F,0xDF,0x7B,0xEF,0x7E,0xF7,0x30,0xFB,0x6D,0xFD,0x79,0xFE},
{0x7B,0xDF,0x7E,0xEF,0x30,0xF7,0x6D,0xFB,0x79,0xFD,0x33,0xFE},
{0x7E,0xDF,0x30,0xEF,0x6D,0xF7,0x79,0xFB,0x33,0xFD,0x5B,0xFE}
};

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Seven Segment Display Example

int main(void)
{
unsigned char k1, k2, k3;
setCPUClkto32Mwith16MCrystal();
PORTA_DIR = 0xFF; // configure Port A for output , PORTA= 0xFF for MEGA
PORTB_DIR = 0xFF; // configure Port B for output to drive digit select
while(1) {
for(k1 = 0; k1 < ROWS; k1++)
for(k2 = 0; k2 < REPCNT; k2++)
for(k3 = 0; k3 < DIGITS; k3++) {
PORTA_OUT = segTable[k1][k3*2];
PORTB_OUT = segTable[k1][k3*2+1];
delayby1ms(1);
}
}
}

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 Simple I/O Devices (cont’d.)

 Generating a digital waveform using an I/O pin:

I/O voltage level manipulated and an appropriate
delay (equal to half of the waveform period)
inserted between the two voltage levels
 Making a sound using an I/O pin
 Create a frequency in audible range with pin
connected to a speaker

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Simple I/O Devices (cont’d.)
 Interfacing with DIP switches: INPUT

// code for MEGA

ldi r16,0x00 ; input
out DDRJ,r16 ; “
in r20, PINJ ;to r20
// C code for MEGA
DDRJ = 0x00; for input
r20 = PINJ;to r20

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Interfacing with a D/A Converter

 Important DAC characteristics

 Resolution
 Conversion time
 Number of channels
 Input format

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 Interfacing with a D/A Converter
 The AD7302 DAC: dual-channel, 8-bit, DAC chip
from Analog Devices that has a parallel interface
with the microcontroller

Vout=2*VREF*N/255

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 Interfacing with a D/A Converter (cont’d.)

Figure 8.22 Circuit connection between the AD7302 and the Mega2560

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 D/A Converter example

 Use figure 8.22 assembly program to generate a

triangular wave from VoutA pin and sine wave
from the VoutB pin, assuming that the
MEGA2560 is running with an 8 MHz crystal
oscillator. Divide both waveforms into 50 points
per period

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 D/A Converter example

Solution: To divide 360 into 50 points, then the sine waveform starts
from 0o to 352.8o and repeats. Since there is no negative value in the
sine waveform, we need to use the following equation to calculate
the voltage corresponding to xo:
Voltage= 5/2 * [sine(x) + 1]
To generate this voltage, we need to send the following value to the
DAC:
N = (sine x + 1) * 255 / 2
For example, we need to send 127 (or 128) to DAC to generate the
sine wave value at 0o.

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D/A Converter example
.include <m2560def.inc>
.def lpCnt = r26
.equ NN = 100
.cseg
.org 0x00
rjmp start
.org 0xF6
start: ldi r16,low(RAMEND)
out SPL,r16
ldi r16,high(RAMEND)
out SPH,r16
ldi r16,0xFF ; configure PORTA for output
sts DDRA,r16 ; "
sts DDRB,r16 ; configure PORTB for output
forever: ldi ZL,low(waveforms << 1) ; use Z as a pointer to the table
ldi ZH,high(waveforms << 1) ; "
ldi lpCnt,NN

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D/A Converter example

loop: cbi PORTB,1 ; select channel A

cbi PORTB,0 ; enable data write to DAC
lpm r16,Z+ ; output data to be converted to voltage
out PORTA,r16 ; "
sbi PORTB,0 ; pull WR high to start DAC
sbi PORTB,1 ; select channel B
cbi PORTB,0 ; enable data write to DAC
lpm r16,Z+ ; output data to be converted to voltage
out PORTA,r16 ; "
sbi PORTB,0 ; start DAC
nop ; insert time to allow DAC complete
nop ; conversion
nop
nop
dec lpCnt ; reach the end of waveform table?
brne loop
rjmp forever

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D/A Converter example

; -------------------------------------------------------------------------------------------------------------------
; Values to generate the triangular and sine waves are stored alternately in the same
; table to simplify data access.
; -------------------------------------------------------------------------------------------------------------------
waveforms:
.db 0,128,10,143,20,159,31,174,41,189,51,202,61,215,71,226,82,235,92,243
.db 102,249,112,253,122,255,133,255,143,253,153,249,163,243,173,235
.db 184,226,194,215,204,202,214,189,224,174,235,159,245,143,255,128
.db 245,112,235,96,224,81,214,66,204,53,194,40,184,29,173,20,163,12,153,6
.db 143,2,133,0,122,0,112,2,102,6,92,12,82,20,71,29,61,40,51,53
.db 41,66,31,81,20,96,10,112

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Part III.3 Interrupt Handling, Resets,
and Power Management

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 Outline

i. Basic Concepts on Interrupt

ii. Resets
iii. The AVR Mega Interrupts
iv. AVR Mega Reset
v. AVR Mega Watchdog Timer
vi. Power Management and Sleep Modes

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 Basic Concepts on Interrupt

 Interrupt: asynchronous signal indicating the

need for attention, or a synchronous event in
software indicating the need for a change in
execution
 Hardware interrupt: state of execution saved;
execution of an interrupt handler (interrupt service
routine) begins
 Software interrupt: implemented as instructions in the
instruction set

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 Basic Concepts on Interrupt (cont’d.)

 Why interrupt is useful

 I/O operations
 Example: polling to determine data availability for data in or
data out, CPU time is wasted. Using interrupt can prevent that
 Routine tasks
 Example: updating/redisplaying time of day, using timer
interrupts.
 Response to emergent events
 Examples: fire alarm, power failure, or overheat

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 Basic Concepts on Interrupt (cont’d.)
 Enabling and disabling interrupts
 Maskable interrupt (can be disabled) vs. nonmaskable interrupt
 Prioritizing multiple interrupts: how to handle several
interrupts pending at same time
 Servicing the interrupt
 CPU executes interrupt service routine and then
resumes the interrupted program
 note:
 The last instruction of an interrupt service routine must be
return from interrupt (RETI)

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 Basic Concepts on Interrupt (cont’d.)

 The interrupt vector: starting address of the

interrupt service routine
 Stored in a fixed location in the interrupt vector table
 Writing an Interrupt-driven program
 Step 1: Initialization of interrupt vector table (no need
for MEGA MCU)
 Step 2: Write the service routine
 Step 3: Enable interrupts

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 Resets

 Power-up reset: all critical registers, the program

counters, and flip-flops are forced to a default value
 Other reset sources: manual reset, brown-out reset,
watchdog reset, clock monitor reset, software reset, etc.

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 The AVR Mega Interrupts

 Categories of interrupt sources

 Internal peripheral interrupts
 External pin interrupts (INT0-INT7)
 Pin change interrupts (PCINT0-PCINT2)
 AVR Mega device interrupt vectors
 ATMega640/1280/2560: 100-pin Mega devices
 See Table 9.1

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The AVR Mega Interrupts

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The AVR Mega Interrupts

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The AVR Mega Reset and Interrupt
Vectors Placement

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 The AVR Mega Interrupts (cont’d.)
 The Mega AVR microcontroller configuration
register (MCUCR): controls interrupt vectors
placement; controls enabling of I/O pins pull-up
and the JTAG interface

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 The AVR Mega Interrupts (cont’d.)
 Special instruction to change the IVSEL bit
 In r16,MCUCR
 Mov r17,r16
 Ori r16,(1<<IVCE) ; set the IVCE bit
 Out MCUCR,r16
 Ori r17,(1<<IVSEL) ; set the IVSEL bit and clear the IVCE bit
 Out MCUCR,r17
 Instruction in C
 Unsigned char temp;
 Temp = MCUCR;
 MCUCR = temp | (1<<IVCE); //sets the IVCE
 MCUCR = temp | (1<<IVSEL); //sets IVSEL & clear IVCE

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 The AVR Mega Interrupts (cont’d.)

 AVR Mega external interrupt pins

 INT7:0 pins trigger interrupt requests to the MCU; pins
shared with PORTD (0-3) and E (4-7), controlled by
EICRA and EICRB register.

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The AVR Mega Interrupts (cont’d.)

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 The AVR Mega Interrupts (cont’d.)

 EIMSK to enable the interrupt and EIFR to flag

the interrupt.

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 The AVR Mega Interrupts : example

Example: Write an instruction sequence to enable

INT0 and INT1 interrupt. INT0 on rise edge and
INT1 on falling edge.

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 The AVR Mega Interrupts : example
.include <m644Adef.inc>
.def tmp = r16
.cseg
.org 0x00
jmp start
jmp INT0_Vect

Start:
.org 0xF6
Code in Assembling,compiled
ldi tmp, low(RAMEND)
out SPL,tmp
ldi tmp, high(RAMEND)
out SPH, tmp
lds tmp,DDRD ; configure PD0/INT0, PD1/INT1 for input
andi tmp,0xFC
sts DDRD,tmp
ldi tmp, 0x0B
sts EICRA, tmp ; //INT0 on rising edge, INT1 on falling edge
ldi tmp,0x03 ; "
sts EIMSK,tmp ; // enable INT0,INT1
sei
again: jmp again ;// loop
INT0_Vect: nop
reti

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 The AVR Mega Interrupts : example
#include <avr\io.h>
#include <avr\interrupt.h>
unsigned char cnt;
int main (void)
{
DDRD &= 0xFC ; //configure PD0/INT0, PD1/INT1 for input
EICRA =0x0B ; //INT0 on rising edge, INT1 on falling edge
EIMSK =0x03 ; // enable INT0,INT1
sei();
cnt =0;
while(1); //wait for interrupt
}
// INT0 interrupt
ISR(INT0_vect)
{
cnt++;
}
// INT1 interrupt
ISR(INT1_vect)
{
cnt++;
}
Code in C (compiled)

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 The AVR Mega Interrupts (cont’d.)
 Pin change interrupt
 ATMega640/1280/2560 has 24 pins (PCINT23~0) that
generate interrupt whenever one or more of these pins
toggle, PCINT23-16 pin toggles will trigger PCINT2;
PCINT15-8 pin toggles will trigger PCINT1; PCINT7-0
pin toggles will trigger PCINT0;
 PCICR register enable three pin change interrupts
 PCIFR flag the interrupts
 PCMSK2,1,0 control the enabling and disabling 24
pins

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The AVR Mega Interrupts (cont’d.)

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The AVR Mega Interrupts (cont’d.)

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The AVR Mega Interrupts (cont’d.)

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 The AVR Mega Interrupts (cont’d.)

 Writing interrupt service routine in C for AVR

Mega devices

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 The AVR Mega Interrupts (cont’d.)

 Interrupt service routine format required by AVR

Studio C compiler
ISR (vector number of the interrupt)
{
. . .
}
 Symbolic names of all interrupt vector numbers and interrupt
vectors have been defined in the appropriate header file (C
lang.) and include file (assembly lang.)

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 The AVR Mega Interrupts : example
Example: Write a sequence of C statements to configure PCINT0, PCINT1, PCINT4, PCINT8, PCINT9,
PCINT14, PCINT18, PCINT20, and PCINT23 to interrupt the MEGA CPU.
Solution:
#include <avr\io.h>
#include <avr\interrupt.h>
unsigned char cnt;
int main(void)
{
PCMSK2 = 0x94; // enable PCINT23, PCINT20, and PCINT18, 10010100
PCMSK1 = 0x43; // enable PCINT14, PCINT9, and PCINT8, 01000011
PCMSK0 = 0x13; // enable PCINT4, PCINT1, and PCINT0, 00010011
PCICR = 0x07; // enable interrupts PCINT2~PCINT0, 00000111
sei(); // enable interrupt globally
cnt=0;
while(1);
}
ISR(PCINT0_vect)
{
cnt++;

} code in assembling??

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The AVR Mega Interrupts (cont’d.)

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 AVR Mega Reset

 Power-on reset: supply voltage is below the

power-on reset threshold (VPOT)
 External reset: low level is present on the RESET
pin for longer than the minimum pulse width
 Brown-out reset: supply voltage VCC is lower than
the brown-out reset threshold (VBOT–) and the
brown out detector is enabled

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 AVR Mega Reset (cont’d.)

 JTAG AVR reset: while logic 1 exists in the reset

register
 Watchdog reset: watchdog timer overflows and
the watchdog is enabled
 Reset service routine finds out the cause of reset
by examining the MCU status register (MCUSR)

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AVR Mega Reset (cont’d.)

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 AVR Mega Watchdog Timer

 Derives its clock signal from an on-chip 128 kHz

oscillator
 Triggers an interrupt or reset when the counter
overflows
 Timing out is prevented by executing the WDR
instruction to restart the WDT

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AVR Mega Watchdog Timer

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AVR Mega Watchdog Timer

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 AVR Mega Watchdog Timer

 Practice in
assignment

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 Power Management and Sleep Modes

Mega sleep modes

 IDLE mode  Standby mode
 ADC noise reduction  Extended standby
mode mode
 Power-down mode  Power reduction
 Power-save mode register

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Power Management and Sleep Modes

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 Power Management and Sleep Modes

 ldi r16,0x0F;extended standby  SMCR = 0x0F;

 sts SMCR,r16  _asm__volatile_(“sleep”);
 sleep

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 Power Reduction Modes

 Configure PRR0 & PRR1 register to disable the

clock to some modules.

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 Power Reduction Modes
 Configure PRR0

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 Power Reduction Modes
 Configure PRR1

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Part III.4 Advanced Parallel I/O

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 Outline

i. Interfacing a Parallel PORT to a Keypad

ii. Driving the Stepper Motor
iii. Direct Memory Access (DMA) Transfer
iv. Liquid Crystal Displays (LCDs)

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107
 Interfacing a Parallel PORT to a Keypad
 Keypad: arranged as an array of switches
(mechanical, membrane, capacitive, or Hall
effect construction)
 Mechanical keypads
 Advantages: low cost and construction strength
 Disadvantage: contact bounce

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Interfacing a Parallel PORT to a Keypad
(cont’d.)

 Keypad input program stages

 Keypad Scanning: performed row by row and
column by column
 Keyboard Debouncing
Hardware debouncing techniques
 Set-reset latches
 Noninverting CMOS buffer with high input impedance
 Integrated debouncers

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Interfacing a Parallel PORT to a Keypad
(cont’d.)

 Hardware debouncing techniques

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Interfacing a Parallel PORT to a Keypad
(cont’d.)

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 Interfacing a Parallel PORT to a Keypad
(cont’d.)

 Keypad input program stages (cont’d.)

 Keyboard debouncing
Software debouncing techniques
 Wait-and-see: adequate for most applications
 ASCII code lookup: can be embedded in the program
that performs the scanning and debouncing

 Keypad interfacing and coding will be used in lab3

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 Driving the Stepper Motor

 Stepper motors: digital motors

 Convenient for applications where a high degree of
positional control is required
 Principles of rotation
 Clockwise full-step rotation
 Counterclockwise full-step rotation

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 Driving the Stepper Motor

 Clockwise full-
step rotation

 Counterclock
wise full-step
rotation
(reverse the
polarities of
C3,C4)

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 Driving the Stepper Motor

Half-step operation:
rotor (in a four-pole
step) is moved to eight
discrete positions (45
degrees)

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 Driving the Stepper Motor (cont’d.)

 Discrete stepper motor drivers

 See Figure 10.8 Driving a stepper motor
 Transistors: switch the current to each of the coils
 Fly-back diodes: protect the transistors from reverse bias
 Transistor loads: windings in the stepper motor
 Windings: inductors, storing energy as magnetic field
 Integrated stepper motor driver
 Darlington array chip ULN2003: replacement to discrete
transistors

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Driving the Stepper Motor (cont’d.)

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Driving the Stepper Motor (cont’d.)

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Driving the Stepper Motor (cont’d.)

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 Driving the Stepper Motor (cont’d.)
 Integrated stepper motor driver
 Darlington array chip ULN2003: replacement to discrete
transistors

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 Driving the Stepper Motor (cont’d.)

 Write subroutine to rotate the motor

 sent the data to PORTA in sequence
 straight forward
 see text example

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 Direct Memory Access (DMA) Transfer

 Data transfer in which the CPU is responsible for

setup; CPU not involved during the data transfer
phase
 MEGA AVU 8 bit doesn’t have DMA
 MEGA 32 bit has DMA
 XMega has DMA controller
 brief introduction

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 Direct Memory Access (DMA) Transfer (cont’d.)

 DMA registers
 Control register (CTRL)
 Status register (STATUS)
 Interrupt flag register (INTFLAGS)
 16-bit temporary register (TEMP): controls the
overall operation
 DMA channel operation: supported by it own
set of registers

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Direct Memory Access (DMA) Transfer (cont’d.)

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Direct Memory Access (DMA) Transfer (cont’d.)

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Direct Memory Access (DMA) Transfer (cont’d.)

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Direct Memory Access (DMA) Transfer (cont’d.)

Table 10.4 DMA channel register summary

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Direct Memory Access (DMA) Transfer (cont’d.)

Example: Write a sequence of C statements to configure the DMA transfer from

channel A of the Timer/Counter1 associated with Port F and data memory starting
from 0x2000.
Solution:
DMA.CTRL |= DMA_ENABLE_bm; // enable DMA
DMA.CH0.CTRLA |= DMA_CH_ENABLE_bm; // enable DMA channel 0
DMA.CH0.CTRLA = 0x81; // set DMA channel 0 burst length to 2 bytes
DMA.CH0.ADDRCTRL = 0x91; // source reload on burst, destination no reload
DMA.CH0.TRIGSRC = DMA_CH_TRIGSRC_TCC0_CCA_gc;
DMA.CH0.TRFCNT = 1024;
DMA.CH0.SRCADDR0 = (uint32_t)((uint16_t)(&TCC1.CCA)) & 0xFF;
DMA.CH0.SRCADDR1 = (uint32_t)(((uint16_t)(&TCC1.CCA))>>8) & 0xFF;
DMA.CH0.SRCADDR2 = (uint32_t)(((uint16_t)(&TCC1.CCA))>>16) & 0xFF;
DMA.CH0.DESTADDR0 = 0;
DMA.CH0.DESTADDR1 = 0x20;
DMA.CH0.DESTADDR2 = 0;
while(!(DMA.CH0.CTRLB & DMA_CH_TRNIF_bm)); // wait for DMA transfer to complete

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 Liquid Crystal Displays (LCDs)
 Advantages
 High contrast
 Low power consumption
 Small footprint
 Ability to display both characters and graphics

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Figure 10.18 A liquid crystal display (LCD)

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 The HD44780 LCD Controller

Figure 10.19 Block diagram of a HD44780-based LCD kit

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 The HD44780 LCD Controller (cont’d.)

 Display data RAM (DDRAM)

 Stores display data represented in 8-bit character
codes
 Extended capacity is 80 x 8 bits (80 characters)
 Character generator ROM (CGROM)
 Generates 5 x 8- or 5 x10-dot character patterns from
8-bit character codes

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 The HD44780 LCD Controller (cont’d.)

 Character generator RAM (CGRAM)

 Permits user to define his or her own character fonts
 LCD controller registers
 Instruction register (IR): stores instruction codes
 Data register (DR): data written into the DR register
are automatically written into the DDRAM or the
CGRAM by an internal operation

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 The HD44780 LCD Controller (cont’d.)

• Instructions
 Clear display  Set CGRAM address
 Return home  Set DDRAM address
 Entry mode set  Read busy flag and address
 Cursor or display shift
 Function set

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The HD44780 LCD Controller (cont’d.)

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The HD44780 LCD Controller (cont’d.)

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The HD44780 LCD Controller (cont’d.)

Note: for 2 line, and 4 line refer to text

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The HD44780 LCD Controller (cont’d.)

Note: over 80
characters
refer to text

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The HD44780 LCD Controller (cont’d.)

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 The HD44780 LCD Controller (cont’d.)

 Interfacing the HD44780 to the AVR

microcontroller
 Data transfer between the HD44780 and the Atmel
AVR can be done in 4 bits or 8 bits at a time
 Choice of using I/O PORTs to interface with the LCD
module or treating the LCD as a memory device

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The HD44780 LCD Controller (cont’d.)

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The HD44780 LCD Controller (cont’d.)

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 The HD44780 LCD Controller (cont’d.)

 LCD Startup Sequence:

 Power on  Wait 30 ms  Execute function set instruction 
Wait 40 ms  Execute display control instruction – Wait 40 ms 
Execute display clear instruction  Wait 1.64 ms  Execute
entry mode set instruction  Wait 40 ms  OK
 See Figure 10.23 next slide

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The HD44780 LCD Controller (cont’d.)

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 The HD44780 LCD Controller (cont’d.)

 Writing LCD programs

 Example: Procedure for sending a command to
the IR register
 Step 1: Pull the RS and the E signals to low
 Step 2: Pull the R/W signal to low
 Step 3: Pull the E signal to high

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 Example: Procedure for sending a command to the IR
register (cont’d.)
 Step 4: Output the given LCD instruction to the I/O

PORT attached to the LCD data bus; the I/O PORT

connected to the LCD data bus must be configured for
output before this can be done
Step 5: Pull the E signal to low, and make sure that
the internal operation is completed; this is achieved by
calling a delay subroutine
 Refer to Examples 10.4 through 10.8

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The HD44780 LCD Controller (Examples)
 All kinds utility in Asm for LCD
 lcdUtil_xmega.asm
 All kinds utility in C for LCD
 lcdUtil_xmega_c
 Display two line message in C for LCD
 eg10_08c
 C head file
 lcdUtil_xmega_h
 C test file
 lcdTest.c
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