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Lec 3

The document discusses embedded system design and ARM architecture. It covers: 1. The objectives of the course which are instruction set, ARM architecture, and pipelining. 2. It recaps the basic stages of instruction execution in a microprocessor - fetch, decode, fetch operands, execute, and store results. 3. ARM is introduced as a reduced instruction set computing (RISC) architecture based on simple but powerful instructions that can execute in a single cycle for high clock speed.

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Prateek Goyal
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15 views20 pages

Lec 3

The document discusses embedded system design and ARM architecture. It covers: 1. The objectives of the course which are instruction set, ARM architecture, and pipelining. 2. It recaps the basic stages of instruction execution in a microprocessor - fetch, decode, fetch operands, execute, and store results. 3. ARM is introduced as a reduced instruction set computing (RISC) architecture based on simple but powerful instructions that can execute in a single cycle for high clock speed.

Uploaded by

Prateek Goyal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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System Design
Lecture-3

Dr. Nalin Kumar Sharma


Objectives of the course

• Instruction Set
• Architecture of ARM
• Pipelining
Recap:
Instruction execution in
Microprocessor
• We can think of a microprocessor’s execution of instructions as consisting of several basic stages:
1. Fetch instruction: the task of reading the next instruction from memory into the instruction register.
2. Decode instruction: the task of determining what operation the instruction in the instruction register
represents (e.g., add, move, etc.).
3. Fetch operands: the task of moving the instruction’s operand data into appropriate registers.
4. Execute operation: the task of feeding the appropriate registers through the ALU and back into an
appropriate register.
5. Store results: the task of writing a register into memory.
• If each stage takes one clock cycle, then we can see that a single instruction may take several cycles to
complete.
Instruction Architecture

• Reduced Instruction Set Computing (RISC)


• Complex Instruction Set Computing (CISC)
RISC and CISC

• RISC is a design philosophy aimed at delivering simple but powerful


instructions that execute within a single cycle at a high clock speed.
• The RISC philosophy concentrates on reducing the complexity of
instructions performed by the hardware because it is easier to provide
greater flexibility and intelligence in software rather than hardware.
• As a result, a RISC design places greater demands on the compiler.
• In contrast, the traditional CISC relies more on the hardware for instruction
functionality, and consequently the CISC instructions are more
complicated.
ARM

• ARM, or “Advanced RISC Machine” is a specific family of instruction set


architecture that’s based on reduced instruction set architecture.
• ARM patents the technology and provide it to other companies for
manufacturing. For example: STM, NXP, TI.

• Applications:
• BenQ
• Apple iphone, Nokia
Four major design rules of RISC: 1.
Instructions
• RISC processors have a reduced number of instruction classes.
These classes provide simple operations that can each execute in a
single cycle.
• The compiler or programmer synthesizes complicated operations
(for example, a divide operation) by combining several simple
instructions.
• In contrast, in CISC processors the instructions are often of variable
size and take many cycles to execute.
Four major design rules of RISC: 2.
Pipelines
• The processing of instructions is broken down into smaller
units that can be executed in parallel by pipelines.
• Ideally the pipeline advances by one step on each cycle for
maximum throughput.
• Instructions can be decoded in one pipeline stage.
Four major design rules of RISC: 3.
Registers
• RISC machines have a large general-purpose register set.
• Any register can contain either data or an address.
• Registers act as the fast local memory store for all data
processing operations.
Four major design rules of RISC: 4.
Load-store architecture
• The processor operates on data held in registers.
• Separate load and store instructions transfer data between the
register bank and external memory.
ARM is not completely RISC

• Variable cycle execution for certain instructions


• Inline barrel shifter leading to more complex instructions
• Thumb 16-bit instruction set
• Conditional execution
• Enhanced instructions
Pipelining
Pipelining

• It is method for speeding execution by fetching the next


instruction while other instructions are being decoded and
executed.
• Pipelining is a common way to increase the instruction throughput of
a microprocessor.
• A instruction is divided in more than one smaller stages.
ARM7 Three-stage pipeline.

• Fetch loads an instruction from memory.


• Decode identifies the instruction to be executed.
• Execute processes the instruction and writes the result back to a
register.
ARM7 Three-stage pipeline.
ARM-9 and ARM-10

As the pipeline length increases, the amount


of work done at each stage is reduced,
which allows the processor to attain a higher
operating frequency.
This in turn increases the performance.
Benefit of more Stages in
pipeline?
• Non pipelined system takes 130ns to process an
instruction . A program of 1000 instructions is
executed in non pipelined system. Then same
program is processed with processor with 5
segment pipeline with clock cycle of 30 ns/stage.

Determine speed up ratio of pipeline.


Stages, Clock and Latches
Thanks

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