BIPOLAR TRANSISTOR AMPLIFIER
ELE2041 Electronics and Circuits
The aim of this experiment is to design and measure a bipolar transistor voltage amplifier to
conform to a given specification. This is a typical audio amplifier that could be used to amplify a
signal from a microphone to supply a loudspeaker.
In the lab session, you will measure the amplifier using the National Instruments Elvis platform.
In addition, as a homework exercise, you will carry out some calculations to work out the
component values for the amplifier.
The requirements of a voltage amplifier include a high input resistance and low output
resistance. The specification to be followed is:
DC supply voltage 9 volts
Voltage swing 5 volts p-p voltage from 50mV input voltage
Input resistance at least 20 kΩ
Output resistance less than 20 Ω
1 Background Theory
1.1 Amplifier Circuit
Figure 1 Three stage bipolar amplifier
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The circuit diagram of the amplifier is shown in Figure 1. From the specification of the amplifier,
the overall gain required is 100. Consider a single stage amplifier, such as stage 1. The voltage
gain of this stage is given by:
−o R2 RT
Av =
RS ( RT + r + o RE )
Where RS = source impedance, RB = R1//R9, and:
RS RB
RT =
RS + RB
The voltage gain equation can be simplified if RB » RS, RT = RS, and (oRE + r) » RT
− o R2 RT −R2
Av =
RS ( RT + r + o RE ) r + R3
r is the internal base-emitter resistance, derived from the hybrid pi small signal model. It can be
assumed to be 25 for a collector current of 1mA and 12.5 for a collector current of 2mA.
From the specification a high input impedance is required of at least 20 kΩ. It can be seen from
Figure 1, that the input impedance is given by:
RIN = (Resistance at base of T1)//R1//R9
It can be shown that the Resistance at base of T1 (Rbase) is given by:
Rbase = f(r+R3)
Therefore to maximise the input impedance, RIN we can set R1 = R9. In this condition, we know,
from the potential divider rule, that the DC voltage at the base of T1 is 4.5V. For a silicon bipolar
transistor we assume a voltage drop of 0.6 V across the base and emitter. This means that the
DC voltage on the emitter of T1 is 4.5V-0.6V = 3.9V. For a 5 v p-p output voltage, a Vce of 3 volts
should be allowed for T1. Hence for a stage collector current of 1mA, R2 = 2 k Ω. The overall
amplifier is required to have a gain of 100. It is good design practice to allow a gain of 10 for each
stage, since for much higher gains in a single stage, some of the approximations made in this
analysis are no longer valid, particularly, the value of r becomes significant and prevents voltage
gains of >>10 being produced, for a single stage. Hence two stages are required. Note that the
third stage of the amplifier has a voltage gain = 1 since it is used as a current amplifier, to provide
sufficient current to the low impedance output of the amplifier.
In the circuit of Figure 1, T1 (BC368) provides a voltage gain of order 10, and a high input
impedance. The input impedance of the first stage is approximately F1 (r + R3). Thus R3 (and
R2) are chosen to give a voltage gain of 10 and an input resistance of at least 20 k Ω. The DC
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biasing system uses R1 and R9 in conjunction with R3 and R4 to provide bias point stability for the
low power stage. As R1 R9 can be high (>20kΩ), it should be possible to meet the specification
with this circuit.
Stage 2 incorporates a PNP transistor, BC369, which is complementary to the BC368. This
configuration enables the two stages to be directly coupled (ie no DC blocking capacitor needed).
The values of R6 and R7 are chosen to provide a voltage gain of 10, giving the overall gain of 100.
Stage 3 consists of a BC368 transistor in the emitter follower configuration. This produces a
voltage gain from base to emitter of approximately unity, and an output resistance R7 / f3 ;
where f3 is the BC368 small signal current gain. This stage is important in order to meet the
low output impedance requirement in the specification.
It is important in the design stage, to consider carefully the DC voltage levels throughout the
amplifier, in order to ensure that clipping of the AC voltage waveform does not occur.
2 Design Procedure
In this section a design procedure is outlined. The aim is to be able to calculate the component
values of the circuit to meet the specification.
Begin by considering the p-p AC voltages, which will be expected at different points in the
amplifier. With a voltage gain of 10 from stage 1, and 10 from stage 2 these should be:
Point (TP4) 5 volts p-p
Point (TP3) 5 volts p-p
Point (TP2) 0.5 volts p-p
Point (TP1) 50mV p-p
In order to eliminate clipping of the AC waveform, suggested DC voltage levels can be estimated.
At point (Ai2, Figure 1) 4 volts DC should be adequate. This will allow an AC voltage swing of 5V
without clipping. If we assume a voltage drop between the base and emitter of T3 of 0.6 volts,
the DC voltage at point (Ai1) can be calculated to be 4.6 volts. In order that the collector emitter
voltage of T2 can swing through 5 volts, a DC collector emitter voltage of 3 volts is chosen, giving
an emitter voltage of T2 of 7.6 volts. A collector voltage of T1 of 7 volts results. As shown
previously, the emitter voltage of T1 is required to be 3.9 volts.
The collector currents suggested for the three transistors are T1, 1 mA; T2, 2 mA; T3, 4 mA.
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2.1 Stage 1 Design
With an IC of 1 mA, R2 = 2 kΩ to give a collector voltage of 7 volts. For an AC gain of 10 from the
stage, with r = 25 Ω, a value of 175 Ω is estimated for the AC emitter resistor, since we know
that:
−R2
Av =
r + R3
In order to achieve the collector current of 1 mA, with an emitter DC voltage of 3.9 volts, the total
emitter resistance should be 3.9 kΩ. Hence R3 = 175Ω and R4 = 3.725 kΩ.
We are told in the specification that an input resistance (RIN) of 20K is required for the first
stage. Assuming a value of f1 for T1 of 300, the inherent input resistance of the stage, at the
base of T1 (Rbase) is 60kΩ. Assuming that R1 = R9, and that:
RIN = Rbase//R1//R9
It is then possible to calculate the values of R1 and R9
Q1. (Homework) Calculate the required values for R1 and R9.
2.2 Stage 2 Design
The output resistance of the amplifier = 1/f3 R7 = 20 Ω. Hence for f3 = 300, R7 ~ 6 kΩ or
less. The emitter to positive battery terminal DC voltage is 1.4 volts. For a collector current of
2 mA assume that r = 12.5. Find R7, R6 and R5, to give a voltage gain of 10, and the required DC
voltage levels. Hint: refer to the calculation for stage 1 (Sec 2.1)
Q2. (Homework) Find R7, R6 and R5, to give a voltage gain of 10, and the required DC
voltage levels.
2.3 Stage 3 Design
In order to get the required voltage swing of 5 Vp-p, the emitter voltage of T3 is assumed to be 4
volts.
Q3. (Homework) Assuming the emitter voltage of T3 is 4 volts, calculate R8, for an emitter
bias current of 4 mA.
In stages, 1 and 2, emitter bypass capacitors C2 and C3 are used as DC blocking capacitors. This
means that they are intended to allow AC current to pass through, but block DC current. Since
these capacitors will have increased impedance at lower frequencies, their values are a
compromise between the size and cost of the capacitors versus low frequency performance. A
value of 47 µF has been found to offer a good compromise.
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3 Practical measurement of a three stage transistor amplifier
The main aim of this practical laboratory session is to produce measured results of a pre-
assembled transistor amplifier circuit, to compare with the design theory.
The circuit will be measured using the Rohde & Schwarz RTB2002 Digital Oscilloscope, Figure
2. This platform includes a function generator and oscilloscope, all in one device. The
transistor amplifier circuit has been constructed on a PCB, (Figure 3).
Figure 2 Rohde & Schwarz RTB2002 Digital Oscilloscope
Figure 3 Transistor amplifier breadboard layout
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3.1 Measuring the gain of the amplifier, with increasing input voltage, using a
function generator and oscilloscope
The aim of this part of the experiment is to measure the amplitude response of the transistor
amplifier. A block diagram of this setup is shown in Figure 4. In this setup a function generator
is connected to the input of the amplifier, and the output voltage is measured using an
oscilloscope.
Figure 4 Measurement setup block diagram
• Setup the transistor amplifier as shown in Figure 5
Figure 5 Transistor amplifier connected to R & S RTB2002 Digital Oscilloscope
• Set the variable power supply to +9V and ensure power is applied to the circuit.
• Set Function Generator of the R&S Oscilloscope to 1 KHz, 0.05Vpp, using the “Gen”
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button. Ensure function generator is set to “on”
• Use “autoset” on the oscilloscope to display the input and output sine waves, which
should look similar to Figure 6.
• If you notice any clipping on the output reduce the function generator voltage until
the clipping just disappears. Use this new lower value for the next parts of the
experiment instead of 0.05Vpp (including the bode plot, sec 3.5)
Figure 6 Oscilloscope display Vin = 50 mVpp
Q4. With the Function generator set to 1 KHz. 0.05 Vpp, note the amplitudes of Vi and
Vo and calculate the gain.
Now do the same experiment for the function generator output set to:
• 0.1 Vpp
• 0.2 Vpp
Q5. Copy a screenshot of the oscilloscope for Vi = 0.05V (or lower, if your amplifier
clipped at this level), 0.1V and 0.2V. Comment on the effects on the output
waveform, Vo.
Figure 7 Example output voltage for Vin = 0.2 Vp-p
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3.2 Effects of changing the amplifier power supply voltage
In this section the power supply voltage to the amplifier will be reduced from 9V to 6V to observe
the effect on the output waveform.
Set the function generator Vpp to 0.05V (or lower, if your amplifier clipped at this level), reduce
the variable power supply to 6V.
Q6. Copy a screenshot of the oscilloscope for Vi = 0.05V with power supply set to 6V.
Comment on the effects on the output waveform, Vo. What is the highest input Vpp
possible for distortion free output?
Figure 8 Example for Vpp = 0.05V, Var power supply = 6V
3.3 Examining the waveforms of each amplifier stage
Here, the aim is to examine the effects of the waveforms at each stage of the amplifier, to
provide an understanding of how the design of each stage is critical to the operation of the
amplifier, in terms of providing distortion free output. To set this up, follow the procedure
below:
• Set the power supply to 9V
• Set function generator to 0.05 Vpp (or lower, if your amplifier clipped at this level), 1 KHz
• Connect Ch1 of the oscilloscope to TP2 and Ch2 to TP3. Ensure the function generator is
still connected to “IN”
• Obtain a display of the two waveforms, you can use “Autoset” for this
• If you get unwanted oscillation waveforms appearing remove the black ground banana
plug from the CH2 lead going to TP3
Q7. Increase the function generator Vpp until stage 2 (TP3, Ch2) just begins to start
clipping. Copy a screenshot of the oscilloscope display to your write-up.
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3.4 Examining the DC biasing of each amplifier stage
Using a multimeter on DC voltage range, measure the DC bias at TP1, TP2, TP3, and TP4
Q8. Copy the DC bias levels to the table in your write-up
Q9. (Homework) Comment on the values of DC bias at each stage. Has the DC biasing
been designed correctly? How might it be improved?
3.5 Producing a Bode Plot for the transistor amplifier
To produce an automated bode plot for the amplifier, follow the steps below:
• Change circuit back to the configuration of Figure 5
• Set the oscilloscope to “bode plot” mode
• Set start frequency to 10 Hz, stop frequency to 10 MHz
• 10 Pts/
• Ampl 0.05 V (or lower, if your amplifier clipped at this level)
• Click “run” on bode analyser
Figure 9 Example bode plot (note your circuit may differ from this)
Q10. Copy a screen capture of the automated bode plot to your write-up
Q11. (Homework) Comment on the results of the automated bode plot. In particular
make reference to the gain at low frequency, mid frequency and high
frequency.
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