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    DSP 21EC42 2ndIA

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    Kirana007
    This document contains instructions for a digital signal processing exam, including: 1) Questions about the architecture of the TMS320CS54X digital signal processor and designing IIR filters using the bilinear transformation. 2) Converting an analog filter transfer function and difference equation to the digital domain, explaining IEEE floating point formats, and mapping points between the S-plane and Z-plane using the bilinear transformation. 3) Explaining digital signal processing hardware units like multipliers, accumulators, shifters, and adders, and designing a digital Butterworth high pass filter that meets specific passband and stopband specifications.

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    DSP 21EC42 2ndIA

    Uploaded by

    Kirana007
    69 views1 page
    This document contains instructions for a digital signal processing exam, including: 1) Questions about the architecture of the TMS320CS54X digital signal processor and designing IIR filters using the bilinear transformation. 2) Converting an analog filter transfer function and difference equation to the digital domain, explaining IEEE floating point formats, and mapping points between the S-plane and Z-plane using the bilinear transformation. 3) Explaining digital signal processing hardware units like multipliers, accumulators, shifters, and adders, and designing a digital Butterworth high pass filter that meets specific passband and stopband specifications.

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    DSP-21EC42-2ndIA

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    This document contains instructions for a digital signal processing exam, including: 1) Questions about the architecture of the TMS320CS54X digital signal processor and designing IIR filters using the bilinear transformation. 2) Converting an analog filter transfer function and difference equation to the digital domain, explaining IEEE floating point formats, and mapping points between the S-plane and Z-plane using the bilinear transformation. 3) Explaining digital signal processing hardware units like multipliers, accumulators, shifters, and adders, and designing a digital Butterworth high pass filter that meets specific passband and stopband specifications.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    69 views1 page

    DSP 21EC42 2ndIA

    Uploaded by

    Kirana007
    This document contains instructions for a digital signal processing exam, including: 1) Questions about the architecture of the TMS320CS54X digital signal processor and designing IIR filters using the bilinear transformation. 2) Converting an analog filter transfer function and difference equation to the digital domain, explaining IEEE floating point formats, and mapping points between the S-plane and Z-plane using the bilinear transformation. 3) Explaining digital signal processing hardware units like multipliers, accumulators, shifters, and adders, and designing a digital Butterworth high pass filter that meets specific passband and stopband specifications.

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    of 1

    9/7/23, 11:46 AM 21EC42 9/7/23, 11:46 AM 21EC42

    Explain the basic architecture of TMS320CS54X used in


    USN : b 5 CO5 PO1 L2
    fixed point Digital Signal processor
    OR
    Angadi Institute of Technology and Management
    PO1,
    Belagavi Discuss the general procedure for IIR filter design using
    4 a 5 CO4 PO2, L2
    Department of Electronics & Communication Engineering Bilinear transformation
    PO5
    II - Internal Assessment
    Find the signed Q-15 representation for the decimal
    b 5 CO5 PO1 L2
    Semester: 4-CBCS 2021 Section: A Date: 7 Sep 2023 number 0.560123
    Subject: DIGITAL SIGNAL PROCESSING (21EC42) Time: 02:00 PM - 03:00 PM
    CO4 : Design FIR and IIR Digital Filters
    Faculty: Mr Kiran Itagi Max Marks: 20 CO5 : Design of Digital Filters using DSP processor

    Answer any 2 question(s)


    Q.No Marks CO PO BT/CL
    Given an analog filter whose transfer function H(s) =
    PO1,
    10/s+10. Convert it to the digital filter transfer function
    1 a 5 CO4 PO2, L3
    and difference equation, respectively, when the sampling
    PO5
    period is given as T=0.01 sec
    Explain IEEE floating point format using: i) Single precision
    b 5 CO5 PO1 L2
    format ii) Double precision format
    OR
    Assuming that T=2 sec in BLT and given the following
    points
    i) S= -1+j, on th left half of S-plane ii) S= 1-j, on the right PO1,
    2 a half of S-plane iii) S= j, on the positive jw on the S-plane iv) 5 CO4 PO2, L2
    S= -j, on the negative jw on the S-plane PO5
    Convert each of these points in the S-plane to the Z-plane
    and verify the maping properties
    Explain the following Digital Signal Processing Hardware
    units i) Mutiplier and Accumuator ii) Shifters iii) Adders
    b 5 CO5 PO1 L2
    Generators

    Design a Digital Butterworth analog high pass filter that


    meets the following specifications
    1. Maximum passband attenuation = 2dB PO1,
    3 a 2. Passband edge frequency = 200rad/sec 5 CO4 PO2, L3
    3. Minimum stopband attenuation = 20dB PO5
    4. Stopband edge frequency = 100rad/sec

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