~ DESIGN CHALLENGES OF TECHNOLOGY SCALING ‘Shekhar Borkar {nte! Corporation 272732801000 © 1950 EEE ls PROCESS TECHNOLOGY MEETIN THE GOALS PREDICTED BY SCALING THEORY? AN ANALYSIS OF MICROPROCESSOR PERFORMANCE, TRANSISTOR DENSITY, AND POWER TRENDS THROUGH SSIVE TECHNOLOGY GENERATIONS HELPS IDENTIFY POTENTIAL LIMITERS OF SCALING, PERFORMANCE, AND INTEGRATION, + Scalingadvanced CMOS technolo: {gy 10 the next generation improves perfor- mance, increases transistor density, and reduces power consumption, Technology scal- ing typically has ehrce main goals 1) reduce tate delay by 30%, resultingin an increase in ‘operating frequency oF bout 43%: 2) double transistor density; and 3) reduce energy per transition by about 65%, saving 50% of power (at2 43% increase in frequency). These are not ad hoc goals: rather, they follow scal- ing theory. This article looks closely a past tuends in technology scaling and how well _mictopracesor technology and products have met these goals. Ielso project the challenges that lie ahead if these trends continue. This analysis uses data from various Intel micro: processor however, this study is equally applicable wo other types of logic design Scaling theory Scaling technology sedces ue delay by Sone andthe lea an veil dimensions iy 0%. Therefore the area and ng Capactanc,ndcomaquny the el pac ane dectee by 30861007 Delay = 0.7, frequency = 1.43 Wideh « W 07, lenggh = £07, (Gg: oxide thickness) Area capacitance Fringing capacitance = C, = L Toral cpacieance => C= 0.7 Since the dimensions decrease by 30%, che die area decreases by 50%, and capacitance per unit of area increases by 43%: Die area =X ¥= 0.70.7 = 0.7 ice ome Area 07 x0. Frequency-scaing trends (performance) To evaathow well pit technologies have met the performance goal, we plot produce Gintoduction) frequencies over tne, as shown in Figure I. Assuming that a echnol- ‘gy generation spans two o thre year, the datashow that microprocesor frequency has doubled every generation nat just increased by 439, Several factors may account for hi Consider che data plotted onthe righthand raisin Figure 1. The average umber of ate delays in ack period is decreasing because aTecHNOLOGY SCALING 10,00 11000 1 z Ene a i of 06 055 028 —ON@ Process technology (miro) Figure 2 Scaling of transistor size. pn " irom _. ‘260 Loge ranssoremn? logan sale) 18 10 08 06 095 025 018 013 Process technology (mirens) Figure. Etfoct of scaling on log transistor density. I (REE MICRO pipeines foe atc gates, and advanced circuit techniques reduce critical path delays ever fut> ‘ther. This could be one reason that Fequen «oy is doubling every technology generation. ‘One might suspect that this Frequency increase comesac the expense of erdesign oF ‘oversicng of eransstors. Figure 2 shows hove sransintorsize scales across technologies in dif {erent Ine microprocessors, The dotted lines show ranitor sieving dawn 30% per ge ‘ation according to scaling theory Novice tht the total eransstor sie, which the sum ofall transistor wide, decreases about 30%. The lower graph shows average transistor sizes (in aubieany unis), which also decease by about 34%, ruling out any suspicion about oversiz- lng and overdcsign, ‘We an conelide thar the twofold Fequen «cy improvemene cach technology genration is primarily due to wo factors + “The reduced numberof gates employed ina clock period makes the design more pipeined ‘Advanced citcuie echnigques reduce the svcrage gate delay heyond 30% per gen Transistor density “Transistor density isthe numberof logic sransstors in a unit of ate, Teansistor dens ‘should doubleevery technology generation, since aoconding wo saling theory area decreas 1 by 509%, Memory density has ben sealing as expected, and therefore this study focuses fo logic tansitor densi Figure 3 plots the loge want density of several microprocesor, showing their com- potion acosifeen technologies. Thedot- te ine shows the expected density doubling wend. Notice that when a processor design is ported othe next proces technology it meets the density goals however, a new processor ‘icrarchiecture implemented inthe same technclogy shows drop in density. This may bed tothe complet ofthe new microae chitecturs, 8 well 50 the Fimited resources arable o accomplish more complex design. Intercomecton-scaing tends To meet technology gas the inerconne- sion system ust ele accordingly. Tn gener alas interconnection width and thickness100808 035 025 Process (micron) 35. 10 08 08 035° Process (microns) 025 T 15 ost oo 1008 06” 035 Process (microns) 025 ® Figure 4. Intecconnection scaling: interconnection stacking a elatve minimum wisth fb, relaive minimum spacing (2) r- atv minima ite ie. decrease, resistance increases, andasintercon inetions become denser, capacitance ineteas «Although chip size should decrease by 30% in each successive technology, new designs add more transistors to farther exploit integration, ‘Asa result, che average die size ofa chip tends rwiincrese ove tie, To account for increased parastics (resistance and capacitance), inte gation, and complexity, manufacturers add ‘more interconnection layers. The thinner, tighter layers are used for local intsrconnes tions, and che new thicker and sparsr layers are sed for global interconnections and power distibution. Figure 4 shows incerconnestion: scaling trends ona relative scale. Notice that Interconnections seem tobe scaling normaly Does advancement in & microarchitectuce make the interconnection sytem more com: ple’ Ifo, this could explain why new mictoae [= Peon rent na Length (nieron) FiguieS. Interconnection sistibution chivecures decrease in density. Figure 5 shows inwerconnection distribution extracted from JULY-AUGUST 1999 4TechwoLacy SCALING Pont 018 Proce (nirons) gue 6. Moximur thermal power dssoaton. Ave capacitance deny (inv?) ‘sto el aaeaates 806 008 02 O18 019 Process irons) Fig 7. Active capacitance density ‘eee NRO seer micropraccsor hipscmploying ier tent micrarchitectores. On the axis (log ‘eal, he number of terconnectons plo te again he length ofthe itercon ‘on the ais. Te graph shows that intercon nection disribuion doesnot change sight cane with advances in microarchitecture Hence, complesity amber oat asthe ve sem for she drop in density, and inerconnse tion ditrbution seme to fallow the rend Power A chip's maximum poser conemption depends on it rchnology 36 well imple- mentation, According scaling theory. a design ported 1 the next-generation tech ology should operate ae 38% high “ques the supply volage emai conse (Gonstane vlege scaling) the power should remain the ste. On the other hand ithe supply voltage scales down by 30% constant clectrie field sealing). che power should Secrecy 5% Vo = 1 Ieomsanevokage cling) Power = CV f= 0.7 81 (00.7) «1 Viv 07 (constant eecteic eld sealing) Power =CxV"f=037 X07 (107) =05 Figure 6 plots the maxima her power Alisipation of several miroprocesor in sc cessive technologies. The technologie used ‘constant voltage sealing until reaching 0.8 twicron and used consti lst ld sal ing thera. Therefore, power incest dr natclly up t00.8 icons when the increase slowed, Novice that microprocesors ported ‘conor generstion technologies with constant solkage realing do not show 2 decease in poser: the power resins coastant. On the ‘other hand, ancroprocesos porte to tech- nologies using conscant cleric Bed scaling ‘ectsiin power. Thisis consistent with a ing tory The power dissipation of chip depends not only on is technology, but also om is implementation-—hatis, on sie, crease tmicroarciteture, operation frequency, a soon. Hence, ro better understand power uuends, iis necessary to normalize by into loci the norion of active capacitance, fe tious valent eapaciance responsible oe power disipation, We ean freer normale the active capacitance tothe chip ate, ina metrical the ative capaciance densey— ‘apactance per uni of area responsible for power distpation cine Power capacitance Va ogc Active Active capacitance capacitance seas cS igure 7 plots the active capacitance densi ty of several microprocesior in diferent tech clogs. rom scaling theory we expect active capacitance density ro inereare by 43% peetechnology generation. The gure shows that the increase is on the order of 30% to 35%, not 43%, due to lower density. That i, in practice the microprocesors do not achieve s ‘twofold improvement oflopic transistor den sity berween technologies, resulting in lower active capacitance density Die size trends “Manufacturers have not only taken advan- tage of increased transistor densry, but have also increased chip (die sie ro further the level of integration. Microprocessor die size tends ‘to grow about 25% per technology generation. Loosely speaking, this satisfies Moore's law. Sofa, wehavescen uendsin sever aspects ‘of microprocesor technologies and charac: tet. Les assume tha these ends con- tinue—that is frequency doubles, supply voltage sales down 308, active capacitance gov 30% ro 35%, and die sie grows 25%. Now we can speculate on power dissipation and supply curens Figute 8 plots che computed power dss pation of Future microprocesor chips ifthe ‘wend continue supply voltae sales dwn, power dsipatin wil increase from 100 W 4 1999 to about 2,000 W in 2010; otherwise, it could reach approximately 10,000 W! So fa, his analysis considers only active power and neglect leakage power. Lskage has not bees highly significant in the past, but will besigficanein the Fue. Figure shows supply curren projections Supply current wil grow fom 100 to about 3,000 A ifsupply voleage scales down ther- wise, ie will Become even higher ‘To bring power dissipation within reason able range we wil have to este die sie With die sie resected to about 15 mn (3 smal die), power wll say around 100 W, and supply curren wll grove to abou 300 A. A larger die, about 22 mn, wllonsume about 200 W of power with 3 supply curene of about 500 A These are exsonable args that wwe can realize in practice. Energy-detay trade ofs Reducing supply voltage, frequency, and/or die sie wil reduce power. All of thee eda tions edice chip peeormance Thai one Figure 9, Supply current projections, bao de off pefrmance ro seduce pow. “Therefore, we must ask whether the primary technology gol 30% dey ection makes Sense Why no et goal that includes delay Sell as power good metic for spur pos woul be the cnegy- delay produc We nn se goals o achieve lower energy delay produand ne nchnology dotnet Sed in Gana etl? The choi ae at flows: Von 1 (onstane voltage sealing) Energy» CxV? «0.7% 1 = 0.7, delay 0.7 Boergy x delay = 07° «0.5 Von = 0:7 (constant electric field scaling) Energy = Cx V? = 0.7% 0.72 = 0.7%, dehy =0.7 Eneagy X delay « 0.7% = 0.25 ULY-AUGUST 1999 aeTeeuNoLaGy SCALING Fique 1 Damino eeu. dromeon “Dremee emer “so 60 70 80 90 109 110 Temperatre 6) (Cleay, constant electric sc (sup ply voleage scaling) gives the lower ener ‘clay price (ignoring leakage energy) and hence prferble. However, i equirescl- ing threshold voltage (Vas well, which increases the subtheeshold leakage current thus increasing the chip leakage power. ‘Subthreshold leakage [Now we attempr to estimate the sub- threshold eakage powerof faeurechis, stare ling with the 0.25.micron technology described in Boh ea,” and projecting sb ‘threshold leakage currents for 0.18, 0.13. and 0. 1-micron technologies, Assume that 10.25-micron technology has Va 450 in and [yi around Ln per ion a 30°C ‘Alo ansume that subheshold slopes are 80 snd 100 mV per decade at 30°C and 100°C respectively. Assume shat V, decreases 158% per generation, and Ly increases by 5 times cach generation. Since a increases exponen aly with semporature, iis importante on sid Lesage currents and leakage power a4 Fancion of temperate. Figure 10 shows pro jected I [asa Fanction of temperature) for the fur diferent technlogis, ‘Next we use these projected cswimate the activeleakage powerafa 15mm cand compare the ctv leakage power with ‘he active poet, The rota easitor with fn the die increases around 50% cach tech- ology generation: hence, the total leskage current ncteses about 7.5 mes, Pisresuls in the chips leakage power increasing about 5 mes ech generation. Sine ative power remains constant according 0 sealing ceo ry) leakage power will come a significant portion of total power ‘Notice shat i is posible to substantially reduce leskage power, and hence overall power, by reducing che die vemperste Therefore, better cooling eeciques wil be more ctitcl in advanced deep-submnicroa technologies to contol both active leakage poser and rota power Impact of scaling on circuits ‘Supply volage sealing increases suber cold leakage caren, increases leakage power and poses numerous challenges in the design of special circuits Domino circuits gure 11), fr example, are wily sed to achieve high performance ‘A domino gate typically reduces delay 308 ‘compared with static gate, bu it consumes 5% more power. domino cricao takes Tes apace Because che logics implemented with N eransstors and most ofthe comple mentary P stack i absent. As the theeshold voltage docesics, the nose margin decrease “To compensate, che size of the keeper P ta sistor ust increas, in turn increasing the Contention current and conseguently reduc Jngthe gute performance. Overall the dom rub advantage ver static logic wil continue to decreaue. This effect isnot restricted 10 osnin logic alone: supply volte scaling wil affect most special circuits, such as sense mpliicrs and programmable logic ara, Soft errs Sof tors (ingle-vent pes} ae cased bya panicles in the chip material and by ‘cosmic as From space Sine capacitance andvoltages will decrease in future sechnologies,a smaller charge (Q = CV) will be needed eo Slip a bitin memory. Therefore, the sof error ‘ace will increase, Atempting to reduce the softertorrateby increasing capacieance on the ‘node wil result in tence performance ‘Typically, we proce data in memory with parity or eror-corecting codes, but there is ‘no mechanism to protect latches and Bip-lops tha tore tatein random loge, The increased sofeertrratewill have a detrimencal effect on logic latches, a problem that needs more investigation Power density Power deny isthe power disipardby che chip per unit of area in Wem? Figure 12 plots the power density of microprocessor Chips in differenceechnology generations Chips in 0.6-micron technology have su pasted the power density ofa Kichen hot plats eating cll and ley che red is Increasing. Conoling die emperature and espn low ae eel or tr pesfor- smance and lowe lesage, Conlin power dei wil beeen more cui or alae contrat in depsubmicron technologies rendsin performance, densi, and power follow scaling theory these tends con- ‘inue, power delivery and dissipation will be the primary limiters of performance and ince- tration, To overcome these limiters, we must constrain dic size growth and continue ro sale supply voltage. We will have ro sale reshold voltage co meee performance demands, thus Increasing subsheshold leakage curtent, lim ining functionality of special circuits, inexea ing leakage power, and increasing solt error susceptibiliy. These are among the major challenges thae circuit designers will fice in future technologies a Acknowledgments J thank my colleagues Vivek De, K. Soumnyanth, Ai Keshavari Ian Young, and several others for providing insight into rop- ies discussed in this article, H also thank Bill Hole, Ricatdo Suarez, Fred Pollack, and Richard Wirt for their continued supporeand ‘encouragement. ae Wont Bes Hoi pie 0 e OWS 10 G8 G6 035 OB O18 019 O10 O07 Process ions) Figure 12. Chip power density, References Ital Carp. rep zw ine com 2. R. Gonzalez, B, Gordon, and M, Horowits, *Suply and Thveshotd Valiage Seaina for LowPower CMOS.” IEEE J. Sold-State ‘Crcuts, Vel 32, No.8, Aug. 1987, pp. 1210- 2M. Bohr eral Meeting, EEE Election Device Soe, 1996, pp. 843850, Pree. nt Election Devices Shekhar Borkar is che dcector of lnel’s Ci ‘ei Research Laboratory, where he leads research on low-power circuits and high-speed signaling. Heisalso an adjunct facley mem ber atthe Oregon Graduate Insite, rach= ing digital CMOS VLSI design. Borkar received a masters degree in physics fom the University of Bombay and an MSE from the University of Notre Dame Send questions and comments to Shekhar Borkar, 5200 NE Flam Young Parkway. EY2 07, Hillsboro, OR, 97124: shekhar@ht inceLeom, ULYAUGUST 1999 a