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Unit 15 Bus Structure

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Bus Structure

Introduction

• Computers are comprised of many internal components;


components must communicate with each other in order to
execute tasks/ jobs etc.

• Bus are used for purposes of internal or even external


components communication.

• So, a bus is a pathway used for communication and can be


established between two or more components.
Introduction

• Modern buses use both parallel and Serial connections and can be used in:

a) Multi drop (electrical parallel)

b) Daisy chain topology

c) Connected by switched hubs as in case of USB

• Parallel buses carry data words striped across multiple wires.

• Serial buses carry data in bi-serial buses.


Functions of a Bus
1. Data sharing- the expansion bus must be able to transfer data between the
computer (CPU) and the peripherals attached to it.
2. Addressing- a bus has address links which match those of the processor-
this allows data to be sent to or from specific memory locations.
3. Power- a bus supplies power to various peripherals that are connected to
it.
4. Timing- the bus provides a system clock signal to synchronize the
peripherals attached to it with the rest of the system.
Interconnection Structures

• A computer is made up of a set of components or modules (e g


processor, memory, I/O) that communicate with each other.

• So, computer is a network of modules and there must be paths that


connect these modules.

• Collection of paths connecting the various modules is called the


interconnection structure. Each line is capable of transmitting a binary 1
or 0. A bus that connects the modules memory, I/O and processor-
system bus.
Example of common interconnection lines to and from memory

• Memory organisation made up of N words of equal length.

- Each word assigned a unique address (numeric) 0,1 .... N-1


- A word of data can be read from or written to memory
- Operation to read or write specified by control lines
- The memory location to write data to or read data from is specified by address signals.
Common interconnection lines to and from I/O modules.

• The I/O module is similar to the memory module computers view print
- Consist of M external device ports (0,1.... M-1). Each device port is identified by a
unique port member
- It has external data paths for input and output
- Sends interrupt signal to the processor.
Common interconnection lines to and from the processor

- The processor reads in instructions and data from memory


- Processor writes out data after processing to the memory
- Processor uses control signals to control overall operation of system
- Processor receives interrupt signals
Interconnection Structure
The interconnection structure supports the following types of data transfers
(exchange) between modules:
 Memory to processor units. A unit of data to memory
 I/0 to processor- processor reads data from an I/O device via an I/O
module.
 Processor to I/O- processor sends data to and or from memory. An I/O
module is allowed to exchange data directly with memory. Without going
through the processor using direct memory access (DMA).
Serial & Parallel transfer
• A bus consists of multiple communications lines.
• Each line is capable of transmitting signals representing binary 1 or binary
0.
• Bits are transmitted in serial & parallel.
• When only one bit is carried at a time it requires only a single wire as
shown in the figure below.
• When many bits are to be transmitted at a time, it requires many wires.
These many wires together constitute a bus and mode of transmission is
termed as parallel transmission
• Serial transmission one bit at a time

• Parallel transmission several bits at a time


Comparison between serial and parallel
transmission

Factor Serial mode Parallel mode

Less costly(only one More costly(many


Cost
wire) wires)
High( more bits at a
Speed Less( 1 bit at a time)
time)

Throughput Low High


Bus Structure

• A bus that connects major components of the computer system ( processor,


memory & I/ O) is called a system bus. Bus consists of 50 to hundreds of
separate lines. On any bus the line are grouped into three main function groups.

- Data lines
- Address lines
- Control lines
Bus Structure
• Data lines

- Paths for moving data and instructions between modules.


- Collectively called data bus
- Consists of 8, 16, 32, 64,128 etc bits key factor in system performance.

• Address lines

- Identify the source or destination of the data on the bus.


- CPU needs to read an instruction or data from a given memory location.
Bus Structure
- Bus width determines the max possible memory capacity for the
system for example 8080 has 16 bit addresses giving access to 64k
address.

• Control lines

- Used to control access to and use of data and address lines.


- Also transmit commands and timing information between modules.
Bus interconnection scheme
Typical control lines.
• Memory writes- causes data on the bus to be written to the addressed
memory location.

• Memory read- causes data from the addressed memory location to be


placed on the bus.

• I/O write- causes data on the bus to be output on the addressed I/O port.

• I/O read- causes data from the addressed I/O port to be placed on the bus.

• Transfer Ack- indicates that the data has been placed on the bus.
Typical control lines
• Bus request- indicates that a module needs to gain control of the bus.

• Bus grant- indicates that the requesting module has been given control of the bus.

• Interrupt request- indicates that an interrupt is pending

• Interrupt ACK- indicates that the pending interrupt has been recognized.

• Clock- used to synchronized operators .

• Reset – initializes all the modules.

• There may also be power distribution lines for attached modules. Distribution lines
that supply power to the attached modules.
Multiple Bus Hierarchies
• Performance of a computer system suffers when a large number of devices are
connected to the bus.

• Two major reasons for this.

(i)If more devices are connected to the common bus, there is need to share bus usage
among the attached devices. The sharing mechanism coordinates bus usage to
different devices.
(ii)When aggregate data transfer demands approaches the capacity of the bus, the bus
become a bottle-neck. In such situation: increase the data rate of the bus or use a
wider bus.
Traditional bus architecture
• The need of high speed shared bus is impractical to satisfy with a single
bus. The traditional bus architecture has been used for a long time and was
reasonably efficient.

• But with higher and higher performance seen in the I/O devices, it begins
to break down.

• Traditional bus architecture is made up of three buses:

- Local bus
- System bus
Traditional bus architecture

• The bus support connection to high speed LANs (network) such as


fiber distributed data interface (FDDI), video and work station
controllers as well as controllers to the local peripheral buses including
SCSI (small computer system interconnection)
high speed bus architecture
• Again, there is a local bus that connects the processor to a cache

• A high speed bus architecture is closely integrated with the rest of the
computer systems, it only requires a bridge between the processors bus
and the high speed bus this arrangement is sometimes known as the
mezzanine architecture.
Elements of bus design
• Bus channels can be separated into two general types.

- Dedicated
- Multiplexed

• Dedicated buses use separated data and address lines.

• Multiplexed are shared lines or address valid or data valid control lines, ie’
the address and the data can be transmitted through the same number channels
using control channel address that is invalid.
Advantages of dedicated buses
• Each bus is connected only to a subject of modules, for example I/O bus
used to interconnect all I/O devises to an I/O module and the I/O bus is
connected to the system bus by means of an interface adapter of some kind.

• The main advantage of dedicated buses is high through put because of less
traffic congestion.

• The disadvantage is increased size of space and lines; this also raises the cost
of implementation.
Advantages of multiplexed bus
- Requires fewer lines (channel)
- Same space
- Lower cost

• Disadvantages

- Need for more complex circuit within, each module


- There is a fairly large decrease in performance due to certain events that use
channel, together cannot function in parallel.
Bus Arbitration

• Bus Arbitration refers to the process by which the


current bus master accesses and then leaves the control of
the bus and passes it to another bus requesting processor unit.

• When using a single bus only one device is allowed to use the bus
for transmitting at a time.

• So when more than one device requests the use of the bus, a
controller called a bus arbiter decides who gets the bus, this is called
bus arbitration.
Methods of bus arbitration
• Centralized

• This method requires a hardware that will grant the bus to one of the requesting
devices. This hardware can be part of CPU or can be a separate device on the
motherboard. On the centralized one level bus arbiter, the following two lines are used;

• Bus request line - is a lined or line where the controller only knows that a request for
bus usage has been made by a device, but the arbiter does not know which device has
made the request.

• Bus grant line - this line is propagated to all the devices. When the controller sees that
a bus request has been made, it assets the bus grant line to the first device.
Methods of bus arbitration
• Distributed or Decentralized Bus arbitration

• In this arrangement, there is no arbiter. The device have to decide who goes
next. This makes the devices more complicated, but saves the expense of having
an arbiter.

• Timing

• This refers to the way in which events are co ordinated on the bus. These can
be synchronous and asynchronous.
Methods of bus arbitration
• Synchronous
- events are determined by clock signed
- the control bus includes a clock line
- usually a single cycle leading an event.
• Asynchronous
• Asynchronous does not mean unchecked. It only means that the clocks device is not
synchronized to the central processor’s clock
• In asynchronous timing one event on a bus follows and depends on the occurrence of
a previous.

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