Unit 15 Bus Structure
Unit 15 Bus Structure
Unit 15 Bus Structure
Introduction
• Modern buses use both parallel and Serial connections and can be used in:
• The I/O module is similar to the memory module computers view print
- Consist of M external device ports (0,1.... M-1). Each device port is identified by a
unique port member
- It has external data paths for input and output
- Sends interrupt signal to the processor.
Common interconnection lines to and from the processor
- Data lines
- Address lines
- Control lines
Bus Structure
• Data lines
• Address lines
• Control lines
• I/O write- causes data on the bus to be output on the addressed I/O port.
• I/O read- causes data from the addressed I/O port to be placed on the bus.
• Transfer Ack- indicates that the data has been placed on the bus.
Typical control lines
• Bus request- indicates that a module needs to gain control of the bus.
• Bus grant- indicates that the requesting module has been given control of the bus.
• Interrupt ACK- indicates that the pending interrupt has been recognized.
• There may also be power distribution lines for attached modules. Distribution lines
that supply power to the attached modules.
Multiple Bus Hierarchies
• Performance of a computer system suffers when a large number of devices are
connected to the bus.
(i)If more devices are connected to the common bus, there is need to share bus usage
among the attached devices. The sharing mechanism coordinates bus usage to
different devices.
(ii)When aggregate data transfer demands approaches the capacity of the bus, the bus
become a bottle-neck. In such situation: increase the data rate of the bus or use a
wider bus.
Traditional bus architecture
• The need of high speed shared bus is impractical to satisfy with a single
bus. The traditional bus architecture has been used for a long time and was
reasonably efficient.
• But with higher and higher performance seen in the I/O devices, it begins
to break down.
- Local bus
- System bus
Traditional bus architecture
• A high speed bus architecture is closely integrated with the rest of the
computer systems, it only requires a bridge between the processors bus
and the high speed bus this arrangement is sometimes known as the
mezzanine architecture.
Elements of bus design
• Bus channels can be separated into two general types.
- Dedicated
- Multiplexed
• Multiplexed are shared lines or address valid or data valid control lines, ie’
the address and the data can be transmitted through the same number channels
using control channel address that is invalid.
Advantages of dedicated buses
• Each bus is connected only to a subject of modules, for example I/O bus
used to interconnect all I/O devises to an I/O module and the I/O bus is
connected to the system bus by means of an interface adapter of some kind.
• The main advantage of dedicated buses is high through put because of less
traffic congestion.
• The disadvantage is increased size of space and lines; this also raises the cost
of implementation.
Advantages of multiplexed bus
- Requires fewer lines (channel)
- Same space
- Lower cost
• Disadvantages
• When using a single bus only one device is allowed to use the bus
for transmitting at a time.
• So when more than one device requests the use of the bus, a
controller called a bus arbiter decides who gets the bus, this is called
bus arbitration.
Methods of bus arbitration
• Centralized
• This method requires a hardware that will grant the bus to one of the requesting
devices. This hardware can be part of CPU or can be a separate device on the
motherboard. On the centralized one level bus arbiter, the following two lines are used;
• Bus request line - is a lined or line where the controller only knows that a request for
bus usage has been made by a device, but the arbiter does not know which device has
made the request.
• Bus grant line - this line is propagated to all the devices. When the controller sees that
a bus request has been made, it assets the bus grant line to the first device.
Methods of bus arbitration
• Distributed or Decentralized Bus arbitration
• In this arrangement, there is no arbiter. The device have to decide who goes
next. This makes the devices more complicated, but saves the expense of having
an arbiter.
• Timing
• This refers to the way in which events are co ordinated on the bus. These can
be synchronous and asynchronous.
Methods of bus arbitration
• Synchronous
- events are determined by clock signed
- the control bus includes a clock line
- usually a single cycle leading an event.
• Asynchronous
• Asynchronous does not mean unchecked. It only means that the clocks device is not
synchronized to the central processor’s clock
• In asynchronous timing one event on a bus follows and depends on the occurrence of
a previous.