Chapter II

Assembly Language
 Learning Objectives
‹ The TMS320C6000 is supported by a set of software
development tools, which includes an optimizing
C/C++ compiler, an assembly optimizer, an assembler,
a linker, and assorted utilities.

‹ Chapter 2 tells you how to use the following Assembly

Language Tools :
ƒ Common Object File Format (COFF)
ƒ Assembler
ƒ Archiver
ƒ Linker
ƒ Cross-Reference Lister
ƒ Hex Conversion Utility

Chapter 2, Slide 2 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Introductory information

Chapter 2, Slide 3 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 COFF : Common Object File Format
‹ The assembler and linker create object files that can
be executed by a TMS320C6000 device. The format
for these object files is called common object file
format (COFF).

‹ COFF makes modular programming easier because

it encourages you to think in terms of blocks of code
and data when you write an assembly language
program. These blocks are known as sections.

‹ Both the assembler and the linker provide directives

that allow you to create and manipulate sections.

Chapter 2, Slide 4 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 COFF: Sections
‹ The smallest unit of an object file is called a section. A
section is a block of code or data that occupies
contiguous space in the memory map with other
sections.
‹ Each section of an object file is separate and distinct.
COFF object files always contain 3 default sections:

1. .text section usually contains executable code

2. .data section usually contains initialized data
3. .bss section usually reserves space for
uninitialized variables

Chapter 2, Slide 5 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 COFF: Sections

Object File Target Memory

.bbs RAM

.data EEPROM

.text

ROM

Memory allocation
Chapter 2, Slide 6 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 COFF: Sections assembler directives
‹ You can create subsections of any section to give
you tighter control of the memory map. Subsections
are created using the .sect and .usect directives.
‹ Initialized sections contain data or code. The .text
and .data sections are initialized; named sections
created with the .sect assembler directive are also
initialized.
‹ Uninitialized sections sections reserve space in the
memory map for uninitialized data. The .bss section
is uninitialized; named sections created with the
.usect assembler directive are also uninitialized.
‹ Because most systems contain several types of
memory, using sections can help you use target
memory more efficiently.

Chapter 2, Slide 7 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 COFF: Sections assembler directives

Initialized sections
.text
.data
.sect “ section name”

Uninitialized sections
.bss symbol, size in bytes [, alignment[, bank offset] ]
symbol .usect “section name”, size in bytes [, alignment[, bank offset] ]

Chapter 2, Slide 8 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 COFF: Sections definition example
1 **************************************************
2 ** Assemble an initialized table into .data. **
3 **************************************************
4 00000000 .data
5 00000000 00000011 coeff .word 011h,022h
6 00000004 00000022
6 **************************************************
7 ** Reserve space in .bss for a variable. **
8 **************************************************
9 00000000 .bss var1,4
10 00000004 .bss buffer,40
11 **************************************************
12 ** Still in .data section **
13 **************************************************
14 00000008 00001234 ptr .word 01234h
15 **************************************************
16 ** Assemble code into .text section **
17 **************************************************
18 00000000 .text
19 00000000 00800528 sum: MVK 10,A1
20 00000004 021085E0 ZERO A4
...................

***************************************************
51 ** Define a named section for interrupt vectors **
52 ****************************************************
53 00000000 .sect ”vectors”
54 00000000 00000012’ B sum
55 00000004 00008000 NOP 5
Chapter 2, Slide 9 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 COFF: Sections linking process
‹ The linker produces executable COFF object
modules. An executable object file has the same
COFF format as object files that are used as linker
input; the sections in an executable object file,
however, are combined and relocated into target
memory.
‹ To run a program, the data in the executable object
module must be transferred, or loaded, into target
system memory

Loading a Program

COFF COFF
object file Linker executable file TARGET

Memory
Realocation
Chapter 2, Slide 10 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 COFF: Sections linking process

Chapter 2, Slide 11 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Assembler Description

Chapter 2, Slide 12 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Assembler Description
‹ The TMS320C6000 assembler translates assembly
language source files into machine language object
files. These files are in COF format (COFF).
‹ Source files can contain the following assembly
language elements:

ƒ Assembly language instructions

ƒ Assembler directive
ƒ Macro directives

Chapter 2, Slide 13 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Invoking the Assembler

asm6x [ input file [ object file [ listing file] ] ] [ options]

asm6x is the command that invokes the assembler

input file names the assembly language source file (.asm)
object file names the object file that the assembler creates (.obj)
listing file names the optional listing file that the assembler can create (.lst)
Options :
-@ filename appends the contents of a file to the command line.
-c makes case insignificant in the assembly language files.
-g makes case insignificant in the assembly language files.
-i specifies a directory where the assembler can find files named by .include
-l produces a listing file with the same name as the input file with a *.lst extension.
-s puts all defined symbols in the object file’s symbol table.
-x to obtain a cross-reference listing.
Chapter 2, Slide 14 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Assembly instructions

label: [||] [ condition] Instruction [unit] operands [;comment]

Label Identify a line of code or a variable and represent a memory address that
contains either an instruction or data. if used, they must begin in column 1.
|| An instruction that executes in parallel with the previous instruction
signifies this with parallel bars (||).
Condition There are five registers available for conditions: A1, A2, B0, B1, and
B2. If blank, the instruction always executes.
Instruction (See next slide)
Unit .D1 and .D2 Data/addition/subtraction.
.L1 and .L2 ALU/compares/long data arithmetic.
.M1 and .M2 Multiply. S1 and .S2
.S1 and .S2 Shift/ALU/branch/bit field
Operands Symbols, Cte or Expressions

Chapter 2, Slide 15 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Assembly Instructions: set by category
Arithmetic Logical Bit Data Program
Management Management Control
BS AND CLR LDB/H/W B
ADD CMPEQ EXT MV IDLE
ADDA CMPGT LMBD MVC NOP
ADDK CMPLT NORM MVK
ADD2 NOT SET MVKL
MPY OR MVKH
MPYH SHL MVKLH
NEG SHR STB/H/W
SMPY SSHL
SMPYH XOR
SADD
SAT
SSUB
SUB
SUBA
SUBC
SUB2
ZERO

Chapter 2, Slide 16 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Assembly Instructions: functionnal units
Register File A Register File B
A0 B0
A1
.S1
.S1 .S2
.S2 B1
A2 B2
A3 .M1 .M2 B3
.M1 .M2
A4 B4

. .L1 .L2 .
. .L1 .L2 .
. .

.D1
.D1 .D2
.D2
A15 B15

32-bits 32-bits

Memory
Chapter 2, Slide 17 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
Assembly Instructions: set by functional units
.S Unit .L Unit .M Unit .D Unit
ADD ABS MPY ADD
ADDK ADD MPYH ADDAB
ADD2 AND MPYLH (B/H/W)
AND CMPEQ MPYHL LDB
B CMPGT SMPY (B/H/W)
CLR CMPLT SMPYH MV
EXT LMBD NEG
MV MV STB
MVC NEG (B/H/W)
MVK NORM SUB
MVKL, MVKH NOT SUBAB
NEG OR (B/H/W)
NOT SADD ZERO
OR SAT
SET SSUB
SHL, SHR SUB
SSHL SUBC
SUB, SUB2 XOR
XOR ZERO
ZERO

Chapter 2, Slide 18 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Assembler directives
‹ Assembler directives supply data to the program and control
the assembly process. Assembler directives enable you to do
the following:
ƒ Assemble code and data into specified sections
ƒ Reserve space in memory for uninitialized variables
ƒ Control the appearance of listings
ƒ Initialize memory
ƒ Assemble conditional blocks
ƒ Define global variables
ƒ Specify libraries from which the assembler can
obtain macros
ƒ Examine symbolic debugging information

Chapter 2, Slide 19 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Assembler directives
‹ Directives that define sections

‹ Directives that initialize constants

Chapter 2, Slide 20 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Assembler directives
‹ Directives that enable conditional assembly

‹ Directives that align the section program counter

Chapter 2, Slide 21 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Assembler directives
‹ Directives that format the output listing

‹ Directives that reference other files

Chapter 2, Slide 22 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Assembler directives : Example
symbol .set value
symbol .equ value

1 00000001 AUX_R1 .set A1

2 00000000 00B802D4 STH AUX_R1,*+B14

3 00000035 INDEX .equ 100/2 +3

4 13000000 01001AD0 ADDK INDEX, A2

5 00000008 0000000A LABEL .word 10

6 00000009 SYMTAB .set LABEL + 1

.int value1 [, ... , value n]

.long value1 [, ... , value n]
.word value1 [ , ... , value n]

1 00000000 FFFFABCD DAT1: .long 0FFFFABCh,’A’+100h

00000004 00000141

1 00000000 00000C80 WordX: .word 3200,1+’AB’,–’AF’,0F410h,’A’

Chapter 2, Slide 23 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Macro Language
‹ The TMS320C6000 assembler supports a macro language
that enables you to create your own instructions. This is
especially useful when a program executes a particular task
several times. The macro language lets you:
ƒ Define your own macros and redefine existing
macros
ƒ Simplify long or complicated assembly code
ƒ Access macro libraries created with the Archiver
ƒ Define conditional and repeatable blocks within a
macro
ƒ Manipulate strings within a macro
ƒ Control expansion listing

Chapter 2, Slide 24 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Define the macro

macname .macro [ parameter1] [, ... , parameter n]

model statements or macro directives
[.mexit]
.endm

macname names the macro. You must place the name in the source
statement’s label field. The assembler places the macro name in the
internal opcode table, replacing any instruction or previous macro
definition with the same name.
.macro is the directive that identifies the source statement as the first line
of a macro definition.
.mexit is an assembly directive that functions as a goto.
.endm is the directive that terminates the macro definition.

Chapter 2, Slide 25 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Call & Expand the macro
Macro definition: The following code defines a macro, sadd4, with four parameters:

1 sadd4 .macro r1,r2,r3,r4

2 !
3 ! Sadd4 r1, r2 ,r3, r4
4 ! r1 = r1 + r2 + r3 + r4 (saturated)
5 !
6 SADD r1,r2,r1
7 SADD r1,r3,r1
8 SADD r1,r4,r1
9 .endm

Macro call: The following code calls the sadd4 macro with four arguments:

10
11 0000000 sadd4 A0,A1,A2,A3

Macro expansion: The following code shows the substitution of the macro definition for the macro
call. The assembler substitutes A0, A1, A2, and A3 for the r1, r2, r3, and r4 parameters of sadd4.

12 00000000 00040278 SADD A0,A1,A0

13 00000004 00080278 SADD A0,A2,A0
14 00000008 000C027 SADD A0,A3,A0

Chapter 2, Slide 26 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Accessing Macro Libraries

.mlib filename

.mlib When the assembler encounters the .mlib directive, it opens the
library named by filename and creates a table of the library’s
contents. If one of these macros is called, the assembler
extracts the entry from the library and loads it into the macro table.
filename the library name.

You can use the Archiver to create a macro library by including the desired files in
an archive. A macro library is no different from any other archive, except that the
assembler expects the macro library to contain macro definitions.

A macro library is a collection of files that contain macro definitions.

Chapter 2, Slide 27 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Archiver
‹ The TMS320C6000E Archiver lets you combine
several individual files into a single archive file.

‹ You can collect several macros into a macro library.

The assembler searches the library and uses the
members that are called as macros by the source
file.

‹ You can also use the archiver to collect a group of

object files into an object library.

‹ The linker includes in the library the members that

resolve external references during the link.

‹ The archiver allows you to modify a library by

deleting, replacing, extracting, or adding members.

Chapter 2, Slide 28 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Archiver

Chapter 2, Slide 29 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Accessing Macro Libraries

ar6x [–] command [ options] libname [ filename1 ... filename n]

ar6x is the command that invokes the archiver.

[–] command tells the archiver how to manipulate the existing library members
and any specified filenames. A command can be preceded by an
optional hyphen. You must use one of the following commands
when you invoke the archiver, but you can use only one command
per invocation. (@, a, d, r, t, x…)
options options In addition to one of the commands, you can specify
options. To use options, combine them with a command. (q, s, u,
v).
libname names the archive library to be built or modified. If you do no
specify an extension for libname, the archiver uses the default
extension .lib.
filenames names individual files to be manipulated. These files can be
existing library members or new files to be added to the library.
Chapter 2, Slide 30 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Archiver Exemple
ar6x –a function sine.obj cos.obj flt.obj

The archiver responds as follows:

TMS320C6x Archiver Version x.xx

Copyright (c) 1996–1997 Texas Instruments Incorporated
==> new archive ’function.lib’
==> building archive ’function.lib’

ar6x –t function

The archiver responds as follows:

TMS320C6x Archiver Version x.xx

Copyright (c) 1996–1997 Texas Instruments Incorporated
FILE NAME SIZE DATE
–––––––––––––––– ––––– ––––––––––––––––––––––––
sine.obj 300 Wed Apr 16 10:00:24 1997
cos.obj 300 Wed Apr 16 10:00:30 1997
flt.obj 300 Wed Apr 16 09:59:56 1997

Chapter 2, Slide 31 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Linker

Chapter 2, Slide 32 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Linker
‹ The TMS320C6000 linker allows you to configure
system memory by allocating output sections
efficiently into the memory map. As the linker
combines object files, it performs the following
tasks:
1. Allocates sections into the target system’s
configured memory
2. Relocates symbols and sections to assign them
to final addresses

‹ Two powerful directives, MEMORY and

SECTIONS, allow you to:

1. Allocate sections into specific areas of memory

2. Combine object file sections
3. Define or redefine global symbols at link time

Chapter 2, Slide 33 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Invoking the Linker

lnk6x [ options] filename 1 ... filename n

lnk6x command that invokes the linker.

options can appear anywhere on the command line or in a linker command
file.
filename can be object files, linker command files, or archive libraries. The
default extension for all input files is .obj, any other extension must
be explicitly specified. The linker can determine whether the input
file is an object or ASCII file that contains linker commands. The
default output filename is “a.out”, unless you use the - o option to
name the output file.

Chapter 2, Slide 34 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Linker options

Chapter 2, Slide 35 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Linker options

Chapter 2, Slide 36 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Linker : Memory directive
‹ The MEMORY directive identifies ranges of
memory that are physically present in the target
system and can be used by a program.
MEMORY {
Name 1 [ R/W/E/I ] : origin = constant, length = constant
…
Name n [ R/W/E/I ] : origin = constant, length = constant
}

Chapter 2, Slide 37 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Linker : Section directive
‹ The SECTIONS directive describes how input
sections are combined into output sections in
memory.
SECTIONS {
Name 1 : [ property [ , property] [ , property] . . . ]
Name n : [ property [ , property] [ , property] . . . ]
}

Chapter 2, Slide 38 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Linker : Section directive

Chapter 2, Slide 39 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Linker : command file Exemple
‹ The MEMORY directive is specified in a command
file by the word MEMORY (uppercase).
‹ The SECTIONS directive is specified in a command
file by the word SECTIONS (uppercase).

Chapter 2, Slide 40 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Cross-Reference Lister

‹ The TMS320C6000 cross-reference lister is a

debugging tool.
‹ This utility accepts linked object files as input and
produces a cross-reference listing as output. This
listing shows symbols, their definitions, and their
references in the linked source files.

Chapter 2, Slide 41 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Invoking the Cross-Reference Lister

xref6x [ options] [ input filename [ output filename] ]

xref6x is the command that invokes the cross-reference utility.

options precede each option with a hyphen (-). The cross-reference lister
options are as follows:
-l : specifies the number of lines per page for the
output file. The format of the -l option is -l num, where
num is a decimal constant. For example, -l 30 sets the
number of lines per page in the output file to 30. The
space between the option and the decimal constant is
optional. The default is 60 lines per page.
-q suppresses the banner and all progress information (run
quiet).
input file is a linked object file. If omitted, the utility prompts for a
filename
output file is the name of the cross-reference listing file.

Chapter 2, Slide 42 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Cross-Reference Listing exemple

Chapter 2, Slide 43 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Hex Conversion Utility

Chapter 2, Slide 44 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Hex Conversion Utility
‹ The TMS320C6000 assembler and linker create
object files that are in common object file format
(COFF). COFF is a binary object file format that
encourages modular programming and provides
powerful and flexible methods for managing code
segments and target system memory.
‹ Most EPROM programmers do not accept COFF
object files as input. The hex conversion utility
converts a COFF object file into one of several
standard ASCII hexadecimal formats, suitable for
loading into an EPROM programmer.
‹ The utility is also useful in other applications
requiring hexadecimal conversion of a COFF object
file (for example, when using debuggers and
loaders).

Chapter 2, Slide 45 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Hex Conversion Utility
‹ The hex conversion utility can produce these output
file formats:

ƒ ASCII-Hex, supporting 16-bit addresses

ƒ Extended Tektronix (Tektronix)
ƒ Intel MCS-86 (Intel)
ƒ Motorola Exorciser (Motorola-S), supporting
16-bit addresses
ƒ Texas Instruments SDSMAC (TI-Tagged),
supporting 16-bit addresses

Chapter 2, Slide 46 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Invoking the Hex Conversion Utility

hex6x [ options] filename

hex6x is the command that invokes the hex conversion utility.

options supplies additional information that controls the hex conversion
process. You can use options on the command line or in a
command file.
filename names a COFF object file or a command file. If you do not specify
a filenname, the utility prompts you for one.

Chapter 2, Slide 47 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Assembly coding Problems

Chapter 2, Slide 48 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Assembly coding Problems
a. Move contents of A0-->A1
MV .L1 A0, A1
or ADD .S1 A0, 0, A1
or MPY .M1 A0, 1, A1 (what’s the problem
with this?)

Chapter 2, Slide 49 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Assembly Coding Problems
a. Move contents of A0-->A1
MV .L1 A0, A1
or ADD .S1 A0, 0, A1
or MPY .M1 A0, 1, A1 (A0 can only be a
16-bit value)
b. Move contents of CSR-->A1
MVC CSR, A1
c. Clear register A5
ZERO .S1 A5
or SUB .L1 A5, A5, A5
or MPY .M1 A5, 0, A5
or CLR .S1 A5, 0, 31, A5
or MVK .S1 0, A5
or XOR .L1 A5,A5,A5
Chapter 2, Slide 50 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Assembly Coding Problems (cont’d)
d. A2 = A02 + A1
MPY.M1 A0, A0, A2
ADD.L1 A2, A1, A2
e. If (B1 ≠ 0) then B2 = B5 * B6
[B1] MPY.M2 B5, B6, B2
f. A2 = A0 * A1 + 10
MPY A0, A1, A2
ADD 10, A2, A2

g. Load an unsigned constant (19ABCh) into

register A6. value .equ 0x00019abc
mvkl.s1 0x00019abc,a6
mvkh.s1 0x00019abc,a6 mvkl.s1 value,a6
mvkh.s1 value,a6
Chapter 2, Slide 51 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Implementation of Sum of Products (SOP)
N
It has been shown in Y = ∑ an * xn
Chapter 1 that SOP is the n = 1
key element for most DSP = a1 * x1 + a2 * x2 +... + aN * xN
algorithms.
Two basic
So let’s write the code for
this algorithm and at the operations are required
same time discover the for this algorithm.
C6000 architecture.
(1) Multiplication
(2) Addition
Therefore two basic
instructions are required

Chapter 2, Slide 52 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Implementation of Sum of Products (SOP)
N
So let’s implement the SOP Y = ∑ an * xn
algorithm! n = 1
= a1 * x1 + a2 * x2 +... + aN * xN

The implementation in this Two basic

module will be done in operations are required
assembly.
for this algorithm.
(1) Multiplication
(2) Addition
Therefore two basic
instructions are required

Chapter 2, Slide 53 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Multiply (MPY)
N
Y = ∑ an * xn
n = 1
= a1 * x1 + a2 * x2 +... + aN * xN

The multiplication of a1 by x1 is done in

assembly by the following instruction:

MPY a1, x1, Y

This instruction is performed by a

multiplier unit that is called “.M”

Chapter 2, Slide 54 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Multiply (.M unit)
40
Y = ∑ an * xn
n = 1

.M
.M
The . M unit performs multiplications in
hardware

MPY .M a1, x1, Y

Note: 16-bit by 16-bit multiplier provides a 32-bit result.

32-bit by 32-bit multiplier provides a 64-bit result.
Chapter 2, Slide 55 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Addition (.?)
40
Y = ∑ an * xn
n = 1

.M
.M

.?
.? MPY .M a1, x1, prod
ADD .? Y, prod, Y

Chapter 2, Slide 56 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Add (.L unit)
40
Y = ∑ an * xn
n = 1

.M
.M

.L
.L MPY .M a1, x1, prod
ADD .L Y, prod, Y

RISC processors such as the C6000 use registers to

hold the operands, so lets change this code.
Chapter 2, Slide 57 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Register File - A
40
Register File A
Y = ∑ an * xn
A0 a1 n = 1
A1 x1
A2
A3 prod .M
.M
A4 Y

. .L
.
.
.L MPY .M a1, x1, prod
ADD .L Y, prod, Y

A15
32-bits

Let us correct this by replacing a, x, prod and Y by the

registers as shown above.
Chapter 2, Slide 58 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Specifying Register Names
40
Register File A
Y = ∑ an * xn
A0 a1 n = 1
A1 x1
A2
A3 prod .M
.M
A4 Y

. .L
.
.
.L MPY .M A0, A1, A3
ADD .L A4, A3, A4

A15
32-bits

The registers A0, A1, A3 and A4 contain the values to

be used by the instructions.
Chapter 2, Slide 59 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Specifying Register Names
40
Register File A
Y = ∑ an * xn
A0 a1 n = 1
A1 x1
A2
A3 prod .M
.M
A4 Y

. .L
.
.
.L MPY .M A0, A1, A3
ADD .L A4, A3, A4

A15
32-bits

Register File A contains 16 registers (A0 -A15) which

are 32-bits wide.
Chapter 2, Slide 60 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Data loading

Register File A Q: How do we load the

A0 a1 operands into the registers?
A1 x1
A2
A3 prod .M
.M
A4 Y

. .L
.
.
.L

A15
32-bits

Chapter 2, Slide 61 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Load Unit “.D”

Register File A Q: How do we load the

A0 a1 operands into the registers?
A1 x1
A2
A3 prod .M
.M
Y
A: The operands are loaded
into the registers by loading
. them from the memory
. .L
.L using the .D unit.
.

A15
.D
.D
32-bits

Data Memory
Chapter 2, Slide 62 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Load Unit “.D”

Register File A
It is worth noting at this
A0 a1 stage that the only way to
A1 x1 access memory is through the
A2 .D unit.
A3 prod .M
.M
Y

. .L
.
.
.L

A15
.D
.D
32-bits

Data Memory
Chapter 2, Slide 63 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Load Instruction

Register File A Q: Which instruction(s) can be

A0 a1 used for loading operands
A1 x1 from the memory to the
A2 registers?
A3 prod .M
.M
Y

. .L
.
.
.L

A15
.D
.D
32-bits

Data Memory
Chapter 2, Slide 64 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
Load Instructions (LDB, LDH,LDW,LDDW)

Register File A Q: Which instruction(s) can be

A0 a1 used for loading operands
A1 x1 from the memory to the
A2 registers?
A3 prod .M
.M
Y A: The load instructions.
. .L
.
.
.L

A15
.D
.D
32-bits

Data Memory
Chapter 2, Slide 65 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Using the Load Instructions

Before using the load unit you Data address

have to be aware that this 00000000
processor is byte addressable,
which means that each byte is 00000002
represented by a unique 00000004
address. 00000006
Also the addresses are 32-bit 00000008
wide.

FFFFFFFF

16-bits

Chapter 2, Slide 66 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Using the Load Instructions

The syntax for the load Data address

instruction is: 00000000
a1
x1 00000002
LD *Rn,Rm
00000004
prod 00000006
Where:
Y 00000008
Rn is a register that contains
the address of the operand to
be loaded
and
Rm is the destination register. FFFFFFFF

16-bits

Chapter 2, Slide 67 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Using the Load Instructions

The syntax for the load Data address

instruction is: 00000000
a1
x1 00000002
LD *Rn,Rm
00000004
prod 00000006
The question now is how many
bytes are going to be loaded Y 00000008
into the destination register?

FFFFFFFF

16-bits

Chapter 2, Slide 68 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Using the Load Instructions

The syntax for the load Data address

instruction is: 00000000
a1
x1 00000002
LD *Rn,Rm
00000004
The answer, is that it depends prod 00000006
on the instruction you choose: Y 00000008
• LDB: loads one byte (8-bit)
• LDH: loads half word (16-bit)
• LDW: loads a word (32-bit)
• LDDW: loads a double word (64-bit)
FFFFFFFF
Note: LD on its own does not
exist. 16-bits

Chapter 2, Slide 69 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Using the Load Instructions
Data address
The syntax for the load 1 0
instruction is: 0xA 0xB 00000000
0xC 0xD 00000002
LD *Rn,Rm
0x2 0x1 00000004
0x4 0x3 00000006
Example:
If we assume that A5 = 0x4 then: 0x6 0x5 00000008
(1) LDB *A5, A7 ; 0x8 0x7
gives A7 = 0x00000001
(2) LDH *A5,A7;
gives A7 = 0x00000201
(3) LDW *A5,A7; FFFFFFFF
gives A7 = 0x04030201
(4) LDDW *A5,A7:A6; 16-bits
gives A7:A6 = 0x0807060504030201
Chapter 2, Slide 70 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Using the Load Instructions

The syntax for the load Data address

instruction is: 0xA 0xB 00000000
0xC 0xD 00000002
LD *Rn,Rm
0x2 0x1 00000004
0x4 0x3 00000006
Question:
0x6 0x5 00000008
If data can only be accessed by the 0x8 0x7
load instruction and the .D unit,
how can we load the register
pointer Rn in the first place?

FFFFFFFF

16-bits

Chapter 2, Slide 71 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Loading the Pointer Rn
‹ The instruction MVKL will allow a
move of a 16-bit constant into a register
as shown below:
MVKL .? a, A5
(‘a’ is a constant or label)

‹ How many bits represent a full address?

32 bits
‹ So why does the instruction not allow a
32-bit move?
All instructions are 32-bit wide (see
instruction opcode).
Chapter 2, Slide 72 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Loading the Pointer Rn
‹ To solve this problem another instruction
is available:
MVKH
ah al a
eg. MVKH .? a, A5
ah x A5
(‘a’ is a constant or label)

‹ Finally, to move the 32-bit address to a

register we can use:

MVKL a, A5
MVKH a, A5

Chapter 2, Slide 73 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Loading the Pointer Rn
‹ Always use MVKL then MVKH, look at
the following examples:
Example 1
A5 = 0x87654321

MVKL 0x1234FABC, A5 MVKH 0x1234FABC, A5

A5 = 0xFFFFFABC (sign extension) A5 = 0x1234FABC ; OK

Example 2

MVKH 0x1234FABC, A5 MVKL 0x1234FABC, A5

A5 = 0x12344321 A5 = 0xFFFFFABC ; Wrong

Chapter 2, Slide 74 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 LDH, MVKL and MVKH

Register File A
A0 a MVKL pt1, A5
A1 x MVKH pt1, A5
A2 MVKL pt2, A6
A3 prod .M
.M MVKH pt2, A6
Y
LDH .D *A5, A0
. .L LDH .D *A6, A1
.
.
.L
MPY .M A0, A1, A3
ADD .L A4, A3, A4
A15
.D
.D
32-bits

Data Memory
Chapter 2, Slide 75 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Creating a loop

So far we have only

implemented the SOP MVKL pt1, A5
for one tap only, i.e. MVKH pt1, A5
MVKL pt2, A6
MVKH pt2, A6
Y= a1 * x1 LDH .D *A5, A0
LDH .D *A6, A1
MPY .M A0, A1, A3
So let’s create a loop
so that we can ADD .L A4, A3, A4
implement the SOP
for N Taps.

Chapter 2, Slide 76 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Creating a loop

So far we have only

implemented the SOP
for one tap only, i.e.
With the C6000 processors
there are no dedicated
Y= a1 * x1 instructions such as block
repeat. The loop is created
using the B instruction.
So let’s create a loop
so that we can
implement the SOP
for N Taps.

Chapter 2, Slide 77 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 What are the steps for creating a loop

1. Create a label to branch to.

2. Add a branch instruction, B.

3. Create a loop counter.

4. Add an instruction to decrement the loop counter.

5. Make the branch conditional based on the value in

the loop counter.

Chapter 2, Slide 78 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 1. Create a label to branch to
MVKL pt1, A5
MVKH pt1, A5
MVKL pt2, A6
MVKH pt2, A6

loop LDH .D *A5, A0

LDH .D *A6, A1
MPY .M A0, A1, A3
ADD .L A4, A3, A4

Chapter 2, Slide 79 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 2. Add a branch instruction, B.
MVKL pt1, A5
MVKH pt1, A5
MVKL pt2, A6
MVKH pt2, A6

loop LDH .D *A5, A0

LDH .D *A6, A1
MPY .M A0, A1, A3
ADD .L A4, A3, A4
B .? loop

Chapter 2, Slide 80 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Which unit is used by the B instruction?
MVKL pt1, A5
Register File A
MVKH pt1, A5
A0 a .S
.S MVKL pt2, A6
A1 x MVKH pt2, A6
A2
prod .M
.M
A3 .M
.M
Y loop LDH .D *A5, A0
. LDH .D *A6, A1
. .L
.L
. .L
.L MPY .M A0, A1, A3
ADD .L A4, A3, A4
.D
.D B .? loop
A15 .D
.D
32-bits

Data Memory
Chapter 2, Slide 81 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Which unit is used by the B instruction?
MVKL .S pt1, A5
Register File A
MVKH .S pt1, A5
A0 a .S
.S MVKL .S pt2, A6
A1 x MVKH .S pt2, A6
A2
prod .M
.M
A3 .M
.M
Y loop LDH .D *A5, A0
. LDH .D *A6, A1
. .L
.L
. .L
.L MPY .M A0, A1, A3
ADD .L A4, A3, A4
.D
.D B .S loop
A15 .D
.D
32-bits

Data Memory
Chapter 2, Slide 82 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 3. Create a loop counter.
MVKL .S pt1, A5
Register File A
MVKH .S pt1, A5
A0 a .S
.S MVKL .S pt2, A6
A1 x MVKH .S pt2, A6
A2 MVKL .S count, B0
prod .M
.M
A3 .M
.M
Y loop LDH .D *A5, A0
. LDH .D *A6, A1
. .L
.L
. .L
.L MPY .M A0, A1, A3
ADD .L A4, A3, A4
.D
.D B .S loop
A15 .D
.D
32-bits
B registers will be introduced later

Data Memory
Chapter 2, Slide 83 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 4. Decrement the loop counter
MVKL .S pt1, A5
Register File A
MVKH .S pt1, A5
A0 a .S
.S MVKL .S pt2, A6
A1 x MVKH .S pt2, A6
A2 MVKL .S count, B0
prod .M
.M
A3 .M
.M
Y loop LDH .D *A5, A0
. LDH .D *A6, A1
. .L
.L
. .L
.L MPY .M A0, A1, A3
ADD .L A4, A3, A4
.D
.D SUB .S B0, 1, B0
A15 .D
.D
B .S loop
32-bits

Data Memory
Chapter 2, Slide 84 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 5. Make the branch conditional based on the
value in the loop counter
‹ What is the syntax for making instruction
conditional?
[condition] Instruction Label
e.g.
[B1] B loop

(1) The condition can be one of the following

registers: A1, A2, B0, B1, B2.
(2) Any instruction can be conditional.

Chapter 2, Slide 85 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 5. Make the branch conditional based on the
value in the loop counter
‹ The condition can be inverted by adding the
exclamation symbol “!” as follows:
[!condition] Instruction Label
e.g.
[!B0] B loop ;branch if B0 = 0
[B0] B loop ;branch if B0 != 0

Chapter 2, Slide 86 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 5. Make the branch conditional
MVKL .S2 pt1, A5
Register File A
MVKH .S2 pt1, A5
A0 a .S
.S MVKL .S2 pt2, A6
A1 x MVKH .S2 pt2, A6
A2 MVKL .S2 count, B0
prod .M
.M
A3 .M
.M
Y loop LDH .D *A5, A0
. LDH .D *A6, A1
. .L
.L
. .L
.L MPY .M A0, A1, A3
ADD .L A4, A3, A4
.D
.D SUB .S B0, 1, B0
A15 .D
.D
[B0] B .S loop
32-bits

Data Memory
Chapter 2, Slide 87 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 More on the Branch Instruction (1)

‹ With this processor all the instructions are

encoded in a 32-bit.
‹ Therefore the label must have a dynamic range
of less than 32-bit as the instruction B has to be
coded.
32-bit

B 21-bit relative address

‹ Case 1: B .S1 label

‹ Relative branch.
‹ Label limited to +/- 220 offset.

Chapter 2, Slide 88 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 More on the Branch Instruction (2)

‹ By specifying a register as an operand instead

of a label, it is possible to have an absolute
branch.
‹ This will allow a dynamic range of 232.

32-bit
5-bit register
B code

‹ Case 2: B .S2 register

‹ Absolute branch.
‹ Operates on .S2 ONLY!

Chapter 2, Slide 89 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Testing the code
MVKL .S2 pt1, A5
MVKH .S2 pt1, A5
MVKL .S2 pt2, A6
MVKH .S2 pt2, A6
This code performs the following MVKL .S2 count, B0
operations:
loop LDH .D *A5, A0

a0*x0 + a0*x0 + a0*x0 + … + a0*x0 LDH .D *A6, A1

MPY .M A0, A1, A3
However, we would like to perform: ADD .L A4, A3, A4
a0*x0 + a1*x1 + a2*x2 + … + aN*xN SUB .S B0, 1, B0
[B0] B .S loop

Chapter 2, Slide 90 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Modifying the pointers
MVKL .S2 pt1, A5
MVKH .S2 pt1, A5
MVKL .S2 pt2, A6
MVKH .S2 pt2, A6
MVKL .S2 count, B0

The solution is to modify the pointers loop LDH .D *A5, A0

LDH .D *A6, A1
A5 and A6.
MPY .M A0, A1, A3
ADD .L A4, A3, A4
SUB .S B0, 1, B0
[B0] B .S loop

Chapter 2, Slide 91 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Indexing Pointers
Pointer
Syntax Description
Modified
*R Pointer No

In this case the pointers are used but not modified.

R can be any register

Chapter 2, Slide 92 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Indexing Pointers
Pointer
Syntax Description
Modified
*R Pointer No
*+R[disp] + Pre-offset No
*-R[disp] - Pre-offset No

In this case the pointers are modified BEFORE being used

and RESTORED to their previous values.

Š [disp] specifies the number of elements size in DW (64-bit), W

(32-bit), H (16-bit), or B (8-bit).
Š disp = R or 5-bit constant.
Š R can be any register.
Chapter 2, Slide 93 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Indexing Pointers
Pointer
Syntax Description
Modified
*R Pointer No
*+R[disp] + Pre-offset No
*-R[disp] - Pre-offset No
*++R[disp] Pre-increment Yes
*--R[disp] Pre-decrement Yes

In this case the pointers are modified BEFORE being used

and NOT RESTORED to their Previous Values.
Chapter 2, Slide 94 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Indexing Pointers
Pointer
Syntax Description
Modified
*R Pointer No
*+R[disp] + Pre-offset No
*-R[disp] - Pre-offset No
*++R[disp] Pre-increment Yes
*--R[disp] Pre-decrement Yes
*R++[disp] Post-increment Yes
*R--[disp] Post-decrement Yes

In this case the pointers are modified AFTER being used

and NOT RESTORED to their Previous Values.
Chapter 2, Slide 95 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Indexing Pointers
Pointer
Syntax Description
Modified
*R Pointer No
*+R[disp] + Pre-offset No
*-R[disp] - Pre-offset No
*++R[disp] Pre-increment Yes
*--R[disp] Pre-decrement Yes
*R++[disp] Post-increment Yes
*R--[disp] Post-decrement Yes

Š [disp] specifies # elements - size in DW, W, H, or B.

Š disp = R or 5-bit constant.
Š R can be any register.
Chapter 2, Slide 96 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
 Modify and testing the code
MVKL .S2 pt1, A5
MVKH .S2 pt1, A5
MVKL .S2 pt2, A6
MVKH .S2 pt2, A6
MVKL .S2 count, B0

This code now performs the following loop LDH .D *A5++, A0

operations:
LDH .D *A6++, A1
a0*x0 + a1*x1 + a2*x2 + ... + aN*xN
MPY .M A0, A1, A3
ADD .L A4, A3, A4
SUB .S B0, 1, B0
[B0] B .S loop

Chapter 2, Slide 97 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Store the final result
MVKL .S2 pt1, A5
MVKH .S2 pt1, A5
MVKL .S2 pt2, A6
MVKH .S2 pt2, A6
MVKL .S2 count, B0

This code now performs the following loop LDH .D *A5++, A0

operations:
LDH .D *A6++, A1
a0*x0 + a1*x1 + a2*x2 + ... + aN*xN
MPY .M A0, A1, A3
ADD .L A4, A3, A4
SUB .S B0, 1, B0
[B0] B .S loop
STH .D A4, *A7

Chapter 2, Slide 98 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Store the final result
MVKL .S2 pt1, A5
MVKH .S2 pt1, A5
MVKL .S2 pt2, A6
MVKH .S2 pt2, A6
MVKL .S2 count, B0

loop LDH .D *A5++, A0

The Pointer A7 has not been initialised.
LDH .D *A6++, A1
MPY .M A0, A1, A3
ADD .L A4, A3, A4
SUB .S B0, 1, B0
[B0] B .S loop
STH .D A4, *A7

Chapter 2, Slide 99 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Store the final result
MVKL .S2 pt1, A5
MVKH .S2 pt1, A5
MVKL .S2 pt2, A6
MVKH .S2 pt2, A6
MVKL .S2 pt3, A7
MVKH .S2 pt3, A7
MVKL .S2 count, B0
The Pointer A7 is now initialised.
loop LDH .D *A5++, A0
LDH .D *A6++, A1
MPY .M A0, A1, A3
ADD .L A4, A3, A4
SUB .S B0, 1, B0
[B0] B .S loop
STH .D A4, *A7

Chapter 2, Slide 100 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 What is the initial value of A4?
MVKL .S2 pt1, A5
MVKH .S2 pt1, A5
MVKL .S2 pt2, A6
MVKH .S2 pt2, A6
MVKL .S2 pt3, A7
MVKH .S2 pt3, A7
A4 is used as an accumulator, MVKL .S2 count, B0
so it needs to be reset to zero. ZERO .L A4
loop LDH .D *A5++, A0
LDH .D *A6++, A1
MPY .M A0, A1, A3
ADD .L A4, A3, A4
SUB .S B0, 1, B0
[B0] B .S loop
STH .D A4, *A7

Chapter 2, Slide 101 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005

 Increasing the processing power!
Register File A
A0
.S1
.S1
A1
A2
How can we add
A3 .M1
more processing
.M1
A4 power to this
. .L1
processor?
. .L1
.
.D1
.D1
A15
32-bits

Data Memory
Chapter 2, Slide 102 Hassen AZIZA, Polytech'Marseille, (c) Septembre 2005
Chapter 1

- End -