The Design and Simulation

of Lateral SiC Power

Devices for Satellite Power
Supply Applications
A presentation to ESCCON 2021

Dr Peter Gammon1, Yunyi Qi1, Dr Marina Antoniou1 and Philippe Fayt2

1University of Warwick, United Kingdom
2Thales Alenia Space, Belgium
Introduction
The UK’s Engineering and Physical Sciences Research
Council (EPSRC) have funded the University of Warwick’s
project entitled Silicon Carbide Power Conversion for
Telecommunications Satellite Applications.
• The project runs from April 2021 to September 2024
• The project will be supported by Thales Alenia Space, Clas-SiC
Wafer Fab, Micross and the Compound Semiconductor
Applications Catapult.
The project will focus on the development of radiation-hard SiC
power devices for satellite applications.
Contents
• Motivation for SiC Power Devices in Telecommunications
Satellites
• SEE testing on COTS SiC Power Devices
• SEE Simulation of Vertical and Lateral SiC Power Devices
• SEE-Tolerant SiC RESURF Devices
• Conclusions
Motivation for SiC Power Devices in
Telecommunications Satellites

Electronic Power Conditioners (EPCs)

EPC Base Plate at 60°C

High Voltage Cables

Travelling Wave Tubes (TWTs)

TWT Base Plate at 85°C

A Typical Telecom Satellite Payload

Image courtesy of project partners Thales Alenia Space
Motivation for SiC Power Devices in
Telecommunications Satellites
Existing Si power devices are limited to 110°C
junction temperature after derating. This requires
an EPC base plate rating of up to 60°C.
The low efficiency of the TWT heats its base plate
up to 85°C.

This discrepancy in temperature:

• Prevents co-mounting of the TWT and EPC
• Requires 1.5m of heavy cabling between the TWT
and EPC.

Smart Topology of an EPC

Images courtesy of project partners Thales Alenia Space
Motivation for SiC Power Devices in
Telecommunications Satellites
The aim of this project is to replace all Si parts in
the EPC with 1200 V SiC MOSFETs and Schottky
diodes rated to 225°C.

The primary motivation for this is to enable an increase of

the EPC baseplate to at least 85°C and hence the co-
mounting of the EPC and TWT.

This will enable:

• Heavy cables to be shortened to ~20 cm.
• A lower cost and faster final payload integration
• Up to 33% more EPC dissipation capability due to better
thermal radiation (T4) outside the satellite
Smart Topology of an EPC
Images courtesy of project partners Thales Alenia Space
Motivation for SiC Power Devices in
Telecommunications Satellites
The aim of this project is to replace all Si parts in
the EPC with 1200 V SiC MOSFETs and Schottky
diodes rated to 225°C.

The secondary motivation for this is to produce a lighter,

smaller and/or more efficient EPC, achieved through
enabling faster switching speeds, and hence smaller
passive components.

Combined, these benefits could enable increase

TWT/EPC capacity, potentially adding 16 more RF
channels.

Smart Topology of an EPC

Images courtesy of project partners Thales Alenia Space
SEE testing on COTS SiC Power Devices
The electrical requirements to meet the brief for a TAS EPC are
simple enough to obtain in SiC. Focussing on just the diode:

• 1200 V Breakdown Voltage (VBD)

• Notional 2 A forward current (IF) rating
• Minimal leakage (IR) and forward voltage drop (VF) requirements.
• 225°C Temperature rating (Tmax)

These could be obtained with a standard (e.g. automotive

focussed) SiC diode chip, repackaged to achieve the Tmax.
SEE testing on COTS SiC Power Devices
However, the standard ESA radiation requirements, in particular
the SEE immunity level (> 60 MeV.cm2/mg), are a more
challenging prospect for SiC discretes.
Presented here are experimental results published1 on a
Wolfspeed 1200 V 20A (C4D020120A) diode in an open package.

1Witulski et al. "Single-event burnout of SiC junction

barrier Schottky diode high-voltage power devices." IEEE
Xe @ 49 MeV.cm2/mg; [email protected] MeV.cm2/mg Transactions on Nuclear Science 65.1 (2017): 256-261.
 SEE Simulation of Vertical SiC Power Devices
In a terrestrial COTS SiC device, there is every motivation to use
a vertical designed power device structure. This is the most
efficient layout to achieve a VBD, while minimising the area
required to attain the required IF.
Yet, the geometries of a vertical device
mean that a heavy ion will always traverse
Device Area = Current Rating the drift region, creating electron-hole
e.g. 1x1 mm ≈ 2 A pairs as it goes.
Anode contact
lDrift lSubs
N- Drift Region

Drift width = Voltage Rating

N- Drift N+
e.g. 10 µm = 1200 V e- h+ h+ h+ e-e- h+ e- h+

Cathode
a)

Anode
e- h+ e- e- h+ e- h+ e- e-
N- Drift Region e- e- h+ e- h+ e- e- h+ e-
h+ e- h+ e- h+ h+ h+ e-
e-
N+ Substrate
VR
Cathode contact
SEE Simulation of Vertical SiC Power Devices VR = 800 V; LET = 60 MeV.cm2/mg
Our simulations have revealed the extent of
the SEE problem in vertical SiC power devices:
• As the device is in its off state pre-strike, it is
blocking a large voltage when the device is off, with
a large peak electric field.
• The heavy ion tears through the drift creating
electron-hole pairs.
• Their presence prevents e-field being supported
locally, squeezing the e-field into ever smaller
regions at the end, creating large e-field spikes lDrift lSubs
• The reverse bias initiates carrier sweep out but the
movement of charge + large voltage creates power, N- Drift N+
e- h+ h+ h+ e-e- h+ e- h+

Cathode
and hence very high temperature. a)

Anode
e- h+ e- e- h+ e- h+ e- e-
e- e- h+ e- h+ e- e- h+ e-
h+ e- h+ e- h+ h+ h+ e-
• The extreme local temperatures cause permanent VR
e-

damage.
 SEE Simulation of Vertical SiC Power Devices lDrift lSubs

Our simulations have revealed the extent of N- Drift

e- h+ h+ e- h+ e- h+
N+

Cathode
a) e- h+ e-h+e- h+ e-

Anode
e- h+ e- e-

the SEE problem in vertical SiC power devices: VR

e- e- h+ e- h+ e- e- h+ e-
h+ e- h+ e- h+ h+ h+ e-
e-

The plots below show the maximum localised e-field spikes and temperatures
simulated in the drift region at various LETs/voltages for a 1200 V rated device:
Maximum Temperature (K) Peak Electric Field (MV/cm)
1985 5.080

1776 4.626
1000 1000
1566 4.173
Reverse Voltage (V)

Reverse Voltage (V)

1357 3.719

1148 3.265

938.1 2.811
500 500

728.8 2.357

519.4 1.904

310.0 1.450

20 40 60 20 40 60
Linear Energy Transfer (MeV/(cm^2/mg)) Linear Energy Transfer (MeV/(cm^2/mg))
 SEE Simulation of Vertical SiC Power Devices lDrift lSubs

Our simulations have revealed the extent of the SEE problem in N- Drift
e- h+ h+ e- h+ e- h+
N+

Cathode
a) e- h+ e-h+e- h+ e-

Anode
e- h+ e- e-

vertical SiC power devices: VR

e- e- h+ e- h+ e- e- h+ e-
h+ e- h+ e- h+ h+ h+ e-
e-

The plots below show the maximum localised e-field spikes and temperatures
simulated in the drift region at various LETs/voltages for a 1200 V rated device:
Maximum Temperature (K)
1985

1776
1000
1566
Reverse Voltage (V)

1357

Burnout
1148

938.1
500
Leakage 728.8

519.4
No Damage
310.0

20 40 60
Practical SiC diode results
Linear Energy Transfer (MeV/(cm^2/mg)) Experimental limits From: 1 Witulski et al. IEEE Transactions on Nuclear Science 65.1 (2017): 256-261.
 SEE Simulation of Lateral SiC Power Devices
lDrift lSubs
Issues with vertical SiC devices parallel Si, SOI and GaN. b) c) d)

Like these, a rad-hard SiC device should be lateral. N- Drift N+

Cathode
a)

Anode
To show this, heavy ions were fired laterally, across the drift region VR

in 3 positions. Here are the e-field results in (b) 1 µm from surface.

Peak Electric Field (MV/cm)
3.480

3.074
1000
2.668
Reverse Voltage (V)

2.261

1.855

1.449
500

1.043

0.6362

0.2300

20 40 60
Linear Energy Transfer (MeV/(cm^2/mg))
 SEE Simulation of Lateral SiC Power Devices
lDrift lSubs
Issues with vertical SiC devices parallel Si, SOI and GaN. b) c) d)

Like these, a rad-hard SiC device should be lateral. N- Drift N+

Cathode
a)

Anode
The temperature plots form the three locations show temp VR

rise of <60 K and 15 K variation in the 3 locations

Maximum Temperature Maximum Temperature Maximum Temperature

352.8 359.6 345.6

346.2 352.2 339.9

1000 1000 1000
339.6 344.8 334.3
Reverse Voltage (V)

Reverse Voltage (V)

Reverse Voltage (V)
333.1 337.3 328.6

326.5 329.9 322.9

319.9 322.5 317.2

500 500 500

313.4 315.1 311.6

306.8 307.6 305.9

300.2 300.2 300.2

20 40 60 20 40 60 20 40 60
Linear Energy Transfer (MeV/(cm^2/mg)) Linear Energy Transfer (MeV/(cm^2/mg)) Linear Energy Transfer (MeV/(cm^2/mg))

Position (b) – 1 µm from surface Position (c) – 5 µm from surface Position (d) – 9 µm from surface
SEE-Tolerant SiC RESURF Devices
Like Si, SOI and GaN before, it is clear that SiC can be made
rad-hard if it is properly designed for. Our first fully-optimised
SiC lateral RESURF design is depicted below.
SEE/Radiation Tolerance
• The lateral design means there is little chance
of a heavy ion traversing the full drift region,
minimising the e-field peak.
• Incorporating the P-/P+ regions act as a sink
for holes, making their extraction much easier,
and minimising temperature rises. (Field Plate)

Anode Field Oxide Cathode

• In our aggressive design, local temperature is
limited to 78 K at 60 MeV.cm2/mg and N-
P+
VR=1200 V. More conservative designs can P-
limit this to <50 K. SiC Substrate
SEE-Tolerant SiC RESURF Devices
Use of field plates and fine control of the
doping/width of the N- layer allows VBD to
be maximised and RON minimised
Electrical Properties
• The RESURF/charge balance effect means the
10 µm drift region supports a VBD of 1800 V.
• The current rating will depend on the length
and number of the anode/cathode stripes.
• The p- and n- layers can be grown and their
doping finely controlled via CVD epitaxy.
(Field Plate)
• Various ideas are being considered to isolate
Field Oxide
the device area from the substrate – either a Anode Cathode

P+ interlayer, or even a semi-insulating layer. N-

P+
• Design is easily adapted for a MOSFET layout P-
once diode is proven. SiC Substrate
Conclusions
The EPSRC project Silicon Carbide Power Conversion for
Telecommunications Satellite Applications begins in April 2021
• Replacing Si technology with high temp SiC devices in a Thales Alenia
Space EPC will improve payload integration, potentially freeing up space
for 16 more RF channels.
• Radiation hardening SiC power devices remains the biggest challenge, one
that requires a shift away from conventional (e.g. automotive) vertical
device architectures
• Preparatory simulations dispel the myth that SiC cannot be radiation
hardened without considerable derating. Lateral RESURF architectures,
similar to those used in Si and SOI, show great promise.
• Over the 3.5 year project, device designs will be fabricated in-house at
Warwick, packaged at Micross, radiation tested at UC Louvain, and
delivered for testing/integration at TAS.