Teach Computer Science

A-level

Computer architecture

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Lesson Objectives
Students will learn about:
Various components of a computer such as memory and
processor.
How are these components connected?
How data is accessed from memory? How are contents copied
to memory?
How are programs executed?
Interrupts

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Content

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Introduction
Systems architecture refers to the structure of the internal components of
a computer system.

Modern computers often have a von Neumann architecture, which

involves: a processor; a memory unit, which stores both instructions and
data; connections for input and output devices; & secondary storage for
data.

The fetch-decode-execute cycle describes how instructions are retrieved &

processed in order to run a program. Several factors affect processor
performance, including the number of cores & the size of the cache.

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Introduction 5

Computer architecture refers to the structure and

organisation of a computer system. It specifies the
components that make up a computer system &
describes how these are interconnected, how they
interact with each other, & how they are managed.

In early days, programming was performed by

manually setting the position of a large number of
switches & plugs, & then entering the input data. The
output was produced by determining the position of
some of the switches.

E.g the Colossus - set of computers developed from

1943 to 1945 to decipher the enemy coded messages
during WW2.
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Introduction 6

Early computers could not store data - nedd for

techniques that would allow programs & data to be
read from an easy-to-access source.

Tackling issues - new model for computer systems with

memory unit that could store data/programs. The
concept of having a stored program into working
(electrical) memory, was a major step forward; can fetch
instructions from the memory unit & executed
sequentially by a processing unit that performs
arithmetic & logical operations.

First electronic computer with RAM - the Manchester

Baby, made by the University of Manchester in 1948;
ENIAC presented in 1946 teachcomputerscience.com
von Neumann Architecture 7

Very early computers could not store programs &,

hence, in 1945, John von Neumann developed an
idea of a computer that could store programs - von
Neumann architecture.

Architecture used idea that data & programs could

be stored in memory & that the data would be
transferred between the memory & the processor
during processing.

Neumann architecture is used in many modern-

day computer systems - comprises:
• a Processor
• a Memory unit that can communicate directly Von Neumann architecture model
with the processor
• connections for input and output devices
• Secondary storage for saving/backing up data teachcomputerscience.com
von Neumann Architecture 8

Processor can access the instructions & data

in the main memory as required to execute
the program. Uses dedicated connections
called buses:
• an address bus is used to identify the
addressed location
• a data bus is used to transfer the
contents to/from that location

This means that the same address & data

buses are used in the process of
transferring instructions & data btn main
memory & the processor. A third bus,
the control bus, is used to synchronise & Von Neumann architecture model
control operations.
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Harvard Architecture 9

Harvard architecture (HA) keeps instructions

& data in separate memories
Processor accesses these memories using
separate data & address buses; the
processor is connected to the ‘instructions
memory’ using a dedicated set of address &
data buses, & is connected to the ‘data
memory’ using a different set of address &
data buses
HA is used extensively in embedded systems,
for example in digital signal processing (DSP)
systems
Many microcontroller devices use a Harvard-
like architecture. Some types of smartphones
use a modified HA Harvard architecture model

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Comparison - Harvard (HA) & Neumann architectures (NA)
10

HA uses separate memory units & buses for instructions & data i.e. both memories can be accessed
simultaneously. This minimises the issue of keeping the processor waiting while loading or saving data
into memory, helps increases the processor performance. NA uses the same address & data buses for
both instructions & data - both instructions & data share the same pathways.
In HA each memory can be adapted to meet the needs of a particular system: the instruction & data
memories can be different sizes, different word lengths, or implemented using a different type of
technology. E.g. for systems with a predetermined use (such as embedded systems), the instruction
memory can be implemented as a ROM which protects the programs from accidental or deliberate
changes by hacking. NA allows for the instructions & data to be saved in the same memory, which can be
exploited by hackers who could disguise instructions (malware) as data that the processor may execute
unknowingly when attempting to read the data.
HA is commonly used in embedded systems, i.e. computer systems that are designed purposefully to
perform a specific set of operations & are used in situations where the speed of operation is very
important e.g. embedded systems such as traffic-control cameras are required to process large amounts
of data in real time.
NA enables a more flexible use of the main memory - allows the processor to run a variety of programs
that are not known in advance. NA is commonly used in general-purpose computers that are expected to
accommodate the varying needs of the end users e.g run numerous applications & switch between
different tasks. teachcomputerscience.com
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Internal components of a computer
The internal components of a computer system consist of the hardware
required to process data & to allow the processor to communicate with other
devices such as secondary storage, display screens, and printers.

The main internal components of a computer system are:

• Processor (CPU)
• Main memory
• Input/output (I/O) controllers

These components are connected together by high-speed

communication buses.

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The processor or Central Processing Unit (CPU)
12

CPU is responsible for the processing of the instructions given to a

computer.
It consists of arithmetic logic unit (ALU), control unit (CU) & cache memory.
The hardware of CPU is made of billions of transistors that form logic
gates.
For the CPU to be able to execute a program, the program instructions
need to be transferred from secondary storage into main memory from
where they can be fetched, decoded, & executed.
The data that needs to be processed is also loaded into main memory
(from secondary storage) or provided by the input and output devices via
the I/O controllers.
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4 000 000 000

A 4 GHz processor processes these many instructions per
second.

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 It would appear that we have
reached the limits of what it is
possible to achieve with computer
technology, although one should be
careful with such statements, as they
tend to sound pretty silly in 5 years.
-John von Neumann

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The buses
Buses connect components of a computer system together . A
bus - communication system that is used to transfer data btn
components.
• System bus - set of parallel connections that allow internal
components to communicate with each other & exchange
data.
• External buses - used to connect the peripherals to the
processor. These can be serial or parallel connections.

Buses can be implemented in different ways, depending on their

intended use, e.g wires, electronic pathways, & tracks on printed
circuits. teachcomputerscience.com
A model of the system bus - von Neumann 16

architecture
von Neumann architecture shows the components of a
computer in detail.
It shows the connection btn the CPU, memory & I/O controllers
using buses.
Three different kinds of buses are the address bus, control bus
and data bus.

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A model of the system bus - von Neumann 17

architecture
The following diagram illustrates an abstract model of the connections

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Buses 18

Type of
Function Direction of bus
bus
Transmits the address Unidirectional: From
Address from the CPU to the processor to
bus memory or I/O memory & I/O
controller controllers to devices

Sends data between

Data bus the CPU, memory & I/O Bidirectional
controllers
Bidirectional: From
Remember that each bus Signals sent by CPU to
Control the processor to
consists of a set of parallel — bus
control the memory &
memory & I/O
not single — lines. peripheral devices
controllers to devices

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Address bus (AB) 19

Used to specify the address of a memory location to either read (i.e. load)
data from or write (i.e. store) data to that memory location.

Unidirectional bus - allows CPU to establish a one-way connection with

an addressable 'unit', whether it's a memory location or an I/O controller.

The width of the address bus refers to its number of parallel lines, which
determines the number of bits that can be used to form an address of
a memory location. It is typically a multiple of a byte (e.g. 8, 16, 32, or 64
bits).
• If width of AB is 8 bits - 28 numbers that can be used to address memory
locations
• If width of AB is 16 bits - 216 numbers that can be used to address memory
locations teachcomputerscience.com
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Address bus (AB)

In general, if width of the AB is expressed as n bits, then there

are 2n numbers that can be used to address memory
locations.

Therefore, the width of the address bus determines the

maximum number of addressable memory locations, i.e.
the maximum memory capacity of a computer system. This is
called the address space & it can affect processor
performance.

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Data bus (DB)
Used to transfer data & instructions. It is bidirectional, i.e. it
allows a two-way connection btn internal components of the
system — allowing values to be written to or read from a
location.
• Data is transferred to & from the processor
• Data is transferred to & from main memory
• Data is transferred to & from the I/O controllers
• Instructions are carried from main memory into the CPU
(to be decoded & executed)

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Data bus (DB) 22

Width of the DB refers to its number of parallel lines. This

determines the number of bits that can be transferred in one
operation e.g. how many bits can be transferred in one go btn the
memory & CPU. Typically a multiple of a byte (e.g. 8, 16, 32, or 64
bits).
• If width of DB is 8 bits, then 8 bits can be transferred at one time
• If width of DB is 16, then 16 bits can be transferred at one time

In general, if the width of the DB is expressed as n bits, then n bits

can be transferred at one time. The amount of data that can be
fetched at one time can affect the processor performance

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Control bus (CB) 23

Used to send control signals that manage & orchestrate the

operations that take place inside a computer system.
Includes exchanging status signals btn the components of the
computer system, & transmitting clock signals required for the
coordination of operations e.g, a control signal can be used to:
• Request communication btn two units
• Acknowledge a communication request
• Specify the type of data that is being transferred via the other buses (i.e.
data values, instructions, or addresses)
• Synchronise the communication btn the components using the clock pulses

Bidirectional, i.e. there are two-way connections btn the components

that the CB connects.
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Control bus (CB) 24

Examples of control signals include:

• Memory read: Places data from a specific memory location (whose
address is on the AB) onto the DB
• Memory write: Stores the data from the DB onto a specific memory
location (whose address is on the AB)
• Bus request: Signifies that a component needs to access a bus
• Bus grant: Signifies that a component is informed that it can use the bus it
requested access to
• Bus busy: Signifies that a bus is not available for use (as it is used by
another component)
• Interrupt request: Signifies that an error or exception has occurred that
requires the attention of the CPU
• Clock signals: The control bus supplies the components with clock pulses
generated by the system clock or synchronises the operations on a
computer
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Memory Unit
Memory device is a device to which we store binary info & this info
is stored in order to be retrieved at a later time to be used.
Therefore, the memory is the unit which info available for
processing when needed and as needed
The memory unit is a collection of cells that are capable of storing
very large amounts of binary info.
In digital systems we distinguish 2 types of memory i.e. RAM
(Random-access memory) and Read-only memory (ROM)
The process of transferring new info into the RAM memory is
called READ operation and the process of transferring info out of
the memory is called the WRITE operation

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Memory Unit and Data storage
A binary digit (or bit) is the fundamental unit of data storage, and
will have a value of 0, or 1. A group of eight bits is called a byte. Four-
bit numbers are called a nibble.

Historically, storage capacity was expressed using the metric prefixes

of kilo (1,000), mega (1,000,000), etc. Since 1998 there has been a
move towards using the special prefixes developed to more
accurately represent binary values (as per the International System of
Units (SI) definition). For example, a kibibyte is equal to 1,024 bytes,
whereas a kilobyte is equal to 1,000 bytes.

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Memory Unit and Data storage 27

The differences between the Name Notation Power of 10 Value

3
two systems are shown below, kilobyte kB 10
6
1,000 bytes
pay close attention to which megabyte MB 10 1,000,000 bytes
letters are capitalised or not: 9
gigabyte GB 10 1,000,000,000 bytes

12
terabyte TB 10 1,000,000,000,000 bytes

Name Notation Power of 2 Value

10 1
kibibyte KiB 2 1024 = 1,024 bytes
20 2
mebibyte MiB 2 1024 = 1,048,576 bytes

30 3
gibibyte GiB 2 1024 = 1,073,741,824 bytes
40 4
tebibyte TiB 2 1024 = 109,951,162,776 bytes

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Memory Unit & Data storage: How many numbers?
28

To start thinking about how many different values can

be represented by a given number of bits, consider Number of Number of
bits different binary
the following examples: (n) sequences
• One bit can represent 21 = 2 distinct binary n
(2 )
sequences: 0 & 1 1 2
• Two bits can represent 22 = 4 distinct binary 2 4
sequences: 00, 01, 10 & 11 3 8
• Three bits can represent 23 = 8 distinct binary 4 16
sequences: 000, 001, 010, 011, 100, 101, 110, 111 5 32
6 64

With every additional bit, the number of different 7 128

arrangements of 0s & 1s doubles. Therefore, n bits 8 256
can represent 2n different binary sequences.

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Try it for yourself?

How many different values can be represented

with 16 bits?

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Memory Unit
The most fundamental unit of the computer memory is the bit. The Address Contents
bit can only take one of two values: 1’s & 0’s
11010000 10010001
Memory words: the word is a group of 1’s & 0’s & it may represent a
11010001 11110101
number character(s) (A, B, C, D), instruction of a program or other
binary coded info 11010010 11100011
Memory unit consists of a number of partitions. 11010011 10101010
Each partition consists of data (contents) & an address. . .
Data is represented on modern storage media using the binary . .
numeral system.
The address uniquely identifies every location in memory & the
contents are in binary form.
. .
An example of data & addresses stored in a memory unit is shown. 11011110 11011011
Most computer memories use words that are multiple of 8 bits 11011111 11001100
(byte). So usually we find the words 8bits, 16bits, 32bits or 64bits etc
32bits (bytes) word memory is very common
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READ operation
31

To read the contents from any location, the registers MAR (Memory
Address Register) & MDR (Memory Data Register) are used. To read the
contents from the address 11010000, the address is copied to MAR.

Register Contents

MAR 1 1 0 1 0 0 0 0

A read signal is sent by the processor to the memory. The contents are
then copied to the MDR (Memory Data Register).

Register Contents

MDR 1 0 0 1 0 0 0 1

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WRITE operation
To write data into a particular address, the data is first written to the MDR.
Let us consider writing the data 10111011 to the address 11101110.

Register Contents

MDR 1 0 1 1 1 0 1 1

The address is written to the MAR register.

Register Contents

MAR 1 1 0 1 1 1 1 0

A write signal is sent by the processor to the memory unit through the
control bus & the location is written with the data in MDR.
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Processor (CPU)
The processor or Central Processing Unit (CPU) is the internal hardware
component of the computer that is responsible for executing the
instructions of programs.

The processor is made up of several important components, each of

which has a specific role e.g. the ALU (Arithmetic & Logic Unit) & Control
Unit (CU).

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Processor: ALU
The ALU is responsible for performing arithmetic calculations & logical
operations that include:
• Addition, subtraction, multiplication, division
• Logical bitwise operations, such as AND, OR, NOT, & XOR
• Comparisons btn values, such as greater than, less than, equal to
• Shifting binary patterns to the left or right

The Accumulator (ACC) is the register that stores the result of arithmetic
and logical operations performed by a processor.

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Processor: CU
The CU (or program control unit) organises the sequence in which
program instructions are executed, followed by decoding the
instructions.

Decoding: the opcode & operand of an instruction are analysed to

determine what needs to be done to execute the instruction, i.e.
specify the type of instruction & the address mode used, fetch any
required data, & co-ordinate the sequence of micro-operations.

The CU is responsible for directing the operations of all the other

components of the processor.
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Processor: CU 36

The CU does the following tasks:

• Uses control signals to enable data to be read (i.e. loaded) from &
written (i.e. stored) to the main memory

• Decodes every instruction that processor will execute to determine

what needs to be done (e.g. perform an arithmetic calculation, a logic
operation, a branching to another instruction, loading or storing data to
the main memory)

• Organises the sequence of micro-operations that need to be performed

in order to carry out an instruction

• Uses control signals to determine the operation the ALU will carry out
at each instance
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Clock 37

The system clock — generates regular clock

pulses by emitting a signal that continuously
oscillates btn a low (or '0’) & a high (or '1') state.
The clock signal is used to synchronise the
operations of the CPU components.
A 'rising edge' is a change from a low (or '0')
state to a high (or '1') state. The opposite is
called a 'falling edge'. The time taken btn two
sequential rising edges is called the clock
period & it corresponds to one clock cycle.
Every operation of the CPU typically requires a
number of clock cycles to complete; the
number of cycles is specific to each type of
CPU. E.g. fetching data from memory could
require many clock cycles even though it may
be described as one operation. teachcomputerscience.com
Clock 38

The clock rate, clock frequency, or clock speed is calculated as the number of clock
cycles that can be completed in one second. Measured in Hz, MHz & GHz. It is the inverse
of the clock period, i.e. clock frequency=1/clock period.
Clock cycles per operation
In the model of a computer, a data transfer is generally described as one operation. In
reality, it can take many clock cycles to achieve a data transfer from one component to
another.
• If processor needs to read a memory location, it sends a read request via CB, along with
the address of the memory location via AB. These operations happen at the same time (i.e.
in the same clock cycle).
• Depending on how long it takes to access the memory, processor then receives the
contents of that memory location via the DB, after a number of clock cycles.
• If processor needs to write to a memory location, it sends a write request via the CB,
along with the address of that memory location via the AB & the data that needs to be
stored via the DB.
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Registers
Registers are locations of computer memory within the
processor that provide extremely fast access.

General-purpose registers
Having to access the main memory can slow down the execution
of instructions.
Therefore, the processor uses registers to temporarily store &
access the results of operations.
The ALU is connected to a set of general-purpose registers that
are used to keep the results of the intermediate calculations that
are produced as part of a larger computation.
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Registers
Dedicated/special-purpose registers
Dedicated or special-purpose registers are processor-based
registers that are used for a specific purpose.

The registers used in the fetch-decode-execute cycle are

special-purpose registers bc each one of them has a specific
role to play in each phase of the fetch-decode-execute cycle.
Their roles are specified below:

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Registers 41

• Program counter (PC): Holds the address of the next instruction to be

executed by the processor.
• Current instruction register (CIR): Holds the current instruction that the
processor is executing.
• Status register (SR): Stores information about the result of the last
instruction that the ALU executed. Each bit within the status register acts as a
flag to indicate if an error or exception has occurred within the process, or
to enable or disable interrupts to be raised:
• An error or exception - result of a calculation requires further action. E.g, it signifies if
the result of a calculation is negative or zero, or if a calculation produced an overflow
or/& a carry.
• An interrupt - event outside of the program process that requires the attention of
the processor. E.g, indicating a hardware malfunction.

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Registers
42

• Memory address register (MAR): Temporarily holds the address of the

memory location (in main memory) that the processor needs to access,
either to read from (i.e. load data) or write (i.e. store data) to.

• Memory buffer register (MBR)/memory data register (MDR):

Temporarily stores the data (data values or instructions) that are read from
or written to the main memory.

• Accumulator (ACCU): Stores the result of any calculation processed by the

ALU. The processor accesses other general-purpose registers where
temporary values are stored while calculations are completed. Any result
resides in the accumulator.
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Detailed von
Neumann
architecture

MAR, MDR, ACC, PC,

SR and CIR shown
are registers.
Addresses are stored
in the memory unit.

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Input-Output Devices
▪ An input device like a keyboard or mouse converts the signals sent by
humans into a form that can be understood by the computer.
▪ Output devices such as printers, monitors, etc. convert the information
from the computer into a form that is understandable by humans.

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I/O controller
I/O controller is a device that interfaces an input or output device with the
processor.
Each device has its own controller which is connected to a control bus. I/O
controller is responsible for receiving the requests from the processor &
sending control signals to the device specified for that operation.
It consists of:
• An interface to connect it to the system or I/O bus
• a set of data, command & status registers
• an interface that connects it to the cable connecting the device & the
processor.

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The fetch-decode-execute (FDE) cycle 46

To carry out the instructions, the processor fetches the

data & instructions from the memory & stores it in
suitable register: it fetches, decodes, & executes the
instruction.
These stages form the FDE cycle — bc they are repeated
for every instruction of every program that is run inside
a computer.

The FDE cycle applies to both application & system

software. Behind every operation you can perform on a
computer (play a video game, fill in a spreadsheet, debug
a program, check your emails, etc.) there are thousands of
instructions that are carried out by repeating the three
stages of the fetch-decode-execute cycle.
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The fetch-decode-execute (FDE) cycle 47

Before the FDE cycle, a program’s instructions need

to be ‘ready’ to be carried out ie.:
a. Program instructions are translated into machine
code
b. Program instructions are loaded into the RAM
End of a cycle for each instruction: the processor
checks the SR to see if an error/exception/
interrupt needs to be handled. E.g. if an interrupt,
the control might be transferred to the
corresponding interrupt service routine.
This model is a simplified version of a computer
system, illustrates this:
• The CU directs data values from general-purpose
registers as inputs to the ALU, retrieving the output of
the ALU, & saving it into the ACCU
• The CPU communicates with RAM using MDR & MAR.
Registers/ACCU can exchange data with RAM directly,
depending on type of instruction that is being
executed & it is also managed by the CU
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The fetch-decode-execute cycle: Fetch stage 48
To fetch an instruction from the main
memory:
1. The PC keeps the address of the next
instruction to be executed. The contents
of the PC are copied to the MAR, which
is connected to the AB. The address of
the next instruction to be executed is
placed on the AB.

Figure: The contents of PC are copied to the MAR

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 The fetch-decode-execute cycle: Fetch stage 49
2. Once the address of the instruction is on the AB,
the CU instructs a memory read operation to allow
the contents of the memory location to be
transferred to CPU. The instruction that is stored
at that address is transferred using the DB from
the RAM to the CPU, & is saved in the MBR/MDR.

Simultaneously, the contents of the PC are

incremented by 1 so that they point to the address
of the next instruction that needs to be fetched.

Figure: The instruction to be executed is fetched

from the RAM to the MBR/MDR & PC is
incremented by 1

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The fetch-decode-execute cycle: Fetch stage 50
3. The contents of the MDR are copied to the
CIR. This ensures that the current
instruction is kept safe so that the MDR can
be used during the execute stage, in order
to store additional data that is needed.

Figure: The contents of MDR are copied to CIR

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The fetch-decode-execute cycle: Decode stage51
The CU decodes the instruction that is
kept in the CIR. This involves splitting
the instruction into operand & opcode
to determine what type of instruction
needs to be carried out, checking if
additional data are required from
memory, & figuring out where these
are kept in RAM.

Figure: The instruction is decoded by the CU

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The fetch-decode-execute cycle: Execute stage
52

1. The instruction is executed. The exact

sequence of operations depends on the type
of instruction that is being executed e.g, for
an arithmetic instruction any required data
are fetched from the RAM, then the
calculation is executed by ALU, & the result of
the instruction is stored in ACCU, a general-
purpose register, or back into RAM.

Non-sequential instruction to be executed,

e.g. if the current instruction is a branch at Figure: Depending on the type of instruction,
executing an instruction can involve the ACCU & the
this stage, the address of the next instruction general-purpose registers, the ACCU, or RAM
to be executed is determined & loaded to PC.

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Summary of fetch-decode-execute cycle 53

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Clock cycles per operation 54

It can take many clock cycles to achieve a data transfer from one component
to another.
• If CPU needs to read a memory location, it sends a read request via the CB,
along with the address of the memory location via the AB. These operations
happen at the same time (i.e. in the same clock cycle

• Depending on how long it takes to access the memory, the CPU then
receives the contents of that memory location via the DB, after a number of
clock cycles.

• If CPU needs to write to a memory location, it sends a write request via

the control bus, along with the address of that memory location via the AB &
the data that needs to be stored via the DB.

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 55
What is an interrupt?
An interrupt is a signal sent from a device or software to the
processor.
The processor will temporarily stop its current process & will
service the interrupt signal.
E.g.: When paper is jammed in a printer, the CPU prompts the
user to check the status.

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 56

Interrupts
§ Interrupts allow the computer to carry out
many tasks at the same time.
§ When the interrupt is serviced, the status of
the current job is saved. The contents of
registers PC & CIR are saved on to the system
stack.
§ Once the interrupt is serviced using the
interrupt service routine, the current job is
serviced according to its status when it was
saved before the interrupt service.

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 57

Vectored interrupt mechanism

Each interrupt is associated with a vector, which points to the
code associated with that interrupt.
When an interrupt occurs, the current values of the registers are
saved to a stack & the CPU identifies the type of interrupt.
Then, the CPU points to the vector & processes the interrupt
service routine. This technique is called vectored interrupt
mechanism.

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Interrupts
▪ Sometimes, when an interrupt is being serviced, another interrupt may
occur.
▪ The CPU may save the status of the current interrupt processing &
proceed to service the new interrupt.
▪ Another methodology that can be used is to use priorities. Based on the
priority of the interrupts, it can be decided whether the current interrupt
service should be paused or not.
▪ E.g., an interrupt that notifies the user that the battery of a laptop is
running low must be given the highest priority.

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Let’s review some concepts

Buses Register CIR (Current Instruction

register)
The connection between the Registers are high-speed data
processor, memory and input- storage areas in the computer. The CIR contains the current
output devices. instruction carried out by the
processor.

PC (Program Counter) Accumulator Processor

The PC contains the location of Accumulator (ACC) is the register The processor contains ALU
the instruction that is to be that stores the result of (Arithmetic and Logic unit) and
executed next. arithmetic and logical operations Control Unit (CU).
performed by the processor.

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 2.
Activities

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Activity-1 (Internet research)

Duration: 15 minutes

1. 8085 is an Intel microprocessor. Use the internet and analyse the

architecture of 8085 microprocessor to answer the following questions.
A. What registers are used to carry memory locations while processing
instructions? Also, state its function.
B. What is the function of a flag register? What does each bit in this register
denote? State the function of each flag bit.

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Activity-2
Duration: 10 minutes

1. A set of instructions in assembly

language is given below with its Address Opcode Instruction
memory location. MOV AX, 22h
2000 A1 22
A. What is the function of this code?
SUB AX, 15h
2002 33 15
B. Consider any instruction and in the
space below describe its fetch- 2004 F4 HLT
decode and execute cycle. Use
appropriate registers in your
explanation.

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Activity-3
Duration: 15 minutes

Address Contents
1. Data stored in a part of the memory 98 78
unit is given in the table. 99 65
A. In the box, explain how the content at 9A 81
the memory location 9D can be read? 9B 2F
9C 3E
B. In the box, explain how the data 76
9D 19
can be written to memory location 9E D4
99?

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