Q4.

Which of the following options would you not expect (or at least it would be uncommon)
to see in the specification of an ISA:
A. The word size
B. The set of accessible general-purpose registers
C. The way a given instruction is expressed as machine code
D. The execution latency of a given instruction
E. The set of accessible special-purpose registers
[1 mark]

Q5. Which of the following statements best describes the semantics of a relative branch
instruction?
A. The program counter is reset to zero, so is independent from the current
program counter value
B. The branch target is at an offset from, and so is dependent on the current
program counter value
C. The branch target is relatively far from the current program counter value
D. The branch target is greater than the current program counter value
E. The program counter is only updated if a condition is true
[1 mark]

Q6. Consider the equivalence

(y ∧ ¬x) ∨ (x ∧ ¬y ) ≡ (x ∨ y ) ∧ ¬(x ∧ y ),

the left-hand side of which can be manipulated into the right-hand side by applying the
following sequence of Boolean axioms:

identity inverse distribution commutativity distribution commutativity X

The final axiom is missing, i.e., replaced with X: which of the following options for X
yields a valid derivation?
A. Absorption
B. Idempotency
C. Implication
D. Null
E. de Morgan

Page 3 of 17 Turn Over/. . .

 [2 marks]

Question Q7 and Question Q8 both relate to Figure 1, which describes the implementation
of two components denoted C0 and C1 . Each component Ci produces one output ri given
two inputs x and y , and has been implemented using MOSFET transistors.

Q7. The truth table below includes 5 possibilities for outputs r0 and r1 (stemming from
instances of C0 and C1 ), given x and y . Recall that Vss and Vdd are used to represent 0
and 1 respectively: which option is correct?

A. B. C. D. E.
z }| { z }| { z }| { z }| { z }| {
x y r0 r1 r0 r1 r0 r1 r0 r1 r0 r1
0 0 1 0 0 0 1 0 Z 0 1 Z
0 1 1 1 0 0 0 0 Z Z Z Z
1 0 1 1 0 0 0 0 Z Z Z Z
1 1 0 1 1 0 0 0 1 Z Z 0

[2 marks]

Q8. The vendor of these components claims they can be used to implement any Boolean
function; their reasoning is based on the fact that a NAND gate can be implemented
using instances of C0 and C1 . Assuming you want to minimise the number of C0 and C1
instances, how many of each are required to implement such a NAND gate?

A. B. C. D. E.
z }| { z }| { z }| { z }| { z }| {
C0 C1 C0 C1 C0 C1 C0 C1 C0 C1
1 1 5 3 3 5 3 3 5 5

[2 marks]

Q9. Consider the specification of an ISA, which includes a) a fixed-length, 32-bit instruction
encoding, and b) a byte addressable memory, with a 32-bit address space; instructions
are required to be aligned in memory. Imagine the ISA is implemented by some micro-
architecture, in which the program counter is a register comprised of n D-type latches:
what is the minimum n possible?
A. 0
B. 14
C. 16
D. 30
E. 32

Page 4 of 17
 [2 marks]

Question Q10 to Question Q13 all relate to Figure 2 and Figure 3, which describe an FSM
implementation and an associated waveform. When read left-to-right, the waveform captures
how values of Φ1 and Φ2 (a 2-phase clock), and r st (a reset signal) change over time; the
other input s maintains the value A6(16) throughout. Note that the waveform is annotated
with some instances and periods in time (e.g., ρ, and each ti ).

Q10. What is the value of r at time t0 ?

A. 0
B. 1
C. undefined
[1 mark]

Q11. What is the value of r at time t1 ?

A. 0
B. 1
C. undefined
[1 mark]

Q12. What is the value of r at time t2 ?

A. 0
B. 1
C. undefined
[1 mark]

Q13. Consider the following NAND-based implementations

D-type latch 7→ Figure 4

2-input XOR gate 7 → Figure 5
2-input, 1-bit multiplexer 7 → Figure 6

relating to components used within Figure 2. The waveform is annotated with ρ, which
illustrates the clock period. If a 2-input NAND gate imposes a gate delay of Tnand =
10ns, which value most closely reflects the maximum possible clock frequency?
A. 1.0MHz
B. 1.2GHz
C. 3.8MHz
D. 5.9MHz

Page 5 of 17 Turn Over/Qu. continues . . .

(cont.)

E. 6.6MHz
[3 marks]

Q14. Consider a counter machine with r = 4 registers which supports the instruction set
shown in Figure 7. After implementing the counter machine, the program, held in memory
as machine code, is fixed to

MEM = h 0A3(16) , 060(16) , 080(16) , 097(16) ,

050(16) , 020(16) , 083(16) , 0C0(16) i

Using the initial configuration

C0 = (l = 0, v0 = 0, v1 = 2, v2 = 1, v3 = 0)

and a subsequent trace of execution, decide which of the following options best describes
the purpose of this program.
A. Compare the values in R1 and R2 , setting R3 to reflect the result
B. Add the values in R1 and R2 , setting R3 to reflect the result
C. Swap the values in R1 and R2
D. Copy the value in R1 into R2 , retaining the value in R1
E. Copy the value in R1 into R2 , clearing the value in R1
[3 marks]

Page 6 of 17
(cont.)

What is the average number of clock cycles per instruction (CPI) for this program?
A. 22.59
B. 0.17
C. 4.25
D. 3.84
E. 384.00
[2 marks]

Q18. In a given computer system, accesses to main memory by the processor are supported
by a 16-way set-associative cache. Memory addresses are 16 bits, and each addressable
element has a word size of 1 byte. The cache has a capacity of 32 KiB (32,768 bytes),
cache blocks are of size 64 bytes, and cache sets are numbered starting at 0 (which
contains the lowest memory addresses).
Consider the memory address 0110100100110101, where here the highest (or most-
significant) bits are on the left-hand side. Which set is this address stored in, and what
tag is stored in the tag store?
A. Set 12, tag 01101001001
B. Set 53, tag 01101
C. Set 4, tag 01101
D. Set 9, tag 011010
E. Set 309, tag 01101
[3 marks]

Question Q19 and Question Q20 both refer to the the two’s complement addition of the
8-bit numbers 00101111 (47 in decimal) and 01010001 (81 in decimal).

Q19. Compute the two’s complement addition of the two 8-bit numbers.
A. 10000000 (128 in decimal)
B. 10000000 (-128 in decimal)
C. 01111110 (126 in decimal)
D. 01111100 (124 in decimal)
[2 marks]

Q20. Did the result overflow?

A. Yes
B. No

Page 8 of 17
 [1 mark]

Q21. Why is it important to support different execution privileges at an architectural level?

A. To ensure user programs cannot access restricted portions of memory
B. To ensure kernel cannot access application memory
C. To allow relocation of programs in memory
D. To allow the kernel to schedule multiple programs on a single processor
[1 mark]

Q22. The Hex 8 ISA has a word length of 8 bits. Each instruction is formed of a 4-bit
opcode and a 4-bit operand, which limits the number of instructions to 16.
Some of the instructions in the Hex 8 ISA do not require operands. Which of the following
schemes would allow the ISA to be expanded to contain 31 instructions, while retaining
4-bit opcodes which can be decoded in a single cycle?
A. Include an instruction to specify the operand is to be interpreted as an opcode
of an instruction which doesn’t require an operand. E.g. EXE ADD
B. Send an interrupt to indicate the instruction opcode is larger than 16. E.g. A
4-bit opcode refers to two instructions depending on an interrupt signal
C. Use a mechanism similar to the PFIX instruction to construct the opcode from
two instructions
D. Write a micro-program to implement the additional instructions
[3 marks]

Q23. When in the instruction execution cycle can interrupts occur?

A. Fetch
B. Decode
C. Execute
D. Writeback
E. At any time
[1 mark]

Q24. When might a processor handle interrupts?

A. Immediately
B. When the program has finished
C. After the current instruction has finished executing
D. At the end of the current subroutine
[1 mark]

Page 9 of 17 Turn Over/. . .

Q25. What type of data dependency hazard occurs in following instruction stream?

r1 ← r2 + r3
r4 ← r3 + r4
r5 ← r3 + r1
A. Read after Write (RAW)
B. Read after Read (RAR)
C. Write after Write (WAW)
D. Write after Read (WAR)
[2 marks]

Q26. Figure 8 and Figure 9 show two different circuits for 3-bit multiplication, labelled A
and B; both are constructed using half adders (HA) and full adders (FA). Which circuit
was generated using the Wallace Tree procedure, and why?
A. Multiplication circuit A (i.e., Figure 8) is a Wallace Tree because it follows the
Wallace Tree procedure
B. Multiplication circuit A (i.e., Figure 8) is a Wallace Tree because it has two
layers
C. Multiplication circuit B (i.e., Figure 9) is a Wallace Tree because it follows the
Wallace Tree procedure
D. Multiplication circuit B (i.e., Figure 9) is a Wallace Tree because it has two
layers
E. Multiplication circuit B (i.e., Figure 9) is a Wallace Tree because it passes
through the lowest partial sum unmodified
[2 marks]

Q27. During the assembly of an assembly program, labels are resolved. Consider the following
Hex 8 assembly program:

Line 1 - label:
Line 2 - ldac 0
Line 3 - ldbc -5
Line 4 - loop: br loop
Line 5 - br next
Line 6 - next: ldbc loop

During label resolution, what constant offsets are the operands on Line 4 (loop) and
Line 6 (loop) replaced with?

Page 10 of 17 Qu. continues . . .

 (cont.)

A. Line 4 becomes br -1 and line 6 becomes ldbc -1

B. Line 4 becomes br 4 and line 6 becomes ldbc 4
C. Line 4 becomes br 0 and line 6 becomes ldbc 4
D. Line 4 becomes br 0 and line 6 becomes ldbc 0
E. Line 4 becomes br -1 and line 6 becomes ldbc 4
[2 marks]

Page 11 of 17 Turn Over/. . .

Additional figures and tables

Vdd Vdd

y r1
x
y
r0
x

Vss Vss
(a) C0 (using P-type MOSFETs). (b) C1 (using N-type MOSFETs).

Figure 1: MOSFET-based implementations of C0 and C1 .

Page 12 of 17
 r
D Q

¬Q

D Q

¬Q
en

en
s7
y c
r
x

D Q

¬Q

D Q

¬Q
en

en
s6
y c
r
x

D Q

¬Q

D Q

¬Q
en

en
s5
y c
r
x
D Q

¬Q

D Q

¬Q
en

en
s4

y c
r
x
D Q

¬Q

D Q

¬Q
en

en
s3

y c
r
x
D Q

¬Q

D Q

¬Q
en

en
s2

y c
r
x
D Q

¬Q

D Q

¬Q
en

en
s1

y c
r
x
D Q

¬Q

D Q

¬Q
en

en
s0

y c
r
x
Φ2

Φ1
r st

Figure 2: An FSM implementation, which has 4 inputs (1-bit Φ1 , Φ2 and r st on the left-hand
side; 8-bit s spread within the design) and 1 output (1-bit r on the right-hand side).

Page 13 of 17 Turn Over/. . .

Φ2

Φ1

r st

t0 t1 ρ t2

Figure 3: A waveform describing behaviour of Φ1 , Φ2 , and r st within Figure ??.

Page 14 of 17
 D S0
Q

en

¬Q
R0
Figure 4: A NAND-based implementation of a D-type latch.

Figure 5: A NAND-based implementation of a 2-input XOR gate.

r
y

c
Figure 6: A NAND-based implementation of a 2-input, 1-bit multipliexer.

Page 15 of 17 Turn Over/. . .

 8 7 6 5 4 3 2 1 0

Li : Raddr ← Raddr + 1 then goto Li+1 7→ 000 addr 0000

8 7 6 5 4 3 2 1 0

Li : Raddr ← Raddr − 1 then goto Li+1 7→ 001 addr 0000

8 7 6 5 4 3 2 1 0

Li : if Raddr = 0 then goto Ltarget else goto Li+1 7→ 010 addr target
8 7 6 5 4 3 2 1 0

Li : halt 7→ 011 00 0000

Figure 7: The instruction set for an example 4-register counter machine.

Page 16 of 17
 x2 y1 x0 y2 x1 y0
x2 y0
x2 y2 x1 y2 x1 y1 x0 y1 x0 y0

HA FA HA

0 0

FA FA FA FA HA

Figure 8: 3-bit multiplication circuit A.

x2 y0 x1 y0

x1 y1 x0 y1 x0 y0

x2 y1

x2 y2 FA HA

x0 y2
HA

x1 y2 HA

FA FA

Figure 9: 3-bit multiplication circuit B.

Page 17 of 17
END OF PAPER