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Syllabus CSE 402

This document outlines a course on computer organization and architecture. The course aims to teach students about the organizational and architectural aspects of computers, including processor and memory design, data transfer techniques, and instruction-level parallelism. The course is divided into five modules covering topics such as computer components, CPU operations, processor organization, memory hierarchy, and I/O systems. Students will learn assessment includes class tests, assignments, and an end of semester exam. References include textbooks on computer architecture, organization, and parallel processing.

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241 views1 page

Syllabus CSE 402

This document outlines a course on computer organization and architecture. The course aims to teach students about the organizational and architectural aspects of computers, including processor and memory design, data transfer techniques, and instruction-level parallelism. The course is divided into five modules covering topics such as computer components, CPU operations, processor organization, memory hierarchy, and I/O systems. Students will learn assessment includes class tests, assignments, and an end of semester exam. References include textbooks on computer architecture, organization, and parallel processing.

Uploaded by

vivekparashar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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COMPUTER ORGANIZATION & ARCHITECTURE

Course Code: CSE 402 Credit Units: 03


Total Hours: 30
Course Objective:
To conceptualize the basics of organizational and architectural issues of a digital computer. To analyse performance issues in
processor and memory design of a digital computer. To understand various data transfer techniques in digital computer. To analyse
processor performance improvement using instruction level parallelism.
Course Contents:
Module I: Overview of Computer Architecture & Organization: (06 Hours)
Introduction of Computer Organization and Architecture. Basic organization of computer and block level description of the
functional units. Performance measure of Computer Architecture. Introduction to buses and connecting I/O devices to CPU and
Memory, bus structure.
Module II: CPU and Register Transfer Operations: (06 Hours)
Instruction Codes, Computer Registers, Computer Instructions, Register Transfer Language, Timing and Control, Instruction Cycle,
Memory, Input-Output and Interrupt Reference Instructions, Signed multiplication, Booth’s algorithm. Division of integers:
Restoring and non-restoring division Floating point arithmetic: Addition, subtraction.
Module III: Processor Organization and Architecture: (08 Hours)
Introduction to CPU Architecture, General Register Organization, Stack Organization, Instruction representation, Instruction
Formats, Instruction type, Control Unit: Soft wired (Micro-programmed) and hardwired control unit design methods.
Microinstruction sequencing and execution. Micro operations. Addressing Modes, Data Transfer and Manipulation, Program
Control, Reduced Instruction Set Computer RISC and CISC. Design of Accumulator Logic. Hardwired and Microprogrammed
control: Control Memory, Address Sequencing, Design of Control Unit.
Module IV: Memory Organization: (05 Hours)
Memory hierarchy and characteristics. Cache memory: Concept, architecture (L1, L2, L3), mapping techniques. Cache Coherency,
Interleaved and Associative Memory. Virtual Memory, Concept, Segmentation and Paging, Page replacement policies.
Module V: I/O Organization and Peripherals: (05 Hours)
Input/output systems, I/O modules and IO processor. Pipeline processing, Parallel Processing, Pipelining, Arithmetic Pipeline,
Instruction Pipeline, RISC Pipeline Types of data transfer techniques: Programmed I/O, Interrupt driven I/O and DMA. Introduction
to parallel processing systems.
Course Outcomes:
• Ability to understand basic structure of computer.
• Ability to perform computer arithmetic operations.
• Ability to understand control unit operations.
• Ability to design memory organization that uses banks for different word size operations.
• Ability to understand the concept of cache mapping techniques.
• Ability to understand the concept of I/O organization.
• Ability to conceptualize instruction level parallelism
Examination Scheme:
Components A CT S/V/Q/HA ESE
Weightage (%) 5 15 10 70
A: Attendance, CT: Class Test,:, S/V/Q/HA: Seminar/Viva/Quiz/ Home Assignment, ESE: End Semester Examination;
Text & References:
Text:
• Carl Hamacher, Zvonko Vranesic and Safwat Zaky, “Computer Organization”, Fifth Edition, Tata McGraw-Hill.
• John P. Hayes, “Computer Architecture and Organization”, Third Edition.
• William Stallings, “Computer Organization and Architecture: Designing for Performance”, Eighth Edition, Pearson.
• B. Govindarajulu, “Computer Architecture and Organization: Design Principles and Applications”, Second Edition, Tata
McGraw-Hill.
Reference:
• WIliam Stallings, Computer Organization and Architecture, 4th Edition-2000, Prentice-Hall of India Private Limited.
• M.J Flynn, “Computer Architecture, Pipelined and Parallel Processor Design”, Narosa Publishing, 1998.
• Hwang and Briggs, “Computer Architecture and Parallel Processing”; MGH, 2000.
• Kai Hwang & Faye a Briggs, McGrew Hill, inc., Computer Architecture & Parallel Processing.
• John D. Carpinelli, Computer system Organization & Architecture, Edition 2001, Addison Wesley, Delhi
• John P Hayes, McGraw-Hill Inc, Computer Architecture and Organization.
• M. Morris Mano and Charles, Logic and Computer Design Fundamentals, 2nd Edition Updated, Pearson Education,
ASIA.
• Hamacher, “Computer Organization,” McGraw hill.
• Tennenbaum,” Structured Computer Organization,” PHI
• B. Ram, “Computer Fundamentals architecture and organization,” New age international Gear C. w., “Computer
Organization and Programming, McGraw hill.

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