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Ass4 Ext Sol23

The document describes an assignment involving the analysis and design of an electronic lock circuit. It involves: 1) Drawing a state diagram for a circuit that opens with codes 0110 or 1001 while indicating detection for a full clock cycle. 2) Answering questions about analyzing the problem definition, approach, and assumptions. 3) Expressing logic functions in sum of products and product of sums form with minimal letters. 4) Finding the simplest implementation for a given logic function map. 5) Designing a multiple output logic circuit and indicating the number of gate inputs.

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20 views4 pages

Ass4 Ext Sol23

The document describes an assignment involving the analysis and design of an electronic lock circuit. It involves: 1) Drawing a state diagram for a circuit that opens with codes 0110 or 1001 while indicating detection for a full clock cycle. 2) Answering questions about analyzing the problem definition, approach, and assumptions. 3) Expressing logic functions in sum of products and product of sums form with minimal letters. 4) Finding the simplest implementation for a given logic function map. 5) Designing a multiple output logic circuit and indicating the number of gate inputs.

Uploaded by

korede
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ELEC 2607 Assignment 5 80 Marks

I. Draw a graph to represent the operation of an electronic lock that opens by either of the codes 0110 and 1001.
Once a code sequence is detected, it could be a portion of the next code. The detection must be indicated for
a whole clock cycle. Answer Parts A-C before attempting the problem, and Part D afterwards? 25 Marks

A. Problem analysis: : Problem definition


1. How many inputs and outputs the circuit has? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. What type of sequential circuit is required? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. What specific type of output(s) are required? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4. Is the priority with the speed or reliability of the resulting circuit? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B. Problem analysis: Approach to the problem
1. Name the technique you would use to solve the problem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. Could this technique result in having redundant states? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. How many out-going arrows would each state of the solution have? . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4. How would you determine the output(s) at each state of the design solution? . . . . . . . . . . . . . . . . . . . . .
C. Problem analysis: Use of assumptions
1. Which state does the circuit start at? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. How many states would raise the indicator flag? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. Shall the circuit receive input(s) in series or parallel? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4. Shall the circuit detect overlapping code sequencer? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D. Problem analysis: Interpreting the solution - validity of results
1. Considering the requirements, would the solution result in
the fastest and least power-consuming circuit? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. After detecting one of the codes, what should be the minimum
number of clock cycles to detect same code again? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. Considering the two codes, what should be the minimum
number of clock cycles to detect the other code? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4. Is it possible for the solution to have fewer states compared
to each of the individual state graphs? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1
Solve the problem here ...

2
¯ d¯ + ā + c + b̄) in sum-of-products form.
II. Express z = (ā + b̄ + c)(a + c̄ + d)(b + a + d)(
10 Marks

III. Find the simplest (i.e. minimum number of gate inputs) implementation for the function g(A,B,C,D) defined
by the map below. 15 Marks

IV. Change to a sum of products form with minimal letters.


Z = (A + BC)(ĀBC + DB̄)(Ā + EF ) 10 Marks

3
V. Change to a product of sums form with minimal letters.
Y = ĀBD + ABC + AC D̄ + E 15 Marks

VI. Find the ΣΠ expression with minimal gate-input count for the multiple-outputs E,F,G. Indicate the number
of gate inputs. 15 Marks

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