Unit-III Interfacing of Memory and I/O Devices

Following major topics will be covered in this unit

• Memory & I/O Interfacing

• Data Transfer Schemes, Interrupt of Intel 8085
• Interfacing Devices
• PPI (Intel8255), PIC (Intel8259), PCI (Intel8251), Intel8253

What is Interfaced?

• A microprocessor combined with memory and input/output devices, forms a microcomputer

• The microprocessor is the heart of a microprocessor
• Memories and input/output devices are interfaced to microprocessor to form a microcomputer
• The selected memories and input/output devices should be compatible with microprocessor

Address Space Partitioning:

• The Intel8085 uses a 16-bit wide address bus for addressing memories and I/O devices
• Using 16-bit wide address bus it can access 216 = 64 K bytes of memory and I/O devices
• The 64K addresses are to be assigned to memories and I/O devices for their addressing
• There are two schemes for the allocation of addresses to memories and input/output devices:
1. Memory mapped I/O scheme
2. I/O mapped memory I/O scheme

Memory mapped I/O scheme:

• In this scheme, there is only one address space

• Address space is defined as the set of all possible addresses that a microprocessor can
generate
• Some addresses are assigned to memories and some addresses to I/O devices
• An I/O device is also treated as memory location and one address is assigned to it
• The addresses of I/O device are different from the addresses which have been assigned to
memories
• The addresses which have not been assigned to memories can be assigned to I/O devices
• One address is assigned to each I/O device
• all the data transfer instructions of the microprocessor can be used for both memory as well as
I/O devices
• For Example: MOV A, M will be valid for data transfer from the memory location or I/O
device, whose address in H-L pair
• If the H-L pair contain the address of a memory location, data will be transferred from the
memory location to accumulator
• If the H-L pair contain the address of an I/O device, data will be transferred from the I/O
device to accumulator
• The memory mapped I/O scheme is suitable for a small system

I/O mapped I/O scheme:

• In this scheme, the address assigned to memory locations can also be assigned to a I/O
devices
• The same address may be assigned to a memory location or to an I/O device
• The microprocessor must issue a signal to distinguish whether the address on the address bus
 • for a memory location or I/O device
• The Intel8085 issues IO/͞M signal for this purpose
• Two extra instructions IN and OUT are used to address I/O devices
• The IN instruction is used to read data from an input device
• The OUT instruction is used to send data to an output device
• This scheme is suitable for a large system

Memory & I/O Interfacing:

• Several memory chips and I/O devices are connected to a microprocessor

Memory Chip and I/O Device selection

• An address decoding circuit is employed to select the required I/O device or a memory chip
• If IO/͞M is high, the decoder-2 is activated and the required I/O device is selected
• If IO/͞M is low, the decoder-1 is activated and the required memory chip is selected
• A few MSBs of the address lines are applied to the decoder to select a memory chip or an I/O
device
Interfacing of Memory and I/O Devices
Memory Interfacing

• The address of a memory location or an I/O device is sent out by the microprocessor
• The corresponding memory chip or I/O device is selected by a decoding circuit
• The decoding task can be performed by a decoder, a comparator, a bipolar PROM or PLA
• PLA (Programmed Logic Array), PROM (Programmable Read Only Memory)

Application of 74LS138, a 3 to 8 lines decoder

• G1, G2A and G2B are enable signals

• To enable 74LS138, G1 should be high and G2A and G2B should be low
• A, B and C are select lines
• Y0, Y1, ……..Y7 are output lines
• An output lines goes low when it is selected, Other output lines remain high

Interfacing of Memory Chips using 74LS138

Truth Table for 74LS138

Interfacing of Memory chips

• When G1 is low or G2A is high or G2B is high, all output lines become high
• Thus, 74LS138 acts as decoder only when G1 is high, and G2A and G2B are low
 • The memory locations for EPROM1lie in the range 0000 to 1FFF
• These are the memory locations for ZONE0 for the memory chip
• Which is connected to the output line Y0 of the decoder
• Similarly, for ZONE1 is 2000 to 3FFFand for ZONE7 is E000 to FFFF

Interfacing of Memory chips

• The entire memory address has been divided into 8 zones

• Address lines A15, A14 and A13 have been applied to select lines A, B and C of the 74LS138
• The logic applied to these lines selects a particular memory device, an EPROM or RAM
• Other address lines A0, A1, …….., A12 go directly to memory chip
• IO/͞M is connected to G2B, when IO/͞M goes low for memory read/write operation G2B goes
low
• G1 is connected to +5Vd.c supply and G2A is grounded

Memory locations for various Zones

I/O Interfacing

• The interfacing of I/O devices through decoder 74LS138

• An address of the I/O device is o 8-bits, only A8–A15 lines of address bus are used for I/O
addressing
• The address lines A8, A9 and A10 have been applied to select lines A, B and C of the
74LS138
• The address line A11–A15 are applied to G2B through a NAND gate
• G2B becomes low only when all address lines A11–A15 are high, G2A is grounded
• IO/͞M is connected to G1, when IO/͞M goes high for I/O read/write operation, G1 goes high

Interfacing of I/O Devices using 74LS138

Address of I/O Devices connected to 74LS138

Data Transfer Schemes

• To solve the problem of speed mismatch between microprocessor and I/O device
• A number of data transfer techniques have been developed
• The data transfer schemes are classified into the following two categories:
1. Programmed data transfer scheme
2. DMA (Direct Memory Access) data transfer scheme

Programmed data transfer scheme

• Programmed data transfer scheme s are controlled by the CPU

• Data are transferred from an I/O device to CPU (or to the memory through CPU) or vice versa
• Programmed data transfer scheme are employed when small amount of data are to be
transferred
• The programmed data transfer schemes are classified into the following three categories:
1. 1.Synchronous data transfer scheme
2. Asynchronous data transfer scheme
3. Interrupt driven data transfer scheme

DMA data transfer scheme

• In DMA data transfer scheme CPU does not participate

• Data are directly transferred from an I/O device to the memory or vice versa
• The data transfer is controlled by the I/O device or a DMA controller
• The scheme is employed when large amount of data are to be transferred
• An I/O device which wants to send data using DMA technique, sends the HOLD signal to the
CPU
• On receiving a HOLD signal the CPU gives up the control of buses on completion of machine
cycle

DMA data transfer scheme

• The CPU sends a hold acknowledge signal to the I/O device to indicate
• It has received the HOLD request and it has released the buses
• DMA transfer scheme is a faster scheme as compared to programmed data transfer scheme
• It is used to transfer data from mass storage devices such as hard disk, optical disk etc.
• DMA data transfer are of the following two types:
1. 1.Burst mode of DMA transfer
 2. Cycle stealing technique of DMA data transfer

Burst mode of DMA transfer

• In which the I/O device withdraws the DMA request only after all the data bytes have been
transferred
• Called burst mode of data transfer
• By this technique a block of data is transferred
• This technique is employed by magnetic disk drives
• In case of magnetic disks data transfer can not be stopped or slowed down without loss of
data
• Hence, block transfer is must

Cycle stealing technique of DMA data transfer

• In this technique a long block of data is transferred by a sequence of DMA cycles

• In this method after transferring one byte or several bytes the I/O device withdraws DMA
request
• This method reduces interference in CPU’s activities
• The interference can be eliminated completely by designing an interference circuitry
• Which can steal bus cycle for DMA data transfer only when the CPU is not using the system
bus
• Examples of DMA controller chips are: Intel 8237A, 8257 etc.

Synchronous data transfer scheme

• Synchronous means “at the same time”

• The device which sends and device which receives data are synchronized with the same clock
• When the CPU and I/O devices match in speed, this technique of the data transfer is
employed
• The data transfer with I/O devices is performed executing IN or OUT instructions for I/O
mapped I/O
• The IN instruction is used to read data from an input device or input port
• The OUT instruction is used to send data from the CPU to an output device or output port
• This technique is rarely used

Asynchronous data transfer scheme

• Asynchronous means “at irregular intervals”

• In this method data transfer is not based on predetermined timing pattern
• This technique is used when the speed of an I/O device does not match the speed of
microprocessor,
• And, the timing characteristic of I/O device is not predictable
• In this technique the status of the I/O device i.e. whether the device is ready or not,
• Checked by the microprocessor before the data is transferred
• When I/O device becomes ready, the microprocessor sends instructions to transfer data
• This mode of data transfer is also called handshaking mode of data transfer
• because some signals are exchanged between the I/O device and microprocessor
• before the actual data transfer takes place
• Asynchronous data transfer is used for slow I/O devices
• This technique is inefficient because the precious time of the microprocessor is wasted in
waiting
Interrupt driven data transfer scheme

• In this scheme the microprocessor initiates an I/O device to get ready, and then
• It executes it main program instead of remaining in a program loop to check the status of the
I/O device
• When the I/O device becomes ready to transfer data,
• It sends a high signal to the microprocessor through a special input line called an interrupt
line
• Interrupt driven data transfer is used for slow I/O devices
• It is an efficient technique as compared asynchronous data transfer scheme

Interrupt Driven Data Transfer Scheme

Interrupts of Intel 8085

Interrupts
• The Intel 8085 has five interrupts inputs namely TRAP, RST7.5, RST6.5, RST5.5 and INTR
• The TRAP has the highest priority, followed by RST7.5, RST6.5 and RST5.5
• The INTR has the lowest priority
• When interrupts are to be used, they are enabled by software using the instruction EI (Enable
Interrupt)
• The instruction EI sets the interrupt enable flip-flop to enable the interrupts
Interrupts Contd…

• The use of the instruction EI enables all the interrupts

• The instruction DI (Disable Interrupt) is used to disable interrupts
• The DI instruction resets the interrupt enable flip-flop and disables all the interrupts
• Except nonmaskable interrupt, TRAP
• The system RESET also resets the interrupt enable flip-flop
• When interrupt line goes high processor completes its current instruction
• Saves program counter on the stack

Interrupts Category

• The interrupt which can be masked-off (i.e., made ineffective) are called maskable interrupts.
• Masking is done by software
• The Intel 8085 has two categories of interrupts: maskable and nonmaskable
• The TRAP is a nonmaskable interrupt, it need not be enabled and disabled, not accessible to
user
• It is used for emergency situation such as power failure and energy shut-off
• RST7.5, RST6.5 and RST5.5 are maskable interrupts

Hardware and Software Interrupts

• Interrupts caused by I/O devices are called hardware interrupt

• The normal operation of a microprocessor can also be interrupted by abnormal internal
conditions
• Such an interrupt is called a software interrupt
• RSTn instructions of the microprocessor are used for software interrupt
• When RSTn instruction is inserted in a program, executed upto the point where RSTn has inserted
• When several I/O devices are connected to INTR, an external hardware is used to interface I/O
devices

Interrupt Call Locations

• When an interrupt occurs, the program is transferred to a specific memory location

• Then the monitor transfers the program form the specific memory location to a RAM memory
location
• From where the user can write the program for interrupt service sub-routine (ISS)
• For TRAP, RST7.5, 6.5, and 5.5 the program is automatically transferred
• To specific memory locations without any external hardware

Vectored Interrupt

• An interrupt for which hardware automatically transfers the program

• To a specific memory location is known as vectored interrupt

Interrupt Call-location in Hex

TRAP 0024
RST 7.5 003C
RST 6.5 0034
RST 5.5 002C
INTR CALL-locations

• There are 8 numbers of CALL-locations for INTR interrupt

RST n Hex-Code Call-locations

RST 0 C7 0000
RST 1 CF 0008
RST 2 D7 0010
RST 3 DF 0018
RST 4 E7 0020
RST 5 EF 0028
RST 6 F7 0030
RST 7 FF 0038

Summary of Intel 8085 Interrupts

RST 7.5, 6.5 and 5.5

• These are mask able interrupts

• These interrupts are enabled by software using instruction EI and SIM (Set Interrupt Mask)
• The execution of the instruction SIM enables/ disables interrupt
• According to the bit pattern of the accumulator
• Bits 0 – 2 set/reset the mask bits of interrupt mask register for RST 5.5, 6.5 and 7.5
• Bit 0 is for RST 5.5 mask, bit 1 for RST 6.5 mask and bit 2 for RST 7.5 mask
• If a bit is set to 1 the corresponding interrupt is masked off (disabled)
• If it is set to 0, the corresponding interrupt is enabled
• Bit 3 is set to make bits 0 – 2 effective
• Bit 4 is an additional control for RST 7.5, if it is set to1, the flip-flop for RST7.5 is reset
• Bit 6 and 7 are for serial data output
• The instruction SIM is also used for serial data transmission
• Bit 6 is to enable SOD
 • If SIM instruction is executed the content of the 7th bit of the accumulator is output on SOD
line
• The content of bit 7 may be either high (1) or low (0)

Accumulator Content for SIM

Ex1: Enables all the interrupt of Intel 8085

• The content of the accumulator for instruction SIM to enable RST 7.5, 6.5 and 5.5 are
programmed as follows:

7 6 5 4 3 2 1 0
SOD SOE X R7.5 MSE M7.5 M6.5 M5.5
0 0 0 0 1 0 0 0 = 08

• Bits 0,1 and 2 are set to 0 to enable R7.5,6.5 & 5.5

• Bit 3 is set to make Bits 0,1,2 effective
• Bit 4 is set to make 0 to enable RST 7.5

Program:

Mnemonics Comments
EI Enable Interrupts
MVI A, 08 Accumulator bit pattern to enable RST7.5, 6.5 and 5.5
SIM Enable RST 7.5, 6.5, and 5.5

Ex2: Enable RST 6.5 and disable RST 7.5 and 5.5

The content of the accumulator for instruction SIM to enable RST 6.5, and disable RST 6.5 and 5.5
are programmed as:

7 6 5 4 3 2 1 0
SOD SOE X R7.5 MSE M7.5 M6.5 M5.5
0 0 0 1 1 1 0 1 = 1D
 • Bits 0 and 2 are set to 1 to mask off (disable) RST7.5, and 5.5
• Bit 3 is set to make Bits 0,1,2 effective
• Bit 4 is set to make 1 to disable RST 7.5, (Bit 1, 0 = enabled)

Program:

Mnemonics Comments
EI Enable Interrupts
MVI A, 1D Accumulator bit pattern to enable RST6.5 and mask-off RST 7.5 and 5.5
SIM Enable RST 6.5 and disable RST 7.5, and 5.5

Pending Interrupts:

• When one interrupt request is being served, other interrupt may occur resulting in a pending
request
• When more than one interrupts occur simultaneously, the interrupt having higher priority is
served
• The interrupt with lower priority remain pending
• An interrupt may occur while other interrupt is being served resulting in a pending interrupt
• The 8085 has an instruction RIM using which we can know the current status of pending
interrupts
• This instruction gives the current status of only maskable interrupts

Bit patterns of RIM instruction

• Bit 0 – 2 are for interrupt mask, 1 = masked

• Bit 3 indicates interrupt enable flag, 1 = enabled
• Bit 4 – 6 indicate pending interrupts, 1 = pending
• Bit 7 serial input data (SID)
• After executing the ISS the processor checks whether any other interrupt is pending using
RIM instruction
• If an interrupt is pending the processor executes its interrupt service subroutine
• Before it returns to the main program

Accumulator Content after the Execution of RIM

Interfacing & I/O Devices

• To communicate with the outside world microcomputer use peripheral (I/O devices)
• Commonly used peripherals are: A/D converter, D/A converter, CRT, printers, hard disks,
floppy disks etc.
• Peripherals are connected to the microcomputer through electronic circuits, called interfacing
circuit
• The interfacing circuit converts the data available from an input device into compatible
format
• The interface associated with the output device converts the output of the microcomputers
• Into the desired peripheral format

General & Special Purpose Interfacing Devices

• General purpose devices are:

• I/O Port
• Programmable Peripheral Interface (PPI)
• DMA Controller
• Communication Interface
• Special purpose interfacing devices are designed to interface a particular type of I/O device,
examples as:
• CRT Controller
• Optical Disk Controller
• Key Board and Display Interface

Control Signals for Memory & I/O Devices

• Intel8085 issues control signals R͞ D, W͞ R for read and write operation of memory and I/O
devices
• It also issues a status signal IO/͞M
• Memory and I/O devices require control signals in the form of:
• MEMR – Memory read
• MEMW – Memory write
• IOR – I/O read
• IOW – I/O write
• These control signals are generated using R͞ D, W͞ R and IO/͞M using logic gates

Control Signals for Memory I/O Read Write Operation

Memory and I/O Read/Write Operations

• To get MEMR, use IO/M̅ ˅ R͞ D: Memory read operation takes place when both are low
• To get MEMW, use IO/͞M ˅ W͞ R: Memory write operation take place when both are low
• I/O read/write operation takes place when IO/͞M is high
• To get IOR and IOW signals, IO/͞M is inverted and then applied to OR gates
• Get IOR using inverted IO/͞M ˅ R͞ D
• Get IOW using inverted IO/͞M ˅ W͞ R

I/O Ports

• An input device is connected to the microprocessor through an input port

• An input port is a place for unloading data
• An input device sends data to the input port
• The microprocessor reads data from the input port
• Thus data are transferred from the input device to the accumulator via input port
• Similarly, an output device is connected to the microprocessor through an output port
• The microprocessor sends data to an output port

Interfacing of I/O Devices through I/O Port

I/O Ports Description

• An I/O port may be programmable or non-programmable

• A non-programmable port behaves as an input port if it has been designed so and connected
in input mode
• Similarly, a non-programmable port designed so and connected in output mode, acts as an
output port
• But a programmable I/O port can be programmed to act either as an input port or output port
• The electrical connections remain same
• The Intel 8212 is an 8-bit non-programmable I/O port
• It can be connected either as an input or output port

Interfacing of Intel 8212

• If we require one input port and one output port, two units of Intel 8212 will be required
• One of them will be connected in input mode and the other in the output mode
 INPUT MODE

OUTPUT MODE

Programmable Peripheral Interface (PPI)

• A programmable peripheral interface is a multiport device

• The ports may be programmed in a variety of ways as required by the programmer
• The device is very useful for interfacing peripheral device
• The term PIA, Peripheral Interface Adapter is also used by some manufacturer

Intel 8255

• The Intel 8255 is a programmable peripheral interface

• It has two versions, namely the Intel 8255A and the Intel 8255A-5
• General description for both are same, known as 8255
• Its main functions are to interface peripheral devices to the microcomputer
• It has three 8-bit ports: Port A, Port B and Port C
• The Port C has been further divided into two of 4-bit ports, Port Cupper and Port Clower
• Each port can be programmed as an input port or an output port

Architecture of Intel 8255

• It is a 40 pin I.C. package, it operates on a single 5 Vd.c.

• Its important characteristics are:
• Ambient temperature 0 to 70oC, Voltage of any pin: 0.5 V to 7 V, power dissipation 1 Watt
• VIL = Input low voltage, Min = 0.5 V, Max = 0.8 V
 • VIH = Input high voltage, Min = 2 V, Max = Vcc
• VOL = Output low voltage = 0.45 V
• VOH = Output high voltage = 2.4 V
• IDR = Darlington drive current = Minimum 1 mA, Maximum 4 mA of any 8 pins of the port

Schematic Diagram of Intel 8255

The Pins for various Ports

• The pins for various ports are as follows:

• PA0 – PA7: 8 pins of port A
• PB0 – PB7: 8 pins of port B
• PC0 – PC3: 8 pins of port Clower
• PC4 – PC7: 8 pins of port Cupper
• D0 – D7: Data bus
• RESET: Indicates that the device is reset
• VCC: supply (operating input) voltage
• GND: Grounded

Important Control Signals

• The important control signals are as follows:

• C͞ S (Chip Select): It is a chip select signal
• The Low status of the signal enables communication between the CPU and 8255
• R͞ D (Read): when R͞ D goes low, the 8255 sends out data or status to the CPU
• W͞ R (Write): when W͞ R goes low, the CPU writes data or control world into 8255
• A0 and A1: the selection of ports and control world register
• It is done using A0 and A1 in conjunction with R͞ D and W͞ R

Operating Modes of 8255

• The Intel 8255 has the following three modes of operations which are selected by software:
• Mode 0: Simple Input/Output
• Mode 1: Strobed Input/Output
• Mode 2: Bidirectional Port
• The 8255 has two 8-bit ports (Port A and Port B) and two 4-bit ports (Port Cupper and Port
Clower)
• In Mode 0: a port can be operated as a simple input or output port
 • Each of the four ports of 8255 can programmed to be either an input or output port
• Mode 1 is strobed input/output mode of operation
• The Port A and Port B both are designed to operate in this mode of operation
• When Port A and Port B are programmed in Mode 1, six pins of port C are used for their
control
• PC0, PC1 and PC2 are used for the control of the Port B which can be used either as input or
output port
• If the Port A is operated as an input port, PC3, PC4 and PC5 are used for its control
• When the Port A is operated as an output port, PC3, PC6 and PC7 are used for its control
• The combination of Mode 1 and Mode 0 operation is also possible
• Ex: when Port A is programmed to operate in Mode 1, the Port B can be operated in Mode 0
• Mode 2 is strobed bidirectional mode of operation
• In this mode, Port A can be programmed to operate as a bidirectional port
• The Mode 2 operation is only for Port A
• When Port A is programmed in Mode 2, the Port B can be used in either Mode 1 or Mode 0
• For Mode 2, PC3 to PC7 are used for the control of Port A

Control Word of Intel 8255

• According to the requirement a port can programmed to act either as an input or an output
port
• For programming the ports of 8255 a control word is formed
• Control word is written into the control word register (CWR) which is within 8255
• No read operation of the CWR is allowed
• The control word bit corresponding to a particular port is set to either 1 or 0
• If a particular port is an input port, the bit is set to 1
• If a particular port is an output port, the bit is set to 0

Control Word Bits for Intel 8255

Description of Control Word Bits

• Bit No. 0: It is for Port Clower, Input = 1, output = 0

• Bit No. 1: it is for Port B, Input = 1, output = 0
• Bit No. 2: it is for selection of the mode for Port B, for Mode0 = 0, for Mode1 = 1
• Bit No. 3: It is for Port Cupper, Input = 1, output = 0
• Bit No. 4: It is for Port A, Input = 1, output = 0
• Bit No. 5 and 6: these bits are to define the operating mode of the port A,
• Mode 0 = 00, Mode1= 01, Mode 2 = 1x (10 or 11)
• Bit No. 7: set to 1,if all Ports are as input/output port, 0 if individual pins of port C are to be
set or reset
Control Words for 8255 for Mode 0 Operation

Problem#1 on Control Word Register

• Ex1: Make the control word when the ports of Intel 8255 are defined as follows:
• Port A as an input port
• Mode of the Port A – Mode 0
• Port B as an output port
• Mode of the Port B – Mode 0
• Port Cupper as an input port
• Port Clower as an output port

7 6 5 4 3 2 1 0
1 0 0 1 1 0 0 0

The Control Word = 98 H

Problem#2 on Control Word Register

• Ex2: Form the control word for the following configuration of the ports of 8255 for Mode 0
• Port A – output
• Port B – output
• Port Cupper – input
• Port Clower – output
7 6 5 4 3 2 1 0
1 0 0 0 1 0 0 0

The Control Word = 88 H

Problem#3 on Control Word Register

• Ex3: Make the control word for the following arrangement of the ports of 8255 for Mode 0
• Port A – output
• Port B – output
• Port Cupper – output
• Port Clower – output

7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0

The Control Word = 80 H

Problem#4 on Control Word Register

• Ex4: Frame the control word for the following configuration of the ports of 8255 for
Mode 0
• Port A – input
• Port B – input
• Port Cupper – input
• Port Clower – input

7 6 5 4 3 2 1 0
1 0 0 1 1 0 1 1

The Control Word = 9B H

Problem#5 on Control Word Register

• Ex5: Make the control word when the ports of Intel 8255 are defined as follows:
• Port A – input, Mode of the Port A – Mode 1
• Port B – output, Mode of the Port B – Mode 1
• Port Cupper – input
• Port Clower – input/output

7 6 5 4 3 2 1 0
1 0 1 1 1 1 0 x

The Control Word = BC H or BD H

Problem#6 on Control Word Register

• Ex6: Frame the control word for the following configuration of the ports of 8255 for Mode 1
• Port A – output
• Port B – output
• Port Cupper – input
7 6 5 4 3 2 1 0
1 0 1 0 1 1 0 x
 • The Control Word = AC H if Port Clower = output
• The Cintrol Word = AD H if Port Clower = input

Problem#7 on Control Word Register

• Ex7: Find control word for the following configuration of the ports of 8255 for Mode 2
• Port A – bidirectional
• Port B – input, Mode of Port B – Mode 0
• Port Clower – output

7 6 5 4 3 2 1 0
1 1 x x x 0 1 0

• If assume all undefined bits 0, the control word is C2

• The computer ignores the undefined bits, for making the control word they me be assumed
either 1 or 0

Problem#8 on Control Word Register

• Ex8: Write the control word for the following configuration of the ports of 8255 for Mode 2
• Port A – bidirectional
• Port B – output, Mode of Port B – Mode 1
• If assume all undefined bits 0, the control word is C4
• If assume all undefined bits 1, the control word is FD

7 6 5 4 3 2 1 0
1 1 x x x 1 0 x

• If assume all undefined bits 0, the control word is C4

• If assume all undefined bits 1, the control word is FD

Problem#9 on Control Word Register

• Ex9: Determine control word for the following configuration of the ports of 8255
• Port A – output, Mode of Port A – Mode1
• Port B – output, Mode of Port B – Mode 0
• Port Clower – output
• Port Cupper – output

7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

The Control Word = ???

Problem#10 on Control Word Register

• Ex10: Determine control word for the following configuration of the ports of 8255
• Port A – input, Mode of Port A – Mode1
• Port B – output, Mode of Port B – Mode 0
• Port Clower – input
• Port Cupper – output
7 6 5 4 3 2 1 0
? ? ? ? ? ? ? ?

The Control Word = ???

Programmable Interrupt Controller (PIC)

• The programmable interrupt controller is used when several I/O devices transfer data using
interrupt
• They are to be connected to the same interrupt line of the microprocessor
• When the number of I/O devices is less than the number of interrupt lines of the
microprocessor
• Such controllers are not required

Intel 8259

• The Intel 8259 is a single chip programmable interrupt controller

• It is compatible with 8086, 8088 and 8085 microprocessor
• It is a 28-pin I.C. package and uses N-MOS technology
• It requires a single +5V supply for its operation

Schematic Diagram of Intel 8259

The Details of Pins of Intel 8259

• C͞ S: Chip Select
• W͞ R: Write, A low on this pin enables Intel 8259 to accept command from CPU
• R͞ D: Read, A low on this pin enables Intel 8259 to send various status signals on data bus for
CPU
• D0 – D7: Bidirectional data bus, control, status and interrupt information are transferred via
this bus
• CAS0 – CAS1: Cascade lines
• S͞ P/ E͞ N: Slave program/ Enable buffer, it is related to cascade control
• INT: Interrupt, it is used to interrupt CPU
• INTA: Interrupt acknowledge
• IR0 – IR7: Interrupt requests, I/O devices send interrupt request through these lines
• A0: Address line, it acts in conjunction with R͞ D, W͞ R and C͞ S
• 8 I/O devices can be connected to Intel 8259 through IR0 – IR7 lines
• The interrupt controller functions as overall manager in an interrupt driven system
 • If more than one I/O devices send interrupt request at the same time, the interrupt controllers
set the priority

Interfacing of Intel 8259 and I/O Devices

Internal Registers of 8259

Interrupt Request Register (IRR):

• It stores the interrupt request
• It keeps information about the interrupts inputs which have requested for interrupt service
• When an interrupt request is received, the corresponding bit in IRR is set
In-Service Register (ISR):
• Which interrupt is currently being serviced, this information is stored in the ISR
• The bit corresponding to the interrupt of the highest priority is selected
Interrupt Mask Register (IMR):
• It contains a specific bit for each interrupt line
• It is used to mask (disable) or enable (unmask) individual interrupt input
• An interrupt input can be masked by setting the corresponding bit to 1 in IMR
• An interrupt which is masked by software is not recognized and serviced
• Even if the corresponding bit is set in the IRR
• The 82C59 is the CHMOS version of NMOS 8259
• It consumes less power

Programmable Communication Interface (PCI)

• Programmable communication interface is used for serial data transmission

• Programmable peripheral designed for synchronous/ asynchronous serial data communication
• It receives parallel data from the CPU and transmit serial data after conversion
• Also receives serial data from the outside & transmits parallel data to the CPU after
conversion

Intel 8251

• The Intel 8251 is a programmable communication interface

• It is Universal Synchronous/ Asynchronous Receiver/ Transmitter (USART)
• It is compatible with 8085, 8086, 8088 etc.. systems
 • The I.C. chip is fabricated using N-channels silicon gate technology
• The 8251 can be used to transmit/ receive serial data
• It is packed in 28 pins I.C. package
• It accepts data in parallel format from the μP and converts them into serial data for
transmission

Schematic Diagram of Intel 8251

The Details of Pins of Intel 8251

• C͞ S: Chip Select
• C/D̅ : Control/Data, When it is low data is transmitted on data bus, when high control signal is
transmitted
• W͞ R: Write, when it is low the CPU writes data into Intel 8251
• R͞ D: Read, when it is low the CPU reads data from Intel 8251
• D0 – D7: Bidirectional data bus, control and status information are transferred via this bus
• DSR: Data Set Ready
• DTR: Data Terminal Ready
• RTS: Request to send
• CTS: Clear to send, A low on this pin enables 8251 to transmit serial data
• TxC: Transmitter clock, it governs the rate of data transmission
• TxE: Transmitter empty, TxE goes high when 8251 has no characters to transmit
• TxRDY: Transmitter ready
• RxRDY: Receiver ready
• RxD: Line for receiving data
• TxD: Line for serial data transmission
• RxC: Receiver clock, it governs the rate at which characters are received
• SYNDET/BRKDET: SYNC Detect/Break Detect
• VCC: Operating voltage
• GND: Ground CLK: Clock
• RESET: Indicates that the device is reset
• A high on TxRDY line informs CPU that the transmitter is ready to accept data
• DSR, DTR, RTS and CTS are standard modem control signals
• Modem is a modulating/ demodulating device
Block Diagram of Intel 8251

Description of Intel 8251:

• The block diagram of Intel 8251 has five different sections

• The five different sections are as follows:
1. 1.Read/ Write control logic
2. Transmitter
3. Receiver
4. Data Bus Buffer
5. Modem Control

Programmable Counter/Interval Timer

• A programmable counter/interval timer is used in real time application

• For timing and counting function such as BCD/ binary counting generation of accurate time
delay
• Generation of square wave of desired frequency, rate generation,
• Hardware/software triggered strobe signals, One shot signal of desired width etc..
• Popular programmable interval timer chips are Intel 8253 and Intel 8254
• Both are pin to pin compatible, operates in six modes

Intel 8253
• The Intel 8253 is a programmable counter/interval timer
• The 8253 is 24-pin I.C, package and operates at 5 Vdc
• It contains three independent 16-bit counter
 • The 8253 is compatible to 8085 microprocessor
• The 8253 operates in the frequency range of d.c. to 2.6 MHz
• The 8253 uses NMOS technology
• The programmer can program 8253 to operate in any one of the 6 operating modes
• It operates under software control

Schematic Diagram of Intel 8253

The Details of Pins of Intel 8253

• C͞ S: Chip Select
• W͞ R: Write, when it is low the CPU outputs data in the form mode information or loading of
counters
• R͞ D: Read, when it is low the CPU reads data
• D0 – D7: Bidirectional data bus
• A0, A1: These pins are connected to the address bus, these are used select on of the three
counters
• These are also used the address the control word registers for mode selection
• CLK0, CLK1 and CLK2 are clock for Counter 0, Counter 1, and Counter 2 respectively
• GATE0, GATE1 and GATE2 are gate terminals of Counter 0, Counter 1 and Counter 2
• OUT0, OUT1 and OUT2 are output terminals of Counter 0, Counter 1 and Counter 2
• VCC: Operating voltage
• GND: Ground
• The 8253 contains a data bus buffer, read/write logic and Control Word registers

Operating Modes of Intel 8253

• The Intel 8253 operates in the following six modes:

Mode 0: Interrupt on terminal count
Mode 1: Programmable one-shot
Mode 2: Rate generator
Mode 3: Square wave generator
Mode 4: Software triggered mode
Mode 5: Hardware triggered mode