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Arm Isa

The ARM instruction set architecture is a RISC architecture used in many embedded and mobile devices. It has 32-bit instructions and uses load/store architecture. It features conditional execution and status register for conditional branching. ARM supports various addressing modes including indexed, relative, pre-indexed with writeback, and post-indexed addressing. It also uses branch instructions with offsets to perform jumps in code. Subroutine calls use the BL instruction which both branches and links the return address to the link register.

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29 views20 pages

Arm Isa

The ARM instruction set architecture is a RISC architecture used in many embedded and mobile devices. It has 32-bit instructions and uses load/store architecture. It features conditional execution and status register for conditional branching. ARM supports various addressing modes including indexed, relative, pre-indexed with writeback, and post-indexed addressing. It also uses branch instructions with offsets to perform jumps in code. Subroutine calls use the BL instruction which both branches and links the return address to the link register.

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Win War
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ARM instruction set architecture

About ARM
● Advanced RISC Machines !
● ARM v4 architecture (latest)
● Popular for mobile phones, embedded devices
– Why?
ARM characteristics
● RISC like
– 32 bit instructions
– Load and store – to do memory I/O
– ALU operations work on registers
● Non-RISC (or CISC) like
– Mov R1, (R2)+ autoincrement type instruction, also autodecrement
– PC Relative addressing mode
● Conceptually like this: Mov R1, PC(-4)
– Conditional codes (N, Z, V, C)for branching
● What does this mean?
– Multiple byte transfers to-and-from memory
Concept: status register
● Many processors have a “status” register
● Used to store “status” of last instruction executed
● E.g. Whether last instruction resulted in an overflow, if the
computation result was zero, etc.
● Conditional branches
– One type: BNZ R1, LOOP
– Status register type: BNZ LOOP
● Here status register is checked, and not R1 or any such register
Addressing Modes
● Basic Indexed Addressing Mode
– Pre-indexed mode—The effective address of the operand is the sum of the
contents of a base register, Rn, and a signed offset.
– Examples
1) LDR Rd, [Rn, #offset]
Meaning
Rd ← [[Rn] + offset]
2) LDR Rd, [Rn, Rm]
meaning
Rd ← [[Rn] + [Rm]]
3) LDR Rd, [Rn]
Meaning
Rd ← [[Rn]]
Addressing Modes
● Relative Addressing Mode
– Program counter used as base register
E.g.
LDR R1, ADDR
Here effective address is PC + ADDR due to
pipelined execution, to be discussed later
In the figure, the offset
calculated by the
assembler is 52,
because the
updated PC will contain
1008 when the offset is
added to it during
program execution.

So although you wrote


ITEM in assembly,
assembler stores the
offset as 52 in machine
code, and at runtime it
resolves to “ITEM”
Addressing Modes
● Index Modes with Writeback
– LDR R0, [R1, −R2]!
performs the operation
R0 ← [[R1] − [R2]]
– LDR R0, [R1, −R2, LSL #4]!
performs (LSL #4 means multiply R2 by 2 4)
R0 ← [[R1] −16 × [R2]]
also loads effective address in R1 because “!” is specified
The Store instruction (STR) stores
the contents of R3 into the word at
memory location 1200.
Example of pushing the
contents of register R0,
which are 27, onto
a programmer-defined
stack.

Register R5 is used as the


stack pointer. Initially, it
contains the address 2012
of the current TOS (top-of-
stack) element.

Pre-indexed with writeback [Rn, ± Rm, shift]! instruction


STR R0, [R5, #−4]!
EA = [Rn] ± [Rm] shifted; The immediate offset −4 is
Rn ← [Rn] ± [Rm] shifted added to the contents of
R5 and the new value
(2008) is written back
into R5.
R5 is stack top, so 27 is
written at (2008)
Figure D.4a shows
the first three
numbers of a list of 25
numbers, starting at
memory address
1000 and spaced 25
words apart: First row
of 25x25 matrix

The numbers
in the first row of
the matrix can be
accessed
conveniently in a
program loop by
using the
Post-indexed
addressing mode,
with the offset
contained in a
register.
Addressing Modes
● Index Modes with Writeback
– Modifications of the auto-increment and auto-decrement addressing modes
– Pre-indexed with writeback mode—The effective address of the operand is
generated in the same way as in the Pre-indexed mode, then the effective
address is written back into Rn.
– Post-indexed mode—The effective address of the operand is the contents of
Rn. The offset is then added to this address and the result is written back into
Rn
● In the Pre-indexed mode, the exclamation character ‘!’ signifies that writeback is to be
done. The Post-indexed mode always involves writeback, so the exclamation character
is not needed.
Branch offset (2’s complement
number in instruction )
Calculation:
the value in the instruction
is shifted left two bit positions
(multiple of word offsets)

then
sign-extended to 32 bits to
generate the offset.

This offset is added to the


updated contents
of the Program Counter to
generate the branch target
address.

Here Instruction (generated by


assembler) containts the offset
(1100-1008)/4 = 23
The Branch and Link (BL)
instruction is used to call a
subroutine. It operates in the
same way as other branch
instructions, with one added
step.

The return address, which is


the address of the next
instruction after the BL
instruction, is loaded into
register R14, which acts as
the link register.

Since subroutines may be


nested, the contents of the
link register must be saved
on the processor stack before
a nested call to another
subroutine is made. Register
R13 is used as the processor
stack pointer.

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