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Real-time implementation of discrete wavelet transform on FPGA

Conference Paper · November 2010

DOI: 10.1109/ICOSP.2010.5655177 · Source: IEEE Xplore

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 Real-Time Implementation of Discrete Wavelet
Transform on FPGA
Mohammed Bahoura Hassan Ezzaidi
Department of Engineering, Department of Applied Sciences,
University of Quebec at Rimouski, University of Quebec at Chicoutimi,
300, allée des Ursulines, Rimouski, Qc, Canada. 550, boul. de l’Université, Chicoutimi, Qc, Canada.

Abstract—This paper presents a real-time architecture for  

forward/inverse wavelet transforms that take into account the 1 t−b
ψs,b (t) = √ ψ (2)
group delays of the used filters. The main idea is based on the s s
equalization of the filter path delays. The perfect reconstruction
of this architecture was evaluated for various data widths. This where s ∈ R+ represents the scale parameter, and b ∈ R
architecture was implemented on FPGA using XUP Virtex-II Pro represents the time translation. A large value of the parameter s
development board. stretches the basis wavelet function and allows the analysis of
I. I NTRODUCTION low-frequency components of the signal. On the other hand,
a small value of this parameter contracts this function and
Over the last decades, the wavelet transform (WT) has allows the analysis of the high-frequency components [7].
attracted attention of a large number of researchers from
diverse fields. Applications include signal and image denoising B. Discrete wavelet transform
and compressing, feature extraction, signal detection, pattern The discrete wavelet transform (DWT) is obtained by
recognition, etc. The extensive use of the wavelet transform discretizing the parameters s and b. In general, the scale
can be explained by its capability to provide simultaneous parameter is discretized by an exponential sampling with fixed
time-scale analysis and its indefinite number of basis functions. step, s = sj0 , and the translation parameter by integer multiple
Due to recent advances in technology and decreasing costs, of a scale dependent step, b = kb0 a, where s0 > 1, b0 > 0,
implementation of the discrete wavelet transform (DWT) on and k ∈ Z. Particularly, one can chose samples from dyadic
field programmable gate array (FPGA) has been widely de- grid: s0 = 2 et b0 = 1. The DWT is defined as:
veloped. To optimize time and resources consuming, many Z +∞
j
FPGA architectures of the WT have been proposed, which wj (k) = 2− 2 x(t)ψ ∗ (2−j t − k)dt (3)
are mainly based on convolution [1]–[3] and lifting [4]–[6] −∞

schemas. However, these architectures don’t take into account j

Here 2 represents the resolution or scale, j is the correspond-
the group delays of the finite impulse response (FIR) filters that ing resolution level and k is the shifting parameter.
are used to compute the DWT. When the signal is processed The discrete wavelet transform (DWT) is usually computed
sample by sample unlike frame by frame, the group delays using the pyramidal algorithm proposed by Mallat [9]. As
of different filter paths can sensibly affect processing in the represented in Fig. 1, this algorithm is based on a pair of
forward and inverse wavelet transforms schemas, as for signal lowpass (h) and highpass (g) filters, named also quadrature
denoising techniques. mirror filters (QMF), that are related through
In this paper, a real-time architecture for forward/inverse
wavelet transforms that take into account the group delays of g(n) = (−1)n h(N − n − 1) (4)
the used filters is proposed. This architecture was implemented
where N is the number of filter coefficients.
on FPGA using Xilinx System Generator tool.
These filters are constructed from the wavelet kernel ψ(t)
II. M ETHOD and its companion scaling function φ(t). They are related by
A. Continuous wavelet transform the following relations:
The continuous wavelet transform (CWT) of a signal x(t) √ X
φ(t) = 2 h(k)φ(2t − k) (5)
is defined by:
k
Z +∞ √ X
ψ
Wx (s, b) = ∗
x(t)ψs,b (t)dt (1) ψ(t) = 2 g(k)φ(2t − k) (6)
−∞ k

where (∗ ) denotes the complex conjugate and ψs,b (t) are the The outputs of the highpass filters are named details dj (n)
basis functions obtained by dilation or contraction (scaling), and those of the lowpass filters are named approximations
and translation of the mother wavelet ψ(t). aj (n).
Fig. 1. A 3-level diagram of the forward and inverse wavelet transforms. Each decomposition cell consists of a lowpass (H) and highpass (G) filter pair,
followed by a down-sampler (↓). However, the reconstruction one uses a lowpass (H)
e and a highpass (G)
e filter pair, proceeded by a up-sampler (↑).

Fig. 2. Real-time architecture of a 3-level pyramidal forward and inverse wavelet transforms. The delay of each path is obtained by summing the delays of
the cascaded filters in this path using the Noble identities [8].

TABLE I
The inverse discrete wavelet transform (IDWT) uses a pair C OEFFICIENTS OF THE FILTERS BASED ON THE DAUBECHIES 5 WAVELET.
h, and a highpass, ge, reconstruction filters. The
of a lowpass, e
Tap h g h g
analysis and synthesis filters are related to each other through:
e e
0 0.003335725285002 -0.160102397974125 0.160102397974125 0.003335725285002
1 -0.012580751999016 0.603829269797473 0.603829269797473 0.012580751999016
2 -0.006241490213012 -0.724308528438574 0.724308528438574 -0.006241490213012
ge(n) = g(N − n − 1) (7) 3 0.077571493840065 0.138428145901103 0.138428145901103 -0.077571493840065
4 -0.032244869585030 0.242294887066190 -0.242294887066190 -0.032244869585030
5 -0.242294887066190 -0.032244869585030 -0.032244869585030 0.242294887066190
6 0.138428145901103 -0.077571493840065 0.077571493840065 0.138428145901103
7 0.724308528438574 -0.006241490213012 -0.006241490213012 -0.724308528438574
h(n) = h(N − n − 1)
e (8) 8 0.603829269797473 0.012580751999016 -0.012580751999016 0.603829269797473
9 0.160102397974125 0.003335725285002 0.003335725285002 -0.160102397974125
However only orthogonal wavelets allow for perfect re-
construction of a signal by IDWT. Table I gives the coeffi-
cients of the analyis/synthesis filters that are derived from the • Path 1: τ = 7(τH + τHe ) + 8τ1
Daubechies 5 wavelet. • Path 2: τ = 3(τH + τHe ) + 4(τG + τGe ) + 8τ2
• Path 3: τ = (τH + τH e ) + 2(τG + τG e ) + 4τ3
C. Architecture with equalized filter path delays
• Path 4: τ = (τG + τG ) + 2τ4
For a given filter h, the group delay is defined as the negative
e

derivative of the phase response versus frequency. If τH + τHe = τG + τGe , delays in the first two paths aren’t
needed (τ1 = τ2 = 0).
dθ(ω)
τH (ω) = − (9)
dω III. E XPERIMENTS AND RESULTS
where θ(ω) is the phase of the filter H(ejω ) = |H(ejω )|ejθ(ω) . The proposed architecture was implemented on FPGA using
Let τH , τG , τHe and τGe the group delays of the filters Xilinx System Generator for DSP, which is high-level software
H, G, H e and G,e respectively. Compared to the conventional tool that enables the use of MATLAB/Simulink environment
architecture (Fig. 1), the proposed one (Fig. 2) ensures perfect to create and verify hardware designs for Xilinx FPGAs [10].
reconstruction in the real-time by equalizing delays on the An orthogonal wavelet (Daubechies 5) is used to generate
filter paths. The delay of each path is obtained by summing the analysis/synthesis filters (Table I) that guarantee the per-
the delays of the cascaded filters using the Noble identities [8]. fect reconstitution. The inserted delay in the filter paths is
Fig. 3. Group delays of the analysis/synthesis filters (based on Daubechies 5 wavelet). The left subfigure gives the group delays of individual and cascaded
analysis and synthesis lowpass filters, while the right one gives those of the highpass filters.

Fig. 4. Implementation of the conventional pyramidal architecture for discrete wavelet transform (top). The direct-form of the FIR filter was used to implement
the decomposition and the reconstruction filters (bottom). The coefficients of the analysis/synthesis filters based on the Daubechies 5 wavelet are given in
Table I.

determined by calculating the delay group for these filters. of the FIR filter was used to implement the decomposition and
Fig. 3 presents the group delays τH , τHe and τH + τHe on the reconstruction filters.
left and τG , τGe and τG + τGe on the right. It can be shown Results obtained with and without equalization of the path
that τH + τHe = τG + τGe = 9. Delays on Path 1 and Path delays are presented in Figs. 5 and 6, respectively. It can
2 are identical τ = 7(τH + τHe ) = 63. By equalizing Path 3 be shown that schema with equalization guaranties a perfect
and Path 4 to Path 1, one can deduce τ3 = 9 and τ4 = 27. reconstitution, |e(n)| < 1.5x10−12 , when quantization uses
Coefficients and group delays of the used filters are computed more than 54 bits. Near perfect reconstruction, |e(n)| <
using wfilters and grpdelay functions of Matlab. 2x10−3 , is obtained using only 18 bits. However, schema
Fig. 4 presents the DWT/IDWT schema that take into ac- without equalization, presents an important error regardless
count the equalization of the filter path delays. The direct-form of the number of bits.
Fig. 5. Results of simulation obtained with the proposed architecture (Fig. 4) using 1024 samples synthetic signal for various fixe-point formats. For example,
the fixe-point format FIX18.14 is a 2’s complement signed 18-bit number having 14 fractional bits. The original signal x(n) is given on top, followed by the
reconstructed signal with equalization xb(n) and the error signal e(n) that is given by x(n − τ ) − x
b(n). The whole delay τ depends on the wavelet based
filters length and the depth of the decomposition tree.

Fig. 6. As in Fig. 5 but without equalization of the filter path delays.

TABLE II
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