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2.1 Lec10 - VHDL - GenerateStatement

The document discusses different forms of the VHDL generate statement. It describes unconditional generate, which allows instantiating multiple copies of code without conditions. It provides examples of reversing vector elements and calculating parity. Conditional generate is also covered, allowing generation based on static conditions like determining if a number is even or odd. Examples are given as complete VHDL programs to demonstrate the concepts.

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15 views12 pages

2.1 Lec10 - VHDL - GenerateStatement

The document discusses different forms of the VHDL generate statement. It describes unconditional generate, which allows instantiating multiple copies of code without conditions. It provides examples of reversing vector elements and calculating parity. Conditional generate is also covered, allowing generation based on static conditions like determining if a number is even or odd. Examples are given as complete VHDL programs to demonstrate the concepts.

Uploaded by

jinto007
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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"Generate" Statement

1
The VHDL statement generate is a concurrent statement. It is used to
generate multiple instances of a program segment.

The generate statement has two different forms which are unconditional
generate and conditional generate.

Let's see these forms separately.

2
Unconditional Generate

The unconditional generate as its name implies has no conditional part. Its syntax is as
follows:

Label: for parameter in number-range generate


[declarative part
begin]
Statements
end generate [Label];

The use of Label is a must in generate statement, and the word begin is used if declarative
part is available in the generate statement.

3
Example-2.6: The generate statement in

Label1: for indx in 0 to 3 generate


y(indx)<=x(indx) xor x(indx+1);
end generate;

is the same as the program segment

y(0)<=x(0) xor x(1);


y(1)<=x(1) xor x(2);
y(2)<=x(2) xor x(3);
y(3)<=x(3) xor x(4);

That is, the same digital logic circuit synthesized for both program segments.

4
Example-2.7: Write a VHDL statement that reverses the elements of an 8-bit logic vector.

Solution-2.7: Let x and y be an 8-bit vectors. We can reverse the content of vector x using
the following VHDL statement:

reverse: for indx in 0 to 7 generate


y(indx)<=x(7-indx);
end generate;

5
Example-2.8: Write the previous example as a complete VHDL program.

Solution-2.8: The complete VHDL program is given in PR 2.6.


entity reverse_vector is
port( x_vec: in bit_vector(7 downto 0);
y_rvec: out bit_vector(7 downto 0));
end entity;

architecture logic_flow of reverse_vector is

begin

reverse: for indx in 0 to 7 generate


y_rvec(indx)<=x_vec(7-indx);
end generate;

end architecture;
6
PR 2.6 Program 2.6.
Parity Generator

The parity of the binary vector

𝑥 = 𝑥0 𝑥1 𝑥2 ⋯ 𝑥𝑁−1

is calculated as

𝑝 = 𝑥0 ⊕ 𝑥1 ⊕ ⋯ ⊕ 𝑥𝑁−1

where ⊕ is the xor operation.

Note that, xor is an odd function, i.e., if the number of ‘1’s in binary vector 𝑥 is an odd
integer, then 𝑝 = 1, otherwise 𝑝 = 0.
7
Example-2.9: Write a VHDL statement that calculates the parity for 16-bit logic vector.

Solution-2.9: Let x_vec be a 16-bit vector, and parr_vec be another 16-bit vector.

We can calculate the parity bit for x_vec using the following VHDL statement:

parr_vec(0)<=x(0);

parity: for indx in 1 to 15 generate


parr_vec(indx)<= parr_vec(indx-1) xor x_vec(indx);
end generate;

p<= parr_vec(15);

8
Example-2.10: Write the previous example as a complete VHDL program.
Solution-2.10: The complete VHDL program is given in PR 2.7.
entity parity_bit_generator is
port( x_vec: in bit_vector(15 downto 0);
p_bit: out bit);
end entity;

architecture logic_flow of parity_bit_generator is

signal parr_vec: bit_vector(15 downto 0);

begin
parr_vec(0)<= x_vec(0);

parity: for indx in 1 to 15 generate


parr_vec(indx)<= parr_vec(indx-1) xor x_vec(indx);
end generate;
p_bit<= parr_vec(15);
9
end architecture;
Conditional Generate

The syntax of the conditional generate is as

Label: if condition generate


[declarative_part
begin]
VHDL Statements
end generate [Label];

where 'condition' must be a static expression.

Note: Note that in VHDL syntax ⋯ shows the optional part.

10
Example-2.11: Write a VHDL statement that checks a constant positive integer and detects
whether it is an even or odd integer.

Solution-2.11: The VHDL program segment can be written as follows:

EvenDetector: if ((number mod 2)=0) generate


EvenFlag<=1;
end generate;

OddDetector: if ((number mod 2)=1) generate


EvenFlag<=0;
end generate;

11
Example-2.12: Write the previous example as a complete VHDL program.
Solution-2.12: The complete program is depicted in PR 2.8.

entity even_odd_detector is
port( EvenFlag: out bit);
end entity;

architecture logic_flow of even_odd_detector is


constant number: positive:=10001; -- 31-bit positive integer
begin
EvenDetector: if ((number mod 2)=0) generate
EvenFlag<=1;
end generate;
OddDetector: if ((number mod 2)=1) generate
EvenFlag<=0;
end generate;
end architecture; 12

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