PRODUCT

OBSOLETE CEMENT ISL6263C

M E N DED REPLA
NO RE C O M Center at
o u r Te c h n ical Support .com/tsc
contact or www.inte
rsil
1-888
Data -INTERSIL
Sheet July 8, 2010 FN6745.1

5-Bit VID Single-Phase Voltage Regulator Features

with Current Monitor for GPU Core Power • Precise Single-Phase Core Voltage Regulator
The ISL6263C IC is a Single-Phase Synchronous-Buck - 0.5% System Accuracy 0°C to +100°C
PWM voltage regulator for GPU core power application. It - Differential Remote GPU Die Voltage Sense
features Intersil’s Robust Ripple Regulator (R3)
• Real-Time GPU Current Monitor Output
Technology™. Integrated current monitor, differential remote
sense amplifier, MOSFET driver and bootstrap diode result • Applications up to 25A
in smaller implementation area and lower component cost.
• Input Voltage Range: +5.0V to +25.0V
Intersil’s R3 Technology™ combines the best features of • Programmable PWM Frequency: 200kHz to 500kHz
both fixed-frequency PWM and hysteretic PWM, delivering
excellent light-load efficiency and superior load transient • Pre-Biased Output Start-Up Capability
response by commanding variable switching frequency • 5-Bit Voltage Identification Input (VID)
during the transitory event. For maximum conversion - 0.41200V to 1.28750V
efficiency, the ISL6263C automatically enters diode - 25.75mV Steps
emulation mode (DEM) when the inductor current attempts
- Sequential or Non-Sequential VID Change On-the-Fly
to flow negative. DEM is highly configurable and easy to
set-up. A PWM filter can be enabled, which prevents the • Configurable PWM Modes
switching frequency from entering the audible spectrum as a - Forced Continuous Conduction Mode
result of extremely light load while in DEM. - Automatic Entry and Exit of Diode Emulation Mode
- Selectable Audible Frequency PWM Filter
The GPU core voltage can be dynamically programmed from
0.41200V to 1.28750V by the five VID input pins without • Integrated MOSFET Drivers and Bootstrap Diode
requiring sequential stepping of the VID states. The
• Choice of Current Sense Schemes
ISL6263C requires only one capacitor for both the soft-start
- Lossless Inductor DCR Current Sense
slew-rate and the dynamic VID slew-rate by internally
- Precise Resistive Current Sense
connecting the SOFT pin to the appropriate current source.
The voltage Kelvin sensing is accomplished with an • Overvoltage, Undervoltage and Overcurrent Protection
integrated unity-gain true differential amplifier.
• Pb-Free (RoHS Compliant)
Ordering Information Pinout
ISL6263C
TEMP (32 LD 5x5 QFN)
PART NUMBER PART RANGE PACKAGE PKG.
TOP VIEW
(Notes 2, 3) MARKING (°C) (Pb-Free) DWG. #
PGOOD

VR_ON
AF_EN

IMON

VID4

VID2
VID3

ISL6263CHRZ ISL6263 CHRZ -10 to +100 32 Ld 5x5 QFN L32.5x5

FDE

ISL6263CHRZ-T ISL6263 CHRZ -10 to +100 32 Ld 5x5 QFN L32.5x5 32 31 30 29 28 27 26 25

(Note 1)
RBIAS 1 24 VID1
NOTES:
1. Please refer to TB347 for details on reel specifications. SOFT 2 23 VID0

2. These Intersil Pb-free plastic packaged products employ special Pb- OCSET 3 22 PVCC
free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS VW 4 THERMAL PAD 21 LGATE
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free COMP 5 (BOTTOM) 20 PGND
peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020. FB 6 19 PHASE

3. For Moisture Sensitivity Level (MSL), please see device information VDIFF 7 18 UGATE
page for ISL6263C. For more information on MSL please see techbrief
TB363. VSEN 8 17 BOOT

9 10 11 12 13 14 15 16
ICOMP

VO

VSS
RTN

VIN

VDD
ISP
ISN

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas LLC
Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas LLC
All other trademarks mentioned are the property of their respective owners.
 Block Diagram

VR_ON PGOOD

VDD BOOT

VREF
 1.545V PWM
POR
 CONTROL
DRIVER UGATE
VREF
  DIODE
VSS 1:1 PGOOD EMULATION
2 
2

SCP SHORT CIRCUIT AUDIBLE PHASE

 FREQUENCY SHOOT-THROUGH
RBIAS OVERCURRENT FILTER
PROTECTION
OCSET  UNDERVOLTAGE PVCC
SEVERE
OCP OVERVOLTAGE
ISP   OVERVOLTAGE SOFT
CROWBAR
CONTROL
ISN  FAULT LATCH DRIVER LGATE

ICOMP 

VO  PGND

ISL6263C
X31
FDE

VSEN  AF_EN

RTN  VW

VDIFF gmVIN PWM


V W  VW

20% 30%
VID0


VID1 R3
VW


MODULATOR
VID2 VID DAC


ISS IDVID
VID3


 
VID4  gmVsoft VCOMP


E/A


SOFT FB COMP IMON VIN

July 8, 2010
FN6745.1

FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF THE ISL6263C

 ISL6263C

Simplified Application Circuit for DCR Current Sense

RVDD

V5V

CVDD CPVCC

VDD PVCC

RRBIAS

RBIAS VIN VIN

CSOFT

SOFT QHS CIN

UGATE

BOOT

PGOOD
RIMON
IMON CBOOT LOUT

CIMON PHASE VOUT

VID<0:4> QLS COUT

VR_ON LGATE

AF_EN PGND

FDE

VOUT VSEN
RS
VGND RTN
RNTC
VW ISP

ISL6263C

RFSET CFSET CN RP RNTCS

VO

CCOMP1
ROCSET RIS1
COMP OCSET

RCOMP CCOMP2 ISN

FB

VDIFF
RIS2 CIS
RDIFF2 CDIFF ICOMP
VSS
RGND
RDIFF1

0

FIGURE 2. ISL6263C GPU CORE VOLTAGE REGULATOR SOLUTION WITH DCR CURRENT SENSE

3 FN6745.1
July 8, 2010
 ISL6263C

Simplified Application Circuit for Resistive Current Sense

RVDD
V5V

CVDD CPVCC

VDD PVCC

RRBIAS

RBIAS VIN VIN

CSOFT

SOFT QHS CIN

UGATE

BOOT

PGOOD
RIMON
IMON CBOOT LOUT
RSNS
CIMON PHASE VOUT

VID<0:4> QLS COUT

VR_ON LGATE

AF_EN PGND

FDE

VOUT VSEN

VGND RTN
RS

VW ISP

ISL6263C

RFSET CFSET CN

VO

CCOMP1
ROCSET RIS1
COMP OCSET

RCOMP CCOMP2
ISN
FB

VDIFF
RIS2 CIS
RDIFF2 CDIFF
ICOMP
VSS
RGND
RDIFF1

0Ω

FIGURE 3. ISL6263C GPU CORE VOLTAGE REGULATOR SOLUTION WITH RESISTOR CURRENT SENSE

4 FN6745.1
July 8, 2010
 ISL6263C

Absolute Voltage Ratings Thermal Information

VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V Thermal Resistance (Typical, Notes 4, 5) JA (°C/W) JC (°C/W)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V 32 Ld QFN Package. . . . . . . . . . . . . . . 35 6
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +150C
VSS to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Operating Temperature Range . . . . . . . . . . . . . . . .-10C to +100C
PHASE to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
(<100ns Pulse Width, 10µJ) -5.0V Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V http://www.intersil.com/pbfree/Pb-FreeReflow.asp
BOOT to VSS or PGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
UGATE. . . . . . . . . . . . . . . . . . . (DC) -0.3V to PHASE, BOOT +0.3V
Recommended Operating Conditions
(<200ns Pulse Width, 20µJ) -4.0V
LGATE . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to PGND, PVCC +0.3V Ambient Temperature Range. . . . . . . . . . . . . . . . . -10°C to +100°C
(<100ns Pulse Width, 4µJ) -2.0V VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +25V
ALL Other Pins. . . . . . . . . . . . . . . . . . . . . -0.3V to VSS, VDD +0.3V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
FDE to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +3.3V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications These specifications apply for TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating
temperature range, -10°C to +100°C.

MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 6) TYP (Note 6) UNITS
VIN

VIN Input Resistance R VIN VR_ON = 3.3V 1.0 MΩ

VIN Shutdown Current IVIN_SHDN VR_ON = 0V, VIN = 25V 1.0 µA

VDD and PVCC

VDD Input Bias Current IVDD VR_ON = 3.3V 2.7 3.3 mA

VDD Shutdown Current IVDD_SHDN VR_ON = 0V, VDD = 5.0V 1.0 µA

VDD POR THRESHOLD

Rising VDD POR Threshold Voltage V 4.35 4.50 V

VDD_THR
Falling VDD POR Threshold Voltage V 3.85 4.10 V
VDD_THF
REGULATION

Output Voltage Range V VID<4:0> = 00000 1.28750 V

OUT_MAX
V VID<4:0> = 11111 0.41200 V
OUT_MIN
VID Voltage Step VID<4:0> = 00000 to 11110 (1.28750V 25.75 mV/step
to 0.51500V)

VID<4:0> = 11110 to 11111 (0.51500V to 103 mV

0.41200V)

System Accuracy VID = 1.28750V to 0.74675V -0.5 0.5 %

TA = 0°C to +100°C

VID = 0.72100V to 0.51500V -1.0 1.0 %

TA = 0°C to +100°C

VID = 0.41200 -3.0 3.0 %

TA = 0°C to +100°C

5 FN6745.1
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 ISL6263C

Electrical Specifications These specifications apply for TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating
temperature range, -10°C to +100°C. (Continued)

MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 6) TYP (Note 6) UNITS

PWM

Nominal Frequency f RFSET = 7kΩVCOMP = 2V 318 333 348 kHz

SW
Frequency Range 200 500 kHz

Audio Filter Frequency f 28 kHz

AF
AMPLIFIERS

Error Amplifier DC Gain (Note 7) AV0 90 dB

Error Amplifier Gain-Bandwidth Product GBW CL = 20pF 18 MHz

(Note 3)

Error Amp Slew Rate (Note 7) SR CL = 20pF 5 V/µs

FB Input Bias Current IFB VFB = 1.28750V 10 150 nA

Current Sense Amplifier Offset V -0.3 0.3 mV

ISENSE_OFS
RBIAS Voltage V R
RBIAS RBIAS = 150kΩ 1.495 1.515 1.535 V

SOFT-START CURRENT

Soft-Start Current ISS -47 -42 -37 µA

Soft Dynamic VID Current IDVID |SOFT - REF|>100mV ±180 ±205 ±230 µA
CURRENT MONITOR

Current Monitor Output Voltage Range V V V

IMON ICOMP - O = 40mV 1.22 1.24 1.26 V
V V
ICOMP - O = 10mV 0.285 0.310 0.335 V
Current Monitor Maximum Output Voltage V 3.1 3.4 V
IMONMAX
Current Monitor Maximum Current Sinking VIMON/ VIMON/ VIMON/
A
Capability 250Ω 180Ω 130Ω

Current Monitor Sourcing Current ISC_IMON V V

ICOMP - O = 40mV 2.0 mA

Current Monitor Sinking Current ISK_IMON V V

ICOMP - O = 40mV 2.0 mA

Current Monitor Impedance (Note 7) IIMON ISK_IMON, IIMON ISC_IMON 7 Ω

GATE DRIVER

UGATE Source Resistance (Note 7) RUGSRC 500mA Source Current 1.0 1.5 Ω

UGATE Source Current (Note 7) IUGSRC VUGATE_PHASE = 2.5V 2.0 A

UGATE Sink Resistance (Note 7) RUGSNK 500mA Sink Current 1.0 1.5 Ω

UGATE Sink Current (Note 7) IUGSNK VUGATE_PHASE = 2.5V 2.0 A

LGATE Source Resistance (Note 7) RLGSRC 500mA Source Current 1.0 1.5 Ω

LGATE Source Current (Note 7) ILGSRC VLGATE_PGND = 2.5V 2.0 A

LGATE Sink Resistance (Note 7) RLGSNK 500mA Sink Current 0.5 0.9 Ω

LGATE Sink Current (Note 7) ILGSNK VLGATE_PGND = 2.5V 4.0 A

UGATE Pull-Down Resistor RPD 1.1 kΩ

UGATE Turn-On Propagation Delay tPDRU PVCC = 5V, UGATE open 20 30 44 ns

LGATE Turn-On Propagation Delay tPDRL PVCC = 5V, LGATE open 7 15 30 ns

BOOTSTRAP DIODE

Forward Voltage VF PVCC = 5V, IF = 10mA 0.56 0.69 0.76 V

Reverse Leakage IR VR = 16V 5.0 µA

6 FN6745.1
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 ISL6263C

Electrical Specifications These specifications apply for TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating
temperature range, -10°C to +100°C. (Continued)

MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 6) TYP (Note 6) UNITS

POWER GOOD and PROTECTION MONITOR

PGOOD Low Voltage VPGOOD IPGOOD = 4mA 0.11 0.40 V

PGOOD Leakage Current IPGOOD VPGOOD = 3.3V -1.0 1.0 µA

Overvoltage Threshold (VO-VSOFT) VOVP VO rising above VSOFT > 1ms 155 195 235 mV

Severe Overvoltage Threshold VOVPS VO rising above 1.55V reference > 0.5µs 1.525 1.550 1.575 V

OCSET Reference Current IOCSET RRBIAS = 150kΩ 9.9 10.1 10.3 µA

OCSET Voltage Threshold Offset VOCSET_OFS VICOMP rising above VOCSET > 120µs -3 3 mV

Undervoltage Threshold (VSOFT-VO) VUVF VO falling below VSOFT for > 1ms -360 -300 -240 mV

CONTROL INPUTS

VR_ON Input Low VVR_ONL 1 V

VR_ON Input High VVR_ONH 2.3 V

AF_EN Input Low VAF_ENL 1 V

AF_EN Input High VAF_ENH 2.3 V

VR_ON Leakage IVR_ONL VVR_ON = 0V -1.0 0 µA

IVR_ONH VVR_ON = 3.3V 0 1.0 µA

AF_EN Leakage IAF_ENL VAF_EN = 0V -1.0 0 µA

IAF_ENH VAF_EN = 3.3V 0.45 1.0 µA

VID<4:0> Input Low VVIDL 0.4 V

VID<4:0> Input High VVIDH 0.7 V

FDE Input Low VFDEL 0.3 V

FDE Input High VFDEH 0.7 V

VID<4:0> Leakage IVIDL VVID = 0V -1.0 0 µA

IVIDH VVID = 1.0V 0.45 1.0 µA

FDE Leakage IFDEL VFDE = 0V -1.0 0 µA

IFDEH VFDE = 1.0V 0.45 1.0 µA

NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Limits established by characterization and are not production tested.

7 FN6745.1
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 ISL6263C

Functional Pin Descriptions UGATE (Pin 18) - High-side MOSFET gate driver output.
Connect to the gate of the high-side MOSFET.
RBIAS (Pin 1) - Sets the internal 10µA current reference.
Connect a 150kΩ±1resistor from RBIAS to VSS. PHASE (Pin 19) - Current return path for the UGATE
high-side MOSFET gate driver. Detects the polarity of the
SOFT (Pin 2) - Sets the output voltage slew-rate. Connect
PHASE node voltage for diode emulation. Connect the
an X5R or X7R ceramic capacitor from SOFT to VSS. The
PHASE pin to the drains of the low-side MOSFETs.
SOFT pin is the non-inverting input of the error amplifier.
PGND (Pin 20) - Current return path for the LGATE low-side
OCSET (Pin 3) - Sets the overcurrent threshold. Connect a
MOSFET gate driver. The PGND pin only conducts current
resistor from OCSET to VO.
when LGATE pulls down. Connect the PGND pin to the
VW (Pin 4) - Sets the static PWM switching frequency in sources of the low-side MOSFETs.
continuous conduction mode. Connect a resistor from VW to
LGATE (Pin 21) - Low-side MOSFET gate driver output.
COMP.
Connect to the gate of the low-side MOSFET.
COMP (Pin 5) - Connects to the output of the control loop
PVCC (Pin 22) - Input power supply for the low-side
error amplifier.
MOSFET gate driver, and the high-side MOSFET gate
FB (Pin 6) - Connects to the inverting input of the control driver, via the internal bootstrap diode connected between
loop error amplifier. the PVCC and BOOT pins. Connect to +5VDC and decouple
with at least 1µF of an MLCC capacitor from the PVCC pin to
VDIFF (Pin 7) - Connects to the output of the VDIFF
the PGND pin.
differential amplifier. Together with the FB pin, it is used for
the output voltage feedback. VID0:VID4 (Pin 23:Pin 27) - Voltage identification inputs.
VID0 input is the least significant bit (LSB) and VID4 input is
VSEN (Pin 8) - This is the VOUT input of the GPU processor
the most significant bit (MSB).
Kelvin connection. Connects internally to the non-inverting
inputs of the VDIFF differential amplifier. IMON (Pin 28) - A voltage signal proportional to the output
current of the converter.
RTN (Pin 9) - This is the VGND input of the GPU processor
Kelvin connection. Connects internally to the inverting inputs VR_ON (Pin 29) - A high logic signal on this pin enables the
of the VDIFF differential amplifier. converter and a low logic signal disables the converter.
ICOMP (Pin 10) - Connects to the output of the differential AF_EN (Pin 30) - Used in conjunction with VID0:VID4 and
current sense amplifier and to the non-inverting inputs of the FDE pins to program the diode-emulation and audio filter
overcurrent comparator. Used for output current monitor and behavior. Refer to Table 2.
overcurrent protection.
PGOOD (Pin 31) - The PGOOD pin is an open-drain output
ISN (Pin 11) - This is the feedback of the current sense that indicates when the converter is able to supply regulated
amplifier. Connects internally to the inverting input of the voltage. Connect the PGOOD pin to a maximum of 5V
current sense amplifier. Used for output current sense. through a pull-up resistor.
VO (Pin 12) - Connects to the inverting inputs of the VDIFF FDE (Pin 32) - Used in conjunction with VID0:VID4 and
differential amplifier. AF_EN pins to program the diode-emulation and audio filter
behavior. Refer to Table 2.
ISP (Pin 13) - Connects to the non-inverting input of the
current sense amplifier. Used for output current sense. BOTTOM - Connects to substrate. Electrically isolated but
should be connected to VSS. Requires best practical
VIN (Pin 14) - Connects to the R3 PWM modulator providing
thermal coupling to PCB.
input voltage feed-forward. For optimum input voltage
transient response, connect near the drain of the high-side
MOSFETs.

VSS (Pin 15) - Analog ground.

VDD (Pin 16) - Input power supply for the IC. Connect to
+5VDC and decouple with at least a 1µF MLCC capacitor
from the VDD pin to the VSS pin.

BOOT (Pin 17) - Input power supply for the high-side

MOSFET gate driver. Connect an MLCC bootstrap capacitor
from the BOOT pin to the PHASE pin.

8 FN6745.1
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 ISL6263C

Theory of Operation TABLE 1. VID AND DAC TRUTH TABLE

GPU VSOFT
The R3 Modulator MODE VID4 VID3 VID2 VID1 VID0 (DAC) (V)
The heart of the ISL6263C is Intersil’s Robust-Ripple-
- - - - - 0
Regulator (R3) Technology™. The R3 modulator is a hybrid
of fixed frequency PWM control, and variable frequency 0 0 0 0 0 1.28750
hysteretic control that will simultaneously affect the PWM 0 0 0 0 1 1.26175
switching frequency and PWM duty cycle in response to
0 0 0 1 0 1.23600
input voltage and output load transients.
0 0 0 1 1 1.21025
The term “Ripple” in the name “Robust-Ripple-Regulator”
refers to the synthesized voltage-ripple signal VR that 0 0 1 0 0 1.18450
appears across the internal ripple-capacitor CR. The V R 0 0 1 0 1 1.15875
signal is a representation of the output inductor ripple 0 0 1 1 0 1.13300
current. Transconductance amplifiers measuring the input

GPU MODE 1
voltage of the converter and the output set-point voltage 0 0 1 1 1 1.10725
VSOFT, together produce the voltage-ripple signal VR. 0 1 0 0 0 1.08150

A voltage window signal V W is created across the VW and 0 1 0 0 1 1.05575

COMP pins by sourcing a current proportional to gmVSOFT 0 1 0 1 0 1.03000
through a parallel network consisting of resistor RFSET and
0 1 0 1 1 1.00425
capacitor CFSET. The synthesized voltage-ripple signal VR
along with similar companion signals are converted into 0 1 1 0 0 0.97850
PWM pulses. 0 1 1 0 1 0.95275
The PWM frequency is proportional to the difference in 0 1 1 1 0 0.92700
amplitude between V W and VCOMP. Operating on these 0 1 1 1 1 0.90125
large-amplitude, low noise synthesized signals allows the
ISL6263C to achieve lower output ripple and lower phase 1 0 0 0 0 0.87550
jitter than either conventional hysteretic or fixed frequency 1 0 0 0 1 0.84975
PWM controllers. Unlike conventional hysteretic converters, 1 0 0 1 0 0.82400
the ISL6263C has an error amplifier that allows the controller
to maintain tight voltage regulation accuracy throughout the 1 0 0 1 1 0.79825
VID range from 0.41200V to 1.28750V. 1 0 1 0 0 0.77250

Voltage Programming 1 0 1 0 1 0.74675

The output voltage VOUT is regulated to the SOFT pin 1 0 1 1 0 0.72100

voltage, VSOFT, which is determined by the DAC output. The 1 0 1 1 1 0.69525
GPU MODE 2

DAC output voltage is programmed by the external five VID

1 1 0 0 0 0.66950
pins. Refer to Table 1 for the VID voltage programming
specification. 1 1 0 0 1 0.64375

Power-On Reset 1 1 0 1 0 0.61800

The ISL6263C is disabled until the voltage at the VDD pin 1 1 0 1 1 0.59225
has increased above the rising VDD power-on reset (POR) 1 1 1 0 0 0.56650
VDD_THR threshold voltage. The controller will become
1 1 1 0 1 0.54075
disabled when the voltage at the VDD pin decreases below
the falling POR VDD_THF threshold voltage. 1 1 1 1 0 0.51500

1 1 1 1 1 0.41200
Start-Up Timing
Figure 4 shows the ISL6263C start-up timing. Once VDD
13 switching cycles, then changes the open-drain output of
has ramped above VDD_THR, the controller can be enabled
the PGOOD pin to high impedance. During soft-start, the
by pulling the VR_ON pin voltage above the input-high
regulator always operates in continuous conduction mode
threshold VVR_ONH. Approximately 100µs later, the soft-start
(CCM).
capacitor CSOFT begins slewing to the designated VID
set-point as it is charged by the soft-start current source ISS.
The VOUT output voltage of the converter follows the VSOFT
voltage ramp to within 10% of the VID set-point then counts

9 FN6745.1
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 ISL6263C

VDD LOUT
DCR
10µA PHASE
 ROCSET
OCSET COUT

OCP RS
ISP
 
Isense ESR
ISN


RNTCS
ICOMP

VO

RIS2

CN

Rp


CIS

RNTC
RIS1

ROPN1
CFILTER1 RFILTER1
VSEN TO
 VOUT PROCESSOR
RFILTER2 KELVIN
RTN VGND
 CONNECTIONS
VDIFF

ROPN2
CFILTER2 CFILTER3

FIGURE 5. SIMPLIFIED GPU KELVIN SENSE AND INDUCTOR DCR CURRENT SENSE

ICOMP pin minus the output voltage measured at the VO

VR_ON
pin, is proportional to the total inductor current. This
information is used for overcurrent protection and current
monitoring. It is important to note that this current
90%
~100µs measurement should not be confused with the synthetic
current ripple information created within the R3 modulator.
VSOFT/VOUT
When using inductor DCR current sense, an NTC
compensation network is optional to compensate the
positive temperature coefficient of the copper winding, thus
PGOOD maintaining the current sense accuracy.

Processor Kelvin Voltage Sense

13 SWITCHING CYCLES
The remote voltage sense input pins VSEN and RTN of the
FIGURE 4. ISL6263C START-UP TIMING
ISL6263C are to be terminated at the die of the GPU. Kelvin
sense allows the voltage regulator to tightly control the
Static Regulation
processor voltage at the die, compensating for various
The output voltage VOUT will be regulated to the value set resistive voltage drops in the power delivery path.
by the VID inputs per Table 1. A true differential amplifier
connected to the VSEN and RTN pins implements processor Since the voltage feedback is sensed at the processor die,
Kelvin sense for precise core voltage regulation at the GPU removing the GPU will open the voltage feedback path of the
voltage sense points. regulator, causing the output voltage to rise towards VIN.
The ISL6263C will shut down when the voltage between the
The ISL6263C can accommodate DCR current sense or VO and VSS pins exceeds the severe overvoltage protection
discrete resistor current sense. The DCR current sense uses threshold VOVPS of 1.55V. To prevent this issue from
the intrinsic series resistance of the output inductor, as occurring, it is recommended to install resistors ROPN1 and
shown in the application circuit of Figure 2. The discrete ROPN2, as shown in Figure 5. These resistors provide
resistor current sense uses a shunt resistor in series with the voltage feedback from the regulator local output in the
output inductor, as shown in the application circuit in absence of the GPU. These resistors should be in the range
Figure 3. In both cases, the signal is fed to the non-inverting of 20Ω to 100Ω
input of the current sense amplifier at the ISP pin, where it is
measured differentially with respect to the output voltage of
the converter at the VO pin and amplified. The voltage at the

10 FN6745.1
July 8, 2010
 ISL6263C

High Efficiency Diode Emulation Mode TABLE 2. DIODE EMULATION MODE and AUDIO FILTER
The ISL6263C operates in continuous-conduction-mode GPU MODE DEM VOLTAGE AUDIO
(CCM) during heavy load for minimum conduction loss by (VID code) FDE AF_EN STATUS WINDOW FILTER
forcing the low-side MOSFET to operate as a synchronous 0 - DISABLED NOM -
rectifier. An improvement in light-load efficiency is achieved MODE 1
1 - ENABLED 130% NOM -
by allowing the converter to operate in diode-emulation
mode (DEM) where the low-side MOSFET behaves as a - 0 ENABLED 150% NOM -
smart-diode, forcing the device to block negative inductor MODE 2 1 1 ENABLED 130% NOM -
current flow.
0 1 ENABLED 130% NOM ENABLED
Positive-going inductor current flows from either the source
of the high-side MOSFET, or the drain of the low-side Smooth mode transitions are facilitated by the R3 modulator,
MOSFET. Negative-going inductor current flows into the which correctly maintains the internally synthesized ripple
source of the high-side MOSFET, or into the drain of the current information throughout mode transitions.
low-side MOSFET. When the low-side MOSFET conducts
Current Monitor
positive inductor current, the phase voltage will be negative
with respect to the VSS pin. Conversely, when the low-side The ISL6263C features a current monitor output. The
MOSFET conducts negative inductor current, the phase voltage between the IMON and VSS pins is proportional to
voltage will be positive with respect to the VSS pin. Negative the output inductor current. The output inductor current is
inductor current occurs when the output DC load current is proportional to the voltage between the ICOMP and VO pins.
less than ½ the inductor ripple current. Sinking negative The IMON pin has source and sink capability for close
inductor current through the low-side MOSFET lowers tracking of transient current events. The current monitor
efficiency through unnecessary conduction losses. Efficiency output is expressed in Equation 1:
can be further improved with a reduction of unnecessary V IMON =  V ICOMP – V O   31 (EQ. 1)
switching losses by reducing the PWM frequency. The PWM
frequency can be configured to automatically make a Protection
step-reduction upon entering DEM by forcing a The ISL6263C provides overcurrent protection (OCP),
step-increase of the window voltage V W. The window overvoltage protection (OVP), and undervoltage protection
voltage can be configured to increase approximately 30%, (UVP), as shown in Table 3.
50%, or not at all. The characteristic PWM frequency Overcurrent protection is tied to the current sense amplifier.
reduction, coincident with decreasing load, is accelerated by Given the overcurrent set point IOC, the maximum voltage
the step-increase of the window voltage. at ICOMP pin VICOMP(max) (which is the voltage when
The converter will enter DEM after detecting three OCP happens) can be determined by the current sense
consecutive PWM pulses with negative inductor current. The network (explained in “Inductor DCR Current Sense” on
negative inductor current is detected during the time that the page 14 and “Resistor Current Sense” on page 15). During
high-side MOSFET gate driver output UGATE is low, with the start-up, the ICOMP pin must fall 25mV below the OCSET
exception of a brief blanking period. The voltage between pin to reset the overcurrent comparator, which requires
the PHASE pin and VSS pin is monitored by a comparator (VICOMP(max) - VO) > 25mV.
that latches upon detection of positive phase voltage. The The OCP threshold detector is checked every 15µs and will
converter will return to CCM after detecting three increment a counter if the OCP threshold is exceeded,
consecutive PWM pulses with positive inductor current. conversely the counter will be decremented if the load
The inductor current is considered positive if the phase current is below the OCP threshold. The counter will latch an
comparator has not been latched while UGATE is low. OCP fault when the counter reaches eight. The fastest OCP
response for overcurrent levels that are no more than 2.5
Because the switching frequency in DEM is a function of times the OCP threshold is 120µs, which is eight counts at
load current, very light load condition can produce 15µs each. The ISL6263C protects against hard shorts by
frequencies well into the audio band. To eliminate this latching an OCP fault within 2µs for overcurrent levels
audible noise, an audio filter can be enabled that briefly turns exceeding 2.5 times the OCP threshold.
on the low-side MOSFET gate driver LGATE approximately
every 35µs. The overcurrent threshold is determined by the resistor
ROCSET between OCSET pin and VO pin. The value of
The DEM and audio filter operation are programmed by the ROCSET is calculated in Equation 2:
AF_EN and FDE pins in conjunction with VID0:VID4 V ICOMP  max  – V O
according to Table 2. R OCSET = ----------------------------------------------------
10A (EQ. 2)

11 FN6745.1
July 8, 2010
 ISL6263C

For example, choose VICOMP(max) - VO = 80mV. ROCSET TABLE 3. FAULT PROTECTION SUMMARY OF
can use a 8.06kΩresistor, according to Equation 2. ISL6263C (Continued)

FAULT
UVP and OVP are independent of the OCP. If the output
DURATION
voltage measured on the VO pin is less than +300mV below PRIOR TO PROTECTION FAULT
the voltage on the SOFT pin for longer than 1ms, the FAULT TYPE PROTECTION ACTIONS RESET
controller will latch a UVP fault. If the output voltage
Severe Immediately UGATE, and Cycle
measured on the VO pin is >195mV above the voltage on Overvoltage PGOOD latched low, VDD only
the SOFT pin for longer than 1ms, the controller will latch an (+1.55V) LGATE toggles ON
OVP fault. Keep in mind that VSOFT will equal the voltage between VO pin when VO > 1.55V
level commanded by the VID states only after the soft-start and VSS pin OFF when
VO < 0.77V
capacitor CSOFT has slewed to the VID DAC output voltage.
until fault reset
The UVP and OVP detection circuits act on static and
dynamic VSOFT voltage. Undervoltage 1ms LGATE, UGATE, and Cycle
(-300mV) PGOOD latched low VR_ON or
When an OCP, OVP, or UVP fault has been latched, PGOOD between VO pin VDD
becomes a low impedance and the gate driver outputs and SOFT pin
UGATE and LGATE are pulled low. The energy stored in the
inductor is dissipated as current flows through the low-side Gate-Driver Outputs LGATE and UGATE
MOSFET body diode. The controller will remain latched in The ISL6263C has internal high-side and low-side
the fault state until the VR_ON pin has been pulled below the N-Channel MOSFET gate-drivers. The LGATE driver is
falling VR_ON threshold voltage VVR_ONL or until VDD has optimized for low duty-cycle applications where the low-side
gone below the falling POR threshold voltage VVDD_THF. MOSFET conduction losses are dominant. The LGATE
pull-down resistance is very low in order to clamp the
A severe-overvoltage protection fault occurs immediately after
gate-source voltage of the MOSFET below the VGS(th) at
the voltage between the VO and VSS pins exceed the rising
turn-off. The current transient through the low-side gate at
severe-overvoltage threshold VOVPS which is 1.545V, the
turn-off can be considerable due to the characteristic large
same reference voltage used by the VID DAC. The ISL6263C
switching charge of a low rDS(ON) MOSFET.
will latch UGATE and PGOOD low but unlike other protective
faults, LGATE remains high until the voltage between VO and
VSS falls below approximately 0.77V, at which time LGATE is
PWM
pulled low. The LGATE pin will continue to switch high and low
at 1.545V and 0.77V until VDD has gone below the falling
POR threshold voltage VVDD_THF. This provides maximum
protection against a shorted high-side MOSFET while LGATE
preventing the output voltage from ringing below ground. The 1V

severe-overvoltage fault circuit can be triggered after another

fault has already been latched.
UGATE
TABLE 3. FAULT PROTECTION SUMMARY OF 1V
ISL6263C

FAULT
t PDRU t PDRL
DURATION
PRIOR TO PROTECTION FAULT
FIGURE 6. GATE DRIVER TIMING DIAGRAM
FAULT TYPE PROTECTION ACTIONS RESET

Overcurrent 120µs LGATE, UGATE, and Cycle Adaptive shoot-through protection prevents the gate-driver
PGOOD latched low VR_ON or outputs from going high until the opposite gate-driver output
VDD has fallen below approximately 1V. The UGATE turn-on
Short Circuit <2µs LGATE, UGATE, and Cycle propagation delay tPDRU and LGATE turn-on propagation
PGOOD latched low VR_ON or delay tPDRL are found in the “Electrical Specifications” table
VDD on page 6. The power for the LGATE gate-driver is sourced
Overvoltage 1ms LGATE, UGATE, and Cycle directly from the PVCC pin. The power for the UGATE
(+195mV) PGOOD latched low VR_ON or gate-driver is sourced from a boot-strap capacitor connected
between VO pin VDD across the BOOT and PHASE pins. The boot capacitor is
and SOFT pin
charged from PVCC through an internal boot-strap diode
each time the low-side MOSFET turns on, pulling the
PHASE pin low.

12 FN6745.1
July 8, 2010
 ISL6263C

Internal Bootstrap Diode output voltage is commanded to rise, and discharging

The ISL6263C has an integrated boot-strap Schottky diode CSOFT when the output voltage is commanded to fall.
connected from the PVCC pin to the BOOT pin. Simply The GPU voltage regulator may require a minimum voltage
adding an external capacitor across the BOOT and PHASE slew rate, which will be guaranteed by the value of CSOFT.
pins completes the bootstrap circuit. For example, if the regulator requires 10mV/µs slew rate, the
2.0 value of CSOFT can be calculated using Equation 4:
1.8 I DVIDmin 180A
C SOFT = ------------------------- = ------------------ = 0.018F
10mV
 --------------- 10K
1.6 -
 s  (EQ. 4)
1.4
CBOOT_CAP (µF)

1.2 I DVID is the soft-dynamic VID current source, and its

minimum value is specified in the “Electrical Specifications”
1.0
table on page 5. Choosing the next lower standard
0.8
component value of 0.015µF will guarantee 10mV/µs slew
QGATE = 100nC
0.6 rate. This choice of CSOFT controls the startup slew-rate as
50

0.4 well. One should expect the output voltage during soft-start
nC

to slew to the voltage commanded by the VID settings at a

0.2
20nC
nominal rate given by Equation 5:
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
dV SOFT I SS 42A 2.8mV
VBOOT_CAP (V) - = -----------------------  ------------------
----------------------- = ------------------
dt C SOFT 0.015F s (EQ. 5)
FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE Note that the slew rate is the average rate of change
The minimum value of the bootstrap capacitor can be between the initial and final voltage values.
calculated using Equation 3: It is worth it to mention that the surge current charges the
Q GATE output capacitors when the output voltage is commanded to
C BOOT  ------------------------
V BOOT (EQ. 3) rise. This surge current could be high enough to trigger the
OC protection circuit if the voltage slew rate is too high,
where QGATE is the amount of gate charge required to fully or/and the output capacitance is too large. The overcurrent
charge the gate of the upper MOSFET. The VBOOT term is set point should guarantee the VID code transition
defined as the allowable droop in the rail of the upper drive. successful.
As an example, suppose an upper MOSFET has a gate RBIAS Current Reference
charge, QGATE , of 25nC at 5V and also assume the droop in The RBIAS pin is internally connected to a 1.545V reference
the drive voltage at the end of a PWM cycle is 200mV. One through a 3kΩ resistance. A bias current is established by
will find that a bootstrap capacitance of at least 0.125µF is connecting a±1% tolerance, 150kΩ resistor between the
required. The next larger standard value capacitance is RBIAS and VSS pins. This bias current is mirrored, creating the
0.15µF. A good quality ceramic capacitor is recommended. reference current I OCSET that is sourced from the OCSET pin.
Soft-Start and Soft Dynamic VID Slew Rates Do not connect any other components to this pin, as they will
have a negative impact on the performance of the IC.
The output voltage of the converter tracks VSOFT, the
voltage across the SOFT and VSS pins. Shown in Figure 1, Setting the PWM Switching Frequency
the SOFT pin is connected to the output of the VID DAC The R3 modulator scheme is not a fixed-frequency
through the unidirectional soft-start current source ISS or the architecture, lacking a fixed-frequency clock signal to
bidirectional soft-dynamic VID current source IDVID, and the produce PWM. The switching frequency increases during
non-inverting input of the error amplifier. Current is sourced the application of a load to improve transient performance.
from the SOFT pin when ISS is active. The SOFT pin can The static PWM frequency varies slightly depending on the
both source and sink current when IDVID is active. The input voltage, output voltage, and output current, but this
soft-start capacitor CSOFT changes voltage at a rate variation is normally less than 10% in continuous conduction
proportional to ISS or IDVID. The ISL6263C automatically mode.
selects ISS for the soft-start sequence so that the inrush
current through the output capacitors is maintained below Refer to Figure 2 and find that resistor R FSET is connected
the OCP threshold. Once soft-start has completed, IDVID is between the V W and COMP pins. A current is sourced from
automatically selected for output voltage changes VW through RFSET creating the synthetic ripple window
commanded by the VID inputs, charging CSOFT when the voltage signal V W, which determines the PWM switching
frequency. The relationship between the resistance of RFSET

13 FN6745.1
July 8, 2010
 ISL6263C

VDD

10µA  ROCSET
OCSET

OCP RS
ISP
 
ISENSE
ISN

ICOMP

+
VO

RIS2
VN VDCR

CN

RN

-

RIS1
FIGURE 8. EQUIVALENT MODEL OF CURRENT SENSE USING INDUCTOR DCR CURRENT SENSE

and the switching frequency in CCM is approximated using Sensing the time varying inductor current accurately
Equation 6: requires that the parallel R-C network time constant match
 t – 0.5  10 
–6 the inductor L/DCR time constant. Equation 10 shows this
R FSET = --------------------------------------- (EQ. 6)
– 12 relationship:
400  10
L  RN  T   RS 
t is the switching period. For example, the value of RFSET for ------------- =  -------------------------------  CN
DCR  R N  T  + R S
300kHz operation is approximated using Equation 7: (EQ. 10)
–6 –6 (EQ. 7)
3  3.33  10 – 0.5  10 
7.1 10 = -------------------------------------------------------------------- Solution of CN yields:
– 12
400  10
L 
 -------------
 DCR
This relationship only applies to operation in constant C N = ------------------------------------- (EQ. 11)
conduction mode because the PWM frequency naturally  RN  T   RS 
 -------------------------------
decreases as the load decreases while in diode emulation  R N  T  + R S
mode.
The first step is to adjust RN(T) and RS such that the correct
Inductor DCR Current Sense current information appears between the ISP and VO pins
ISL6263C provides the option of using the inductor DCR for even at light loads. Assume VN is the voltage drop across
current sense. To maintain the current sense accuracy, an RN(T). The VN to VDCR gain G1(T) provides a reasonable
NTC compensation network is optional when using DCR amount of light load signal from which to derive the current
sense. The process to compensate the DCR resistance information. G1(T) is given by Equation 12:
variation takes several iterative steps. Figure 2 shows the RN  T 
G 1  T  = -------------------------------
DCR sense method. Figure 8 shows the simplified model of RN  T  + RS (EQ. 12)
the current sense circuitry. The inductor DC current IO
generates a DC voltage drop on the inductor DCR. The gain of the current sense amplifier circuit is expressed in
Equation 8 gives this relationship: Equation 13:

V DCR = I O  DCR R IS2

(EQ. 8) K ISENSE = 1 + -------------
R IS1 (EQ. 13)
An R-C network senses the voltage across the inductor to
get the inductor current information. RN represents the The current sense amplifier output voltage is given by
equivalent resistance of RP and the optional NTC network Equation 14:
consisting of RNTC and RNTCS. RN is temperature T V ICOMP = V O + V N  K ISENSE (EQ. 14)
dependent and is given by Equation 9:
 R NTC + R NTCS   R P The inductor DCR is a function of temperature T and is
R N  T  = ------------------------------------------------------------
R NTC + R NTCS + R P (EQ. 9) approximated using Equation 15:
DCR  T  = DCR  +25C    1 + 0.00393  T –  +25C  
If the NTC network is not used, simply set RN(T) = RP. (EQ. 15)

14 FN6745.1
July 8, 2010
 ISL6263C

VDD

10µA  ROCSET
OCSET

OCP RS
ISP
 
ISENSE
ISN

ICOMP
 +
VO

RIS2
RP VRSNS

CN
 VN
- (OPTIONAL)

RIS1
FIGURE 9. EQUIVALENT MODEL OF CURRENT SENSE USING DISCRETE RESISTOR CURRENT SENSE

0.00393 is the temperature coefficient of the copper. To sense. It is recommended to start out using 100Ω for RS and
make VICOMP independent of the inductor temperature, the 47pF for CN. Since the current sense resistance changes
NTC characteristic is desired to satisfy: very little with temperature, the NTC network is not needed
G 1  T    1 + 0.00393  T –  +25C    G 1t arg et for thermal compensation. Discrete resistor sense design
(EQ. 16)
follows the same approach as DCR sense. The voltage on
where G1target is the desired ratio of VN / VDCR. Therefore, the current sense resistor is given by Equation 19:
the temperature characteristics G1, which determines V RSNS = I O  R SNS
(EQ. 19)
parameters selection, is described by Equation 17:
It is optional to parallel a resistor RP to form a voltage divider
G 1t arg et
G 1  T  = ------------------------------------------------------------------------- with RS to obtain more flexibility. Assume the voltage across
1 + 0.00393   T –  +25C   (EQ. 17)
RP is VN, which is given by Equation 20:
RP
It is recommended to begin the DCR current sense design V N = V RSNS  ----------------------
RS + R (EQ. 20)
using the RNTC, RNTCS, and RP component values of the P
evaluation board available from Intersil. The current sense amplifier output voltage VICOMP is given
Given the inductor DCR and the overcurrent set point IOC, the by Equation 21:
maximum voltage of ICOMP pin is determined by  R IS2
V ICOMP = V O + V   1 + -------------
Equation 18: N  R IS1 (EQ. 21)
R N  +25C   R IS2
V ICOMP  max  – V O = I OC  DCR  25C   ----------------------------------------------   1 + ------------- Given an current sense resistor RSNS and the overcurrent set
R N  +25C  + R S  R IS1
point IOC, the maximum voltage of ICOMP pin is determined
(EQ. 18) by Equation 22:
RP  R IS2
RN, RS, RIS1, RIS2 should be adjusted to meet the V ICOMP  max  – V O = I OC  R SNS  ----------------------   1 + ------------- (EQ. 22)
RS + RP  R IS1
requirement (VICOMP(max) - VO) > 25mV and the time
constant matching according to Equation 10. If RP is not used, the maximum voltage of ICOMP pin is
determined by Equation 23:
The effectiveness of the RN network is sensitive to the
 R IS2
coupling coefficient between the NTC thermistor and the V ICOMP  max  – V O = I OC  R SNS   1 + -------------
 R IS1 (EQ. 23)
inductor. The NTC thermistor should be placed in the closet
proximity of the inductor.
RS, RP, RIS1, RIS2 should be adjusted to meet the
Resistor Current Sense requirement (VICOMP(max) - VO) > 25mV.
Figure 3 shows a detailed schematic using discrete resistor The current sense traces should be routed directly to the
sense of the inductor current. Figure 9 shows the equivalent current sense resistor pads for accurate measurement.
circuit. Since the current sense resistor voltage represents However, due to layout imperfection, the calculated RIS2
the actual inductor current information, RS and CN simply may still need slight adjustment to achieve optimum load line
provide noise filtering. A low ESL sense resistor is strongly slope. It is recommended to adjust RIS2 after the system has
recommended for RSNS because this parameter is the most achieved thermal equilibrium at full load.
significant source of noise that affects discrete resistor

15 FN6745.1
July 8, 2010
 ISL6263C

Dynamic Mode of Operation - Compensation UGATE, BOOT, and PHASE

Parameters PHASE is the return path for the entire UGATE high-side
Intersil provides a spreadsheet to calculate the compensator MOSFET gate driver. The layout for these signals require
parameters. Caution needs to be used in choosing the input similar treatment, but to a greater extent, than those for
resistor to the FB pin. Excessively high resistance will cause LGATE, PVCC, and PGND. These signals swing from
an error to the output voltage regulation due to the bias approximately VIN to VSS and are more likely to couple into
current flowing through the FB pin. It is recommended to other signals.
keep this resistor below 3kΩ.
VSEN and RTN
Layout Considerations These traces should be laid out as noise sensitive. For
optimum load line regulation performance, the traces
As a general rule, power should be on the bottom layer of
connecting these two pins to the Kelvin sense leads of the
the PCB and weak analog or logic signals are on the top
processor should be laid out away from rapidly rising voltage
layer of the PCB. The ground-plane layer should be adjacent
nodes, (switching nodes) and other noisy traces. The filter
to the top layer to provide shielding.
capacitors CFILTER1, CFILTER2, and CFILTER3 used in
Inductor Current Sense and the NTC Placement conjunction with filter resistors RFILTER1 and RFILTER2 form
It is crucial that the inductor current be sensed directly at the common mode and differential mode filters, as shown in
PCB pads of the sense element, be it DCR sensed or discrete Figure 8. The noise environment of the application and
resistor sensed. The effect of the NTC on the inductor DCR actual board layout conditions will drive the extent of filter
thermal drift is directly proportional to its thermal coupling with complexity. The maximum recommended resistance for
the inductor and thus, the physical proximity to it. RFILTER1 and RFILTER2 is approximately 10Ω to avoid
interaction with the 50kΩ input resistance of the remote
Signal Ground and Power Ground sense differential amplifier. The physical location of these
The ground plane layer should have a single point connection resistors is not as critical as the filter capacitors. Typical
to the analog ground at the VSS pin. The VSS island should capacitance values for CFILTER1, CFILTER2, and CFILTER3
be located under the IC package along with the weak analog range between 330pF to 1000pF and should be placed near
traces and components. The paddle on the bottom of the the IC.
ISL6263C QFN package is not electrically connected to the
IC, however, it is recommended to make a good thermal RBIAS
connection to the VSS island using several vias. Connect the The resistor RRBIAS should be placed in close proximity to
input capacitors, the output capacitors, and the source of the the ISL6263C using a noise-free current return path to the
lower MOSFETs to the power ground plane. VSS pin.

LGATE, PVCC, and PGND IMON, SOFT, OCSET, V W, COMP, FB, VDIFF,
PGND is the return path for the pull-down of the LGATE ICOMP, ISP, ISN and VO
low-side MOSFET gate driver. Ideally, PGND should be The traces and components associated with these pins
connected to the source of the low-side MOSFET with a require close proximity to the IC as well as close proximity to
low-resistance, low-inductance path. The LGATE trace should each other. This section of the converter circuit needs to be
be routed in parallel with the trace from the PGND pin. These located above the island of analog ground with the
two traces should be short, wide, and away from other traces single-point connection to the VSS pin.
because of the high peak current and extremely fast dv/dt.
Resistor RS
PVCC should be decoupled to PGND with a ceramic capacitor
Resistor RS is preferably located near the boundary
physically located as close as practical to the IC pins.
between the power ground and the island of analog ground
GND
connected to the VSS pin.
VIAS TO
GROUND OUTPUT
PLANE CAPACITORS
VID<0:4>, AF_EN, PGOOD, and VR_ON
SCHOTTKY These are logic signals that do not require special attention.
VOUT DIODE
FDE
PHASE LOW-SIDE
INDUCTOR NODE
MOSFETS This logic signal should be treated as noise sensitive and
HIGH-SIDE should be routed away from rapidly rising voltage nodes,
MOSFETS INPUT (switching nodes) and other noisy traces.
VIN CAPACITORS
VIN
FIGURE 10. TYPICAL POWER COMPONENT PLACEMENT
The VIN signal should be connected near the drain of the
high-side MOSFET.

16 FN6745.1
July 8, 2010
 ISL6263C

Copper Size for the Phase Node

The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the high-side MOSFET and the source of the
low-side MOSFET to suppress turn-off voltage spikes.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
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17 FN6745.1
July 8, 2010
 ISL6263C

Package Outline Drawing

L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 02/07

4X 3.5
5.00 A 28X 0.50
6
B
25 32 PIN #1 INDEX AREA

6
PIN 1 24 1
INDEX AREA

5.00
3 .10 ± 0 . 15

17 8
(4X) 0.15
16 9
0.10 M C A B

+ 0.07
32X 0.40 ± 0.10 4 32X 0.23 - 0.05

TOP VIEW BOTTOM VIEW

SEE DETAIL "X"

0.10 C
0 . 90 ± 0.1 C
BASE PLANE
SEATING PLANE
0.08 C
( 4. 80 TYP )
( 28X 0 . 5 )
SIDE VIEW
( 3. 10 )

(32X 0 . 23 )

C 0 . 2 REF 5
( 32X 0 . 60)

0 . 00 MIN.
0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.

18 FN6745.1
July 8, 2010