INTEGRATED CIRCUITS

SCN68681
Dual asynchronous receiver/transmitter
(DUART)

Product specification 1998 Sep 04

Supersedes data of 1995 May 01
IC19 Data Handbook

 
   
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

DESCRIPTION • 16-bit programmable Counter/Timer

The Philips Semiconductors SCN68681 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is a single-chip • Parity, framing, and overrun error detection
MOS-LSI communications device that provides two independent • False start bit detection
full-duplex asynchronous receiver/transmitter channels in a single
package. It is compatible with other S68000 family devices, and can • Line break detection and generation
also interface easily with other microprocessors. The DUART can • Programmable channel mode
be used in polled or interrupt driven systems.
– Normal (full-duplex)
The operating mode and data format of each channel can be – Automatic echo
programmed independently. Additionally, each receiver and
– Local loopback
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16X clock derived from a programmable counter/timer, – Remote loopback
or an external 1X or 16X clock. The baud rate generator and • Multi-function programmable 16-bit counter/timer
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating • Multi-function 6-bit input port
speed of the receiver and transmitter make the DUART particularly – Can serve as clock or control inputs
attractive for dual-speed channel applications such as clustered – Change-of-state detection on four inputs
terminal systems.
– 100kΩ typical pull-up resistors
Each receiver is quadruply buffered to minimize the potential of
receiver overrun or to reduce interrupt overhead in interrupt driven
• Multi-function 8-bit output port
systems. In addition, a flow control capability is provided to disable – Individual bit set/reset capability
a remote DUART transmitter when the buffer of the receiving device – Outputs can be programmed to be status/interrupt signals
is full.
• Versatile interrupt system
Also provided on the SCN68681 are a multipurpose 6-bit input port – Single interrupt output with eight maskable interrupting
and a multipurpose 8-bit output port. These can be used as general conditions
purpose I/O ports or can be assigned specific functions (such as – Interrupt vector output on interrupt acknowledge
clock inputs or status/interrupt outputs) under program control.
– Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
FEATURES
• Maximum data transfer rates:
• S68000 bus compatible 1X - 1MB/sec, 16X - 125kB/sec
• Dual full-duplex asynchronous receiver/transmitter • Automatic wake-up mode for multidrop applications
• Quadruple buffered receiver data registers • Start-end break interrupt/status
• Programmable data format • Detects break which originates in the middle of a character
– 5 to 8 data bits plus parity
– Odd, even, no parity or force parity
• On-chip crystal oscillator
– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments • Single +5V power supply
• Programmable baud rate for each receiver and transmitter • Commercial and industrial temperature ranges available
selectable from: • DIP and PLCC packages
– 22 fixed rates: 50 to 115.2k baud
– Non-standard rates to 115.2kb
– Non-standard user-defined rate derived from programmable
counter/timer
– External 1X or 16X clock

ORDERING INFORMATION
COMMERCIAL INDUSTRIAL
DESCRIPTION VCC = +5V +5%, VCC = +5V +10%, DWG #
TA = 0°C to +70°C TA = 40°C to +85°C
40-Pin Ceramic Dual In-Line Package (cerdip) Not available SCN68681E1F40 0590B
40-Pin Plastic Dual In-Line Package (DIP) SCN68681C1N40 SCN68681E1N40 SOT129-1
44-Pin Plastic Leaded Chip Carrier (PLCC) SCN68681C1A44 SCN68681E1A44 SOT187-2

1998 Sep 04 2 853–1083 19970

Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

PIN CONFIGURATIONS

A1 1 40 VCC

IP3 2 39 IP4
6 1 40
A2 3 38 IP5
7 39
IP1 4 37 IACKN

A3 5 36 IP2
PLCC
A4 6 35 CSN

IP0 7 34 RESETN

R/WN 8 33 X2 17 29

DTACKN 9 32 X1/CLK 18 28

RxDB 10 31 RxDA PIN/FUNCTION

DIP
TxDB 11 30 TxDA 1 NC 16 OP5 31 OP2
2 A1 17 OP7 32 OP0
OP1 12 29 OP0 3 IP3 18 D1 33 TxDA
4 A2 19 D3 34 NC
5 IP1 20 D5 35 RxDA
OP3 13 28 OP2
6 A3 21 D7 36 X1/CLK
7 A4 22 GND 37 X2
OP5 14 27 OP4 8 IP0 23 NC 38 RESETN
9 R/WN 24 INTRN 39 CSN
OP7 15 26 OP6 10 DTACKN 25 D6 40 IP2
11 RxDB 26 D4 41 IACKN
D1 16 25 D0 12 NC 27 D2 42 IP5
13 TxDB 28 D0 43 IP4
D3 17 24 D2
14 OP1 29 OP6 44 VCC
15 OP3 30 OP4
D5 18 23 D4

D7 19 22 D6

GND 20 21 INTRN

SD00107

Figure 1. Pin Configurations

ABSOLUTE MAXIMUM RATINGS1

SYMBOL PARAMETER RATING UNIT
TA Operating ambient temperature range2 See Note 4 °C
TSTG Storage temperature range -65 to +150 °C
All voltages with respect to ground3 -0.5 to +6.0 V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150oC maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC
supply range.

1998 Sep 04 3
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

BLOCK DIAGRAM

8 CHANNEL A
D0–D7 BUS BUFFER
TRANSMIT TxDA
HOLDING REG

TRANSMIT
SHIFT REGISTER

R/WN OPERATION CONTROL

RECEIVE
DTACKN ADDRESS HOLDING REG (3)
CSN DECODE RxDA
4 RECEIVE
A1–A4 SHIFT REGISTER
R/W CONTROL
RESETN
MR1, 2
CRA
SRA

INTERRUPT CONTROL
INTRN TxDB
IMR CHANNEL B
ISR (AS ABOVE)
IACKN RxDB
IVR
INTERNAL DATABUS

INPUT PORT
CONTROL

CHANGE OF
TIMING

TIMING STATE
DETECTORS (4) 6
IP0-IP5
BAUD RATE
GENERATOR IPCR
ACR

CLOCK
SELECTORS

COUNTER/ OUTPUT PORT

TIMER
FUNCTION 8
SELECT LOGIC OP0-OP7
X1/CLK
XTAL OSC
X2 OPCR
OPR
CSRA
CSRB
ACR
U
CTLR
CTLR VCC

GND

SD00108

Figure 2. Block Diagram

1998 Sep 04 4
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

PIN DESCRIPTION
SYMBOL TYPE NAME AND FUNCTION
D0-D7 I/O Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the DUART and the
CPU. D0 is the least significant bit.
CSN I Chip Select: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on
D0-D7 as controlled by the R/WN, RDN and A1-A4 inputs. When High, places the D0-D7 lines in the 3-State condition.
R/WN I Read/Write: A High input indicates a read cycle and a Low input indicates a write cycle, when a cycle is initiated by
assertion of the CSN input.
A1-A4 I Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESETN I Reset: A Low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex 0F, puts
OP0-OP7 in the High state, stops the counter/timer, and puts Channel A and B in the inactive state, with the TxDA
and TxDB outputs in the mark (High) state. Clears Test modes, sets MR pointer to MR1.
DTACKN O Data Transfer Acknowledge: Three-state active Low output asserted in write, read, or interrupt cycles to indicate
proper transfer of data between the CPU and the DUART.
INTRN O Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable
interrupting conditions are true.
IACKN I Interrupt Acknowledge: Active-Low input indicating an interrupt acknowledge cycle. In response, the DUART will
place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending.
X1/CLK I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally
3.6864 MHz) must be supplied at all times. For crystal connections see Figure 9, Clock Timing.
X2 I Crystal 2: Crystal connection. See Figure 9. If a crystal is not used it is best to keep this pin not connected although
it is permissible to ground it.
RxDA I Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.
RxDB I Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.
TxDA O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the
“mark” condition when the transmitter is disabled, idle or when operating in local loopback mode. “Mark” is High,
“space” is Low.
TxDB O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the
‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is High,
‘space’ is Low.
OP0 O Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be deactivated
automatically on receive or transmit.
OP1 O Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can be deactivated
automatically on receive or transmit.
OP2 O Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver 1X clock
output.
OP3 O Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B transmitter 1X clock
output, or Channel B receiver 1X clock output.
OP4 O Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYA/FFULLA output.
OP5 O Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYB/FFULLB output.
OP6 O Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYA output.
OP7 O Output 7: General purpose output, or Channel B open-drain, active-Low, TxRDYB output.
IP0 I Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an internal VCC
pull-up device supplying 1 to 4
A of current.
IP1 I Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an internal VCC
pull-up device supplying 1 to 4
A of current.
IP2 I Input 2: General purpose input, or Channel B receiver external clock input (RxCB), or counter/timer external clock
input. When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock.
Pin has an internal VCC pull-up device supplying 1 to 4
A of current.
IP3 I Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external clock is
used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC
pull-up device supplying 1 to 4
A of current.
IP4 I Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used
by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device
supplying 1 to 4
A of current.
IP5 I Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is
used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC
pull-up device supplying 1 to 4
A of current.
VCC I Power Supply: +5V supply input.
GND I Ground:

1998 Sep 04 5
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

DC ELECTRICAL CHARACTERISTICS TA = -40°C to +85°C, VCC = 5.0V ± 10%1, 2, 3

LIMITS
SYMBOL PARAMETER TEST CONDITIONS UNIT
Min Typ Max
VIL Input low voltage 0.8
VIH Input high voltage (except X1/CLK)5 2
V
VIH Input high voltage (except X1/CLK)4 2.5
VIH Input high voltage (X1/CLK) 4
VOL Output low voltage IOL = 2.4mA 0.4
VOH Output high voltage (except o.d. outputs)5 IOH = -400µA 2.4 V
VOH Output high voltage (except o.d. outputs)4 IOH = -400µA 2.9
IIL Input leakage current VIN = 0 to VCC –10 10
µA
ILL Data bus 3-State leakage current VO = 0.4 to VCC –10 10
IX1L X1/CLK low input current VIN = 0, X2 grounded -4 -2 0 mA
VIN = 0, X2 floated -3 -1.5 0 mA
IX1H X1/CLK high input current VIN = VCC, X2 grounded -1 0.2 1 mA
VIN = VCC, X2 floated 0 3.5 10 mA
IX2L X2 low input current VIN = 0, X1/CLK floated -100 -30 0 µA
IX2H X2 high input current VIN = VCC, X1/CLK floated 0 +30 100 µA
IOC Open-collector output leakage current 10 µA
ICC Power supply current
VO = 0.4 to VCC –10
0°C to +70°C version 150 mA
-40°C to +85°C version 175 mA
NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages
of 0.8V and 2.0V as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. TA < 0°C
5. TA > 0°C

1998 Sep 04 6
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

AC CHARACTERISTICS TA = -40°C to +85°C, VCC = 5.0V ± 10% 1, 2, 3, 4

LIMITS
SYMBOL PARAMETER UNIT
Min Typ3 Max
Reset Timing (See Figure 3)
tRES RESETN pulse width 200 ns
Bus Timing (See Figures 4, 5, 6)
tAS A1-A4 setup time to CSN Low 10 ns
tAH A1-A4 hold time from CSN Low 100 ns
tRWS RWN setup time to CSN High 0 ns
tRWH RWN holdup time to CSN High 0 ns
tCSW CSN High pulse width 90 ns
tCSD5 CSN or IACKN High from DTACKN Low 20 ns
tDD Data valid from CSN or IACKN Low 175 ns
tDF Data bus floating from CSN or IACKN High7 100 ns
tDS Data setup time to CLK High 100 ns
tDH Data hold time from CSN High 20 ns
tDAL DTACKN Low from read data valid 0 ns
tDCR DTACKN Low (read cycle) from CLK High 125 ns
tDCW DTACKN Low (write cycle) from CLK High 125 ns
tDAH DTACKN High from CSN or IACKN High 100 ns
tDAT DTACKN High impedance from CSN or IACKN High 125 ns
tCSC 6 CSN or IACKN setup time to clock High 90 ns
Port Timing (See Figure 7)
tPS Port input setup time to CSN Low 0 ns
tPH Port input hold time from CSN High 0 ns
tPD Port output valid from CSN High 400 ns
Interrupt Reset Timing (See Figure 8)
INTRN or OP3-OP7 when used as interrupts negated from:
Read RHR (RxRDY/FFULL interrupt) 300 ns
Write THR (TxRDY interrupt) 300 ns
tIR Reset command (delta break interrupt) 300 ns
Stop C/T command (counter interrupt) 300 ns
Read IPCR (input port change interrupt) 300 ns
Write IMR (clear of interrupt mask bit) 300 ns
Clock Timing (See Figure 9)
tCLK X1/CLK High or Low time 100 ns
fCLK8 X1/CLK frequency 0 3.6864 4.0 MHz
tCTC CTCLK High or Low time 100 ns
fCTC CTCLK frequency 0 4.0 MHz
tRX RxC High or Low time 220 ns
fRX RxC frequency (16X) 0 2.0 MHz
(1X) 0 1.0 MHz
tTX TxC High or Low time 220 ns
fTX TxC frequency (16X) 0 2.0 MHz
(1X) 0 1.0 MHz
Transmitter Timing (See Figure 10)
tTXD TxD output delay from TxC external clock input on IP pin 350 ns
tTCS Output delay from TxC low at OP pin to TxD data output 150 ns
Receiver Timing (See Figure 11)
tRXS RxD data setup time before RxC high at external clock input on IP pin 240 ns
tRXH RxD data hold time after RxC high at external clock input on IP pin 200 ns
NOTES:
1. Parameters are valid over specified temp. range. See Ordering information table for applicable operating temp. and VCC supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with
a transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input
voltages of 0.8V and 2.0V as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test condition for interrupt outputs: CL = 50pF, RL = 2.7kΩ to VCC.
5. This specification will impose maximum 68000 CPU CLK to 6MHz. Higher CPU CLK can be used if repeating bus reads are not performed.
Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
6. This specification imposes a lower bound on CSN and IACKN Low, guaranteeing that it will be Low for at least 1 CLK period. This
requirement is made on CSN only to insure assertion of DTACKN and not to guarantee operation of the part.
7. This spec is made only to insure that DTACKN is asserted with respect to the rising edge of the X1/CLK pin as shown in the timing diagram,
not to guarantee operation of the part. If setup time is violated, DTACKN may be asserted as shown, or may be asserted 1 clock cycle later.
8. Operation to 0MHz is assured by design. Minimum test frequency is 2.0MHz.

1998 Sep 04 7
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

BLOCK DIAGRAM • In the timer mode it generates a square wave.

The SCN68681 DUART consists of the following eight major
sections: data bus buffer, operation control, interrupt control, timing, • In the counter mode it generates a time delay.
communications Channels A and B, input port and output port. • In the time out mode it monitors the receiver data flow and signals
Refer to the Block Diagram. data flow has paused. In the time out mode the receiver controls
Data Bus Buffer the starting/stopping of the C/T.
The data bus buffer provides the interface between the external and
The counter operates as a down counter and sets its output bit in
internal data buses. It is controlled by the operation control block to
the ISR (Interrupt Status Register) each time it passes through 0.
allow read and write operations to take place between the controlling
The output of the counter/timer may be seen on one of the OP pins
CPU and the DUART.
or as an Rx or Tx clock.
Operation Control
The Timer/Counter is controlled with six (6) “commands”; Start C/T,
The operation control logic receives operation commands from the
Stop C/T, write C/T, preset registers, read C/T value, set or reset
CPU and generates appropriate signals to internal sections to
time out mode.
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via Please see the detail of the commands under the Counter/Timer
the data bus buffer. The DTACKN output is asserted during write register descriptions.
and read cycles to indicate to the CPU that data has been latched
Communications Channels A and B
on a write cycle, or that valid data is present on the bus on a read
Each communications channel of the SCN68681 comprises a
cycle.
full-duplex asynchronous receiver/transmitter (DUART). The
Interrupt Control operating frequency for each receiver and transmitter can be
A single active-Low interrupt output (INTRN) is provided which is selected independently from the baud rate generator, the counter
activated upon the occurrence of any of eight internal events. timer, or from an external input.
Associated with the interrupt system are the Interrupt Mask Register
The transmitter accepts parallel data from the CPU, converts it to a
(IMR) and the Interrupt Status Register (ISR), the Auditory Control
serial bit stream, inserts the appropriate start, stop, and optional
Register(ACR) and the Interrupt Vector Register (IVR). The IMR
parity bits and outputs a composite serial stream of data on the TxD
may be programmed to select only certain conditions to cause
output pin. The receiver accepts serial data on the RxD pin,
INTRN to be asserted. The ISR can be read by the CPU to
converts this serial input to parallel format, checks for start bit, stop
determine all currently active interrupting conditions. When IACKN
bit, parity bit (if any), or break condition and sends an assembled
is asserted, and the DUART has an interrupt pending, the DUART
character to the CPU.
responds by placing the contents of the IVR register on the data bus
and asserting DTACKN. The input port pulse detection circuitry uses a 38.4kHz sampling
clock derived from one of the baud rate generator taps. This results
Outputs OP3-OP7 can be programmed to provide discrete interrupt
in a sampling period of slightly more than 25µs (assuming that the
outputs for the transmitter, receivers, and counter/timer.
clock input is 3.6864MHz). The detection circuitry, in order to
Timing Circuits guarantee a true change in level has occurred, requires that two
The timing block consists of a crystal oscillator, a baud rate successive samples at the new logic level be observed. As a
generator, a programmable 16-bit counter/timer, and four clock consequence, the minimum duration of the signal change is 25µs if
selectors. The crystal oscillator operates directly from a crystal the transition occurs coincident with the first sample pulse. The
connected across the X1/CLK and X2 inputs. If an external clock of 50µs time refers to the situation in which the change of state is just
the appropriate frequency is available, it may be connected to missed and the first change of state is not detected until 25µs later.
X1/CLK. The clock serves as the basic timing reference for the
Input Port
Baud Rate Generator (BRG), the counter/timer, and other internal
The inputs to this unlatched 6-bit port can be read by the CPU by
circuits. A clock signal within the limits specified in the
performing a read operation at address H‘D’. A High input results in
specifications section of this data sheet must always be supplied to
a logic 1 while a Low input results in a logic 0. D7 will always read
the DUART. If an external is used instead of a crystal, X1 should be
as a logic 1 and D6 will reflect the level of IACKN. The pins of this
driven using a configuration similar to the one in Figure 9.
port can also serve as auxiliary inputs to certain portions of the
The baud rate generator operates from the oscillator or external DUART logic.
clock input and is capable of generating 18 commonly used data
Four change-of-state detectors are provided which are associated
communications baud rates ranging from 50 to 38.4k baud. The
with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High
clock outputs from the BRG are at 16X the actual baud rate. The
transition of these inputs, lasting longer than 25 - 50µs, will set the
counter/timer can be used as a timer to produce a 16X clock for any
corresponding bit in the input port change register. The bits are
other baud rate by counting down the crystal clock or an external
cleared when the register is read by the CPU. Any change-of-state
clock. The four clock selectors allow the independent selection, for
can also be programmed to generate an interrupt to the CPU.
each receiver and transmitter, of any of these baud rates or external
timing signal. All the IP pins have a small pull-up device that will source 1 to 4
A
of current from VCC. These pins do not require pull-up devices or
Counter/Timer (C/T) VCC connections if they are not used.
The counter timer is a 16 bit programmable divider that operates
one of three modes: Counter, Timer or Time Out mode. In all three
Output Port
The 8-bit multipurpose output port can be used as a general
modes it uses the 16-bit value loaded to the CTUR and CTLR
purpose output port, in which case the outputs are the complements
registers. (Counter timer upper and lower preset registers).

1998 Sep 04 8
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

of the Output Port Register (OPR). OPR[n] = 1 results in clock for 7-1/2 clocks (16X clock mode) or at the next rising edge of
OP[n] = Low and vice versa. Bits of the OPR can be individually set the bit time clock (1X clock mode). If RxD is sampled High, the start
and reset. A bit is set by performing a write operation at address bit is invalid and the search for a valid start bit begins again. If RxD
H’E’ with the accompanying data specifying the bits to be reset (1 = is still Low, a valid start bit is assumed and the receiver continues to
set, 0 = no change). Likewise, a bit is reset by a write at address sample the input at one bit time intervals at the theoretical center of
H’F’ with the accompanying data specifying the bits to be reset (1 = the bit, until the proper number of data bits and parity bit (if any)
reset, 0 = no change). have been assembled, and one stop bit has been detected. The
least significant bit is received first. The data is then transferred to
Outputs can be also individually assigned specific functions by
the Receive Holding Register (RHR) and the RxRDY bit in the SR is
appropriate programming of the Channel A mode registers (MR1A,
set to a 1. This condition can be programmed to generate an
MR2A), the Channel B mode registers (MR1B, MR2B), and the
interrupt at OP4 or OP5 and INTRN. If the character length is less
Output Port Configuration Register (OPCR).
than 8 bits, the most significant unused bits in the RHR are set to
Please note that these pins drive both high and low. HOWEVER zero.
when they are programmed to represent interrupt type functions
After the stop bit is detected, the receiver will immediately look for
(such as receiver ready, transmitter ready or counter/timer ready)
the next start bit. However, if a non-zero character was received
they will be switched to an open drain configuration in which case an
without a stop bit (framing error) and RxD remains Low for one half
external pull-up device would be required.
of the bit period after the stop bit was sampled, then the receiver
operates as if a new start bit transition had been detected at that
OPERATION point (one-half bit time after the stop bit was sampled).
Transmitter The parity error, framing error, and overrun error (if any) are strobed
The SCN68681 is conditioned to transmit data when the transmitter into the SR at the received character boundary, before the RxRDY
is enabled through the command register. The SCN68681 indicates status bit is set. If a break condition is detected (RxD is Low for the
to the CPU that it is ready to accept a character by setting the entire character including the stop bit), a character consisting of all
TxRDY bit in the status register. This condition can be programmed zeros will be loaded into the RHR and the received break bit in the
to generate an interrupt request at OP6 or OP7 and INTRN. When SR is set to 1. The RxD input must return to high for two (2) clock
a character is loaded into the Transmit Holding Register (THR), the edges of the X1 crystal clock for the receiver to recognize the end of
above conditions are negated. Data is transferred from the holding the break condition and begin the search for a start bit. This will
register to transmit shift register when it is idle or has completed usually require a high time of one X1 clock period or 3 X1
transmission of the previous character. The TxRDY conditions are edges since the clock of the controller is not synchronous to
then asserted again which means one full character time of buffering the X1 clock.
is provided. Characters cannot be loaded into the THR while the
transmitter is disabled. Receiver FIFO
The RHR consists of a First-In-First-Out (FIFO) stack with a
The transmitter converts the parallel data from the CPU to a serial
capacity of three characters. Data is loaded from the receive shift
bit stream on the TxD output pin. It automatically sends a start bit
register into the topmost empty position of the FIFO. The RxRDY bit
followed by the programmed number of data bits, an optional parity
in the status register is set whenever one or more characters are
bit, and the programmed number of stop bits. The least significant
available to be read, and a FFULL status bit is set if all three stack
bit is sent first. Following the transmission of the stop bits, if a new
positions are filled with data. Either of these bits can be selected to
character is not available in the THR, the TxD output remains High
cause an interrupt. A read of the RHR outputs the data at the top of
and the TxEMT bit in the Status Register (SR) will be set to 1.
the FIFO. After the read cycle, the data FIFO and its associated
Transmission resumes and the TxEMT bit is cleared when the CPU
status bits (see below) are ‘popped’ thus emptying a FIFO position
loads a new character into the THR. If the transmitter is disabled, it
for new data.
continues operating until the character currently being transmitted is
completely sent out. The transmitter can be forced to send a Receiver Status Bits
continuous Low condition by issuing a send break command.
In addition to the data word, three status bits (parity error, framing
The transmitter can be reset through a software command. If it is error, and received break) are also appended to each data character
reset, operation ceases immediately and the transmitter must be in the FIFO (overrun is not). Status can be provided in two ways, as
enabled through the command register before resuming operation. programmed by the error mode control bit in the mode register. In
If CTS operation is enable, the CTSN input must be Low in order for the ‘character’ mode, status is provided on a character-by-character
the character to be transmitted. If it goes High in the middle of a basis; the status applies only to the character at the top of the FIFO.
transmission, the character in the shift register is transmitted and In the ‘block’ mode, the status provided in the SR for these three bits
TxDA then remains in the marking state until CTSN goes Low. The is the logical-OR of the status for all characters coming to the top of
transmitter can also control the deactivation of the RTSN output. If the FIFO since the last ‘reset error’ command was issued. In either
programmed, the RTSN output will be reset one bit time after the mode reading the SR does not affect the FIFO. The FIFO is
character in the transmit shift register and transmit holding register ‘popped’ only when the RHR is read. Therefore the status register
(if any) are completely transmitted, if the transmitter has been should be read prior to reading the FIFO.
disabled.
If the FIFO is full when a new character is received, that character is
Receiver held in the receive shift register until a FIFO position is available. If
The SCN68681 is conditioned to receive data when enabled through an additional character is received while this state exits, the
the command register. The receiver looks for a High-to-Low contents of the FIFO are not affected; the character previously in the
(mark-to-space) transition of the start bit on the RxD input pin. If a shift register is lost and the overrun error status bit (SR[4]) will be
transition is detected, the state of the RxD pin is sampled each 16X set-upon receipt of the start bit of the new (overrunning) character).

1998 Sep 04 9
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

The receiver can control the deactivation of RTS. If programmed to CPU should program the mode register prior to loading the
operate in this mode, the RTSN output will be negated when a valid corresponding data bits into the THR.
start bit was received and the FIFO is full. When a FIFO position In this mode, the receiver continuously looks at the received data
becomes available, the RTSN output will be re-asserted stream, whether it is enabled or disabled. If disabled, it sets the
automatically. This feature can be used to prevent an overrun, in RxRDY status bit and loads the character into the RHR FIFO if the
the receiver, by connecting the RTSN output to the CTSN input of received A/D bit is a one (address tag), but discards the received
the transmitting device. character if the received A/D bit is a zero (data tag). If enabled, all
Receiver Reset and Disable received characters are transferred to the CPU via the RHR. In
Receiver disable stops the receiver immediately – data being either case, the data bits are loaded into the data FIFO while the
assembled if the receiver shift register is lost. Data and status in the A/D bit is loaded into the status FIFO position normally used for
FIFO is preserved and may be read. A re-enable of the receiver after parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
a disable will cause the receiver to begin assembling characters at the break detect operate normally whether or not the receive is enabled.
next start bit detected. A receiver reset will discard the present shift
register data, reset the receiver ready bit (RxRDY), clear the status of PROGRAMMING
the byte at the top of the FIFO and re-align the FIFO read/write The operation of the DUART is programmed by writing control words
pointers. This has the appearance of “clearing or flushing” the into the appropriate registers. Operational feedback is provided via
receiver FIFO. In fact, the FIFO is NEVER cleared! The data in the status registers which can be read by the CPU. The addressing of
FIFO remains valid until overwritten by another received character. the registers is described in Table 1.
Because of this, erroneous reading or extra reads of the receiver The contents of certain control registers are initialized to zero on
FIFO will miss-align the FIFO pointers and result in the reading of RESET. Care should be exercised if the contents of a register are
previously read data. A receiver reset will re-align the pointers. changed during operation, since certain changes may cause
Multidrop Mode operational problems.
The DUART is equipped with a wake up mode for multidrop For example, changing the number of bits per character while the
applications. This mode is selected by programming bits MR1A[4:3] or transmitter is active may cause the transmission of an incorrect
MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this mode of character. In general, the contents of the MR, the CSR, and the
operation, a ‘master’ station transmits an address character followed by OPCR should only be changed while the receiver(s) and
data characters for the addressed ‘slave’ station. The slave stations, transmitter(s) are not enabled, and certain changes to the ACR
with receivers that are normally disabled, examine the received data should only be made while the C/T is stopped.
stream and ‘wake up’ the CPU (by setting RxRDY) only upon receipt of
Mode registers 1 and 2 of each channel are accessed via
an address character. The CPU compares the received address to its
independent auxiliary pointers. The pointer is set to MR1x by RESET
station address and enables the receiver if it wishes to receive the
or by issuing a ‘reset pointer’ command via the corresponding
subsequent data characters. Upon receipt of another address character,
command register. Any read or write of the mode register while the
the CPU may disable the receiver to initiate the process again.
pointer is at MR1x, switches the pointer to MR2x. The pointer then
A transmitted character consists of a start bit, the programmed remains at MR2x, so that subsequent accesses are always to MR2x
number of data bits, and Address/Data (A/D) bit, and the unless the pointer is reset to MR1x as described above.
programmed number of stop bits. The polarity of the transmitted
Mode, command, clock select, and status registers are duplicated
A/D bit is selected by the CPU by programming bit
for each channel to provide total independent operation and control.
MR1A[2]/MR1B[2]. MR1A[2]/MR1B[2] = 0 transmits a zero in the
Refer to Table 2 for register bit descriptions. The reserved
A/D bit position, which identifies the corresponding data bits as data
registers at addresses H‘02’ and H‘OA’ should never be read during
while MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position,
normal operation since they are reserved for internal diagnostics.
which identifies the corresponding data bits as an address. The

Table 1. SCN68681 Register Addressing

A4 A3 A2 A1 READ (R/WN = 1) WRITE (R/WN = 0)
0 0 0 0 Mode Register A (MR1A, MR2A) Mode Register A (MR1A, MR2A)
0 0 0 1 Status Register A (SRA) Clock Select Register A (CSRA)
0 0 1 0 BRG Test Command Register A (CRA)
0 0 1 1 Rx Holding Register A (RHRA) Tx Holding Register A (THRA)
0 1 0 0 Input Port Change Register (IPCR) Aux. Control Register (ACR)
0 1 0 1 Interrupt Status Register (ISR) Interrupt Mask Register (IMR)
0 1 1 0 Counter/Timer Upper Value (CTU) C/T Upper Preset Value (CRUR)
0 1 1 1 Counter/Timer Lower Value (CTL) C/T Lower Preset Value (CTLR)
1 0 0 0 Mode Register B (MR1B, MR2B) Mode Register B (MR1B, MR2B)
1 0 0 1 Status Register B (SRB) Clock Select Register B (CSRB)
1 0 1 0 1X/16X Test Command Register B (CRB)
1 0 1 1 Rx Holding Register B (RHRB) Tx Holding Register B (THRB)
1 1 0 0 Interrupt Vector Register (IVR) Interrupt Vector Register (IVR)
1 1 0 1 Input Ports IP0 to IP6 Output Port Conf. Register (OPCR)
1 1 1 0 Start Counter Command Set Output Port Bits Command
1 1 1 1 Stop Counter Command Reset Output Port Bits Command
* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication

1998 Sep 04 10
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

Table 2. Register Bit Formats

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RxRTS RxINT ERROR PARITY BITS PER
PARITY MODE
CONTROL SELECT MODE* TYPE CHARACTER
MR1A
MR1B 00 = With Parity 00 = 5
0 = No 0 = RxRDY 0 = Char 01 = Force Parity 0 = Even 01 = 6
1 = Yes 1 = FFULL 1 = Block 10 = No Parity 1 = Odd 10 = 7
11 = Multidrop Mode 11 = 8
NOTE:
*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

TxRTS CTS
CHANNEL MODE STOP BIT LENGTH*
CONTROL ENABLE Tx
MR2A
MR2B 00 = Normal 0 = 0.563 4 = 0.813 8 = 1.563 C = 1.813
01 = Auto-Echo 0 = No 0 = No 1 = 0.625 5 = 0.875 9 = 1.625 D = 1.875
10 = Local loop 1 = Yes 1 = Yes 2 = 0.688 6 = 0.938 A = 1.688 E = 1.938
11 = Remote loop 3 = 0.750 7 = 1.000 B = 1.750 F = 2.000
NOTE:
*Add 0.5 to values shown for 0 - 7 if channel is programmed for 5 bits/char.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CSRA RECEIVER CLOCK SELECT TRANSMITTER CLOCK SELECT
CSRB
See Text See Text
NOTE:
* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CRA MISCELLANEOUS COMMANDS DISABLE Tx ENABLE Tx DISABLE Rx ENABLE Rx
CRB Not used – See Text 0 = No 0 = No 0 = No 0 = No
should be 0 1 = Yes 1 = Yes 1 = Yes 1 = Yes
NOTE:
*Access to the upper four bits of the command register should be separated by three (3) edges of the X1 clock. A disabled transmitter cannot
be loaded.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

RECEIVED FRAMING PARITY OVERRUN
SRA TxEMT TxRDY FFULL RxRDY
BREAK* ERROR* ERROR* ERROR
SRB
0 = No 0 = No 0 = No 0 = No 0 = No 0 = No 0 = No 0 = No
1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes
NOTE:
*These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from the
top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are discarded when
the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using the error reset
command (command 4x) or a receiver reset.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OP7 OP6 OP5 OP4 OP3 OP2
OPCR 00 = OPR[3] 00 = OPR[2]
0 = OPR[5] 0 = OPR[4]
0 = OPR[7] 0 = OPR[6] 01 = C/T OUTPUT 01 = TxCA(16x)
1 = RxRDY/ 1 = RxRDY/
1 = TxRDYB 1 = TxRDYA 10 = TxCB(1x) 10 = TxCA(1x)
FFULLB FFULLA
11 = RxCB(1x) 11 = RxCA(1x)

OPR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OPR bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
OP pin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
NOTE:
The level at the OP pin is the inverse of the bit in the OPR register.

1998 Sep 04 11
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

Table 2. Register Bit Formats (Continued)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

BRG SET COUNTER/TIMER DELTA DELTA DELTA DELTA
ACR SELECT MODE AND SOURCE IP3 INT IP2 INT IP1 INT IP0 INT
0 = set 1 0 = Off 0 = Off 0 = Off 0 = Off
See Table 4
1 = set 2 1 = On 1 = On 1 = On 1 = On

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

DELTA DELTA DELTA DELTA
IP3 IP2 IP1 IP0
IPCR IP3 IP2 IP1 IP0
0 = No 0 = No 0 = No 0 = No 0 = Low 0 = Low 0 = Low 0 = Low
1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = High 1 = High 1 = High 1 = High

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

INPUT
DELTA RxRDY/ COUNTER DELTA RxRDY/
PORT TxRDYB TxRDYA
ISR BREAK B FFULLB READY BREAK A FFULLA
CHANGE
0 = No 0 = No 0 = No 0 = No 0 = No 0 = No 0 = No 0 = No
1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes 1 = Yes

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

IN. PORT DELTA RxRDY/ COUNTER DELTA RxRDY/
TxRDYB TxRDYA
CHANGE BREAK B FFULLB READY BREAK A FFULLA
IMR INT INT
INT INT INT INT INT INT
0 = Off 0 = Off 0 = Off 0 = Off 0 = Off 0 = Off 0 = Off 0 = Off
1 = On 1 = On 1 = On 1 = On 1 = On 1 = On 1 = On 1 = On

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CTUR C/T[15] C/T[14] C/T[13] C/T[12] C/T[11] C/T[10] C/T[9] C/T[8]

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CTLR C/T[7] C/T[6] C/T[5] C/T[4] C/T[3] C/T[2] C/T[1] C/T[0]

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

IVR IVR[7] IVR[6] IVR[5] IVR[4] IVR[3] IVR[2] IVR[1] IVR[0]

MR1A – Channel A Mode Register 1 MR1A[5] – Channel A Error Mode Select

MR1A is accessed when the Channel A MR pointer points to MR1. This bit select the operating mode of the three FIFOed status bits
The pointer is set to MR1 by RESET or by a ‘set pointer’ command (FE, PE, received break) for Channel A. In the ‘character’ mode,
applied via CRA. After reading or writing MR1A, the pointer will status is provided on a character-by-character basis; the status
point to MR2A. applies only to the character at the top of the FIFO. In the ‘block”
mode, the status provided in the SR for these bits is the
MR1A[7] – Channel A Receiver Request-to-Send Control accumulation (logical-OR) of the status for all characters coming to
This bit controls the deactivation of the RTSAN output (OP0) by the the top of the FIFO since the last ‘reset error’ command for Channel
receiver. This output is normally asserted by setting OPR[0] and A was issued.
negated by resetting OPR[0]. MR1A[7] = 1 causes RTSAN to be
negated upon receipt of a valid start bit if the Channel A FIFO is full. MR1A[4:3| – Channel A Parity Mode Select
However, OPR[0] is not reset and RTSAN will be asserted again If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
when an empty FIFO position is available. This feature can be used transmitted character and the receiver performs a parity check on
for flow control to prevent overrun in the receiver by using the incoming data MR1A[4:3] = 11 selects Channel A to operate in the
RTSAN output signal to control the CTSN input of the transmitting special multidrop mode described in the Operation section.
device.
MR1A[2] – Channel A Parity Type Select
MR1A[6] – Channel A Receiver Interrupt Select This bit selects the parity type (odd or even) if the ‘with parity’ mode
This bit selects either the Channel A receiver ready status (RxRDY) is programmed by MR1A[4:3], and the polarity of the forced parity bit
or the Channel A FIFO full status (FFULL) to be used for CPU if the ‘force parity’ mode is programmed. It has no effect if the ‘no
interrupts. It also causes the selected bit to be output on OP4 if it is parity’ mode is programmed. In the special multidrop mode it
programmed as an interrupt output via the OPCR. selects the polarity of the A/D bit.

1998 Sep 04 12
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

MR1A[1:0] – Channel A Bits Per Character Select The user must exercise care when switching into and out of the
This field selects the number of data bits per character to be various modes. The selected mode will be activated immediately
transmitted and received. The character length does not include the upon mode selection, even if this occurs in the middle of a received
start, parity, and stop bits. or transmitted character. Likewise, if a mode is deselected the
device will switch out of the mode immediately. An exception to this
MR2A – Channel A Mode Register 2
is switching out of autoecho or remote loopback modes: if the
MR2A is accessed when the Channel A MR pointer points to MR2,
de-selection occurs just after the receiver has sampled the stop bit
which occurs after any access to MR1A. Accesses to MR2A do not
(indicated in autoecho by assertion of RxRDY), and the transmitter
change the pointer.
is enabled, the transmitter will remain in autoecho mode until the
MR2A[7:6] – Channel A Mode Select entire stop has been re-transmitted.
Each channel of the DUART can operate in one of four modes.
MR2A[5] – Channel A Transmitter Request-to-Send Control
MR2A[7:6] = 00 is the normal mode, with the transmitter and
CAUTION: When the transmitter controls the OP pin (usually used
receiver operating independently. MR2A[7:6] = 01 places the
for the RTSN signal) the meaning of the pin is not RTSN at all!
channel in the automatic echo mode, which automatically
Rather, it signals that the transmitter has finished the transmission
re-transmits the received data. The following conditions are true
(i.e., end of block).
while in automatic echo mode:
1. Received data is re-clocked and re-transmitted on the TxDA This bit allows deactivation of the RTSN output by the transmitter.
output. This output is manually asserted and negated by the appropriate
2. The receive clock is used for the transmitter. commands issued via the command register. MR2[5] set to 1
caused the RTSN to be reset automatically one bit time after the
3. The receiver must be enabled, but the transmitter need not be
character(s) in the transmit shift register and in the THR (if any) are
enabled.
completely transmitted (including the programmed number of stop
4. The Channel A TxRDY and TxEMT status bits are inactive. bits) if a previously issued transmitter disable is pending. This
5. The received parity is checked, but is not regenerated for trans- feature can be used to automatically terminate the transmission as
mission, i.e. transmitted parity bit is as received. follows:
1. Program the auto-reset mode: MR2[5]=1
6. Character framing is checked, but the stop bits are retransmitted
2. Enable transmitter, if not already enabled
as received.
3. Assert RTSN via command
7. A received break is echoed as received until the next valid start 4. Send message
bit is detected. 5. After the last character of the message is loaded to the THR,
8. CPU to receiver communication continues normally, but the CPU disable the transmitter. (If the transmitter is underrun, a special
to transmitter link is disabled. case exists. See note below.)
6. The last character will be transmitted and the RTSN will be reset
Two diagnostic modes can also be configured. MR2A[7:6] = 10 one bit time after the last stop bit is sent.
selects local loopback mode. In this mode:
1. The transmitter output is internally connected to the receiver NOTE: The transmitter is in an underrun condition when both the
TxRDY and the TxEMT bits are set. This condition also exists
input.
immediately after the transmitter is enabled from the disabled or
2. The transmit clock is used for the receiver. reset state. When using the above procedure with the transmitter in
3. The TxDA output is held High. the underrun condition, the issuing of the transmitter disable must be
4. The RxDA input is ignored. delayed from the loading of a single, or last, character until the
TxRDY becomes active again after the character is loaded.
5. The transmitter must be enabled, but the receiver need not be
enabled. MR2A[4] – Channel A Clear-to-Send Control
6. CPU to transmitter and receiver communications continue nor- If this bit is 0, CTSAN has no effect on the transmitter. If this bit is a
mally. 1, the transmitter checks the state of CTSAN (IP0) each time it is
ready to send a character. If IP0 is asserted (Low), the character is
The second diagnostic mode is the remote loopback mode, selected transmitted. If it is negated (High), the TxDA output remains in the
by MR2A[7:6] = 11. In this mode: marking state and the transmission is delayed until CTSAN goes
1. Received data is re-clocked and re-transmitted on the TxDA low. Changes in CTSAN while a character is being transmitted do
output. not affect the transmission of that character.
2. The receive clock is used for the transmitter. MR2A[3:0] – Channel A Stop Bit Length Select
3. Received data is not sent to the local CPU, and the error status This field programs the length of the stop bit appended to the
conditions are inactive. transmitted character. Stop bit lengths of 9/16 to 1 and 1-9/16 to 2
4. The received parity is not checked and is not regenerated for bits, in increments of 1/16 bit, can be programmed for character
transmission, i.e., transmitted parity is as received. lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1-1/16
to 2 stop bits can be programmed in increments of 1/16 bit. The
5. The receiver must be enabled.
receiver only checks for a ‘mark’ condition at the center of the first
6. Character framing is not checked, and the stop bits are retrans- stop bit position (one bit time after the last data bit, or after the parity
mitted as received. bit is enabled), in all cases.
7. A received break is echoed as received until the next valid start
bit is detected.

1998 Sep 04 13
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

If an external 1X clock is used for the transmitter, MR2A[3] = 0 CSRB[7:4] ACR[7] = 0 Baud Rate ACR[7] = 1
selects one stop bit and MR2A[3] = 1 selects two stop bits to be
transmitted. 1110 IP2-16X IP2-16X
1111 IP2-1X IP2-1X
MR1B – Channel B Mode Register 1
MR1B is accessed when the Channel B MR pointer points to MR1. The receiver clock is always a 16X clock except for CSRB[7:4] =
The pointer is set to MR1 by RESET or by a ‘set pointer’ command 1111.
applied via CRB. After reading or writing MR1B, the pointer will
point to MR2B. CSRB[3:0] – Channel B Transmitter Clock Select
This field selects the baud rate clock for the Channel B transmitter.
The bit definitions for this register are identical to MR1A, except that
The field definition is as shown in Table 3, except as follows:
all control actions apply to the Channel B receiver and transmitter
and the corresponding inputs and outputs. CSRB[3:0] ACR[7] = 0 Baud Rate ACR[7] = 1

MR2B – Channel B Mode Register 2 1110 IP5-16X IP5-16X

MR2B is accessed when the Channel B MR pointer points to MR2, 1111 IP5-1X IP5-1X
which occurs after any access to MR1B. Accesses to MR2B do not
The transmitter clock is always a 16X clock except for CSRB[3:0] =
change the pointer.
1111.
The bit definitions for mode register are identical to the bit
definitions for MR2A, except that all control actions apply to the
CRA – Channel A Command Register
CRA is a register used to supply commands to Channel A. Multiple
Channel B receiver and transmitter and the corresponding inputs
commands can be specified in a single write to CRA as long as the
and outputs.
commands are non-conflicting, e.g., the ‘enable transmitter’ and
CSRA – Channel A Clock Select Register ‘reset transmitter’ commands cannot be specified in a single
CSRA[7:4] – Channel A Receiver Clock Select command word.
This field selects the baud rate clock for the Channel A receiver. CRA[7] – Not Used
The field definition is shown in Table 3. Should be set to zero for upward compatibility with newer parts.
CSRA[3:0] – Channel A Transmitter Clock Select CRA[6:4] – Miscellaneous Commands
This field selects the baud rate clock for the Channel A transmitter. The encoded value of this field may be used to specify a single
The field definition is as shown in Table 3, except as follows: command as follows:
CRA[6:4] – COMMAND
CSRA[3:0] ACR[7] = 0 Baud Rate ACR[7] = 1
NOTE: Access to the upper four bits of the command register should be separated by three
1110 IP3-16X IP3-16X (3) edges of the X1 clock.
1111 IP3-1X IP3-1X 000 No command.
The transmitter and receiver clock is always a 16X clock except 001 Reset MR pointer. Causes the Channel A MR pointer to point to MR1.
for 1111 selection. 010 Reset receiver. Resets the Channel A receiver as if a hardware reset had been ap-
plied. The receiver is disabled and the FIFO is flushed.
Table 3. Baud Rate Clock = 3.6864 MHz 011 Reset transmitter. Resets the Channel A transmitter as if a hardware reset had been
applied.
CSRA[7:4] ACR[7] = 0 Baud Rate ACR[7] = 1
100 Reset error status. Clears the Channel A Received Break, Parity Error, and Overrun
0000 50 75 Error bits in the status register (SRA[7:4]). Used in character mode to clear OE status
(although RB, PE and FE bits will also be cleared) and in block mode to clear all error
0001 110 110 status after a block of data has been received.
0010 134.5 134.5 101 Reset Channel A break change interrupt. Causes the Channel A break detect
0011 200 150 change bit in the interrupt status register (ISR[2]) to be cleared to zero.

0100 300 300 110 Start break. Forces the TxDA output Low (spacing). If the transmitter is empty the
start of the break condition will be delayed up to two bit times. If the transmitter is
0101 600 600 active the break begins when transmission of the character is completed. If a charac-
ter is in the THR, the start of the break will be delayed until that character, or any other
0110 1,200 1,200 loaded subsequently are transmitted. The transmitter must be enabled for this com-
0111 1,050 2,000 mand to be accepted.
1000 2,400 2,400 111 Stop break. The TxDA line will go High (marking) within two bit times. TxDA will
remain High for one bit time before the next character, if any, is transmitted.
1001 4,800 4,800
1010 7,200 1,800 CRA[3] – Disable Channel A Transmitter
1011 9,600 9,600 This command terminates transmitter operation and reset the
1100 38.4k 19.2k TxDRY and TxEMT status bits. However, if a character is being
1101 Timer Timer transmitted or if a character is in the THR when the transmitter is
1110 IP4-16X IP4-16X disabled, the transmission of the character(s) is completed before
1111 IP4-1X IP4-1X assuming the inactive state.
CRA[2] – Enable Channel A Transmitter
See Table 6.
Enables operation of the Channel A transmitter. The TxRDY status
CSRB – Channel B Clock Select Register bit will be asserted.

CSRB[7:4] – Channel B Receiver Clock Select CRA[1] – Disable Channel A Receiver

This field selects the baud rate clock for the Channel B receiver. This command terminates operation of the receiver immediately – a
The field definition is as shown in Table 3, except as follows: character being received will be lost. The command has no effect

1998 Sep 04 14
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

on the receiver status bits or any other control registers. If the state. It is always set after transmission of the last stop bit of a
special multidrop mode is programmed, the receiver operates even character if no character is in the THR awaiting transmission.
if it is disabled. See Operation section.
It is reset when the THR is loaded by the CPU, a pending
CRA[0] – Enable Channel A Receiver transmitter disable is executed, the transmitter is reset, or the
Enables operation of the Channel A receiver. If not in the special transmitter is disabled while in the underrun condition.
wake up mode, this also forces the receiver into the search for
start-bit state. SRA[2] – Channel A Transmitter Ready (TxRDYA)
This bit, when set, indicates that the THR is empty and ready to be
CRB – Channel B Command Register loaded with a character. This bit is cleared when the THR is loaded
CRB is a register used to supply commands to Channel B. Multiple by the CPU and is set when the character is transferred to the
commands can be specified in a single write to CRB as long as the transmit shift register. TxRDY is reset when the transmitter is
commands are non-conflicting, e.g., the ‘enable transmitter’ and disabled and is set when the transmitter is first enabled, viz.,
‘reset transmitter’ commands cannot be specified in a single characters loaded into the THR while the transmitter is disabled will
command word. not be transmitted.
The bit definitions for this register are identical to the bit definitions
SRA[1] – Channel A FIFO Full (FFULLA)
for CRA, except that all control actions apply to the Channel B
This bit is set when a character is transferred from the receive shift
receiver and transmitter and the corresponding inputs and outputs.,
register to the receive FIFO and the transfer causes the FIFO to
SRA – Channel A Status Register become full, i.e., all three FIFO positions are occupied. It is reset
SRA[7] – Channel A Received Break when the CPU reads the RHR. If a character is waiting in the
This bit indicates that an all zero character of the programmed receive shift register because the FIFO is full, FFULL will not be
length has been received without a stop bit. Only a single FIFO reset when the CPU reads the RHR.
position is occupied when a break is received further entries to the SRA[0] – Channel A Receiver Ready (RxRDYA)
FIFO are inhibited until the RxDA line to the marking state for at This bit indicates that a character has been received and is waiting
least one-half a bit time two successive edges of the internal or in the FIFO to be read by the CPU. It is set when the character is
external 1X clock. This will usually require a high time of one X1 transferred from the receive shift to the FIFO and reset when the
clock period or 3 X1 edges since the clock of the controller is CPU reads the RHR, if after this read there are not more characters
not synchronous to the X1 clock. still in the FIFO.
When this bit is set, the Channel A ‘change in break’ bit in the ISR SRB – Channel B Status Register
(ISR[2]) is set. ISR[2] is also set when the end of the break The bit definitions for this register are identical to the bit definitions
condition, as defined above, is detected. for SRA, except that all status applies to the Channel B receiver and
The break detect circuitry can detect breaks that originate in the transmitter and the corresponding inputs and outputs.
middle of a received character. However, if a break begins in the OPCR – Output Port Configuration Register
middle of a character, it must persist until at least the end of the next
character time in order for it to be detected. OPCR[7] – OP7 Output Select
This bit programs the OP7 output to provide one of the following:
SRA[6] – Channel A Framing Error 0: The complement of OPR[7].
This bit, when set, indicates that a stop bit was not detected when
1: The Channel B transmitter interrupt output which is the comple-
the corresponding data character in the FIFO was received. The
ment of TxRDYB. When in this mode OP7 acts as an open-
stop bit check is made in the middle of the first stop bit position.
drain output. Note that this output is not masked by the contents
SRA[5] – Channel A Parity Error of the IMR.
This bit is set when the ‘with parity’ or ‘force parity’ mode is
programmed and the corresponding character in the FIFO was OPCR[6] – OP6 Output Select
received with incorrect parity. This bit programs the OP6 output to provide one of the following:
0: The complement of OPR[6].
In the special multidrop mode the parity error bit stores the receive
A/D bit. 1: The Channel A transmitter interrupt output which is the comple-
ment of TxRDYA. When in this mode OP6 acts as an open-
SRA[4] – Channel A Overrun Error drain output. Note that this output is not masked by the contents
This bit, when set, indicates that one or more characters in the of the IMR.
received data stream have been lost. It is set upon receipt of a new
character when the FIFO is full and a character is already in the OPCR[5] – OP5 Output Select
receive shift register waiting for an empty FIFO position. When this This bit programs the OP5 output to provide one of the following:
occurs, the character in the receive shift register (and its break 0: The complement of OPR[5].
detect, parity error and framing error status, if any) is lost. 1: The Channel B transmitter interrupt output which is the comple-
ment of ISR[5]. When in this mode OP5 acts as an open-drain
This bit is cleared by a ‘reset error status’ command.
output. Note that this output is not masked by the contents of
SRA[3] – Channel A Transmitter Empty (TxEMTA) the IMR.
This bit will be set when the transmitter underruns, i.e., both the
TxEMT and TxRDY bits are set. This bit and TxRDY are set when OPCR[4] – OP4 Output Select
the transmitter is first enabled and at any time it is re-enabled after This field programs the OP4 output to provide one of the following:
either (a) reset, or (b) the transmitter has assumed the disabled 0: The complement of OPR[4].

1998 Sep 04 15
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

1: The Channel A receiver interrupt output which is the complement Asynchronous UART communications can tolerate frequency error
of ISR[1]. When in this mode OP4 acts as an open-drain output. of 4.1% to 6.7% in a “clean” communications channel. The percent
Note that this output is not masked by the contents of the IMR. of error changes as the character length changes. The above
percentages range from 5 bits not parity to 8 bits with parity and one
OPCR[3:2] – OP3 Output Select stop bit. The error with 8 bits no parity and one stop bit is 4.6%. If a
This bit programs the OP3 output to provide one of the following: stop bit length of 9/16 is used, the error tolerance will approach 0
00: The complement of OPR[3]. due to a variable error of up to 1/16 bit time in receiver clock phase
01: The counter/timer output, in which case OP3 acts as an open- alignment to the start bit.
drain output. In the timer mode, this output is a square wave at
the programmed frequency. In the counter mode, the output
remains High until terminal count is reached, at which time it
Table 5. ACR 6:4 Field Definition
goes Low. The output returns to the High state when the count- ACR MODE CLOCK SOURCE
er is stopped by a stop counter command. Note that this output [6:4]
is not masked by the contents of the IMR. 000 Counter External (IP2)*
001 Counter TxCA – 1x clock of Channel
10: The 1X clock for the Channel B transmitter, which is the clock
A transmitter
that shifts the transmitted data. If data is not being transmitted, 010 Counter TxCB – 1x clock of Channel
a free running 1X clock is output. B transmitter
11: The 1X clock for the Channel B receiver, which is the clock that 011 Counter Crystal or external clock
samples the received data. If data is not being received, a free (x1/CLK) divided by 16
100 Timer (square wave) External (IP2)*
running 1X clock is output.
101 Timer (square wave) External (IP2) divided by 16*
110 Timer (square wave) Crystal or external clock
OPCR[1:0] – OP2 Output Select
(X1/CLK)
This field programs the OP2 output to provide one of the following: Crystal or external clock
00: The complement of OPR[2]. 111 Timer (square wave) (X1/CLK) divided by 16
01: The 16X clock for the Channel A transmitter. This is the clock NOTE:
selected by CSRA[3:0], and will be a 1X clock if CSRA[3:0] = 1111. * In these modes, the Channel B receiver clock should normally be
10: The 1X clock for the Channel A transmitter, which is the clock generated from the baud rate generator. Timer mode generates
that shifts the transmitted data. If data is not being transmitted, squarewave.
a free running 1X clock is output.
11: The 1X clock for the Channel A receiver, which is the clock that ACR – Auxiliary Control Register
samples the received data. If data is not being received, a free ACR[7] – Baud Rate Generator Set Select
running 1X clock is output. This bit selects one of two sets of baud rates to be generated by the
BRG:
Table 4. Bit Rate Generator Characteristics Set 1: 50, 110, 134.5, 200, 300, 600, 1.05k, 1.2k, 2.4k, 4.8k, 7.2k,
Crystal or Clock = 3.6864MHz 9.6k, and 38.4k baud.
NORMAL RATE ACTUAL 16x Set 2: 75, 110, 134.5, 150, 300, 600, 1.2k, 1.8k, 2.0k, 2.4k, 4.8k,
(BAUD) CLOCK (kHz) ERROR (%)
9.6k, and 19.2k baud.
50 0.8 0
The selected set of rates is available for use by the Channel A and
75 1.2 0
B receivers and transmitters as described in CSRA and CSRB.
110 1.759 -0.069
Baud rate generator characteristics are given in Table 4.
134.5 2.153 0.059
150 2.4 0 ACR[6:4] – Counter/Timer Mode And Clock Source Select
200 3.2 0 This field selects the operating mode of the counter/timer and its
300 4.8 0 clock source as shown in Table 5.
600 9.6 0
ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable
1050 16.756 -0.260
This field selects which bits of the input port change register (IPCR)
1200 19.2 0
cause the input change bit in the interrupt status register (ISR[7]) to
1800 28.8 0
be set. If a bit is in the ‘on’ state the setting of the corresponding bit
2000 32.056 0.175 in the IPCR will also result in the setting of ISR[7], which results in
2400 38.4 0 the generation of an interrupt output if IMR[7] = 1. If a bit is in the
4800 76.8 0 ‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7].
7200 115.2 0
9600 153.6 0
IPCR – Input Port Change Register
14.4K 230.4 0 IPCR[7] – IP3, IP2, IP1, IP0 Change-of-State
19.2k 307.2 0 These bits are set when a change-of-state, as defined in the input
28.8K 460.8 0 port section of this data sheet, occurs at the respective input pins.
38.4k 614.4 0 They are cleared when the IPCR is read by the CPU. A read of the
57.6K 921.6 0 IPCR also clears ISR[7], the input change bit in the interrupt status
115.2K 1843.2K 0 register. The setting of these bits can be programmed to generate
NOTE: an interrupt to the CPU.
Duty cycle of 16x clock is 50% ± 1%.

1998 Sep 04 16
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

IPCR[3:0] – IP3, IP2, IP1, IP0 Current State Channel A and is waiting in the FIFO to be read by the CPU. It is
These bits provide the current state of the respective inputs. The set when the character is transferred from the receive shift register
information is unlatched and reflects the state of the input pins at the to the FIFO and reset when the CPU read the RHR. If after this
time the IPCR is read. read there are more characters still in the FIFO the bit will be set
again after the FIFO is ‘popped’. If programmed as FIFO full, it is
ISR – Interrupt Status Register
set when a character is transferred from the receive holding register
This register provides the status of all potential interrupt sources.
to the receive FIFO and the transfer caused the Channel A FIFO to
The contents of this register are masked by the Interrupt Mask
become full; i.e., all three FIFO positions are occupied. It is reset
Register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit
when the CPU reads the RHR. If a character is waiting in the
in the IMR is also a ‘1’, the INTRN output will be asserted (Low). If
receive shift register because the FIFO is full, the bit will be set
the corresponding bit in the IMR is a zero, the state of the bit in the
again when the ISR[0] and IMR waiting character is loaded into the
ISR has no effect on the INTRN output. Note that the IMR does not
FIFO.
mask the reading of the ISR – the true status will be provided
regardless of the contents of the IMR. The contents of this register ISR[0] – Channel A Transmitter Ready
are initialized to 0016 when the DUART is reset. This bit is a duplicate of TxRDYA (SRA[2]).

ISR[7] – Input Port Change Status IMR – Interrupt Mask Register

This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1, The programming of this register selects which bits in the ISR
IP2, or IP3 inputs and that event has been selected to cause an causes an interrupt output. If a bit in the ISR is a ‘1’ and the
interrupt by the programming of ACR[3:0]. The bit is cleared when corresponding bit in the IMR is also a ‘1’ the INTRN output will be
the CPU reads the IPCR. asserted. If the corresponding bit in the IMR is a zero, the state of
the bit in the ISR has no effect on the INTRN output. Note that the
ISR[6] – Channel B Change In Break IMR does not mask the programmable interrupt outputs OP3-OP7 or
This bit, when set, indicates that the Channel B receiver has the reading of the ISR.
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel B ‘reset break change interrupt’
CTUR and CTLR – Counter/Timer Registers
command. The CTUR and CTLR hold the eight MSBs and eight LSBs,
respectively, of the value to be used by the counter/timer in either
ISR[5] – Channel B Receiver Ready or FIFO Full the counter or timer modes of operation. The minimum value which
The function of this bit is programmed by MR1B[6]. If programmed may be loaded into the CTUR/CTLR registers is 000216. Note that
as receiver ready, it indicates that a character has been received in these registers are write-only and cannot be read by the CPU.
Channel B and is waiting in the FIFO to be read by the CPU. It is
In the timer (programmable divider) mode, the C/T generates a
set when the character is transferred from the receive shift register
square wave with a period of twice the value (in clock periods) of the
to the FIFO and reset when the CPU reads the RHR. If after this
CTUR and CTLR. If the value in CTUR and CTLR is changed, the
read there are more characters still in the FIFO the bit will be set
current half-period will not be affected, but subsequent half periods
again after the FIFO is ‘popped’. If programmed as FIFO full, it is
will be. In this mode the C/T runs continuously. Receipt of a start
set when a character is transferred from the receive holding register
counter command (read with A4-A1) = 1110) causes the counter to
to the receive FIFO and the transfer caused the Channel B FIFO to
terminate the current timing cycle and to begin a new cycle using the
become full; i.e., all three FIFO positions are occupied. It is reset
values in CTUR and CTLR. The waveform so generated is often
when the CPU reads the RHR. If a character is waiting in the
used for a data clock. The formula for calculating the divisor n to
receive shift register because the FIFO is full, the bit will be set
load to the CTUR and CTLR for a particular 1X data clock is shown
again when the waiting character is loaded into the FIFO.
below:
ISR[4] – Channel B Transmitter Ready CT Clock Frequency
This bit is a duplicate of TxRDYB (SRB[2]). n

2  16  Baud rate desired
ISR[3] – Counter Ready. Often this division will result in a non-integer number; 26.3, for
In the counter mode, this bit is set when the counter reaches example. One can only program integer numbers in a digital divider.
terminal count and is reset when the counter is stopped by a stop Therefore, 26 would be chosen. This gives a baud rate error of
counter command. 0.3/26.3 which is 1.14%; well within the ability asynchronous mode
In the timer mode, this bit is set once each cycle of the generated of operation.
square wave (every other time that the counter/timer reaches zero The counter ready status bit (ISR[3]) is set once each cycle of the
count). The bit is reset by a stop counter command. The command, square wave. The bit is reset by a stop counter command (read
however, does not stop the counter/timer. with A4-A1 = 1111). The command, however, does not stop the C/T.
The generated square wave is output on OP3 if it is programmed to
ISR[2] – Channel A Change in Break
be the C/T output.
This bit, when set, indicates that the Channel A receiver has
detected the beginning or the end of a received break. It is reset On power-up and after reset, the counter/timer runs in timer mode
when the CPU issues a Channel A ‘reset break change interrupt’ and can only be restarted. Because it cannot be shut off or stopped,
command. and runs continuously in timer mode, it is recommended that at
initialization, the output port, OP3, should be masked off through the
ISR[1] – Channel A Receiver Ready Or FIFO Full OPCR[3:2} = 00 until the C/T is programmed to the desired
The function of this bit is programmed by MR1A[6]. If programmed operational state.
as receiver ready, it indicates that a character has been received in

1998 Sep 04 17
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

In the counter mode, the C/T counts down the number of pulses In the counter mode, the current value of the upper and lower 8 bits
loaded into CTUR and CTLR by the CPU. Counting begins upon of the counter (CTU, CTL) may be read by the CPU. It is
receipt of a start counter command. Upon reaching terminal count recommended that the counter be stopped when reading to prevent
000016, the counter ready interrupt bit (ISR[3]) is set. The counter potential problems which may occur if a carry from the lower 8 bits
continues counting past the terminal count until stopped by the CPU. to the upper 8 bits occurs between the times that both halves of the
If OP3 is programmed to be the output of the C/T, the output counter are read. However, note that a subsequent start counter
remains High until terminal count is reached, at which time it goes command will cause the counter to begin a new count cycle using
Low. The output returns to the High state and ISR[3] is cleared the values in CTUR and CTLR.
when the counter is stopped by a stop counter command. The
IVR – Interrupt Vector Register
CPU may change the values of CTUR and CTLR at any time, but
This register contains the interrupt vector. The register is initialized
the new count becomes effective only on the next start counter
to H‘0F’ by RESET. The contents of the register are placed on the
commands. If new values have not been loaded, the previous count
data bus when the DUART responds to a valid interrupt
values are preserved and used for the next count cycle
acknowledge cycle.

1998 Sep 04 18
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

RESETN

tRES

SD00109

Figure 3. Reset Timing

tCSC

X1/CLK
tAS

A1–A4

tRWS tRWH

RWN tAH
tCSW
CSN

tDD tDF
D0–D7

tCSD
tDAL
DTACKN

tDAH
tDCR
tDAT
SD00110

Figure 4. Bus Timing (Read Cycle)

tCSC

X1/CLK
tAS

A1–A4

tRWS tRWH
RWN
tAH

tCSW
CSN

D0–D7

tDH
tDS
tCSD
DTACKN

NOTE: tDCW tDAH

DACKN requires two rising edges of X1 clock after CEN is low.
tDAT
SD00111

Figure 5. Bus Timing (Write Cycle)

1998 Sep 04 19
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

tCSC
X1/CLK

INTRN

IACKN

tDD tDF

D0–D7

tCSD

tDAL

DTACKN

tDCR tDAH

tDAT
SD00112

Figure 6. Interrupt Cycle Timing

CSN

tPS tPH

IP0–IP5

CSN

OP0–OP7 OLD DATA NEW DATA

tPD
SD00113

Figure 7. Port Timing

RxC
(1X INPUT)

tRXS tRXH

RxD

SD00114

Figure 8. Receive Timing

1998 Sep 04 20
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

+5V
R1: 100K - 1Meg (See design note)
C1 = C2: 0-5pF + (STRAY < 5pF)
tCLK 1K
tCTC
DRIVING FROM CLOCK
tRx EXTERNAL SOURCE TO OTHER
tTx CHIPS
X1/CLK 74LS04
CTCLK
RxC
TxC SCN2681
X1 TO THE REST
tCLK OF THE DUART
tCTC OPEN CIRCUITS
X1
tRx +5V C1
tTx R2
R1
1KΩ
C2
When using an external clock it is preferred to drive X2 and leave X1 open. U1
X2 is the input to the internal driver, while X1 is the output.
R1 is only required if U1 will not drive to X2 high level. X2 X2
Previous specifications indicated X2 should be grounded and X1
3.6864MHz
should be driven. This is still acceptable. It is electrically easier to drive
the amplifier input than to overdrive its output. CRYSTAL SERIES RESISTANCE3 SHOULD BE LESS THAN 180Ω
R2 = 50kΩ to 150kΩ
SD00115

Figure 9. Clock Timing

CSN
(READ OR
VM
WRITE)

tIR
VOL +0.5V
INTERRUPT 1
OUTPUT
VOL
NOTES:
1. INTRN or OP3 – OP7 when used as interrupt outputs.
2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the mid point of the switching signal, VM, to
a point 0.5 volts above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are
pronounced and can greatly affect the resultant measurement.
SD00116

Figure 10. Interrupt Timing

1 BIT TIME
(1 OR 16 CLOCKS)
TxC
(INPUT)

tTXD

TxD

tTCS
TxC
(1X OUTPUT)

SD00117

Figure 11. Transmit Timing

1998 Sep 04 21
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

RxC
(1X INPUT)

tRXS tRXH

RxD

SD00093

Figure 12. Receive Timing

TxD D1 D2 D3 BREAK D4 D6

TRANSMITTER
ENABLED

TxRDY
(SR2)

CSN
(WRITE)
D1 D2 D3 START D4 STOP D5 WILL D6
BREAK BREAK NOT BE
CTSN1 TRANSMITTED
(IP0)

RTSN2
(OP0)

OPR(0) = 1 OPR(0) = 1

NOTES:
1. Timing shown for MR2(4) = 1.
2. Timing shown for MR2(5) = 1.
SD00118

Figure 13. Transmitter Timing

RxD D1 D2 D3 D4 D5 D6 D7 D8
D6, D7, D8 WILL BE LOST
RECEIVER
ENABLED

RxRDY
(SR0)

FFULL
(SR1)

RxRDY/
FFULL
(OP4)2

CSN
(READ)
STATUS DATA STATUS DATA STATUS DATA STATUS DATA

D1 D5 WILL D2 D3 D4
OVERRUN BE LOST
(SR4) RESET BY COMMAND

RTS1
(OP0)

OPR(0) = 1
NOTES:
1. Timing shown for MR1(7) = 1.
2. Shown for OPCR(4) and MR1(6) = 0. SD00119

Figure 14. Receive Timing

1998 Sep 04 22
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

MASTER STATION
BIT 9 BIT 9 BIT 9

TxD ADD#1 1 D0 0 ADD#2 1

TRANSMITTER
ENABLED

TxRDY
(SR2)

CSN
(WRITE)
MR1(4+3) = 11 ADD#1 MR1(2) = 0 D0 MR1(2) = 1 ADD#2
MR1(2) = 1

PERIPHERAL STATION
BIT 9 BIT 9 BIT 9 BIT 9 BIT 9
RxD 0 ADD#1 1 D0 0 ADD#2 1 0

RECEIVER
ENABLED

RxRDY
(SR0)

CSN

MR1(4:3) = 11 ADD#1 STATUS DATA STATUS DATA

D0 ADD#2

SD00120

Figure 15. Wake-Up Mode

Output Port Notes driven high, the transmitter will stop sending data at the end of the
The output ports are controlled from three places: the OPCR present character being serialized. It is usually the RTS output of
register, the OPR register, and the MR registers. The OPCR the receiver that will be connected to the transmitter’s CTS input.
register controls the source of the data for the output ports OP2 The receiver will set RTS high when the receiver FIFO is full AND
through OP7. The data source for output ports OP0 and OP1 is the start bit of the fourth character is sensed. Transmission then
controlled by the MR and CR registers. When the OPR is the stops with four valid characters in the receiver. When MR2(4) is set
source of the data for the output ports, the data at the ports is to one, CTSN must be at zero for the transmitter to operate. If
inverted from that in the OPR register. The content of the OPR MR2(4) is set to zero, the MP pin will have no effect on the operation
register is controlled by the “Set Output Port Bits Command”. These of the transmitter.
commands are at E and F, respectively. When these commands are MR1(7) is the bit that allows the receiver to control MP0. When MP0
used, action takes place only at the bit locations where ones exist. is controlled by the receiver, the meaning of that pin will be RTS.
For example, a one in bit location 5 of the data word used with the However, a point of confusion arises in that MP0 may also be
“Set Output Port Bits” command will result in OPR5 being set to one. controlled by the transmitter. When the transmitter is controlling this
The OP5 would then be set to zero (VSS). Similarly, a one in bit pin, its meaning is not RTS at all. It is, rather, that the transmitter
position 5 of the data word associated with the “Reset Output Ports has finished sending its last data byte. Programming the MP0 pin to
Bits” command would set OPR5 to zero, and hence, the pin OP5 to be controlled by the receiver and the transmitter at the same time is
a one (VDD). allowed, but would usually be incompatible.
The CTS, RTS, CTS Enable Tx signals RTS is expressed at the MP0 pin which is still an output port.
CTS (Clear To Send) is usually meant to be a signal to the Therefore, the state of MP0 should be set low for the receiver to
transmitter meaning that it may transmit data to the receiver. The generate the proper RTS signal. The logic at the output is basically
CTS input is on pin MPI. The CTS signal is active low; thus, it is a NAND of the MP0 bit register and the RTS signal as generated by
called CTS. the receiver. When the RTS flow control is selected via the MR(7)
bit the state of the MP0 register is not changed. Terminating the use
RTS is usually meant to be a signal from the receiver indicating that
of “Flow Control” (via the MR registers) will return the MP0 pin to the
the receiver is ready to receive data. It is also active low and is,
control of the MP0 register.
thus, called RTSN. RTSN is on pin MP0. A receiver’s RTS output
will usually be connected to the CTS input of the associated Transmitter Disable Note
transmitter. Therefore, one could say that RTS and CTS are The sequence of instructions enable transmitter — load transmit
different ends of the same wire! holding register — disable transmitter will result in nothing being
MR2(4) is the bit that allows the transmitter to be controlled by the sent if the time between the end of loading the transmit holding
CTS pin (MPI). When this bit is set to one AND the CTS input is register and the disable command is less that 3/16 bit time in the

1998 Sep 04 23
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

16x mode or one bit time in the 1x mode. Also, if the transmitter, been enabled), be sure the TxRDY bit is active immediately before
while in the enabled state and underrun condition, is immediately issuing the transmitter disable instruction. TxRDY sets at the end of
disabled after a single character is loaded to the transmit holding the “start bit” time. It is during the start bit that the data in the
register, that character will not be sent. transmit holding register is transferred to the transmit shift register.
In general, when it is desired to disable the transmitter before the Non-standard baud rates are available as shown in Table 6 below,
last character is sent AND the TxEMT bit is set in the status register via the BRG Test function.
(TxEMT is always set if the transmitter has underrun or has just

Table 6. Baud Rates Extended

Normal BRG BRG Test
CSR[7:4] ACR[7] = 0 ACR[7] = 1 ACR[7] = 0 ACR[7] = 1
0000 50 75 4,800 7,200
0001 110 110 880 880
0010 134.5 134.5 1,076 1,076
0011 200 150 19.2K 14.4K
0100 300 300 28.8K 28.8K
0101 600 600 57.6K 57.6K
0110 1,200 1,200 115.2K 115.2K
0111 1,050 2,000 1,050 2,000
1000 2,400 2,400 57.6K 57.6K
1001 4,800 4,800 4,800 4,800
1010 7,200 1,800 57.6K 14.4K
1011 9,600 9,600 9,600 9,600
1100 38.4K 19.2K 38.4K 19.2K
1101 Timer Timer Timer Timer
1110 I/O2 – 16X I/O2 – 16X I/O2 – 16X I/O2 – 16X
1111 I/O2 – 1X I/O2 – 1X I/O2 – 1X I/O2 – 1X
NOTE:
Each read on address H‘2’ will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left. This
change affects all receivers and transmitters on the DUART. See “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication.
The test mode at address H‘A’ changes all transmitters and receivers to the 1x mode and connects the output ports to some internal nodes.

A condition that occurs infrequently has been observed where the receiver will ignore all data. It is caused by a corruption of the start bit
generally due to noise. When this occurs the receiver will appear to be asleep or locked up. The receiver must be reset for the UART to
continue to function properly.

Reset in the Normal Mode (Receiver Enabled)

Recovery can be accomplished easily by issuing a receiver software reset followed by a receiver enable. All receiver data, status and
programming will be preserved and available before reset. The reset will NOT affect the programming.

Reset in the Wake-Up Mode (MR1[4:3] = 11)

Recovery can also be accomplished easily by first exiting the wake-up mode (MR1[4:3] = 00 or 01 or 10), then issuing a receiver software
reset followed by a wake-up re-entry (MR1[4:3] = 11). All receiver data, status and programming will be preserved and available before
reset. The reset will NOT affect the programming.
The receiver has a digital filter designed to reject “noisy” data transitions and the receiver state machine was designed to reject noisy start
bits or noise that might be considered a start bit. In spite of these precautions, corruption of the start bit can occur in 15ns window
approximately 100ns prior to the rising edge of the data clock. The probability of this occurring is less than 10–5 at 9600 baud.
A corrupted start bit may have some deleterious effects in ASYNC operation if it occurs within a normal data block. The receiver will tend
to align its data clock to the next ‘0’ bit in the data stream, thus potentially corrupting the remainder of the data block. A good design
practice, in environments where start bit corruption is possible, is to monitor data quality (framing error, parity error, break change and
received break) and “data stopped” time out periods. Time out periods can be enabled using the counter/timer in the SCC2691, SCC2692,
SCC2698B and SC68692 products. This monitoring can indicate a potential start bit corruption problem.
SD00097

1998 Sep 04 24
1998 Sep 04

0590B

Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
853–0590B 06688

40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)
0.098 (2.49) 0.098 (2.49)
NOTES:
SEE NOTE 6 1. Controlling dimension: Inches. Millimeters are
0.040 (1.02) 0.040 (1.02)
shown in parentheses.
2. Dimension and tolerancing per ANSI Y14. 5M-1982.
3. “T”, “D”, and “E” are reference datums on the body
and include allowance for glass overrun and meniscus
on the seal line, and lid to base mismatch.
4. These dimensions measured with the leads
0.598 (15.19)
–E– constrained to be perpendicular to plane T.
0.571 (14.50)
5. Pin numbers start with Pin #1 and continue
counterclockwise to Pin #40 when viewed
from the top.
6. Denotes window location for EPROM products.

PIN # 1
0.100 (2.54) BSC
2.087 (53.01)
–D–
2.038 (51.77)
25

0.620 (15.75)
0.070 (1.78) 0.590 (14.99)
0.050 (1.27) (NOTE 4)

0.175 (4.45)
0.225 (5.72) MAX. 0.145 (3.68)
–T–

SEATING 0.165 (4.19)

PLANE 0.055 (1.40)
0.125 (3.18)
0.020 (0.51)
BSC
0.600 (15.24)
(NOTE 4)
0.023 (0.58)
T E D 0.010 (0.254)
0.015 (0.38) 0.695 (17.65)
0.015 (0.38)
0.600 (15.24)
0.010 (0.25)

SCN68681

Product specification
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

1998 Sep 04 26
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

1998 Sep 04 27
Philips Semiconductors Product specification

Dual asynchronous receiver/transmitter (DUART) SCN68681

Data sheet status

Data sheet Product Definition [1]
status status

Objective Development This data sheet contains the design target or goal specifications for product development.
specification Specification may change in any manner without notice.

Preliminary Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date.
specification Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make
specification changes at any time without notice in order to improve design and supply the best possible product.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors  Copyright Philips Electronics North America Corporation 1998

811 East Arques Avenue All rights reserved. Printed in U.S.A.
P.O. Box 3409
Sunnyvale, California 94088–3409 Date of release: 09-98
Telephone 800-234-7381
Document order number: 9397 750 04364

 
   
1998 Sep 04 28