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HT46R47
8-Bit OTP Battery Charger Controller

Features
· Operating voltage: · Up to 0.5ms instruction cycle with 8MHz
fSYS=4MHz: 3.3V~5.5V system clock at VDD=5V
fSYS=8MHz: 4.5V~5.5V · Six-level subroutine nesting
· 13 bidirectional I/O lines (max.) · 4 channels 9-bit resolution (8-bit accuracy)
· 1 interrupt input shared with an I/O line A/D converter
· 8-bit programmable timer/event counter with · 1 channel (6+2)-bit PWM output shared
overflow interrupt and 7-stage prescaler with an I/O line
· On-chip crystal and RC oscillator · Bit manipulation instruction
· Watchdog Timer · 14-bit table read instruction
· 2048´14 program memory PROM · 63 powerful instructions
· 64´8 data memory RAM · All instructions in one or two machine
· Supports PFD for sound generation cycles
· HALT function and wake-up feature reduce · Low voltage reset function
power consumption · 18-pin DIP/SOP package

General Description
The device is an 8-bit high performance The program and option memories can be elec-
RISC-like microcontroller designed for multi- trically programmed, making the microcontrol-
ple I/O product applications. The device is par- ler suitable for use in product development.
ticularly suitable for use in products such as
battery charger controllers and A/D applica-
tions. A HALT feature is included to reduce
power consumption.

Rev. 1.40 1 July 18, 2001

 HT46R47

Block Diagram
P A 5 /IN T

In te rru p t
C ir c u it M P r e s c a le r fS Y S
T M R U
S T A C K X P A 4 /T M R
P ro g ra m P ro g ra m IN T C T M R C
R O M C o u n te r
P A 4
P A 3 /P F D
S Y S C L K /4

In s tr u c tio n M
W D T
R e g is te r W D T U
M P M D A T A P r e s c a le r
X
U M e m o ry
X
P W M R C O S C
P D C P O R T D
P D 0 /P W M
P D
In s tr u c tio n M U X
D e c o d e r 4 -C h a n n e l
A /D C o n v e rte r
A L U S T A T U S
P B C P O R T B
T im in g S h ifte r P B 0 /A N 0 ~ P B 3 /A N 3
P B
G e n e ra to r
P A 3 , P A 5
P A 0 ~ P A 2
P A C P O R T A P A 3 /P F D
O p tio n
P A 4 /T M R
O S C 2 O S C 1 A C C L V R P R O M P A
P A 5 /IN T
R E S P A 6 , P A 7
V D D
V S S

Pin Assignment

P A 3 /P F D 1 1 8 P A 4 /T M R
P A 2 2 1 7 P A 5 /IN T
P A 1 3 1 6 P A 6
P A 0 4 1 5 P A 7
P B 3 /A N 3 5 1 4 O S C 2
P B 2 /A N 2 6 1 3 O S C 1
P B 1 /A N 1 7 1 2 V D D
P B 0 /A N 0 8 1 1 R E S
V S S 9 1 0 P D 0 /P W M

H T 4 6 R 4 7
1 8 D IP -A /S O P -A

Rev. 1.40 2 July 18, 2001

 HT46R47

Pin Description
ROM Code
Pin No. Pin Name I/O Description
Option
Bidirectional 8-bit input/output port. Each bit can be
4~2 PA0~PA2 configured as wake-up input by ROM code option.
1 PA3/PFD Pull-high Software instructions determine the CMOS output or
18 PA4/TMR I/O Wake-up Schmitt trigger input with or without pull-high resistor
17 PA5/INT PA3 or PFD (determined by pull-high options: bit option). The PFD,
16, 15 PA6, PA7 TMR and INT are pin-shared with PA3, PA4 and PA5,
respectively.
Bidirectional 4-bit input/output port. Software in-
structions determine the CMOS output, Schmitt trig-
8 PB0/AN0 ger input with or without pull-high resistor
7 PB1/AN1 (determined by pull-high options: bit option) or A/D in-
I/O Pull-high
6 PB2/AN2 put.
5 PB3/AN3 Once a PB line is selected as an A/D input (by using
software control), the I/O function and pull-high
resistor are disabled automatically.
9 VSS ¾ ¾ Negative power supply, ground.
Bidirectional I/O line. Software instructions deter-
Pull-high mine the CMOS output, Schmitt trigger input with or
10 PD0/PWM I/O PD0 or without a pull-high resistor (determined by pull-high
PWM options: bit option). The PWM output function is
pin-shared with PD0 (dependent on PWM options).
11 RES I ¾ Schmitt trigger reset input. Active low.
12 VDD ¾ ¾ Positive power supply
OSC1, OSC2 are connected to an RC network or a
13 OSC1 I Crystal Crystal (determined by ROM code option) for the in-
14 OSC2 O or RC ternal system clock. In the case of RC operation, OSC2
is the output terminal for 1/4 system clock.

Absolute Maximum Ratings

Supply Voltage ...............VSS-0.3V to VSS+5.5V Storage Temperature ................-50°C to 125°C
Input Voltage.................VSS-0.3V to VDD+0.3V Operating Temperature ..............-40°C to 85°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi-
mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo-
sure to extreme conditions may affect device reliability.

Rev. 1.40 3 July 18, 2001

 HT46R47

D.C. Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VDD1 Operating Voltage ¾ fSYS=4MHz 3.3 ¾ 5.5 V
VDD2 Operating Voltage ¾ fSYS=8MHz 4.5 ¾ 5.5 V

Operating Current 3.3V No load, f ¾ 1.3 3 mA

IDD1 SYS=4MHz
(Crystal OSC) 5V ADC disable ¾ 3 5 mA

Operating Current 3.3V No load, f ¾ 1.3 3 mA

IDD2 SYS=4MHz
(RC OSC) 5V ADC disable ¾ 3 5 mA

IDD3 No load, fsys=8MHz

Operating Current 5V ¾ 4 8 mA
ADC disable

Only ADC Enable, 3.3V ¾ 1 2 mA

IADC No load
Others Disable 5V ¾ 2 4 mA

Standby Current 3.3V ¾ ¾ 5 mA

ISTB1 No load, system HALT
(WDT Enabled) 5V ¾ ¾ 10 mA

Standby Current 3.3V ¾ ¾ 1 mA

ISTB2 No load, system HALT
(WDT Disabled) 5V ¾ ¾ 2 mA
VAD A/D Input Voltage ¾ ¾ 0 ¾ VDD V

Input Low Voltage for 3.3V ¾ 0 ¾ 0.3VDD V

VIL1
I/O Ports, TMR and INT 5V ¾ 0 ¾ 0.3VDD V

Input High Voltage for 3.3V ¾ 0.7VDD ¾ VDD V

VIH1
I/O Ports, TMR and INT 5V ¾ 0.7VDD ¾ VDD V

Input Low Voltage 3.3V ¾ 0 ¾ 0.4VDD V

VIL2
(RES) 5V ¾ 0 ¾ 0.4VDD V

Input High Voltage 3.3V ¾ 0.9VDD ¾ VDD V

VIH2
(RES) 5V ¾ 0.9VDD ¾ VDD V
VLVR Low Voltage Reset ¾ ¾ 2.7 3.0 3.3 V
3.3V VOL=0.1VDD 4 8 ¾ mA
IOL I/O Port Sink Current
5V VOL=0.1VDD 10 20 ¾ mA

I/O Port Source 3.3V VOH=0.9VDD -2 -4 ¾ mA

IOH
Current 5V VOH=0.9VDD -5 -10 ¾ mA

Rev. 1.40 4 July 18, 2001

 HT46R47

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
3.3V ¾ 40 60 80 kW
RPH Pull-high Resistance
5V ¾ 10 30 50 kW
EAD A/D Conversion Error 5V ¾ ¾ ±0.5 ±1 LSB

A.C. Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions

System Clock 3.3V ¾ 400 ¾ 4000 kHz

fSYS1
(Crystal OSC) 5V ¾ 400 ¾ 8000 kHz
3.3V ¾ 400 ¾ 4000 kHz
fSYS2 System Clock (RC OSC)
5V ¾ 400 ¾ 8000 kHz
3.3V ¾ 0 ¾ 4000 kHz
fTIMER Timer I/P Frequency (TMR)
5V ¾ 0 ¾ 8000 kHz
tAD A/D Clock Period 5V ¾ 1 ¾ ¾ ms
tADC A/D Conversion Time ¾ ¾ ¾ 76 ¾ tAD
3.3V ¾ 43 86 168 ms
tWDTOSC Watchdog Oscillator
5V ¾ 36 72 144 ms

Watchdog Time-out Period 3.3V 2.8 5.6 11 s

tWDT1 ¾
(RC) 5V 2.3 4.7 9.4 s
Watchdog Time-out Period
tWDT2 ¾ ¾ 217 ¾ 218 tSYS
(System Clock)

tRES External Reset Low Pulse

¾ ¾ 1 ¾ ¾ ms
Width

tSST System Start-up Timer *tSYS

¾ Wake-up from HALT ¾ 1024 ¾
Period
tINT Interrupt Pulse Width ¾ ¾ 1 ¾ ¾ ms

Note: *tSYS=1/fSYS

Rev. 1.40 5 July 18, 2001

 HT46R47

Functional Description
When executing a jump instruction, conditional
Execution flow
skip execution, loading PCL register, subrou-
The system clock for the microcontroller is de- tine call, initial reset, internal interrupt, exter-
rived from either a crystal or an RC oscillator. nal interrupt or return from subroutine, the PC
The system clock is internally divided into four manipulates the program transfer by loading
non-overlapping clocks. One instruction cycle the address corresponding to each instruction.
consists of four system clock cycles.
The conditional skip is activated by instruc-
Instruction fetching and execution are tions. Once the condition is met, the next in-
pipelined in such a way that a fetch takes an in- struction, fetched during the current
struction cycle while decoding and execution instruction execution, is discarded and a
takes the next instruction cycle. However, the dummy cycle replaces it to get the proper in-
pipelining scheme causes each instruction to ef- struction. Otherwise proceed with the next in-
fectively execute in a cycle. If an instruction struction.
changes the program counter, two cycles are re-
The lower byte of the program counter (PCL) is
quired to complete the instruction.
a readable and writeable register (06H).
Moving data into the PCL performs a short
Program counter - PC jump. The destination will be within 256 loca-
The program counter (PC) controls the se- tions.
quence in which the instructions stored in pro- When a control transfer takes place, an addi-
gram PROM are executed and its contents tional dummy cycle is required.
specify full range of program memory.
After accessing a program memory word to fetch Program memory - PROM
an instruction code, the contents of the program
The program memory is used to store the pro-
counter are incremented by one. The program
gram instructions which are to be executed. It
counter then points to the memory word contain-
also contains data, table, and interrupt entries,
ing the next instruction code.
and is organized into 2048´14 bits, addressed
by the program counter and table pointer.

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4
S y s te m C lo c k

O S C 2 ( R C o n ly )

P C P C P C + 1 P C + 2

F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )

Execution flow

Rev. 1.40 6 July 18, 2001

 HT46R47
0 0 0 H
Certain locations in the program memory are D e v ic e In itia liz a tio n P r o g r a m
reserved for special usage:
0 0 4 H
· Location 000H E x te r n a l In te r r u p t S u b r o u tin e

This area is reserved for program initializa- 0 0 8 H

T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
tion. After chip reset, the program always be-
gins execution at location 000H. 0 0 C H
A /D C o n v e r te r In te r r u p t S u b r o u tin e
· Location 004H P ro g ra m
M e m o ry
This area is reserved for the external inter-
rupt service program. If the INT input pin is n 0 0 H
activated, the interrupt is enabled and the L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
stack is not full, the program begins execution
at location 004H.
· Location 008H
7 0 0 H
This area is reserved for the timer/event coun- L o o k - u p T a b le ( 2 5 6 w o r d s )
7 F F H
ter interrupt service program. If a timer inter- 1 4 b its
rupt results from a timer/event counter N o te : n ra n g e s fro m 0 to 7
overflow, and if the interrupt is enabled and the
stack is not full, the program begins execution Program memory
at location 008H.
· Table location
· Location 00CH
Any location in the PROM space can be used
This area is reserved for the A/D converter in- as look-up tables. The instructions "TABRDC
terrupt service program. If an A/D converter [m]" (the current page, 1 page=256 words)
interrupt results from an end of A/D conver- and "TABRDL [m]" (the last page) transfer
sion, and if the interrupt is enabled and the the contents of the lower-order byte to the
stack is not full, the program begins execution specified data memory, and the higher-order
at location 00CH. byte to TBLH (08H). Only the destination of
the lower-order byte in the table is

Program Counter
Mode
*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset 0 0 0 0 0 0 0 0 0 0 0
External Interrupt 0 0 0 0 0 0 0 0 1 0 0
Timer/Event Counter Overflow 0 0 0 0 0 0 0 1 0 0 0
A/D Converter Interrupt 0 0 0 0 0 0 0 1 1 0 0
Skip PC+2
Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program counter
Note: *10~*0: Program counter bits S10~S0: Stack register bits
#10~#0: Instruction code bits @7~@0: PCL bits

Rev. 1.40 7 July 18, 2001

 HT46R47

well-defined, the other bits of the table word a subroutine or an interrupt routine, signaled
are transferred to the lower portion of TBLH, by a return instruction (RET or RETI), the pro-
and the remaining 2 bits are read as "0". The gram counter is restored to its previous value
Table Higher-order byte register (TBLH) is from the stack. After a chip reset, the SP will
read only. The table pointer (TBLP) is a point to the top of the stack.
read/write register (07H), which indicates the If the stack is full and a non-masked interrupt
table location. Before accessing the table, the takes place, the interrupt request flag will be
location must be placed in TBLP. The TBLH recorded but the acknowledgment will be inhib-
is read only and cannot be restored. If the ited. When the stack pointer is decremented (by
main routine and the ISR (Interrupt Service RET or RETI), the interrupt will be serviced.
Routine) both employ the table read instruc- This feature prevents stack overflow allowing
tion, the contents of the TBLH in the main the programmer to use the structure more eas-
routine are likely to be changed by the table ily. In a similar case, if the stack is full and a
read instruction used in the ISR. Errors can "CALL" is subsequently executed, stack over-
occur. In other words, using the table read in- flow occurs and the first entry will be lost (only
struction in the main routine and the ISR si- the most recent 6 return addresses are stored).
multaneously should be avoided. However, if
the table read instruction has to be applied in
Data memory - RAM
both the main routine and the ISR, the inter-
rupt is supposed to be disabled prior to the ta- The data memory is designed with 85´8 bits.
ble read instruction. It will not be enabled The data memory is divided into two func-
until the TBLH has been backed up. All table tional groups: special function registers and
related instructions require two cycles to com- general purpose data memory (64´8). Most are
plete the operation. These areas may function read/write, but some are read only.
as normal program memory depending upon The special function registers include the indi-
the requirements. rect addressing register (00H), timer/event
counter (TMR;0DH), timer/event counter con-
Stack register - STACK trol register (TMRC;0EH), program counter
This is a special part of the memory which is lower-order byte register (PCL;06H), memory
used to save the contents of the program coun- pointer register (MP;01H), accumulator
ter (PC) only. The stack is organized into 6 lev- (ACC;05H), table pointer (TBLP;07H), table
els and is neither part of the data nor part of the higher-order byte register (TBLH;08H), status
program space, and is neither readable nor register (STATUS;0AH), interrupt control reg-
writeable. The activated level is indexed by the ister (INTC;0BH), PWM data register
stack pointer (SP) and is neither readable nor (PWM;1AH), the A/D result lower-order byte
writeable. At a subroutine call or interrupt ac- register (ADRL;20H), the A/D result
knowledgment, the contents of the program higher-order byte register (ADRH;21H), the
counter are pushed onto the stack. At the end of A/D control register (ADCR;22H), the A/D

Table Location
Instruction
*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table location
Note: *10~*0: Table location bits P10~P8: Current program counter bits
@7~@0: Table pointer bits

Rev. 1.40 8 July 18, 2001

 HT46R47

clock setting register (ACSR;23H), I/O regis- All of the data memory areas can handle arith-
ters (PA;12H, PB;14H, PD;18H) and I/O con- metic, logic, increment, decrement and rotate
trol registers (PAC;13H, PBC;15H, PDC;19H). operations directly. Except for some dedicated
The remaining space before the 40H is re- bits, each bit in the data memory can be set and
served for future expanded usage and reading reset by "SET [m].i" and "CLR [m].i". They are
these locations will get "00H". The general also indirectly accessible through memory
purpose data memory, addressed from 40H to pointer register (MP;01H).
7FH, is used for data and control information
under instruction commands. Indirect addressing register

0 0 H In d ir e c t A d d r e s s in g R e g is te r Location 00H is an indirect addressing register

0 1 H M P that is not physically implemented. Any
0 2 H read/write operation of [00H] accesses data mem-
0 3 H ory pointed to by MP (01H). Reading location 00H
0 4 H itself indirectly will return the result 00H. Writ-
A C C
0 5 H ing indirectly results in no operation.
0 6 H P C L
0 7 H T B L P The memory pointer register MP (01H) is a 7-bit
0 8 H T B L H register. The bit 7 of MP is undefined and reading
0 9 H will return the result ²1². Any writing operation to
0 A H S T A T U S MP will only transfer the lower 7-bit data to MP.
0 B H IN T C S p e c ia l P u r p o s e
0 C H D A T A M E M O R Y
Accumulator
0 D H T M R
0 E H T M R C The accumulator is closely related to ALU oper-
0 F H ations. It is also mapped to location 05H of the
1 0 H data memory and can carry out immediate data
1 1 H operations. The data movement between two
1 2 H P A
data memory locations must pass through the
1 3 H P A C
accumulator.
1 4 H P B
1 5 H P B C
1 6 H Arithmetic and logic unit - ALU
1 7 H This circuit performs 8-bit arithmetic and logic
1 8 H P D
: U n u s e d
operations. The ALU provides the following func-
1 9 H P D C
1 A H P W M
tions:
R e a d a s "0 0 "
1 B H · Arithmetic operations (ADD, ADC, SUB,
1 C H SBC, DAA)
1 D H
· Logic operations (AND, OR, XOR, CPL)
1 E H
1 F H · Rotation (RL, RR, RLC, RRC)
2 0 H A D R L · Increment and Decrement (INC, DEC)
2 1 H A D R H · Branch decision (SZ, SNZ, SIZ, SDZ ....)
2 2 H A D C R
2 3 H A C S R The ALU not only saves the results of a data op-
2 4 H eration but also changes the status register.
3 F H
4 0 H Status register - STATUS
G e n e ra l P u rp o s e
D A T A M E M O R Y This 8-bit register (0AH) contains the zero flag
(6 4 B y te s )
(Z), carry flag (C), auxiliary carry flag (AC),
7 F H
overflow flag (OV), power down flag (PD), and
RAM mapping watchdog time-out flag (TO). It also records the

Rev. 1.40 9 July 18, 2001

 HT46R47

status information and controls the operation ternal timer/event counter interrupt and A/D
sequence. converter interrupts. The Interrupt Control
With the exception of the TO and PD flags, Register (INTC;0BH) contains the interrupt
bits in the status register can be altered by control bits to set the enable/disable and the in-
instructions like most other registers. Any terrupt request flags.
data written into the status register will not Once an interrupt subroutine is serviced, all
change the TO or PD flag. In addition opera- the other interrupts will be blocked (by clearing
tions related to the status register may give the EMI bit). This scheme may prevent any fur-
different results from those intended. The ther interrupt nesting. Other interrupt re-
TO flag can be affected only by system quests may happen during this interval but
power-up, a WDT time-out or executing the only the interrupt request flag is recorded. If a
"CLR WDT" or "HALT" instruction. The PD certain interrupt requires servicing within the
flag can be affected only by executing the service routine, the EMI bit and the correspond-
"HALT" or "CLR WDT" instruction or a sys- ing bit of INTC may be set to allow interrupt
tem power-up. nesting. If the stack is full, the interrupt request
The Z, OV, AC and C flags generally reflect the will not be acknowledged, even if the related in-
status of the latest operations. terrupt is enabled, until the SP is decremented.
If immediate service is desired, the stack must
In addition, on entering the interrupt sequence be prevented from becoming full.
or executing the subroutine call, the status reg-
ister will not be pushed onto the stack automat- All these kinds of interrupts have a wake-up ca-
ically. If the contents of the status are pability. As an interrupt is serviced, a control
important and if the subroutine can corrupt the transfer occurs by pushing the program counter
status register, precautions must be taken to onto the stack, followed by a branch to a sub-
save it properly. routine at specified location in the program
memory. Only the program counter is pushed
Interrupt onto the stack. If the contents of the register or
status register (STATUS) are altered by the in-
The device provides an external interrupt, in- terrupt service program which corrupts the de-
Labels Bits Function
C is set if the operation results in a carry during an addition operation or if a bor-
C 0 row does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC is set if the operation results in a carry out of the low nibbles in addition or no
AC 1 borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
Z 2
cleared.
OV is set if the operation results in a carry into the highest-order bit but not a
OV 3
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD is cleared by system power-up or executing the "CLR WDT" instruction. PD
PD 4
is set by executing the "HALT" instruction.
TO is cleared by system power-up or executing the "CLR WDT" or "HALT" in-
TO 5
struction. TO is set by a WDT time-out.
¾ 6, 7 Unused bit, read as "0"
Status register

Rev. 1.40 10 July 18, 2001

 HT46R47

sired control sequence, the contents should be cleared to disable further interrupts.
saved in advance. During the execution of an interrupt subroutine,
External interrupts are triggered by a high to other interrupt acknowledgments are held until
low transition of INT and the related interrupt the "RETI" instruction is executed or the EMI
request flag (EIF; bit 4 of INTC) will be set. bit and the related interrupt control bit are set to
When the interrupt is enabled, the stack is not 1 (of course, if the stack is not full). To return
full and the external interrupt is active, a sub- from the interrupt subroutine, "RET" or "RETI"
routine call to location 04H will occur. The in- may be invoked. RETI will set the EMI bit to en-
terrupt request flag (EIF) and EMI bits will be able an interrupt service, but RET will not.
cleared to disable other interrupts. Interrupts, occurring in the interval between
The internal timer/event counter interrupt is the rising edges of two consecutive T2 pulses,
initialized by setting the timer/event counter will be serviced on the latter of the two T2
interrupt request flag (TF; bit 5 of INTC), pulses, if the corresponding interrupts are en-
caused by a timer overflow. When the interrupt abled. In the case of simultaneous requests the
is enabled, the stack is not full and the TF bit is following table shows the priority that is ap-
set, a subroutine call to location 08H will occur. plied. These can be masked by resetting the
The related interrupt request flag (TF) will be EMI bit.
reset and the EMI bit cleared to disable further
No. Interrupt Source Priority Vector
interrupts.
a External Interrupt 1 04H
The A/D converter interrupt is initialized by
setting the A/D converter request flag (ADF; bit Timer/event
b 2 08H
6 of INTC), caused by an end of A/D conversion. Counter Overflow
When the interrupt is enabled, the stack is not A/D Converter
full and the ADF is set, a subroutine call to loca- c 3 0CH
Interrupt
tion 0CH will occur. The related interrupt re-
quest flag (ADF) will be reset and the EMI bit The timer/event counter interrupt request flag
(TF), external interrupt request flag (EIF), A/D
Register Bit No. Label Function
Controls the master (global) interrupt
0 EMI
(1= enabled; 0= disabled)
Controls the external interrupt
1 EEI
(1= enabled; 0= disabled)
Controls the timer/event counter interrupt
2 ETI
(1= enabled; 0= disabled)
Controls the A/D converter interrupt
INTC 3 EADI
(1= enabled; 0= disabled)
(0BH)
External interrupt request flag
4 EIF
(1= active; 0= inactive)
Internal timer/event counter request flag
5 TF
(1= active; 0= inactive)
A/D converter request flag
6 ADF
(1= active; 0= inactive)
7 ¾ Unused bit, read as "0"

INTC register

Rev. 1.40 11 July 18, 2001

 HT46R47

c o n v e r t er r eq ues t f l a g ( AD F ) , e n a b l e mode stops the system oscillator and ignores an

timer/event counter bit (ETI), enable external external signal to conserve power.
interrupt bit (EEI), enable A/D converter inter- If an RC oscillator is used, an external resistor
rupt bit (EADI) and enable master interrupt bit between OSC1 and VSS is required and the re-
(EMI) constitute an interrupt control register sistance must range from 30kW to 750kW. The
(INTC) which is located at 0BH in the data system clock, divided by 4, is available on
memory. EMI, EEI, ETI, EADI are used to con- OSC2, which can be used to synchronize exter-
trol the enabling/disabling of interrupts. These nal logic. The RC oscillator provides the most
bits prevent the requested interrupt from being cost effective solution. However, the frequency
serviced. Once the interrupt request flags (TF, of oscillation may vary with VDD, tempera-
EIF, ADF) are set, they will remain in the INTC tures and the chip itself due to process varia-
register until the interrupts are serviced or tions. It is, therefore, not suitable for timing
cleared by a software instruction. sensitive operations where an accurate oscilla-
tor frequency is desired.
It is recommended that a program does not
use the "CALL subroutine" within the inter- If the Crystal oscillator is used, a crystal across
rupt subroutine. Interrupts often occur in an OSC1 and OSC2 is needed to provide the feed-
unpredictable manner or need to be serviced back and phase shift required for the oscillator,
immediately in some applications. If only one and no other external components are required.
stack is left and enabling the interrupt is not Instead of a crystal, a resonator can also be con-
well controlled, the original control sequence will nected between OSC1 and OSC2 to get a fre-
be damaged once the "CALL" operates in the in- quency reference, but two external capacitors
terrupt subroutine. in OSC1 and OSC2 are required (If the oscillat-
ing frequency is less than 1MHz).
Oscillator configuration The WDT oscillator is a free running on-chip RC
There are two oscillator circuits in the oscillator, and no external components are re-
microcontroller. quired. Even if the system enters the power down
mode, the system clock is stopped, but the WDT
O S C 1 O S C 1 oscillator still works with a period of approxi-
mately 72ms/5V. The WDT oscillator can be dis-
abled by ROM code option to conserve power.
O S C 2 fS Y S /4 O S C 2
N M O S O p e n D r a in
C r y s ta l O s c illa to r R C O s c illa to r Watchdog Timer - WDT
The clock source of WDT is implemented by a
System oscillator dedicated RC oscillator (WDT oscillator) or in-
struction clock (system clock divided by 4), de-
Both are designed for system clocks, namely
cided by ROM code option. This timer is
the RC oscillator and the Crystal oscillator,
designed to prevent a software malfunction or
which are determined by the ROM code option. sequence from jumping to an unknown location
No matter what oscillator type is selected, the with unpredictable results. The Watchdog
signal provides the system clock. The HALT

S y s te m C lo c k /4
R O M W D T P r e s c a le r
C o d e fs W D T T im e - o u t
8 - b it C o u n te r 7 - b it C o u n te r T T 1 5 1 6
O p tio n fs/2 ~ fs/2
W D T S e le c t
O S C C L R W D T

Watchdog Timer

Rev. 1.40 12 July 18, 2001

 HT46R47

Timer can be disabled by a ROM code option. If · The contents of the on chip RAM and regis-
the Watchdog Timer is disabled, all the execu- ters remain unchanged.
tions related to the WDT result in no operation. · WDT will be cleared and recounted again (if
Once the internal oscillator (RC oscillator with the WDT clock is from the WDT oscillator).
a period of 72ms/5V normally) is selected, it is · All of the I/O ports maintain their original sta-
first divided by 256 (8-stage) to get the nominal tus.
time-out period of approximately 18.6ms/5V. · The PD flag is set and the TO flag is cleared.
This time-out period may vary with tempera-
tures, VDD and process variations. By invoking The system can leave the HALT mode by means
the WDT prescaler, longer time-out periods can of an external reset, an interrupt, an external
be realized and the maximum time-out period falling edge signal on port A or a WDT overflow.
is 2.3s/5V~4.7s/5V seconds. If the WDT oscilla- An external reset causes a device initialization
tor is disabled, the WDT clock may still come and the WDT overflow performs a ²warm re-
from the instruction clock and operate in the set². After the TO and PD flags are examined,
same manner except that in the HALT state the the reason for chip reset can be determined.
WDT may stop counting and lose its protecting The PD flag is cleared by system power-up or
purpose. In this situation the logic can only be executing the ²CLR WDT² instruction and is
restarted by external logic. set when executing the ²HALT² instruction.
If the device operates in a noisy environment, us- The TO flag is set if the WDT time-out occurs,
ing the on-chip RC oscillator (WDT OSC) is and causes a wake-up that only resets the PC
strongly recommended, since the HALT will stop and SP; the others keep their original status.
the system clock. The port A wake-up and interrupt methods can
The WDT overflow under normal operation will be considered as a continuation of normal exe-
initialize ²chip reset² and set the status bit cution. Each bit in port A can be independently
²TO². But in the HALT mode, the overflow will selected to wake up the device by the ROM code
initialize a ²warm reset², and only the PC and option. Awakening from an I/O port stimulus,
SP are reset to zero. To clear the contents of the program will resume execution of the next
WDT, three methods are adopted; external re- instruction. If it is awakening from an inter-
set (a low level to RES), software instruction rupt, two sequences may happen. If the related
and a "HALT" instruction. The software in- interrupt is disabled or the interrupt is enabled
struction include ²CLR WDT² and the other set but the stack is full, the program will resume
- ²CLR WDT1² and ²CLR WDT2². Of these two execution at the next instruction. If the inter-
types of instruction, only one can be active de- rupt is enabled and the stack is not full, the reg-
pending on the ROM code option - ²CLR WDT ular interrupt response takes place. If an
times selection option². If the ²CLR WDT² is se- interrupt request flag is set to ²1² before enter-
lected (i.e. CLRWDT times equal one), any exe- ing the HALT mode, the wake-up function of
cution of the ²CLR WDT² instruction will clear the related interrupt will be disabled. Once a
the WDT. In the case that ²CLR WDT1² and wake-up event occurs, it takes 1024 tSYS (sys-
²CLR WDT2² are chosen (i.e. CLRWDT times tem clock period) to resume normal operation.
equal two), these two instructions must be exe- In other words, a dummy period will be inserted
cuted to clear the WDT; otherwise, the WDT after wake-up. If the wake-up results from an
may reset the chip as a result of time-out. interrupt acknowledgment, the actual inter-
rupt subroutine execution will be delayed by
one or more cycles. If the wake-up results in the
Power down operation - HALT
next instruction execution, this will be executed
The HALT mode is initialized by the ²HALT² immediately after the dummy period is fin-
instruction and results in the following... ished.
· The system oscillator will be turned off but To minimize power consumption, all the I/O
the WDT oscillator keeps running (if the pins should be carefully managed before enter-
WDT oscillator is selected). ing the HALT status.

Rev. 1.40 13 July 18, 2001

 HT46R47

Reset V D D

There are three ways in which a reset can occur:

· RES reset during normal operation
· RES reset during HALT
R E S
· WDT time-out reset during normal operation
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a ²warm reset² that resets only the PC
and SP, leaving the other circuits in their origi- Reset circuit
nal state. Some registers remain unchanged
during other reset conditions. Most registers H A L T W a rm R e s e t
are reset to the ²initial condition² when the re-
W D T
set conditions are met. By examining the PD
and TO flags, the program can distinguish be-
R E S
tween different ²chip resets².
C o ld
TO PD RESET Conditions R e s e t
S S T
O S C 1 1 0 - b it R ip p le
0 0 RES reset during power-up C o u n te r

u u RES reset during normal operation

S y s te m R e s e t
0 1 RES wake-up HALT
WDT time-out during normal opera- Reset configuration
1 u
tion
The functional unit chip reset status are shown
1 1 WDT wake-up HALT below.

Note: ²u² means ²unchanged² PC 000H

To guarantee that the system oscillator is Interrupt Disable
started and stabilized, the SST (System Clear. After master reset,
WDT
Start-up Timer) provides an extra-delay of WDT begins counting
1024 system clock pulses when the system reset Timer/Event
(power-up, WDT time-out or RES reset) or the Off
Counter
system awakes from the HALT state.
Input/output
When a system reset occurs, the SST delay is Input mode
Ports
added during the reset period. Any wake-up
from HALT will enable the SST delay. Points to the top of the
SP
stack

V D D

R E S
tS S T

S S T T im e - o u t

C h ip R e s e t

Reset timing chart

Rev. 1.40 14 July 18, 2001

 HT46R47

The registers¢ states are summarized in the following table.

WDT Time-out RES Reset WDT
Reset RES Reset
Register (Normal (Normal Time-out
(Power On) (HALT)
Operation) Operation) (HALT)*
TMR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMRC 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu
Program
000H 000H 000H 000H 000H
Counter
MP -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu
STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu
INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu
PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PB ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu
PBC ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu
PD ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u
PDC ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u
PWM xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
ADRL x--- ---- x--- ---- x--- ---- x--- ---- u--- ----
ADRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu
ACSR 1--- --00 1--- --00 1--- --00 1--- --00 u---- --uu

Note: ²*² stands for ²warm reset²

²u² stands for ²unchanged²
²x² stands for ²unknown²

Rev. 1.40 15 July 18, 2001

 HT46R47

Timer/Event Counter measure time intervals or pulse widths, or to

A timer/event counter (TMR) is implemented in generate an accurate time base.
the microcontroller. The timer/event counter There are 2 registers related to the timer/event
contains an 8-bit programmable count-up coun- counter; TMR ([0DH]), TMRC ([0EH]). Two phys-
ter and the clock may come from an external ical registers are mapped to TMR location; writ-
source or the system clock. ing TMR makes the starting value be placed in
Using the internal system clock, there is only the timer/event counter preload register and
one reference time-base. The internal clock reading TMR gets the contents of the timer/event
source comes from fSYS. The external clock in- counter. The TMRC is a timer/event counter con-
put allows the user to count external events, trol register, which defines some options.

Label (TMRC) Bits Function

To define the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
PSC0~PSC2 0~2 011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
To define the TMR active edge of timer/event counter
TE 3
(0=active on low to high; 1=active on high to low)
To enable/disable timer counting
TON 4
(0=disabled; 1=enabled)
¾ 5 Unused bit, read as ²0²
To define the operating mode
01=Event count mode (external clock)
TM0 6
10=Timer mode (internal clock)
TM1 7
11=Pulse width measurement mode
00=Unused

TMRC register

P W M

(6 + 2 ) c o m p a re to P D 0 c ir c u it

fS Y S 8 - s ta g e p r e s c a le r
f IN T D a ta B u s
8 -1 M U X
T M 1
T M 0 T im e r /E v e n t C o u n te r R e lo a d
P S C 2 ~ P S C 0 T M R P r e lo a d R e g is te r

T E

P u ls e W id th T im e r /E v e n t O v e r flo w
T M 1 M e a s u re m e n t C o u n te r
T M 0 to In te rru p t
M o d e C o n tro l
T O N
1 /2 P F D

Timer/Event Counter

Rev. 1.40 16 July 18, 2001

 HT46R47

The TM0, TM1 bits define the operating mode. counter is turned on, data written to it will only
The event count mode is used to count external be kept in the timer/event counter preload reg-
events, which means the clock source comes from ister. The timer/event counter will still operate
an external (TMR) pin. The timer mode functions until overflow occurs. When the timer/event
as a normal timer with the clock source coming counter (reading TMR) is read, the clock will be
from the fINT clock. The pulse width measurement blocked to avoid errors. As clock blocking may re-
mode can be used to count the high or low level du- sults in a counting error, this must be taken into
ration of the external signal (TMR). The counting consideration by the programmer.
is based on the fINT. The bit0~bit2 of the TMRC can be used to de-
In the event count or timer mode, once the fine the pre-scaling stages of the internal clock
timer/event counter starts counting, it will count sources of timer/event counter. The definitions
from the current contents in the timer/event are as shown. The overflow signal of
counter to FFH. Once overflow occurs, the coun- timer/event counter can be used to generate the
ter is reloaded from the timer/event counter PFD signal. The timer prescaler is also used as
preload register and generates the interrupt re- the PWM counter.
quest flag (TF; bit 5 of INTC) at the same time.
In the pulse width measurement mode with Input/output ports
the TON and TE bits equal to one, once the There are 13 bidirectional input/output lines in
TMR has received a transient from low to high the microcontroller, labeled as PA, PB and PD,
(or high to low if the TE bits is ²0²) it will start which are mapped to the data memory of [12H],
counting until the TMR returns to the original [14H] and [18H] respectively. All of these I/O
level and resets the TON. The measured result ports can be used for input and output opera-
will remain in the timer/event counter even if tions. For input operation, these ports are
the activated transient occurs again. In other non-latching, that is, the inputs must be ready at
words, only one cycle measurement can be the T2 rising edge of instruction ²MOV A,[m]²
done. Until setting the TON, the cycle measure- (m=12H, 14H or 18H). For output operation, all
ment will function again as long as it receives the data is latched and remains unchanged until
further transient pulse. Note that, in this oper- the output latch is rewritten.
ating mode, the timer/event counter starts Each I/O line has its own control register (PAC,
counting not according to the logic level but ac- PBC, PDC) to control the input/output configu-
cording to the transient edges. In the case of ration. With this control register, CMOS output
counter overflows, the counter is reloaded from or Schmitt trigger input with or without
the timer/event counter preload register and is- pull-high resistor structures can be reconfig-
sues the interrupt request just like the other ured dynamically (i.e. on-the-fly) under soft-
two modes. To enable the counting operation, ware control. To function as an input, the
the timer ON bit (TON; bit 4 of TMRC) should corresponding latch of the control register must
be set to 1. In the pulse width measurement write ²1². The input source also depends on the
mode, the TON will be cleared automatically af- control register. If the control register bit is ²1²,
ter the measurement cycle is completed. But in the input will read the pad state. If the control
the other two modes the TON can only be reset register bit is ²0², the contents of the latches
by instructions. The overflow of the timer/event will move to the internal bus. The latter is pos-
counter is one of the wake-up sources. No mat-
sible in the ²read-modify-write² instruction.
ter what the operation mode is, writing a 0 to
ETI can disable the interrupt service. For output function, CMOS is the only configu-
ration. These control registers are mapped to
In the case of timer/event counter OFF condi-
locations 13H, 15H and 19H.
tion, writing data to the timer/event counter
preload register will also reload that data to After a chip reset, these input/output lines re-
the timer/event counter. But if the timer/event main at high levels or floating state (dependent

Rev. 1.40 17 July 18, 2001

 HT46R47

on pull-high options). Each bit of these in- erated by timer/event counter overflow signal.
put/output latches can be set or cleared by ²SET The input mode always remaining its original
[m].i² and ²CLR [m].i² (m=12H, 14H or 18H) in- functions. Once the PFD option is selected, the
structions. PFD output signal is controlled by PA3 data
Some instructions first input data and then fol- register only. Writing ²1² to PA3 data register
low the output operations. For example, ²SET will enable the PFD output function and writ-
[m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read ing ²0² will force the PA3 to remain at ²0². The
the entire port states into the CPU, execute the I/O functions of PA3 are shown below.
defined operations (bit-operation), and then I/O I/P O/P I/P O/P
write the results back to the latches or the accu- Mode (Normal) (Normal) (PFD) (PFD)
mulator. Logical Logical Logical PFD
PA3
Each line of port A has the capability of wak- Input Output Input (Timer on)
ing-up the device. The highest 4-bit of port B and
7 bits of port D are not physically implemented; Note: The PFD frequency is the timer/event
on reading them a ²0² is returned whereas writ- counter overflow frequency divided by 2.
ing then results in a no-operation. See Applica- The PA5 and PA4 are pin-shared with INT and
tion note. TMR pins respectively.
Each I/O line has a pull-high option. Once the The PB can also be used as A/D converter in-
pull-high option is selected, the I/O line has a puts. The A/D function will be described later.
pull-high resistor, otherwise, there¢s none. There is a PWM function shared with PD0. If
Take note that a non-pull-high I/O line operat- the PWM function is enabled, the PWM signal
ing in input mode will cause a floating state. will appear on PD0 (if PD0 is operating in out-
The PA3 is pin-shared with the PFD signal. If put mode). The I/O functions of PD0 are as
the PFD option is selected, the output signal in shown.
output mode of PA3 will be the PFD signal gen-
V D D

C o n tr o l B it P U
D a ta B u s D Q

W r ite C o n tr o l R e g is te r C K Q B
C h ip R e s e t S P A 0 ~ P A 2
P A 3 /P F D
P A 4 /T M R
R e a d C o n tr o l R e g is te r P A 5 /IN T
D a ta B it P A 6 , P A 7
D Q P B 0 /A N 0 ~ P B 3 /A N 3
P D 0 /P W M
W r ite D a ta R e g is te r C K Q B
S
M
P A 3 U
(P D 0 o r P W M ) X
P F D
P F D E N
M (P A 3 )
U
X
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly ) O P 0 ~ O P 7
IN T fo r P A 5 O n ly
T M R fo r P A 4 O n ly
Input/output ports

Rev. 1.40 18 July 18, 2001

 HT46R47

I/O I/P O/P I/P O/P In a PWM cycle, the duty cycle of each modula-
Mode (Normal) (Normal) (PWM) (PWM) tion cycle is shown in the table.
Logical Logical Logical Parameter AC (0~3) Duty Cycle
PD0 PWM
Input Output Input DC + 1
i<AC
It is recommended that unused or not bonded Modulation cycle i 64
out I/O lines should be set as output pins by (i=0~3) DC
software instruction to avoid consuming power i³AC
64
under input floating state.
The modulation frequency, cycle frequency and
PWM cycle duty of the PWM output signal are sum-
The microcontroller provides 1 channel (6+2) marized in the following table.
bits PWM output shared with PD0. The PWM PWM
channel has its data register denoted as PWM PWM Cycle PWM Cycle
Modulation
(1AH). The frequency source of the PWM coun- Frequency Duty
Frequency
ter comes from fSYS. The PWM register is an
eight bits register. The waveforms of PWM out- fSYS/64 fSYS/256 [PWM]/256
put are as shown. Once the PD0 is selected as
the PWM output and the output function of A/D converter
PD0 is enabled (PDC.0=²0²), writing 1 to PD0 The 4 channels and 9-bit resolution A/D (8-bit
data register will enable the PWM output func- accuracy) converter are implemented in this
tion and writing ²0² will force the PD0 to stay microcontroller. The reference voltage is VDD.
at ²0². The A/D converter contains 4 special registers
A PWM cycle is divided into four modulation cy- which are; ADRL (20H), ADRH (21H), ADCR
cles (modulation cycle 0~modulation cycle 3). (22H) and ACSR (23H). The ADRH and ADRL
Each modulation cycle has 64 PWM input clock are A/D result register higher-order byte and
period. In a (6+2) bit PWM function, the con- lower-order byte and are read-only. After the
tents of the PWM register is divided into two A/D conversion is completed, the ADRH and
groups. Group 1 of the PWM register is denoted ADRL should be read to get the conversion re-
by DC which is the value of PWM.7~PWM.2. sult data. The ADCR is an A/D converter con-
The group 2 is denoted by AC which is the value trol register, which defines the A/D channel
of PWM.1~PWM.0. number, analog channel select, start A/D con-
fS Y S /2

[P W M ] = 1 0 0

P W M
2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4
[P W M ] = 1 0 1

P W M
2 6 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4
[P W M ] = 1 0 2

P W M
2 6 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4
[P W M ] = 1 0 3

P W M
2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 6 /6 4
P W M m o d u la tio n p e r io d : 6 4 /fS Y S

P W M c y c le : 2 5 6 /fS Y S

PWM

Rev. 1.40 19 July 18, 2001

 HT46R47

version control bit and the end of A/D conver- PB line is selected as an analog input, the I/O
sion flag. If the users want to start an A/D functions and pull-high resistor of this I/O line
conversion, define PB configuration, select the are disabled, and the A/D converter circuit is
converted analog channel, and give START bit power on. The EOC bit (bit6 of the ADCR) is
a raising edge and a falling edge (0®1®0). At end of A/D conversion flag. Check this bit to
the end of A/D conversion, the EOC bit is know when A/D conversion is completed. The
cleared and an A/D converter interrupt occurs START bit of the ADCR is used to begin the
(if the A/D converter interrupt is enabled). The conversion of A/D converter. Give START bit a
ACSR is A/D clock setting register, which is raising edge and falling edge that means the
used to select the A/D clock source. A/D conversion has started. In order to ensure
The A/D converter control register is used to the A/D conversion is completed, the START
control the A/D converter. The bit2~bit0 of the should stay at ²0² until the EOC is cleared to
ADCR are used to select an analog input chan- ²0² (end of A/D conversion).
nel. There are a total of four channels to select. The bit 7 of the ACSR is used for testing pur-
The bit5~bit3 of the ADCR are used to set PB pose only. It can not be used for the users. The
configurations. PB can be an analog input or as bit1 and bit0 of the ACSR are used to select A/D
digital I/O line decided by these 3 bits. Once a clock sources.

Label (ADCR) Bits Function

ACS2, ACS1, ACS0: Select A/D channel
0, 0, 0: AN0
ACS0 0
0, 0, 1: AN1
ACS1 1
0, 1, 0: AN2
ACS2 2
0, 1, 1: AN3
1, X, X: undefined, cannot be used
PCR2, PCR1, PCR0: PB3~PB0 configurations
0, 0, 0: PB3 PB2 PB1 PB0 (The ADC circuit is power off to reduce
PCR0 3 power consumption.)
PCR1 4 0, 0, 1: PB3 PB2 PB1 AN0
PCR2 5 0, 1, 0: PB3 PB2 AN1 AN0
0, 1, 1: PB3 AN2 AN1 AN0
1, x, x: AN3 AN2 AN1 AN0
End of A/D conversion flag.
EOC 6
(0: end of A/D conversion)
Start the A/D conversion
START 7 0®1®0: Start
0®1: Reset A/D converter and set EOC to ²1²

Bits Function
ADCS1, ADCS0: Select the A/D converter clock source.
0, 0: fSYS/2
ADCS0 0
0, 1: fSYS/8
ADCS1 1
1, 0: fSYS/32
1, 1: Undefined, cannot be used.
¾ 2~6 Unused bit, read as ²0².
TEST 7 For internal test only.

Rev. 1.40 20 July 18, 2001

 HT46R47

When the A/D conversion is completed, the A/D · The LVR uses the ²OR² function with the exter-
interrupt request flag is set. The EOC bit is set nal RES signal to perform chip reset.
to ²1² when the START bit is set from ²0² to ²1². The relationship between VDD and VLVR is
Bit Bit Bit Bit Bit Bit Bit Bit shown below.
Register
7 6 5 4 3 2 1 0
V D D V O P R
ADRL D0 ¾ ¾ ¾ ¾ ¾ ¾ ¾ 5 .5 V 5 .5 V
ADRH D8 D7 D6 D5 D4 D3 D2 D1

* D0~D8 is A/D conversion result data bit

LSB~MSB.
V L V R

3 .3 V
Low voltage reset - LVR
3 .0 V
The microcontroller provides low voltage reset
circuit in order to monitor the supply voltage of
the device. If the supply voltage of the device is
within the range 0.9V~3.3V, such as changing a 0 .9 V
battery, the LVR will automatically reset the Note: VOPR is the voltage range for proper chip
device internally. operation at 4MHz system clock.
The LVR includes the following specifications:
· The low voltage (0.9V~3.3V) has to remain in
their original state to exceed 1ms. If the low
voltage state does not exceed 1ms, the LVR
will ignore it and do not perform a reset func-
tion.

S T A R T

E O C

*7 6 T A D *7 6 T A D

P C R 0 ~ P C R 2 0 0 0 B 1 0 0 B 1 0 0 B 0 0 0 B

A C S 0 ~ A C S 2 0 0 0 B 0 1 0 B 0 0 0 B **X X X B

P o w e r S ta rt o f A /D S ta rt o f A /D 1 : A ll P B lin e is d ig ita l in p u t
O n c o n v e r s io n c o n v e r s io n
R e s e t 2 : A /D c o n v e r te r is p o w e r o ff
R e s e t A /D R e s e t A /D to r e d u c e p o w e r c o n s u m p tio n
c o n v e rte r c o n v e rte r
1 : D e fin e P B c o n fig u r a tio n E n d o f A /D E n d o f A /D
2 : S e le c t a n a lo g c h a n n e l c o n v e rte r c o n v e rte r
***3 : S e le c t A D C c lo c k
(E x a m p le : 4 c h a n n e l, A N 2 ,
fS Y S /8 )

N o te : " * " A /D c o n v e r tin g tim e is 7 6 T A D

" * * " X X X B m e a n s d o n 't c a r e
" * * * " A D C c lo c k m u s t b e fS Y S /2 , fS Y S /8 , fS Y S /3 2

Rev. 1.40 21 July 18, 2001

 HT46R47

V D D

5 .5 V

V L V R L V R D e te c t V o lta g e

0 .9 V

0 V

R e s e t S ig n a l

R e s e t N o r m a l O p e r a tio n R e s e t

*1 *2

Low voltage reset

Note: *1:To make sure that the system oscillator has stabilized, the SST provides an extra delay of
1024 system clock pulses before entering the normal operation.
*2:Since the low voltage has to maintain in its original state and exceed 1ms, therefore 1ms
delay enter the reset mode.

ROM code option

The following table shows all kinds of ROM code option in the microcontroller. All of the ROM code
options must be defined to ensure proper system functioning.
Items Option
1 WDT clock source: WDTOSC/fTID
2 WDT enable/disable: enable/disable
CLRWDT instruction(s)
3 : one/two clear WDT
instruction(s)
4 System oscillator: RC/Crystal
Pull-high resistors (PA, PB, PD):
5
none/pull-high
6 PWM enable/disable
7 PA0~PA7 wake-up: disable/enable
8 PFD enable/disable
9 Lock: unlock/lock
10 Low voltage reset selection: Enable or disable LVR function.

Rev. 1.40 22 July 18, 2001

 HT46R47

Application Circuits

Battery charger for 1-set battery charger applications

P A 0 , P A 1 1 2 V
O S C 1
P A 3 /P F D
O S C
C ir c u it P A 4 /T M R
P A 5 /IN T
O S C 2
S e e b e lo w P A 6 , P A 7

5 V H T 4 6 R 4 7 5 V
P D 0 /P W M
V D D
1 0 0 k W V R t
P B 0 /A N 0
0 .1 m F V b a t
R E S P B 1 /A N 1
0 .1 m F
V S S
P A 2
If
P B 2 /A N 2
P B 3 /A N 3

N o te : T h e r e s is ta n c e a n d c a p a c ita n c e fo r r e s e t c ir c u it s h o u ld b e d e s ig n e d
to e n s u r e th a t th e V D D is s ta b le a n d r e m a in s in a v a lid r a n g e o f th e
o p e r a tin g v o lta g e b e fo r e b r in g in g R E S to h ig h .
V b a t: 3 .6 V ( N iC d , N iM H ) o r 4 .1 V ( L i+ )

Rev. 1.40 23 July 18, 2001

 HT46R47

Battery charger for 2-set battery charger applications

1 2 V

O S C 1 P A 0
O S C P A 3 /P F D
C ir c u it P A 4 /T M R
O S C 2 P A 5 /IN T
S e e b e lo w
P D 0 /P W M
5 V

V D D
H T 4 6 R 4 7
1 0 0 k W C H 0
P A 6
0 .1 m F R E S
0 .1 m F C H 1
P A 7
V S S V b a t0
P B 0 /A N 0
V b a t1

P B 1 /A N 1

P B 3 /A N 3 P A 1
P A 2
If
P B 2 /A N 2

V D D

2 7 0 p F
O S C 1 R C s y s te m o s c illa to r
R O S C 3 0 k W < R O S C < 7 5 0 k W
fS Y S /4
O S C 2

O S C 1
C 1 C r y s ta l s y s te m o s c illa to r
C 1 = C 2 = 3 0 0 p F , if fS Y S < 1 M H z
O S C 2 O th e r w is e , C 1 = C 2 = 0
C 2

V b a t0 , V b a t1 : 3 .6 V ( N iC d , N iM H ) o r 4 .1 V ( L i+ )

Rev. 1.40 24 July 18, 2001

 HT46R47

Instruction Set Summary

Instruction Flag
Mnemonic Description
Cycle Affected
Arithmetic
ADD A,[m] Add data memory to ACC 1 Z,C,AC,OV
ADDM A,[m] Add ACC to data memory 1(1) Z,C,AC,OV
ADD A,x Add immediate data to ACC 1 Z,C,AC,OV
ADC A,[m] Add data memory to ACC with carry 1 Z,C,AC,OV
ADCM A,[m] Add ACC to register with carry 1(1) Z,C,AC,OV
SUB A,x Subtract immediate data from ACC 1 Z,C,AC,OV
SUB A,[m] Subtract data memory from ACC 1 Z,C,AC,OV
SUBM A,[m] Subtract data memory from ACC with result in data 1(1) Z,C,AC,OV
memory
1
SBC A,[m] Subtract data memory from ACC with carry Z,C,AC,OV
1(1)
SBCM A,[m] Subtract data memory from ACC with carry and result Z,C,AC,OV
in data memory
DAA [m] Decimal adjust ACC for addition with result in data 1(1) C
memory
Logic Operation
AND A,[m] AND data memory to ACC 1 Z
OR A,[m] OR data memory to ACC 1 Z
XOR A,[m] Exclusive-OR data memory to ACC 1 Z
ANDM A,[m] AND ACC to data memory 1(1) Z
ORM A,[m] OR ACC to data memory 1(1) Z
XORM A,[m] Exclusive-OR ACC to data memory 1(1) Z
AND A,x AND immediate data to ACC 1 Z
OR A,x OR immediate data to ACC 1 Z
XOR A,x Exclusive-OR immediate data to ACC 1 Z
CPL [m] Complement data memory 1(1) Z
CPLA [m] Complement data memory with result in ACC 1 Z
Increment & Decrement
INCA [m] Increment data memory with result in ACC 1 Z
INC [m] Increment data memory 1(1) Z
DECA [m] Decrement data memory with result in ACC 1 Z
DEC [m] Decrement data memory 1(1) Z

Rev. 1.40 25 July 18, 2001

 HT46R47

Instruction Flag
Mnemonic Description
Cycle Affected
Rotate
RRA [m] Rotate data memory right with result in ACC 1 None
RR [m] Rotate data memory right 1(1) None
RRCA [m] Rotate data memory right through carry with result in 1 C
ACC
RRC [m] Rotate data memory right through carry 1(1) C
RLA [m] Rotate data memory left with result in ACC 1 None
RL [m] Rotate data memory left 1(1) None
RLCA [m] Rotate data memory left through carry with result in 1 C
ACC
RLC [m] Rotate data memory left through carry 1(1) C
Data Move
MOV A,[m] Move data memory to ACC 1 None
MOV [m],A Move ACC to data memory 1(1) None
MOV A,x Move immediate data to ACC 1 None
Bit Operation
CLR [m].i Clear bit of data memory 1(1) None
SET [m].i Set bit of data memory 1(1) None
Branch
JMP addr Jump unconditionally 2 None
SZ [m] Skip if data memory is zero 1(2) None
SZA [m] Skip if data memory is zero with data movement to 1(2) None
ACC
SZ [m].i Skip if bit i of data memory is zero 1(2) None
SNZ [m].i Skip if bit i of data memory is not zero 1(2) None
SIZ [m] Skip if increment data memory is zero 1(3) None
SDZ [m] Skip if decrement data memory is zero 1(3) None
SIZA [m] Skip if increment data memory is zero with result in 1(2) None
ACC
SDZA [m] Skip if decrement data memory is zero with result in 1(2) None
ACC
CALL addr Subroutine call 2 None
RET Return from subroutine 2 None
RET A,x Return from subroutine and load immediate data to 2 None
ACC
RETI Return from interrupt 2 None

Rev. 1.40 26 July 18, 2001

 HT46R47

Instruction Flag
Mnemonic Description
Cycle Affected
Table Read
TABRDC [m] Read ROM code (current page) to data memory and 2(1) None
TBLH
TABRDL [m] Read ROM code (last page) to data memory and TBLH 2(1) None
Miscellaneous
NOP No operation 1 None
CLR [m] Clear data memory 1(1) None
SET [m] Set data memory 1(1) None
CLR WDT Clear Watchdog Timer 1 TO,PD
CLR WDT1 Pre-clear Watchdog Timer 1 TO(4),PD(4)
CLR WDT2 Pre-clear Watchdog Timer 1 TO(4),PD(4)
SWAP [m] Swap nibbles of data memory 1(1) None
SWAPA [m] Swap nibbles of data memory with result in ACC 1 None
HALT Enter power down mode 1 TO,PD

Note: x: 8 bits immediate data

m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed
for one more cycle (four system clocks).
(2)
: If a skipping to next instruction occurs, the execution cycle of instructions will be delayed
one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
: and (2)
(4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by
executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared.
Otherwise the TO and PD flags remain unchanged.

Rev. 1.40 27 July 18, 2001

 HT46R47

Instruction Definition

ADC A,[m] Add data memory and carry to the accumulator.

Description The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the accumulator.
Operation ACC ¬ ACC+[m]+C
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ Ö Ö Ö Ö

ADCM A,[m] Add the accumulator and carry to data memory.

Description The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the specified data memory.
Operation [m] ¬ ACC+[m]+C
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ Ö Ö Ö Ö

ADD A,[m] Add data memory to the accumulator.

Description The contents of the specified data memory and the accumulator are added.
The result is stored in the accumulator.
Operation ACC ¬ ACC+[m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ Ö Ö Ö Ö

ADD A,x Add immediate data to the accumulator.

Description The contents of the accumulator and the specified data are added, leaving
the result in the accumulator.
Operation ACC ¬ ACC+x
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ Ö Ö Ö Ö

Rev. 1.40 28 July 18, 2001

 HT46R47

ADDM A,[m] Add the accumulator to the data memory.

Description The contents of the specified data memory and the accumulator are added.
The result is stored in the data memory.
Operation [m] ¬ ACC+[m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ Ö Ö Ö Ö

AND A,[m] Logical AND accumulator with data memory.

Description Data in the accumulator and the specified data memory perform a bitwise
logical_AND operation. The result is stored in the accumulator.
Operation ACC ¬ ACC "AND" [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

AND A,x Logical AND immediate data to the accumulator.

Description Data in the accumulator and the specified data perform a bitwise logi-
cal_AND operation. The result is stored in the accumulator.
Operation ACC ¬ ACC "AND" x
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

ANDM A,[m] Logical AND data memory with the accumulator.

Description Data in the specified data memory and the accumulator perform a bitwise
logical_AND operation. The result is stored in the data memory.
Operation [m] ¬ ACC "AND" [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

Rev. 1.40 29 July 18, 2001

 HT46R47

CALL addr Subroutine call.

Description The instruction unconditionally calls a subroutine located at the indicated
address. The program counter increments once to obtain the address of the
next instruction, and pushes this onto the stack. The indicated address is
then loaded. Program execution continues with the instruction at this ad-
dress.
Operation Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

CLR [m] Clear data memory.

Description The contents of the specified data memory are cleared to 0.
Operation [m] ¬ 00H
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

CLR [m].i Clear bit of data memory.

Description The bit i of the specified data memory is cleared to 0.
Operation [m].i ¬ 0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

CLR WDT Clear Watchdog Timer.

Description The WDT and the WDT Prescaler are cleared (re-counting from 0). The
power down bit (PD) and time-out bit (TO) are cleared.
Operation WDT and WDT Prescaler ¬ 00H
PD and TO ¬ 0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ 0 0 ¾ ¾ ¾ ¾

Rev. 1.40 30 July 18, 2001

 HT46R47

CLR WDT1 Preclear Watchdog Timer.

Description The TO, PD flags, WDT and the WDT Prescaler has cleared (re-counting
from 0), if the other preclear WDT instruction has been executed. Only exe-
cution of this instruction without the other preclear instruction just sets the
indicated flag which implies this instruction has been executed and the TO
and PD flags remain unchanged.
Operation WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ 0* 0* ¾ ¾ ¾ ¾

CLR WDT2 Preclear Watchdog Timer.

Description The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting
from 0), if the other preclear WDT instruction has been executed. Only exe-
cution of this instruction without the other preclear instruction, sets the in-
dicated flag which implies this instruction has been executed and the TO and
PD flags remain unchanged.
Operation WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ 0* 0* ¾ ¾ ¾ ¾

CPL [m] Complement data memory.

Description Each bit of the specified data memory is logically complemented (1's comple-
ment). Bits which previously contained a 1 are changed to 0 and vice-versa.
Operation [m] ¬ [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

Rev. 1.40 31 July 18, 2001

 HT46R47

CPLA [m] Complement data memory and place result in the accumulator.
Description Each bit of the specified data memory is logically complemented (1's comple-
ment). Bits which previously contained a 1 are changed to 0 and vice-versa.
The complemented result is stored in the accumulator and the contents of
the data memory remain unchanged.
Operation ACC ¬ [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

DAA [m] Decimal-Adjust accumulator for addition.

Description The accumulator value is adjusted to the BCD (Binary Coded Decimal) code.
The accumulator is divided into two nibbles. Each nibble is adjusted to the
BCD code and an internal carry (AC1) will be done if the low nibble of the ac-
cumulator is greater than 9. The BCD adjustment is done by adding 6 to the
original value if the original value is greater than 9 or a carry (AC or C) is set;
otherwise the original value remains unchanged. The result is stored in the
data memory and only the carry flag (C) may be affected.
Operation If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0) ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö

DEC [m] Decrement data memory.

Description Data in the specified data memory is decremented by 1.
Operation [m] ¬ [m]-1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

Rev. 1.40 32 July 18, 2001

 HT46R47

DECA [m] Decrement data memory and place result in the accumulator.
Description Data in the specified data memory is decremented by 1, leaving the result in
the accumulator. The contents of the data memory remain unchanged.
Operation ACC ¬ [m]-1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

HALT Enter power down mode.

Description This instruction stops program execution and turns off the system clock. The
contents of the RAM and registers are retained. The WDT and prescaler are
cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is
cleared.
Operation PC ¬ PC+1
PD ¬ 1
TO ¬ 0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ 0 1 ¾ ¾ ¾ ¾

INC [m] Increment data memory.

Description Data in the specified data memory is incremented by 1.
Operation [m] ¬ [m]+1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

INCA [m] Increment data memory and place result in the accumulator.
Description Data in the specified data memory is incremented by 1, leaving the result in
the accumulator. The contents of the data memory remain unchanged.
Operation ACC ¬ [m]+1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

Rev. 1.40 33 July 18, 2001

 HT46R47

JMP addr Directly jump.

Description Bits of the program counter are replaced with the directly-specified address
unconditionally, and control is passed to this destination.
Operation PC ¬ addr
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

MOV A,[m] Move data memory to the accumulator.

Description The contents of the specified data memory are copied to the accumulator.
Operation ACC ¬ [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

MOV A,x Move immediate data to the accumulator.

Description The 8-bit data specified by the code is loaded into the accumulator.
Operation ACC ¬ x
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

MOV [m],A Move the accumulator to data memory.

Description The contents of the accumulator are copied to the specified data memory (one
of the data memory).
Operation [m] ¬ ACC
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

NOP No operation.
Description No operation is performed. Execution continues with the next instruction.
Operation PC ¬ PC+1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.40 34 July 18, 2001

 HT46R47

OR A,[m] Logical OR accumulator with data memory.

Description Data in the accumulator and the specified data memory (one of the data
memory) perform a bitwise logical_OR operation. The result is stored in the
accumulator.
Operation ACC ¬ ACC "OR" [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

OR A,x Logical OR immediate data to the accumulator.

Description Data in the accumulator and the specified data perform a bitwise logical_OR
operation. The result is stored in the accumulator.
Operation ACC ¬ ACC "OR" x
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

ORM A,[m] Logical OR data memory with the accumulator.

Description Data in the data memory (one of the data memory) and the accumulator per-
form a bitwise logical_OR operation. The result is stored in the data memory.
Operation [m] ¬ ACC "OR" [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

RET Return from subroutine.

Description The program counter is restored from the stack. This is a 2 cycle instruction.
Operation PC ¬ Stack
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.40 35 July 18, 2001

 HT46R47

RET A,x Return and place immediate data in the accumulator.

Description The program counter is restored from the stack and the accumulator loaded
with the specified 8-bit immediate data.
Operation PC ¬ Stack
ACC ¬ x
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

RETI Return from interrupt.

Description The program counter is restored from the stack, and interrupts are enabled
by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0;
register INTC).
Operation PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

RL [m] Rotate data memory left.

Description The contents of the specified data memory are rotated 1 bit left with bit 7 ro-
tated into bit 0.
Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

RLA [m] Rotate data memory left and place result in the accumulator.
Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into
bit 0, leaving the rotated result in the accumulator. The contents of the data
memory remain unchanged.
Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.40 36 July 18, 2001

 HT46R47

RLC [m] Rotate data memory left through carry.

Description The contents of the specified data memory and the carry flag are rotated 1 bit
left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0
position.
Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö

RLCA [m] Rotate left through carry and place result in the accumulator.
Description Data in the specified data memory and the carry flag are rotated 1 bit left. Bit
7 replaces the carry bit and the original carry flag is rotated into bit 0 posi-
tion. The rotated result is stored in the accumulator but the contents of the
data memory remain unchanged.
Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö

RR [m] Rotate data memory right.

Description The contents of the specified data memory are rotated 1 bit right with bit 0
rotated to bit 7.
Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.40 37 July 18, 2001

 HT46R47

RRA [m] Rotate right and place result in the accumulator.

Description Data in the specified data memory is rotated 1 bit right with bit 0 rotated into
bit 7, leaving the rotated result in the accumulator. The contents of the data
memory remain unchanged.
Operation ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

RRC [m] Rotate data memory right through carry.

Description The contents of the specified data memory and the carry flag are together ro-
tated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated
into the bit 7 position.
Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö

RRCA [m] Rotate right through carry and place result in the accumulator.
Description Data of the specified data memory and the carry flag are rotated 1 bit right.
Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7
position. The rotated result is stored in the accumulator. The contents of the
data memory remain unchanged.
Operation ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö

Rev. 1.40 38 July 18, 2001

 HT46R47

SBC A,[m] Subtract data memory and carry from the accumulator.
Description The contents of the specified data memory and the complement of the carry
flag are subtracted from the accumulator, leaving the result in the accumula-
tor.
Operation ACC ¬ ACC+[m]+C
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ Ö Ö Ö Ö

SBCM A,[m] Subtract data memory and carry from the accumulator.
Description The contents of the specified data memory and the complement of the carry
flag are subtracted from the accumulator, leaving the result in the data
memory.
Operation [m] ¬ ACC+[m]+C
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ Ö Ö Ö Ö

SDZ [m] Skip if decrement data memory is 0.

Description The contents of the specified data memory are decremented by 1. If the result
is 0, the next instruction is skipped. If the result is 0, the following instruc-
tion, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise
proceed with the next instruction (1 cycle).
Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SDZA [m] Decrement data memory and place result in ACC, skip if 0.
Description The contents of the specified data memory are decremented by 1. If the result
is 0, the next instruction is skipped. The result is stored in the accumulator
but the data memory remains unchanged. If the result is 0, the following in-
struction, fetched during the current instruction execution, is discarded and
a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise
proceed with the next instruction (1 cycle).
Operation Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

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 HT46R47

SET [m] Set data memory.

Description Each bit of the specified data memory is set to 1.
Operation [m] ¬ FFH
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SET [m].i Set bit of data memory.

Description Bit ²i² of the specified data memory is set to 1.
Operation [m].i ¬ 1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SIZ [m] Skip if increment data memory is 0.

Description The contents of the specified data memory are incremented by 1. If the result
is 0, the following instruction, fetched during the current instruction execu-
tion, is discarded and a dummy cycle is replaced to get the proper instruction
(2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SIZA [m] Increment data memory and place result in ACC, skip if 0.
Description The contents of the specified data memory are incremented by 1. If the result
is 0, the next instruction is skipped and the result is stored in the accumula-
tor. The data memory remains unchanged. If the result is 0, the following in-
struction, fetched during the current instruction execution, is discarded and
a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise
proceed with the next instruction (1 cycle).
Operation Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

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 HT46R47

SNZ [m].i Skip if bit ²i² of the data memory is not 0.

Description If bit ²i² of the specified data memory is not 0, the next instruction is skipped.
If bit ²i² of the data memory is not 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is re-
placed to get the proper instruction (2 cycles). Otherwise proceed with the
next instruction (1 cycle).
Operation Skip if [m].i¹0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SUB A,[m] Subtract data memory from the accumulator.

Description The specified data memory is subtracted from the contents of the accumula-
tor, leaving the result in the accumulator.
Operation ACC ¬ ACC+[m]+1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ Ö Ö Ö Ö

SUBM A,[m] Subtract data memory from the accumulator.

Description The specified data memory is subtracted from the contents of the accumula-
tor, leaving the result in the data memory.
Operation [m] ¬ ACC+[m]+1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ Ö Ö Ö Ö

SUB A,x Subtract immediate data from the accumulator.

Description The immediate data specified by the code is subtracted from the contents of
the accumulator, leaving the result in the accumulator.
Operation ACC ¬ ACC+x+1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ Ö Ö Ö Ö

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 HT46R47

SWAP [m] Swap nibbles within the data memory.

Description The low-order and high-order nibbles of the specified data memory (one of
the data memories) are interchanged.
Operation [m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SWAPA [m] Swap data memory and place result in the accumulator.
Description The low-order and high-order nibbles of the specified data memory are inter-
changed, writing the result to the accumulator. The contents of the data
memory remain unchanged.
Operation ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SZ [m] Skip if data memory is 0.

Description If the contents of the specified data memory are 0, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation Skip if [m]=0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SZA [m] Move data memory to ACC, skip if 0.

Description The contents of the specified data memory are copied to the accumulator. If
the contents is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1
cycle).
Operation Skip if [m]=0, ACC ¬ [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

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 HT46R47

SZ [m].i Skip if bit ²i² of the data memory is 0.

Description If bit ²i² of the specified data memory is 0, the following instruction, fetched
during the current instruction execution, is discarded and a dummy cycle is
replaced to get the proper instruction (2 cycles). Otherwise proceed with the
next instruction (1 cycle).
Operation Skip if [m].i=0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

TABRDC [m] Move the ROM code (current page) to TBLH and data memory.
Description The low byte of ROM code (current page) addressed by the table pointer
(TBLP) is moved to the specified data memory and the high byte transferred
to TBLH directly.
Operation [m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

TABRDL [m] Move the ROM code (last page) to TBLH and data memory.
Description The low byte of ROM code (last page) addressed by the table pointer (TBLP)
is moved to the data memory and the high byte transferred to TBLH directly.
Operation [m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

XOR A,[m] Logical XOR accumulator with data memory.

Description Data in the accumulator and the indicated data memory perform a bitwise
logical Exclusive_OR operation and the result is stored in the accumulator.
Operation ACC ¬ ACC "XOR" [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

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 HT46R47

XORM A,[m] Logical XOR data memory with the accumulator.

Description Data in the indicated data memory and the accumulator perform a bitwise
logical Exclusive_OR operation. The result is stored in the data memory. The
0 flag is affected.
Operation [m] ¬ ACC "XOR" [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

XOR A,x Logical XOR immediate data to the accumulator.

Description Data in the accumulator and the specified data perform a bitwise logical Ex-
clusive_OR operation. The result is stored in the accumulator. The 0 flag is
affected.
Operation ACC ¬ ACC "XOR" x
Affected flag(s)
TC2 TC1 TO PD OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

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 HT46R47

Holtek Semiconductor Inc. (Headquarters)

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Tel: 886-3-563-1999
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Tel: 886-2-2782-9635
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Tel: 510-252-9880
Fax: 510-252-9885

Copyright Ó 2001 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres-
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

Rev. 1.40 45 July 18, 2001