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UCS510

This document contains a computer architecture exam with 5 questions covering topics like combinational logic design, memory sizes, 2's complement arithmetic, Boolean minimization, instruction formats, floating point representation, and arithmetic circuits. It provides the roll number, course details, date, time, and instructions for the exam.

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Sanyam Gupta
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86 views1 page

UCS510

This document contains a computer architecture exam with 5 questions covering topics like combinational logic design, memory sizes, 2's complement arithmetic, Boolean minimization, instruction formats, floating point representation, and arithmetic circuits. It provides the roll number, course details, date, time, and instructions for the exam.

Uploaded by

Sanyam Gupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Roll Number:

Thapar Institute of Engineering & Technology, Patiala


Department of Computer Science &Engineering
Course Code: UCS510 B. E.(COE/CSE) : MST
Course Name: Computer Architecture and Organization
28/9/2022 1:00 PM - 3:00 PM
Time: 2 Hours, M. Marks: 30 Faculty: SHI/SOL/ALK/YAS/SHR
Note: All questions carry equal marks. Attempt all questions.

Q.1. A. A circuit outputs a digit in the form of 4 bits. 0 is represented (4+2)


by 0000, 1 by 0001..., 9 by 1001. A combinational circuit is to be designed
which takes these 4 bits as input and outputs 1 if the digit 5, and 0 otherwise.
If only AND, OR and NOT gates may be used, Draw the circuit and Find the
minimum number of gates required?
B. A computer uses a memory of 65536 words with 8 bit in each word. Determine
the size of PC, IR, DR, AC?
Q.2 A. Let R1 and R2 be two 4-bit registers that store numbers in 2's complement (2+4)
form. If the value to be stored in R1 is 1100 and R2 is 1010 what will be the
value of Vs (overflow bit) after performing operation R1+R2?
B. Minimize the given Boolean Expression by using the four-variable K-Map. F (A,
B, C, D) = E m (1, 5, 6, 12, 13, 14) + d (2, 4).

Q.3 A. A processor has 64 registers and uses 16-bit instruction format. It has two (3+3)
types of instructions: I-type and R-type. Each I-type instruction contains an
opcode, a rtgister name, and a 4-bit immediate value. Each R-type instruction
contains an opcode and two register names. If there are 8 distinct 1-type
opcodes, then how many maximum number of distinct R-type opcodes will be
possible?
B. Convert following numbers in IEEE-754 floating point 32 bit short precision
format. A. (14.25)io B. (C164)16

Q.4 Perform the signed multiplication of following number using Booth's Algorithm with (6)
clear steps [12*5] using 5 bits to represent both multiplier and multiplicands.
Q.5 Design an arithmetic circuit with one selection variable So and two 4-bit data inputs A (6)
and B. The circuit generates the following four arithmetic operations
in conjunction with the input carry Co, Draw the logic diagram for

io=0 Cio=1
So =0 A+B Transfer A
So =1 A+1 A-B

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