ELECTRONICS AND COMMUNICATION ENGINEERING

SUBJECT: EC8791 EMBEDDED AND REAL TIME SYSTEMS

SEM /YEAR: VII / IV Year B.E

QUESTION BANK

UNIT I - INTRODUCTION TO EMBEDDEDSYSTEM DESIGN

Complex systems and microprocessors– Embedded system design process –Design example: Model
train controller- Design methodologies- Design flows - Requirement Analysis – Specifications-System
analysis and architecture design – Quality Assurance techniques - Designing with computing
platforms – consumer electronics architecture – platform-level performance analysis.

PART-A

1. What is an embedded computer system? (R)

An Embedded computer system is any device that includes a programmable computer but is
not itself intended to be a general-purpose computer. Thus, a PC is not itself an embedded
computing system. But a fax machine or a clock built from a microprocessor is an embedded
computing system.
2. Describe the major steps in embedded system design process. (U)
3. Write about UML. (R)
Unified Modeling Language (UML) was designed to be useful at many levels of abstraction in
the design process. UML is useful because it encourages design by successive refinement and
progressively adding detail to the design, rather than rethinking the design at each new level of
abstraction. UML is an object-oriented modeling language.
4. Define DCC and its standards. (R)
The Digital Command Control (DCC) standard was created by the National Model Railroad
Association to support interoperable digitally controlled model trains. DCC was created to
provide a standard that could be built by any manufacturer so that hobbyists could mix and match
components from multiple vendors.
The DCC standard is given in two documents:
• Standard S-9.1, the DCC Electrical Standard, defines how bits are encoded on the rails for
transmission.
• Standard S-9.2, the DCC Communication Standard, defines the packets that carry information.
5. Illustrate the various embedded system design modeling in refining or partitioning? (AP)
• Abstract co-design finite-state machines
• Extended co-design finite-state machines
• Using Unified Modeling Language
6. Why microprocessor is used in embedded system? (C)
• Microprocessors are an efficient way to implement digital systems.
• They make it easier to design families of products that can be built to provide various
feature sets at different price points and can be extended to provide new features to keep up
with rapidly changing market.
7. Mention the challenges in embedded computing system design. (or) Summarize the
challenges in embedded computing system design. (R)
How much hardware do we need? How do we meet deadlines? How do we minimize power
consumption? How do we design for upgradeability? Does it really work? - Complex Testing.
8. Enumerate various issues in real time computing. (or) Identify the various issues in real
time computing. (E)
 Complex algorithms
 Complex user interface
 Data must be ready by deadline
 Multirate data to be handled
 Manufacturing cost and power are critical
9. List the non-functional requirements of an Embedded Architecture. (R)
Typical nonfunctional requirements include:
 Performance
 Cost
 Physical size and weight
 Power Consumption
10. Assess the characteristics of embedded computing. (AZ)
 Embedded computing systems have to provide sophisticated functionality: Complex
Algorithm, User Interface
 Embedded computing operations must often be performed to meet deadlines: Real time,
 Multirate
 Costs of various sorts are also very important: Manufacturing Cost, Power and energy
 Most embedded computing systems are designed by small teams on tight deadlines.
11. State the major goals of embedded system design. (R)
A design process has several important goals beyond function, performance, and power:
 Time-to-market
 Manufacturing Cost
 Quality
12. Elaborate, Quality Assurance Techniques? (C)
The quality of a product or service can be judged by how well it satisfies its intended function.
Quality must be designed in. One can‟t test out enough bugs to deliver a high-quality product.
The quality assurance (QA) process is vital for the delivery of a satisfactory system.
13. Justify, how the state bar chart used to state based system specification analysis. (E)
The Statechart is a well-known technique for state-based specification that introduced some
important concepts. The Statechart notation uses an event-driven model. Statecharts allow states
to be grouped together to show common functionality. There are two basic groupings: OR and
AND.
14. Categories the steps involved in system analysis using CRC card. (AZ)
The CRC card methodology is informal; the following steps are used to analyze a system:

 Develop an initial list of classes

 Write an initial list of responsibilities and collaborators
 Create some usage scenarios
 Walk through the scenarios
 Refine the classes, responsibilities, and collaborators
 Add class relationships
15. Estimate about the function quality management of ISO 9000? (U)
The International Standards Organization (ISO) has created a set of quality standards known as
ISO 9000. ISO 9000 was created to apply to a broad range of industries, including but not limited
to embedded hardware and software. A wide-ranging standard such as ISO 9000 cannot specify
the detailed standards for every industry. Consequently, ISO 9000 concentrates on processes used
to create the product or service.
16. What are the services to be provided by consumer electronics? (R)
Consumer electronics devices provide several types of services in different combinations:
 Multimedia: A large and growing number of standards have been developed for
multimedia compression: MP3, Dolby DigitalTM, and so on for audio; JPEG for still
images; MPEG-2, MPEG-4, H.264, and so on for video.
 Data storage and management: Many devices provide PC-compatible file systems so
that data can be shared more easily.
 Communications: Communications may be relatively simple, such as a USB interface to
a host computer. The communications link may also be more sophisticated, such as an
Ethernet port or a cellular telephone link.
17. What you mean by wear-leveling flash file system? (R)
A wear-leveling flash file system manages the use of flash memory locations to equalize wear
while maintaining compatibility with existing file systems. A simple model of a standard file
system has two layers: the bottom layer handles physical reads and writes on the storage device;
the top layer provides a logical view of the file system.

PART-B

1. (i) What are the factors to be considered while designing an Embedded System Process? (7)
Refer page no. 10-19 in Marilyn Wolf Book 3rd Edition

(ii) State the importance of Structural and Behavioral description in detail. (6)
Refer page no. 21-28 in Marilyn Wolf Book 3rd Edition

2. (i) Explain in detail the characteristics of embedded computing applications. (6)

Refer page no. 4-5 in Marilyn Wolf Book 3rd Edition

(ii) Analyze in detail about the challenges in embedded computing system design. (7)
Refer page no. 8-9 in Marilyn Wolf Book 3rd Edition

3. (i) Mention the requirements for designing a GPS moving map in embedded system design
process.
Refer page no. 12-16 in Marilyn Wolf Book 3rd Edition (8)

(ii) Write down the major operations and data flows of a GPS moving map and draw its
Architecture. (5)
Refer page no. 17-19 in Marilyn Wolf Book 3rd Edition

4. Write short notes on the following:

(i) Control-Oriented Specification Languages. (7)
Refer page no. 391-394 in Marilyn Wolf Book 3rd Edition
(ii) Quality Assurance Techniques. (6)
Refer page no. 402-404 in Marilyn Wolf Book 3rd Edition

5. Define acronym of CRC. Make the use of a CRC card Layout to explain the system analysis
and architecture design. (13)
Refer page no. 396-400 in Marilyn Wolf Book 3rd Edition

6. Explain the platform level performance analysis of Embedded System Design. (13)
Refer page no. 188-191 in Marilyn Wolf Book 3rd Edition

7. Analyze the hierarchical design flow for an embedded system with suitable diagrams. (13)
Refer page no. 383, 386-387 in Marilyn Wolf Book 3rd Edition
 8. Construct system design methods using water fall, spiral and rain fall method and also give
the differences. (13)
Refer page no. 383-385 in Marilyn Wolf Book 3rd Edition

9. Demonstrate the goal of design methodology in detail. (13)

Refer page no. 381-383 in Marilyn Wolf Book 3rd Edition

10. Develop a model that would change system design using hardware/software design system
method.
Refer page no. 383, 385-386 in Marilyn Wolf Book 3rd Edition (13)

11. (i) Design in detail a Model Train Controller with suitable diagrams. (8)
Refer page no. 28-32 in Marilyn Wolf Book 3rd Edition
(iii) Formulate design steps of Model Train Controller in detail. (5)

Refer page no. 32-42 in Marilyn Wolf Book 3rd Edition

12. Describe the performance of embedded computing systems. (13)

Refer page no. 9-10 in Marilyn Wolf Book 3rd Edition

13. Write short note on the following in terms of consumer electronicssystem architecture.
(i) Use Cases and Requirements (5)
Refer page no. 185-186 in Marilyn Wolf Book 3rd Edition
(ii) Platforms and Operating Systems (5)
Refer page no. 187 in Marilyn Wolf Book 3rd Edition
(iii) Flash File Systems (3)
Refer page no. 188 in Marilyn Wolf Book 3rd Edition

PART-C

1. Develop the requirement, specification and state diagram of a model train controller with
necessary illustrations. (15)
Refer page no. 28-42 in Marilyn Wolf Book 3rd Edition
2. Elaborate following in detail as per system level design analysis.
(i) Consumer electronics architecture (5)
Refer page no. 185-186 in Marilyn Wolf Book 3rd Edition
(ii) Quality Assurance techniques (5)
Refer page no. 402-403 in Marilyn Wolf Book 3rd Edition
(iii) Architecture design (5)
Refer page no. 396-397 in Marilyn Wolf Book 3rd Edition
3. Evaluate the different factors involved in embedded system design process. (15)
Refer page no. 10-19 in Marilyn Wolf Book 3rd Edition

4. Justify poor specifications lead to poor quality code - do aspects of a poorly constructed
specification necessarily lead to bad software? (15)
Refer page no. 402-404 in Marilyn Wolf Book 3rd Edition
 UNIT II - ARM PROCESSOR AND PERIPHERALS

ARM Architecture Versions – ARM Architecture – Instruction Set – Stacks and Subroutines –
Features of the LPC 214X Family – Peripherals – The Timer Unit – Pulse Width Modulation Unit –
UART – Block Diagram of ARM9 and ARM Cortex M3 MCU.

PART-A

1. What is Code density? (R)

Code density refers to how many microprocessor instructions it takes to perform a requested
action, and how much space each instruction takes up. It is a measure of how much stuff you can get
into a given amount of program memory, or how many bytes of program memory you need to store a
given amount of functionality.
2. Illustrate the three different profiles of ARM cortex Processor. (U)
The ARM Cortex family includes processors based on the three distinct profiles of the ARMv7
architecture.
 Cortex-A: built for advanced operating systems and exhibits the highest possible performance;
 Cortex-R: caters perfectly to the needs of real-time applications and provides its users with the
fastest response times;
 Cortex-M: mainly built for microcontrollers
3. Evaluate the important features that make ARM ideal for embedded applications. (E)
ARM has got better performance when compared to other processors. The ARM processor is
basically consisting of low power consumption and low cost. It is very easy to use ARM for quick
and efficient embedded application developments so that is the main reason why ARM is most
popular.
4. Name the registers set of ARM processor. (R)
In all ARM processors, the following registers are available and accessible in any processor mode:
 13 general-purpose registers R0-R12.
 One Stack Pointer (SP).
 One Link Register (LR).
 One Program Counter (PC).
 One Application Program Status Register (APSR).
5. Develop the differences between MULS and MULSEQ. (AP)
MULS R0, R2, R0; multiply with flag update, R0 = R0 x R2
MULSEQ R3, R2, R1; R1=R2 x R3 is done only if Z=1 because of suffix SEQ flags are updated.
6. Explain the execution of instruction MOV R11, R2. (C)
The content of R2 is copied to R11.
7. Write down the significance of TST instruction. (R)
The TST instruction performs a bitwise AND operation on the value in Rn and the value of
Operand2. This is the same as an ANDS instruction, except that the result is discarded.
8. Outline the significance of TEQ instruction. (U)
The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the
value of Operand2.
9. State the usage of EQU directive in programming. (R)
The EQU directive gives a symbolic name to a numeric constant, a register-relative value or a
PC-relative value. The EQU instruction assigns absolute or relocatable values to symbols. EQU also
assigns attributes. It takes the value, relocation, and length attributes of the operand and assigns them
to the name field symbol, and sets the integer and scale attributes to zero.
10. Examine the maximum size of the constant that can be used in the immediate mode? (AP)
The maximum size of an immediate on RISC architecture is much lower; for example, on the
ARM architecture the maximum size of an immediate is 12-bits as the instruction size is fixed at 32-
bits.
11. Explain how the literal pool is accessed? (E)
The assembler uses literal pools to store some constant data in code sections. The assembler
places a literal pool at the end of each section. The end of a section is defined either by the END
directive at the end of the assembly.
12. Draw the sequence of actions needed for a nested procedure. (R)

13. What is meant by idle mode? (R)

In idle mode, execution of instructions is suspended until either a reset or interrupt occurs.
Peripheral functions continue operation during idle mode and may generate interrupts to cause the
processor to resume execution. Idle mode eliminates power used by the processor itself, memory
systems and related controllers, and internal buses.
14. Find the methods to terminate the power down mode. (AP)
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The
processor state and registers, peripheral registers, and internal SRAM values are preserved throughout
Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can
be terminated and normal operation resumed by either a reset or certain specific interrupts that are able
to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode
reduces chip power consumption to nearly zero.
15. Mention the features of LPC214x. (U)
It has 60-MHz operation
• On-chip Flash and SRAM memory
– LPC2141: 32 KB Flash, 8 KB SRAM
– LPC2142: 64 KB Flash, 16 KB SRAM
– LPC2144: 128 KB Flash, 16 KB SRAM
– LPC2146: 256 KB Flash, 40 KB SRAM
– LPC2148: 512 KB Flash, 40 KB SRAM
• Very fast Flash programming via on-chip boot-loader software
• 45 Fast I/O pins (5-V tolerant) – up to 15-MHz switching
• Temperature range: -40 to +85 °C
16. Draw the pin diagram of LPC 2148 with its pin names.

17. Summarize any five peripherals in the LPC 2148 MCU. (U)
Timer: Timer is a specific type of clock which is used to measure the time intervals. It
provides/measures the time interval by counting the input clocks.
UART: UART (Universal Asynchronous Receiver/Transmitter) is a serial communication protocol
in which data is transferred serially bit by bit at a time. In Asynchronous serial communication, a
byte of data is transferred at a time. UART serial communication protocol uses a defined frame
structure for their data bytes.
PWM: Pulse Width Modulation (PWM) is a technique by which width of a pulse is varied while
keeping the frequency constant. A period of a pulse consists of an ON cycle (HIGH) and
an OFF cycle (LOW). The fraction for which the signal is ON over a period is known as duty cycle.
 Watchdog timer: The purpose of the watchdog is to reset the microcontroller within a reasonable
amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to „feed‟ (or reload) the watchdog within a predetermined amount of
time.
10 bit ADC: The LPC2141/42 contains one and the LPC2144/46/48 contains two analog to digital
converters. These converters are single 10-bit successive approximation analog to digital converters.
While ADC0 has six channels, ADC1 has eight channels. Therefore, total number of available ADC
inputs for LPC2141/42 is 6 and for LPC2144/46/48 are 14.
18. Compare PCLK and CCLK. (AZ)
The APB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first is to
provide peripherals with the desired PCLK via APB bus so that they can operate at the speed chosen
for the ARM processor.
19. For a GPIO pin to be made to act as an ON/OFF switch, which are the registers to be used.
(AZ)
PORT1 pins are configured as GPIO using PINSEL register and then their direction is set as
Output using the IODIR register. LEDs are turned ON by sending a high pulse using IOSET register.
20. How does the prescalar in a timer unit function? (C)

A 32-bit timer/counter has a programmable 32-bit prescalar. This is used to specify the
prescalar value for incrementing the TC (Timer Counter).
21. Distinguish between single and double edged PWM. (AZ)
Single Edge Controlled PWM: All the rising (positive going) edges of the output waveform are
positioned/fixed at the beginning of the PWM period. Only falling (negative going) edge position can
be controlled to vary the pulse width of PWM.
Double Edge Controlled PWM: All the rising (positive going) and falling (negative going) edge
positions can be controlled to vary the pulse width of PWM. Both the rising as well as the falling
edges can be positioned anywhere in the PWM period.

PART-B

1. Demonstrate the advanced features of the ARM Core. (13)

2. From the fundamentals, draw the architecture of ARM processor with relevant
explanation.(13)
3. (i) Point out the operating modes of ARM. (7)
(ii) Briefly explain the Register set of ARM. (6)
4. Examine the interrupt vector table by providing the vector address of each interrupt
supported by ARM. (13)
5. (i) Classify the ARM instruction set. (3)
 (ii) Explain any one type of instruction set with example. (10)
6. The content of registers is given as below
R1 = 0xEF00DE12,
R12 = 0x0456123F,
R5 = 4,
R6 = 28.
Find the result in the destination register when the following instructions are executed:
(i) LSL R1, #8 (5)
(ii) ASR R1, R5 (5)
(iii)ROR R2, R6 (3)
7. Give the general structure of an Assembly language line and provide examples for each
directive. (13)
8. Analyze the following indexed addressing mode with a sample instruction:
(i) Pre indexed Addressing mode (7)
(ii) Post indexed Addressing mode (6)
9. Discuss about the types of stacks and subroutines supported by ARM processor. (13)
10. Demonstrate the GPIO peripheral used in LPC214x family. (13)
11. Investigate the working of an UART in LPC214x. (13)
12. Describe briefly about the ARM peripheral PWM and its registers. (13)
13. (i) Calculate the value of the value to be given in PWMMR0 and PWMMR3 to get a pulse
train of period 5ms and duty cycle of 25%. (7)
(ii) Evaluate the features of LPC 214x processor. (6)
14. Neatly draw and explain ARM Cortex M3 and ARM 9. (13)

PART-C

1. Write a program to find the sum of 3X + 4Y + 9Z, where X = 2, Y = 3 and Z = 4 using ARM
Processor instruction set. (15)
2. Generate the program using ARM instruction to calculate 3X2 + 5Y2, where X = 8 and
Y = 5. (15)
3. Discuss on the procedure to generate the square wave from Timer unit in LPC214x chip with
an example code. (15)
4. Evaluate the values to be entered in the PWMPCR register for the following situations? (15)
(i) Single edge control for PWM3
(ii) Double edge control for PWM3
(iii)Single edge control for PWM1, 2 and 3
 UNIT III - EMBEDDED PROGRAMMING

Components for embedded programs- Models of programs- Assembly, linking and loading –
compilation techniques- Program level performance analysis – Software performance optimization –
Program level energy and power analysis and optimization – Analysis and optimization of program
size- Program validation and testing.

PART – A

1. Mention the different components for embedded programs. (R)

The components that are commonly used in embedded software: the state machine, the circular
buffer, and the queue. State machines are well suited to reactive systems such as user interfaces,
circular buffers and queues are useful in digital signal processing.
2. Evaluate the importance of circular buffer. (E)
The circular buffer is a data structure that lets us handle streaming data in an efficient way.

A circular buffer stores a subset of the data stream. At each point in time, the algorithm needs a
subset of the data stream that forms a window into the stream. The window slides with time as we
throw out old values no longer needed and add new values.
3. Compare enqueueing and dequeueing. (AZ)
Enqueueing: The code for adding an element to the tail of the queue is known as enqueueing.
void enqueue(int val)
{
if (((tail+1) % Q_SIZE) == head) error("enqueue onto full queue",tail);
q[tail] = val;
if (tail == Q_MAX) tail = 0;
else tail++;
}
Dequeueing: The code for removing an element from the head of the queue is known as
dequeueing.
int dequeue()
{
int returnval;
 if (head == tail) error("dequeue from empty queue",head);
returnval = q[head];
if (head == Q_MAX) head = 0;
else head++;
return returnval;
}
4. Describe about state machine. (C)
When inputs appear intermittently rather than as periodic samples, it is often convenient to
think of the system as reacting to those inputs. The reaction of most systems can be characterized
in terms of the input received and the current state of the system. This leads naturally to a finite-
state machine style of describing the reactive system‟s behavior.
5. Draw the signal flow graph of 3 stage FIR filter and write its code in C. (U)

The code for the FIR filter function:

int fir(int xnew)
{
int i;
int result;
circ_update(xnew);
for (i=0, result=0; i<CMAX; i++)
result += b[i] * circ_get(i);
return result;
}
6. Develop the differences between loop fusion and loop tiling. (AP)
Loop fusion combines two or more loops into a single loop. For this transformation to be
legal, two conditions must be satisfied. First, the loops must iterate over the same values. Second,
the loop bodies must not have dependencies that would be violated if they are executed together.
Loop tiling breaks up a loop into a set of nested loops, with each inner loop performing the
operations on a subset of the data.
7. Outline the significance of CDFG and its node types. (U)
A CDFG uses a data flow graph as an element, adding constructs to describe control. In a basic
CDFG, we have two types of nodes: decision nodes and data flow nodes. A data flow node
 encapsulates a complete data flow graph to represent a basic block. We can use one type of
decision node to describe all the types of control in a sequential program.
8. Construct a Data Flow Graph and Control/ Data Flow Graph (CDFG) with an example. (AP)
The data flow graph is generally drawn in the form shown in Fig. Here, the variables are not
explicitly represented by nodes. Instead, the edges are labeled with the variables they represent.

The Figure shows a bit of C code with control constructs and the CDFG constructed from it.

9. Define Dead Code. (R)

Dead code is code that can never be executed. Dead code can be generated by programmers,
either inadvertently or purposefully. Dead code can also be generated by compilers. Dead code can
be identified by reachability analysis; finding the other statements or instructions from which it can
be reached.
10. Design a Data Flow Graph for the block shown below: r = a + b - c; s = a*r; t = b-d; r = d + e.
(C)
Rewriting the basic block in single-assignment form is given by, r1 = a + b; s = a * r; t = b – d; r2
= d + e. The Data Flow Graph for the given basic block is given below:
11. State the basic principle of compilation technique. (R)
Compilation technique is useful to understand how a high-level language program is translated
into instructions: interrupt handling instructions, placement of data and instructions in memory,
etc. Understanding how the compiler works can help you know when you cannot rely on the
compiler. Understanding how code is generated can help you meet your performance goals. We
can summarize the compilation process with a formula: compilation = translation + optimization
12. Name any two techniques used to optimize execution time of program. (R)
Loop Optimization and Cache Optimization are the two techniques used to optimize execution
time of program.
13. Explain how power can be optimized at the program level? (E)
A few optimizations often useful for improving energy consumption are:
• Try to use registers efficiently.
• Analyze cache behavior to find major cache conflicts
• Make use of page mode accesses in the memory system whenever possible.
14. Mention the various compilation techniques. (R)
15. What does a linker do? (R)
A linker allows a program to be stitched together out of several smaller pieces. The linker
operates on the object files created by the assembler and modifies the assembled code to make the
necessary links between files. The linker determines the addresses of instructions and data and
produces an executable binary file.
16. Illustrate the need of symbol table in Assemblers. (U)

As shown in the figure, the name of each symbol and its address is stored in a symbol table that
is built during the first pass. The symbol table is built by scanning from the first instruction to the
last.
17. Discuss about the elements of program performance. (U)
Program execution time can be seen as, Execution time = Program path + Instruction timing.
The path is the sequence of instructions executed by the program. The instruction timing is
determined based on the sequence of instructions traced by the program path, which takes into
account data dependencies, pipeline behavior, and caching.
18. State the difference between program location counter and program counter. (R)
The symbol table is built by scanning from the first instruction to the last. During scanning, the
current location in memory is kept in a program location counter (PLC). Despite the similarity in
name to a program counter, the PLC is not used to execute the program, only to assign memory
locations to labels.

PART – B
1. Analyze the components of embedded program and discuss in detail about each component.
(13)
Refer page no. 214 – 223 in Marilyn Wolf Book 3rd Edition
2. Describe about stream-oriented programming and circular buffer with example. (13)
Refer page no. 216 – 221 in Marilyn Wolf Book 3rd Edition
3. (i) List the different models of Program. (3)
Refer page no. 223 in Marilyn Wolf Book 3rd Edition
(ii)Briefly explain with neat diagrams on various models of program. (10)
Refer page no. 224 - 228 in Marilyn Wolf Book 3rd Edition
4. Examine the Data flow graph with the help of an example. (13)
Refer page no. 224 in Marilyn Wolf Book 3rd Edition
5. Illustrate the Code/Data flow graph for a While loop with necessary diagrams. (13)
Refer page no. 226 – 228 in Marilyn Wolf Book 3rd Edition
6. In compilation process, Elaborate the role of:
(i) Assembly (7)
Refer page no. 229 – 233 in Marilyn Wolf Book 3rd Edition
 (ii) Linking and Loading (6)
Refer page no. 233 – 235 in Marilyn Wolf Book 3rd Edition
7. With the help of a flow chart describe the basic compilation process. (13)
Refer page no. 236 – 245 in Marilyn Wolf Book 3rd Edition
8. For the given conditional code snippet, generate the code (13)
if (a + b > 0)
x = 5;
else
x = 7;
Refer page no. 240 – 242 in Marilyn Wolf Book 3rd Edition
9. Discuss about the Procedure and Data structure with respect to compilers. (13)
Refer page no. 242 – 245 in Marilyn Wolf Book 3rd Edition
10. Demonstrate the dead code elimination to optimize the program with a code snippet. (13)
Refer page no. 246 – 247 in Marilyn Wolf Book 3rd Edition
11. Investigate the Loop transformation techniques for optimization of code. (13)
Refer page no. 262 – 263 in Marilyn Wolf Book 3rd Edition
12. Outline the Program level energy and power analysis and optimization. (13)
Refer page no. 266 – 269 in Marilyn Wolf Book 3rd Edition
13. Write about
(i) Black Box Testing (7)
Refer page no. 278 – 279 in Marilyn Wolf Book 3rd Edition
(ii) White Box/Clear Box Testing (6)
Refer page no. 271 – 278 in Marilyn Wolf Book 3rd Edition
14. (i) Illustrate with necessary diagrams about the program level performance analysis. (7)
Refer page no. 254 – 260 in Marilyn Wolf Book 3rd Edition
(ii)Frame the key features of clear box testing. (6)
Refer page no. 271 – 278 in Marilyn Wolf Book 3rd Edition
PART – C
1. Create a symbol table for the following code snippet (15)
ORG 100
label1: ADR r4, c
LDR r0, [r4]
label2: ADR r4, d
LDR r1, [r4]
label3: SUB r0, r0, r1
Refer page no. 231 – 232 in Marilyn Wolf Book 3rd Edition
2. Generate the statement translation into ARM instruction for the expression a*b + 5*(c-d).
(15)
Refer page no. 238 – 239 in Marilyn Wolf Book 3rd Edition
3. Explain the steps for Program generation from compilation through loading. (15)
Refer page no. 228 – 236 in Marilyn Wolf Book 3rd Edition
4. Evaluate the different techniques used in software performance optimization. (15)
Refer page no. 262 – 266 in Marilyn Wolf Book 3rd Edition
 UNIT IV - REAL TIME SYSTEMS
Structure of a Real Time System –– Estimating program run times – Task Assignment and Scheduling
– Fault Tolerance Techniques – Reliability, Evaluation – Clock Synchronisation.

PART – A
1. List out the two RM scheduling conditions. (R)
The rate-monotonic (RM) scheduling algorithm is a uniprocessor static-priority preemptive
scheme. The following assumptions are made in addition to assumptions A1 to A3
A4: All tasks in the task set are periodic.
A5: The relative deadline of a task is equal to its period.
2. Outline the uniprocessor scheduling algorithms. (R)
Uni-processor scheduling is part of the process of developing a multiprocessor schedule. Our
ability to obtain a feasible multiprocessor schedule is therefore linked to obtain feasible
uniprocessor schedules.
3. Define Performance measures for real time systems. (R)
A good performance measure must:
• Represent an efficient encoding of relevant information.
• Provide an objective basis for the ranking of candidate controller for a given application.
• Provide objective optimization criteria for design.
• Represent verifiable facts.
4. What is mean by hardware and software fault? (R)
A hardware fault is some physical defect that can cause a component to malfunction. A broken
wire or the output of a logic gate that is perpetually stuck at some logic value (0 or 1) are hardware
faults.
A software fault is a "bug" that can cause the program to fail for a given set of inputs.
5. Show the limitation of RM algorithm. (R)
Processes involved should not share the resources with other processes. Deadlines must be
similar to the time periods. Deadlines are deterministic. Process running with highest priority that
needs to run, will preempt all the other processes.
6. Discuss the performance degradation of a fault tolerant system. (U)
As the extent of the failures increases, performance starts to degrade. The system runs out of
slack capacity, and the operating system must begin shedding computational load. The less critical
tasks are shed, and the system is still able to carry out the critical core of tasks that are vital to the
survival of the controlled process.
7. Explain the forward and backward error recovery. (U)
Error recovery is the process by which the system attempts to recover from the effects of an
error. There are two forms of error recovery: forward and backward.
In forward error recovery, the error is masked without any computations having to be
redone.
In backward error recovery, the system is rolled back to a moment in time before the error is
believed to have occurred and the computation is carried out again. Backward error recovery uses
time redundancy, since it consumes additional time to mask the effects of failure.
8. Classify the partitioning of the intervote interval. (U)
The intervote interval can be divided into a first segment of negligible duration during which
any reconfiguration is carried out, and a second segment of length, which is when the application
programs are run.

9. Illustrate the role of static priority algorithm. (AP)

Static Priority Algorithms: Assume that the task priority does not change within a mode.
Eg: Rate-Monotonic(RM) Algorithm.
10. How will you distinguish static priority algorithm & dynamic priority algorithm? (AP)
Static Priority Algorithms: Assume that the task priority does not change within a mode.
Eg: Rate-Monotonic (RM) Algorithm
Dynamic Priority Algorithms: Assume that the task priority can change with time.
Eg: Earliest Deadline First (EDF) Algorithm
11. Analyze the causes of preemptive and non-preemptive schedule. (AZ)
A schedule is preemptive if tasks can be interrupted by other task (and then resumed). By
contrast, once a task is begun in a non-preemptive schedule, it must be run to completion or until
it gets blocked over a resource.
12. Categorize the difference between release time and deadline. (AZ)
Release time: The time at which all the data that are required to begin executing the task are
available. Deadline: The time by which task must complete its execution.
(i) Absolute Deadline: The time by which the task must be completed.
(ii) Relative Deadline: Absolute Deadline - Release Time
13. Choose some of the fault types based on temporal behavior classification and its conditions.
(AZ)
There are three fault types: permanent, intermittent, and transient. A permanent fault does not
die away with time, but remains until it is repaired or the affected unit is replaced. An intermittent
fault cycles between the fault-active and fault benign states. A transient fault dies away after
some time.
Fault Types Condition
Permanent a(t) > 0, b(t) = c(t) = d(t) =0
Intermittent a(t) > 0, b(t) = 0, c(t) > 0, d(t) = 0
Transient a(t) > 0. b (t)>0, c (t)=0, d(t)> 0
 14. Write down the assumptions made for both the RM and EDF algorithms. (R)
The following assumptions are made for both the RM and EDF algorithms,
A1: No task has any non-preemptable section and the cost of preemption is negligible.
A2: Only processing requirements are significant; memory, I/O, and other resource requirements
are negligible.
A3: All tasks are independent; there are no precedence constraints.
15. Briefly explain how a task assignment is said to be feasible. (E)
A task assignment/scheduling is said to be feasible if all the task start after their release times
and complete before their deadlines. The schedule can be formally defined as a function,
S: Set of Processors × Time → Set of Tasks
16. What are the features that discriminates offline and online scheduling? (E)
Offline Scheduling (Pre-computed): Tasks are scheduled in advance of the operation, with
specifications of when the periodic tasks will be run and slots for the sporadic /aperiodic tasks in
the event that they are invoked.
Online Scheduling (Obtained Dynamically): Tasks are scheduled as they arrive in the system.
The algorithms used in online scheduling must be fast.
17. Discuss about malicious or byzantine failures. (C)
The output of some malicious intelligence that has captured the device and is putting forth
errors in such a way as to cause maximum disruption to the functioning of the system. Such
failures are known as malicious or Byzantine failures. In short, a malicious fault is one that is
assumed to behave arbitrarily.
18. Elaborate about periodic, sporadic and aperiodic tasks. (C)
Periodic Task: A task 𝑇𝑖 is periodic if it is released periodically for every 𝑃𝑖 seconds. The
periodicity constraint requires the task to run exactly once every period.
Sporadic Task: The task is not periodic, but may be invoked at irregular intervals.
Aperiodic Task: The task is not periodic and which also has no upper bound on their invocation
rate.

PART – B

1. Write short notes on

(iii) Introduction of transient faults. (7)
(iv)Use of state aggregation. (6)
2. (i) List out the sequence of events resulting in triad failure. (6)
(ii) Explain the methodology to choose the best distribution. (7)
3. (i) Draw and explain the structure of real time systems. (6)
(ii) Explain Earliest Deadline First algorithm in brief. (7)
4. Describe briefly about the fault toleration technique. (13)
5. Give a detail notes on mathematical understanding of the priority ceiling algorithm using a
series of results. (13)
6. Summarize the important points on :
(i) Obtaining device failure rates. (6)
(ii) Measuring error propagation times. (7)
7. (i) Give a brief note on loss of synchrony. (7)
(ii) Explain the principle of clocks in basic level. (6)
8. (i) Explain the permanent faults in series parallel systems. (7)
(ii) What are the performance measures for real time systems? (6)
9. Apply the knowledge of uniprocessor scheduling algorithms in developing a multiprocessor
schedule. (13)
10. (i) What would be multiprocessor scheduling? (5)
(ii) Inspect how the clocks are synchronized if the times are close to each other. (8)
11. (i) Compare independent failure and correlated failure. (3)
(ii) Examine the process of completely connected zero propagation system. (10)
12. Examine the exponentially distributed fault latency with the condition mean 1/µ. (13)
13. Criticize on reliability models for hardware redundancy. (13)
14. Determine the more general model assuming that the failure process was Poisson and fault
latencies were exponentially distributed. (13)

PART – C

1. Estimate the Techniques for allocating and scheduling tasks on processors to ensure that
deadlines are met. (15)
2. Discuss the preemptive earliest deadline first algorithm. (15)
3. Evaluate utilization bound for the RM algorithm and explain it in detail. (15)
4. Construct the reliability models for hardware redundancy. (15)
 UNIT V - PROCESSES AND OPERATING SYSTEMS
Introduction – Multiple tasks and multiple processes – Multirate systems- Preemptive real-time
operating systems- Priority based scheduling- Interprocess communication mechanisms – Evaluating
operating system performance- power optimization strategies for processes – Example Real time
operating systems-POSIXWindows CE. - Distributed embedded systems – MPSoCs and shared
memory multiprocessors. – Design Example - Audio player, Engine control unit – Video accelerator.

PART – A

1. Mention the networks for distributed embedded systems. (R)

Networks are used to build distributed embedded systems. The International Standards
Organization (ISO) has developed a seven-layer model for networks known as Open Systems
Interconnection (OSI) models. The OSI model includes seven levels of abstraction:

2. Compare between a process and thread. (AZ)

A process is a program under execution i.e an active program. A thread is a lightweight process that
can be managed independently by a scheduler. Processes require more time for context switching as
they are heavier. Threads require less time for context switching as they are lighter than processes.

3. Differentiate between initiation time and completion time (AZ)

The initiation time is the time when the process actually starts executing, while the completion
time is the time when it finishes.

4. Summarize the essential criteria’s of rate monolithic scheduling. (U)

Rate-monotonic scheduling (RMS) is a priority assignment algorithm used in real-time operating
systems (RTOS) with a static-priority scheduling class. The static priorities are assigned according to
the cycle duration of the job, so a shorter cycle duration result in a higher job priority. These operating
systems are generally pre-emptive and have deterministic guarantees with regard to response times.
Rate monotonic analysis is used in conjunction with those systems to provide scheduling guarantees for
a particular application.

5. Explain priority inversion briefly. (U)

Priority Inversion can occur within embedded systems when using an RTOS configured for
priority based, pre-emptive scheduling. Priority Inversion is a term used to describe a situation
when a higher priority task cannot execute because it is waiting for a low priority task to complete.
6. Recognize the term time quantum? (R)
A preemptive scheduler will allow a particular process to run for a short amount of time
called a quantum (or time slice). After this amount of time, the process is placed back in the ready
queue and another process is placed into the run state (i.e., the scheduler ensures that the processes
take turns to run).

7. Outline the various scheduling states of a process. (U)

The work of choosing the order of running processes is known as scheduling. The operating system
considers a process to be in one of three basic scheduling states: waiting, ready, or executing.

8. Investigate the organization of scheduling policy. (C)

A scheduling policy defines how processes are selected for promotion from the ready state to
the running state. The Operating System maintains the following important process scheduling
queues:
 Job queue − This queue keeps all the processes in the system.
 Ready queue − This queue keeps a set of all processes residing in main memory, ready and
waiting to execute. A new process is always put in this queue.
 Device queues − The processes which are blocked due to unavailability of an I/O device
constitute this queue.

9. What is Semaphore? (R)

A signal between tasks/interrupts that does not carry any additional data. The meaning of
the signal is implied by the semaphore object, so you need one semaphore for each purpose. The
most common type of semaphore is a binary semaphore, that triggers activation of a task. The
typical design pattern is that a task contains a main loop with an RTOS call to “take” the
semaphore. If the semaphore is not yet signalled, the RTOS blocks the task from executing further
until some task or interrupt routine “gives” the semaphore, i.e., signals it.
10. Draw the block diagram of Distributed embedded systems (AP)

11. Evaluate the communication among processes which runs at different rates. (E)
 Interprocess communication mechanisms are provided by the operating system as part of the
process abstraction.
 In general, a process can send a communication in one of two ways: blocking or
nonblocking. After sending a blocking communication, the process goes into the waiting
state until it receives a response. Nonblocking communication allows the process to
continue execution after sending the communication.
 Both types of communication are useful.
 There are two major styles of interprocess communication: shared memory and message
passing.

12. List the advantages and limitations of Priority based process scheduling. (R)
Priority Scheduling is a method of scheduling processes that is based on priority. In this
algorithm, the scheduler selects the tasks to work as per the priority. The processes with higher priority
should be carried out first, whereas jobs with equal priorities are carried out on a round-robin or FCFS
basis. Priority depends upon memory requirements, time requirements, etc.

Advantages:

 Easy to use scheduling method

 Processes are executed on the basis of priority so high priority does not need to wait for long
which saves time
 This method provides a good mechanism where the relative important of each process may be
precisely defined.
 Suitable for applications with fluctuating time and resource requirements.

Disadvantages:

 If the system eventually crashes, all low priority processes get lost.
 If high priority processes take lots of CPU time, then the lower priority processes may starve
and will be postponed for an indefinite time.
 This scheduling algorithm may leave some low priority processes waiting indefinitely.
 A process will be blocked when it is ready to run but has to wait for the CPU because some
other process is running currently.
 If a new higher priority process keeps on coming in the ready queue, then the process which is
in the waiting state may need to wait for a long duration of time.
13. Analyze the multi-processing systems. (AZ)
A multiprocessor system consists of a multiple number of processors, including multi-core
processors, which share main memory and I/O devices. If, in addition to the shared memory, each
processor also has private local memory, it is called a Non-uniform Memory Access (NUMA)
system.

14. Determine the important characteristics of Multitasking. (E)

Multitasking does not require parallel execution of multiple tasks at exactly the same time;
instead, it allows more than one task to advance over a given period of time. Even on multiprocessor
computers, multitasking allows many more tasks to be run than there are CPUs.

15. Design a hard-real-time operating system with an example. (C)

Cars are best example for hard real time operating system with multiprocessing. A car is
controlled by a network of processors that each has its own responsibility but must communicate
with other processors to make sure that the different subsystems act together. Three of the major
subsystems in the car: the engine, the transmission, and the anti-lock braking system (ABS).

16. Identify the principle of multi rate embedded system by quoting three examples. (AP)
Multirate embedded computing systems are very common, including automobile engines,
printers, and cell phones. In all these systems, certain operations must be executed periodically, and
each operation is executed at its own rate.
Examples: Automotive Engine Control, Digital Camera, Cell phones.

17. Brief the blocking and Non-blocking inter process communication. (U)
A process can send a communication in one of two ways: blocking or nonblocking. After sending a
blocking communication, the process goes into the waiting state until it receives a response.
Nonblocking communication allows the process to continue execution after sending the
communication.

18. State the major function of POSIX RTOS? (R)

POSIX is a version of the Unix operating system created by a standards organization. POSIX,
compliant operating systems are source-code compatible, an application can be compiled and run
without modification on a new POSIX platform. While Unix was not originally designed as a real-
time operating system, POSIX has been extended to support realtime requirements. Many RTOSs
are POSIX-compliant and it serves as a good model for basic RTOS techniques. The POSIX
 standard has many options; particular implementations do not have to support all options. All these
options are defined in the system include file unistd.h.

19. Frame the two different styles used for inter process communication. (AP)
There are two major styles of interprocess communication: shared memory and message passing.
Shared Memory Communication:
• Two components, such as CPU and an I/O device, communicate through a shared memory
location.
• The software on the CPU has been designed to know the address of the shared location; the shared
location has also been loaded into the proper register of the I/O device

Message Passing Communication:

• Message passing communication complements the shared memory model. In Figure, each
communicating entity has its own message send/receive unit.
• The message is not stored on the communications link, but rather at the senders/receivers at the
endpoints

PART – B

1. (i) Outline about priority-based scheduling in detail. (7)

rd
Refer page no. 325 - 340 in Marilyn Wolf Book 3 Edition
(ii) With the help of an example, explain that the knowledge of data dependencies can help to
use the CPU more efficiently. (6)
Refer page no. 314 - 316 in Marilyn Wolf Book 3rd Edition
2. (i) Discuss in detail multitasking and multiprocessing. (9)
rd
Refer page no. 308 - 310 in Marilyn Wolf Book 3 Edition
(ii) Illustrate process state and scheduling. (4)
Refer page no. 316 - 317 in Marilyn Wolf Book 3rd Edition
3. (i) Summarize the preemptive real time operating systems in detail. (7)
Refer page no. 319 - 325 in Marilyn Wolf Book 3rd Edition
(ii) Analyze the special characteristics of Processes and Internet with the help of a suitable
diagram.(6)
Refer page no. 329 - 331 in Marilyn Wolf Book 3rd Edition
4. Explain the concepts of Multiprocessor System-On-Chip (MPSoC) and Shared memory
multiprocessor are used in embedded applications. (13)
rd
Refer page no. 331 - 339 in Marilyn Wolf Book 3 Edition
5. Infer in detail about the
(i) Characteristics of distributed embedded System. (7)
rd
Refer page no. 414 - 415 in Marilyn Wolf Book 3 Edition
(ii) Architecture of Distributed Embedded System with neat sketches. (6)
Refer page no. 414 - 430 in Marilyn Wolf Book 3rd Edition
6. (i) Enumerate the context switch mechanism for moving the CPU from one executing process
to another.(7)
Refer page no. 321 - 324 in Marilyn Wolf Book 3rd Edition
(ii) State how the Kernel determines the order of the processes which has to be executed. (6)
Refer page no. 320 - 321 in Marilyn Wolf Book 3rd Edition
7. (i) Evaluate operating system performance. (5)
Refer page no. 344 - 347 in Marilyn Wolf Book 3rd Edition
(ii) Compare the principle, merits and limitations of inter-process communication
mechanisms. (8)
Refer page no. 340 - 344 in Marilyn Wolf Book 3rd Edition
8. (i) Demonstrate in detail about power optimization strategies for CPU operation. (7)
rd
Refer page no. 349 - 352 in Marilyn Wolf Book 3 Edition
(ii) Identify how the Predictive shut down technique proved itself as more sophisticated. (6)
Refer page no. 349 - 350 in Marilyn Wolf Book 3rd Edition
9. (i) Enumerate why an automobile engine requires multi rate control. (4)
Refer page no. 369 - 370 in Marilyn Wolf Book 3rd Edition
(ii) Recall the performance of the Earliest – Deadline – First scheduling with other
scheduling algorithms with suitable example. (9)
Refer page no. 333 - 337 in Marilyn Wolf Book 3rd Edition
10. (i) Describe the real time operating system called POSIX in detail. (7)
rd
Refer page no. 352 - 357 in Marilyn Wolf Book 3 Edition
(ii) Write short notes on power optimization strategies in embedded system. (6)
rd
Refer page no. 349 - 352 in Marilyn Wolf Book 3 Edition
11. (i) Predict the services of operating system in handling multiple tasks and multiple processes.
Refer page no. 308 - 310 in Marilyn Wolf Book 3rd Edition (7)
(ii) Identify the features of preemptive execution with the help of a sequence diagram. (6)
rd
Refer page no. 320 - 322 in Marilyn Wolf Book 3 Edition
12. Briefly explain about the Multirate systems. (13)
Refer page no. 310 - 319 in Marilyn Wolf Book 3rd Edition
13. (i) Investigate this statement with the help of an example. The timing requirements on a set
of process can strongly influence the type of appropriate scheduling. (7)
rd
Refer page no. 311 - 315 in Marilyn Wolf Book 3 Edition
 (ii) Write about a critical section using semaphores in operating system.

(6)
Refer page no. 330 - 331 in Marilyn Wolf Book 3rd Edition
14. (i) Develop an approach for cooperative multitasking in the
PIC16F with the help of aprogram. What would happen if we
put the tasks into Time Handler? (10)
Refer page no. 319 in Marilyn Wolf Book 3rd Edition
(ii) Manipulate about CPU usage metrics. (3)
Refer page no. 316 in Marilyn Wolf Book 3rd Edition
15. (i) Mention in detail about Shared Resources. (7)
Refer page no. 330 - 332 in Marilyn Wolf Book
3rd Edition
(ii) Explain about Windows CE with a neat
diagram. (6)
Refer page no. 357 - 361 in Marilyn Wolf Book
3rd Edition

PART – C

1. From design flow analysis to architectural design, illustrate video

accelerator using UMLmethodology. (15)
Refer page no. 441 - 449 in Marilyn Wolf Book 3rd Edition
2. Formulate the working of Engine control unit in detail.
(i) Theory of operations and requirements. (4)
Refer page no. 369 - 370 in Marilyn Wolf Book 3rd Edition
(ii) Specification (4)
Refer page no. 370 - 371 in Marilyn Wolf Book 3rd Edition
(iii) System Architecture (3)
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(iv) Component designing and testing (2)
Refer page no. 373 in Marilyn Wolf Book 3rd Edition
(v) System integration and testing (2)
Refer page no. 374 in Marilyn Wolf Book 3rd Edition
3. Explain in detail how shared memory and message passing
mechanisms are used forinterprocess communication.
(15)
Refer page no. 340 - 342 in Marilyn Wolf Book 3rd Edition
4. Develop the Multirate system using condition of multi task and
processes? Explain withsuitable example and its necessary
conditions. (15)
Refer page no. 310 - 319 in Marilyn Wolf Book 3rd Edition