NCS333 D-2317376

Operational Amplifier,
Zero-Drift, 10 mV Offset,
0.07 mV/5C
NCS333A, NCV333A,
NCS2333, NCV2333,
NCS4333, NCV4333, www.onsemi.com
NCS333
5 5
The NCS333/2333/4333 family of zero−drift op amps feature offset 1 1
voltage as low as 10 mV over the 1.8 V to 5.5 V supply voltage range. SOT23−5 SC70−5
The zero−drift architecture reduces the offset drift to as low as SN SUFFIX SQ SUFFIX
0.07 mV/°C and enables high precision measurements over both time CASE 483 CASE 419A
and temperature. This family has low power consumption over a wide
dynamic range and is available in space saving packages. These
features make it well suited for signal conditioning circuits in portable,
1
industrial, automotive, medical and consumer markets.
UDFN8 MSOP−8
Features MU SUFFIX DM SUFFIX
• Gain−Bandwidth Product: CASE 517AW CASE 846A−02
♦ 270 kHz (NCx2333)
♦ 350 kHz (NCx333, NCx333A, NCx4333)
8 14
• Low Supply Current: 17 mA (typ at 3.3 V)
1
1
• Low Offset Voltage: SOIC−8 SOIC−14
♦ 10 mV max for NCS333, NCS333A D SUFFIX D SUFFIX
♦ 30 mV max for NCV333A, NCx2333 and NCx4333 CASE 751 CASE 751A
• Low Offset Drift: 0.07 mV/°C max for NCS333/A
• Wide Supply Range: 1.8 V to 5.5 V
14
• Wide Temperature Range: −40°C to +125°C
1
• Rail−to−Rail Input and Output
TSSOP−14 WB
• Available in Single, Dual and Quad Packages DT SUFFIX
• NCV Prefix for Automotive and Other Applications Requiring CASE 948G
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
Applications DEVICE MARKING INFORMATION

See general marking information in the device marking
• Automotive section on page 2 of this data sheet.
• Battery Powered/ Portable Application
• Sensor Signal Conditioning
• Low Voltage Current Sensing ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
• Filter Circuits this data sheet.
• Bridge Circuits
• Medical Instrumentation
© Semiconductor Components Industries, LLC, 2017 1 Publication Order Number:

April, 2021 − Rev. 20 NCS333/D
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
DEVICE MARKING INFORMATION
Single Channel Configuration

NCS333, NCS333A, NCV333A
33XAYWG 33XMG
G G
TSOP−5/SOT23−5 SC70−5
CASE 483 CASE 419A
Dual Channel Configuration

NCS2333, NCV2333
8 8
2333 N2333
33A
AYWG ALYW
YM
1 G G
1 1
UDFN8, 2x2, 0.5P Micro8/MSOP8 SOIC−8

CASE 517AW CASE 846A−02 CASE 751
Quad Channel Configuration

NCS4333, NCV4333
14 14
NCS4333G 4333
AWLYWW ALYWG
G
1
1
SOIC−14
CASE 751A TSSOP−14
CASE 948G
X = Specific Device Code

= E = NCS333 (SOT23−5)
= H = NCS333 (SC70−5)
= G = NCS333A (SOT23−5)
= K = NCS333A (SC70−5)
= M = NCV333A (SOT23−5)
= N = NCV333A (SC70−5)
A = Assembly Location
Y = Year
W = Work Week
M = Date Code
G or G = Pb−Free Package
(Note: Microdot may be in either location)
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2
PIN CONNECTIONS
Single Channel Configuration

NCS333, NCS333A, NCV333A
OUT 1 5 VDD IN+ 1 5 VDD
VSS 2 VSS 2
IN+ 3 4 IN− IN− 3 4 OUT
SOT23−5 / TSOP−5 SC70−5 / SC−88−5 / SOT−353−5
Dual Channel Configuration Quad Channel Configuration

NCS2333, NCV2333 NCS4333, NCV4333
OUT 1 1 8 OUT 1 1 14 OUT 4

VDD
IN− 1 2 − 7 OUT 2 IN− 1 2 − − 13 IN− 4

IN+ 1 3 + − 6 IN− 2 IN+ 1 3 + + 12 IN+ 4
VSS 4 + 5 IN+ 2 VDD 4 11 VSS
UDFN8* / Micro8 / SOIC−8 IN+ 2 5 + + 10 IN+ 3
IN− 2 6 − − 9 IN− 3
*The exposed pad of the UDFN8 package
can be floated or connected to VSS.
OUT 2 7 8 OUT 3
SOIC−14 / TSSOP−14
ORDERING INFORMATION
Channels Device Package Shipping †
Single NCS333SN2T1G SOT23−5 / TSOP−5 3000 / Tape & Reel
NCS333ASN2T1G 3000 / Tape & Reel
NCS333SQ3T2G SC70−5 / SC−88−5 / SOT−353−5 3000 / Tape & Reel
NCS333ASQ3T2G 3000 / Tape & Reel
Dual NCS2333MUTBG UDFN8 3000 / Tape & Reel
NCS2333DR2G SOIC−8 3000 / Tape & Reel
NCS2333DMR2G MICRO−8 4000 / Tape & Reel
Quad NCS4333DR2G SOIC−14 2500 / Tape & Reel
NCS4333DTBR2G TSSOP−14 2500 / Tape & Reel
Automotive Qualified
Channels Device Package Shipping †
Single NCV333ASN2T1G SOT23−5 / TSOP−5 3000 / Tape & Reel
NCV333ASQ3T2G SC70−5 / SC−88−5 / SOT−353−5 3000 / Tape & Reel
Dual NCV2333DR2G SOIC−8 3000 / Tape & Reel
NCV2333DMR2G MICRO−8 4000 / Tape & Reel
Quad NCV4333DR2G SOIC−14 2500 / Tape & Reel
NCV4333DTBR2G TSSOP−14 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
ABSOLUTE MAXIMUM RATINGS

Over operating free−air temperature, unless otherwise stated.
Parameter Rating Unit

Supply Voltage 7 V
INPUT AND OUTPUT PINS
Input Voltage (Note 1) (VSS) − 0.3 to (VDD) + 0.3 V
Input Current (Note 1) ±10 mA
Output Short Circuit Current (Note 2) Continuous
TEMPERATURE
Operating Temperature Range −40 to +125 °C
Storage Temperature Range −65 to +150 °C
Junction Temperature +150 °C
ESD RATINGS (Note 3)
Human Body Model (HBM) ±4000 V
Machine Model (MM) ±200 V
Charged Device Model (CDM) ±2000 V
OTHER RATINGS
Latch−up Current (Note 4) 100 mA
MSL Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Input terminals are diode−clamped to the power−supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less
2. Short−circuit to ground.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC standard JS−001 (AEC−Q100−002)
ESD Machine Model tested per JEDEC standard JESD22−A115 (AEC−Q100−003)
ESD Charged Device Model tested per JEDEC standard JESD22−C101 (AEC−Q100−011)
4. Latch−up Current tested per JEDEC standard: JESD78.
THERMAL INFORMATION (Note 5)

Parameter Symbol Package Value Unit
Thermal Resistance, qJA SOT23−5 / TSOP5 290 °C/W
Junction to Ambient
SC70−5 / SC−88−5 / SOT−353−5 425
Micro8 / MSOP8 298
SOIC−8 250
UDFN8 228
SOIC−14 216
TSSOP−14 155
5. As mounted on an 80x80x1.5 mm FR4 PCB with 650 mm2 and 2 oz (0.07 mm) thick copper heat spreader. Following JEDEC JESD/EIA 51.1,
51.2, 51.3 test guidelines
RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Range Unit
Supply Voltage (VDD − VSS) VS 1.8 to 5.5 V
Specified Operating Temperature Range NCS333 TA −40 to 105 °C
NCx333A, NCx2333, NCx4333 −40 to 125
Input Common Mode Voltage Range VCM VSS−0.1 to VDD+0.1 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V

At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Boldface limits apply over the specified operating temperature range, guaranteed by characterization and/or design.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS VS = +5 V NCS333, NCS333A 3.5 10 mV
NCV333A, 6.0 30
NCx2333, NCx4333
Offset Voltage Drift vs Temp DVOS/DT NCS333, NCS333A 0.03 0.07 mV/°C
NCV333A, VS = 5 V 0.03 0.14
NCx2333, VS = 5 V 0.04 0.07
NCx4333, VS = 5 V 0.095 0.19
Offset Voltage Drift vs Supply DVOS/DVS NCS333, NCS333A Full temperature range 0.32 5 mV/V
NCV333A TA = +25°C 0.40 5
Full temperature range 8
NCx2333, NCx4333 TA = +25°C 0.32 5
Full temperature range 12.6
Input Bias Current IIB TA = +25°C NCS333, NCx333A ±60 ±200 pA
(Note 6)
NCx2333, NCx4333 ±60 ±400
Full temperature range +400
Input Offset Current IOS TA = +25°C NCS333, NCx333A ±50 ±400 pA
(Note 6)
NCx2333, NCx4333 ±50 ±800
Common Mode Rejection Ratio CMRR VS = 1.8 V 111 dB
(Note 7)
VS = 3.3 V 118
VS = 5.0 V NCS333, NCS333A, 106 123
NCx2333, NCx4333
NCV333A 103 123

VS = 5.5 V 127
Input Resistance RIN Differential 180 GW
Common Mode 90
Input Capacitance CIN NCS333 Differential 2.3 pF
Common Mode 4.6
NCx2333, NCx4333, Differential 4.1
NCx333A
Common Mode 7.9
OUTPUT CHARACTERISTICS
Open Loop Voltage Gain AVOL VSS + 100 mV < VO < VDD − 100 mV 106 145 dB
(Note 6)
Open Loop Output Impedance Zout−OL f = UGBW, IO = 0 mA 300 W

Output Voltage High, VOH TA = +25°C 10 50 mV
Referenced to VDD
Output Voltage Low, VOL TA = +25°C 10 50 mV
Referenced to VSS
6. Guaranteed by characterization and/or design
7. Specified over the full common mode range: VSS − 0.1 < VCM < VDD + 0.1
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5
ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V

At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Boldface limits apply over the specified operating temperature range, guaranteed by characterization and/or design.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Current Capability IO Sinking Current NCS333 25 mA
NCx333A, 11
NCx2333, NCx4333
Sourcing Current 5.0

Capacitive Load Drive CL See Figure 13
NOISE PERFORMANCE
Voltage Noise Density eN fIN = 1 kHz 62 nV / √Hz
Voltage Noise eP−P fIN = 0.1 Hz to 10 Hz 1.1 mVPP
fIN = 0.01 Hz to 1 Hz 0.5
Current Noise Density iN fIN = 10 Hz 350 fA / √Hz
Channel Separation NCx2333, NCx4333 135 dB
DYNAMIC PERFORMANCE
Gain Bandwidth Product GBWP CL = 100 pF NCS333, NCx333A, 350 kHz
NCx4333
NCx2333 270
Gain Margin AM CL = 100 pF 18 dB
Phase Margin fM CL = 100 pF 55 °
Slew Rate SR G = +1 0.15 V/ms
POWER SUPPLY
Power Supply Rejection Ratio PSRR NCS333, NCS333A Full temperature 106 130 dB
range
NCx2333, NCx4333, TA = +25°C 106 130
NCV333A
Turn−on Time tON VS = 5 V 100 ms
Quiescent Current IQ NCS333, NCS333A, 1.8 V ≤ VS ≤ 3.3 V 17 25 mA
(Note 8) NCx2333, NCx4333
27
3.3 V < VS ≤ 5.5 V 21 33
35
NCV333A 1.8 V ≤ VS ≤ 3.3 V 20 30
35
3.3 V < VS ≤ 5.5 V 28 40
45
8. No load, per channel
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
TYPICAL CHARACTERISTICS
120 120 120

110
100 105
100 TA = 25°C
80 Phase Margin 90 90
PHASE MARGIN (°)

80
60 75
CMRR (dB)
GAIN (dB)
Gain 70
40 60 60
50
20 45
40
CL = 100 pF
0 RL = 10 kW 30 30
TA = 25°C 20
−20 15
10
−40 0 0
10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 1. Open Loop Gain and Phase Margin Figure 2. CMRR vs. Frequency
vs. Frequency
120 3
TA = 25°C VS = 5.5 V, VOH TA = 25°C
100 2
OUTPUT SWING (V)
80 1 VS = 1.8 V, VOH
+PSRR
PSRR (dB)
60 0
−PSRR VS = 1.8 V, VOL
40 −1
20 −2
VS = 5.5 V, VOL
0 −3
10 100 1k 10k 100k 1M 0 1 2 3 4 5 6 7 8 9 10
FREQUENCY (Hz) OUTPUT CURRENT (mA)
Figure 3. PSRR vs. Frequency Figure 4. Output Voltage Swing vs. Output
Current
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7
200 200
TA = 25°C
150 150
VS = 1.8 V
INPUT BIAS CURRENT (pA)
INPUT BIAS CURRENT (pA)

100 100
IIB+
50 IIB+ 50
0 0 IIB−
IIB−
−50 −50
TA = 25°C
−100 −100
VS = 5 V
−150 −150
−200 −200
−0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 −40 −20 0 20 40 60 80 100
COMMON MODE VOLTAGE (V) TEMPERATURE (°C)
Figure 5. Input Bias Current vs. Common Figure 6. Input Bias Current vs. Temperature
Mode Voltage
30 4 5
VS = 5.5 V
3 4
25
Input
VS = 5.0 V 2 3
20 VS = 3.3 V
1
OUTPUT (V)
2
INPUT (V)
Output
IQ (mA)
15 VS = 1.8 V 0 1
−1 0
10
−2 VS = 5.0 V −1
5 AV = +1
−3 RL = 10 kW −2
Per Channel
0 −4 −3
−40 −20 0 20 40 60 80 100 −100 0 100 200 300 400
TEMPERATURE (°C) TIME (ms)
Figure 7. Quiescent Current vs. Temperature Figure 8. Large Signal Step Response
0.20 1.0 3.0
0.15 0.5 2.5

Input
INPUT AND OUTPUT (V)
Input 0 2.0
0.10 OUTPUT (V)
−0.5 1.5
INPUT (V)
0.05 VS = 5.0 V
VS = 5.0 V −1.0 AV = −10 1.0
0 AV = −1 RL = 10 kW
RL = 10 kW −1.5 Output 0.5
−0.05
−2.0 0
Output
−0.10 −2.5 −0.5
−0.15 −3.0 −1.0
−10 0 10 20 30
TIME (ms) TIME (50 ms/div)
Figure 9. Small Signal Step Response Figure 10. Positive Overvoltage Recovery
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8
3.0 1.0 500

TA = 25°C
2.5 0.5 RL = 10 kW
Output 400
2.0 0
SETTLING TIME (ms)

OUTPUT (V)
1.5 −0.5 300
INPUT (V)
1.0 VS = 5.0 V −1.0

AV = −10
0.5 200
RL = 10 kW −1.5
Input
0 −2.0
100
−0.5 −2.5
−1.0 −3.0 0
1 10 100
TIME (50 ms/div) GAIN (V/V)
Figure 11. Negative Overvoltage Recovery Figure 12. Setting Time to 0.1% vs.
Closed−Loop Gain
65 2000
60
1500 VCM = VS/2
55 RL = 10 kW
50 TA = 25°C 1000 TA = 25°C
45
OVERSHOOT (%)
VOLTAGE (nV)
40 500
35
0
30
25 −500
20
15 −1000
10
−1500
5
0 −2000
10 100 1000 0 1 2 3 4 5 6 7 8 9 10
LOAD CAPACITANCE (pF) TIME (s)
Figure 13. Small−Signal Overshoot vs. Load Figure 14. 0.1 Hz to 10 Hz Noise
Capacitance
1000 1000
CURRENT NOISE DENSITY (fA/√Hz)
VOLTAGE NOISE DENSITY (nV/√Hz)
TA = 25°C
TA = 25°C
100 100
10 10
1 10 100 1000 10,000 1 10 100 1000 10,000
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 15. Voltage Noise Density vs. Figure 16. Current Noise Density vs.
Frequency Frequency
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9
APPLICATIONS INFORMATION
OVERVIEW NCS333 series of precision op amps uses a

The NCS333, NCS333A, NCS2333, and NCS4333 chopper−stabilized architecture, which provides the
precision op amps provide low offset voltage and zero drift advantage of minimizing offset voltage drift over
over temperature. The input common mode voltage range temperature and time. The simplified block diagram is
extends 100 mV beyond the supply rails to allow for sensing shown in Figure 17. Unlike the classical chopper
near ground or VDD. These features make the NCS333 architecture, the chopper stabilized architecture has two
series well−suited for applications where precision is signal paths.
required, such as current sensing and interfacing with
sensors.
Main amp
IN+ +
O
−
IN− − +
+
−
− +
Chopper Chopper RC notch filter RC notch filter
Figure 17. Simplified NCS333 Block Diagram
In Figure 17, the lower signal path is where the chopper cascaded, symmetrical, RC notch filters tuned to the
samples the input offset voltage, which is then used to chopper frequency and its fifth harmonic to reduce aliasing
correct the offset at the output. The offset correction occurs effects.
at a frequency of 125 kHz. The chopper−stabilized The chopper−stabilized architecture also benefits from
architecture is optimized for best performance at the feed−forward path, which is shown as the upper signal
frequencies up to the related Nyquist frequency (1/2 of the path of the block diagram in Figure 17. This is the high speed
offset correction frequency). As the signal frequency signal path that extends the gain bandwidth up to 350 kHz.
exceeds the Nyquist frequency, 62.5 kHz, aliasing may Not only does this help retain high frequency components of
occur at the output. This is an inherent limitation of all the input signal, but it also improves the loop gain at low
chopper and chopper−stabilized architectures. frequencies. This is especially useful for low−side current
Nevertheless, the NCS333 op amps have minimal aliasing sensing and sensor interface applications where the signal is
up to 125 kHz and low aliasing up to 190 kHz when low frequency and the differential voltage is relatively
compared to competitor parts from other manufacturers. small.
ON Semiconductor’s patented approach utilizes two
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10
APPLICATION CIRCUITS sense resistor is less than 100 mW to reduce power loss
Low−Side Current Sensing across the resistor. The op amp amplifies the voltage drop
Low−side current sensing is used to monitor the current across the sense resistor with a gain set by external resistors
through a load. This method can be used to detect R1, R2, R3, and R4 (where R1 = R2, R3 = R4). Precision
over−current conditions and is often used in feedback resistors are required for high accuracy, and the gain is set
control, as shown in Figure 18. A sense resistor is placed in to utilize the full scale of the ADC for the highest resolution.
series with the load to ground. Typically, the value of the
R3
VLOAD
VDD
VDD VDD
Load
R1
Microcontroller
+
RSENSE ADC
control
−
R2
R4
Figure 18. Low−Side Current Sensing
Differential Amplifier for Bridged Circuits produced is relatively small and needs to be amplified before
Sensors to measure strain, pressure, and temperature are going into an ADC. Precision amplifiers are recommended
often configured in a Wheatstone bridge circuit as shown in in these types of applications due to their high gain, low
Figure 19. In the measurement, the voltage change that is noise, and low offset voltage.
VDD
VDD
Figure 19. Bridge Circuit Amplification
EMI Susceptibility and Input Filtering General Layout Guidelines

Op amps have varying amounts of EMI susceptibility. To ensure optimum device performance, it is important to
Semiconductor junctions can pick up and rectify EMI follow good PCB design practices. Place 0.1 mF decoupling
signals, creating an EMI−induced voltage offset at the capacitors as close as possible to the supply pins. Keep traces
output, adding another component to the total error. Input short, utilize a ground plane, choose surface−mount
pins are the most sensitive to EMI. The NCS333 op amp components, and place components as close as possible to
family integrates low−pass filters to decrease sensitivity to the device pins. These techniques will reduce susceptibility
EMI. to electromagnetic interference (EMI). Thermoelectric
effects can create an additional temperature dependent
offset voltage at the input pins. To reduce these effects, use
metals with low thermoelectric−coefficients and prevent
temperature gradients from heat sources or cooling fans.
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11
UDFN8 Package Guidelines center pad can be electrically connected to VSS or it may be
The UDFN8 package has an exposed leadframe die pad on left floating. When connected to VSS, the center pad acts as
the underside of the package. This pad should be soldered to a heat sink, improving the thermal resistance of the part.
the PCB, as shown in the recommended soldering footprint
in the Package Dimensions section of this datasheet. The
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE M
SCALE 2:1
DATE 11 APR 2023
GENERIC MARKING
DIAGRAM*
*This information is generic. Please refer to
device data sheet for actual part marking.
XXXMG Pb−Free indicator, “G” or microdot “G”, may
G or may not be present. Some products may
not follow the Generic Marking.
XXX = Specific Device Code

M = Date Code
G = Pb−Free Package
STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5:

PIN 1. BASE PIN 1. ANODE PIN 1. ANODE 1 PIN 1. SOURCE 1 PIN 1. CATHODE
2. EMITTER 2. EMITTER 2. N/C 2. DRAIN 1/2 2. COMMON ANODE
3. BASE 3. BASE 3. ANODE 2 3. SOURCE 1 3. CATHODE 2
4. COLLECTOR 4. COLLECTOR 4. CATHODE 2 4. GATE 1 4. CATHODE 3
5. COLLECTOR 5. CATHODE 5. CATHODE 1 5. GATE 2 5. CATHODE 4
STYLE 6: STYLE 7: STYLE 8: STYLE 9: Note: Please refer to datasheet for

PIN 1. EMITTER 2 PIN 1. BASE PIN 1. CATHODE PIN 1. ANODE
2. BASE 2 2. EMITTER 2. COLLECTOR 2. CATHODE style callout. If style type is not called
3. EMITTER 1 3. BASE 3. N/C 3. ANODE out in the datasheet refer to the device
4. COLLECTOR 4. COLLECTOR 4. BASE 4. ANODE
5. COLLECTOR 2/BASE 1 5. COLLECTOR 5. EMITTER 5. ANODE datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42984B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: SC−88A (SC−70−5/SOT−353) PAGE 1 OF 1
onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018 www.onsemi.com

PACKAGE DIMENSIONS
TSOP−5
CASE 483
5 ISSUE N
1 DATE 12 AUG 2020
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
NOTE 5 D 5X Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
0.20 C A B 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
2X 0.10 T THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
M 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
5 4 FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
2X 0.20 T S
B FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
1 2 3 EXCEED 0.15 PER SIDE. DIMENSION A.
K 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
B TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
G DETAIL Z
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
A A
MILLIMETERS
TOP VIEW DIM MIN MAX
A 2.85 3.15
B 1.35 1.65
DETAIL Z C 0.90 1.10
J D 0.25 0.50
G 0.95 BSC
C H 0.01 0.10
0.05 J 0.10 0.26
H SEATING K 0.20 0.60
C PLANE
END VIEW M 0_ 10 _
SIDE VIEW S 2.50 3.00
GENERIC
SOLDERING FOOTPRINT*
MARKING DIAGRAM*
1.9
0.074 5 5
0.95
0.037 XXXAYWG XXX MG
G G
1 1
Analog Discrete/Logic
2.4 XXX = Specific Device Code XXX = Specific Device Code

0.094 A = Assembly Location M = Date Code
Y = Year G = Pb−Free Package
1.0 W = Work Week
0.039 G = Pb−Free Package
0.7 *This information is generic. Please refer to
0.028 SCALE 10:1 ǒinches
mm Ǔ
Pb−Free indicator, “G” or microdot “ G”,
*For additional information on our Pb−Free strategy and soldering may or may not be present.
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER: 98ARB18753C Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: TSOP−5 PAGE 1 OF 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

PACKAGE DIMENSIONS
UDFN8, 2x2
CASE 517AW
1
ISSUE A
SCALE 2:1 DATE 13 NOV 2015
D A B NOTES:
L L 1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
L1 3. DIMENSION b APPLIES TO PLATED TERMI-
PIN ONE NALS AND IS MEASURED BETWEEN 0.15
ÇÇ
REFERENCE E DETAIL A AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
ALTERNATE
ÇÇ
CONSTRUCTIONS PAD AS WELL AS THE TERMINALS.
2X 0.10 C 5. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
2X 0.10 C
TOP VIEW
ÇÇ
MOLD CMPD MILLIMETERS
EXPOSED Cu DIM MIN MAX
ÇÇ
ÉÉ
DETAIL B A 0.45 0.55
A A1 0.00 0.05
0.10 C A3 A3 0.13 REF
b 0.18 0.30
D 2.00 BSC
A1 A3 D2 1.50 1.70
0.08 C DETAIL B E 2.00 BSC
NOTE 4 A1 ALTERNATE E2 0.80 1.00
SEATING
SIDE VIEW C PLANE CONSTRUCTION e 0.50 BSC
L 0.20 0.45
L1 −−− 0.15
DETAIL A
D2
8X L
1 4
GENERIC
MARKING DIAGRAM*
E2 1
XX MG
G
8 5
8X b
e 0.10 C A B XX = Specific Device Code
e/2 M = Date Code
0.05 C NOTE 3
BOTTOM VIEW G = Pb−Free Package
RECOMMENDED *This information is generic. Please refer to
SOLDERING FOOTPRINT* device data sheet for actual part marking.
8X Pb−Free indicator, “G” or microdot “ G”,
1.73 0.50
PACKAGE may or may not be present.
OUTLINE
1.00 2.30
1
8X
0.50 0.30
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering

DOCUMENT NUMBER: 98AON34462E Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: UDFN8, 2X2 PAGE 1 OF 1
rights of others.

PACKAGE DIMENSIONS
SOIC−8 NB
8 CASE 751−07
1 ISSUE AK
SCALE 1:1 DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS INCHES
G
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 _ B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H M J K 0.40 1.27 0.016 0.050
D
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M Z Y S X S
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8 8 8 8
XXXXX XXXXX XXXXXX XXXXXX
ALYWX ALYWX AYWW AYWW
1.52
G G
0.060
1 1 1 1
IC IC Discrete Discrete
(Pb−Free) (Pb−Free)
7.0 4.0
XXXXX = Specific Device Code XXXXXX = Specific Device Code
0.275 0.155
A = Assembly Location A = Assembly Location
L = Wafer Lot Y = Year
Y = Year WW = Work Week
W = Work Week G = Pb−Free Package
0.6 1.270 *This information is generic. Please refer to

0.024 0.050 device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
SCALE 6:1 ǒinches
mm Ǔ or may not be present. Some products may
STYLES ON PAGE 2
DESCRIPTION: SOIC−8 NB PAGE 1 OF 2

SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1: STYLE 2: STYLE 3: STYLE 4:
PIN 1. EMITTER PIN 1. COLLECTOR, DIE, #1 PIN 1. DRAIN, DIE #1 PIN 1. ANODE
2. COLLECTOR 2. COLLECTOR, #1 2. DRAIN, #1 2. ANODE
3. COLLECTOR 3. COLLECTOR, #2 3. DRAIN, #2 3. ANODE
4. EMITTER 4. COLLECTOR, #2 4. DRAIN, #2 4. ANODE
5. EMITTER 5. BASE, #2 5. GATE, #2 5. ANODE
6. BASE 6. EMITTER, #2 6. SOURCE, #2 6. ANODE
7. BASE 7. BASE, #1 7. GATE, #1 7. ANODE
8. EMITTER 8. EMITTER, #1 8. SOURCE, #1 8. COMMON CATHODE
PIN 1. DRAIN PIN 1. SOURCE PIN 1. INPUT PIN 1. COLLECTOR, DIE #1
2. DRAIN 2. DRAIN 2. EXTERNAL BYPASS 2. BASE, #1
3. DRAIN 3. DRAIN 3. THIRD STAGE SOURCE 3. BASE, #2
4. DRAIN 4. SOURCE 4. GROUND 4. COLLECTOR, #2
5. GATE 5. SOURCE 5. DRAIN 5. COLLECTOR, #2
6. GATE 6. GATE 6. GATE 3 6. EMITTER, #2
7. SOURCE 7. GATE 7. SECOND STAGE Vd 7. EMITTER, #1
8. SOURCE 8. SOURCE 8. FIRST STAGE Vd 8. COLLECTOR, #1
PIN 1. EMITTER, COMMON PIN 1. GROUND PIN 1. SOURCE 1 PIN 1. SOURCE
2. COLLECTOR, DIE #1 2. BIAS 1 2. GATE 1 2. SOURCE
3. COLLECTOR, DIE #2 3. OUTPUT 3. SOURCE 2 3. SOURCE
4. EMITTER, COMMON 4. GROUND 4. GATE 2 4. GATE
5. EMITTER, COMMON 5. GROUND 5. DRAIN 2 5. DRAIN
6. BASE, DIE #2 6. BIAS 2 6. DRAIN 2 6. DRAIN
7. BASE, DIE #1 7. INPUT 7. DRAIN 1 7. DRAIN
8. EMITTER, COMMON 8. GROUND 8. DRAIN 1 8. DRAIN

PIN 1. N.C. PIN 1. N−SOURCE PIN 1. ANODE 1 PIN 1. EMITTER, DIE #1
2. SOURCE 2. N−GATE 2. ANODE 1 2. BASE, DIE #1
3. SOURCE 3. P−SOURCE 3. ANODE 1 3. EMITTER, DIE #2
4. GATE 4. P−GATE 4. ANODE 1 4. BASE, DIE #2
5. DRAIN 5. P−DRAIN 5. CATHODE, COMMON 5. COLLECTOR, DIE #2
6. DRAIN 6. P−DRAIN 6. CATHODE, COMMON 6. COLLECTOR, DIE #2
7. DRAIN 7. N−DRAIN 7. CATHODE, COMMON 7. COLLECTOR, DIE #1
8. DRAIN 8. N−DRAIN 8. CATHODE, COMMON 8. COLLECTOR, DIE #1

PIN 1. VCC PIN 1. ANODE PIN 1. SOURCE 1 PIN 1. SOURCE (N)
2. V2OUT 2. ANODE 2. GATE 1 2. GATE (N)
3. V1OUT 3. SOURCE 3. SOURCE 2 3. SOURCE (P)
4. TXE 4. GATE 4. GATE 2 4. GATE (P)
5. RXE 5. DRAIN 5. DRAIN 2 5. DRAIN
6. VEE 6. DRAIN 6. MIRROR 2 6. DRAIN
7. GND 7. CATHODE 7. DRAIN 1 7. DRAIN
8. ACC 8. CATHODE 8. MIRROR 1 8. DRAIN
PIN 1. CATHODE 1 PIN 1. I/O LINE 1 PIN 1. LINE 1 IN PIN 1. BASE
2. CATHODE 2 2. COMMON CATHODE/VCC 2. COMMON ANODE/GND 2. EMITTER
3. CATHODE 3 3. COMMON CATHODE/VCC 3. COMMON ANODE/GND 3. COLLECTOR/ANODE
4. CATHODE 4 4. I/O LINE 3 4. LINE 2 IN 4. COLLECTOR/ANODE
5. CATHODE 5 5. COMMON ANODE/GND 5. LINE 2 OUT 5. CATHODE
6. COMMON ANODE 6. I/O LINE 4 6. COMMON ANODE/GND 6. CATHODE
7. COMMON ANODE 7. I/O LINE 5 7. COMMON ANODE/GND 7. COLLECTOR/ANODE
8. CATHODE 6 8. COMMON ANODE/GND 8. LINE 1 OUT 8. COLLECTOR/ANODE

PIN 1. VIN PIN 1. GND PIN 1. ILIMIT PIN 1. SW_TO_GND
2. N/C 2. dv/dt 2. OVLO 2. DASIC_OFF
3. REXT 3. ENABLE 3. UVLO 3. DASIC_SW_DET
4. GND 4. ILIMIT 4. INPUT+ 4. GND
5. IOUT 5. SOURCE 5. SOURCE 5. V_MON
6. IOUT 6. SOURCE 6. SOURCE 6. VBULK
7. IOUT 7. SOURCE 7. SOURCE 7. VBULK
8. IOUT 8. VCC 8. DRAIN 8. VIN
STYLE 29: STYLE 30:
PIN 1. BASE, DIE #1 PIN 1. DRAIN 1
2. EMITTER, #1 2. DRAIN 1
3. BASE, #2 3. GATE 2
4. EMITTER, #2 4. SOURCE 2
5. COLLECTOR, #2 5. SOURCE 1/DRAIN 2
8. COLLECTOR, #1 8. GATE 1

PACKAGE DIMENSIONS
SOIC−14 NB
14 CASE 751A−03
1
ISSUE L
DATE 03 FEB 2016
SCALE 1:1
D A NOTES:
B ASME Y14.5M, 1994.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
0.25 M B M 13X b DIM MIN MAX MIN MAX
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h
A X 45 _
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
0.10 L 0.40 1.25 0.016 0.049
e A1 M
SEATING M 0_ 7_ 0_ 7_
C PLANE
GENERIC
SOLDERING FOOTPRINT* MARKING DIAGRAM*
6.50 14X 14
1.18
XXXXXXXXXG
1 AWLYWW
XXXXX = Specific Device Code

1.27
WL = Wafer Lot
PITCH
Y = Year
WW = Work Week
14X *This information is generic. Please refer to
0.58 device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
STYLES ON PAGE 2

SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016

PIN 1. COMMON CATHODE CANCELLED PIN 1. NO CONNECTION PIN 1. NO CONNECTION
2. ANODE/CATHODE 2. ANODE 2. CATHODE
4. NO CONNECTION 4. NO CONNECTION 4. NO CONNECTION
14. COMMON ANODE 14. COMMON CATHODE 14. COMMON ANODE

PIN 1. COMMON CATHODE PIN 1. CATHODE PIN 1. ANODE/CATHODE PIN 1. COMMON CATHODE
2. ANODE/CATHODE 2. CATHODE 2. COMMON ANODE 2. ANODE/CATHODE
3. ANODE/CATHODE 3. CATHODE 3. COMMON CATHODE 3. ANODE/CATHODE
4. ANODE/CATHODE 4. CATHODE 4. ANODE/CATHODE 4. NO CONNECTION
5. ANODE/CATHODE 5. CATHODE 5. ANODE/CATHODE 5. ANODE/CATHODE
6. NO CONNECTION 6. CATHODE 6. ANODE/CATHODE 6. ANODE/CATHODE
7. COMMON ANODE 7. CATHODE 7. ANODE/CATHODE 7. COMMON ANODE
8. COMMON CATHODE 8. ANODE 8. ANODE/CATHODE 8. COMMON ANODE
9. ANODE/CATHODE 9. ANODE 9. ANODE/CATHODE 9. ANODE/CATHODE
10. ANODE/CATHODE 10. ANODE 10. ANODE/CATHODE 10. ANODE/CATHODE
11. ANODE/CATHODE 11. ANODE 11. COMMON CATHODE 11. NO CONNECTION
12. ANODE/CATHODE 12. ANODE 12. COMMON ANODE 12. ANODE/CATHODE
13. NO CONNECTION 13. ANODE 13. ANODE/CATHODE 13. ANODE/CATHODE
14. COMMON ANODE 14. ANODE 14. ANODE/CATHODE 14. COMMON CATHODE

PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
SCALE 2:1 DATE 16 JUL 2020
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX = Specific Device Code
Y = Year
W = Work Week
STYLE 1: STYLE 2: STYLE 3:
(Note: Microdot may be in either location) PIN 1. SOURCE PIN 1. SOURCE 1 PIN 1. N-SOURCE
2. SOURCE 2. GATE 1 2. N-GATE
*This information is generic. Please refer to 3. SOURCE 3. SOURCE 2 3. P-SOURCE
4. GATE 4. GATE 2 4. P-GATE
device data sheet for actual part marking. 5. DRAIN 5. DRAIN 2 5. P-DRAIN
Pb−Free indicator, “G” or microdot “G”, may 6. DRAIN 6. DRAIN 2 6. P-DRAIN
or may not be present. Some products may 7. DRAIN 7. DRAIN 1 7. N-DRAIN
8. DRAIN 8. DRAIN 1 8. N-DRAIN
DOCUMENT NUMBER: 98ASB14087C Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: MICRO8 PAGE 1 OF 1
rights of others.

PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
14 ISSUE C
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF NOTES:
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
−U− N PROTRUSION. ALLOWABLE DAMBAR
PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IDENT. F IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 7
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
0.15 (0.006) T U S
A K
MILLIMETERS INCHES
K1
ÉÉÉ
ÇÇÇ
−V− DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
ÇÇÇ
ÉÉÉ
B 4.30 4.50 0.169 0.177
J J1 C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N−N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C −W− K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
−T− SEATING D G H DETAIL E
PLANE GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT XXXX
XXXX
7.06
ALYWG
G
1 1
L = Wafer Lot
Y = Year
W = Work Week
0.65 G = Pb−Free Package
PITCH
*This information is generic. Please refer to
14X
14X Pb−Free indicator, “G” or microdot “G”, may
0.36
1.26 or may not be present. Some products may
DOCUMENT NUMBER: 98ASH70246A Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: TSSOP−14 WB PAGE 1 OF 1

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NCS333SN2T1G NCS333SQ3T2G NCS4333DR2G NCS2333DR2G NCS2333DMR2G NCV2333DR2G
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NCV333ASN2T1G NCS4333DTBR2G NCV4333DTBR2G

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Operational Amplifier,

Applications DEVICE MARKING INFORMATION

© Semiconductor Components Industries, LLC, 2017 1 Publication Order Number:

DEVICE MARKING INFORMATION

Single Channel Configuration

Dual Channel Configuration

UDFN8, 2x2, 0.5P Micro8/MSOP8 SOIC−8

Quad Channel Configuration

X = Specific Device Code

(Note: Microdot may be in either location)

Single Channel Configuration

OUT 1 5 VDD IN+ 1 5 VDD

IN+ 3 4 IN− IN− 3 4 OUT

SOT23−5 / TSOP−5 SC70−5 / SC−88−5 / SOT−353−5

Dual Channel Configuration Quad Channel Configuration

OUT 1 1 8 OUT 1 1 14 OUT 4

IN− 1 2 − 7 OUT 2 IN− 1 2 − − 13 IN− 4

UDFN8* / Micro8 / SOIC−8 IN+ 2 5 + + 10 IN+ 3

ABSOLUTE MAXIMUM RATINGS

Parameter Rating Unit

THERMAL INFORMATION (Note 5)

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V

NCV333A 103 123

Open Loop Output Impedance Zout−OL f = UGBW, IO = 0 mA 300 W

ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V

Sourcing Current 5.0

120 120 120

PHASE MARGIN (°)

INPUT BIAS CURRENT (pA)

0.20 1.0 3.0

0.15 0.5 2.5

3.0 1.0 500

SETTLING TIME (ms)

1.0 VS = 5.0 V −1.0

OVERVIEW NCS333 series of precision op amps uses a

Chopper Chopper RC notch filter RC notch filter

Figure 17. Simplified NCS333 Block Diagram

Figure 18. Low−Side Current Sensing

Figure 19. Bridge Circuit Amplification

EMI Susceptibility and Input Filtering General Layout Guidelines

XXX = Specific Device Code

STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5:

STYLE 6: STYLE 7: STYLE 8: STYLE 9: Note: Please refer to datasheet for

DESCRIPTION: SC−88A (SC−70−5/SOT−353) PAGE 1 OF 1

© Semiconductor Components Industries, LLC, 2018 www.onsemi.com

2.4 XXX = Specific Device Code XXX = Specific Device Code

DESCRIPTION: TSOP−5 PAGE 1 OF 1

© Semiconductor Components Industries, LLC, 2018 www.onsemi.com

*For additional information on our Pb−Free strategy and soldering

DESCRIPTION: UDFN8, 2X2 PAGE 1 OF 1

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

0.6 1.270 *This information is generic. Please refer to

DESCRIPTION: SOIC−8 NB PAGE 1 OF 2

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

STYLE 13: STYLE 14: STYLE 15: STYLE 16:

STYLE 17: STYLE 18: STYLE 19: STYLE 20:

STYLE 25: STYLE 26: STYLE 27: STYLE 28: