J Electron Test

DOI 10.1007/s10836-013-5430-8

Counterfeit Integrated Circuits: Detection, Avoidance,

and the Challenges Ahead
Ujjwal Guin · Daniel DiMase ·
Mohammad Tehranipoor

Received: 6 August 2013 / Accepted: 19 December 2013

© Springer Science+Business Media New York 2014

Abstract The counterfeiting of electronic components has 1 Counterfeit ICs: The Problem
become a major challenge in the 21st century. The elec-
tronic component supply chain has been greatly affected by Counterfeiting and piracy are longstanding problems grow-
widespread counterfeit incidents. A specialized service of ing in scope and magnitude. They are of great concern to
testing, detection, and avoidance must be created to tackle government and industry because of (i) the negative impact
the worldwide outbreak of counterfeit integrated circuits they can have on innovation, economic growth, and employ-
(ICs). So far, there are standards and programs in place ment, (ii) the threat they pose to the welfare of consumers,
for outlining the testing, documenting, and reporting proce- (iii) the substantial resources that they channel into crimi-
dures. However, there is not yet enough research addressing nal networks, organized crime, and other groups that disrupt
the detection and avoidance of such counterfeit parts. In this and corrupt society, and finally, (iv) the loss of business
paper we will present, in detail, all types of counterfeits, from the trade in counterfeits [53]. Based on a 2008 report
the defects present in them, and their detection methods. by the International Chamber of Commerce, it was esti-
We will then describe the challenges to implementing these mated that the cost of counterfeiting and piracy for G20
test methods and to their effectiveness. We will present sev- nations was as much as US$775 billion every year and will
eral anti-counterfeit measures to prevent this widespread grow to $1.7 trillion in 2015 [10].
counterfeiting, and we also consider the effectiveness and Innovation in the business sector has always been the
limitations of these anti-counterfeiting techniques. main driver of economic growth, through the development
and implementation of ideas for new products and pro-
Keywords Counterfeit ICs · Counterfeit detection and cesses. These inventions are usually protected via patents,
avoidance · Electronic component supply chain copyrights, and trademarks. However, without adequate
protection of these intellectual property (IP) rights, the
incentives to develop these new ideas and products would be
considerably reduced, thereby weakening critical thinking
and the innovation process [53]. These risks are particularly
high for those industries in which the research and devel-
Responsible Editor: M. Hsiao opment (R&D) costs associated with the development of
U. Guin · M. Tehranipoor () new products are very high compared to the cost of pro-
ECE Department, University of Connecticut, ducing the resulting products. In the world of electronics,
Storrs, CT 06269, USA the R&D costs for the semiconductor industry are indeed
e-mail: [email protected] extremely high, and protection of their IP rights is of the
U. Guin utmost importance.
e-mail: [email protected] Counterfeiting of integrated circuits has become a major
D. DiMase challenge due to deficiencies in the existing test solutions
Honeywell Inc., Morristown, NJ, USA and lack of effective avoidance mechanisms in place. Over
e-mail: [email protected] the past couple of years, numerous reports [69] have pointed
 J Electron Test

Fig. 1 Counterfeit incidents

reported by IHS [7]

to the counterfeiting issues in the US electronics compo- There are a handful of standards that seek to do just this,
nent supply chain. A Senate Armed Services public hearing with more being written and revised. The group respon-
on this issue and its later report clearly identified this as a sible for many of these standards is the G-19 Counterfeit
major issue to address because of its significant impact on Electronic Parts Committee, set forth by SAE International
reliability and security of electronic systems [74, 75]. [59]. Their standards target three different sectors of the
As the complexity of the electronic systems, along with industry: distributors, users, and test service providers (i.e.,
the ICs used in them, has increased significantly over the test laboratories). A collection of the standards that they
past few decades, they are assembled (fabricated) globally have written or are currently working on is as follows:
to reduce the production cost. For example, large foundries (i) AS6081 - Counterfeit Electronic Parts Avoidance, Dis-
located in different countries can offer lower prices to the tributors, (ii) ARP 6178 - Counterfeit Electronic Parts;
design houses. This globalization leads to an illicit mar- Tool for Risk Assessment of Distributors, Distributors &
ket willing to undercut the competition with counterfeit Users, (iii) AS5553 - Counterfeit Electronic Parts; Avoid-
parts. If these parts end up in critical applications like ance, Detection, Mitigation, and Disposition, Users, and
defense, aerospace, or medical systems, the results could be (iv) AS6171 - Test Methods Standard; Counterfeit Elec-
catastrophic [71]. tronic Parts, Test Providers.
Just how big the market is remains a mystery. A study While SAE is the most prominent entity when it comes to
conducted from 2005–2007 reveals that 50 % of original standards, there are a couple of programs designed to help
component manufacturers (OCM) and 55 % of distributors independent distributors gain customers’ trust. Components
(authorized and unauthorized) have encountered counterfeit Technology Institute, Inc. (CTI) [13] has created the Coun-
parts [70]. The Electronic Resellers Association Interna- terfeit Components Avoidance Program (CCAP-101) [15].
tional [19] monitors, investigates, and reports issues that are Independent distributors can be certified as CCAP-101 com-
affecting the global supply chain of electronics. ERAI, in pliant, done by means of a yearly audit. Another program
combination with Information Handling Services Inc. [34], with similar goals has been developed by the Indepen-
has been monitoring and reporting counterfeit component dent Distributors of Electronics Association (IDEA) [33].
statistics dating back to 2001. The most recent data (Fig. 1) A comparison of the SAE’s AS5553, CTI’s CCAP-101,
provided by IHS shows that reports of counterfeit parts have and IDEA’s STD-1010 is available in [14]. The main issue
quadrupled since 2009. with many of these standards is that the “policy” and the
With counterfeit incidents on the rise, it is increasingly
important to analyze the vulnerabilities of the electronic Table 1 Top-5 most counterfeited semiconductors in 2011 (Percent-
component supply chain. Table 1 shows the five most com- age of counterfeit part reports)
monly counterfeited components according to percentage of Rank Commodity type % of reported
reported counterfeit incidents. They are as follows: analog incidents
ICs, microprocessor ICs, memory ICs, programmable logic
ICs, and transistors. Together, these five component groups #1 Analog IC 25.2 %
contribute around 68 %, slightly more than two-thirds, of #2 Microprocessor IC 13.4 %
all counterfeit incidents reported in 2011. Note that in this #3 Memory IC 13.1 %
paper, we will use parts and components interchangeably to #4 Programmable logic IC 8.3 %
refer to semiconductor devices. #5 Transistor 7.6 %
This steady increase of reported incidents reflects the #6 Others 32.4 %
need for effective methods of testing parts and for maintain-
1 Source:
ing proper records as parts travel through the supply chain. IHS parts management 2012 [35]
J Electron Test

“regulations” are their main focus rather than the “technol- 2 Electronic Component Supply Chain Vulnerabilities
ogy”. Thus it is easy for counterfeiters to adapt to the new
regulations circumventing effective detection of counterfeit 2.1 Counterfeit Types
parts.
A counterfeit component (i) is an unauthorized copy; (ii)
Detection and avoidance of counterfeit components are
does not conform to original OCM design, model, and/or
difficult challenges, partly because there are such a wide
performance standards; (iii) is not produced by the OCM
variety of counterfeit types impacting the supply chain. It is or is produced by unauthorized contractors; (iv) is an off-
of the utmost importance to develop a taxonomy of defects specification, defective, or used OCM product sold as “new”
and anomalies present in counterfeit components, to enable or working; or (v) has incorrect or false markings and/or
detection of these components with a group of test methods. documentation [70]. Based on the definitions above and
In this paper, we have developed a comprehensive taxon- analyzing supply chain vulnerabilities, we classify the coun-
omy of counterfeit types, defects and test methods. Our terfeit types into seven distinct categories [25, 26, 28, 29]
contributions include the development of: shown in Fig. 2.

(i) Taxonomy of counterfeit types: We develop a tax- 1) Recycled: The most widely discussed counterfeit types
onomy of counterfeit types to analyze supply chain at the present time are the recycled and remarked
types. It is reported that in today’s supply chain, more
vulnerabilities.
than 80 % of counterfeit components are recycled and
(ii) Taxonomy of counterfeit defects: We develop a
remarked [38]. In the United States, only 25 % of elec-
detailed taxonomy of the defects present in coun- tronic waste was properly recycled in 2009 [73]. That
terfeit ICs. To the best of our knowledge, this is percentage might be lower for many other countries.
the first approach to analyzing counterfeit compo- This huge resource of e-waste allows counterfeiters
nents based on their defects and anomalies. This list to pile up an extremely large supply of counterfeit
of defects and anomalies is based on our detailed components. The components become recycled when
analysis of numerous counterfeit parts in collabo- they are taken from a used system, repackaged and
ration with SAE G-19A, Test Laboratory Standards remarked, and then sold in the market as new. These
Development Subcommittee [58]. recycled parts either may be non-functioning or prior
usage may have done significant damage to the part’s
(iii) Taxonomy of counterfeit detection methods: Our
life or performance.
counterfeit methods taxonomy describes all the test
2) Remarked: In remarking, the counterfeiters remove
methods currently available for counterfeit detection. the old marking on the package (or even on the die)
Test methods for counterfeit detection primarily tar- and mark them again with forged information. During
get all the counterfeit parts already on the market the remarking process, the components’ packages are
(known as obsolete and active parts). sanded or ground down to remove old markings (part
(iv) Taxonomy of counterfeit avoidance methods: The number, date code, country of origin, etc.). Then, to
taxonomy of avoidance methods addresses how to cover the sanding or grinding marks, a new coating is
prevent counterfeit parts from entering into supply created and applied to the component. Components can
chain and to identify counterfeit parts without per- also be remarked to obtain a higher specification than
they are rated for by the original component manufac-
forming the costly and time consuming detection
turer (OCM), e.g., from commercial grade to industrial
methods.
or defense grade.
The rest of the paper is organized as follows. In 3) Overproduced: Today’s high-density integrated cir-
Section 2, we will describe different types of counterfeits cuits are mostly manufactured in state-of-art fabri-
and how they infiltrate the electronic component supply cation facilities. Building or maintaining such facil-
ities for the present CMOS technology is reported
chain. Section 3 will present a detailed taxonomy of coun-
to cost more than several billion dollars and this
terfeit defects. In Section 4, we will describe the taxonomy
number is growing [51]. Given this increasing cost
of counterfeit detection methods. The counterfeit avoidance and the complexity of foundries and their processes,
techniques will be presented in Section 5. We will then dis- the semiconductor business has largely shifted to
cuss challenges to the implementation of current counterfeit a contract foundry business model (horizontal busi-
detection and avoidance technologies. We will conclude the ness model) over the past two decades. This is also
paper in Section 7. true for the assembly where the dies are packaged,
 J Electron Test

Fig. 2 Taxonomy of counterfeit

types Counterfeits

Out-of-spec/ Forged
Recycled Remarked Overproduced Cloned Tampered
Defective Documentation

Performance Pirated IP Fake Certifications Silicon Time

Aged New Fabrication Bomb
Non Outside Contract Manufacturer Reverse
Recycled Forged Changelog Backdoor
Functional Reject Engineered

tested, and shipped to the market. Any untrusted of a component. Archived documentation for older
foundry/assembly that has access to a designer’s IP, designs and older parts may not be available at the
also has the ability to fabricate ICs outside of contract. OCM, making it difficult to verify their authenticity.
They can easily sell excess ICs on the open market. In addition, many organizations have merged or have
4) Out-of-Spec/Defective: The other variation of an been acquired over the years, and information is often
untrusted foundry/assembly sourcing counterfeit com- lost in the transition.
ponents is out of specification or rejected components. 7) Tampered: Tampering can be done during any phase
They may either knowingly sell these components, or of the life cycle of a component. It can either be on
the components may be stolen and sold on open mar- the die level (“hardware Trojan”) or package level.
kets. During manufacturing tests, a component is con- Such components can either act as a silicon time bomb
sidered defective if it produces an incorrect response where the device can behave differently under certain
to even one test vector. Sometimes, the probability of conditions or act as a backdoor where secret informa-
activating a component’s defective node is extremely tion from the chip can be sent out to an adversary. In
small. If these components make their way into the both cases, the chip behaves outside of its specifica-
supply chain, detection will be extremely difficult as tion, and thus we have included such ICs as counterfeit
they produce correct responses in most of the test parts. A detailed taxonomy for tampering a device by
cases. These components can pose a serious threat to hardware Trojans can be found in [68].
the quality and reliability of a system.
5) Cloned: Cloning is commonly used by a wide vari- 2.2 Supply Chain Vulnerability
ety of adversaries/counterfeiters (from small entity to
large corporation) to copy a design in order to reduce Typically an electronic component will go through a process
the large development cost of a component. A cloned shown in Fig. 3. This process includes design, fabrica-
component is an unauthorized production without a tion, assembly, distribution, usage in the system, and finally
legal IP. Cloning can be done in two ways – by reverse end of life. As seen, there are vulnerabilities associated
engineering, and by obtaining IPs illegally. In reverse with each step in this supply chain. In design stage, an IP
engineering, counterfeiters copy designs and then man- may be stolen or a hardware Trojan may be inserted into
ufacture (fabricate) components which are the exact the design. An untrusted foundry or assembly can insert a
copy of their original counterpart. Sometimes cloning hardware Trojan or produce different types of counterfeits.
can be done by copying the – contents of a memory The design house can use illegally obtained IPs in their
used in a tag for electronic chip ID, bitstream targeted designs. Overproduced and out-of-spec/defective parts can
to programmable gate arrays, etc. be entered into the supply chain in the fabrication stage.
6) Forged Documentation: Forged documentation may Untrusted foundries can potentially sell these parts in the
include certifications of compliance for some stan- open market. They can also tamper with the design to cre-
dards or programs, or a revision history or change-log ate a backdoor for getting secret information from the field.

Fig. 3 Electronic components

Overproduction Recycled
supply chain vulnerabilities Out-of-Spec/ Remarked
Cloned Defective Out-of-Spec/
Tampered Tampered Defective
Tampered

End of Life/
Design Fabrication Assembly Distribution Lifetime
Recycling

Recycled
Overproduction Remarked
Out-of-Spec/ All Counterfeit Defective/ Out-of-
Defective Types spec
Tampered Tampered
J Electron Test

These parts also get into the supply chain in the assembly anomalies and defective behavior by them can be attributed
phase. An untrusted assembly can possibly sell these parts to being counterfeit. Figure 4 presents the classification of
or tamper the designs. Illegal activities during distribution, the defects present in the counterfeit components.
in-the-system (lifetime), and end-of-life may bring different
types of counterfeits back into the supply chain (recycled, 3.1 Physical Defects
remarked, etc.).
Physical defects are directly related to the physical proper-
ties of the components. They can be classified as exterior
3 Counterfeit Defects and interior defects, depending on the location of the defects
related to the packaging.
The detection of counterfeit components is a multifaceted
Exterior defects are related to packaging/shipping,
problem. Different types of components (analog, digital,
leads/balls/columns, and package of a component. The
etc.) and counterfeits (discussed in Section 2.1) impact the
most obvious defects will be ones that are associated
detection results. Some counterfeits are easier to detect
with the packaging or shipping the parts arrived in. The
than others and some components are easier to test than
others. To address this, it is of the utmost importance to leads/balls/columns of an IC can show how the part has
develop a taxonomy of defects and anomalies present in been handled if it was previously used. Physically, they
the counterfeit components. By ensuring the detection of should adhere to datasheet specifications, including size and
one or more defects, one can confidently detect counter- shape. The final coating on the leads should conform to the
feit components. A counterfeit part may present anomalies specification sheet. The package of an IC can reveal sig-
on the leads/package, degradation in its performance, or nificant information about the chip. As this is the location
a change in specification. Since we assume, the compo- where all model numbers, country of origin, date codes, and
nents are comprehensively tested by the assembly, any such other information are etched, counterfeiters will try to be

Defects

Physical Electrical

Exterior Interior Parametric Manufacturing

Packaging/ Leads/Balls/ Package Bond Wires Die Process Material Package

Shipping Columns
D45: Transistor D56: Fine D60: Surface
D19: Invalid D34: Missing Vth Variation D52: Missing Cracks
D9: Dents Lot/Date/ D39: Missing Die Contact Passivation and
D1: Invalid Wires Corrosion
Country Code Windows
Lot Code D40: Wrong Die D46: TDDB D57: Crystal
D10: Re-tinned D35: Poor Imperfection
D20: Sanding / Connection D47: Resistive D53: Misaligned D61: Contact
D2: Invalid OCM/ D41: Window Degradation
OEM Shipping Grinding Marks Delamination Open / Short
D11: Incorrect D58: Surface
Labels Dimensions D36: Broken D54: Oxide Impurities
D21: Markings Wires D42: Gross D48: Out-of- D62: Seal Leaks
Cracks Break-down
D3: Invalid OCM/ spec Leakage D59: Improper
D12: Wrong D22: Burned D37: Poor/ Current
OEM Packaging Materials Inconsistent D43: Improper Materials D63: Electromigration
Markings Die Markings D55: Parasitic (Seals, Epoxies,
Lead Dress D49: Out-of- Transistors
D4: No ESD spec. Transient Dielectrics, etc)
Bags for ESD D13: D23:Ghost D38: Double D44: Die Damage/ D64: Mechanical
Contamination Markings Current Interfaces:
Sensitive Wire Bonds Extraneous Intermetallic Growth
Devices Markings D50: Incorrect
D14: Oxidation/ D24: Color Temp. Profile
D5: Missing/ Corrosion Variations/Fade D65: Mechanical
Forged D51: Delay Defects Interfaces: Fatigue
Paperwork D15: Color D25: Improper
Variations Textures
D6: Multiple
Date Codes D16: Tooling D26: Extraneous
within a Lot Marks Markings

D7: Part D17: D27: Dirty Cavities

Orientation Misaligned/
within Packaging missing Balls/ D28: Incorrect
Columns Dimensions/ Weight
D8: Missing/ D18: Distorted/
incorrect MSD D29: High Fine/Gross
Indicators Non-uniform Leak (Hermetic)
Balls/Columns
D30: Package Mold
Variations

D31: Corrosion

D32: Contamination
D33: Package
Damage

Fig. 4 A taxonomy of defects in counterfeit components

 J Electron Test

especially careful not to damage anything and to keep the requires a low power microscope (generally less than
package looking as authentic as possible. 10X magnification) to inspect the exterior of the CUT.
Interior defects are mainly divided into two types: bond The markings on genuine components tend to be clear
wire and die-related defects. Some common defects related and identical. The internal structure of the CUTs are
to bond wires are missing/broken bond wires inside the analyzed using X-Ray imaging. If a known good com-
package, a poor connection between the die and bond ponent (golden model) is available, one can compare
wire, etc. The die reveals a significant amount of relevant the images taken from the CUT with this golden model.
information regarding the component. Die-related defects 2) Exterior Test: The exterior part of the package and
include die markings, cracks, etc. leads of the CUT are being analyzed by using exterior
tests. In package configuration and dimension analy-
3.2 Electrical Defects sis, the physical dimensions of the CUTs are measured
either by hand-held or automated test equipment. Any
Typical electrical defects can be classified into two distinct abnormal deviation of measurement from the specifi-
categories, namely parametric defects and manufacturing cation sheet indicates that the CUT may be counterfeit.
defects. Parametric defects are shifts in component param- Blacktop testing is the procedure of testing the marking
eters due to prior usage or temperature. A shift in circuit permanency of a CUT with various solvents. A non-
parameters due to aging will occur when a chip is used in epoxy blacktop coating should be dissolved in acetone,
the field for some time. Manufacturing defects come from while a thermal or UV-cured epoxy will require the
the fabrication process of components and are classified use of a much more aggressive solvent [45]. Microb-
into three categories – process, material, and package. The lasting analysis is a dry and superfine blasting process.
defects under the process category come from the photo- Various blasting agents with proper grain sizes are
lithography and etching processes during the fabrication. bombarded on the surface (package) of the CUT, and
The defects related to material arise from impurities within the materials are collected for analysis. Some com-
the silicon or oxide layers. The passivation layer provides mon blasting agents are aluminum oxide powder, glass
some form of protection for the die, but failure occurs when beads, sodium bicarbonate powder, etc. Hermiticity
corrosion causes cracks or pin holes. The aluminum layer testing is a special type of package analysis specific to
can easily be contaminated with the presence of sodium and hermetically sealed parts that tests the hermetic seal.
chloride and results in an resistive open defect. The seal on such components ensures its correct oper-
ation in the environment that it was designed for. A
break in this seal leads to the failure of the component.
4 Counterfeit Detection Methods Scanning acoustic microscopy (SAM) is one of the
most efficient, though expensive, ways of studying the
It has become necessary for manufacturers, distributors, structure of a component. This technology functions by
and users of electronic components to inspect all incom- using the reflection or the transmission of ultrasound
ing electronic components for authenticity, especially with waves to generate an image of the component based
parts purchased outside of OCM-authorized distributors. It on its acoustic impedance at various depths. This is
is absolutely necessary to analyze the current counterfeit very useful in detecting delamination [37]. Cracks and
detection methods for the inspection of such parts. In this voids in the die will also be detectable, as well as the
section, we will describe these detection methods in detail. structure of bond wires.
Figure 5 shows the detailed taxonomy of such methods. 3) Interior Test: The internal structures, die and
bond wires, of the CUTs are inspected by
4.1 Physical Inspections delid/decapsulation. There are three mainstream meth-
ods commercially available for decapsulation. These
are chemical, mechanical, or laser-based products.
Physical inspections are performed to examine the phys-
Chemical decapsulation involves etching away the
ical and chemical/material properties of the component’s
package with an acid solution. Newer laser-based tech-
package, leads and die of a component mostly to detect the
niques can remove an area of the package. Mechanical
physical counterfeit defects (Section 3.1).
decapsulation involves grinding the part until the die is
1) Incoming Inspection: When an order is received, it exposed. Once the part has been decapsulated and the
first goes through the incoming inspection. All the required structures exposed, the following tests need
components under test (CUTs) are inspected thor- to be performed:
oughly. In low power visual inspection (LPVI), all the In optical inspection, all the related information
CUTs are strictly documented and inspected. LPVI regarding die and bond wires are properly documented.
J Electron Test

Counterfeit Detection Methods

Physical Inspections Electrical Inspections

Incoming Burn-In Structural

Exterior Tests Interior Tests Material Analysis Parametric Tests Functional Tests
Inspection Tests Tests

DC AC Function
Memory Microprocessor
Verification
Low Power Visual Optical X-Ray
Blacktop Testing Contact Propagation
Inspection Inspection Fluorescence
Test Delay Test MARCH Stuck-at Fault
Microblast (XRF) Functional Fmax
Wire Pull Power Test Analysis Test
X-Ray Imaging Analysis Fourier Transform Set Up / Hold
Consumption
Infrared Spec. Time Test Transition Delay
Package Confg. Die Shear Test
(Hermetic (FTIR) Access Time Fault Test
and dimension
Leakage Test
Analysis Devices) Ion Path Delay
Test
Chromatography Rise / Fall Time Fault Test
Hermeticity
Ball Shear (IO) Output Short Test
Testing
Raman Current Test
Scanning Acoustic Scanning Acoustic Spectroscopy Output Drive
Microscopy (SAM) Microscopy (SAM)
Current Test
Energy Dispersive
Scanning Electron Scanning Electron Spectroscopy Threshold Test
Microscopy (SEM) Microscopy (SEM) (EDS)

Fig. 5 A taxonomy of counterfeit detection methods

The relevant information regarding die markings (com- 4.2 Electrical Inspections
pany logo, date code, chip ID, country of manufacturer,
etc.), bond wire positions, bond types, etc. are to be In this section, we will discuss various manufacturing tests
documented. The integrity of the bonds with the die suitable for detecting the defects and anomalies discussed in
is tested using wire pull. The adhesiveness between Section 3.2. An automatic test equipment (ATE) [23] may
be required for some of these tests.
die and bond wires degrades with time if the compo-
nent is in the field. Comparison of the tension (pulling 1) Parametric Tests: Parametric tests are performed to
force) with the golden and test components determines measure the parameters of a chip [52, 63]. If the chip
whether it was used before or not. In die shear, die has been used before, the DC and AC parameters
attach integrity is verified. This test is applicable to may shift from their specified value (mentioned on the
hermitic devices only. A ball shear test is applied to datasheet). After observing test results from a paramet-
ric test, a decision can be made as to whether or not
verify the ball bond integrity at the die. In scanning
a component is counterfeit. In DC parametric tests,
electron microscopy (SEM), the images of die, pack-
the parametric measurement unit (PMU) of an ATE
age, or leads are taken by scanning it with a focused forces an I/O voltage and current to a steady state and
beam of electrons. If there is an anomaly present in it, it measures the electrical parameters using Ohm’s law.
can easily be detected by SEM. It has an effective reso- The operating conditions are set carefully during mea-
lution up to a few nanometers which refers that the die surement. The DC parametric tests can be classified
can be analyzed down to its gate level. This is useful in different categories - contact test, power consump-
for a thorough analysis of the die. tion test, output short current test, output drive current
4) Material Analysis: The chemical composition of the test, threshold test, etc. Detailed descriptions of each
CUT is verified using material analysis. This is the test can be found in [6]. In AC parametric tests, the
only category of tests that can detect defects and measurement of AC parameters (terminal impedance,
timing, etc.) is performed by using AC voltages with
anomalies related to materials. Defects such as wrong
a set of frequencies. AC parametric tests can be clas-
materials, contamination, oxidation of leads and pack-
sified as follows: rise and fall time tests, set-up, hold
ages, etc., can be detected. There are several tests that
and release time tests, propagation delay tests, etc. A
can perform material analysis. Some of the most pop- different set of parametric tests can also be applied to
ular tests are X-Ray fluorescence (XRF), fourier trans- memories, as in [48]. DC parametric tests include volt-
form infrared spectroscopy(FTIR), ion chromatogra- age bump test, leakage tests, etc. AC parametric tests
phy (IO), Raman spectroscopy, and energy-dispersive include set-up time sensitivity test, access time test,
X-ray spectroscopy (EDS). running time test, etc.
 J Electron Test

2) Functional Tests: Functional tests are the most effi- while implementing anti-counterfeit measures. New mech-
cient way of verifying the functionality of a compo- anisms can be put in place during the design of new chips
nent. A majority of the defects from the defect taxon- that could help to prevent counterfeiting. As obsolete parts
omy (Fig. 4) can be detected by these tests. Any defects are no longer being manufactured, and active parts are being
that impacts the functionality (from some easy defects fabricated based on previous designs and developed masks,
such as missing or broken bond wires, missing or the focus should be on the detection of such counterfeit
wrong dies, etc., to hard to detect defects related to pro- components and the implementation of avoidance measures
cess, material, and package) can be detected. In func- at the package level. As we described earlier, at this point,
tion verification, the functionality of a component is all the standards are in place simply for detection. In this
verified. It determines whether individual components, section, we will briefly discuss various anti-counterfeit mea-
possibly designed with different technologies, func- sures that can be implemented for new, active, and obsolete
tion as a system and produce the expected response. In parts. Figure 6 shows the taxonomy of such anti-counterfeit
memory tests, read/write operations are performed on measures.
a memory to verify its functionality. MARCH tests [6,
48, 67] can be applied for counterfeit detection. Since 5.1 Chip ID
the functions of memories are simple, exhaustive func-
tional testing is possible and is normally used during Techniques to generate chip IDs are based on extract-
manufacturing testing [6]. ing unique features and parameters from a circuit to help
3) Burn-In Test: The reliability of a device is mainly uniquely identify each chip or embedding a unique ID
into the chip during or after fabrication and test. They are
ensured by burn-in [36]. In burn-in, the device is oper-
described in the following:
ated at an elevated temperature to simulate a stress
condition in order to find infant mortality failures and 1) Physically Unclonable Functions: PUFs have
unexpected failures, to assure reliability. Burn-in test received much attention from the hardware security
methods are described in MIL-STD-883 for integrated and cryptography communities as a new approach
circuits and MIL-STD-750 for other discrete compo- for IC identification, authentication, and on-chip key
nents [16, 17]. The implementation of burn-in is very generation [5, 42, 43, 54, 64]. Silicon PUFs exploit
important as it can easily weed out the commercial inherent physical variations (process variations) that
grade components marked as military grade. It can exist in modern integrated circuits. These variations
also remove defective components or those compo- are uncontrollable and unpredictable, making PUFs
nents that were not designed to perform under these suitable for IC identification and authentication [1,
stress conditions. 76]. These variations can help generate a unique signa-
4) Structural Tests: Over the past decade, there has been ture for each IC in a challenge-response form, which
a major shift toward using structural tests [18, 20, 55, allows later identification of genuine ICs. In recent
62] to reduce the overall cost of manufacturing tests. years, various PUF architectures have been proposed.
Structural tests are very effective in detecting manu- They are the arbiter PUF [21, 65], the ring oscillator
facturing defects (discussed in Section 3.2) for out-of- PUF [21, 64], the SRAM PUF [24], etc.
spec/defective counterfeit types. They can detect the PUFs can be used to detect cloned ICs as they gen-
cloned (reversed engineered) counterfeit components erate unique IDs resulting from randomness in the IC
if there are some anomalies in the reverse engineering
process. If the cloned netlist does not match with the Counterfeit Avoidance Methods
genuine netlist for even few gates, some of the struc-
tural test vectors will produce an incorrect response
and the CUT will be flagged as defective. It can Chip ID Package ID
also detect some of the delay defects due to aging in
Physically Unclonable Functions (PUF)
recycled and remarked counterfeit types. DNA Markings
Hardware Metering
Nano-rods
Secure Split Test (SST)
Magnetic PUFs
5 Counterfeit Avoidance Methods Combating Die/IC Recovery (CDIR)

Poly Fuse-based Technology for

Recording Usage Time
The avoidance of counterfeit components from entering
Electronic Chip ID (ECID)
the supply chain is a major challenge. One must consider
all types of components, namely obsolete, active, and new Fig. 6 A taxonomy of counterfeit avoidance techniques
J Electron Test

manufacturing process that cannot be controlled or process, the design house keeps track of the number of
cloned. These unique IDs of the genuine ICs can be activated ICs, which helps to prevent overproduction.
stored in a secured database for future comparison. 3) Secure Split Test: Due to the globalization of the semi-
Overproduced ICs can also be detected, by search- conductor industry and the prohibitively high cost of
ing the chip IDs under authentication in these secured creating foundries and assembly companies for pack-
databases. If no match is found, there is a high proba- aging, test, and burn-in processes, foundries now often
bility that the IC is not registered and is a member of fabricate the wafers/dies, test them, and ship them to
an overproduced type. the assembly. The assembly then packages the dies,
2) Hardware Metering: Hardware metering is a set of tests them, and ships the ICs to the market. The
security protocols that enables the design house to foundry/assembly, however, can ship defective, out-of-
achieve post-fabrication control of the produced ICs. spec, or even overproduced chips to the black market,
The design house can distinguish different ICs pro- as described in Section 2.1. Secure Split-Test (SST)
duced with the same masks, as hardware metering secures the manufacturing test process to prevent coun-
provides a unique way to tag each chip and/or its terfeits, allowing intellectual property (IP) owners to
functionality [39, 40]. Hardware metering approaches protect and meter their IPs [12]. SST introduces hard-
can be either passive or active. Passive approaches ware components for cryptography and to block the
uniquely identify each IC and register the IC using correct functionality of an IC until it is activated by
challenge-response pairs. Later, suspect ICs taken from the IP owner. SST is designed to be resilient against
the market are checked for proper registration [39, 42, different types of attacks to prevent the IC from being
46, 47, 64, 66]. Active metering approaches, however, activated without IP owner’s key. SST introduces the IP
lock each IC until it is unlocked by the IP holder [1, owner back into the manufacturing test process. SST is
2, 4, 8, 32, 57]. This locking is done in a variety of designed to prevent different types of counterfeited ICs
ways, including: (i) initializing ICs to a locked state such as cloned, overproduced, defective/out-of-spec
on power-up [1], (ii) combinational locking by, for ICs.
instance, scattering XOR gates randomly throughout 4) Combating Die / IC Recovery (CDIR): The first
the design [4, 32, 57], and (iii) adding a finite-state CDIR to preventing parts from recycling has been
machine (FSM) which is initially locked and can be presented in [79]. The technique in [79] inserts a light-
unlocked only with the correct sequence of primary weight sensor in the chip to capture the usage of the
inputs [2, 9]. chip in the field and provides an easy detection capa-
Figure 7 shows the design flow of hardware meter- bility. This type of sensor relies on the aging effects
ing. The design house uses the high level design of MOSFETs to change a ring oscillator frequency in
description to identify the best places to insert a lock. comparison with the golden one embedded in the chip.
The design then passes subsequent design phases – As a part used in the field ages because of the wearout
synthesis, place, and route. The foundry receives the mechanisms such as NBTI and HCI, the shift in the fre-
blueprint of the chip in the form of OASIS or GDSII quency of this sensor indicates the level of aging and
files to fabricate the ICs. After manufacturing, the provides a simple readout of the value.
foundry scans the unique ID from each IC and sends it 5) Poly Fuse-Based Technology for Recording Usage
back to the design house. The design house then sends Time: The antifuse-based sensor was first proposed for
the unlock key to the foundry to unlock the IC. In this recycled IC detection [78]. It is composed of counters
and an embedded antifuse memory block. The coun-
ters are used to record the usage time of ICs while
Insertion of Synthesis, its value is continuously stored in an antifuse memory
Original locking Modified place, and
Netlist netlist
block. Since the antifuse memory block is one-time
mechanisms route
programmable, counterfeiters cannot erase the context
during the recycling process. Two different structures
Foundry sends of the AF-based sensor have been proposed to mea-
unique IDs to Locked Fabrication GDSII files sure the usage time of ICs. CAF-based sensor records
design house ICs
the cycle count of the system clock during chip oper-
ation. The usage time of recycled ICs can be reported
Design house ICs are tested by this sensor, and the measurement scale and total
returns keys to and shipped to
unlock ICs the market measurement time could be adjusted according to the
application of ICs. On the other hand, SAF-based sen-
Fig. 7 IC enabling flow by active metering sor uses circuit activity as the trigger (clock) to the
 J Electron Test

counter. A number of signals with low switching prob- varies, so that each set of nanorods is distinct. After the
ability are selected to calculate the usage time. This array of nanorods is grown, it is applied to a chip using
sensor generally requires less area overhead than the a specialized printer. The chip can be authenticated by
CAF-based sensor. comparing the overall pattern and visual properties of
6) Electronic Chip ID (ECID): To track ICs through- each nano-rod to a database.
out the supply chain, each IC can be tagged with a 3) Magnetic PUFs: A magnetic PUF uses the inherent
unique ID. This ID can be easily read during the chip’s characteristics of magnetic stripes for unique identi-
lifetime. The conventional approach for writing the fication [30, 50]. Each magnetic stripe, due to the
unique ID into a non-programmable memory (such as randomness of the creation process, has a noise-like
One-Time-Programmable [OTP], ROM, etc.) require component along with the data that is stored. This
post-fabrication external programming, such as laser noise is unpredictable and difficult to clone, yet is
fuses [3] or electrical fuses (eFuses) [56]. The eFuse is consistent and repeatable, therefore acting as a PUF.
gaining popularity over laser fuses because of its small
area and scalability [56].
6 Detection and Avoidance Challenges
5.2 Package ID
We believe that research in the detection and avoidance
The anti-counterfeit avoidance measures discussed so far of counterfeit electronic components is still in its infancy.
only target new ICs. However, a large portion of the sup- There are major challenges that must be overcome in the
ply chain is populated by active and obsolete components. development of effective test methods. In this section, we
There is no opportunity for adding any extra hardware to will discuss the counterfeit detection and avoidance chal-
create a chip ID in those designs. For tagging such active lenges that must be overcome in the near future.
and obsolete components, we need to create package IDs
that do not require access to designs. No package mod- 6.1 Detection Challenges
ifications are allowed during the generation of package
IDs. These IDs can be used for new components as well. The counterfeit detection standards [15, 33, 60] guide us
DNA markings, nanorods, and magnetic PUFs are the viable to segregate the counterfeit components by recommending
options for creating package IDs. a set of detection methods. However, all these standards
deal mainly with two types of counterfeits – recycled and
1) DNA Markings: Plant DNA is scrambled to cre- remarked. In addition, they focus on existing test techniques
ate new and unique genetic sequences, and these which have proven to be ineffective as counterfeiters con-
sequences of DNA are integrated with inks. These inks tinuously improve their own skills and techniques. Further,
are then applied on the packages of the IC at the end of there are currently no simple methods to verify components
the packaging process. Once the ICs are received, then, as genuine if they belong to the overproduced, cloned, or
authentication includes first checking whether the ink tampered categories. In the following, we will briefly dis-
fluoresces under specific light, and second, sending a cuss the implementation challenges of counterfeit detection
sample of the ink to a lab to verify that the DNA is methods.
in the database of valid sequences [49]. Recently, the
DOD mandated [72] that DNA marking be placed on 1) Physical Inspections: Physical methods generally
the components in order to track them throughout the entail the inspection of the physical structure and the
supply chain. DNA markings have several limitations material analysis of a component. The major chal-
that introduce some serious concerns of their applica- lenges for the implementation of physical inspections
bility in counterfeit avoidance. The fast authentication are:
achieved by observing the fluorescence of the marking (i) Sampling: Most of the physical tests are
under specific light can be imitated by counterfeit- destructive. Sample preparation is extremely
ers, either with invalid DNA or other materials. But important as it directly relates to test confi-
detailed DNA validation is extremely time-consuming dence. If a few counterfeit components are
and costly [61]. mixed with a large batch, the probability
2) Nanorods: In this technique, a microscopic pattern of selecting the counterfeit one for test is
is created by growing an array of nanospheres into extremely small.
nanorods that are less than 100nm long [41]. Each time (ii) Test Time and Cost: The test time and cost are
the process is repeated, the same pattern is created, but major limiting factors in the use of physical
the exact angle and length of each individual nano-rod tests for counterfeit detection. The equipment
J Electron Test

used for physical inspections (e.g., scanning or the information required may no longer be avail-
electron and acoustic microscopy [SEM or able in archived records at the OCM. Burn-in tests are
SAM]) are not custom-designed to detect useful in detecting infant mortality failures of com-
counterfeit parts. It takes several hours (e.g., ponents. However, because of excessive test time and
typically more than 8 hours for SEM anal- cost, these tests are only attractive and useful only for
ysis) to test a single component with good critical and high-risk applications. The implementation
resolution. of structural tests in counterfeit detection is extremely
(iii) Automation: These tests are done in an ad- challenging for several reasons. First, the structural
hoc fashion with no metrics for quantifying tests require total access to the internal scan chains of a
against a set of counterfeit types, anomalies, component. Sometimes, IP owners do not give permis-
and defects. Most of the tests are carried out sion to access their design and disable the internal scan
without automation. chains with a fuse. Second, obsolete parts may not have
(iv) Metrics: Currently, there are no metrics to design for testability (DFT) structures implemented.
evaluate the effectiveness of physical inspec- Finally, analog chips cannot be tested.
tions. The test results mostly depend on the
subject matter experts (SMEs). The decision- 6.2 Avoidance Challenges
making process is entirely dependent on the
operator (or SMEs) – this is indeed error The techniques described in Section 5 pose several concerns
prone. A chip could be considered counter- for counterfeit avoidance. Table 2 presents the comparison
feit in one lab while it could be marked as study of all the different counterfeit avoidance technolo-
authentic in another lab. This was proven gies. We have assigned a score of high, medium, or low,
by a test run by G-19A group, where some depending on effectiveness.
labs reported a chip as counterfeit and others
1) Reliability: This is a major issue that must be over-
labeled it authentic [11].
come for many of these techniques. For example, the
2) Electrical Inspections: Electrical tests have the poten- response of a PUF must be constant for a given chal-
tial to be an efficient means of counterfeit detection, as lenge over a wide range of environmental variations,
they do not have the limitations of physical inspections. ambient noise, and aging. Active hardware metering
However, there are major challenges that are unique does not have a reliability problem. However, its effec-
to electrical tests. In this section, we will briefly dis- tiveness for counterfeit avoidance is yet to be verified.
cuss the limitations of the electrical tests described in There is a serious reliability concern on DNA marking
Section 4.2. as environmental conditions such as high temperatures
Parametric tests are generally very time efficient. can potentially damage the DNA and either make the
However, due to increased process variations and envi- sequence unreadable or change the sequence. The reli-
ronmental variations (temperature, noise, aging, etc.), ability of nanorods and magnetic PUFs have not yet
the electrical parameters of a component vary signifi- been verified.
cantly. It will be very difficult to conclude whether the 2) Uniqueness: This is a measure of uncorrelatedness
variations in the parameters of a component are due to between two chip IDs. Ideally, two IDs should differ
the aging (for recycled and remarked components) or with a probability of 0.5 under the same test conditions.
to the process variations in the circuit. One can per- Better uniqueness makes it difficult for counterfeiters
form a statistical analysis based on the data observed to guess new IDs after obtaining a set of IDs. PUFs
from the parametric tests to determine the confidence and magnetic PUFs produce responses nearly equal to
level that a part is counterfeit with or without a golden the ideal case [31, 44, 77]. Any high-level language
IC. The efficiency of such analysis must be proven on (C/C++, Java, Matlab etc.) can generate a true ran-
a large number of golden and counterfeit parts. dom number, which is generally used as the chip ID.
For functional tests, test program generation for Due to the huge number of base pairs in DNA, there
obsolete and active parts with limited knowledge of are enough sequences to support billions of unique
the part will be extremely difficult, if not impossi- markings. However, fast authentication – observing the
ble. The requirement of having a high-speed tester in specific light – can be easily imitated. The uniqueness
order to apply functional test patterns to chips make it of the marking is based on the number of nanorods in
extremely expensive. It is nearly impossible to get the the pattern and the sensitivity of the measuring device
complete set of test vectors for an obsolete part from to color and intensity of light. Since the exact angle of
the OCM. In some cases, the OCM may no longer exist each individual nano-rod is random, it is very unlikely
 J Electron Test

that the same process will produce the same result, and

Implementation
manually cloning the marking at a nano scale is not

Not verified
Not verified
practical.

Medium

Medium
3) Tamper resistance: This is defined as the difficul-

High
High

High
Low

Low
cost
ties faced by the attacker/counterfeiter when attempt-
ing to disable the counterfeit avoidance system. It

All (digital/analog/RF/etc.)
All (digital/analog/RF/etc.)
All (digital/analog/RF/etc.)
is extremely difficult to clone the IDs generated by
PUFs and magnetic PUFs. The CDIR sensors also pro-
vide high tamper resistance because they use natural
Target component

random process variation. As the poly fuse provides

excellent resistance against tampering, it is hard to alter
Digital ICs
Digital ICs
Digital ICs

Digital ICs
Digital ICs

Digital ICs
the contents in poly fuse-based sensors. It is easy to
clone the ECID, as it static and readable. It is sim-
ple for counterfeiters to imitate the color generated by
DNA markings, during fast authentication. The tamper
Overproduced, out-of-spec/

resistance of nanorods has not yet been verified.

Remarked, overproduced,
Target counterfeit Types

4) Area overhead: This is the area required on the die

Overproduced, cloned

Recycled, remarked

Recycled, remarked
Recycled, remarked

Recycled, remarked

to implement a counterfeit avoidance measure. PUFs,

defective, cloned

Remarked, cloned

CDIR sensors and ECID provide low area overhead

whereas hardware metering, SST, and poly fuse-based
Remarked
cloned

sensors offer medium area overhead. DNA markings,

nanorods, and magnetic PUFs do not require any area
overhead.
5) Target counterfeit types: This represents the
Area overhead

Low/medium

detectable counterfeit types (from the counterfeit tax-

Medium
Medium

onomy discussed in Section 2.1). PUFs and magnetic

Low

Low

Low

PUFs can detect remarked and cloned counterfeit

NA

NA
NA

types. SST can likely detect overproduced, out-of-

spec/defective, and cloned component types. CDIR
Not verified
resistance

and poly fuse-based sensors are designed to target

Medium

Medium
Medium
Tamper

recycled and remarked types. ECID can potentially

High
High

High

High
Low

detect remarked type. DNA markings and nanorods

may possibly be used to detect recycled and remarked
Uniqueness

counterfeit types.
Table 2 Implementation challenges of counterfeit avoidance techniques

Medium
Medium

6) Target components: This describes what type of com-

High

High
High

High

ponents should be targeted for anti-counterfeiting.

NA
NA

NA

DNA markings, nanorods, and magnetic PUFs may be

implemented in both analog and digital components,
Not verified
Not verified
Reliability

whereas the other anti-counterfeit measures can only

Medium
Medium

Medium
Medium

Medium

target digital components.

High
NA

7) Implementation cost: The cost of implementing

a PUF would entail storing and maintaining the
Poly fuse-based technology for recording

challenge-response pairs in a secure database, in addi-

Physically unclonable functions (PUF)

tion to its area overhead. For hardware metering

Combating die/IC recovery (CDIR)

and SST, back-and-forth communication between the

design house and foundry make it expensive to imple-
Electronic chip ID (ECID)

ment. For CDIR and poly fuse-based structures, the

Secure split test (SST)

cost comes from the area overhead. To authenticate the

Avoidance techniques

Hardware metering

ICs, low-cost equipment is required. We need only a

DNA markings

Magnetic PUF

secure database to store the ECID. Thus, the cost from

usage time

area overhead is negligible. The detailed authentica-

Nanorods

tion for identifying the plant DNA applied to the IC is

expensive.
J Electron Test

6.3 Test Selection and Confidence Analysis sufficient. More research is needed to implement effective
test methods that are adaptable, as the counterfeiting pro-
We must make every attempt to stay ahead of counterfeit- cess will become more sophisticated over time. Finally, new,
ers to prevent the widespread infiltration of counterfeit parts low-cost, and robust anti-counterfeit mechanisms must be
into our critical infrastructures. This should begin with a developed.
necessary comprehensive assessment of current detection
technologies. A particular set of methods may be useful Acknowledgments This work was supported in part by the National
when applied to a specific type of components such as Science Foundation under grant CNS 1344271, Missile Defense
Agency, and Honeywell. The authors would like to thank Steve Walters
microprocessors, memories, etc., but the same set of meth- of Honeywell, and the G-19A group members for providing valuable
ods may not extend to others such as analog ICs, transistors, feedback on the defect taxonomy.
etc. Physical methods, on the other hand, can be applied
to all component types. However, some of the methods
are destructive and take hours to implement. As a result, References
sampling is performed to certify a batch of parts by observ-
ing a small number of parts. Electrical methods, on the 1. Alkabani YM, Koushanfar F (2007) Active hardware metering
other hand, are non-destructive and time efficient, but very for intellectual property protection and security. In: Proceed-
difficult to implement. ings of 16th USENIX security symposium on USENIX security
symposium, pp 20:1–20:16
We need to develop a test selection technique [27] that 2. Alkabani Y, Koushanfar F, Potkonjak M (2007) Remote activa-
will consider test time, test cost, and application risks while tion of ICs for piracy prevention and digital right management. In:
recommending a set of tests to detect the defects and anoma- Proceedings of IEEE/ACM international conference on computer-
lies present in counterfeit components with high confidence. aided design, pp 674–677
3. Arndt K, Narayan C, Brintzinger A, Guthrie W, Lachtrupp D,
While selecting a set of tests from the complete test set, one Mauger J, Glimmer D, Lawn S, Dinkel B, Mitwalsky A (1999)
should first be chosen that detects all high frequency defects Reliability of laser activated metal fuses in drams. In: Proceedings
(those that occur most frequently in the counterfeit compo- of IEEE on electronics manufacturing technology symposium,
pp 389–394
nents), to reach a quicker decision as to a component being
4. Baumgarten A, Tyagi A, Zambreno J (2010) Preventing IC piracy
counterfeit. This technique should allow us to perform the using reconfigurable logic barriers. IEEE Des Test of Comput
following: 27(1):66–75
5. Bolotnyy L, Robins G (2007) Physically unclonable function-
1) Risk-Based Analysis: The model should consider based security and privacy in rfid systems. In: Proceedings of
application risks while recommending a set of tests. IEEE international conference on pervasive computing and com-
The test set should be different for different risks. For munications, pp 211–220
6. Bushnell M, Agrawal V (2000) Essentials of electronic testing for
critical applications we need to concentrate on obtain- digital, memory, and mixed-signal VLSI circuits. Springer
ing the maximum test coverage of counterfeit defects 7. Cassell J (2012) Reports of counterfeit parts quadruple since 2009.
irrespective of test time and cost. We should also focus Challenging US Defence Industry and National Security
on test time and cost while developing the test set for 8. Chakraborty R, Bhunia S (2008) Hardware protection and authen-
tication through netlist level obfuscation. In: Proceedings of
other application risks. IEEE/ACM international conference on computer-aided design,
2) Data-Driven Analysis: The model should be devel- pp 674 –677
oped on the data received from Government-Industry 9. Chakraborty R, Bhunia S (2009) HARPOON: an obfuscation-
based SoC design methodology for hardware protection. IEEE
Data Exchange Program, GIDEP [22]. The decision
Trans Comput Aided Des Integr Circ Syst 28(10):1493–1502
that a component is counterfeit must be taken from data 10. Chardonnal D (2011) Impacts of counterfeiting and piracy to reach
rather than from subject matter experts. US$1.7 trillion by 2015
11. CHASE (2013). http://www.chase.uconn.edu/arochase-special-
workshop-on-counterfeit-electronics.php
12. Contreras G, Rahman T, Tehranipoor M (2013) Secure split-
7 Conclusion test for preventing IC piracy by untrusted foundry and assembly.
In: Proceedings of international symposium on fault and defect
In this paper, we have presented all the counterfeit types tolerance in VLSI systems
13. CTI, Components technology institute, Inc. http://www.cti-us.
currently corrupting the electronic component supply chain
com/
and the defects present in them. We have also presented a 14. CTI (2010) Comparison of AS 5553, CTI-CCAP-101B, and
comprehensive taxonomy of the current counterfeit detec- IDEA-STD-1010-A
tion methods. We have described various types of anti- 15. CTI (2011) Certification for coutnerfeit components avoidance
program, http://www.cti-us.com/pdf/CCAP101Certification.pdf
counterfeit measures that prevent counterfeit ICs from 16. Departnent of Defense (2010) Test method standard: microcir-
entering into the supply chain. We believe that current cuits. Available: http://www.landandmaritime.dla.mil/Downloads/
efforts to address the counterfeiting problem are clearly not MilSpec/Docs/MIL-STD-883/std883.pdf
 J Electron Test

17. Departnent of Defense (2012) Test method standard: test 40. Koushanfar F, Qu G (2001) Hardware metering. In: Pro-
methods for semiconductor devices. Available: http:// ceedings IEEE-ACM design automation conference, pp 490–
www.landandmaritime.dla.mil/Downloads/MilSpec/Docs/ 493
MIL-STD-750/std750.pdf 41. Kuemin C, Nowack L, Bozano L, Spencer ND, Wolf H (2012)
18. Eldred RD (1959) Test routines based on symbolic logical state- Oriented assembly of gold nanorods on the single-particle level.
ments. J ACM 6(1):33–37 Adv Funct Materi 22(4):702–708
19. ERAI, Electronic resellers association international (ERAI), 42. Kumar S, Guajardo J, Maes R, Schrijen G-J, Tuyls P (2008)
http://www.erai.com/ Extended abstract: the butterfly puf protecting ip on every fpga.
20. Galey JM, Norby RE, Roth JP (1961) Techniques for the diag- In: Proceedings of IEEE international workshop on hardware-
nosis of switching circuit failures. In: Proceedings of the second oriented security and trust, pp 67–70
annual symposium on switching circuit theory and logical design, 43. Kursawe K, Sadeghi A-R, Schellekens D, Skoric B, Tuyls P
pp 152–160 (2009) Reconfigurable physical unclonable functions—enabling
21. Gassend B, Clarke D, van Dijk M, Devadas S (2002) Silicon phys- technology for tamper-resistant storage. In: Proceedings of IEEE
ical random functions. In: Proceedings of the 9th ACM conference international workshop on hardware-oriented security and trust,
on computer and communications security, ser. CCS ’02. ACM, pp 22–29
New York, pp 148–160 44. Maiti A, Gunreddy V, Schaumont P A systematic method to
22. GIDEP Government-industry data exchange program (GIDEP). evaluate and compare the performance of physical unclonable
http://www.gidep.org/ functions. Available: http://eprint.iacr.org/2011/657.pdf
23. Grochowski A, Bhattacharya D, Viswanathan T, Laker K (1997) 45. Marshall M (2011) Best detection methods for counterfeit compo-
Integrated circuit testing for quality assurance in manufacturing: nents
history, current status, and future trends. IEEE Trans Circ Syst II: 46. Lee J, Lim D, Gassend B, Suh G, van Dijk M, Devadas S
Analog Digit Signal Process 44(8):610–633 (2004) A technique to build a secret key in integrated circuits
24. Guajardo J, Kumar S, Schrijen G-J, Tuyls P (2007) Physical for identification and authentication applications. In: Proceed-
unclonable functions and public-key crypto for fpga ip protec- ings of digest of technical papers on VLSI circuits, pp 176–
tion. In: International conference onfield programmable logic and 179
applications, pp 189–195 47. Lofstrom K, Daasch W, Taylor D (2000) Ic identification cir-
25. Guin U, Tehranipoor M (2013) Counterfeit detection technology cuit using device mismatch. In: Proceedings of IEEE international
assessment. In: GOMACTech solid-state circuits conference, pp 372–373
26. Guin U, Tehranipoor M (2013) On selection of counterfeit ic 48. Mazumder P, Chakraborty K (1996) Testing and testable design
detection methods. In: IEEE north atlantic test workshop (NATW) of high-density random-access memories. Springer
27. Guin U, DiMase D, Tehranipoor M (2014) A comprehensive 49. Miller M, Meraglia J, Hayward J (2012) Traceability in the age
framework for counterfeit defect coverage analysis and detec- of globalization: a proposal for a marking protocol to assure
tion assessment. J Electron Test Theory Appl (JETTA) 30(1). authenticity of electronic parts. In: SAE aerospace electronics and
doi:10.1007/s10836-013-5428-2 avionics systems conference
28. Guin U, Forte D, Tehranipoor M (2013) Anti-Counterfeit tech- 50. Morley RE, Richter EJ, Engel GL (2007) Method and appa-
niques: from design to resign. In: Microprocessor test and verifi- ratus for authenticating a magnetic fingerprint signal using
cation (MTV) an adaptive analog to digital converter. Patent US7 210 627
29. Guin U, Tehranipoor M, DiMase D, Megrdician M (2013) Coun- B2. Available: https://patentimages.storage.googleapis.com/pdfs/
terfeit IC detection and challenges ahead. In: ACM SIGDA US7210627.pdf
30. Hart AD, Meyers LR, Hernandez C, Morley RE, Richter EJ, 51. Mouli C, Carriker W (2007) Future Fab: how software is
Indeck RS (2013) Card authentication system, Patent US8 447 991 helping Intel go nano—and beyond. IEEE Spectr 44(3):38–
B2. Available: https:patentimages.storage.googleapis.com/pdfs/ 43
US8447991.pdf 52. Nelson GF, Boggs WF (1975) Parametric tests meet the challenge
31. Hori Y, Yoshida T, Katashita T, Satoh A (2010) Quantitative and of high-density ICs. Electronics 48(5):108–111
statistical performance evaluation of arbiter physical unclonable 53. OECD (2007) The economic impact of counterfeiting and piracy.
functions on FPGAs. In: International conference on reconfig- http://www.oecd.org/dataoecd/13/12/38707619.pdf
urable computing and FPGAs (ReConFig), pp 298–303 54. Pappu R (2001) Physical one-way functions. Ph.D. dissertation,
Massachusetts Institute of Technology
32. Huang J, Lach J (2008) IC Activation and user authentication for
55. Poage JF (1963) Derivation of optimal tests to detect faults in
security-sensitive systems. In: Proceedings of IEEE international
combinational circuits. In: Proceedings of the symposium on
workshop on hardware-oriented security and trust, pp 76–80
mathematical theory of automata, pp 483–528
33. IDEA, Acceptability of electronic components distributed in the
56. Robson N, Safran J, Kothandaraman C, Cestero A, Chen X,
open market. http://www.idofea.org/products/118-idea-std-1010b
Rajeevakumar R, Leslie A, Moy D, Kirihata T, Iyer S (2007) Elec-
34. IHS, Information handling services Inc. (IHS), http://www.ihs. trically programmable fuse (eFUSE): from memory redundancy to
com/ autonomic chips. In: CICC, pp 799–804
35. IHS iSuppli (2011) Top 5 most counterfeited parts represent a 57. Roy J, Koushanfar F, Markov I (2008) EPIC: ending piracy of
$169 billion potential challenge for global semiconductor market integrated circuits. In: Proceedings on design, automation and test
36. Jensen F, Petersen NE (1982) Burn-in: an engineering approach to in Europe, pp 1069–1074
the design and analysis of burn-in procedures. Wiley 58. SAE, http://www.sae.org/works/committeeHome.do?comtID=
37. Jones J (2009) Counterfeit components and acoustic microscopy TEAG19
38. Kessler LW, Sharpe T (2010) Faked parts detection. Circ Assemb J 59. SAE, SAE International, http://www.sae.org/
Surf Mt Electron Assemb. http://www.circuitsassembly.com/cms/ 60. SAE (2009) Counterfeit electronic parts; avoidance, detection,
component/content/article/159/9937-smt mitigation, and disposition
39. Koushanfar F, Qu G, Potkonjak M (2001) Intellectual property 61. Semiconductor Industry Association (SIA) (2012) Public
metering. In: Information hiding. Springer-Verlag, pp 81–95 comments—DNA authentication marking on items in FSC5962
J Electron Test

62. Seshu S, Freeman DN (1962) The diagnosis of asynchronous Daniel DiMase is the Director of Compliance and Quality at
sequential switching systems. IRE Trans Electron Comput EC- Honeywell International Inc, working in the counterfeit parts preven-
11(4):459–465 tion team for the Aerospace Quality organization. He is involved in
63. Soma M (1993) Fault coverage of dc parametric tests for embed- implementing policies and procedures to mitigate the counterfeit risk,
ded analog amplifiers. In: Proceedings on international test con- and oversees customer and regulatory concerns. He participates in
ference, pp 566–573 standards development activities to deploy industry best practices and
64. Suh G, Devadas S (2007) Physical unclonable functions for procedures, and to create testing solutions for detection of suspect
device authentication and secret key generation. In: Proceedings counterfeit electronic parts. He also contributes in site and supplier
of ACM/IEEE on design automation conference, pp 9–14 audits for Honeywell. He has worked on the NASA Contract Assur-
65. Suh GE, Clarke D, Gassend B, van Dijk M, Devadas S (2003) ance Services team assisting NASA centers become compliant to
Aegis: architecture for tamper-evident and tamper-resistant pro- NASA policy and the AS5553 standard for mitigating counterfeit
cessing. In: Proceedings of the 17th annual international con- electronic parts.
ference on supercomputing, ser. ICS ’03. New York, ACM, Mr. DiMase is an active participant in SAE Internationals G-19
pp 160–171 Counterfeit Electronic Parts Document Development group. He is co-
66. Su Y, Holleman J, Otis B (2007) A 1.6pj/bit 96 circuit using chairman of the Test Laboratory Standards Development committee,
process variations. In: Proceedings of IEEE international on solid- co-chairman of the Distributor Process Rating committee, and actively
state circuits conference, pp 406–611 participates on the Counterfeit Electronic Parts standard development
67. Suk D, Reddy S (1981) A march test for functional faults in committee for distributors. Among other committees, has been active
semiconductor random access memories. IEEE Trans Comput in the executive committee of the Aerospace Industry Associations
C-30(12):982–985 Counterfeit Parts Integrated Projects Team. He is on the Department of
68. Tehranipoor M, Koushanfar F (2010) A survey of hardware trojan Homeland Securitys Customs and Border Protection Advisory Com-
taxonomy and detection. IEEE Des Test Comput 27(1):10–25 mittee on Commercial Operations of CBP in the Intellectual Property
69. trust-HUB http://trust-hub.org/home Rights subcommittee. He received a special recognition award at the
70. US (2010) Department Of commerce, defense industrial base DMSMS and Standardization 2011 Conference for his leadership role
assessment: counterfeit electronics in mitigating counterfeit parts.
71. US Congress (2011) Ike skelton national defense authoriza- Dan DiMase has over 20 years of industry experience, previously
tion act for fiscal year. Available: http://www.gpo.gov/fdsys/pkg/ serving in leadership positions as president of SemiXchange, Inc. and
BILLS-111hr6523enr/pdf/BILLS-111hr6523enr.pdf ERAI. He is a results-oriented leader proficient in supply-chain, oper-
72. US Defense Logistics Agency (2012) Dna authentication marking ations and finance, with cross functional expertise in numerous areas,
on items in fsc 5962. Available: https://www.dibbs.bsm.dla.mil/ including international logistics, global sourcing, risk management,
notices/msgdspl.aspx?msgid=685 and strategic planning. He has a Six-Sigma Green Certificate from
73. US Environmental Protection Agency (2011) Electronic waste Bryant University. He received his Bachelor of Science degree in Elec-
management in the united states through 2009 trical Engineering from The University of Rhode Island. He has an
74. US Senate Committee on armed services (2012) Inquiry into Executive MBA from Northeastern University.
counterfeit electronic parts in the department of defence supply
chain
75. US Senate Committee on armed services (2012) Suspect counter- Mohammad Tehranipoor is currently the F.L. Castleman Associate
feit electronic parts can be found on internet purchasing platforms, Professor in Engineering Innovation at the University of Connecti-
Available: http://www.gao.gov/assets/590/588736.pdf cut. His current research projects include: computer-aided design and
76. Wang X, Tehranipoor M (2010) Novel physical unclonable func- test for CMOS VLSI designs, reliable systems design at nanoscale,
tion with process and environmental variations. In: Proceedings on counterfeit electroincs detection and prevention, supply chain risk
design, automation test in europe conference exhibition (DATE), management, and hardware security and trust. Dr. Tehranipoor has
pp 1065–1070 published over 200 journal articles and refereed conference papers and
77. Yu M-DM, Sowell R, Singh A, M’Rahi D, Devadas S (2012) Per- has given more than 110 invited talks and keynote addresses since
formance metrics and empirical results of a PUF cryptographic 2006. He has published four books and ten book chapters. He is a
key generation ASIC. In: HOST, pp 108–115 recipient of several best paper awards as well as the 2008 IEEE Com-
78. Zhang X, Tehranipoor M (2013) Design of on-chip light-weight puter Society (CS) Meritorious Service Award, the 2012 IEEE CS
sensors for effective detection of recycled ICs. In: IEEE transac- Outstanding Contribution, the 2009 NSF CAREER Award, the 2009
tions on VLSI systems UConn ECE Research Excellence Award, and the 2012 UConn SOE
79. Zhang X, Tuzzio N, Tehranipoor M (2012) Identification of recov- Outstanding Faculty Advisor Award.
ered ICs using fingerprints from a light-weight on-chip sensor. He serves on the program committee of more than a dozen of lead-
In: Proceedings on IEEE-ACM design automation conference, ing conferences and workshops. He served as Program Chair of the
pp 703–708 2007 IEEE Defect-Based Testing (DBT) workshop, Program Chair of
the 2008 IEEE Defect and Data Driven Testing (D3T) workshop, Co-
program Chair of the 2008 International Symposium on Defect and
Fault Tolerance in VLSI Systems (DFTS), General Chair for D3T-2009
Ujjwal Guin is a doctoral student at the Electrical and Computer and DFTS-2009, and Vice-general Chair for NATW-2011. He co-
Engineering Department, University of Connecticut. He received his founded a new symposium called IEEE International Symposium on
B.E. degree from Department of Electronics and Telecommunication Hardware-Oriented Security and Trust (HOST) and served as HOST-
Engineering, Bengal Engineering and Science University, India and 2008 and HOST-2009 General Chair and Chair of Steering Committee.
M.Sc. degree from Department of Electrical and Computer Engineer- He is currently serving as an Associate EIC for IEEE Design & Test,
ing, Temple University in 2004 and 2010, respectively. He is an active an Associate Editor for JETTA, an Associate Editor for Journal of Low
participant in SAE International’s G-19A Test Laboratory Standards Power Electronics (JOLPE), an IEEE Distinguished Speaker, and an
Development Committee. His current research interests include coun- ACM Distinguished Speaker. Dr. Tehranipoor is a Senior Member of
terfeit detection and avoidance, hardware security, VLSI testing, and the IEEE and Member of ACM and ACM SIGDA. He is currently
reliability. serving as the director of CHASE center.