Subject Code & Name: CS3691- EMBEDDED SYSTEMS AND IOT

Year/Branch: III YEAR IT Semester: V

UNIT I 8-BIT EMBEDDED PROCESSOR

8-Bit Microcontroller – Architecture – Instruction Set and Programming – Programming Parallel

Ports – Timers and Serial Port – Interrupt Handling.

ARCHITECTURE OF 8051 MICROCONTROLLER

Features:

4K bytes internal ROM

128 bytes internal RAM

Four 8-bit I/O ports (P0 - P3).

Two 16-bit timers/counters

One serial interface

only 1 On chip oscillator (external crystal)

6 interrupt sources (2 external , 3 internal, Reset)

64K external code (program) memory(only read)PSEN

64K external data memory(can be read and write) by RD,WR

Code memory is selectable by EA (internal or external)

External memory can be interfaced when data and code storage capacity
exceed size of the internal memory.

ALU - Arithmetic Logical Unit: This unit is used for the arithmetic calculations.
A-Accumulator: This register is used for arithmetic operations. This is also bit addressable and8
bit register.
B-Register: This register is used in only two instructions MUL AB and DIV AB. This is also
bitaddressable and 8 bit register.
PC-Program Counter:
  Points to the address of next instruction to be executed from ROM
 It is 16 bit register means the 8051 can access program address from 0000H to FFFFH. A
total of 64KB of code.
  Initially PC has 0000H
 PC is incremented after each instruction.
Flag Bits and PSW Register:
→ Used to indicate the Arithmetic condition of Accumulator (ACC).
→ Flag register in 8051 is called as program status word (PSW). This special function register
 PSW is also bit addressable and 8 bit wide means each bit can be set or reset independently.

Structure of RAM or 8051 Register Bank and Stack:

  128 byte RAM is available in 8051.
  Address range of RAM is 00H to 7FH.
 In MC8051, 128 byte visible or user accessible RAM is available which is shown in
 figure.
 Extra 128B RAM which is not user accessible. 80H to FFH used for storage of SFR
(special function register)
Four Register Banks:
 There are four register banks, in each register bank there are eight 8 bit register
 available from R0 to R7
 By default Bank 0 is selected. For Bank 0, R0 has address 00H and R1 has 07H
 For selecting banks we use RS0 and RS1 bit of PSW.
Stack in 8051: RAM locations from 08H to 1FH can be used as stack. Stack is used to store the
data temporarily. Stack is last in first out (LIFO)
 8bit register
 It indicates current RAM address available for stack or it points the top of stack.
  Initially by default at 07H because first location of stack is 08H.
 After each PUSH instruction the SP is incremented by one while in
Microprocessor after PUSH instruction SP is decremented.
 After each POP instruction the SP is decremented
 PIN DIAGRAM

8051 microcontroller IC is a 40 Pin Dual Inline Package IC

PIN Details
• The 8051 has an on-chip oscillator but requires an external clock to run it
 A quartz crystal oscillator is connected to inputs XTAL1 (pin19) and XTAL2 (pin18)
 • RESET pin is an input and is active high (normally low)
• Upon applying a high pulse to this pin, the microcontroller will reset and terminate
 allactivities
• EA‟,“external access’’, is an input pin and must be connected to Vcc or GND
• Normally EA pin is connected to Vcc
• EA pin must be connected toGNDto indicate that the code or data isstored externally.
 
• PSEN,“program store enable’’, is an output pin
 • This pin is connected to theOEpin of the external memory.
• For External Code Memory, PSEN‟ = 0
 • For External Data Memory, PSEN‟ = 1
• ALE pin is used for demultiplexing the address and data.
• The four 8-bit I/O ports P0, P1, P2 and P3 each uses 8 pins.
• Port 0 is also designated as AD0-AD7.
• When connecting an 8051 to an external memory, port 0 provides both address and data.
• The 8051 multiplexes address and data through port 0 to save pins.
• ALE indicates if P0 has address or data.
• When ALE=0, it provides data D0-D7
• When ALE=1, it has address A0-A7
• Port 2 must be used along with P0 to provide the 16-bit address for the external memory.
• P0 provides the lower 8 bits via A0 – A7.
• P2 is used for the upper 8 bits of the 16-bit address, designated as A8 – A15, and it cannot
be used for I/O.

I/O & Port PIN Configuration

 Port 0- Alternate function: Multiplexed Address/data bus (AD0-AD7)
Port 1- Alternate function: Only I/O Ports
Port 2- Alternate function: Higher order address bus (A8-A15)
Port 3- Alternate function: Multiple functions.

PORT 0
 Port 0 pins may serve as inputs, outputs, or, when used together, as a bi-directional low
 order address and data bus for external memory.
 When a pin is to be used as an input, a „1‟ must be written to the corresponding port 0 latch
 by the program, thus turning both of the output transistors off,
 When port 0 is used as an address bus to external memory, internal control signals
switch the address lines to the gates of the Field Effect Transistors (FETs).

PORT 1
  Port 1 pins have no dual functions.
 When a pin is to be used as an input, a „1‟ must be written to the corresponding port 1 latch
by the program, thus turning both of the output transistors off.
 To aid in speeding up switching times when the pin is used as an output. the internal FET
pull up has another FET in parallel with it.

PORT 2
 Port 2 may be used as an input/output port similar in operation to port 1.
 The alternate use of port 2 is to supply a high-order address byte in conjunction with
the port 0 low-order byte to address external memory.
 Port 2 pins are momentarily changed by the address control signals when supplying the
high byte of a 16- bit address.

PORT 3
  Port 3 is an input/output port similar to port 1
 The input and output functions can be programmed under the control of the P3 latches or
 under the control of various other special function registers.
 The port 3 alternate uses are shown in the following table
ADDRESSING MODES OF 8051
An "addressing mode" refers to the way of specifying operand in the instruction. In
summary, the addressing modes are as follows, with an example of each:

Immediate Addressing MOV A,#20h

Internal Direct Addressing MOV A,30h
Internal Indirect Addressing MOV A,@R0
External indirect MOVX A,@DPTR

Each of these addressing modes provides important flexibility.

The addressing modes in 8051 are as follows:
Register addressing : e.g., MOV A,R3
Direct byte addressing : e.g., ADD A,50H
Register indirect addressing : e.g., MOV A,@R0
Immediate addressing : e.g., MOV A,#52H
Register Specific : e.g., SWAP A
Index : e.g., MOVC A,@A+DPTR

Immediate Addressing: Immediate addressing is so-named because the value to be stored in

memory immediately follows the operation code in memory. That is to say, the instruction
itself dictates what value will be stored in memory. For example, the instruction: MOV A,#20h

This instruction uses Immediate Addressing because the Accumulator will be loaded with the
value that immediately follows; in this case 20 (hexadecimal). Immediate addressing is very fast
since the value to be loaded is included in the instruction. However, since the value to be loaded
is fixed at compile-time it is not very flexible.

Direct Addressing: Direct addressing is so-named because the value to be stored in memory
is obtained by directly retrieving it from another memory location. For example: MOV A,30h

This instruction will read the data out of Internal RAM address 30 (hexadecimal) and store it in the
Accumulator. Direct addressing is generally fast since, although the value to be loaded is not
included in the instruction, it is quickly accessible since it is stored in the 8051s Internal RAM. It
is also much more flexible than Immediate Addressing since the value to be loaded is whatever is
found at the given address--which may be variable. Also, it is important to note that when using
direct addressing any instruction which refers to an address between 00h and 7Fh is referring to
Internal Memory. Any instruction which refers to an address between 80h and FFh is referring to
the SFR control registers that control the 8051 microcontroller itself.

Indirect Addressing: Indirect addressing is a very powerful addressing mode which in many
cases provides an exceptional level of flexibility. Indirect addressing is also the only way to access
the extra 128 bytes of Internal RAM found on an 8052. Indirect addressing appears as follows:
MOV A,@R0
This instruction causes the 8051 to analyze the value of the R0 register. The 8051 will then load
the accumulator with the value from Internal RAM which is found at the address indicated by R0.
For example, lets say R0 holds the value 40h and Internal RAM address 40h holds the value 67h.

External Indirect
External memory can also be accessed using a form of indirect addressing.
MOVX A,@DPTR and MOVX @DPTR,A
Both commands utilize DPTR. In these instructions, DPTR must first be loaded with the address
of external memory. Once DPTR holds the correct external memory address, the first command
will move the contents of that external memory address into the Accumulator. The second
command will do the opposite: it will allow to write the value of the Accumulator to the external
memory address pointed to by DPTR.
INSTRUCTION SET OF 8051 MICROCONTROLLER

DATA TRANSFER INSTRUCTIONS:

Data transfer instructions move the content of one register to another. The register the content
of which is moved remains unchanged. If they have the suffix “X” (MOVX), the data is
exchanged with external memory.

Data Transfer Instructions

Mnemonic Description Byte Cycle
MOV A,Rn Moves the register to the accumulator 1 1
MOV A,direct Moves the direct byte to the accumulator 2 2
MOV A,@Ri Moves the indirect RAM to the accumulator 1 2
MOV A,#data Moves the immediate data to the accumulator 2 2
MOV Rn,A Moves the accumulator to the register 1 2
MOV Rn,direct Moves the direct byte to the register 2 4
MOV Rn,#data Moves the immediate data to the register 2 2
MOV direct,A Moves the accumulator to the direct byte 2 3
MOV direct,Rn Moves the register to the direct byte 2 3
MOV direct,direct Moves the direct byte to the direct byte 3 4
MOV direct,@Ri Moves the indirect RAM to the direct byte 2 4
MOV direct,#data Moves the immediate data to the direct byte 3 3
MOV @Ri,A Moves the accumulator to the indirect RAM 1 3
MOV @Ri,direct Moves the direct byte to the indirect RAM 2 5
MOV @Ri,#data Moves the immediate data to the indirect RAM 2 3
MOV DPTR,#data Moves a 16-bit data to the data pointer 3 3

MOVC Moves the code byte relative to the DPTR to the accumulator
A,@A+DPTR (address=A+DPTR) 1 3
Moves the code byte relative to the PC to the accumulator
MOVC A,@A+PC (address=A+PC) 1 3
MOVX A,@Ri Moves the external RAM (8-bit address) to the accumulator 1 3-10
MOVX A,@DPTR Moves the external RAM (16-bit address) to the accumulator 1 3-10
MOVX @Ri,A Moves the accumulator to the external RAM (8-bit address) 1 4-11
MOVX @DPTR,A Moves the accumulator to the external RAM (16-bit address) 1 4-11
PUSH direct Pushes the direct byte onto the stack 2 4
POP direct Pops the direct byte from the stack 2 3
XCH A,Rn Exchanges the register with the accumulator 1 2
XCH A,direct Exchanges the direct byte with the accumulator 2 3
XCH A,@Ri Exchanges the indirect RAM with the accumulator 1 3
XCHD A,@Ri Exchanges the low-order nibble indirect RAM with the accumulator 1 3
ARITHMETIC INSTRUCTIONS
Arithmetic instructions perform several basic operations such as addition, subtraction,
division, multiplication etc. After execution, the result is stored in the first operand. For
example:
ADD A,R1 - The result of addition (A+R1) will be stored in the accumulator.
Mnemonic Description
ADD A,Rn Adds the register to the accumulator
ADD A,direct Adds the direct byte to the accumulator
ADD A,@Ri Adds the indirect RAM to the accumulator
ADD A,#data Adds the immediate data to the accumulator
ADDC A,Rn Adds the register to the accumulator with a carry flag
ADDC A,direct Adds the direct byte to the accumulator with a carry flag
ADDC A,@Ri Adds the indirect RAM to the accumulator with a carry flag
ADDC A,#data Adds the immediate data to the accumulator with a carry flag
SUBB A,Rn Subtracts the register from the accumulator with a borrow
SUBB A,direct Subtracts the direct byte from the accumulator with a borrow
SUBB A,@Ri Subtracts the indirect RAM from the accumulator with a borrow
SUBB A,#data Subtracts the immediate data from the accumulator with a borrow
INC A Increments the accumulator by 1
INC Rn Increments the register by 1
INC direct Increments the direct byte by 1
INC @Ri Increments the indirect RAM by 1
DEC A Decrements the accumulator by 1
DEC Rn Decrements the register by 1
DEC direct Decrements the direct byte by 1
DEC @Ri Decrements the indirect RAM by 1
INC DPTR Increments the Data Pointer by 1
MUL AB Multiplies A and B
DIV AB Divides A by B
DA A Decimal adjustment of the accumulator according to BCD code
LOGIC INSTRUCTIONS:
Logic instructions perform logic operations upon corresponding bits of two registers.
After execution, the result is stored in the first operand.

Mnemonic Description
ANL A,Rn AND register to accumulator
ANL A,direct AND direct byte to accumulator
ANL A,@Ri AND indirect RAM to accumulator
ANL A,#data AND immediate data to accumulator
ANL direct,A AND accumulator to direct byte
ANL direct,#data AND immediae data to direct register
ORL A,Rn OR register to accumulator
ORL A,direct OR direct byte to accumulator
ORL A,@Ri OR indirect RAM to accumulator
ORL direct,A OR accumulator to direct byte
ORL direct,#data OR immediate data to direct byte
XRL A,Rn Exclusive OR register to accumulator
XRL A,direct Exclusive OR direct byte to accumulator
XRL A,@Ri Exclusive OR indirect RAM to accumulator
XRL A,#data Exclusive OR immediate data to accumulator
XRL direct,A Exclusive OR accumulator to direct byte
XRL direct,#data Exclusive OR immediate data to direct byte
CLR A Clears the accumulator
CPL A Complements the accumulator (1=0, 0=1)
SWAP A Swaps nibbles within the accumulator
RL A Rotates bits in the accumulator left
RLC A Rotates bits in the accumulator left through carry
RR A Rotates bits in the accumulator right
RRC A Rotates bits in the accumulator right through carry

ROTATE AND SWAP INSTRUCTIONS:

SWAP A Swaps nibbles within the accumulator

RL A Rotates bits in the accumulator left
RLC A Rotates bits in the accumulator left through carry
RR A Rotates bits in the accumulator right
RRC A Rotates bits in the accumulator right through carry

SWAP A - Swaps nibbles within the accumulator

Description: A nibble refers to a group of 4 bits within one register (bit0-bit3 and bit4-bit7).
This instruction interchanges high and low nibbles of the accumulator.
Syntax: SWAP A;
Byte: 1 (instruction code);
STATUS register flags: No flags are affected;
EXAMPLE:
Before execution: A=E1h (11100001)bin.
After execution: A=1Eh (00011110)bin.
RL A - Rotates the accumulator one bit left
Description: Eight bits in the accumulator are rotated one bit left, so that the bit 7 is rotated
into the bit 0 position.
Syntax: RL A;
Byte: 1 (instruction code);
STATUS register flags: No flags affected;

EXAMPLE:
Before execution: A= C2h (11000010 Bin.)
After execution: A=85h (10000101 Bin.)

RLC A - Rotates the accumulator one bit left through the carry flag
Description: All eight bits in the accumulator and carry flag are rotated one bit left. After
this operation, the bit 7 is rotated into the carry flag position and the carry flag is rotated into the bit
0 position.
Syntax: RLC A;
Byte: 1 (instruction code); STATUS register flags: C; EXAMPLE:
Before execution: A= C2h (11000010 Bin.) C=0
After execution: A= 85h (10000100 Bin.) C=1

RR A - Rotates the accumulator one bit right

Description: All eight bits in the accumulator are rotated one bit right so that the bit 0 is
rotated into the bit 7 position.
Syntax: RR A;
Byte: 1 (instruction code);
STATUS register flags: No flags affected;
EXAMPLE:
Before execution: A= C2h (11000010 Bin.)
After execution: A= 61h (01100001 Bin.)
RRC A - Rotates the accumulator one bit right through the carry flag Description: All eight
bits in the accumulator and carry flag are rotated one bit right. After
this operation, the carry flag is rotated into the bit 7 position and the bit 0 is rotated into the
carry flag position.

Syntax: RRC A;
Byte: 1 (instruction code); STATUS register flags: C; EXAMPLE:
Before execution: A= C2h (11000010 Bin.) C=0
After execution: A= 61h (01100001 Bin.) C=0

BRANCH INSTRUCTIONS OR CONTROL TRANSFER INSTRUCTIONS:

There are two kinds of branch instructions:
Unconditional jump instructions: a jump to a new program location is executed without any
condition. Conditional jump instructions: a jump to a new program location is executed only
if a specified condition is met. Otherwise, the program normally proceeds with the next
instruction. Program Control Instructions
The 8051 supports three kind of jump instructions:
1. LJMP (long jump)
2. SJMP (short jump)
LCALL:
This instruction is used to call a subroutine at a specified address. The address is 16 bits long
so the call can be made to any location within the 64KByte memory space. When a LCALL
instruction is executed the current PC content is automatically pushed onto the stack of the PC.
When the program returns from the subroutine the PC contents is returned from the stack so
that the program can resume operation from the point where the LCALL was made The return
from subroutine is achieved using the RET instruction, which simply pops the PC back from
the stack.
ACALL:

The ACALL instruction is logically similar to the LCALL but has a limited address range
similar to the AJMP instruction. CALL is a generic call instruction supported by many 8051
assemblers. The assembler will decide which type of call instruction, LCALL or ACALL, to
use so as to choose the most efficient instruction.

Mnemonic Description
ACALL addr11 Absolute subroutine call
LCALL addr16 Long subroutine call
RET Returns from subroutine
RETI Returns from interrupt subroutine
AJMP addr11 Absolute jump
LJMP addr16 Long jump
Short jump (from –128 to +127 locations relative to the following instruction)
SJMP rel
JC rel Jump if carry flag is set. Short jump.
JNC rel Jump if carry flag is not set. Short jump.
JB bit,rel Jump if direct bit is set. Short jump.
JBC bit,rel Jump if direct bit is set and clears bit. Short jump.
JMP @A+DPTR Jump indirect relative to the DPTR
JZ rel Jump if the accumulator is zero. Short jump.
JNZ rel Jump if the accumulator is not zero. Short jump.
Compares direct byte to the accumulator and jumps if not equal. Short jump.
CJNE A,direct,rel
Compares immediate data to the accumulator and jumps if not equal. Short jump.
CJNE A,#data,rel
CJNE Rn,#data,rel Compares immediate data to the register and jumps if not equal. Short jump.
CJNE Compares immediate data to indirect register and jumps if not equal. Short jump.
@Ri,#data,rel
DJNZ Rn,rel Decrements register and jumps if not 0. Short jump.
DJNZ Rx,rel Decrements direct byte and jump if not 0. Short jump.
NOP No operation
PROGRAMS
8 Bit Addition (Immediate Addressing)
LABEL MNEMONIC OPERAND COMMENTS
CLR C Clear CY Flag
MOV A, data1 Get the data1 in Accumulator
ADDC A, # data 2 Add the data1 with data2
MOV DPTR, #4500H Initialize the memory location
MOVX @ DPTR, A Store the result in memory location
L1 SJMP L1 Stop the program

8 Bit Subtraction (Immediate Addressing)

LABEL MNEMONIC OPERAND COMMENTS
CLR C Clear CY flag
MOV A, # data1 Store data1 in accumulator
SUBB A, # data2 Subtract data2 from data1
MOV DPTR, # 4500 Initialize memory location
MOVX @ DPTR, A Store the difference in memory
location
L1 SJMP L1 Stop

8 Bit Multiplication
LABEL MNEMONIC OPERAND COMMENTS
MOV A ,#data1 Store data1 in accumulator
MOV B, #data2 Store data2 in B reg
MUL A,B Multiply both
MOV DPTR, # Initialize memory location
4500H
MOVX @ DPTR, A Store lower order result
INC DPTR Go to next memory location
MOV A,B Store higher order result
MOV @ DPTR, A
STOP SJMP STOP Stop

8 Bit Division
LABEL MNEMONIC OPERAND COMMENTS
MOV A, # data1 Store data1 in accumulator
MOV B, # data2 Store data2 in B reg
DIV A,B Divide
MOV DPTR, # 4500H Initialize memory location
MOVX @ DPTR, A Store remainder
INC DPTR Go to next memory location
MOV A,B Store quotient
MOV @ DPTR, A
STOP SJMP STOP Stop