This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2944638, IEEE
Transactions on Power Electronics

Finite-Level-State Model Predictive Control for

Sensorless Three-Phase Four-Arm Modular
Multilevel Converter
Xing Liu, Lin Qiu, Member, IEEE, Youtong Fang, Senior Member, IEEE, Zhouhua Peng, Member, IEEE,
and Dan Wang, Senior Member, IEEE

Abstract—This letter focuses on a finite-level-state model extra hardware circuitry are exploited to make the operation
predictive control strategy for sensorless three-phase four-arm transition seamless and reliable for MMC. In [6], four different
modular multilevel converter (MMC). The aim of this letter redundancy control strategies are investigated for reliable and
is to enhance the reliability of the whole system under the stable operation of MMC. In [7], a cascaded open-circuit fault
arm and sensor fault conditions. Firstly, a three-phase four- ride-through technique is presented to enhance the reliability
arm MMC topology, which has a good potential to further
improve the fault tolerance ability of the MMC, is presented.
of MMC. In [8], a fault-tolerant space vector modulation
Next, a novel control strategy for sensorless three-phase four- control scheme for MMC with bypassed faulty submodules
arm MMC is proposed by combining an adaptive linear-neuron- (SMs) is proposed. Although the aforementioned approaches
based submodule voltage estimation scheme with a currentless can improve the reliability of the control system and guarantee
sorting based capacitor-voltage-balancing approach. Thus, the the proper operation of the MMC, fault tolerance and lack
complexity of the control system and the associated costs can of stability under the whole arm and sensor fault conditions
be reduced. Finally, comprehensive experiments are conducted have not been paid sufficient attention among the existing fault
to demonstrate the effectiveness and feasibility of the proposed tolerance researches.
methodology for three-phase four-arm MMC. Motivated by the above observations, aiming at enhancing
Keywords—Finite-level-state model predictive control, three- the reliability of the control system, this letter takes a funda-
phase four-arm modular multilevel converter, submodule voltage mentally different approach. To be specific, a finite-level-state
estimation, fault tolerance. model predictive control (FLS-MPC) methodology for regu-
lated three-phase four-arm MMC is proposed by combining
I. I NTRODUCTION an adaptive linear-neuron-based SM voltage estimation scheme
with a currentless sorting based capacitor-voltage-balancing
The modular multilevel converter (MMC) is a promising approach. To sufficient clear the main contribution of this
topology for high-voltage high-power applications due to the paper, it will be organized as follows. The first one is the
merits of higher efficiency, superior availability, and lower enhancement of the reliability by the proposed methodology.
harmonic distortion [1], [2]. In this topology, it is widely ac- The second one is the reduction of the complexity and the
knowledged that an instrumental role is played as an interface associated costs by eliminating the SMs voltage and arm
between grid and electronic equipments which are supplied current sensors while guaranteeing adaptability to different
with a direct current link (DC-link) voltage. In this sense, fault conditions. Finally, comprehensive experiments are presented
tolerance and lack of stability are well-known challenges for to demonstrate the effectiveness and feasibility of the proposed
MMC [3], [4]. solution for three-phase four-arm MMC.
Recently, numerous research activities have been conducted
as an alternative solution to further circumvent the afore-
mentioned shortcomings [5], [6], [7], [8], [9], [10]. In [5], II. FLS-MPC M ETHOD OF T HREE -P HASE F OUR -A RM
fault diagnosis and fault-tolerant control approaches without MMC

This work was supported in part by the National Natural Science Foundation
The common topology of the three-phase four-arm MMC
of China under Grants 51827810, 51637009, 61673081, 51979020, 51909021, is depicted in Fig. 1. The output voltage of phase-x
0
(x =
51579023, and in part by the Innovative Talents in Universities of Liaoning {a, b, c}) with respect to the DC-link mid-point O can be
Province under Grant LR2017014, and in part by the National Key Research illustrated as [11]
and Development Program of China under Grant 2016YFC0301500, and 
in part by Natural Science Foundation of Zhejiang Province under Grant
LY18E070002, and in part by the Chinese Universities Scientific Fund under
vga = vgaO = vgaO0 + vO0 O ,

Grant 2018QNA4021. (Corresponding authors: Lin Qiu.) vgb = vgbO = vgbO0 + vO0 O , (1)
X. Liu, L. Qiu, and Y. Fang are with the College of Electrical Engineering,

v = v
gc gcO = v 0
gcO O ,
Zhejiang University, Hangzhou 310027, China (e-mail: [email protected];
[email protected]; [email protected]). where vO0 O denotes the voltage between the DC-link midpoint
Z. Peng and D. Wang are with the School of Marine Electrical En- 0
gineering, Dalian Maritime University, Dalian 116026, China (e-mail: zh- O and the point O on the grid-side voltage source.
[email protected]; [email protected]). Without loss of generality, the grid-side dynamic model in

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Transactions on Power Electronics

and C1 and C2 are DC-link capacitor values, respectively.

The predicted grid-side active and reactive powers can be
expressed by using the instantaneous power theory [14]
Pg (k + 1) =1.5 Re {eg (k + 1)īg (k + 1)} (7)
=1.5(egα igα + egβ igβ )
Qg (k + 1) =1.5 Im {eg (k + 1)īg (k + 1)} (8)
=1.5(egβ igα − egα igβ )
where eg (k + 1) is the predicted grid-side voltage.
In cost function, three control objectives are addressed in
terms of active power tracking and reactive power tracking as
well as DC-link capacitor voltage tracking, and then, all these
MMC terms are integrated into a complete cost function:
Fig. 1: Common topology of the three-phase four-arm MMC. fM M C = fM M C1 + fM M C2 + fM M C3 (9)
  ∗ 
fM M C1 = λgp Pg (k + 1) − Pg (k + 1) 
  
∗
fM M C2 = λgq Qg (k + 1) − Qg (k + 1)
 (10)
the αβ stationary reference for the MMC can be obtained as 
fM M C3 = λgd |∆UC12 (k + 1)|

dig
Lz = eg − vg − Rz ig (2) where ∆UC12 (k+1) = UC1 (k+1)−UC2 (k+1). λgp , λgq and
dt
λgd are the weighting factors for the three terms, respectively.
v −v
where vg = glx 2 gux , Rz = Rg + 0.5Rarm , and Lz = In this sense, several empirical approaches are deployed to
Lg + 0.5Larm . eg denotes the grid-side voltage, vglx and determine these weighting factors. Meanwhile, to eliminate the
vgux denote the upper and lower arm voltages, respectively. ig control delay, the cost function in (9) is reorganized to select
denotes the grid-side current, Rg denotes the grid resistance, the optimal voltage vector for the compensation control. Thus,
and Lg denotes the grid filter inductance. It is important the optimal one that minimizes the cost function (11) should
to emphasize that, in our work, the voltage vector can be be applied at instant k + 1 [15].
redefined by (3) according to the presentable output voltage-
level so as to improve the computationally efficient [12], [13], fM M C = fM M C1 + fM M C2 + fM M C3 (11)
and the number of statuses to be determined is reduced to   ∗ 
fM M C1 = λgp Pg (k + 2) − Pg (k + 2) 
  
N + 1. It yields ∗
fM M C2 = λgq Qg (k + 2) − Qg (k + 2) (12)
1 
vg (k) = Udc Ng (3) fM M C3 = λgd |∆UC12 (k + 1)|

N
where where
Pg∗ (k + 2) =10Pg∗ (k) − 20Pg∗ (k − 1) + 15Pg∗ (k − 2) (13)
 
N N −2 N −2 N
Ng = − , − , ..., 0, ..., , (4)
2 2 2 2 − 4Pg∗ (k − 3)
and where N denotes the SM number per arm, and Ng denotes Q∗g (k + 2) =10Q∗g (k) − 20Q∗g (k − 1) + 15Q∗g (k − 2) (14)
the presentable output voltage-level. − 4Q∗g (k − 3).
Then, the discrete-time model of the predicted grid-side
current with respect to the approximate Euler formula is given Furthermore, in order to achieve the SMs capacitor voltage-
as balancing, many SMs voltage and arm current sensors are
required to serve this purpose. It is highly desired that MMC
Rz Ts Ts
ig (k + 1) = (1 − )ig (k) + (eg (k) − vg (k)) (5) can continue its operation without interruption or severe degra-
Lz Lz dation of performance, even though some of the sensors are
where Ts denotes the sampling period. failed. Motivated by the need for reliable and stable operation
Meanwhile, the discrete-time model of the predicted DC- of an MMC in applications, an attractive solution to this issue
link capacitor voltage has the following form: is to present a novel sensorless FLS-MPC scheme, as it will
 be elaborated in the following section.
Ts
UC1 (k + 1) = UC1 (k) + iC1 (k)


C1 III. T HE P ROPOSED S ENSORLESS FLS-MPC S CHEME
(6)
UC2 (k + 1) = UC2 (k) + Ts iC2 (k)

 In this section, in order to enhance the system reliability
C2 and stability, an adaptive linear-neuron-based SM voltage esti-
where UC1 and UC2 denote the DC-link capacitor voltages, mation approach is first presented. Next, a currentless sorting
iC1 and iC2 denote the current flowing through the capacitors, based capacitor-voltage-balancing scheme is developed [16].

0885-8993 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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Transactions on Power Electronics

The schematic of the whole proposed solution is shown in Fig. it yields

2. To present the control scheme clearly, the proposed solution µm
requires only one total arm voltage per arm to achieve the SM W
cgux (k + 1) = W
cgux (k) +
T (k)S
egu (k)Sgux (k)
γ + Sgux gux (k)
capacitor-voltage-balancing of MMC, without sacrificing the
simplicity of the control structure. (21)
µm
W
cglx (k + 1) = W
cglx (k) +
T (k)S
egl (k)Sglx (k)
γ + Sglx glx (k)
Upper Arm Estimation
(22)
Voltages in (13)

where µm represents the learning rate of the weight update

Predict Future
Current
Predict Future
Active and Reactive Cost Function of FLS-MPC
Currentless Sorting based
Capacitor-Voltage-Balancing (0 < µm < 1), and γ is a sufficiently small and positive
in (9) Approach
Power T
value used to avoid division by zero if Sglx (k)Sglx (k) = 0.
Lower Arm Estimation
A schematic diagram of the eliminated SM capacitor voltage
Proposed FLS-MPC Method
Voltages in (14)
scheme is presented in Fig. 3. In this sense, the SM capacitor
voltage can be accurately estimated for the stable and reliable
Fig. 2: System configuration and control structure of proposed FLS- operation of MMC. Furthermore, the proposed methodology
MPC solution. is able to achieve satisfactory regulation performance and
decrease the system complexity and cost, which is reflected on
elimination in SM capacitor voltage and arm current sensors.
The relationship between the output upper and lower arm Actual Signal
voltages can be expressed as
vgux (k) = Wcgux T (k)Sgux (k) (15) Estimated Signal

T
vglx (k) = Wcglx (k)Sglx (k) (16) Error Signal

Upper Arm
where Estimation
Voltages
T
Sgux (k) = [Sg1 (k), Sg2 (k), ..., SgN −1 (k), SgN (k)] Least Mean Square
Weight Updating
T Algorithm
Sglx (k) = [SgN +1 (k), SgN +2 (k), ..., Sg2N −1 (k), Sg2N (k)]
Fig. 3: Adaptive linear-neuron-based upper SM voltage estimation
T scheme.
Wcgux (k) = [Ucg1 (k), Ucg2 (k), ..., UcgN −1 (k), UcgN (k)]
T
Wcglx (k) = [UcgN +1 (k), UcgN +2 (k), ..., Ucg2N −1 (k), Ucg2N (k)]
Notably, the direction information of the arm current is
and where T denotes the transpose symbol, and Ucgi denotes essential for allowing the balancing of the SM capacitor
the SM capacitor voltage. voltages. In this regard, the arm current is usually directly
Then, the output upper and lower arm estimation voltages measured for the sorting. However, in out work, a currentless
can be obtained sorting based capacitor-voltage-balancing technique along with
vbgux (k) = W T
cgux (k)Sgux (k) (17) SM voltage estimation scheme is proposed. Next, a clear
explanation of this procedure will be illustrated as follows.
T
vbglx (k) = W
cglx (k)Sglx (k) (18) According to the capacitor dynamics, the relationship be-
tween the estimated SM capacitor voltage and the arm current
where can be expressed as
h iT
W
cgux (k) = U bcg1 (k), U
bcg2 (k), ..., U
bcgN −1 (k), U
bcgN (k)
dU
bcgxi
iT Cg = Sgxibiarm (23)
h dt
W
cglx (k) = UbcgN +1 (k), UbcgN +2 (k), ..., U
bcg2N −1 (k), U
bcg2N (k)
where biarm denotes the estimated arm current.
and where Wcgux (k) and Wcglx (k) denote the adjustable weight Accordingly, summing the differential equations of the N
vector, and Ucgi denotes the estimated SM capacitor voltage.
b estimated SM capacitor voltage yields
0
bcgi = d
Thus, the error between the actual signal and the estimated
X X X Sgxi
signal can be calculated as follows: U Ubcgi = biarm . (24)
dt Cg
egu (k) = vgux (k) − vbgux (k) (19) It is worth emphasizing0 that the sign of biarm is substituted
egl (k) = vglx (k) − vbglx (k). (20) P 
by the sign of Ubcgi since Cg is always positive in the
In order to minimize the errors egu and egl , a Normalized whole control process, and Sgxi = 0 or Sgxi = 1. Then,
Least Mean Square (NLMS) algorithm is deployed here with the issue of determining unknown arm current flow direction
respect to the update rule of the weight vector [17]. For clarity, can be transformed into a problem to identify the sign of

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Transactions on Power Electronics

P 0 (100V/div)
Time(10ms/div) Time(10ms/div)

the estimated SM capacitor voltage information U

bcgi . (2000W/div)

In that sense, the balancing of the SM capacitor voltages can (2000Var/div)

be achieved without the knowledge of arm current signals. (100A/div)

Therefore, the proposed solution leads to simple, accurate, (200V/div) Time(10ms/div) (25A/div) (25A/div) (25A/div)
(25V/div)

and fast capacitor voltages estimation, and makes it ideal for

implementation. Time(10ms/div)
(2000W/div) (100V/div)

(100V/div)
(2000W/div)
(50V/div)
IV. E XPERIMENTAL R ESULTS (2000Var/div)

(50V/div)
(25V/div) (25V/div)
In order to verify the effectiveness of the proposed solution, (2000Var/div)
Time(10ms/div) Time(10ms/div)

a hardware-in-the-loop (HIL) test bench for the three-phase

four-arm MMC is built to serve this purpose. The software (2000W/div)

(100V/div)
is implemented on StarSim Field-Programmable Gate Array (10000Var/div)
(100V/div)
(50V/div)
(FPGA) Circuit Solver (MT FPGA 8000 Solver) and StarSim (2000W/div)

HIL. Meanwhile, a PXIe-7868R is employed as an external (10000Var/div)

(50V/div)

controller. For an effective practical implementation of the Time(10ms/div) (50V/div) Time(10ms/div)

(50V/div)
Time(10ms/div)

FLS-MPC, the delay associated with the proposed solution

is compensated by employing the method presented in [15].
Fig. 4: Experimental results with the proposed FLS-MPC with the
TABLE I indicates the design parameters of the control system. NLMS voltage estimation scheme.

TABLE I: SYSTEM AND CONTROL PARAMETERS

accurate voltage estimation and achieve the capacitor voltage-
balancing of the converter, while maintaining computationally
Parameter Symbol Experiment feasible.
Due to the fact that the FCS-MPC directly uses the system
Grid resistance Rg 0.01Ω
Grid filter inductance Lg 10mH discrete-time model to predict the future behavior of the
Arm resistance Rarm 0.2Ω controlled variables. This model is dependent on the system
Arm filter inductance Larm 10mH parameters that may not match with their real values due
DC-link capacitor C 4400µF to temperature and operating point. It is thus worthwhile
SM capacitor Cg 2200µF
Load resistance RL 65Ω
to investigate this influence in order to obtain the desired
Phase voltage peak eg 100V control performance for stable operation of regulated three-
Grid frequency f 50Hz phase four-arm MMC. To this end, the robustness of the
DC-link reference voltage Udc 500V proposed controller has been investigated in more detail under
Sampling/control period Ts 100µs the effect of the inductor Lg mismatch, as shown Fig. 5. It
Number of SMs per arm N 2
Weighting factors λgp , λgq , λgd 1, 1, 0.3
5.5
Conventional FCS-MPC
5 Proposed FLS-MPC
The experimental results of the three-phase four-arm MMC
4.5
operation with the proposed solution for FLS-MPC using the
NLMS voltage estimation scheme are depicted in Figs. 4(a)- 4
THD(%)

4(i), respectively. As illustrated in Fig. 4(a), they can be 3.5

observed that the grid-side active and reactive power wave- 3
forms are smooth and constant in steady-state. Meanwhile, the 2.5
control performance of DC-link voltage and three-phase grid-
2
side currents is illustrated in Fig. 4(b). Furthermore, the steady-
1.5
state performance of estimated and measured SM capacitor
voltages can be further confirmed and illustrated in Fig. 4(c) -50% -40% -30% -20% -10% 0 10% 20% 30% 40% 50%
Lg
and Fig. 4(d).
To present the control scheme clearly, Figs. 4(e)-4(h) indi- Fig. 5: The robustness of the proposed controller under the effect of
cate that considerably better tracking can be obtained with the the inductor Lg mismatch.
proposed approach under the steady-state and transient-state
operation. Furthermore, the control performance of the DC-
link capacitor voltages are depicted in Fig. 4(f) and Fig. 4(h). is clearly observed from Fig. 5 that the proposed solution
The transient-state performance of estimated and measured allows an enhanced system reliability. As a consequence, as
SM capacitor voltages can be illustrated in Fig. 4(i). Results can be clearly appreciated in these figures, the proposed design
confirmed the capability of the proposed solution to provide is capable of accomplishing the SM voltage estimation while

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Transactions on Power Electronics

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