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Introduction To LLC Resonant Converters (PDFDrive)

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290 views507 pages

Introduction To LLC Resonant Converters (PDFDrive)

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juan

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Introduction to LLC resonant

converters
Roman Stuler

LLC resonant converter training, Brno 2012

Agenda
• Introduction
• Switching techniques in SMPS
• Soft switched topologies
• Resonant topologies
• Configurations of the HB LLC converter and a resonant tank
• Operating states of the HB LLC with discrete resonant tank
• HB LLC converter modeling and gain characteristics
• Primary currents and resonant cap dimensioning
• Secondary rectification design and output cap dimensioning
• Resonant inductance balance
• Transformer winding dimensioning and transformer construction
• Overcurrent protection sensing
• Design example of 12 V / 20 A output LLC converter with SR

2 LLC resonant converter training. Brno 2012

Introduction - Regulatory Agencies Targets
•Standby (no load) Power Reduction
• ~25% of total energy passing through power supplies is in standby mode[13]
• Concerted effort by worldwide regulatory agencies
•Active Mode Efficiency Improvement
• ~75% of total energy passing through power supplies is in active mode[13]
•Power Factor Correction (or Harmonic
Reduction)
• Applicable with IEC61000-3-2[11] (Europe, Japan)
• Some efficiency specifications also require >0.9 PF.
example: computers (ENERGY STAR® rev. 4[12])
=> Energy conversion efficiency significantly
affects total power consumption !

Korea e-Standby program[8]

China CSC[6] Japan Top Runner[9] Japan Eco Mark[10] Australia AGO[7] California CEC[5] Europe ENERGY
(ex-CECP), program program COC[4] STAR®[3]

3 LLC resonant converter training. Brno 2012

Energy Efficiency Regulations
Computing
•Desktops:
• ENERGY STAR® 5.0 effective on Jul. 1, 2009
• 80 PLUS & Climate Savers Computing Initiative
• Tiered efficiency levels
•Laptops (More information at ENERGY STAR® 2.0 for External Power Supplies)
• Efficiency: ≥ 87%
• Standby (no load) power: ≤ 500 mW
• PF ≥ 0.9

Set-Top Boxes (STB)

•ENERGY STAR® 2.0 effective on Jan 1, 2009
•Europe Code of Conduct version 7 effective Jan 1, 2009
Solid State Lighting Luminaires • Standard is based on maximum allowable TEC (Total
Energy Consumption in kWh/year) or allowance
•ENERGY STAR® 1.1 effective on Feb. 1, 2009 • Base Allowance depends on the type of STB (Cable,
• Off-state power: 0 Satellite, etc…)
• Minimum efficacy (Lumen/Watt) requirements by applications • Additional functionalities allowance (DVR, etc…)
(downlights, outdoor lights, etc…) • Annual Energy Allowance (kWh/year) = Base Functionality
• PF ≥ 0.9 for Commercial Allowance + Additional Functionalities Allowance
≥ 0.7 for Residential
•ENERGY STAR® 1.2 effective in 2H2009
•ENERGY STAR® additional requirements for LED bulbs
• PF ≥ 0.7
• High system efficacy high efficiency power supply

For up-to-date information on agencies and regulations, check the PSMA energy efficiency data base at:
www.psma.com
4 LLC resonant converter training. Brno 2012
Regulation example - Computing Power Supplies
Efficiency (%)
20% of 50% of 100% of
rated rated rated Effective
Levels Specification
output output output Date
power power power

• Single-Output
Start
• Non-Redundant 81% 85% 81%
June 2007
• PFC 0.9 at 50%
Single-Output

• Single-Output
Start
• Non-Redundant 85% 89% 85%
June 2008
• PFC 0.9 at 50%

All in 1 PC
• Single-Output
Start
• Non-Redundant 88% 92% 88%
June 2010
• PFC 0.9 at 50%

• Single-Output
• Non-Redundant 90% 94% 91% Target
• PFC 0.9 at 50%

Sources:
• 80 PLUS® : http://www.80plus.org/
• Climate Savers® Computing Initiative: http://www.climatesaverscomputing.org/
• ENERGY STAR®: http://www.energystar.gov/index.cfm?c=revisions.computer_spec

5 LLC resonant converter training. Brno 2012

Summary
- World consumption of energy increases year-by-year (More and more
Computers, LCD and PLASMA TVs, Game consoles)

- Significant portion of energy is lost during power conversion and

also during standby mode

- Conversion efficiency has to be increased and no-load consumption

has to be minimized to assure that given power networks will be
able to supply increased number of electric equipment

- Energy agencies releasing various national programs that define

minimum equipment efficiency and maximum no-load consumption
in given category

6 LLC resonant converter training. Brno 2012

7 LLC resonant converter training. Brno 2012

Switch in power electronics

Lower Upper Complementary

switch switch switch
- Power switch always composes from a switch and freewheeling
path (diode or transistor)
- Switch is used to deliver energy to storage element (inductor)
- Freewheeling path is used to close demagnetization current

8 LLC resonant converter training. Brno 2012

Switch in power electronics using MOSFET

Lower Upper Complementary

switch switch switch

- Body diode can be used as a freewheeling diode in complementary

switch configuration when using MOSFET
9 LLC resonant converter training. Brno 2012
Switch
i
in basic non-isolated topologies
1

T ss motor
DC motor or LC filter
uCE
I2
R L R L
U1 Ui (U2)
D i2,I2 i2,I2
uX U2
iD C RZ

Buck converter topology

i2=iD

i1 L
U2
uL iC CZ RZ
= U1 uX

Magnetization phase
Boost converter topology Demagnetization phase

10 LLC resonant converter training. Brno 2012

Switch in forward topology

Forward topology

Magnetization phase

Two switch forward topology Demagnetization phase

11 LLC resonant converter training. Brno 2012

Switch in buck-boost topology

Inverting B-B topology

Magnetization phase
Demagnetization phase
Flyback topology
12 LLC resonant converter training. Brno 2012
Switch in ideal flyback converter

- Minimum current and voltage overlap i.e. negligible switching losses

13 LLC resonant converter training. Brno 2012
Real components parasitic elements
Transistor
Diode

Transformer

- Parasitic inductances and capacitances causes unwanted resonances

- PCB parasitic inductances and capacitances has to be included as well
14 LLC resonant converter training. Brno 2012
Switch in real flyback converter

-Ringing and more significant voltage and current overlap occurs in real
application just due to parasitic elements
15 LLC resonant converter training. Brno 2012
Switch in real flyback converter with snubbers

- Ringing can be damped by snubbers that however uses dissipative

elements – the power dissipation is still here
16 LLC resonant converter training. Brno 2012
Agenda
• Introduction
• Switching techniques in SMPS
• Soft switched topologies
• Resonant topologies
• Configurations of the HB LLC converter and a resonant tank
• Operating states of the HB LLC with discrete resonant tank
• HB LLC converter modeling and gain characteristics
• Primary currents and resonant cap dimensioning
• Secondary rectification design and output cap dimensioning
• Resonant inductance balance
• Transformer winding dimensioning and transformer construction
• Overcurrent protection sensing
• Design example of 12 V / 20 A output LLC converter with SR

17 LLC resonant converter training. Brno 2012

Need for soft switched topologies
- High turn-on and turn-off losses occur during hard switching

- Coss energy (1/2CossVds^2) is burnt during each turn-on

- Llk energy (1/2LlkId^2) is burnt during each turn-off

- Diode is commutated under high current => Qrr related losses

- Various parasitic resonances are present causing voltage spikes that

may exceed maximum ratings of used components

- Passive and thus dissipative snubber networks are usually needed to

damp system

- Application EMI signature is affected by parasitic oscillations and

capacitive currents (Coss discharge)
18 LLC resonant converter training. Brno 2012
Soft switching basic principles
- Using application parasitic and/or adding some additional energy
storage devices (L or C) to implement two basic soft switching
principles:

ZVS – Zero Voltage Switching: Switch is turned ON when there is

low or ideally zero voltage across its terminals
- Ideal switching technique for MOSFETs because it eliminates
Coss related losses

ZCS – Zero Current Switching: Switch is turned OFF when there is

low or ideally zero current flowing though its terminals
- Ideal switching technique for diodes, BJTs or IGBTs because
eliminates trr and storage time related losses

Note: ZVS/ZCS techniques eliminates switching losses however, usually

increases conduction losses due to higher RMS current in the
switch
19 LLC resonant converter training. Brno 2012
Zero voltage switching QR converters

- Example: Half wave mode ZVS QR buck

20 LLC resonant converter training. Brno 2012

Zero current switching QR converters

- Example: Full wave mode ZCS QR buck

21 LLC resonant converter training. Brno 2012

Quasi resonant AC/DC topologies
- Uses portion of the resonant cycle to prepare nearly ZVS or ZCS condition
- Typical example is flyback quasi resonant topology

- Drawback of DCM operation => high primary and secondary rms current
- Vin and Pout are dependent parameters

22 LLC resonant converter training. Brno 2012

Agenda
• Introduction
• Switch techniques in SMPS
• Soft switched topologies
• Resonant topologies
• Configurations of the HB LLC converter and a resonant tank
• Operating states of the HB LLC with discrete resonant tank
• HB LLC converter modeling and gain characteristics
• Primary currents and resonant cap dimensioning
• Secondary rectification design and output cap dimensioning
• Resonant inductance balance
• Transformer winding dimensioning and transformer construction
• Overcurrent protection sensing
• Design example of 12 V / 20 A output LLC converter with SR

23 LLC resonant converter training. Brno 2012

Resonant and Multi-resonant topologies
-The primary current has sinusoidal wave shape for nominal load
and line conditions
- ZVS and ZCS conditions are prepared for power semiconductors
-Some resonant converters are called multi resonant because the
resonant frequency changes during one switching cycle
- Two main resonant converter topologies can be identified:

Series resonant converter

Parallel resonant converter

Came out from well known half bridge topology by its power stage
modification . Disadvantage of these converters is relatively low regulation
range => the line and load changes are limited.

24 LLC resonant converter training. Brno 2012

Classical HB to resonant topology transition
Classical HB topology LLC resonant topology

25 LLC resonant converter training. Brno 2012

Series resonant converter

- Lr, Cr and load resistance forms series resonant circuit.

- Resonant tank impedance is frequency dependent
- Regulation can be done by the operating frequency modification
- Maximum gain of this converter is equal to transformer turns ratio for:
1
f sw = fs =
2 ⋅ π ⋅ Lr ⋅ Cr
26 LLC resonant converter training. Brno 2012
Parallel resonant converter

- Lr and Cr forms the series resonant circuit again

- Load resistance is now connected in parallel with resonant capacitor
thus called parallel RC.

27 LLC resonant converter training. Brno 2012

Series parallel resonant converter (LCC)

- Contains three resonant components Lr, Csr and Cpr

- Combines advantages of SRC and PRC
- The light or even no load regulation is not problem.

28 LLC resonant converter training. Brno 2012

Transition to the LLC resonant converter

-The LCC converter has still many disadvantages => other topology
is desirable for high density and efficiency SMPS
- LCC resonant tank can be changed to the LLC resonant tank

29 LLC resonant converter training. Brno 2012

Gain characteristics of the LLC converter

- Operation at fs is possible for nominal load and line conditions

30 LLC resonant converter training. Brno 2012

Benefits of an LLC series resonant converter
• Type of serial resonant converter that allows operation in relatively
wide input voltage and output load range when compared to the
other resonant topologies

• Limited number of components: resonant tank elements can be

integrated to a single transformer – only one magnetic component
needed

• Zero Voltage Switching (ZVS) condition for the primary switches

under all normal load conditions

• Zero Current Switching (ZCS) for secondary diodes, no reverse

recovery losses

Cost effective, highly efficient and EMI friendly solution

for high and medium output voltage converters
31 LLC resonant converter training. Brno 2012
Classical HB and LLC topology differences
Topology Advantages Disadvantages

Classical •Low ripple current on the •Switching under high

HB secondary currents (primary and
•Wide regulation range secondary)
•Constant frequency •ZVS conditions for primary
operation switches can be assured
only for limited loads
LLC •ZVS condition is assured •Higher ripple current on the
resonant for whole load range secondary => lower ESR
•Primary current is harmonic capacitors needed
for heavy loads =>EMI •Operating frequency isn't
•ZCS condition for constant
secondary rectifier for heavy •Lower regulation range
loads

32 LLC resonant converter training. Brno 2012

33 LLC resonant converter training. Brno 2012

Configurations of an HB LLC – single res. cap

- Higher input current ripple and RMS value

- Higher RMS current through the resonant capacitor
- Lower cost
- Small size / easy layout

34 LLC resonant converter training. Brno 2012

Configurations of an HB LLC – split res. cap

Compared to the single capacitor solution this connection offers:

- Lower input current ripple and RMS value by 30 %
- Resonant capacitors handle half RMS current
- Capacitors with half capacitance are used

35 LLC resonant converter training. Brno 2012

Resonant tank configurations – discrete solution
Resonant inductance is located outside of the transformer
Advantages:
- Greater design flexibility (designer can setup any Ls and Lm value)
- Lower radiated EMI emission

Disadvantages of this solution are:

- Complicated insulation between primary and secondary windings
- Worse cooling conditions for the windings
- More components to be assembled
36 LLC resonant converter training. Brno 2012
Resonant tank configurations – integrated solution
Leakage inductance of the transformer is used as a resonant inductance.
Advantages:
- Low cost, only one magnetic component is needed
- Usually smaller size of the SMPS
-Insulation between primary and secondary side is easily achieved
- Better cooling conditions for transformer windings

Disadvantages:
- Less flexibility (achievable Ls inductance range is limited)
- Higher radiated EMI emission
- LLC with integrated resonant tank operates in a slightly different way than
the solution with discrete Ls, different modeling has to be used
- Strong proximity effect in the primary and secondary windings
37 LLC resonant converter training. Brno 2012
Agenda
• Introduction
• Switching techniques in SMPS
• Soft switched topologies
• Resonant topologies
• Configurations of the HB LLC converter and a resonant tank
• Operating states of the HB LLC with discrete resonant tank
• HB LLC converter modeling and gain characteristics
• Primary currents and resonant cap dimensioning
• Secondary rectification design and output cap dimensioning
• Resonant inductance balance
• Transformer winding dimensioning and transformer construction
• Overcurrent protection sensing
• Design example of 12 V / 20 A output LLC converter with SR

38 LLC resonant converter training. Brno 2012

Operating states of the LLC converter
Discrete resonant tank solution
Two resonant frequencies can be defined:
1 1
Fs = Fmin =
2 ⋅ π ⋅ C s ⋅ Ls 2 ⋅ π ⋅ C s ⋅ ( Ls + Lm )
LLC converter can operate:
a) between Fmin and Fs c) above Fs
b) direct in Fs d) between Fmin and Fs - overload
e) below Fmin

39 LLC resonant converter training. Brno 2012

Operating states of the LLC converter
a) Operating waveforms for fmin < fop < fs

A B C D E F GH

40 LLC resonant converter training. Brno 2012

Operating states of the LLC converter
b) Operating waveforms for fop = fs

A B C D E F

41 LLC resonant converter training. Brno 2012

Operating states of the LLC converter
c) Operating waveforms for Fop > Fs Discrete resonant tank solution

A B C D E F

42 LLC resonant converter training. Brno 2012

Operating states of the LLC converter
d) Operating waveforms for fmin < fop < fs – strong overload

A B C D E F G H

43 LLC resonant converter training. Brno 2012

Operating states of the LLC converter
Integrated resonant tank solution
- Integrated resonant tank behaves differently than the discrete resonant tank
- leakage inductance is given by the transformer coupling
- Llk participates only if there is a energy transfer between primary and secondary
- Once the secondary diodes are closed under ZCS, Llk has no energy

Llk
M = 1−
Lm

Secondary diodes are always turned OFF under ZCS condition in HB LLC.
The resonant inductance Ls and magnetizing inductance Lm do not participate in
the resonance together as for discrete resonant tank solution when secondary
diodes are closed!
44 LLC resonant converter training. Brno 2012
Operating states of the LLC converter
Integrated resonant tank solution
Two resonant frequencies can be defined:
1 1
Fs = Fmin =
2 ⋅ π ⋅ C s ⋅ Ls 2 ⋅ π ⋅ C s ⋅ Lm
LLC converter can again operate:
a) between Fmin and Fs c) above Fs
b) direct in Fs d) between Fmin and Fs – overload
e) below Fmin

45 LLC resonant converter training. Brno 2012

46 LLC resonant converter training. Brno 2012

LLC converter modeling – equivalent circuit
LLC converter can be described using firs fundamental approximation. Only
approximation – accuracy is limited!! Best accuracy is reached around Fs.

n ⋅ Vout Z2
Transfer function of equivalent circuit: Gac = =
Vin Z1 + Z 2

Z1, Z2 are frequency dependent => LLC converter behaves like frequency
dependent divider. The higher load, the Lm gets to be more clamped by Rac.
Resonant frequency of LLC resonant tank thus changes between Fs and Fmin.

47 LLC resonant converter training. Brno 2012

LLC converter modeling – equivalent circuit
Real load resistance has to be modified when using fundamental approximation
to convert non linear circuitry to linear model.
In a full-wave bridge
circuit the RMS current
is: π
I ac _ RMS = IO
2 2

Considering the
fundamental component
of the square wave, the
RMS voltage is:
2 2
Vac _ RMS = VO
π
The AC resistance Rac ca be expressed as:
Vac _ RMS 8 EO 8
Rac = = = RL
I ac _ RMS π IO π
2 2

48 LLC resonant converter training. Brno 2012

Resonant tank equations
Quality factor: Characteristic impedance:
n 2 ⋅ RL Ls
Q= Z0 =
Z0 Load dependent ! Cs

Lm/Ls ratio: Gain of the converter:

Lm 2 ⋅ (Vout + V f )
m= G=
Ls Vin
Series resonant frequency: Minimum resonant frequency:
1 1
Fs = Fmin =
2 ⋅ π ⋅ C s ⋅ Ls 2 ⋅ π ⋅ C s ⋅ ( Ls + Lm )
49 LLC resonant converter training. Brno 2012
Normalized gain characteristic
2.0
Q=0.05
Q=200 – Light load
Q=0.5
1.8 Lm/Ls=6
Q=1
Region 2 Q=2
1.6 Q=3
ZVS Q=4
Q=5
1.4
Q=10
Q=20
1.2
Q=50
voltage gain

Region 1 Q=100
1.0 Q=200

0.8

0.6
ZCS Region 3
0.4
Q=0.05 – Heavy load
0.2

0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
f / fs

Region3: ZCS region Region 1 and 2: ZVS operating regions

50 LLC resonant converter training. Brno 2012
Gain characteristic discussion
- The desired operating region is on the right side of the gain characteristic
(negative slope means – ZVS mode for primary MOSFETs).

-Gain of the LLC converter, which operates in the fs is 1 (for discrete resonant
tank solution) - i.e. is given by the transformer turns ratio. This operating point is
the most attractive from the efficiency and EMI point of view – sinusoidal primary
current, MOSFETs and secondary diodes optimally used. This operating point
can be reached only for specific input voltage and load (usually full load and
nominal Vbulk).

Gain characteristics shape and also needed operating frequency range is given
by these parameters:

- Lm/Ls ratio
- Characteristic impedance of the resonant tank
- Load value

51 LLC resonant converter training. Brno 2012

How to obtain gain characteristics?
Use fundamental approximation and AC simulation in any simulation software
like PSpice, Icap4 etc..

Direct gain plot for given Rac

1 V amplitude AC supply

52 LLC resonant converter training. Brno 2012

Discrete and integrated tank gain differences

Simulation schematic for discrete solution

Simulation schematic for integrated solution

53 LLC resonant converter training. Brno 2012
Discrete and integrated tank gain differences
(the same Ls, Lm values and transformer turn ratio)
0.180

0.160
Gain = 0,137

Gain = 0,125
0.140

Gain = 0,125 @ 109 kHz i.e. out from fs for integrated

version and same turns ratio !!!!!
0.120

0.100
Gain [-]

0.080

0.060

0.040

0.020
Ls and Lm separated
fs Ls and Lm integrated
0.000
1.00E+04 1.00E+05 1.00E+06
Frequency [Hz]

54 LLC resonant converter training. Brno 2012

Discrete and integrated tank gain differences
- Integrated solution provides higher gain in comparison to the discrete solution
and the same transformer turn ratio!
- The leakage inductance “boost” the transformer gain
- Gain difference increases with Ls/Lm ratio i.e. higher Ls causes higher gain
difference as the Lm gets to be less clamped by the secondary load
- Turns ratio correction has to be done when designing integrated solution based
on the discrete solution model.
ndisc ndisc
nint = =
k L
1 − lk
Lm

Where: nint is turns ratio of the integrated solution

ndisc is turns ratio of the discrete solution
k is transformer coupling coefficient

Note: Leakage inductance is usually very small in comparison to the magnetizing inductance for discrete
solution => its impact to the gain characteristic can be neglected but in fact the discrete solution is always
combination of both solutions as ideal transformer doesn’t exist.

55 LLC resonant converter training. Brno 2012

Discrete and integrated tank gain differences
(the same Ls, Lm values after turn ratio correction)

0.180

0.160

0.140
Gain = 0,125 @ fs for both versions when correction
of turns ratio is used for integrated version!!!!

0.120

0.100
Gain [-]

0.080

0.060

0.040

0.020
Ls and Lm separated
fs Ls and Lm integrated
0.000
1.00E+04 1.00E+05 1.00E+06
Frequency [Hz]

56 LLC resonant converter training. Brno 2012

Basic transformer model
As mentioned in previous slides, there exist differences in gain characteristic and
power stage operation when comparing discrete and integrated resonant tank
solutions. These differences are related to the leakage inductance existence.
Generic transformer model reflects the reality and can be used without any
problems:

Thanks to the transformer reciprocity the M12=M21=M

one can then derive: How to get coupling coefficient k ?:
L1s L
k = 1− = 1 − 2s
di (t ) di (t ) L1 L2
u1 (t ) = L1 ⋅ 1 − M ⋅ 2
dt dt M
k= Where: L1s is primary inductance when secondary is shorted
di1 (t ) di (t ) L1 ⋅ L2 L1 is primary inductance when secondary is opened
u 2 (t ) = M ⋅ − L2 ⋅ 2 L2s is secondary inductance when primary is shorted
dt dt L2 is secondary inductance when primary is opened

57 LLC resonant converter training. Brno 2012

Impedance transformer model parameters
derivation from Ls and k and Gnom
Inputs from res. tank deign:

Ls - required resonant inductance

G nom - nominal gain at f s
Lm
m= - Inductance ratio
Ls

L1 = Lm = m ⋅ Ls 1 L2 = Ls (m − 1) ⋅ Gnom
2
k = 1−
m

Basic model parameters can be easily derived from resonant

inductance, required nominal gain and primary to resonant
inductances ratio
58 LLC resonant converter training. Brno 2012
APR transformer model
Inputs from real
transformer:
L1 , L2 , k

Where:
Ls = Llk1 Lm _ eq = L1 − Llk1 Gnom – nominal gain at fs
n – primary and secondary
1 L transformer ratio
n APR = = k ⋅n = k ⋅ 1
Gnom L2
- FHA can be easily applied to APR model => suitable for analysis
- Ideal trf. in APR model transfers sec. impedance to primary by 1/Gnom
- Real transformer inductance ratio n is affected by coupling coefficient
Integrated LLC stage can be also modeled using T or Π transf. model

59 LLC resonant converter training. Brno 2012

T model of the transformer
Inputs from real
transformer:
L1, L2, k, n

L1
n=
L2

Llk 1_ e = (1 − k ) ⋅ L1 Lm1_ e = k ⋅ L1 Llk 2 _ e = Llk1_ e

- The equivalent magnetizing inductance cannot be clamped by output load

- Model components values cannot be measured physically
- This model uses ideal transformer with turns ratio that is equal to
inductance turns ratio

60 LLC resonant converter training. Brno 2012

Π model of the transformer
Inputs from real
transformer:
L1 , L2 , k

L1
n=
L2

Lm1=

- The left equivalent magnetizing inductance cannot be clamped by load

- Model components values cannot be measured physically
- This model uses ideal transformer with turns ratio that is equal to
inductance turns ratio

- Magnetizing inductance is not fully clamped by load in integrated

res. tank designs due to leakage inductance
61 LLC resonant converter training. Brno 2012
Gain characteristics - multiple output design
Use fundamental approximation with AC simulation and recalculate AC resistances
to only one output i.e. parallel combination of recalculated AC resistances.

2
 n2 
Rac1 ⋅ Rac2 ⋅  
Rac _ total =  n3 
2
 n2 
Rac1 + Rac 2 ⋅  
 n3 

62 LLC resonant converter training. Brno 2012

Full load Q and m factors optimization
Proper selection of these two factors is the key point for the LLC resonant
converter design! Their selection will impact these converter characteristics:

- Needed operating frequency range for output voltage regulation

- Line and load regulation ranges
- Value of circulating energy in the resonant tank
- Efficiency of the converter

The efficiency, line and load regulation ranges are usually the most important
criteria for optimization.

Quality factor Q directly depends on the load. It is given by the Ls and Cs

components values for full load conditions:

n 2 ⋅ RL
Q=
Ls
Cs
63 LLC resonant converter training. Brno 2012
Full load Q and m factors optimization
n=8, Ls/Lm=6, Q=parameter, Rload=2.4Ω
0.250

0.200

Gmax
0.150
Gain [-]

Needed gains band

for full load regulation

Gmin
0.100

0.050
∆ f@Q=4

∆ f@Q=3

0.000
1.00E+04 1.00E+05 1.00E+06
Frequency [Hz]

Q=2 Q=3 Q=4

- Higher Q factor results in larger Fop range

- Characteristic impedance has to be lower for higher Q and given load => higher Cs
- Low Q factor can cause the loss of regulation capability!
- LLC gain characteristics are degraded to the SRC for very low Q values.

64 LLC resonant converter training. Brno 2012

Full load Q and m factors optimization
n=8, Cs=33nF, Ls=100uH, Lm=parameter, Rload=2.4Ω
0.250

0.200

0.150
Gain [-]

Gmax
Needed gains band
for full load regulation
Gmin
0.100

0.050
∆ f@k=2

∆ f@k=6
0.000
1.00E+04 1.00E+05 1.00E+06
Frequency [Hz]

k=2 k=4 k=6 k=8 k=10

- The m=Lm/Ls ratio dictates how much energy is stored in the Lm.
- Higher m will result in the lover magnetizing current and gain of the converter.
- Needed regulation frequency range is higher for larger m factor.
65 LLC resonant converter training. Brno 2012
Full load Q and k factors optimization
Practically, the Ls (i.e. leakage inductance of the integrated transformer version)
has only limited range of values and is given by the transformer construction (for
needed power level) and turns ratio.

The Q factor calculation is then given by the wanted nominal operating frequency fs.

The m factor has to be calculated to assure gains needed for the output
voltage regulation (with line and load changes).

The m factor can be set in such a way that converter wont be able to maintain
regulation at light loads – skip mode can be easily implemented to lover no load
consumption.

The higher Z0 i.e. Ls/Cs ratio is used the lower freq range is needed to maintain
Regulation. If to low Cs is used the voltage grows to excessive values and gain
doesn’t have to be high enough for regulation.

66 LLC resonant converter training. Brno 2012

67 LLC resonant converter training. Brno 2012

Primary currents – single resonant cap
2.0A

IIN, IDM1 1.0A

-0.0A

-1.0A

Fsw = Fs -2.0A

3.25665ms
-I(IDM1)
3.26000ms 3.26400ms 3.26800ms 3.27200ms
Time
3.27600ms 3.28000ms 3.28400ms 3.28740ms

2.0A

2.0A
1.0A

IDM2 -0.0A
400V
1.0A

-1.0A

300V

-2.0A

3.25665ms
-I(IDM2)
3.26000ms 3.26400ms 3.26800ms 3.27200ms
Time
3.27600ms 3.28000ms 3.28400ms 3.28740ms

VCs 200V
ICs -0.0A

100V
-1.0A

0V
2.780ms 2.782ms 2.784ms 2.786ms 2.788ms 2.790ms 2.792ms 2.794ms 2.796ms 2.798ms
V(Cs2:2) -2.0A
Time

2.8160ms 2.8200ms 2.8240ms 2.8280ms 2.8320ms 2.8360ms 2.8400ms

I(Cs2) I(L5) -I(TX1)
Time

1  I out ⋅ π 2 
2 2
I sec Vbulk
I C s = I primary = + I Lm I Cs _ RMS ≈ ⋅  + 
2 
24 ⋅ Lm ⋅ f sw 
2 2
n 8  n

68 LLC resonant converter training. Brno 2012

Primary currents – split resonant cap
2.0A
2.0A

ICs1
1.0A 1.0A

IDM1 -0.0A

-1.0A
-0.0A

-1.0A

-2.0A -2.0A

3.25665ms 3.26000ms 3.26400ms 3.26800ms 3.27200ms 3.27600ms 3.28000ms 3.28400ms 3.28740ms 1.3200ms 1.3240ms 1.3280ms 1.3320ms 1.3360ms 1.3400ms 1.3440ms 1.3479ms
-I(IDM1)
Time I(Cs)
Time

Fsw=Fs

2.0A

1.0A

IDM2 -0.0A

-1.0A

-2.0A

3.25665ms 3.26000ms 3.26400ms 3.26800ms 3.27200ms 3.27600ms 3.28000ms 3.28400ms 3.28740ms

-I(IDM2)
Time
400V
2.0A

2.54A

2.00A 300V
1.0A

IIN
1.00A

VCs2 200V

100V
ICs2 -0.0A

-1.0A
0A

-2.0A
-1.00A 0V
1.320ms 1.325ms 1.330ms 1.335ms 1.340ms 1.345ms 1.350ms 1.3200ms 1.3240ms 1.3280ms 1.3320ms 1.3360ms 1.3400ms 1.3440ms 1.3479ms
V(Cs2:2) I(Cs2)
Time
Time
-1.49A
1.9648ms 1.9680ms 1.9720ms 1.9760ms 1.9800ms 1.9840ms 1.9880ms
-I(V1)
Time

69 LLC resonant converter training. Brno 2012

Comparison of Primary Currents
Single and split resonant capacitor solutions - 24 V / 10 A application

Parameter Single Cap Split Caps

ICs_Pk 2.16 A 1.08 A

ICs_RMS 1.52 A 0.76 A
IIN_Pk 2.16 A 1.08 A
IIN_RMS 1.07 A 0.76 A

• Split solution offers 50% reduction in resonant capacitor current

and 30% reduction in input rms current
• Select resonant capacitor(s) for current and voltage ratings

70 LLC resonant converter training. Brno 2012

Primary switches dimensioning
2.0A

1.0A

A B

-1.0A

3.26620ms 3.26800ms 3.27200ms 3.27600ms 3.28000ms 3.28400ms 3.28707ms

-I(IDM1) (V(M1:g)- V(bridge))/10 V(M2:g)/10
Time

- Body diode is conducting during the dead time only (A)

- MOSFET is conducting for the rest of the period (B)
- Turn ON losses are given by Qg (burned in the driver not in MOSFET)
- MOSFET turns OFF under non-zero current => turn OFF losses

71 LLC resonant converter training. Brno 2012

Primary switches dimensioning
MOSFET RMS current calculation
- The body diode conduction time is negligible
- Assume that the MOSFET current has half sinusoid waveform

1  I out ⋅ π 2 
2 2
Vbulk
I switch _ RMS ≈ ⋅  + 
2 
24 ⋅ Lm ⋅ f sw 
2 2
16  n

Turn OFF current calculation

- Assume that the magnetizing current increases linearly
Vbulk
I OFF ≈
8 ⋅ Lm ⋅ f sw

-Turn OFF losses (EOFF @ IOFF) can be find in the MOSFET datasheet
or calculated

Pswitch _ total ≈ I switch _ RMS ⋅ RdsON + POFF

2
Total switch loses:

72 LLC resonant converter training. Brno 2012

73 LLC resonant converter training. Brno 2012

Secondary Rectifier Design
• Secondary rectifiers work in ZCS
• Possible configurations:

a) Push-Pull configuration – for

low voltage / high current
output
b) Bridge configuration – for high
voltage / low current output
c) Bridge configuration with two
secondary windings – for
complementary output
voltages
Push-Pull Configuration
Advantages: Disadvantages:
- Half the diode drops compared to bridge - Need additional winding
- Single package, dual diode can be used - Higher rectifier breakdown voltage
- Space efficient - Need good matching between windings
74 LLC resonant converter training. Brno 2012
Secondary Rectifier Design
Rectifier waveforms for different operating states

a) Fop < Fs b) Fop = Fs

█ - rectifier current
█ - rectifier voltage

c)Fop > Fs
Simplification by analyzing the operating state in the series resonant frequency Fs
is used thereafter. Another simplification is done – assume that the secondary
current has sinusoidal shape.
75 LLC resonant converter training. Brno 2012
Secondary Current Calculations – Push-Pull

Equations 24 V/10 A output 12 V/20 A output

RMS diode current
π I D _ RMS = 7.85 A I D _ RMS = 15.7 A
I D _ RMS = I out ⋅
4
AVG diode current
I out I D _ AVG = 5 A I D _ AVG = 10 A
I D _ AVG =
2
Peak diode current
π I D _ PK = 15.7 A I D _ PK = 31.4 A
I D _ PK = I out ⋅
2

• To simplify calculations, assume sinusoidal current and Fop=Fs

76 LLC resonant converter training. Brno 2012

Rectifier Losses – Push-Pull
Equations 24 V/10 A 12 V/20 A
Vf=0.8 V, Rd=0.01 Ohm Vf=0.5 V, Rd=0.01 Ohm
Losses due to forward drop:
V ⋅I PDFW = 4.0 W PDFW = 5.0 W
PDFW = F OUT
2
Losses due to dynamic resistance:

Rd ⋅ I OUT ⋅ π 2
2
PDRd = 0.62 W PDRd = 2.48 W
PDRd =
16

Equation 24 V/10 A 12 V/20 A

PRe ct _ total = ( PDFW + PDRd ) ⋅ nrect PRe ct _ total = 9.24 W PRe ct _ total = 15 W

77 LLC resonant converter training. Brno 2012

Secondary Rectifier - Bridge Configuration

Advantages: Disadvantages:
- Lower voltage rating - Higher diode drops
- Needs only one winding - Need four rectifiers
- No matching needed for windings

78 LLC resonant converter training. Brno 2012

Secondary Rectifier – Complementary outputs
Bridge configuration – complementary output

Advantages: Disadvantages:
- Needs only two windings - Rectifiers with higher breakdown voltage
- Low power looses (one Vf only) (Vbr>2*Vout)
- Matching between secondary windings needed
79 LLC resonant converter training. Brno 2012
Secondary Rectifier Design Procedure
1. Select appropriate topology (push-pull or bridge)
2. Calculate rectifier peak, AVG and RMS current
3. Select rectifier based on the needed current and voltage ratings
4. Measure the diode voltage waveform in the application and design
snubber to limit diode voltage overshoot and improve EMI signature (for
LLC “weak” snubber is needed since diodes operate in ZCS mode)

Notes:

- The current ripple increases for fop<fs, the current waveform is still half
“sinusoidal” but with dead times between each half period
- The peak current is very high for low voltage and high current LLC
applications – example 12 V/20 A output: Ipeak= 31.4 A and IRMS= 9.7 A!!
Each “mΩ” becomes critical - PCB layout. The secondary rectification
paths should be as symmetrical as possible to assure same parameters
for each switching half cycle.

80 LLC resonant converter training. Brno 2012

Output Capacitor Dimensioning

• Output capacitor is the only energy storage device

– Higher peak/rms ripple current and energy
• Ripple current leads to:
– Voltage ripple created by the ESR of output capacitor (dominant)
– Voltage ripple created by the capacitance (less critical)
81 LLC resonant converter training. Brno 2012
ESR Component of Output Ripple
• In phase with the current ripple and frequency independent
• Low ESR capacitors needed to keep ripple acceptable
– Cost/performance trade-off (efficiency impact)

24 V/10 A example:
Equations: Ω
Cf=5000 uF, ESR=6 mΩ
Peak rectifier current
π I rect _ peak = 15.7 A
I rect _ peak = I out ⋅
2
Output voltage ripple peak to peak
V out _ ripple _ pk − pk= 94 mV
Vout _ ripple _ pk − pk = ESR ⋅ I rect _ peak
Capacitor RMS current:
π2 I Cf _ RMS = 4.83 A
I Cf _ RMS = I out ⋅ −1
8
ESR power losses
PESR = I Cf _ RMS ⋅ ESR
2 PESR = 140 mW

82 LLC resonant converter training. Brno 2012

ESR Component of Output Ripple
15.9

10.0

-10.0
2.8106ms 2.8150ms 2.8200ms 2.8250ms 2.8300ms 2.8350ms
I(rect) I(Iout) -I(Cf) (V(Iout:+)-24)*10
Time

ESR component of the output voltage ripple is in phase with current ripple and is frequency independent.

83 LLC resonant converter training. Brno 2012

Capacitive Component of Output Ripple
• Out of phase with current and frequency dependent
• Actual ripple negligible due to high value of
capacitance chosen
24 V/10 A output example:
Equation:
Cf=5000 uF, Fop=100 kHz
Vout _ ripple _ cap = 2.1 mV
I out
Vout _ ripple _ cap _ pk − pk = ⋅ (π − 2)
2 ⋅ 3 ⋅ π ⋅ f op ⋅ C f 24 V/10 A output example:
Cf=100 uF, Fop=100 kHz

Vout _ ripple _ cap = 104 mV

84 LLC resonant converter training. Brno 2012

Capacitive Component of Output Ripple
15.92

12.00

8.00

4.00

-4.00

-8.00

-10.45
413.9us 416.0us 420.0us 424.0us 428.0us 432.0us
I(rect) I(Iout) -I(Cf) (V(Iout:+)-23.98)*1000
Time

Capacitive component of the output voltage ripple is out of phase with current ripple and is frequency dependent.

85 LLC resonant converter training. Brno 2012

Filter Capacitor Design Procedure

1. Calculate peak and rms rectifier and capacitor currents based on
Io and Vout
2. Calculate needed ESR value that will assure that the output
ripple will be lower than maximum specification
3. Select appropriate capacitor(s) to handle the calculated rms
current and having calculated ESR or lower
4. Factor in price, physical dimensions and transient response
5. Check the capacitive component value of the ripple (usually
negligible for high enough Cf)

Notes:
• The secondary rectification paths should be as symmetrical as
possible to assure same parameters for each switching half
cycle

86 LLC resonant converter training. Brno 2012

Slide 86

f3 This slide may be better off getting split into two slides and add some more notes. Let's discuss.
ffmrmw; 3.9.2007
Agenda
• Introduction
• Switching techniques in SMPS
• Soft switched topologies
• Resonant topologies
• Configurations of the HB LLC converter and a resonant tank
• Operating states of the HB LLC with discrete resonant tank
• HB LLC converter modeling and gain characteristics
• Primary currents and resonant cap dimensioning
• Secondary rectification design and output cap dimensioning
• Resonant inductance balance
• Transformer winding dimensioning and transformer construction
• Overcurrent protection sensing
• Design example of 12 V / 20 A output LLC converter with SR

87 LLC resonant converter training. Brno 2012

Resonant inductance balance
Transformer leakage inductance
- Total Ls is always affected by the transformer leakage inductance
- Special case for transformer with integrated leakage inductance - Ls=Llk
- Push pull and mult. output app. are sensitive to the leakage inductance balance
Parameter Measured Secondary pins
between configuration
pins

Llk(p-s1) A-B C-D short

D-E open

Llk(p-s2) A-B C-D open

D-E short

Llk(total) A-B C-D short

D-E short

Lm A-B C-D open

Example:Llk(p-s1) = 105 uH D-E open

Llk(p-s2) = 115 uH fs1 = 85.5 kHz

∆Llk = 10 uH 5 % difference
Llk(total) = 100 uH fs2 = 81.7 kHz
Lm = 600 uH
Cs = 33 nF
88 LLC resonant converter training. Brno 2012
Resonant inductance balance
Series resonant frequency differs for each switching half-cycle that results
in primary and mainly secondary current imbalance.

16A

12A

608.00us 612.00us 616.00us 620.00us 624.00us 628.00us 632.00us 635.45us

I(D6) I(D3)
Time

3 A difference in the peak secondary current – the power dissipation is different

for each rectifier from pair as well as for the secondary windings.

89 LLC resonant converter training. Brno 2012

Resonant inductance balance

Iprimary

Converter works below series resonant frequency Fs for the one half of the
switching cycle and in the Fs for the second half of the switching cycle.
90 LLC resonant converter training. Brno 2012
Resonant inductance balance
For high power app. it is beneficial to connect primary windings in series and
secondary windings in parallel. There is possibility to compensate transformer
leakage imbalance by appropriate connection of the secondary windings:

∆Llk_total = 2* ∆Llk ∆Llk_total = 0

91 LLC resonant converter training. Brno 2012

Resonant inductance balance
The secondary leakage inductance is transformed to the primary and increases
the total resonant inductance value. Situation becomes critical for the LLC
applications with high turns ratios.

12 V / 20 A application example:
Np = 35 turns Llk_s1 = 100 nH
Ns = 2x2 turns Llk_s2 = 150 nH
n = Np/Ns = 17.5
Ls = 110 uH
Lm = 630 uH

∆Llk_s = 50 nH ∆Ls = ∆Llk _ s ⋅ n 2 = 15.3 µH

50 nH difference on the secondary causes 14 % difference of Ls !!!

92 LLC resonant converter training. Brno 2012
Resonant inductance balance
Transformer construction and secondary layout considerations:

- Resonant tank parameters can change each switching half cycle when
push pull configuration is used. This can cause the primary and secondary
currents imbalance.

- For the transformer with integrated resonant inductance, it has to be

checked how the transformer manufacturer specifies the leakage
inductance. Specification for all secondary windings shorted is irrelevant.
The particular leakage inductance values can differ.

- When using more transformers with primary windings in series and

secondary windings in parallel the leakage inductance asymmetry can be
compensated by appropriate secondary windings connection.

- Secondary leakage inductance can cause significant resonant inductance

imbalance in applications with high transformer turns ratio. Layout on the
secondary side of the LLC resonant converter is critical in that case.

93 LLC resonant converter training. Brno 2012

94 LLC resonant converter training. Brno 2012

Transformer winding dimensioning
The primary current is sinusoidal for Fop = Fs. The secondary current is almost
sinusoidal too – there is slight distortion that is given by the magnetizing current.

1  I out ⋅ π 2 
2 2
Vbulk
I primary _ RMS ≈ ⋅  + 
2 
24 ⋅ Lm ⋅ f sw 
2 2
8  n

π
I sec ondary _ RMS ≈ I out ⋅ (single winding solution)
2⋅ 2
- The skin effect and mainly proximity effect decreases effective cooper area.
- Proximity effect can be overcome by the interleaved winding construction (for
discrete resonant tank solution)

- The proximity effect becomes critical for the transformer with integrated leakage
- Wires that are located to the center of the bobbin “feels” much higher current
density than the rest of the windings even when litz wire used!
95 LLC resonant converter training. Brno 2012
Transformer with integrated leakage
- For the standard transformer with good coupling (Llk<0.1*Lm) is the leakage
inductance independent on the air gap thickness and position

Llk
M = 1−
Lm

- Transformer with divided bobbin exhibits high leakage inductance

- Significant energy is related to the stray flux
- The Llk is dependent on air gap thickness and position

96 LLC resonant converter training. Brno 2012

Transformer with integrated leakage
- A ferrite core with air gap on the center leg is used to allow for primary inductance
adjustment.
- The air gap stores most of the magnetizing current energy related to the primary
winding. Thus it is beneficial to place the air gap below the primary winding to
minimize additional stray flux and reduce the proximity effect.

97 LLC resonant converter training. Brno 2012

Transformer with integrated leakage
-The air gap position within the bobbin affects primary and secondary inductance
- Inductance inductor with gapped ferrite core is lower when the gap is located
below the coil winding rather than outside of the winding
- The difference between both cases is due to the magnetic flux bulging out from
the gap and coil

- Same coil features higher inductance when gap is not shielded !!

98 LLC resonant converter training. Brno 2012

Transformer with integrated leakage
- Gap is shielded by primary winding only
- The magnetic conductivity for the primary
winding Λprimary is lower than magnetic
conductivity for the secondary winding
Λsecondary
L primary Lsec ondary
Λ primary = 2
Λ sec ondary = 2
Np Ns

Λ primary < Λ sec ondary

- Thanks to this core non-homogeneity, the physical turns ratio (N) is

not equal to the electrical turns ratio (n) that is given by the primary and
secondary inductances:
Np L primary
≠
Np – is the primary winding turns number
Ns – is the secondary winding turns
Ns Lsec ondary

=> It makes no sense to specify transformer turn number before we

know real primary and secondary magnetic conductivities
99 LLC resonant converter training. Brno 2012
Agenda
• Introduction
• Switching techniques in SMPS
• Soft switched topologies
• Resonant topologies
• Configurations of the HB LLC converter and a resonant tank
• Operating states of the HB LLC with discrete resonant tank
• HB LLC converter modeling and gain characteristics
• Primary currents and resonant cap dimensioning
• Secondary rectification design and output cap dimensioning
• Resonant inductance balance
• Transformer winding dimensioning and transformer construction
• Overcurrent protection sensing
• Design example of 12 V / 20 A output LLC converter with SR

100 LLC resonant converter training. Brno 2012

Overcurrent protection techniques for the LLC series resonant converters
Impedance of the resonant tank reaches very low values when LLC converter operates near the
resonant frequency. Fast over current protection has thus be used to protect the primary switches in
case of overload or short circuit.

There are few solutions how to protect the LLC power stage from over current:

A) Use current sense transformer in the primary path

B) Use charge pump to monitor resonant capacitor voltage

C) Use split resonant capacitor with clamping diodes

D) Prepare design which will work always above fs (not very good solution from
the efficiency point of view)

Operating frequency of the converter is pushed up by the current control loop in cases A) and B).
Primary current is thus limited to the desired value.

101 LLC resonant converter training. Brno 2012

A) Using current sense transformer to prepare OCP feature

Advantages:
- Easy to implement
- Immediate reaction to the primary current changes
- Good accuracy of the output current limit when bulk voltage is stable (with PFC front stage)

Disadvantages:
- High component count
- CST transformer needed => higher cost

102 LLC resonant converter training. Brno 2012

B) OCP with resonant capacitor voltage monitoring using charge pump

Advantages:
- Easy to implement
- Good accuracy of the output current limit when bulk voltage is stable (with PFC front stage)

Disadvantages:
- Another HV capacitor (C1) needed
- One half period delay in response

103 LLC resonant converter training. Brno 2012

C) Use two resonant capacitors with voltage clamps

Advantages:
- Resonant capacitors voltage cannot go above bulk voltage, primary current and output power are
thus limited automatically – no need for other control loop
- Converter will never enter ZCS region
- Input current ripple is lower in comparison to the one cap solution
- Resonant capacitors with lower voltage ratings can be used
- Can be also used in single resonant capacitor solution

Disadvantages:
- Output current limit has pure accuracy => can be used only as short circuit protection
- Limits the resonant capacitor value
- Is bulk voltage dependent
104 LLC resonant converter training. Brno 2012
Agenda
• Introduction
• Switching techniques in SMPS
• Soft switched topologies
• Resonant topologies
• Configurations of the HB LLC converter and a resonant tank
• Operating states of the HB LLC with discrete resonant tank
• HB LLC converter modeling and gain characteristics
• Primary currents and resonant cap dimensioning
• Secondary rectification design and output cap dimensioning
• Resonant inductance balance
• Transformer winding dimensioning and transformer construction
• Overcurrent protection sensing
• Design example of 12 V / 20 A output LLC converter with SR

105 LLC resonant converter training. Brno 2012

Design Example
12 V / 20 A LLC converter
with synchronous
rectification - AND8460

106 LLC resonant converter training. Brno 2012

LLC stage requirements
Requirement Min Nom Max Unit
Input voltage (dc) 350 395 425 V
Output voltage (dc) - 12 - V
Output current 0 - 20 A
Total output power 0 - 240 W
Consumption a 500 mW output load in STBY mode - - 1.7 W
Consumption a 100 mW output load in STBY mode - - 1.2 W
No load consumption SR operating - - 870 mW
No load consumption SR turned off - - 1 W
Load regulation - - 20 mV
Average Efficiency 95 - - %

-High efficiency is required

=> secondary SR is needed to fulfill this requirement

107 LLC resonant converter training. Brno 2012

SMPS block diagram
NCP4303B
EMI SR controller
Filter
Synchronous Rectification
for improved efficiency

90V – 265Vac NCP1605

PFC NCP1397B 12V / 20A
Controller Resonant Controller
with built-in
Half Bridge Driver

Resonant Technology
for Increased TL431
Frequency Clamped Efficiency and Lower EMI NCP4303B
Critical Conduction Mode
Power Factor Controller SR controller
Bias
circuitry

- Bulk voltage is provided by PFC stage driven by NCP1605

- NCP1397B is used to implement latched OCP protection
- NCP4303 control SR MOSFETs to maximize efficiency
- TL431 regulates output voltage by modulating LLC stage
operating frequency via optocoupler and NCP1397B
108 LLC resonant converter training. Brno 2012
Resonant tank design
Selection of some design parameters:

- Resonant tank type: Integrated resonant inductance (cost constrains)

- Nominal operating frequency: 80 kHz (Efficiency constrains)

- Resonant frequency: same as nominal operating frequency 80 kHz

- Minimum operating frequency: > 60 kHz (transformer size constrains)

- Maximum full load operating frequency: < 100 kHz

- Maximum light load operating frequency: 110 kHz (then skip)

- Nominal resonant capacitor voltage: < 350 V pk

109 LLC resonant converter training. Brno 2012

Step 1 – calculate Rac needed for FHA analysis
- Small signal AC analysis is desirable for accurate resonant tank design

- Equivalent load resistance (Rac) has to be used for FHA:

8 Vout 12 8
Rac = 2 ⋅ = 2⋅ = 0.51Ω
π I out _ nom ⋅η π 20 ⋅ 0.95

110 LLC resonant converter training. Brno 2012

Step 2 – calculate needed LLC stage gain
- Calculate needed converter gain for maximum bulk voltage:
2 ⋅ (Vout + V f _ SR ) 2 ⋅ (12 + 0.2)
Gmin = = = 0.057
Vbulk _ max 425

- Calculate needed converter gain for nominal bulk voltage:

2 ⋅ (Vout + V f _ SR ) 2 ⋅ (12 + 0.2)
Gnom = = = 0.0618
Vbulk _ nom 395

- Calculate needed converter gain for minimum bulk voltage:

2 ⋅ (Vout + V f _ SR ) 2 ⋅ (12 + 0.2)
Gmax = = = 0.0697
Vbulk _ min 350

111 LLC resonant converter training. Brno 2012

Step 3 – Cs value selection/calculation
- Optimization criterion has to be selected
- Maximum efficiency is required for this design

Z0 =
Ls
fs =
1 n 2 ⋅ Rac
Cs 2 ⋅ π ⋅ Ls ⋅ Cs
Q=
Z0
Several facts can be considered from above equations:
- The lower Cs is, the higher characteristic impedance and lower quality factor are
- The lower Cs is the higher Ls needs to be used to keep required res. frequency
- The higher Ls is used the lower frequency range is needed for regulation
- The higher Ls is used the higher Lm will be and thus lower magnetizing current

⇒Design with minimized Cs brings two main advantages

- low operating frequency range for regulation
- high efficiency

112 LLC resonant converter training. Brno 2012

Step 3 – Cs value selection/calculation
- Resonant capacitor voltage reaches too high level if low capacitance is used
- It is beneficial to keep Vcs below Vbulk for nominal operating conditions because:
- Low voltage caps. handle higher RMS current with small dimensions,
lower cost and good reliability
- Lower voltage stress occurs to the PCB and transformer primary

Step 3 with regards to above considerations is finally as follows:

Calculate ICs_RMS_nom based on load current value:
π π
I Cs _ RMS _ nom ≈ I sec_ RMS _ mon ⋅ Gnom ≈ ⋅ I out _ nom ⋅ Gnom ≈ ⋅ 20 ⋅ 0.062 ≈ 1.38 A
2⋅ 2 2⋅ 2
Calculated Cs value based on the Ics_RMS_mon and selected Vcs_peak_nom:
I Cs _ RMS _ nom ⋅ 2 1.38 ⋅ 2
Cs = = = 31.6nF => 2 *15nF
 V  3  395 
2 ⋅ π ⋅ f op _ nom ⋅ VCs _ peak _ nom − bulk _ nom  2 ⋅ π ⋅ 80 ⋅10 ⋅  320 − 
 2   2 
Note: Some error is induced because we did not included magnetizing current component into
calculation as it is not know yet.

113 LLC resonant converter training. Brno 2012

Step 4 – Ls calculation
- Resonant inductor value can be calculated based on selected resonant frequency
and previously calculated resonant capacitor value using modified Thompson law:
1 1
Ls = = = 131.9µH => 130µH
Cs ⋅ (2 ⋅ π ⋅ f s ) 2
30 ⋅10 ⋅ (2 ⋅ π ⋅ 80 ⋅10 )
−9 3 2

Step 5 – maximum Lm calculation

-The maximum Lm value is given by total bridge parasitic capacitance (Coss of
MOSFETs and stray capacitance). Magnetizing inductance has to provide enough
energy to overcharge bridge parasitic capacitance and prepare ZVS condition
within selected deadtime.

DT 350 ⋅10−9
Lm _ max = = −12
= 1.1mH
8 ⋅ f op _ max ⋅ CHB _ total 8 ⋅110 ⋅10 ⋅ 360 ⋅10
3

Future transformer magnetizing inductance should not be higher than this value.

114 LLC resonant converter training. Brno 2012

Step 6 – Ls/Lm ratio selection
-The most appropriate Ls/Lm ratio can be selected based on application gain
characteristics simulation. Simulation schematic for gain characteristics analysis:

- Use Lm = k*Ls as a parameter we will get several gain characteristics

115 LLC resonant converter training. Brno 2012

Step 6 – Ls/Lm ratio selection

-It is evident that k = 5.5 provides optimum performance + some gain margin
=> Lm = Lprimary = 130u * 5.5 = 715 uH
116 LLC resonant converter training. Brno 2012
Step 7 – Integrated resonant tank turns ratio
- The turns ration for discrete resonant tank solution that uses transformer with
negligible leakage is inverse of nominal gain at resonant frequency
1 L primary Vbulk _ nom 395
ndiscrete = = = = = 16.18
Gnom L sec ondary 2 ⋅ (Vout + V f ) 2 ⋅ (12 + 0.2)

- The gain is boosted when using integrated resonant tank solution because the
leakage inductance is not located just only before Lm like in used model
1
Gnom _ int egrated >
ndiscrete
- The higher leakage inductance is the higher gain boost will occur.The integrated
resonant tank turns ratio can be then calculated as:
ndiscrete 16.18
nint egrated = = = 17.88
L 130
1− s 1−
Lm 715

117 LLC resonant converter training. Brno 2012

Step 8 – Secondary inductance calculation
- The secondary inductance Lsec can be calculated using nint. and Lprimary
L sec ondary 715 ⋅10 −6
L sec ondary = = = 2.23µH
n 2 int egrated 17.88 2

Step 9 – Final resonant tank gain simulation

Calculated components of future integrated resonant tank:
Cs = 30 nF (2 x 15 nF) Lprimary= 715 uH
Llk_primary = 130 uH Lsecondary= 2.23 uH

118 LLC resonant converter training. Brno 2012

Step 10 – Final gain characteristic review

- Integrated resonant tank provides higher peak gain margin (~12 % above Gmax)

119 LLC resonant converter training. Brno 2012

Step 11 – Transient simulation

- Simple model for transient simulation using elementary simulator libraries

120 LLC resonant converter training. Brno 2012

Step 11 – Transient simulation

- Proposed resonant tank operates at fs for full load and nominal Vbulk conditions
- Ics_rms = 1.57 A can be measured more precisely

121 LLC resonant converter training. Brno 2012

Step 11 – Transient simulation

- Operating frequency has to drop to 66.6 kHz to maintain full load regulation for
Vbulk = 350 Vdc

122 LLC resonant converter training. Brno 2012

Step 11 – Transient simulation

- Operating frequency has to increase to 90 kHz to maintain full load regulation for
Vbulk = 425 Vdc

123 LLC resonant converter training. Brno 2012

LLC stage primary side components design

- Typical NCP1397B connection with minimum component count

124 LLC resonant converter training. Brno 2012

OCP network design
- Charge pump OCP sensing is used in
consumer electronics due to cost
reasons

- AC voltage on the resonant capacitor

causes AC current through C29

- Current goes through D14 and

causes voltage drop on R60 when
upslope occurs on the Vcs voltage i.e.
each half period only

- Charge pump sensor features natural

delay as it delivers current information
only during one switching half period

125 LLC resonant converter training. Brno 2012

OCP network design
- Calculate or simulate primary RMS current during overload:

1  
2
V
I Pr imary _ rms ≈ ⋅ I out _ max ⋅ π ⋅ Gnom +
2 2 2 bulk _ nom  = 1.68 A
8  24 ⋅ Lm ⋅ f op _ ovld 
2 2

- Calculate resonant capacitor AC voltage during overload:

I Pr imary _ rms 1.68
VCs _ ac = = = 114Vac
2 ⋅ π ⋅ f op _ ovld ⋅ Cs 2 ⋅ 3.14 ⋅ 78 ⋅10 ⋅ 30 ⋅10
3 −9

- Calculate series limiting resistors and OCP charge pump capacitor value:
1
C 29 = = 214.6 pF
VCs _ peak 1 ⋅ 103
Rs = = = 50kΩ (R + R64 )  − (R + R )2
2
 VCs _ ac ⋅ R60
2 ⋅ π ⋅ f op _ ovld ⋅ 2 ⋅  − 60
I f _ lim it 20 ⋅ 10−3  π ⋅V
 ref _ faul ⋅ 0.9 2 

42 52

- Calculate filtering capacitor value and check power loss :

2
C28 =
5
=
5
≈ 68nF  π ⋅ Vref _ fault ⋅ 0.9 
PRs =   ⋅ Rs = 0.208W
f op _ ovld ⋅ R23 78 ⋅ 103 ⋅ 1000  2 ⋅ R60 


126 LLC resonant converter training. Brno 2012

Fault timer components selection
- NCP1397 uses cumulative fault timer that allows for fault and also auto-recovery
periods adjustment

Ctimer

4u7 150k

- Time to fault confirmation:

 Vtimer ( on ) 
 = −150 ⋅10 3 ⋅ 4.7 ⋅10 −6 ⋅ ln1 − 
4
T fault = − R103 ⋅ C56 ⋅ ln1 − −6 
= 117 ms
 R103 ⋅ I timer 1   150 ⋅10 ⋅175 ⋅10 
3

- Time to auto-recovery time:

 Vtimer ( on ) 
Toff = R103 ⋅ C56 ⋅ ln   = 150 ⋅10 3 ⋅ 4.7 ⋅10 −6 ⋅ ln  4  = 977 ms
V  1
 timer ( off ) 

127 LLC resonant converter training. Brno 2012

DT, Fmin, Fmax resistor values
- Use NCP1397 DT, Fmin and Fmax nomograms from DS or calculate based on
below equations:
- Deadtime calculation
(
TDT = 4.28 ⋅10 −8 + RDT ⋅ 2.41 ⋅10 −11 )
- Fmin calculation based on Rdt and Rt
1 8 .9 ⋅ 10 − 7
f min = −
4 .64 ⋅ 10 −10 −11
⋅ Rt + 4 .8 ⋅ 10 ⋅ R DT + 8 ⋅ 10 −8
Rt
- Fmax calculation based on Rdt, Rt and Rfmax
1 8 ⋅10 7
f max = −
7.3 ⋅10 −11 ⋅ R f max ⋅ Rt R f max
+ 4.8 ⋅10 −11 ⋅ RDT + 8 ⋅10 −8
0.1⋅ Rt + 0.157 ⋅ R f max
=> Values for our design: Rdt = 13 kΩ, Rfmin = 30 kΩ Rfmax = 27 kΩ
Note: Excel sheet available
128 LLC resonant converter training. Brno 2012
Soft Start and frequency shift components
- R97 is used to slow down the frequency shift slope in order to overcome
oscillations during slight overloading
- Startup frequency is given by the total resistance connected to Rt pin during
application start:

R104 ⋅ ( R97 + R100 )

R Rt _ start =
R104 + R97 + R100

- RRrt_start value can be calculated from above equations or find in the Fmin vs.
Rfmin nomogram. The value of R100 can be then calculated as:
RRt _ start ⋅ R104 + RRt _ start ⋅ R104 − R97 ⋅ R104
R100 = = 6.2kΩ
R104 − RRt _ start

- Soft Start capacitor value C55 = 1 uf has been used to provide SS time constant
of ~ 6 ms (C55 - R100).
129 LLC resonant converter training. Brno 2012
FB pin and skip mode components
- R84 and R94 values has been used as compromise between optocoupler pole
position and light load consumption. R84 limits max. voltage on FB pin.

- FB pin voltage overshoot above 5.1 V during skip is given by FB loop response
and Skip pin divider R101, R105. The higher overshoot is the longer time SMPS
stays in skip mode – reducing switching losses.

130 LLC resonant converter training. Brno 2012

Secondary side design

- SR with parasitic inductance compensation is used to maximize efficiency when

SR MOSFETs in TO220 package are used

131 LLC resonant converter training. Brno 2012

SR design
Vds SR MOSFET losses:
- Conduction losses
Id
π
2

PCOND =  Iout ⋅  ⋅ Rds _ on @Vgs _ clamp
 4
=> Rds_on selection

- Gate drive losses

PDRV = Vcc ⋅ Vclamp ⋅ C g _ ZVS ⋅ f SW _ max

=> gate charge selection

- Body diode losses

π
2
I out 
SR controllers consumption and Pbody = ⋅V f +  I out ⋅  ⋅ Rdyn
gate drive losses in standby will 2  4
affect light load efficiency => Affected by diode Vf and
dynamic resistance

132 LLC resonant converter training. Brno 2012

SR design – MOSFET selection
• SR MOSFET works under ZVS conditions
=> Gate charge is given by Ciss capacitance (Cgs+Cgd) and
gate voltage

MOSFET Qg @ 5 V Qg @ 12 V Rds_on @ 5V Rds_on @ 12V

type [nC] [nC] Ω]
[mΩ Ω]
[mΩ
IPP015N04N 101 245 1.9 1.2
FDP047AN 39 96 5.8 4
IRFB3206 55 133 3.3 2.3
133 LLC resonant converter training. Brno 2012
Lpar compensation
1.8
Vclamp= 6 V Vclamp= 12 V
Total SR MOSFETs power losses 1.6

1.4
(conduction+driving) [W]

1.2

0.8

0.6

0.4

0.2

0
0 5 10 15 20
Output current [A]

134 LLC resonant converter training. Brno 2012

NCP4303 Zero Current Detection

- The Vcs_off threshold is 0 mV in case no resistor is used in CS

- Maximum conduction period of SR MOSFET is desirable for max efficiency
135 LLC resonant converter training. Brno 2012
SR MOSFET parasitic inductance impact

- The SR MOSFET conduction time is shortened when MOSFET in TO220 package

is used

136 LLC resonant converter training. Brno 2012

SR MOSFET parasitic inductance impact
• TO220 package is mostly used due to cost and also
simple soldering process

• Parasitic inductances Ldrain and Lsource create voltage drop that is

proportional to the secondary current Isec(t) derivative.
• The Vds voltage reaches zero level prior secondary current
• SR controller detects zero voltage in the time the secondary current has
still significant level => efficiency degradation
• Higher frequency or dIsec(t)/dt is, higher efficiency drop will be

137 LLC resonant converter training. Brno 2012

NCP4303 parasitic inductance compensation

Lcomp can be
done on PCB or
using ferrite bead

Secondary SR MOSFET
current gate voltage

SR MOSFET conduction period is maximized when

NCP4303 implemented with compensation Inductance
138 LLC resonant converter training. Brno 2012
SR MOSFET driver power dissipation
- Vcc related power dissipation
PIcc = Vcc ⋅ I cc = 35mW

- Driving losses related power dissipation

1  Rdrv _ low _ eq   Rdrv _ high _ eq 
PDRV _ IC = ⋅ C g _ ZVS ⋅ Vclamp ⋅ f SW ⋅ 
2
 + C g _ ZVS ⋅ Vclamp ⋅ f SW ⋅ (Vcc − Vclamp ) + 1 ⋅ C g _ ZVS ⋅ Vclamp 2 ⋅ f SW ⋅   = 76mW
   
2  Rdrv _ low _ eq + Rg _ int  2  Rdrv _ high _ eq + Rg _ int 

- DIE temperature related to above losses

TDIE = (PDRV_ IC + PIcc) ⋅ RθJ −A +TA = (0.076+ 0.035) ⋅180+ 60 = 80o C

139 LLC resonant converter training. Brno 2012

SR MOSFET snubbers
- Snubber is needed to suppress voltage ringing

Lsec,leak
Rsnubber = C snubber ≈ 3 → 4 ⋅ Coss
Coss

Minimum Ton and Toff blanking times

Ton _ min − 4.66 ⋅10−8 1.1⋅10−6 − 4.66 ⋅10−8
RT _ on _ min = = ≈ 11kΩ
9.82 ⋅10 −11 9.82 ⋅10−11

Toff _ min − 5.4 ⋅10−8 3.9 ⋅10 −6 − 5.4 ⋅10 −8

RT _ off _ min = = ≈ 39kΩ
9.56 ⋅10−11 9.56 ⋅10 −11

140 LLC resonant converter training. Brno 2012

Secondary filtering capacitor
- Filtering capacitor RMS current in LLC:

π2
I Cf _ RMS = I out _ nom ⋅ − 1 = 20 ⋅ 0.483 = 9.7 A
8
= > 8 x 1mF/35 V to be used
- ESR related ripple:
π
VCf _ ripple _ pk − pk = ESR ⋅ I rect _ peak = 2.2 ⋅10 −3 ⋅ ⋅ 20 = 69mV
2

- Capacitance related ripple:

I out _ nom 20
Vout _ ripple _ cap _ pk − pk = ⋅ (π − 2) = ⋅ (π − 2) = 4mV
2 ⋅ 3 ⋅ π ⋅ f op _ nom ⋅ C f 2 ⋅ 2 ⋅ π ⋅ 80 ⋅103 ⋅ 8 ⋅10 −3

- Filtering capacitor losses:

2 2
 π 2   π 2 
PCf _ ESR =  I out _ nom ⋅ − 1 ⋅ ESR =  20 ⋅ − 1 ⋅ 2.25 ⋅10 −3 = 0.21W
 8   8 
   

141 LLC resonant converter training. Brno 2012

Efficiency results
98
Vbulk= 400 V

96
LLC Stage Efficiency [%]

86
0 5 10 15 20
Iout [A]

IRFB3206 compensated IRFB3206 uncompensated

142 LLC resonant converter training. Brno 2012

Efficiency results
98
Vbulk=400 Vdc

94
Efficiency [%]

86
0 5 10 15 20
Output Current [A]

IPP015N014N compensated IPP015N04N uncompensated

143 LLC resonant converter training. Brno 2012

Operating wfms. – Full load operation

144 LLC resonant converter training. Brno 2012

Operating wfms. – light load (Iout=2.5 A)

145 LLC resonant converter training. Brno 2012

Thank you for your attention!

146 LLC resonant converter training. Brno 2012

Backup slides!

147 LLC resonant converter training. Brno 2012

148 LLC resonant converter training. Brno 2012

Operating states of the LLC converter – Discrete resonant tank solution:
A) Operating waveforms for fmin < fop < fs

A B C D E F GH

149 LLC resonant converter training. Brno 2012

Operating states of the LLC converter – Discrete resonant tank solution:
Operating intervals explanation – fmin < fop < fs:
A - Switch M1 has been turned ON (ZVS) and conducts together with secondary diode D1, primary current has
sinusoidal wave shape because the Cs and Ls form series resonant circuit, Lm doesn't participate
in the resonance now because it is clamped by the output impedance. Diode D1 current is nearly sinusoidal with
a slight distortion that is given by the primary magnetizing current that flows into Lm. Energy is taken from bulk.
B - Secondary current reached zero and corresponding diode D1 has been closed (ZCS), resonant circuit
has therefore been reconfigured to Cs - (Ls+Lm), primary current further increases but with slighter slope while
accumulating energy in the Lm and Ls. Energy is taken from bulk.
C - Switch M1 has been turned OFF, energy stored in the Lm and Ls prepares ZVS condition for opposite
switch M2 – overcharges the total parasitic capacitance on the bridge and opens M2 body diode. Energy is
supplied by Ls and Lm.
D - M2 body diode conducts current until M2 is turned ON by the controller. Diode D2 starts to conduct. Energy is
supplied by Ls and Lm until Is = 0. One part of the Lm+Ls energy holds ZVS for M2 and the other part goes to the output.
E - Switch M2 has been turned ON (ZVS) and conducts together with secondary diode D2, primary current has
sinusoidal wave shape because the Cs and Ls form series resonant circuit, Lm doesn't participate
in the resonance now because it is clamped by the output impedance. Diode D2 current is nearly sinusoidal with
a slight distortion that is given by the primary magnetizing current that flows into Lm. Energy is taken from Cs.
F - Secondary current reached zero and corresponding diode D2 has been closed (ZCS), resonant circuit
has therefore been reconfigured to Cs - (Ls+Lm), primary current further increases but with slighter slope while
accumulating energy in the Lm and Ls. Energy is taken from Cs.
G - Switch M2 has been turned OFF, energy stored in the Lm and Ls prepares ZVS condition for opposite
switch M1 – overcharges the total parasitic capacitance on the bridge and opens M1 body diode. Energy is
supplied by Ls and Lm.
H – M1 body diode conducts current until M1 is turned ON by the controller. Diode D1 starts to conduct. Energy is
supplied by Ls and Lm until Is = 0. One part of the Lm+Ls energy holds ZVS for M1 and the other part goes to the
output.
150 LLC resonant converter training. Brno 2012
Operating states of the LLC converter – Discrete resonant tank solution:
b) Operating waveforms for fop = fs

A B C D E F

151 LLC resonant converter training. Brno 2012

Operating states of the LLC converter – Discrete resonant tank solution:

Operating intervals explanation – fop = fs:

A - Switch M1 has been turned ON (ZVS) and conducts together with secondary diode D1, primary current has
sinusoidal wave shape because the Cs and Ls form series resonant circuit, Lm doesn't participate in the
resonance now because it is clamped by the output impedance. Diode D1 current is nearly sinusoidal with
a slight distortion that is given by the primary magnetizing current that flows into Lm. Energy is taken from bulk.
Diode D1 current reaches zero in the end of this interval (ZCS).
B - Switch M1 has been turned OFF, energy stored in the Lm and Ls prepares ZVS condition for opposite
switch M2 – overcharges the total parasitic capacitance on the bridge and opens M2 body diode. Energy is
supplied by Ls and Lm. Diode D2 starts to conduct.
C - M2 body diode conducts current until M2 is turned ON by the controller. Diode D2 conducts. Energy is
supplied by Ls and Lm until Is = 0. One part of the Lm+Ls energy holds ZVS for M2 and the other part goes
to the output.
D - Switch M2 has been turned ON (ZVS) and conducts together with secondary diode D2, primary current has
sinusoidal wave shape because the Cs and Ls form series resonant circuit, Lm doesn't participate in the
resonance now because it is clamped by the output impedance. Diode D2 current is nearly sinusoidal with
a slight distortion that is given by the primary magnetizing current that flows into Lm. Energy is taken from Cs.
Diode D2 current reaches zero in the end of this interval (ZCS).
E - Switch M2 has been turned OFF, energy stored in the Lm and Ls prepares ZVS condition for opposite
switch M1 – overcharges the total parasitic capacitance on the bridge and opens M1 body diode. Energy is
supplied by Ls and Lm. Diode D1 starts to conduct.
F – M1 body diode conducts current until M1 is turned ON by the controller. Diode D1 conducts. Energy is
supplied by Ls and Lm until Is = 0. One part of the Lm+Ls energy holds ZVS for M2 and the other part goes
to the output.

152 LLC resonant converter training. Brno 2012

Operating states of the LLC converter – Discrete resonant tank solution:
c) Operating waveforms for fop > fs

A B C D E F

153 LLC resonant converter training. Brno 2012

Operating states of the LLC converter – Discrete resonant tank solution:

Operating intervals explanation – fop > fs:

A - Switch M1 has been turned ON (ZVS) and conducts together with secondary diode D1, primary current has
sinusoidal wave shape because the Cs and Ls form series resonant circuit, Lm doesn't participate in the
resonance now because it is clamped by the output impedance. Diode D1 current is nearly sinusoidal with
a slight distortion that is given by the primary magnetizing current that flows into Lm. Energy is taken from bulk.
B - Switch M1 has been turned OFF, energy stored in the Ls prepares ZVS condition for opposite
switch M2 – overcharges the total parasitic capacitance on the bridge and opens M2 body diode. Energy is
supplied by Ls.
C - M2 body diode conducts current until M2 is turned ON by the controller. Current of the Lm Increases, current
of the Ls decreases until ILs=ILm. At the time ILs=ILm Diode D1 current reaches zero and transformer voltage
reverses D1 has been turned OFF with ZSC. Diode D2 is opened (by the energy stored in the Lm and Ls). The
Lm and Ls supply energy until the Is=0. Part of the Lm+Ls energy holds ZVS for M2 and part goes to the output.
D – Switch M2 has been turned ON (ZVS) and conducts together with secondary diode D2, primary current has
sinusoidal wave shape because the Cs and Ls form series resonant circuit, Lm doesn't participate in the
resonance now because it is clamped by the output impedance. Diode D2 current is nearly sinusoidal with
a slight distortion that is given by the primary magnetizing current that flows into Lm. Energy is taken from Cs.
E – Switch M2 has been turned OFF, energy stored in the Ls prepares ZVS condition for opposite switch M1
– overcharge total parasitic capacitance on the bridge and opens body diode of M1. Energy is supplied by Ls.
F – M1 body diode conducts until M1 is turned ON by the controller. Current of the Lm Increases, current of
the Ls decreases until ILs=ILm. At the time ILs=ILm Diode D2 current reaches zero and transformer voltage
reverses D2 has been turned OFF with ZSC. Diode D1 is opened (by the energy stored in the Lm and Ls). The
Lm and Ls supply energy until the Is=0. Part of the Lm+Ls energy holds ZVS for M1 and part goes to the output.

154 LLC resonant converter training. Brno 2012

Operating states of the LLC converter – Discrete resonant tank solution:
d) Operating waveforms for fmin < fop < fs – strong overload

A B C D E F G H

155 LLC resonant converter training. Brno 2012

Operating states of the LLC converter – Discrete resonant tank solution:
Operating intervals explanation – fop < fmin - strong overload :
A - Switch M1 has been turned ON (hard switching!) and conducts together with secondary diode D1, primary
current has sinusoidal wave shape because the Cs and Ls form series resonant circuit, Lm don't
participate on the resonance now because it is clamped by the output impedance. Diode D1 current is nearly sinusoidal
with a slight distortion that is given by the primary magnetizing current that flows into Lm. D1 closes at the end of
this period (ZCS).
B - D1 has been closed, resonant circuit has thus been reconfigured to Cs - (Ls+Lm), primary current continues
to flow but with different slope because Lm contributes on the resonance now.
C - Primary current crossed zero and continues in a opposite way – resonant tank supplies energy now.
D - Switch M1 has been turned OFF. Current is further flowing through the M1 body diode until switch M2 is
turned ON by the controller – we have prepared hard switching condition for the M1 body diode!!!
E - Switch M2 has been turned ON (hard switching!) and conducts together with secondary diode D2, primary
current has sinusoidal wave shape because the Cs and Ls form series resonant circuit, Lm don't
participate on the resonance now because it is clamped by the output impedance. Diode D2 current is nearly sinusoidal
with a slight distortion that is given by the primary magnetizing current that flows into Lm. D2 closes at the end of
this period (ZCS).
F – D2 has been closed, resonant circuit has thus been reconfigured to Cs - (Ls+Lm), primary current continues
to flow but with different slope because Lm contributes on the resonance now.
G - Primary current crossed zero and continues in a opposite way – resonant tank supplies energy now!
H - Switch M2 has been turned OFF. Current is further flowing through the M2 body diode until switch M1 is
turned ON by the controller – we have prepared hard switching condition for the M2 body diode!!!

Note: This operating mode is extremely dangerous because hard switching is achieved for
the MOSFET that is going to be turn ON and also for the body diode of the opposite MOSFET.
This situation can lead to the MOSFETs failure.

156 LLC resonant converter training. Brno 2012

Design Considerations
for an LLC Resonant Converter

Hangseok Choi
Power Conversion Team

www.fairchildsemi.com
1. Introduction
Growing demand for higher power
density and low profile in power
High frequency
converter has forced to increase operation
switching frequency
However, Switching Loss has been
an obstacle to high frequency
operation

Overlap of voltage and current Capacitive loss Reverse recovery loss

2
1. Introduction

Resonant converter: processes power in a sinusoidal manner and

the switching devices are softly commutated
9 Voltage across the switch drops to zero before switch turns on (ZVS)
• Remove overlap area between V and I when turning on
• Capacitive loss is eliminated
Series resonant converter / Parallel resonant converter

3
1. Introduction

Series Resonant (SR) converter

Q1 resonant network
Ip
Vin n:1
Vd +
Lr Ro
Q2 VO
Lm -
Ids2 Cr

The resonant inductor (Lr) and resonant capacitor (Cr) are in series
The resonant capacitor is in series with the load
9 The resonant tank and the load act as a voltage dividerÆ DC gain is always
lower than 1 (maximum gain happens at the resonant frequency)
9 The impedance of resonant tank can be changed by varying the frequency
of driving voltage (Vd)

4
1. Introduction

Series Resonant (SR) converter

Advantages
9 Reduced switching loss and EMI through ZVS Æ Improved
efficiency
9 Reduced magnetic components size by high frequency operation

Drawbacks
9 Can optimize performance at one operating point, but not with wide
range of input voltage and load variations
9 Can not regulate the output at no load condition
9 Pulsating rectifier current (capacitor output): limitation for high
output current application

5
1. Introduction

Parallel Resonant (PR) converter

Q1 resonant network
Ip
Vin n:1
Vd +
Llkp Ro
Q2 VO
Cr
-
Ids2

The resonant inductor (Lr) and resonant capacitor (Cr) are in series
The resonant capacitor is in parallel with the load
9 The impedance of resonant tank can be changed by varying the
frequency of driving voltage (Vd)

6
1. Introduction

Parallel Resonant (PR) converter

Advantages
9 No problem in output regulation at no load condition
9 Continuous rectifier current (inductor output): suitable for high
output current application

Drawbacks
9 The primary side current is almost independent of load condition:
significant current may circulate through the resonant network,
even at the no load condition
9 Circulating current increases as input voltage increases: limitation
for wide range of input voltage

7
1. Introduction

What is LLC resonant converter?

9 Topology looks almost same as the conventional LC series
resonant converter
9 Magnetizing inductance (Lm) of the transformer is relatively small
and involved in the resonance operation
9 Voltage gain is different from that of LC series resonant converter

LC Series resonant converter LLC resonant converter

8
1. Introduction

Features of LLC resonant converter

- Reduced switching loss through ZVS: Improved efficiency
- Narrow frequency variation range over wide load range
- Zero voltage switching even at no load condition

- Typically, integrated transformer is used instead of discrete magnetic

components

9
1. Introduction

Integrated transformer in LLC resonant converter

9 Two magnetic components are implemented with a single core (use
the primary side leakage inductance as a resonant inductor)
9 One magnetic components (Lr) can be saved
9 Leakage inductance not only exists in the primary side but also in
the secondary side
9 Need to consider the leakage inductance in the secondary side

Q1 Integrated transformer
Q1

Vin Io Ip Io
n:1 ID Vin n:1 ID
Vd + Vd +
Ro Ro
Lr Llkp Llks
Q2 VO Q2 VO
Lm Im
- Lm -
Ids2 Cr Ids2 Cr

10
2. Operation principle and Fundamental Approximation

Square wave generator: produces a square wave voltage, Vd by driving switches,

Q1 and Q2 with alternating 50% duty cycle for each switch.
Resonant network: consists of Llkp, Llks, Lm and Cr. The current lags the voltage
applied to the resonant network which allows the MOSFET’s to be turned on
with zero voltage.
Rectifier network: produces DC voltage by rectifying AC current
Ip

Im
Square wave generator
Ids2
Q1 resonant network Rectifier network
Ip Io
Vin n:1 ID
Vd +
ID
Llkp Llks Ro
Q2 Im VO Vin
Vd
Lm - (Vds2)
Ids2 Cr
Vgs1

Vgs2

11
2. Operation principle and Fundamental Approximation

The resonant network filters the higher harmonic currents. Thus, essentially
only sinusoidal current is allowed to flow through the resonant network even
though a square wave voltage (Vd) is applied to the resonant network.
Fundamental approximation: assumes that only the fundamental component of
the square-wave voltage input to the resonant network contributes to the power
transfer to the output.
The square wave voltage can be replaced by its fundamental component

Isec Ip Isec
Ip
Vd Vd Resonant
Resonant
netw ork netw ork

12
2. Operation principle and Fundamental Approximation

Because the rectifier circuit in the secondary side acts as an impedance

transformer, the equivalent load resistance is different from actual load resistance.

The primary side circuit is replaced

pk
by a sinusoidal current source (Iac) I ac
and a square wave of voltage (VRI) Io
appears at the input to the rectifier.
The equivalent load resistance is Iac +
+
obtained as VRI VO
Ro
- -
F F
VRI VRI 8 Vo 8
Rac = = = = Ro
I ac F
I ac π Io π
2 2
π ⋅ Io
Iac I ac = sin( wt )
2
VRIF
Vo
4Vo
VRI VRI F = sin( wt )
π

13
2. Operation principle and Fundamental Approximation

AC equivalent circuit (L-L-L-C)

4n ⋅ Vo
sin(ωt )
Cr Llks VRO n ⋅ VRI
F
π
F
2n ⋅ Vo
Vd Llkp + M= F = = =
+ VO Vd Vd F 4 Vin
sin(ωt ) Vin
+
Vin π 2
Lm VRI
Ro
-
- ω 2 Lm Rac Cr
n:1 =
- ω2 ω2
jω ⋅ (1 − 2 ) ⋅ ( Lm + n Llks ) + Rac (1 − 2 )
2

ωo ωp
8n 2
Rac = Ro
π2
n2Llks 8n 2
Rac = Ro
π2
Cr Llkp 1 1
ωo = , ωp =
VdF Rac VROF Lr Cr L p Cr
Lm
Lp = Lm + Llkp , Lr = Llkp + Lm //(n 2 Llks )

- Lr is measured in primary side with secondary winding short circuited

- Lp is measured in primary side with secondary winding open circuited

14
2. Operation principle and Fundamental Approximation

Simplified AC equivalent circuit (L-L-C)

Cr Llkp Llks
Assuming Llkp=n2Llks
Vd +
Vin
+
+
VO ω2 k
( 2)
Lm VRI 2n ⋅ VO ωp k +1
M= =
- Ro Vin ω ω2 (k + 1) 2 ω2
- j ( ) ⋅ (1 − 2 ) ⋅ Q + (1 − 2 )
n:1
- ωo ωo 2k + 1 ωp
Lr = Llkp + Lm //(n Llks )
2

= Llkp + Lm // Llkp Lr / Cr Lm
Lp
Q= k=
L p = Llkp + Lm 1: Rac Llkp
L p − Lr

Cr Lr Expressing in terms of Lp and Lr

VinF Lp-Lr Rac VROF
ω 2 Lp − Lr
( 2)
2n ⋅ VO ωp Lp
M= =
Vin ω ω2 Lp ω2
- Lr is measured in primary side with secondary winding short circuited j ( ) ⋅ (1 − 2 ) ⋅ Q + (1 − 2 )
ωo ωo Lr ωp
- Lp is measured in primary side with secondary winding open circuited

15
2. Operation principle and Fundamental Approximation

Gain characteristics LLC resonant C onverter

fp fo
9 Two resonant frequencies (fo and fp) 2.0
exist Lr / Cr
Q=0.2 Q=
9 The gain is fixed at resonant frequency 1.8
Rac
(fo) regardless of the load variation Q= 1

1.6 Q = 0.8
Q = 0.6

k +1 Lp Q = 0.4
= =
1.4
M @ω =ωo
Lp − Lr

G ain
Q = 0.2
k
1.2

9 Peak gain frequency exists between fo Q=1

1.0
and fp
9 As Q decreases (as load decreases), k +1 Lp
0.8 M= =
the peak gain frequency moves to fp and k Lp − Lr
higher peak gain is obtained.
0.6
9 As Q increases (as load increases), 40 50 60 70 80 90 100 110 120 130 140

peak gain frequency moves to fo and the freq (kH z)

peak gain drops

16
2. Operation principle and Fundamental Approximation

Peak gain (attainable maximum gain) versus Q for different k values

2.4

2.2

2.0

k=1.5
Peak Gain

1.8
k=1.75
k=2
1.6

k=2.5

1.4 k=3

k=4
k=5
1.2
k=7
k=9
1
0.2 0.4 0.6 0.8 1 1.2 1.4

17
3. Design procedure

Design example
- Input voltage: 380Vdc (output of PFC stage)
- Output: 24V/5A (120W)
- Holdup time requirement: 17ms
- DC link capacitor of PFC output: 100uF

PFC DC/DC
Q1 ID

Ip
VDL Np:Ns
Vd VO
Llkp Llks + Ro
CDL Q2 Im
Lm -
Ids2 Cr

18
3. Design procedure

[STEP-1] Define the system specifications

9 Estimated efficiency (Eff)
9 Input voltage range: hold up time should be considered for minimum input voltage

2 PinTHU
Vin min = VO. PFC 2 −
CDL

19
3. Design procedure

[STEP-2] Determine the maximum and minimum voltage gains of the

resonant network by choosing k ( k = Lm / Llkp )
- it is typical to set k to be 5~10, which results in a gain of 1.1~1.2 at fo

VRO Lm + n 2 Llks Lm + Llkp k + 1

M min
= max = = =
Vin Lm Lm k Gain (M)
2 Peak gain (available maximum gain)

Vin max min 1.36 for Vinmin

M max
= min M Mmax
Vin

1.14
Mmin for Vinmax

k +1
M= = 1.14
k

fs
fo

20
3. Design procedure

[STEP-3] Determine the transformer turns ratio (n=Np/Ns)

Np Vin max
n= = ⋅ M min
N s 2 (Vo + VF )

[STEP-4] Calculate the equivalent load resistance (Rac)

8n 2 Vo 2
Rac = 2
π Po

21
3. Design procedure

[STEP-5] Design the resonant network

- With k chosen in STEP-2, read proper Q from gain curves

k = 7 , M max = 1.36
peak gain = 1.36 × 110% = 1.5

22
3. Design procedure

[STEP-6] Design the transformer

- Plot the gain curve and read the minimum switching frequency. Then, the minimum
number of turns for the transformer primary side is obtained as
n(Vo + VF )
N p min =
2 f s min ⋅ ΔB ⋅ Ae

23
3. Design procedure

[STEP-7] Transformer Construction

- Since LLC converter design results in relatively large Lr, usually sectional bobbin is typically
used
- # of turns and winding configuration are the major factors determining Lr
- Gap length of the core does not affect Lr much
- Lp can be easily controlled with gap length

Np=52T Ns1=Ns2=6T
Bifilar

Design value: Lr=234uH, Lp=998uH

24
3. Design procedure

[STEP-8] Select the resonant capacitor

π Io n(V + 2 ⋅ VF ) 2 Vin max 2 ⋅ I Cr RMS

I Cr RMS
≅ [ ] +[ o
2
] VCr max
≅ +
2 2n 4 2 f o Lm 2 2 ⋅ π ⋅ f o ⋅ Cr

25
4. Conclusion

Using a fundamental approximation, gain equation has

been derived

Leakage inductance in the secondary side is also

considered (L-L-L-C model) for gain equation

L-L-L-C equivalent circuit has been simplified as a

conventional L-L-C equivalent circuit

Practical design consideration has been presented

26
Appendix - FSFR-series

Variable frequency control with 50% duty cycle for half-bridge resonant
converter topology
High efficiency through zero voltage switching (ZVS)
Internal Super-FETs with Fast Recovery Type Body Diode (trr=120ns)
Fixed dead time (350ns)
Up to 300kHz operating frequency
Pulse skipping for Frequency limit (programmable) at light load condition
Simple remote ON/OFF control
Various Protection functions: Over Voltage Protection (OVP), Over Current
Protection (OCP), Abnormal Over Current Protection (AOCP), Internal Thermal
Shutdown (TSD)

27
Appendix - FSFR-series demo board

28
Appendix - FSFR-series demo board

29
AN2644
Application note
An introduction to LLC resonant
half-bridge converter

Introduction
Although in existence for many years, only recently has the LLC resonant converter, in
particular in its half-bridge implementation, gained in the popularity it certainly deserves. In
many applications, such as flat panel TVs, 85+ ATX PCs or small form factor PCs, where the
requirements on efficiency and power density of their SMPS are getting tougher and
tougher, the LLC resonant half-bridge with its many benefits and very few drawbacks is an
excellent solution. One of the major difficulties that engineers are facing with this topology is
the lack of information concerning the way it operates. The purpose of this application note
is to provide insight into the topology and help familiarize the reader with it, therefore, the
approach is essentially descriptive.

Figure 1. LLC resonant topology schematics and waveforms

September 2008 Rev 2 1/64

www.st.com
Contents AN2644

Contents

1 Classification of resonant converters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 The LLC resonant half-bridge converter . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 General overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 The switching mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Fundamental operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.1 Operation at resonance (f = fR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.3.2 Operation above resonance (f > fR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CCMA operation at heavy load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
DCMA at medium load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
DCMAB at light load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3.3 Operation below resonance (fR2 < f < fR1, R>Rcrit) . . . . . . . . . . . . . . . . 30
DCMAB at medium-light load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
DCMB at heavy load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.4 Capacitive-mode operation below resonance (fR2 < f < fR1, R<Rcrit) . . . 34
Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

2.4 No-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.5 Overload and short circuit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.6 Converter's startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.7 Analysis of power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.8 Small-signal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.8.1 Operation above resonance (f > fR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.8.2 Operation below resonance (fR2 < f < fR1, R>Rcrit) . . . . . . . . . . . . . . . . 44
2.8.3 Operation at resonance (f = fR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Appendix A Power MOSFET driving energy in ZVS operation . . . . . . . . . . . . . . 48

2/64
AN2644 Contents

Appendix B Resonant transitions of half-bridge midpoint . . . . . . . . . . . . . . . . . 50

Appendix C Power MOSFET effective Coss and half-bridge midpoint's transition

times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Appendix D Power MOSFETs switching losses at turn-off. . . . . . . . . . . . . . . . . 59

Appendix E Input current in LLC resonant half-bridge with split resonant

capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3/64
List of figures AN2644

List of figures

Figure 1. LLC resonant topology schematics and waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. General block diagram of a resonant inverter, the core of resonant converters . . . . . . . . . . 5
Figure 3. LLC resonant half-bridge schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. LLC resonant half-bridge with split resonant capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Equivalent schematic of a real transformer (left, tapped secondary; right, single
secondary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Example of high-leakage magnetic structures (cross-section) . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Equivalent schematic of a transformer including parasitic capacitance . . . . . . . . . . . . . . . 12
Figure 8. Power MOSFET totem-pole network driving a resonant tank circuit in a half-bridge
converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Detail of Q1 ON-OFF and Q2 OFF-ON transitions with soft-switching for Q2 . . . . . . . . . . 14
Figure 10. Q2 gate voltage at turn-on: with soft-switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Q2 gate voltage at turn-on: with hard-switching (no ZVS) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Q1 ON-OFF and Q2 OFF-ON transitions with hard switching for Q2 and recovery for
DQ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Bridge leg transitions in the neighborhood of inductive-capacitive regions boundary . . . . 17
Figure 14. Bridge leg transitions under no-load conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Reference LLC converter for the analysis of the fundamental operating modes . . . . . . . . 21
Figure 16. Operation at resonance (f = fR1): main waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17. Operation above resonance (f > fR1): main waveforms in CCMA operation at heavy load 25
Figure 18. Operation above resonance (f > fR1): main waveforms in DCMA operation at medium
load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 19. Operation above resonance (f > fR1): main waveforms in DCMAB operation at light
load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20. Operation below resonance (fR2 < f < fR1 , R>Rcrit): main waveforms in DCMAB
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 21. Operation below resonance (fR2 < f < fR1, R>Rcrit): main waveforms in DCMB2 operation 32
Figure 22. Capacitive mode operation below resonance (fR2 < f < fR1, R<Rcrit): main waveforms . . . 35
Figure 23. No-load operation (cutoff): main waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 24. Circuit's equivalent schematic under: no-load conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 25. Circuit's equivalent schematic under: short-circuit conditions. . . . . . . . . . . . . . . . . . . . . . . 38
Figure 26. Converter's startup: main waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 27. High-side driving with bootstrap approach and bootstrap capacitor charge path . . . . . . . . 41
Figure 28. Frequency compensation with an isolated type 3 amplifier (3 poles + 2 zeros) . . . . . . . . 45
Figure 29. Comparison of gate-charge characteristics with and without ZVS . . . . . . . . . . . . . . . . . . . 48
Figure 30. Equivalent circuit to analyze the transitions of the half-bridge midpoint node when Q2
turns off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 31. Voltage of HB node vs time (see Equation 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 32. Resonant current vs time (see Equation 34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 33. Capacitance associated to the half-bridge midpoint node . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 34. Coss capacitances vs. half-bridge midpoint's voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 35. Simplified schematic to analyze transition times of the node HB when Q2 turns off . . . . . 56
Figure 36. Schematization of Q2 turn-off transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 37. Input current components in a split-capacitor LLC resonant half-bridge. . . . . . . . . . . . . . . 61
Figure 38. Timing diagram showing currents flow in the converter of Figure 37 . . . . . . . . . . . . . . . . . 61

4/64
AN2644 Classification of resonant converters

1 Classification of resonant converters

Resonant conversion is a topic that is at least thirty years old and where much effort has
been spent in research in universities and industry because of its attractive features: smooth
waveforms, high efficiency and high power density. Yet the use of this technique in off-line
powered equipment has been confined for a long time to niche applications: high-voltage
power supplies or audio systems, to name a few. Quite recently, emerging applications such
as flat panel TVs on one hand, and the introduction of new regulations, both voluntary and
mandatory, concerning an efficient use of energy on the other hand, are pushing power
designers to find more and more efficient AC-DC conversion systems. This has revamped
and broadened the interest in resonant conversion. Generally speaking, resonant
converters are switching converters that include a tank circuit actively participating in
determining input-to-output power flow. The family of resonant converters is extremely vast
and it is not an easy task to provide a comprehensive picture. To help find one's way, it is
possible to refer to a property shared by most, if not all, of the members of the family. They
are based on a "resonant inverter", i.e. a system that converts a DC voltage into a sinusoidal
voltage (more generally, into a low harmonic content ac voltage), and provides ac power to a
load. To do so, a switch network typically produces a square-wave voltage that is applied to
a resonant tank tuned to the fundamental component of the square wave. In this way, the
tank will respond primarily to this component and negligibly to the higher order harmonics,
so that its voltage and/or current, as well as those of the load, will be essentially sinusoidal
or piecewise sinusoidal. As shown in Figure 2, a resonant DC-DC converter able to provide
DC power to a load can be obtained by rectifying and filtering the ac output of a resonant
inverter.

Figure 2. General block diagram of a resonant inverter, the core of resonant

converters

Switch Resonant
Vindc network tank circuit Voutac

Resonant Inverter

Switch Resonant Low-pass

Vindc Rectifier Voutdc
network tank circuit filter

Resonant Converter

Different types of DC-AC inverters can be built, depending on the type of switch network and
on the characteristics of the resonant tank, i.e. the number of its reactive elements and their
configuration [1].
As to switch networks, we will limit our attention to those that drive the resonant tank
symmetrically in both voltage and time, and act as a voltage source, namely the half-bridge
and the full-bridge switch networks. Borrowing the terminology from power amplifiers,

5/64
Classification of resonant converters AN2644

switching inverters driven by this kind of switch network are considered part of the group
called "class D resonant inverters".
As to resonant tanks, with two reactive elements (one L and one C) there are a total of eight
different possible configurations, but only four of them are practically usable with a voltage
source input. Two of them generate the well-known series resonant converter and parallel
resonant converter considered in [2] and thoroughly treated in literature.
With three reactive elements the number of different tank circuit configurations is thirty-six,
but only fifteen can be used in practice with a voltage source input. One of these, commonly
called LCC because it uses one inductor and two capacitors, with the load connected in
parallel to one C, generates the LCC resonant inverter commonly used in electronic lamp
ballast for gas-discharge lamps. Its dual configuration, using two inductors and one
capacitor, with the load connected in parallel to one L, generates the LLC inverter.
As previously stated, for any resonant inverter there is one associated DC-DC resonant
converter, obtained by rectification and filtering of the inverter output. Predictably, the above-
mentioned class of inverters will originate the "class D resonant converters". Considering
off-line applications, in most cases the rectifier block will be coupled to the resonant inverter
through a transformer to guarantee the isolation required by safety regulations. To maximize
the usage of the energy handled by the inverter, the rectifier block can be configured as
either a full-wave rectifier, which needs a center tap arrangement of transformer's secondary
winding, or a bridge rectifier, in which case tapping is not needed. The first option is
preferable with a low voltage / high current output; the second option with a high voltage /
low current output. As to the low-pass filter, depending on the configuration of the tank
circuit, it will be made by capacitors only or by an L-C type smoothing filter. The so-called
"series-parallel" converter described in [2], typically used in high-voltage power supply, is
derived from the previously mentioned LCC resonant inverter. Its dual configuration, the LLC
inverter, generates the homonymous converter, addressed in [3], [4] and [5], that will be the
subject of the following discussion. In particular we will consider the half-bridge
implementation, illustrated in Figure 3, but the extension to the full-bridge version is quite
straightforward.

Figure 3. LLC resonant half-bridge schematic

Q1
Center-tapped output with full-wave
rectification
Cr Ls
Half-bridge

(low voltage and high current)

Driver

Vin a:1:1
D1 R
Q2
Lp Vout
LLC tank circuit D2

Single-ended output with bridge

rectification
(high voltage and low current)
Preferably integrated into a single
a:1 D1
magnetic structure
R
D4
D3 Vout

6/64
AN2644 The LLC resonant half-bridge converter

In resonant inverters (and converters too) power flow can be controlled by the switch
network either by changing the frequency of the square wave voltage, or its duty cycle, or
both, or by special control schemes such as phase-shift control. In this context we will focus
on power flow control by frequency modulation, that is, by changing the frequency of the
square wave closer to or further from the tank circuit's resonant frequency while keeping its
duty cycle fixed.

2 The LLC resonant half-bridge converter

2.1 General overview

According to another way of designating resonant converters, the LLC resonant half-bridge
belongs to the family of multiresonant converters. Actually, since the resonant tank includes
three reactive elements (Cr, Ls and Lp, shown in Figure 3), there are two resonant
frequencies associated to this circuit. One is related to the condition of the secondary
winding(s) conducting, where the inductance Lp disappears because dynamically shorted
out by the low-pass filter and the load (there is a constant voltage a Vout across it):

Equation 1
1
f R1 = ----------------------------
-
2π Ls ⋅ Cr

the other resonant frequency is relevant to the condition of the secondary winding(s) open,
where the tank circuit turns from LLC to LC because Ls and Lp can be unified in a single
inductor:

Equation 2
1
f R2 = ------------------------------------------
-
2π ( Ls + Lp )Cr

It will be of course fR1 > fR2. Normally, fR1 is referred to as the resonance frequency of the
LLC resonant tank, while fR2 is sometimes called the second (or lower) resonance
frequency. The separation between fR1 and fR2 depends on the ratio of Lp to Ls. The larger
this ratio is, the further the two frequencies will be and vice versa. The value of Lp/Ls
(typically > 1) is an important design parameter.
It is possible to show that for frequencies f > fR1 the input impedance of the loaded resonant
tank is inductive and that for frequencies f < fR2 the input impedance is capacitive. In the
frequency region fR2 < f < fR1 the impedance can be either inductive or capacitive depending
on the load resistance R. A critical value Rcrit exists such that if R < Rcrit then the
impedance will be capacitive, inductive for R> Rcrit. For a given tank circuit the value of Rcrit
depends on f. More precisely, in [6] it is shown that for any tank circuit configuration (then for
the LLC in particular):

Equation 3
R crit = Zo 0 ⋅ Zo ∞

where Zo0 and Zo∞ are the resonant tank output impedances with the source input short-
circuited and open-circuited, respectively.

7/64
The LLC resonant half-bridge converter AN2644

For certain reasons that will be clarified in the following sections, the LLC resonant
converter is normally operated in the region where the input impedance of the resonant tank
has inductive nature, i.e. it increases with frequency. This implies that power flow can be
controlled by changing the operating frequency of the converter in such a way that a
reduced power demand from the load produces a frequency rise, while an increased power
demand causes a frequency reduction.
The Half-bridge Driver switches the two power MOSFETs Q1 and Q2 on and off in phase
opposition symmetrically, that is, for exactly the same time. This is commonly referred to as
"50% duty cycle" operation even if the conduction time of either power MOSFET is slightly
shorter than 50% of the switching period. In fact, a small deadtime is inserted between the
turn-off of either switch and the turn-on of the complementary one. The role of this deadtime
is essential for the operation of the converter. It goes beyond ensuring that Q1 and Q2 will
never cross-conduct and will be clarified in the next sections as well. For the moment it will
be neglected, and the voltage applied to the resonant tank will be a square-wave with 50%
duty cycle that swings all the way from 0 to Vin. Before going any further, however, it is
important to make one concept clear.

Figure 4. LLC resonant half-bridge with split resonant capacitor

Q1
Cr / 2
Ls
Half-bridge
Driver

a:1:1
Vin
Q2
Lp Cr / 2

A few paragraphs above, the impedance of the tank circuit was mentioned. Impedance is a
concept related to linear circuits under sinusoidal excitation, whereas in this case the
excitation voltage is a square wave.
However, as a consequence of the selective nature of resonant tanks, most power
processing properties of resonant converters are associated with the fundamental
component of the Fourier expansion of voltages and currents in the circuit. This applies in
particular to the input square wave and is the foundation of the First Harmonic
Approximation (FHA) modeling methodology presented in [2] as a general approach and
used in [4] and [5] for the LLC resonant converter specifically. This approach justifies the
usage of the concept of impedance as well as those coming from complex ac circuit
analysis.
Coming back to the input square wave excitation, it has a DC component equal to Vin/2. In
the LLC resonant tank the resonant capacitor Cr is in series to the voltage source and under
steady state conditions the average voltage across inductors must be zero. As a result, the
DC component Vin/2 of the input voltage must be found across Cr which consequently plays
the double role of resonant capacitor and DC blocking capacitor.
It is possible to see, especially at higher power levels, a slightly modified version of the LLC
resonant half-bridge converter, where the resonant capacitor is split as illustrated in
Figure 4. This configuration can be useful to reduce the current stress in each capacitor

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AN2644 The LLC resonant half-bridge converter

and, in certain conditions, the initial imbalance of the V·s applied to the transformer at start
up (see "Converter's start-up" section). Additionally, it makes the input current to the
converter look like that of a full-bridge converter, as shown in Appendix E, with a resulting
reduction in both the input differential mode noise and the stress of the input capacitor.
Obviously, the currents through Q1 and Q2 will be unchanged. It is easy to recognize that
the two Cr/2 capacitors are dynamically in parallel, so that the total resonant tank's
capacitance is again Cr.
The system appears quite bulky, with its three magnetic components. However, the LLC
resonant topology lends itself well to magnetic integration. With this technique inductors and
transformers are combined into a single physical device to reduce component count, usually
with little or no penalty to the converter's characteristics, sometimes even enhancing its
operation. To understand how magnetic integration can be done, it is worth looking at the
well-known equivalent schematics of a real transformer in Figure 5 and comparing them to
the inductive component set of Figure 3.
Lp occupies the same place as the magnetizing inductance LM, Ls the same place as the
primary leakage inductance LL1. Then, assuming that we are going to use a ferrite core plus
bobbin assembly, Lp can be used as the magnetizing inductance of the transformer with the
addition of an air gap into the magnetic circuit and leakage inductance can be used to make
Ls.

Figure 5. Equivalent schematic of a real transformer (left, tapped secondary; right,

single secondary)
i1(t) LL1 n:1:1 LL2 i (t) i1(t) LL1 n:1 LL2 i (t)
2 2

iM(t) iM(t)
v2(t)

v1(t) LM v1(t) LM v2(t)

v2(t)
LL2
ideal ideal

To do so, however, a leaky magnetic structure is needed, which is contrary to the traditional
transformer design practice that aims at minimizing leakage inductance. The usual
concentric winding arrangement is not recommended here, although higher leakage
inductance values can be achieved by increasing the space between the windings.

Figure 6. Example of high-leakage magnetic structures (cross-section)

Primary Primary
winding winding

Secondary Secondary
winding winding

Windings on separate legs of an EE core Side-by-side windings (EE or pot core)

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The LLC resonant half-bridge converter AN2644

It is difficult, however to obtain reproducible values, because they depend on parameters

(such as winding surface irregularities or spacer thickness) difficult to control. Other fashions
are recommended, such as placing the windings on separate core legs (using E or U cores)
or side by side on the same leg which is possible with both E and pot cores and shown in
Figure 6. They permit reproducible leakage inductance values, because related to the
geometry and the mechanical tolerances of the bobbin, which are quite well controlled. In
addition, these structures possess geometric symmetry, so they lead to magnetic devices
with an excellent magnetic symmetry.
However, in the real transformer model of Figure 5 there is the secondary leakage
inductance LL2 that is not considered in the model of Figure 3. The presence of LL2 is not a
problem from the modeling point of view because the transformer's equivalent schematic
can be manipulated so that LL2 disappears (it is transferred to the primary side and
incorporated in LL1). This is exactly what has been done in the transformer model shown in
Figure 3. Then, it is important to underline that Ls and Lp are not real physical inductances
(LL1, LM and LL2 are), their numerical values are different (Ls ≠ LL1, Lp ≠ LM), and, finally, the
turn ratio a is not the physical turn ratio n=N1/N2. Ls and Lp can be given a physical
interpretation. Ls is the inductance of the primary winding measured with the secondary
winding(s) shorted, while Lp is the difference between the inductance of the primary winding
measured with the secondary windings open and Ls.
However, LL2 is not free from side effects. For a given impressed voltage, LL2 decreases the
voltage available on the secondary winding, which carries a current i2, by the drop LL2·di2/dt.
This is an effect that is taken into account by the above mentioned manipulation of the
transformer model. In addition, in multioutput converters, where there is leakage inductance
associated to each output winding, cross-regulation between the various outputs will be
adversely affected because of their decoupling effect.
Finally, there is one more adverse effect to consider in the center-tapped output
configuration. With reference to Figure 3 and 5, when one half-winding is conducting, the
voltage v2(t) externally applied to that half-winding is Vout+VF (VF is the rectifier forward drop
of the conducting diode). With no secondary leakage inductance, this voltage will be found
across the secondary winding of the ideal transformer and then coupled one-to-one to the
nonconducting half-winding. Consequently, the reverse voltage applied to the reverse-
biased rectifier will be 2·Vout+VF. If now we introduce the leakage inductance LL2, the drop
LL2·di2/dt adds up to Vout+VF. and is reflected to the other half-winding as well. As a result,
the reverse voltage applied to the nonconducting rectifier will be increased by LL2·di2/dt.
Note that in case of single-winding secondary with bridge rectification, the voltage applied to
reverse-biased diodes of the bridge is only Vout+VF and is not affected by LL2. The reason is
that the negative voltage of the secondary winding is fixed at -VF externally and is not
determined by internal coupling like in the case of tapped secondary.
It is worth pointing out that the 50% duty cycle operation of the LLC half-bridge equalizes
the stress of secondary rectifiers both in terms of reverse voltage - as just seen - and
forward conduction current. In fact, each rectifier carries half the total output current under
all operating conditions. Then, if compared to similar PWM converters (such as the ZVS
Asymmetrical Half-bridge, or the Forward converter), in the center-tapped output
configuration the equal reverse voltage typically allows the use of lower blocking voltage
rating diodes. This is especially true when using common cathode diodes housed in a single
package. A lower blocking voltage means also a lower forward drop for the same current
rating, and then lower losses.
It must be said, however, that in the LLC resonant converter the output current form factor is
worse, so the output capacitor bank is stressed more. Although the stress level is

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AN2644 The LLC resonant half-bridge converter

considerably lower than that in a flyback converter, as shown in Table 1, this is one of the
few real drawbacks of the topology.

Table 1. Output stress for LLC resonant half-bridge vs. PWM topologies @ 50% duty cycle
Output current form factors Forward - ZVS AHB LLC resonant HB Flyback (CCM-DCM boundary)

≈1.05÷1.15 π
Peak-to-DC ratio ≈ --- = 1.57 4
2

π 8
Rms-to-DC ratio ≈1 ≈ ----------- = 1.11 --- ≈ 1.63
2 2 3

2
AC-to-DC ratio ≈0.03÷0.09 π - – 1 = 0.48
≈ -----
8
--- – 1 ≈ 1.29
8 3

Additional details concerning power losses will be discussed in Analysis of power losses on
page 41.
To complete the general picture on the LLC resonant converter, there is another aspect that
needs to be addressed concerning parasitic components which affect the behavior of the
circuit.
The first parasitic element to consider is the capacitance of the midpoint of the half-bridge
structure, the node common to the source of the high-side power MOSFET and to the drain
of the low-side power MOSFET. Its effect is that the transitions of the half-bridge midpoint
will require some energy and take a finite time to complete. This is linked to the previously
mentioned deadtime inserted between the turn-off of either switch and the turn-on of the
complementary one, and will be discussed in more detail in Section 2.2.
The second parasitic element to consider is the distributed capacitance of transformer's
windings. This capacitance, which exists for both the primary and the secondary windings,
in combination with windings' inductance, originates what is commonly designated as the
transformer "self-resonance". In addition to this capacitance one needs to consider also the
junction capacitance of the secondary rectifiers, which adds up to that of the secondary
windings and lowers the resulting self-resonance frequency (loaded self-resonance).
The effect of all this parasitic capacitance can be modeled with a single capacitor CP
connected in parallel to LM as illustrated in Figure 7. The resonant tank, as a consequence,
turns from LLC to LLCC. This 4th- order tank circuit features a third resonance frequency at
the transformer's loaded self-resonance (fLSR > fR1). When the operating frequency is
considerably lower than fLSR the effect of CP is negligible. However, at frequencies greater
than fR1 and if the load impedance is high enough, its effect starts making itself felt,
eventually resulting in reversing the transferable power vs. frequency relationship as
frequency approaches fLSR. Power now increases with the switching frequency, feedback
becomes positive and the converter loses control of the output voltage. The onset of this
"feedback reversal" in closed-loop operation is revealed by a sudden frequency jump to its
maximum value as the load falls below a critical value (i.e. the frequency exceeds a critical
value) and a simultaneous output voltage rise.
In some way, either appropriately choosing the operating frequency range (<< fLSR) or
increasing fLSR, the converter must work away from feedback reversal. This usually sets the
practical upper limit to a converter's operating frequency range.

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The LLC resonant half-bridge converter AN2644

Figure 7. Equivalent schematic of a transformer including parasitic capacitance

2.2 The switching mechanism

Still another way of classifying resonant converters would include the LLC resonant half-
bridge in the family of "resonant-transition" converters. This nomenclature refers to the fact
that in this class of converters power switches are driven in such a way that a resonant tank
circuit is stimulated to create a zero-voltage condition for them to turn-on.
To understand how this can be achieved in the LLC half-bridge, it is instructive to consider
the circuits illustrated in Figure 8 where the switches Q1 and Q2 that generate the square
wave input voltage to the resonant tank are power MOSFETs. Their body diodes DQ1, DQ2
are pointed out because they play an important role. In circuit a), the drain-to-source
parasitic capacitances Coss1, Coss2 are pointed out as well. In fact, as far as voltage
changes of the node HB are concerned, the parasitic capacitances Cgd and Cds are
effectively in parallel, then Cgd+Cds=Coss has to be considered.
Additionally, other contributors to the parasitic capacitance of the node HB (e.g. that formed
between the case of the power MOSFETs and the heat sink, the intrawinding capacitance of
the resonant inductor, etc.) are lumped together in the capacitor CStray. Note that Coss1, like
Coss2, is connected between the node HB and a node having a fixed voltage (Vin for Coss1,
ground for Coss2). Then, as far as voltage changes of the node HB are concerned, Coss1 is
effectively connected in parallel to Coss2 and CStray. It is convenient to lump all of them
together in a single capacitor CHB from the node HB to ground, as shown in the circuit b):

Equation 4
C HB = C OSS1 + C OSS2 + C Stray

which we will refer to in the following discussion. Note also that Coss1 and Coss2 are non-
linear capacitors, i.e. their value is a function of the drain-to-source voltage. It is intended
that their time-related equivalent value will be considered (see Appendix A).

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AN2644 The LLC resonant half-bridge converter

Figure 8. Power MOSFET totem-pole network driving a resonant tank circuit in a

half-bridge converter

Q1 Q1
Coss1
DQ1 DQ1
Resonant

HB Driver
Resonant

HB Driver
Vin Node IR Vin IR
Node
HB Tank & HB Tank &
Q2 Load Q2 Load
Coss2
CStray CHB
DQ2 DQ2

a) b)

As previously stated, there is no overlap between the conduction of Q1 and Q2.

Additionally, a deadtime TD between the transitions from one state to the other of either
switch, where they both are open, is intentionally inserted. It is intended that when Q1 is
closed and Q2 is open, the voltage applied to the resonant tank circuit is positive. Similarly
we will define as negative the voltage applied to the resonant tank circuit when Q1 is open
and Q2 is closed. Consistently with two-port circuits sign convention, the input current to the
resonant tank, IR, will be positive if entering the circuit, negative otherwise.
Let us assume Q1 closed and Q2 open. It is then IR = I(Q1). Despite that the voltage applied
to the circuit is positive (VHB = Vin), IR can flow in either direction since we are in presence of
reactive elements. Let us suppose that IR is entering the tank circuit (positive current) in the
instant t0 when Q1 opens, and refer to the timing diagram of Figure 9.
The current through Q1 falls quickly and becomes zero at t = t1. Q2 is still open and IR must
keep on flowing almost unchanged because of the inductance of the resonant tank that acts
as a current flywheel. The electrical charge necessary to sustain IR will come initially from
CHB, initially charged at Vin, which will be now discharged. Provided IR(t1) is large enough,
the voltage of the node HB will then fall at a certain rate until t = t2, when its voltage
becomes negative and the body diode of Q2, DQ2, becomes forward biased, thus clamping
the voltage at a diode forward drop VF below ground. IR will go on flowing through DQ2 for
the remaining part of the deadtime TD until t = t3, when Q2 turns on and its RDS(on) shunts
DQ2. When this occurs, the voltage across Q2 is -VF, a value negligible as compared to the
input voltage Vin. In the end, this is what is called zero-voltage switching (ZVS): the turn-on
transition of Q2 is done with negligible dissipation due to voltage-current overlap and with
CHB already discharged, there will be no significant capacitive loss either. Note, however,
that there will be nonnegligible power dissipation associated to Q1's turn-off because there
will be some voltage-current overlap during the time interval t0 - t1.

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The LLC resonant half-bridge converter AN2644

Figure 9. Detail of Q1 ON-OFF and Q2 OFF-ON transitions with soft-switching for

Q2
Dead-time

t0 – t1 Q1 current fall time;

Q1 ON Q1 OFF Q1 OFF voltage-current overlap for Q1
Q2 OFF Q2 OFF Q2 ON
t0 – t2 Node HB transition time
Q2 is switched on with essentially t2 – t3 Q2’ body diode conduction time
VHB
Low turn-off losses zero drain-to-source voltage: ZVS!
Vc = Resonant capacitor voltage

VHB = Node HB voltage

Tank circuit’s current Magnetizing current equals

IR I(Q1) I(CHB) is positive tank circuit’s current
IR = Tank circuit’s current
I(Lp) = Lp (magnetizing) current
I(Q1) = MOSFET Q1 current
I(CHB) = CHB current
Q1’s current HB node’s parasitic capa-
falls to zero t0 t1 t2 t3 citance discharge current

There is an additional positive side effect in turning on Q2 with zero drain-to-source voltage.
It is the absence of the Miller effect, normally present in power MOSFETs at turn-on when
hard-switched. In fact, as the drain-to-source voltage is already zero when the gate is
supplied, the drain-to-gate capacitance Cgd cannot "steal" the charge provided to the gate.
The so-called "Miller plateau", the flat portion in the gate voltage waveform, as well as the
associated gate charge, is missing here and less driving energy is therefore required. Note
that this property provides a method to check if the converter is running with soft-switching
or not by looking at the gate waveform of Q2 (which is more convenient because it is source-
grounded), as shown in Figure 10 and 11.

Figure 10. Q2 gate voltage at turn-on: with Figure 11. Q2 gate voltage at turn-on: with
soft-switching hard-switching (no ZVS)

Current injection through

Cgd due to hard-switching

Miller effect

HB node is falling down

here; current due to Cgd

With similar reasoning it is possible to understand that the same ZVS mechanism occurs to
Q1 when it turns on if IR is flowing out of the resonant tank circuit (negative current).
In the end we can conclude that, if the tank current at the instant of half-bridge transitions
has the same sign as the impressed voltage, both switches will be "soft-switched" at turn-on,
i.e. turned on with zero voltage across them (ZVS). It is intuitive that this sign coincidence

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AN2644 The LLC resonant half-bridge converter

occurs if the tank current lags the impressed voltage (e.g. it is still positive while voltage has
already gone to zero), which is a condition typical of inductors. In other words, ZVS occurs if
the resonant tank input impedance is inductive. The frequency range where tank current
lags the impressed voltage is therefore called the "inductive region".
It is worth emphasizing the essential role of DQ1 and DQ2 in ensuring continuity to current
flow and clamping the voltage swing of the node HB at Vin+VF and -VF respectively (the LLC
resonant half-bridge belongs to the family of ZVS clamped-voltage topologies). Power
MOSFETs, with their inherent body diodes are therefore the best suited power switches to
be used in this converter topology. Other types of switches, such as BJT or IGBT, would
need the addition of external diodes.
Going back to the state when Q1 is closed and Q2 open, let us now assume that at the
instant t0 when Q1 opens, current is flowing out of the resonant tank towards the input
source, i.e. it is negative. This operation is shown in the timing diagrams of Figure 12.
With Q1 now open the current will go on flowing through DQ1 throughout the deadtime, and
will eventually be diverted through Q2 only when Q2 closes at t = t1, the end of the
deadtime. As far as Q1 is concerned, then, there will be no loss associated to turn-off
because the voltage across it does not change significantly (it is essentially the same
situation seen at turn-on when the converter works in the inductive region).
Q2, instead, will experience now a totally different situation. As DQ1 is conducting during
the deadtime, the voltage across Q2 at t = t1 equals Vin+VF so that there will be not only a
considerable voltage-current overlap but the energy of CHB will be dissipated inside its
RDS(on) as well. In this respect, it is a "hard-switching" condition identical to what normally
happens in PWM-controlled converters at turn-on. The associated power dissipation
½CHBVin2f may be considerably higher than that normally dissipated under "soft-switching"
conditions and this may easily lead to Q1 overheating, since heat sinking is not usually sized
to handle this abnormal condition.
In addition to that, at t = t1 the body diode of Q1, DQ1, is conducting current and its voltage
is abruptly reversed by the node HB being forced to ground by Q2. Hence, DQ1 will keep its
low impedance and there will be a condition equivalent to a shoot-through between Q1 and
Q2 until it recovers (at t = t2).
It is well-known the power MOSFET's body diodes do not have brilliant reverse recovery
characteristics. Hence DQ1 will undergo a reverse current spike large in amplitude (it can
be much larger than the forward current it was carrying at t=t1) and relatively long in duration
(in the hundred ns) that will go through Q2 as well. This spike, in fact, cannot flow through
the resonant tank because Ls does not allow for abrupt current changes.
This is a potentially destructive condition not only because of the associated power
dissipation that adds up to the others previously considered, but also due to the current and
voltage of DQ1 which are simultaneously high during part of its recovery. In fact, there will
be an extremely high dv/dt (many tens of V/ns!) experienced by Q1 as DQ1 recovers and
the voltage of the node HB goes to zero. This dv/dt may exceed Q1 rating and lead to an
immediate failure because of the second breakdown of the parasitic bipolar transistor
intrinsic in power MOSFET structure. Finally, it is also possible that Q1 is parasitically turned
on if the current injected through its Cgd and flowing through the gate driver's pull down,
which is holding the gate of Q1 low, is large enough to raise the gate voltage close to the
turn-on threshold (see the spike after turn-off in the graph of Figure 11). This would cause a
lethal shoot-through condition for the half-bridge leg.
An additional drawback of this operation is the large and energetic negative voltage spikes
induced by the recovery of DQ1 because of the unavoidable parasitic inductance of the PCB

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The LLC resonant half-bridge converter AN2644

subject to its di/dt, which may damage any control IC coupled to the half-bridge leg, not to
mention the big EMI generation.
Similarly, it is possible to show that the same series of adverse events will happen to Q1 and
Q2, with exchanged roles, when Q2 is turned off if IR is flowing into the resonant tank circuit
(positive current).
The obvious conclusion is that, if the tank current and the impressed voltage at the instant of
half-bridge transitions have opposite signs, both switches will be hard-switched and the
reverse recovery of their body diodes will be invoked, with all the resulting negative effects. It
is intuitive that this sign opposition occurs if the tank current leads the impressed voltage,
which is typical of capacitors and then occurs if the resonant tank input impedance is
capacitive. This kind of operation is often termed "capacitive mode" and the frequency range
where tank current leads the impressed voltage is called the "capacitive region".

Figure 12. Q1 ON-OFF and Q2 OFF-ON transitions with hard switching for Q2 and
recovery for DQ1
Dead-time

t0 – t1 Q2’ body diode conduction time;

Q1 ON Q1 OFF Q1 OFF coinciding with dead-time
Q2 OFF Q2 OFF Q2 ON
t1 – t2 Q1’s body diode recovery time

Q1 has soft turn-off Q2 is hard-switched

VHB

Vc = Resonant capacitor voltage

Resonant capacitor voltage
Node HB voltage
High dv/dt VHB = Node HB voltage

Q1’s body diode

IR I(Q1) I(Q2) is recovered
IR = Tank circuit’s current
I(Lp) = Lp (magnetizing) current
I(Q1) = MOSFET Q1 current
Tank circuit’s current Current is circulating
is negative t0 t1 t2 through Q1’s body diode

Then, the converter must be operated in the region where the input impedance is inductive
(the inductive region), that is, for frequencies f > fR1 or in the range fR2 < f < fR1 provided the
load resistance R is such that R> Rcrit. This is a necessary condition in order for Q1 and Q2
to achieve ZVS, which is evidently a crucial point for the good operation of the LLC resonant
half-bridge.
To summarize, ZVS brings the following benefits:
1. low switching losses: either high efficiency can be achieved if the half-bridge is
operated at a not too high switching frequency (for example < 100 kHz) or high
switching frequency operation is possible with a still acceptably high efficiency
(definitely out of reach with a hard-switched converter);
2. reduction of the energy needed to drive Q1 and Q2, thanks to the absence of Miller
effect at turn-on. Not only is turn-on speed unimportant because there is no voltage-
current overlap but also gate charge is reduced, then a small source capability is
required from the gate drivers.
3. low noise and EMI generation, which minimizes filtering requirements and makes this
converter extremely attractive in noise-sensitive applications.

4. all of the above-mentioned adverse effects of capacitive mode, which not only impair
efficiency but also jeopardize the converter, are prevented.

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AN2644 The LLC resonant half-bridge converter

Note, however, that working in the inductive region is not a sufficient condition in order for
ZVS to occur.
In the above discussion, it has been said that the voltage of the node HB could swing from
Vin to zero "provided IR is large enough". Of course the same holds if we consider node HB's
swing from zero up to Vin. What actually happens when Q1 turns off with positive IR current
is that the associated inductive energy level of the resonant tank circuit is maintained at the
expense of the energy contained in the capacitance CHB. If the inductive energy (∝ IR2) is
greater than that owned by CHB (∝ Vin2) CHB will be completely depleted and the voltage of
the node HB will be able to reach -VF, injecting DQ2 and allowing Q2 to turn-on with
essentially zero drain-to-source voltage. Similarly, when Q2 turns off with negative current,
part or all of the associated inductive energy will be transferred to CHB. If the available
inductive energy is greater than that needed to charge CHB up to Vin+VF, the node HB will be
allowed to swing all the way up until DQ1 is injected, thus clamping the voltage, and Q1 will
be able to turn-on with essentially zero drain-to-source voltage.
Seen from a different perspective, the inductive part of the tank circuit resonates with CHB,
and this is the origin of the term "resonant transition" used for designating resonant
converters having this property. This "parasitic" tank circuit active during transitions is
formed by CHB with the series inductance Ls if during the half-bridge transition there is
current circulating on the secondary side (so that Lp is shorted out) or with the total
inductance Ls + Lp if there is no current conduction on the secondary side.

Figure 13. Bridge leg transitions in the neighborhood of inductive-capacitive

regions boundary

Q1 ON Q1 OFF Q1 OFF Q1 ON Q1 OFF Q1 OFF

Q2 OFF Q2 OFF Q2 ON Q2 OFF Q2 OFF Q2 ON

VHB Q1’s body diode conduction VHB Q1’s body diode conduction

Q2 is hard switched VHB = Node HB Q2 is hard switched

Q1’s body diode is recovered voltage Q1’s body diode is recovered

IR I(Lp) IR = 0 IR I(Lp) IR = 0
IR = Tank circuit’s
current
I(Lp) = Lp (magnetizing)
current

a) b)

Q1 ON Q1 OFF Q1 OFF Q1 ON Q1 OFF Q1 OFF

Q2 OFF Q2 OFF Q2 ON Q2 OFF Q2 OFF Q2 ON

VHB VHB

Q2 is hard switched VHB = Node HB

voltage Q2 is soft switched

IR I(Lp) IR = 0 IR I(Lp) IR = 0
IR = Tank circuit’s
current
I(Lp) = Lp (magnetizing)
current

c) d)

The above mentioned energy balance considerations, however, are not still sufficient to
guarantee ZVS under all operating conditions. There is an additional element that needs to
be considered, the duration of the deadtime TD.
The first obvious consideration is that the duration of the deadtime represents an upper limit
to the time the node HB takes to swing from one rail to the other: in order for the mosfet that
is about to turn on to achieve ZVS (i.e. to be turned on with zero drain-to-source voltage),
the transition has to be completed within TD as depicted in Figure 9. However, the way the

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The LLC resonant half-bridge converter AN2644

deadtime and ZVS are related is actually more complex and depends on converter's
operating conditions.
It is instructive to see this in Figure 13, which shows typical node HB waveforms occurring
when working in the inductive region but too close to the capacitive region, so that ZVS is
not achieved. They refer to the Q1 →OFF, Q2 → ON transition; those related to the opposite
transition are obviously turned upside down.
● Case a) is very close to the boundary between inductive and capacitive regions. Tank
current reverses just after Q1 is switched off, a portion of node HB ringing appears as a
small "dip", then the tank current becomes negative enough to let the body diode of Q1
start conducting. When Q2 turns on there are capacitive losses and the recovery of the
Q1's body diode with all the related issues.
● Case b) is slightly more in the inductive region but still IR crosses zero within the
deadtime. The node HB ringing becomes larger and the body diode of Q1 still conducts
for a short time and its recovery is invoked as Q2 turns on.
● Case c) Is even more in the inductive region but still not sufficiently away from the
capacitive-inductive boundary. The ringing of the node HB is large enough to reach
zero but IR reverses within the deadtime and the voltage goes up again. At the end of
the deadtime the voltage does not reach Vin, hence the body diode of Q1 does not
conduct and Q2, when turned on, will experience only capacitive losses.
● Case d) Is further in the inductive region and IR crosses zero nearly at the end of the
deadtime. Q2 is now almost soft-switched with no losses. This can be considered as
the boundary of the operating region where ZVS can be achieved with the given
duration of TD.
Note that the resonant tank's current during node HB ringing is lower than the one flowing
through Lp. This means that their difference is flowing into the transformer and,
consequently, that one of the secondary half-windings is conducting. Therefore, CHB is
resonating with Ls only.
This analysis shows that there is a "border belt" in the inductive region, close to the
boundary with the capacitive region (fR2 < f < fR1, R = Rcrit) and that as converter's operation
is moved away from the capacitive-inductive boundary and pushed more deeply in the
inductive region there is a progressive behavior change from hard-switching to soft-
switching. In the cases a and b the inductive energy in the resonant tank is too small to let
the node HB even swing "rail-to-rail"; moving away from the boundary, as shown in case c,
the energy is higher and allows a rail-to-rail swing, but it is not large enough to keep the
node HB "hooked" to the rail throughout the deadtime TD. If the converter is operated in this
border belt, Q1 and Q2 will be hard-switched at turn-on and, in cases such as case a and
case b, the body diode of the just turned off power MOSFET is injected and then recovered
as the other power MOSFET turns on.
Case b and, especially, case c highlight that it is possible to look at the deadtime TD also
from another standpoint: looking at those waveforms, one might conclude that the current IR
at the beginning of the deadtime is too low or, conversely, that the deadtime is too long. In
case c, for example, if the dead-time had been approximately half the value actually shown,
Q2 would have been soft-switched at turn-on. Of course, the more appropriate interpretation
depends on whether TD is fixed or not.
These cases are related to heavy load conditions.
Figure 14 shows a case typical of no-load conditions, where ZVS is not achieved because of
a too slow transition of the node HB so that it does not swing completely within the deadtime
TD. In this case the situation seems less stressful than operating in the capacitive region.

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AN2644 The LLC resonant half-bridge converter

There is no body diode conduction and, consequently, no recovery. Q1 will be almost soft-
switched at turn-off, while Q2 will have capacitive losses at turn-on. It is true that the turn-on
voltage is lower than Vin, thus the associated energy of CHB is lower, but at no-load the
operating frequency is usually considerably higher than in the capacitive region, then these
power losses may easily overheat Q1 and Q2. Finally, note in Figure 14 that I(Lp) is exactly
superimposed on IR, then the secondary side of the transformer is open and CHB is
resonating with the total inductance Ls+Lp.

Figure 14. Bridge leg transitions under no-load conditions

Q1 ON Q1 OFF Q1 OFF
Q2 OFF Q2 OFF Q2 ON

VHB

Q2 is hard switched VHB = Node HB voltage

IR I(Lp)

IR = Tank circuit’s current

I(Lp) = Lp (magnetizing) current

From what we have seen we can conclude that the conditions in order for the half-bridge
switches to achieve ZVS are:
1. Under heavy load conditions, as one switch turns off, the tank current must have the
same sign as the impressed voltage and be large enough so that both the rail-to-rail
transition of the node HB is completed and the current itself does not reverse before the
end of the deadtime, when the other switch turns on.
2. With no-load, the tank current at the moment one switch turns off (which has definitely
the same sign as the impressed voltage) must be large enough to complete the node
HB transition within the deadtime, before the other switch turns on.
Both conditions can be translated into specifying a minimum current value IRmin that needs
to be switched when either power MOSFET turns off. In general, different IRmin values are
needed to ensure ZVS at heavy load and at no-load. One can simply pick the greater one to
ensure ZVS under any operating condition by design. On the other hand, this minimum
required amount of current is to the detriment of efficiency.
At light or no-load a significant current must be kept circulating in the tank circuit, just to
maintain ZVS, in spite of the current delivered to the load that is close to zero or zero. Using
ac-analysis terminology, a certain amount of reactive energy is required even with no active
energy.
Finally, also at heavy load the value of IRmin to be specified is the result of a trade-off. In fact,
its value is directly related to the turn-off losses of both Q1 and Q2. The higher the switched
current is, the larger the switching loss due to voltage-current overlap will be.
The discussion on the switching mechanism has been focused on the primary-side
switches, and the conditions in order for them to achieve soft-switching (ZVS at turn-on,
precisely) have been found. One important merit of the LLC resonant converter is that also
the rectifiers on the secondary side are soft-switched. They feature zero-current switching
(ZCS) at both turn-on and turn-off. In fact, at turn-on the initial current is always zero and
ramps up with a relatively low di/dt, so that forward recovery does not come into play. At
turn-off they become reverse biased when their forward current is already zero, so that their

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The LLC resonant half-bridge converter AN2644

reverse recovery is not invoked. This topic will be addressed in Section 2.3, where it will be
shown that this property is inherent in the topology, hence it occurs regardless of converter's
design or operating conditions.

2.3 Fundamental operating modes

The LLC resonant half-bridge converter features a considerable number of different
operating modes, which stem from its multiresonant nature. Essentially, the term
"multiresonant" means that the configuration of the resonant tank may change within a
single switching cycle. We have seen that there are two resonant frequencies, one (the
higher) associated to either of the secondary rectifiers conducting, the lower one associated
to both rectifiers non-conducting. Then, depending on the input-to-output voltage ratio, the
output load and the characteristics of the resonant tank circuit, the secondary rectifiers can
be always conducting (with the exception of a single point in time), which is referred to as
CCM (Continuous Conduction Mode) like in PWM converters, or there can be finite time
intervals during which neither of the secondary rectifiers is conducting. This will obviously be
called a DCM (Discontinuous Conduction Mode) operating mode.
Different kinds of CCM and DCM operating modes exist, although not all of them can be
seen in a given converter, some are not even recommended, like those associated with
capacitive mode operation. However, in all CCM modes the parallel inductance Lp is always
shunted by the load resistance reflected back to the primary side, so that it never
participates in resonance, rather it acts as an additional load to the remaining LC resonant
circuit. Similarly, in all DCM modes, there will be some finite time intervals where Lp, being
no longer shunted from the secondary side, becomes part of resonance.
In the following we will consider four fundamental operating modes and use the
nomenclature defined in [3]:
1. Operation at resonance, when the converter works exactly at f = fR1;
2. Above-resonance operation, when the converter works at a frequency f > fR1. Moving
away from resonance, we will consider three sub-modes:
a) CCMA operation at heavy load;
b) DCMA operation at medium load;
c) DCMAB operation at light load;
3. Below-resonance operation, when the converter works at a frequency fR2 < f < fR1 with
a load resistor R > Rcrit. Moving away from resonance, we will consider two sub-modes:
a) DCMAB operation at medium-light load;
b) DCMB operation at heavy load;
4. Below-resonance operation, when the converter works at a frequency fR2 < f < fR1 with
a load resistor R < Rcrit (capacitive mode), corresponding to the CCMB operating mode
defined in [3];
In addition, two extreme operating conditions will be considered:
1. No-load operation (cutoff)
2. Output short-circuit operation
It is interesting to point out that, unlike PWM converters where DCM operation is invariably
associated to light load operation and CCM to heavy load operation, in the LLC resonant
converter this combination does not hold.

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AN2644 The LLC resonant half-bridge converter

To illustrate the above-mentioned operating modes we will refer to the reference converter
shown in Figure 15. The discussion will start from the inspection of the main waveforms in a
switching cycle, highlighting each subinterval where the circuit assumes a topological state
and deducing the properties of the converter when operated in that mode from those
waveforms. Half-bridge leg transitions are considered instantaneous. Their features have
been already discussed.

Figure 15. Reference LLC converter for the analysis of the fundamental operating
modes

Q1
I(Q1)
360 to 420 Coss1
Vdc 100 pF
Ls 24 Vdc
IR Vc 200 uH D1 300W
Driver 8.33:1:1
Vin + HB
Cr
CTRL 22 nF I(Lp)
I(D1)
Cout
Coss2 Vout
Lp
100 pF 500 uH I(D2)
I(Q2) Q2

Isolated
feedback

2.3.1 Operation at resonance (f = fR1)

In this operating mode it is possible to distinguish six fundamental time subintervals within a
switching cycle, which are illustrated in Figure 16.
The first subinterval and, then, the instant t0 can be chosen quite arbitrarily. We fix t0 as the
instant when, with Q1 conducting and Q2 open, the tank current IR has a positive-going
zero-crossing.
a) t0 → t1. Q1 is ON and Q2 is OFF. This is the "energy taking" phase, when current
flows from the input source to the tank circuit, so that energy is positive and both
refills the resonant tank and supplies the load. The operating point of Q1 is in the
first quadrant (current is flowing from drain to source). D2 is reverse-biased with a
voltage -2·Vout (it is actually larger because of the contribution from the secondary
leakage inductance LL2). D1 is conducting, so Lp is shorted by the output load
reflected back to the primary side and the voltage across it is fixed at a·Vout. Lp,
then, is not participating in resonance and Cr is resonating with Ls only. IR is a
portion of a sinusoid having a frequency f = fR1. During this phase, which ends
when Q1 is switched off at t=t1, IR reaches its maximum value, after that it starts
decaying. Note that at t=t1 IR=I(Lp) and then I(D1)=0.
b) t1 → t2. This is the deadtime during which both Q1 and Q2 are OFF. At t=t1
I(Q1)=I(Lp)=IR is greater than zero and provides the energy to let the node HB
swing from Vin to 0, so that the body diode of Q2, DQ2, is injected. This allows IR
to flow. The voltage across Lp reverses to -a·Vout and the slope of its current
changes sign. D2 starts conducting while D1 is reverse biased with a negative
voltage approximately equal to 2·Vout (plus the contribution from LL2, here not
shown). This phase ends when Q2 is switched on at t=t2.
c) t2 → t3. Q1 is OFF and Q2 is ON. At t=t2 IR is diverted from DQ2 to the RDS(on) of
Q2, so that no significant energy is lost during the turn-on transient. Note that now

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The LLC resonant half-bridge converter AN2644

the operating point of Q2 is in the third quadrant, current is flowing from the source
to drain. D2 keeps on conducting and the voltage across Lp is -a·Vout, so that Lp
is not participating in resonance and Cr is resonating with Ls only. IR is a portion
of a sinusoid having a frequency f = fR1. This phase ends when IR=0 at t=t3.
d) t3 → t4. Q1 is OFF and Q2 is ON. Tank circuit current, which is zero at t=t3
becomes negative. D1 is non-conducting and its reverse voltage is approximately
2·Vout (plus the contribution from LL2, here not shown). Lp's current has a
negative slope, so the voltage across Lp must be negative. Since the diode D2 is
conducting, this voltage will be equal to -a·Vout. Lp, then, is not participating in
resonance, Cr is resonating with Ls only and IR is a portion of a sinusoid having a
frequency f = fR1. During this phase, which ends when Q2 is switched off at t=t4,
IR reaches its minimum value, after that it starts increasing. Note that at t=t4
IR=I(Lp) and then I(D2)=0.
e) t4 → t5. This is the deadtime during which both Q1 and Q2 are OFF. At t=t4
I(Q2)=-I(Lp)=-IR is greater than zero and provides the energy to let the node HB
swing from 0 to Vin, so that the body diode of Q1, DQ1, is injected. This allows IR
to flow back to the input source. The voltage across Lp reverses to a Vout and its
current slope changes sign. D1 starts conducting while D2 is reverse biased with
a negative voltage approximately equal to 2·Vout (plus the contribution from LL2,
here not shown). This phase ends when Q1 is switched on at t=t5.

Figure 16. Operation at resonance (f = fR1): main waveforms

t0 t1 t2 t3 t4 t5 t6

Q1 ON Q1 OFF Q1 ON
Q2 OFF Q2 ON Q2 OFF

HVG= Q1 gate VHB = Node HB voltage IR = Tank circuit’s current I(Q1) = Q1 current V(D1) = D1 anode voltage I(D1) = D1 current

LVG = Q2 gate Vc = Resonant capacitor voltage I(Lp) = Lp (magnetizing) current I(Q2) = Q2 current V(D2) = D2 anode voltage I(D2) = D2 current

f) t5 → t6. Q1 is ON and Q2 is OFF. At t=t5 IR is diverted from DQ1 to the RDS(on) of

Q1, so that no significant energy is lost during the turn-on transient. Note that now
the operating point of Q1 is in the third quadrant, current is flowing from the source
to drain. This phase, along with the preceding one can be referred to as the
"external energy recirculation phase": current is negative (coming out of the input
terminal) despite that the impressed voltage is positive so that the input energy is

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AN2644 The LLC resonant half-bridge converter

negative, i.e. it is returned to the input source. D1 keeps on conducting and the
voltage across Lp is a·Vout, so that Lp is not participating in resonance and Cr is
resonating with Ls only. IR is a portion of a sinusoid having a frequency f = fR1.
This phase ends when IR=0 at t=t6 and another switching cycle starts.

Remarks
1. Parallel inductor Lp never resonates and its current is essentially triangular (note: the
real magnetizing current is sinusoidal and cannot be seen on the oscilloscope). The
LLC converter, then, can be regarded as a series LC resonant half-bridge (composed
by Ls and Cr) that supplies a reactive RL load (composed by Lp and Rac, the equivalent
ac resistor loading the converter, as defined in [2] and reflected back to the primary
side). This standpoint provides considerable insight into the operation of the converter,
as shown in some of the following remarks.
2. In a resistively loaded series LC tank operating at resonance, the impressed voltage
and the tank current are exactly in-phase, hence the switched current is zero and,
thereby, ZVS cannot be achieved. The effect of adding an inductor (Lp) in parallel to
the resistive load is to provide tank current with the phase shift (lagging) necessary to
switch a current greater than zero, so that ZVS becomes now possible at resonance.
As shown in the diagrams of Figure 16, the tank circuit current lags the impressed
voltage by an angle ϕ equal to:

Equation 5
t6 – t4
ϕ = 2π --------------
t6 – t0
so that they have the same sign at half-bridge leg transitions. Furthermore, the
switched currents IR(t1) and IR(t4) are large enough to complete the HB node swing well
within the deadtimes (t1, t2) and (t4, t5) respectively. It is not difficult to recognize that
the angle ϕ is the phase of the input impedance of the loaded resonant tank evaluated
at f=fR1. Additionally, since the impedance of a series LC tank operating at resonance
is zero, it is possible to state that the input impedance of the LLC resonant tank at
resonance equals the impedance of the RL load.
3. Generally speaking, in a series LC tank operating at resonance, the voltage drop
across L is equal in module and opposite in sign to the drop across C at all times (this
is why its impedance is zero). In our specific case the drop across the series Cr-Ls will
be zero, so that it is possible to write the following voltage balance equations:

Equation 6
V in
V in – -------- = a ⋅ V out Q1 ON, Q2 OFF
2
V in
– -------- = – a ⋅ V out Q1 OFF, Q2 ON
2
both of them resulting in the following relationship:

Equation 7
V in
- = a ⋅ V out
-------
2
This is a fundamental property of the LLC resonant half-bridge: operating at f=fR1
implies that input and output voltages fulfill (1) and, vice versa, if input and output
voltages meet Equation 7 the converter is operating at f=fR1. Then, the fact that the
converter operates at resonance or not, for a given output voltage Vout and a given turn

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The LLC resonant half-bridge converter AN2644

ratio a (n), depends only on the input voltage, not on the load and on the parameters of
the resonant tank. From the design point of view, since Vin and Vout are specified, one
can decide the input voltage where to operate at resonance by choosing the turns ratio
a. Vin/2=a·Vout considered as the 1:1 conversion ratio for the LLC resonant half-bridge.
4. The logical consequence of LLC converter's ability to operate at resonance
independently of the output load is that the LLC resonant half-bridge can deliver any
power if operated at resonance. This can be seen also in another way. As the
impedance of the series Cr-Ls is zero, the RL load Rac//Lp "sees" the impressed
voltage directly or, in other words, it is supplied by an ideal voltage source. This is a
"singularity" in LLC converter's operation, sometimes referred to as the "load-
independent" point, where the usual energy vs. frequency relationship does not hold.
Actually, the inevitable voltage drops across the resistive elements of the real-world
circuit (such as power MOSFETs' RDS(on), winding resistance, secondary rectifier's
drop, etc.) cause a slight dependence of the frequency on the load. Note that this is a
situation analog to that of CCM-operated PWM converters, where duty cycle is ideally
independent of the load, in reality slightly dependent because of losses.
5. Energy is taken from the input source only from t0 to t1, the "energy taking" phase, then
for less than half the switching period, while from t1 to t4 energy recirculates internally
to allow energy flow to the load while Q1 is not conducting. This low "duty cycle" of the
input current can be a limiting factor in terms of power handling capability, especially if
the input voltage is low. This consideration suggests the use of the half-bridge topology
in high input voltage applications (e.g. with a PFC front-end, which provides a
400 V input rail). The natural improvement to this limitation is the full-bridge topology,
where phase d) becomes active as well.
6. Tank circuit current lag ϕ originates the external energy recirculation phase from t4 to t6
during which energy flow is negative (impressed voltage and input current have
opposite signs). This energy subtracts to that drawn from the input during the energy
taking phase a), hence reducing the net energy flow from the input source to the load
each cycle. This energy can be regarded as reactive energy and cos ϕ as the input
power factor. Making ϕ as small as possible (i.e. increasing Lp) would shorten the
duration of the external energy recirculation phase and reduce the amount of reactive
energy, thus improving the energy transfer process. This, however, would also reduce
IR(t1) and IR(t4), hence ϕ can be reduced as long as ZVS is maintained.
7. Recalling that the current switched at turn-off by Q1, IR(t1) and by Q2, IR(t4) determine
their switching losses, it is straightforward that keeping ϕ to the minimum value that
ensures ZVS of Q1 and Q2 provides an optimum design. Of course, component
tolerance must be adequately accounted for, thus ϕ must be larger than the minimum
required and the typical operation will be suboptimal.
8. The secondary rectifiers D1 and D2 start conducting as Q2 and Q1 turn-off
respectively. The initial current is zero and also its di/dt is low, thus they have a soft
turn-on. D1 and D2 cease to conduct exactly when Q1 and Q2 turn-off, respectively.
These are also the moments when the voltages across D1 and D2 reverse. As a result,
neither D1 nor D2 experience a voltage reversal while conducting a forward current.
Reverse recovery, with all its adverse effects, does not occur. Note that, in this respect,
this is a situation identical to that of a PWM converter operating on the boundary
between CCM and DCM.

2.3.2 Operation above resonance (f > fR1)

In this operating mode the converter exhibits its usual frequency vs. load characteristic. We
will consider three submodes where, in a closed-loop regulated system, CCM operation

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AN2644 The LLC resonant half-bridge converter

progressively turns into DCM operation as the output load is reduced and frequency is
moved away from resonance.

CCMA operation at heavy load

Also in this case it is possible to identify six fundamentals subintervals. The relevant
waveforms are illustrated in the timing diagram of Figure 17. Again, t0 is the instant when,
with Q1 conducting and Q2 open, the tank current IR has a positive-going zero-crossing.
a) t0 → t1. Q1 is ON and Q2 is OFF. This is the "energy taking" phase. It is identical
to the corresponding phase seen in the operation at resonance with the only
difference that at the end of this phase, at t=t1, it is still IR > I(Lp) and then I(D1)>0.
b) t1 → t2. This is the deadtime during which both Q1 and Q2 are OFF. At t=t1 IR is
greater than zero and provides the energy to let the node HB swing from Vin to 0,
so that the body diode of Q2, DQ2, is injected. This allows IR to flow; IR slope
changes to a higher negative value, so that it quickly approaches I(Lp), which is
still increasing with the same slope. D1 conducts until IR equals I(Lp), and then
becomes reverse biased, with a negative voltage equal to 2·Vout (plus the
contribution from LL2, here not shown), I(Lp) slope changes sign and D2 starts
conducting. This phase ends when Q2 is switched on at t=t2. Note that the time
Tz needed for IR to hit I(Lp) is related to their values at t=t1 and their slopes after
t=t1 and not to the duration of the deadtime TD. Here it is Tz = TD just by chance.

Figure 17. Operation above resonance (f > fR1): main waveforms in CCMA operation
at heavy load
t0 t1 t2 t3 t4 t5 t6

Q1 ON Q1 OFF Q1 ON
Q2 OFF Q2 ON Q2 OFF

HVG= Q1 gate VHB = Node HB voltage IR = Tank circuit’s current I(Q1) = Q1 current V(D1) = D1 anode voltage I(D1) = D1 current

LVG = Q2 gate Vc = Resonant capacitor voltage I(Lp) = Lp (magnetizing) current I(Q2) = Q2 current V(D2) = D2 anode voltage I(D2) = D2 current

c) t2 → t3. Q1 is OFF and Q2 is ON. At t=t2 IR is diverted from DQ2 to the RDS(on) of
Q2, so that no significant energy is lost during the turn-on transient. This phase,
which ends when IR=0 at t=t3, is identical to the (t2, t3) phase of the operation at
resonance.

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The LLC resonant half-bridge converter AN2644

d) t3 → t4. Q1 is OFF and Q2 is ON. It is identical to the phase (t3, t4) seen in the
operation at resonance with the only difference that at the end of this phase, at
t=t4, it is still IR < I(Lp) and then I(D2)>0.
e) t4 → t5. This is the deadtime during which both Q1 and Q2 are OFF. At t=t4 IR is
(in absolute value) greater than zero and provides the energy to let the node HB
swing from 0 to Vin, so that the body diode of Q1, DQ1, is injected. This allows IR
to flow back to the input source. IR changes to a higher slope, so that it quickly
approaches I(Lp), which is still decreasing with the same slope. D2 conducts until
IR equals I(Lp), after that it becomes reverse biased, with a negative voltage
approximately equal to 2·Vout (plus the contribution from LL2, here not shown),
I(Lp) slope changes sign and D1 starts conducting. This phase ends when Q1 is
switched on at t=t5. Again, the time Tz needed for IR to hit I(Lp) is only by chance
equal to TD as shown.
f) t5 → t6. Q1 is ON and Q2 is OFF. At t=t5 IR is diverted from DQ1 to the RDS(on) of
Q1, so that no significant energy is lost during the turn-on transient. This phase,
which ends when IR=0 at t=t6, is identical to the (t5, t6) phase of the operation at
resonance.

Remarks
1. In this "above-resonance" CCM submode the parallel inductor Lp never resonates and
the LLC converter can be regarded as a series LC resonant half-bridge supplying a
reactive RL load.
2. As shown in the diagrams of Figure 17, the tank circuit current lags the impressed
voltage by an angle ϕ equal to:

Equation 8
t6 – t4
ϕ = 2π --------------
t6 – t0
so that they have the same sign at half-bridge leg transitions. Furthermore, the
switched currents IR(t1) and IR(t4) are large enough to complete the HB node swing well
within the deadtimes (t1, t2) and (t4, t5) respectively. Still ϕ is the phase of the input
impedance of the loaded resonant tank evaluated at f=fR1, but now since the
impedance of the series LC tank is no longer zero, it is different from the impedance of
the RL load.
3. In the series Cr-Ls tank circuit operating above resonance the voltage drop across it is
positive (the inductive reactance is larger in module than the capacitive reactance), i.e.
the plus sign is located on the side of the node HB. The obvious conclusion is that:

Equation 9
V in
a ⋅ V out < --------
2
Then, when operating above resonance, for a given input voltage the LLC resonant
half-bridge will provide an output voltage lower than that available at resonance and
vice versa, with a given output voltage the LLC resonant half-bridge will operate above
resonance with an input voltage greater than 2·n·Vout. In this case the conversion ratio,
intended as previously mentioned is < 1, then the LLC is said to have a "step-down" or
"buck" characteristic when operating above resonance.
4. When operating above resonance, the Thevenin-equivalent schematic of the LLC
resonant tank as seen by the load has finite impedance (no more zero as when
operating at resonance). When the load current increases, for a given frequency (open-

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AN2644 The LLC resonant half-bridge converter

loop operation) the voltage conversion ratio diminishes. For a given Vout (closed-loop
operation) operating frequency needs to get back closer to resonance.
5. The secondary rectifiers D1 and D2 start conducting as Q1 and Q2 turn-on
respectively. The initial current is zero and also its di/dt is low, thus they have a soft
turn-on. D1 and D2 cease to conduct when tank circuit's current IR equals Lp's current
I(Lp). The transformer's secondary current is a·[IR-I(Lp)], then the equality IR = I(Lp)
means that the secondary rectifiers current is zero as well. Unlike when operating at
resonance, this does not happen synchronously with the half-bridge leg transitions
(IR < I(Lp) at t=t1 and IR > I(Lp) at t=t4). However as the leg transition occurs IR and
I(Lp) are "forced" to become equal, then the current of the conducting diode goes to
zero. The physical reason for that is the presence of Ls. When there is a transition of
the half-bridge leg the resulting voltage change is not immediately directly impressed
on the transformer (C can be considered as a short circuit during transitions, i.e. the
voltage across it can be considered constant) but falls across Ls that acts as a "shock
absorber". This leaves I(Lp) unchanged but pushes IR towards I(Lp), forcing a rate of
change that is approximately:

Equation 10
⎧ Vc + a ⋅ V out ⎫ t ∈(t , t )
⎪ – -------------------------------- - ⎪ 1 2
dI R ⎪ Ls ⎪
-------- ≈ ⎨
dt ⎪ V in – Vc + a ⋅ V out ⎬⎪ t ∈(t , t )
4 5
⎪ ----------------------------------------------
Ls
-⎪
⎩ ⎭
Only when IR equals I(Lp) and no current is flowing through the secondary rectifier
previously conducting can the voltage across the primary winding of the transformer
reverse and hence also the voltage across the secondary rectifiers. In the end, also in
this case they are reverse-biased only when their current has gone to zero, thus
ensuring ZCS.

Figure 18. Operation above resonance (f > fR1): main waveforms in DCMA operation
at medium load
t0 t1 t2 t3 t4 t5 t6 t7 t8

Q1 ON Q1 OFF Q1 ON
Q2 OFF Q2 ON Q2 OFF

HVG= Q1 gate VHB = Node HB voltage IR = Tank circuit’s current I(Q1) = Q1 current V(D1) = D1 anode voltage I(D1) = D1 current

LVG = Q2 gate Vc = Resonant capacitor voltage I(Lp) = Lp (magnetizing) current I(Q2) = Q2 current V(D2) = D2 anode voltage I(D2) = D2 current

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The LLC resonant half-bridge converter AN2644

DCMA at medium load

In this "above-resonance" DCM submode it is possible to identify eight fundamentals
subintervals. The relevant waveforms are illustrated in the timing diagram of Figure 18.
Two new subintervals, namely (t2, t3) and (t6, t7), appear just after the deadtimes of the half-
bridge leg transitions (t1, t2), (t5, t6), respectively. The other six phases are exactly identical
to those of the CCM above-resonance mode.
a) t2 → t3. Q1 is OFF and Q2 is ON. At t=t2 IR is diverted from DQ2 to the RDS(on) of
Q2, so that no significant energy is lost during the turn-on transient. Note that the
operating point of Q2 is in the third quadrant, current is flowing from the source to
drain. D1 is nonconducting but the voltage across the secondary windings is still
too low to let D2 conduct, then still IR = I(Lp) is a portion of a sinusoid having a
frequency f = fR2. This phase ends when D2 starts conducting at t=t3.
b) t6 → t7. Q1 is ON and Q2 is OFF. At t=t6 IR is diverted from DQ1 to the RDS(on) of
Q1, so that no significant energy is lost during the turn-on transient. Note that the
operating point of Q1 is in the third quadrant, current is flowing from the source to
drain. D2 is nonconducting but the voltage across the secondary windings is still
too low to let D1 conduct, then still IR = I(Lp) is a portion of a sinusoid having a
frequency f = fR2. This phase ends when D1 starts conducting at t=t7.

Remarks
1. In this "above-resonance" DCM submode the multiresonant nature of the LLC
converter shows up. In a switching cycle there are two time intervals just after bridge-
leg transitions during which no current is flowing on the secondary side (hence this is
DCM operation), then the entire transformer's primary inductance Ls+Lp resonates and
the second resonance frequency fR2 appears. At the transitions of the half-bridge leg
the resonant current IR is still slightly greater than I(Lp) in absolute value, so it takes a
very small portion of the deadtimes for the two currents to equal each other. Then, the
first one starts as IR equals I(Lp) slightly after t1 and ends at t= t3. The second one
starts slightly after t5 and ends at t= t7.
2. As shown in the diagrams of Figure 18, the tank circuit current is still lagging the
impressed voltage, so that they have the same sign at half-bridge leg transitions.
Furthermore, the switched currents IR(t1) and IR(t5) are large enough to complete the
HB node swing well within the deadtimes (t1, t2) and (t5, t6) respectively. However, as
compared to CCM mode, the duration of the energy taking phase (t0, t1) is shorter, the
external recirculation phase is longer and the displacement angle ϕ:

Equation 11
t8 – t6
ϕ = 2π --------------
t8 – t0
gets close to π/2. Using ac terminology, the active energy is lower and the reactive
energy is higher.
3. The secondary rectifiers D1 and D2 start conducting during the conduction period of
Q1 and Q2, respectively. Both the initial current and also its di/dt are zero, thus they
have a soft turn-on. D1 and D2 cease to conduct when tank circuit's current IR equals
Lp's current I(Lp). In this case this is almost synchronous with either switch turn-off.
Again, only when IR equals I(Lp) and no current is flowing through the secondary
rectifier previously conducting can the voltage across the primary winding of the
transformer reverse and hence also the voltage across the secondary rectifiers. In the

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AN2644 The LLC resonant half-bridge converter

end, also in this case they are reverse-biased only when their current has gone to zero,
thus ensuring ZCS.
4. Essentially, the reason why D2 does not conduct during (t2, t3) and D1 does not during
(t6, t7) is that the voltage across the transformer (given by Vin - Vc) is not large enough
so that the voltage developed across Lp (given by the inductive divider ratio Lp/(Ls+Lp))
and reflected to the secondary side can forward-bias D2 or D1. In formulae, this is
expressed as:

Equation 12
Lp
( V in ( t ) – Vc ( t ) ) -------------------- ≤ a ⋅ V out
Ls + Lp

DCMAB at light load

In this "above-resonance" DCM sub-mode it is possible to identify ten fundamental
subintervals. The relevant waveforms are illustrated in the timing diagram of Figure 19.
Two more new subintervals, namely (t1, t2), (t6, t7) appear just before the deadtimes of the
half-bridge leg transitions (t2, t3), (t7, t8), respectively. The remaining eight phases are
exactly identical to those of the DCMA above-resonance mode.
a) t1 → t2. Q1 is ON and Q2 is OFF. At t=t1 IR equals I(Lp) and then I(D1) becomes
zero before Q1 turns off at t=t2, when this phase ends, and remains zero until t=t2.
During this interval the Equation 12 is met and the current IR = I(Lp) is a portion of
a sinusoid having a frequency f = fR2.
b) t6 → t7. Q1 is OFF and Q2 is ON. At t=t6 IR equals I(Lp) and then I(D2) becomes
zero before Q2 turns off at t=t7, when this phase ends, and remains zero until t=t7.
During this interval the Equation 12 is met and the current IR = I(Lp) is a portion of
a sinusoid having a frequency f = fR2.

Remarks
1. The transition between this DCMAB mode and the previous DCMA is marked by the
IR = I(Lp) condition occurring exactly at t = t1 of Figure 18.
2. In this "above-resonance" DCM submode, in a switching cycle there are two time
intervals (t1, t4), (t6, t9) during which no current flows on the secondary side (hence this
is DCM operation) and then the entire transformer's primary inductance Ls+Lp
resonates and fR2 appears. Considering each half-cycle, nonconductive intervals
appear at the beginning and the end.
3. As shown in the diagrams of Figure 19, the tank circuit current is still lagging the
impressed voltage, so that they have the same sign at half-bridge leg transitions.
Furthermore, the switched currents IR(t2) and IR(t6) are large enough to complete the
HB node swing well within the deadtimes (t2, t3) and (t7, t8) respectively. As compared
to DCMA mode, the duration of the energy taking phase (t0, t1) is even shorter, the
external recirculation phase is longer and the displacement angle ϕ:

Equation 13
t 10 – t 8
ϕ = 2π -----------------
t 10 – t 0
is even closer to π/2. Most of the energy in the tank circuit is reactive.
4. As to the secondary rectifiers, they start conducting during the conduction period of Q1
and Q2, respectively. Both the initial current and also its di/dt are zero, thus they have a

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The LLC resonant half-bridge converter AN2644

soft turn-on. They cease to conduct before the transitions of the half-bridge. The
operation is DCM, then ZCS occurs by definition.

Figure 19. Operation above resonance (f > fR1): main waveforms in DCMAB
operation at light load
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

Q1 ON Q1 OFF Q1 ON
Q2 OFF Q2 ON Q2 OFF

HVG= Q1 gate VHB = Node HB voltage IR = Tank circuit’s current I(Q1) = Q1 current V(D1) = D1 anode voltage I(D1) = D1 current

LVG = Q2 gate Vc = Resonant capacitor voltage I(Lp) = Lp (magnetizing) current I(Q2) = Q2 current V(D2) = D2 anode voltage I(D2) = D2 current

2.3.3 Operation below resonance (fR2 < f < fR1, R>Rcrit)

In this operating mode the converter still exhibits its usual frequency vs. load characteristic.
We will consider two submodes where, in a closed-loop regulated system, DCM operation
gets deeper and deeper as the output load is increased and frequency is moved away from
resonance.

DCMAB at medium-light load

This "below-resonance" DCM submode is exactly equal to the above-resonance DCMAB
submode previously considered. The waveforms are shown in Figure 20 and it is possible to
see that they match those shown in Figure 19.
Note only that in this case the condition IR = I(Lp) at t=t1 occurs at a considerably higher
power level than in the case of the above-resonance DCMAB submode (2:1 in the example
shown).

DCMB at heavy load

This "below-resonance" DCM submode, which is unique to below resonance operation,
actually comprises two submodes (DCMB2 & DCMB1) as frequency goes away from
resonance. Their waveforms do not differ much, only those of DCMB2 will be shown. It is
possible to identify eight fundamentals subintervals and the relevant waveforms are

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AN2644 The LLC resonant half-bridge converter

illustrated in the timing diagram of Figure 21. Again, t0 is the instant when, with Q1
conducting and Q2 open, the tank current IR has a positive-going zero-crossing.

Figure 20. Operation below resonance (fR2 < f < fR1 , R>Rcrit): main waveforms in
DCMAB operation
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

Q1 ON Q1 OFF Q1 ON
Q2 OFF Q2 ON Q2 OFF

HVG= Q1 gate VHB = Node HB voltage IR = Tank circuit’s current I(Q1) = Q1 current V(D1) = D1 anode voltage I(D1) = D1 current

LVG = Q2 gate Vc = Resonant capacitor voltage I(Lp) = Lp (magnetizing) current I(Q2) = Q2 current V(D2) = D2 anode voltage I(D2) = D2 current

a) t0 → t1. Q1 is ON and Q2 is OFF. This is the "energy taking" phase, when current
flows from the input source to the tank circuit, so that energy is positive. The
operating point of Q1 is in the first quadrant (current is flowing from drain to
source). D2 is nonconducting and its reverse voltage is approximately 2·Vout (plus
the contribution from LL2, here not shown). D1 is conducting as well, so the
voltage across Lp is a Vout. Lp, then, is not participating in resonance and Cr is
resonating with Ls only. IR is a portion of a sinusoid having a frequency f = fR1.
During this phase, which ends when IR equals I(Lp) and, then, I(D1)=0 at t=t1, IR
reaches its maximum value, after that it starts decaying.
b) t1 → t2. Q1 is ON and Q2 is OFF. At t=t1 I(D1) becomes zero and IR equals I(Lp),
that is before the conduction time of Q2 ends. Both D1 and D2 are nonconducting
and Lp, no longer shunted by the load reflected to the primary side, goes
effectively in series to Ls and participates to resonance. IR is a portion of a
sinusoid having a frequency f = fR2. Depending on the tank circuit's parameters
and on the operating conditions, this portion can be similar to a straight line, as
shown in the diagrams of Figure 21. This phase ends when Q1 is switched off at
t=t2.
c) t2 → t3. This is the deadtime during which both Q1 and Q2 are OFF. At t=t2
I(Q1)=I(Lp)=IR is greater than zero and provides the energy to let the node HB
swing from Vin to ground, so that the body diode of Q2, DQ2, is injected. This
allows IR to flow. The voltage across Lp reverses to -a·Vout. D2 starts conducting
while D1 is reverse biased with a negative voltage approximately equal to 2·Vout

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The LLC resonant half-bridge converter AN2644

(plus the contribution from LL2, not shown here). This phase ends when Q2 is
switched on at t=t3.
d) t3 → t4. Q1 is OFF and Q2 is ON. At t=t3 IR is diverted from DQ2 to the RDS(on) of
Q2, so that no significant energy is lost during the turn-on transient. Note that now
the operating point of Q2 is in the third quadrant, current is flowing from the source
to drain. D2 keeps on conducting and the voltage across Lp is -a·Vout, so that Lp
is not participating in resonance and Cr is resonating with Ls only. IR is a portion of
a sinusoid having a frequency f = fR1. This phase ends when IR=0 at t=t4.

Figure 21. Operation below resonance (fR2 < f < fR1, R>Rcrit): main waveforms in
DCMB2 operation

t0 t1 t2 t3 t4 t5 t6 t7 t8

Q1 ON Q1 OFF Q1 ON
Q2 OFF Q2 ON Q2 OFF

HVG= Q1 gate VHB = Node HB voltage IR = Tank circuit’s current I(Q1) = Q1 current V(D1) = D1 anode voltage I(D1) = D1 current

LVG = Q2 gate Vc = Resonant capacitor voltage I(Lp) = Lp (magnetizing) current I(Q2) = Q2 current V(D2) = D2 anode voltage I(D2) = D2 current

e) t4 → t5. Q1 is OFF and Q2 is ON. The tank circuit current, which is zero at t=t4
becomes negative. D1 is nonconducting and its reverse voltage is approximately
2·Vout (plus the contribution from LL2, here not shown). Lp's current has a
negative slope, so the voltage across Lp must be negative. Since the diode D2 is
conducting this voltage will be equal to -a·Vout. Lp, then, is not participating in
resonance, Cr is resonating with Ls only and IR is a portion of a sinusoid having a
frequency f = fR1. During this phase, which ends when IR equals I(Lp) and,
thereby, I(D2) is zero at t=t15. IR reaches its minimum value, after that it starts
increasing.
f) t5 → t6. This phase mirrors (t1, t2). At t=t5 I(D2) becomes zero and IR equals I(Lp),
that is before the conduction time of Q1 ends. Both D1 and D2 are nonconducting
and Lp, no longer shunted by the load reflected to the primary side, goes
effectively in series to Ls and participates to resonance. IR is now a portion of a
sinusoid having a frequency f = fR2. This phase ends when Q2 is switched off at
t=t6.

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AN2644 The LLC resonant half-bridge converter

g) t6 → t7. This is the deadtime during which both Q1 and Q2 are OFF. At t=t6
IR = I(Lp) is (in absolute value) greater than zero and provides the energy to let the
node HB swing from 0 to Vin, so that the body diode of Q1, DQ1, is injected. This
allows IR to flow back to the input source. The voltage across Lp reverses to a
Vout, D1 starts conducting while D2 is reverse biased with a negative voltage
approximately equal to 2·Vout (plus the contribution from LL2, here not shown).
This phase ends when Q1 is switched on at t=t7.
h) t7 → t8. Q1 is ON and Q2 is OFF. At t=t7 IR is diverted from DQ1 to the RDS(on) of
Q1, so that no significant energy is lost during the turn-on transient. Note that now
the operating point of Q1 is in the third quadrant, current is flowing from the source
to drain. This phase, along with the preceding one is the "external energy
recirculation phase": current is negative (coming out of the input terminal) despite
that the impressed voltage is positive so that the input energy is negative, i.e. it is
returned to the input source. D1 is still conducting and the voltage across Lp is a
Vout, so that Lp is not participating in resonance anymore and Cr is resonating with
Ls only. IR is again a portion of a sinusoid having a frequency f = fR1. This phase
ends when IR=0 at t=t8 and another switching cycle begins.

Remarks
1. Also in this "below-resonance" DCM submode the multiresonant nature of the LLC
converter shows up. From t1 to t2 and from t5 to t6 the secondary rectifiers are both
open and the second resonance frequency fR2 appears. This is one of the fundamental
advantages of the LLC resonant converter over the traditional LC series-resonant
converter. In fact it helps keep operation away from capacitive mode. Although the tank
circuit current IR lags the impressed voltage (being R>Rcrit by assumption) so that they
have the same sign at half-bridge leg transitions, the switching period is longer than the
resonant period,1/fR1. Then IR, which is decaying (in absolute value), might come close
to zero or even reverse if it still evolved according to the same sinusoid at frequency
f=fR1 (see the extrapolated black lines drawn in (t1, t2) and (t5, t6)). This lower frequency
sinusoid "holds up" the tank current, hence ensuring that the switched currents IR(t2)
and IR(t6) do not change sign and have amplitude large enough to complete the HB
node swing well within the deadtimes (t2, t3) and (t6, t7) respectively, i.e. ZVS.
2. In the series LC tank Ls-Cr operating below resonance with R>Rcrit the voltage drop
across the L-C series is negative (the capacitive reactance is larger in module than the
inductive reactance), i.e. a minus sign is located at the node HB. As a result:

Equation 14
V in
a ⋅ V out > --------
2
Then, when operating below resonance, for a given input voltage, the LLC resonant
half-bridge will provide an output voltage higher than that available at resonance, and
vice versa, with a given output voltage the LLC resonant half-bridge will operate below
a resonance if the input voltage is lower than 2·Vout. In other words, the conversion
ratio, intended as previously mentioned, is > 1, then the LLC is said to have a "step-up"
characteristic when operating below resonance.
3. The secondary rectifiers D1 and D2 start conducting when Q2 and Q1 are switched off,
respectively. The initial current is zero and its di/dt is low, thus they have a soft turn-on.

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The LLC resonant half-bridge converter AN2644

They cease to conduct before the transitions of the half-bridge. The operation is DCM,
then ZCS occurs by definition.
4. Essentially, the reason why D2 does not conduct during (t1, t2) and D1 does not during
(t5, t6) is that during these subintervals the condition expressed by Equation 12 is met.
5. The waveforms in DCMB1 are very similar, only the portion of sinusoid at f = fR2 decays
to zero more quickly. While DCMB2 is characterized by the duration of the intervals (t1,
t2) and (t5, t6) that gets longer as frequency is reduced, in DCMB1 the duration of these
intervals starts decreasing quite rapidly to reach zero at the boundary with capacitive
mode operation. The "border belt" adjacent to the capacitive region is included in the
region where DCMB1 occurs, thus it can be a good design practice to limit the
operation of the converter to the DCMB1-DCMB2 boundary.

2.3.4 Capacitive-mode operation below resonance (fR2 < f < fR1, R<Rcrit)
In this operating mode, unique to below-resonance operation and corresponding to the
CCMB operating mode defined in [3], it is possible to distinguish six fundamental time
subintervals within a switching cycle, as illustrated in the timing diagrams of Figure 22.
In this case it is convenient to define t0 as the instant when Q1 is switched on.
a) t0 → t1. The tank current IR(t0) as Q1 is switched on is already positive: this
means that in the just finished deadtime it was flowing through the body diode of
Q2, DQ2. Actually, this is confirmed by the voltage VHB of the half-bridge midpoint
which was previously zero and is abruptly pulled up to Vin exactly at t=t0 with a
large dv/dt. The body diode DQ2 is then reverse-recovered and a large current
spike flows through Q1 and DQ2 until the latter recovers completely. Functionally
this is similar to a cross-conduction of the half-bridge leg. Very high di/dt may
occur and, as a result, large voltage spikes are generated across the parasitic
inductances experiencing this large di/dt. The voltage VHB may have large
positive overshoots. During this phase when energy is taken from the input source,
the tank current reaches its maximum value and then decays. The phase ends
when IR=I(Lp) and, then, I(D1)=0 at t=t1.
b) t1 → t2. Unlike what happens in the below-resonance DCMB2 submode, where
there was insufficient voltage across the resonant capacitor to forward-bias D2,
here Vc is much larger and D2 starts conducting immediately at t=t1. IR starts
decreasing, becoming lower than I(Lp) and eventually crosses zero before Q1
turns off, which marks the end of the this phase at t=t2.
c) t2 → t3. This is the deadtime during which both Q1 and Q2 are OFF. During this
phase IR is already negative and further decreasing. Since Q1 is off, it is flowing
through DQ1. Note that the voltage of the half-bridge midpoint VHB does not
change. This phase ends when Q2 turns on at t=t3.

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AN2644 The LLC resonant half-bridge converter

Figure 22. Capacitive mode operation below resonance (fR2 < f < fR1, R<Rcrit): main
waveforms
t0 t1 t2 t3 t4 t5 t6

Q1 ON Q1 OFF
Q2 OFF Q2 ON

HVG= Q1 gate VHB = Node HB voltage IR = Tank circuit’s current I(Q1) = Q1 current V(D1) = D1 anode voltage I(D1) = D1 current

LVG = Q2 gate Vc = Resonant capacitor voltage I(Lp) = Lp (magnetizing) current I(Q2) = Q2 current V(D2) = D2 anode voltage I(D2) = D2 current

d) t3 → t4. The tank current IR(t3) as Q2 is switched on is already negative and

flowing through the body diode of Q1, DQ1. The voltage of the half-bridge
midpoint, VHB, is abruptly pulled down to ground at t=t3 with a large dv/dt. The
body diode DQ1 is then reverse-recovered and a large current spike flows through
Q2 and DQ1 until the latter recovers completely. Again there is a condition
functionally equivalent to a cross-conduction of the half-bridge leg. Very high di/dt
may occur and, as a result, large voltage spikes are generated across the parasitic
inductances experiencing this large di/dt. The voltage VHB may have large
negative undershoots. During this phase energy is internally recirculated, the tank
current reaches its minimum value and then increases. The phase ends when
IR=I(Lp) and, then, I(D2)=0 at t=t4.
e) t4 → t5. This phase mirrors exactly (t1, t2). The voltage across the resonant
capacitor is so large that D1 is forward-biased and, thereby, starts conducting
immediately at t=t4. IR starts increasing, becoming higher than I(Lp) and
eventually crosses zero before Q2 turns off, which marks the end of this phase at
t=t5.
f) t5 → t6. This is the deadtime during which both Q1 and Q2 are OFF. During this
phase IR is already positive and increasing. Since Q2 is off, it is flowing through
DQ2. Note again that the voltage of the half-bridge midpoint VHB does not
change. This phase ends when Q2 turns on at t=t3 and another switching cycle
begins.

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The LLC resonant half-bridge converter AN2644

Remarks
1. In the below-resonance capacitive mode operation, since current is continuously
flowing on the secondary side, this is a CCM mode (as already stated, it corresponds to
the CCMB mode defined in [3].
2. The physical reason of this CCMB operation is, as previously pointed out, the large
voltage developed across the resonant capacitor. A large energy level must be
circulating in the tank circuit and this is consistent with R<Rcrit condition in order for the
capacitive mode to take place. Capacitive operating mode is then likely to occur under
heavy load, overload or short circuit conditions and appropriate countermeasures must
be taken to handle this.
3. Note that in all the inductive modes the absolute value of the switched currents (i.e. the
current IR when either power MOSFET is switched off) is always greater than (in CCM
mode above resonance) or equal to (in all DCM modes) the current I(Lp). In the
capacitive mode, instead, the absolute value of the switched currents is lower than that
in Lp. This consideration is useful when analyzing the transitions of the node HB.
4. Unlike the other modes, in capacitive mode the secondary rectifiers D1 and D2 start
conducting during the conduction period of Q2 and Q1, respectively. The initial current
is zero and its di/dt is low, thus they have a soft turn-on. Also in this case the voltage
across the secondary rectifiers reverses as a result of their currents going to zero.
Then, ZCS is maintained even under these conditions and it is possible to conclude
that the secondary rectifiers are soft-switched at both turn-on and turn-off under all
operating conditions and that this property is inherent in the topology. In fact no
assumption has been made about the tank circuit's parameters.

Figure 23. No-load operation (cutoff): main waveforms

t0 t1 t2 t3 t4 t5 t6

Q1 ON Q1 OFF Q1 ON
Q2 OFF Q2 ON Q2 OFF

HVG= Q1 gate VHB = Node HB voltage IR = Tank circuit’s current I(Q1) = Q1 current V(D1) = D1 anode voltage I(D1) = D1 current

LVG = Q2 gate Vc = Resonant capacitor voltage I(Lp) = Lp (magnetizing) current I(Q2) = Q2 current V(D2) = D2 anode voltage I(D2) = D2 current

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AN2644 The LLC resonant half-bridge converter

2.4 No-load operation

The ability to operate under no-load conditions is another peculiar characteristic of the LLC
resonant half-bridge converter. The typical waveforms in this operating mode, called also
"cutoff" mode, which can occur at frequencies both above, below and at the resonant
frequency fR1, as demonstrated in [3], are illustrated in the timing diagrams of Figure 23.
Note that it is IR=I(Lp), then I(D1)=I(D2)=0, throughout the entire switching cycle. IR is made
by portions of sinusoid at f=fR2, but looks very much like a triangular waveform. In order for
this operation to occur, the voltage developed across Lp and reflected to the secondary side
has to be lower than the output voltage throughout the entire switching cycle, so that either
secondary rectifier cannot be forward-biased. In other words, Equation 12 has to be met for
t ∈(t0, t6). The ability of the converter to operate with no-load can be easily deducted by
Equation 12 itself. However big the peak value of Vin(t)-Vc(t) is and provided a·Vout is not
zero, it is possible to find a value of Lp that meets condition (α). In the end, no-load
operation is not an intrinsic property of the LLC resonant converter (like ZCS for the
secondary rectifiers) but it can be achieved with an appropriate design of the tank circuit.
The difference with respect to the LC series resonant converter is apparent. If Lp → ∞ the
LLC converter turns into the LC one but Vc → 0 because there is no current through the
resonant tank and the only possible equilibrium condition is Vin = a·Vout. If the input and
output voltage have a different ratio, output voltage regulation will be impossible.
Seen from a different standpoint, under no load conditions and at a frequency considerably
higher than fR1, the resonant capacitor Cr "disappears" (Vc(t) ≈ Vin/2) and the output voltage
is given by the inductive divider made up by Ls and Lp as shown by the equivalent circuit of
Figure 24. Then, if the voltage conversion ratio is greater than the inductive divider ratio,
regulation will be possible at some finite frequency, otherwise it will not be. From Equation
12, substituting Vin(t) = Vin and, then, Vc(t) = Vin/2, it is possible to find a necessary condition
in order for the converter to be able to regulate at zero load:

Equation 15
Lp - a ⋅ V out
------------------- ≤ 2 -------------------
Ls + Lp V in

Lp, then, plays a key role. It not only makes zero load operation possible but allows soft-
switching under these conditions too, as already discussed. The price to pay for that is the
considerable tank current IR=I(Lp) circulating in the circuit and illustrated in Figure 23. This
circulation is not lossless. Power is dissipated in power MOSFET, the resonant capacitor
and the transformer.
This prevents the LLC resonant converter from achieving extremely low input power levels at
no load, unless appropriate countermeasures are taken. The most effective way to reduce
no-load consumption to a very low level is to let the converter operate intermittently ("burst-
mode" or "pulse-skipping" operation). In this way, the average value of the tank current can
be reduced at an almost negligible value. Furthermore, the average switching frequency will
be considerably lowered thus minimizing the residual turn-off switching losses.

2.5 Overload and short circuit operation

The equivalent schematic of the converter under short circuit conditions is illustrated in
Figure 25. The inductance Lp is actually shunted by an extremely low impedance, so that
the LLC circuit reduces to a series LC circuit. The transformer will work as a "current
transformer", so that the output current will be a times the primary (input) current Iin. It is

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The LLC resonant half-bridge converter AN2644

intuitive that the impedance of the Ls-Cr resonant tank plays a key role. Note that this
impedance becomes zero at f = fR1. Two cases will be considered:
1. The converter always works above resonance (some means is provided to bottom-limit
the operating frequency at a value fm > fR1). The control loop, in the attempt to keep the
output voltage regulated, will reduce the switching frequency to the minimum value fm.
In this case the converter still operates in the inductive region (CCM submode) and
ZVS is ensured. However, the impedance of the Ls-Cr tank circuit can be very low and
then the current Iin can reach very high values, the closer the minimum frequency to
fR1 is, the lower the impedance and the higher the current will be.
2. The converter can operate below resonance (some means is provided to bottom-limit
the operating frequency at a value fm such that fR2 < fm < fR1). Again, the control loop,
in the attempt to keep the output voltage regulated, will reduce the switching frequency
to the minimum value fm. In this case, the input current will be limited by the impedance
of the Ls-Cr tank circuit at a value that is as lower as fm is lower. However the capacitive
region is entered and ZVS is lost, with all the consequent troubles previously
mentioned. The waveforms will be similar to those in Figure 22.

Figure 24. Circuit's equivalent schematic Figure 25. Circuit's equivalent schematic
under: no-load conditions under: short-circuit conditions

Iin
Ls
a:1

Cr Ls
Vin a·Vout Lp Vout
Vin

It is interesting to see what happens under short circuit if the converter is operating at
resonance (f = fR1). Tank circuit's impedance is zero, then the short circuit is directly
connected across the input source and the current Iin is theoretically unlimited.
Theoretically, switching frequency should not change (the system is working in the load-
independent point). In real-world operation, Iin, though reaching very high values, will be
limited by the parasitic resistance of the short-circuit mesh, the ESR of Cr and by
transformer's nonidealities. Additionally, the drop across the secondary rectifiers does not
reflect a true short circuit on the primary side. Because of the parasitic resistances, the
output voltage will drop and the control loop will react pushing the operating frequency to the
minimum fm, which, realistically, must be lower than fR1 if operation at resonance is allowed.
In the end this will fall into case 2.
Still with reference to case 2, it is worth remembering that the capacitive region is entered
and ZVS for MOSFETs is lost as Rcrit = Zo 0 ⋅ Zo ∞ , well before short circuit.
From the above analysis it is possible to draw the following conclusions:
1. Two major issues arise under overload or short circuit conditions: very high current
levels, and capacitive mode operation (with loss of ZVS, etc.). This makes the operation
of the LLC resonant converter under overload or short circuit inherently unsafe if no
overcurrent protection (OCP) is used, just like in conventional PWM-controlled
converters. OCP will have to prevent not only the tank current from exceeding unsafe

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AN2644 The LLC resonant half-bridge converter

values but also ZVS from being lost. In principle, its setpoint must be such that the
condition R>Rcrit is always fulfilled.
2. Limiting the minimum operating frequency of the converter is not always effective. It
prevents losing ZVS under overload or short circuit only if this minimum value is above
the resonant frequency fR1. Thereby, relying on just limiting the minimum operating
frequency would force giving up the below-resonance operating region and its
interesting properties, severely limiting the usability range of the converter.
Furthermore, the problem of having too high circulating current would be still unsolved.
3. Converters are often specified to have peak load demands that are considerably higher
than the maximum continuous power, and whose duration is such that it cannot be
averaged by the output capacitor bank. While these peak loads may be thermally
irrelevant, from the electrical standpoint they must be considered as steady-state. OCP
circuits must not be triggered and the converter must be designed so that the condition
R>Rcrit is not violated under these transient conditions as well.
The inspection of the waveforms under heavy load conditions shows that, unlike PWM-
controlled converters, the peak current in a switching cycle is not reached at the end of the
conduction time of either MOSFET. This suggests that the usual cycle-by-cycle current
limitation so widely used in PWM-controlled converters is not applicable to LLC resonant
converters.
The simplest and also most immediate action to take in response to the detection of an
overload or short circuit condition is to increase the operating frequency. It is advantageous
to push the frequency well above the resonance frequency fR1, so that the converter
definitely operates in the inductive region, and ZVS is maintained, with the input current kept
under control by the inductive reactance of the tank circuit.
However, this frequency rise is not typically sufficient to effectively limit the short-circuit
output current at safe values. In fact, on one hand, the input impedance of the tank circuit in
the inductive region is essentially proportional to frequency. Since there are practical limits
on the maximum operating frequency (it rarely exceeds 3-4 times fR1), the short circuit tank
current can still be considerably large. On the other hand, as the output voltage drops
because of the action of the OCP circuits, the voltage reflected across Lp becomes smaller
and smaller. Then, less and less current flows through Lp and the transformer tends to
transfer all the primary current to the output.
As a consequence, the short circuit output current can be still much higher than the nominal
full-load current and the resulting stress, especially for the secondary rectifiers, might be
unacceptable. In addition to current limiting it is therefore advisable to provide some timed
shutdown protection that either forces an intermittent operation of the converter to
drastically reduce the average value of the output current or latches it off if the OCP circuits
are active for more than some time.

2.6 Converter's startup

Like in PWM-controlled converters, startup is quite a critical moment that needs to be
properly handled in LLC resonant converter as well. When the converter is first switched on
(or also while it is recovering after a protection shutdown) the energy flow should be
progressively increased to allow a slow buildup in output current and voltage. This is
commonly known as "soft-start". Doing otherwise, high and potentially destructive currents
might be drawn from the input source and through the power devices in an attempt to
charge the output capacitors and bring the output voltage to the regulated value.

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The LLC resonant half-bridge converter AN2644

Since at startup the output capacitors are discharged, the startup phase can be regarded as
a "temporary short circuit" (where, however, the output voltage is allowed to increase) and
actually it has to be handled like a short circuit as mentioned in the previous section. To
minimize energy flow, the initial switching frequency will have to be much higher than the
resonance frequency fR1, so that the converter operates in the inductive region, ZVS is
maintained and the input current is kept under control by the inductive reactance of the tank
circuit. The frequency will be allowed to progressively decay until the output voltage comes
close to the regulated value and the control loop closes and takes over.
Some typical waveforms at startup for the converter of Figure 15 are shown in Figure 26,
where the initial frequency is set at 300 kHz (against fR1≈ 76 kHz).
In the LLC resonant converter there is an additional phenomenon that shows up just at the
very beginning and causes higher resonant tank current to flow and ZVS loss.
As mentioned in the Section 2, the resonant capacitor Cr plays the double role of resonant
capacitor and DC blocking capacitor. This essentially means that the resonant voltage on Cr
is superimposed on a DC value that equals Vin/2 because the half-bridge is driven with 50%
duty cycle. As a result, the primary of the transformer is symmetrically driven by a ±Vin/2
square wave. This is true when steady-state operation has been reached.
At startup the initial voltage across Cr is zero and for the first few cycles the voltage seen by
the transformer when the high-side power MOSFET Q1 is on is considerably different from
the voltage seen when Q2 is on. The transformer driving voltage will tend to become
symmetrical as switching cycles follow one another and Cr is charged at the steady state
DC level. During the Cr charge transient the v·s unbalance can be quite high and this makes
the tank current irregular in the first few cycles, with peak values that can be considerably
higher than the steady-state peak-to-peak current expected at the starting frequency.
Additionally, the fundamental ZVS conditions ("when one switch turns off, the tank current
must have the same sign as the impressed voltage") may be violated so that even capacitive
mode operation can be observed.

Figure 26. Converter's startup: main waveforms

HVG= Q1 gate VHB = Node HB voltage IR = Tank circuit’s current I(Q1) = Q1 current V(D1) = D1 anode voltage I(D1) = D1 current

LVG = Q2 gate Vc = Resonant capacitor voltage I(Lp) = Lp (magnetizing) current I(Q2) = Q2 current V(D2) = D2 anode voltage I(D2) = D2 current

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AN2644 The LLC resonant half-bridge converter

This phenomenon is well-known in push-pull and half-bridge topologies and is sometimes

referred to as "flux doubling" because the transformer's magnetic flux excursion, which
normally swings by 2Bpk from -Bpk to +Bpk under steady state operation, in the first cycle
goes from 0 to 2Bpk. Fortunately, if the integrated magnetics approach is used, there will be
no risk of saturation. Flux doubling will concern only the resonant inductor Ls, which is
mostly associated to the transformer's leakage inductance that, by definition, cannot
saturate because the relevant flux is developed in air.
Although not inherently hazardous, (capacitive mode and ZVS loss will typically occur in the
first two-three cycles, then the associated stress level is practically negligible) this
phenomenon is not nice to see. To eliminate or, at least, minimize it, the split capacitor
configuration of Figure 4 can be used in some cases. In fact, the initial voltage across each
capacitor will be close to Vin/2 (equal to Vin/2 if the two capacitors had exactly the same
value), then there will be only a minimum transient.
However, this is ineffective with many control ICs with high-side MOSFET driving capability
using capacitive bootstrap. To guarantee an adequate precharge of the bootstrap capacitor
to correctly drive the high-side MOSFET Q1 since the first cycle, the low-side MOSFET Q2
is turned on for some time before starting to operate (as shown in Figure 26), which
discharges completely the lower Cr/2 capacitor. This bootstrap precharge mechanism,
shown in Figure 27, makes ineffective also any pull-up that could precharge Cr.
In this case the initial current peak cannot be completely eliminated, just reduced by either
using a higher starting frequency or by forcing the duty cycle to start from a value
considerably smaller than 50% and letting it widen progressively.

Figure 27. High-side driving with bootstrap approach and bootstrap capacitor
charge path
Vin
DBOOT

CBOOT
I BOOTCHARGE
Vcc

Level Q1 Cr / 2
Shifter
Ls
a:1:1

Vcc
Lp
Control Q2 Cr / 2
Logic

2.7 Analysis of power losses

Conduction power losses on the primary side are located in the power MOSFETs, in the
resonant capacitor Cr and the transformer (for convenience the secondary winding losses
can be incorporated). On the secondary side, losses will be essentially located in the
secondary rectifiers, although those in the output capacitors cannot be neglected, at least
as far as capacitor selection is concerned.

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The LLC resonant half-bridge converter AN2644

Unless the converter is running at very high frequency, which would make turn-off losses
dominant, RDS(on) is usually the major source of power loss in power MOSFET. In the total
loss budget, however, the power wasted in power MOSFETs is usually a minor contributor,
especially when the converter is powered from the output of a PFC preregulator (400 V
typ.). It is not uncommon to see power MOSFETs running cool with minimum heat sinking.
The resonant capacitor Cr dissipates because of its own ESR. For this reason, especially
when very high efficiency is required, Cr should be a low-loss one, suited for AC/pulse
applications. Polypropylene film capacitors are the preferred choice.
Concerning the transformer, high frequency copper losses need to be particularly
addressed. In fact, eddy currents and proximity losses are considerable, especially in the
side-by-side winding arrangement because of the high transverse flux. Litz-type or
multistrand wire is a must for both primary and secondary windings.
Switching losses are essentially located in the power MOSFET Q1 and Q2. As previously
stated, the value of the switched current at heavy load (IRmin) is a trade-off between the
need for ensuring ZVS for both Q1 and Q2 and their turn-off losses. The higher the
switched current is, the higher the margin for ZVS will be, but at the expense of larger
switching loss due to voltage-current overlap. It is intuitive that the optimum design, in terms
of total dynamic losses minimization, is the one that uses for IRmin the minimum value
necessary to achieve ZVS. It still provides zero capacitive turn-on losses with minimum
switching losses at turnoff. Since component tolerance must be accounted for, and losing
ZVS must be avoided not only for efficiency reasons but also to prevent troubles, adequate
margin needs to be considered and the typical operation will be suboptimal.
Secondary rectifiers are usually the components where the majority of power losses occur.
Assuming the rectifiers are identical, their cumulative conduction losses are given by:

Equation 16
⎧ 2 ⎫
⎪ V th I out – dc + R d I out – rms ⎪ full - wave rectification
Pd = ⎨ ⎬
⎪ 2 ( V th I out – dc + R d I 2out – rms ) ⎪ bridge rectification
⎩ ⎭

where Vth is the rectifier's threshold voltage and Rd its dynamic resistance. With bridge
rectification, losses are almost double because there are always two diodes in the
conduction path (we say "almost" because of the lower blocking voltage rating, so that Vth
and Rd are expected to be slightly lower for the same current rating). Hence this
arrangement is preferred when the output voltage is high. Firstly, the efficiency loss due to
the rectifiers (which is ∝ 2 VF/Vout) becomes less significant. Secondly, the higher the
output voltage is, the more a lower blocking voltage requirement becomes beneficial.
As compared to the ZVS Asymmetrical Half-bridge and the Forward converter, conduction
losses (for the same technology and blocking voltage) would be slightly greater because of
the worse current form factor that would increase the term, but this is compensated by the
absence of recovery and its associated losses. In the end, considering also that in the LLC
resonant half-bridge there is no secondary choke with its associated losses, it is expected
that the total secondary losses will be lower.

2.8 Small-signal behavior

It is essential to know the small-signal behavior of the LLC resonant converter to be able to
design the feedback loop. In line with the approach followed to describe its steady-state

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AN2644 The LLC resonant half-bridge converter

operation, here only a qualitative description will be given, which is the result of a
characterization by simulation [7] (refer to Section 4).
As stated many times, the operating frequency is the parameter that allows regulation of the
input-to-output energy flow. The control-to-output transfer function G(jω) that characterizes
the small-signal behavior of the LLC resonant converter will then be defined as:

Equation 17
^
Vo
^ = G ( jω )
------
f
In the overall converter's dynamics it is convenient to separate the contribution of the
"inverter" part and that of the rectifying and filtering block that transforms the inverter in a
converter. This is quite a useful concept of superposition because it gives considerable
physical insight. Regardless of the operating mode of the inverter and, then, of its
contribution to converter's dynamics, the rectifying and filtering block always introduces a
low frequency pole associated to the output capacitor, the load resistance and the open-
loop output impedance Zo0 of the resonant tank, plus a zero due to the output capacitor and
its ESR (equivalent series resistor). This pole moves with the load (frequency is higher at
heavy load, lower at light load) because of the changes in Zo0, while the zero is at an
essentially fixed frequency, exactly like in PWM converters.
Different types of dynamic behavior, corresponding to different pole distributions of G(jω),
can be observed depending on the operating mode. Again we will consider operation at,
above and below resonance.

2.8.1 Operation above resonance (f > fR1)

In this operating mode the converter features a special characteristic typical of resonant
converters, the so-called "beat frequency double pole", i.e. two complex and conjugate
poles having their imaginary part at the difference between the switching frequency f and
the resonant frequency fR1. In addition to this double pole, contributed by the inverter part,
there is the pole-zero pair associated to the output filter. If f is significantly higher than fR1,
the system can be regarded as a single-pole system.
As switching frequency moves close to resonant frequency, the beat frequency double pole
will move to lower frequency. When the switching frequency is very close to resonant
frequency, the beat frequency double pole will eventually split and become two real poles.
One moves to higher frequencies and the other moves to lower frequencies as switching
frequency gets closer and closer to resonant frequency. Finally, the split pole moving to low
frequency will merge with the low frequency pole caused by the output filter and form a
double pole. This type of characteristic is very similar to that of the conventional series LC
converter.
Provided the converter is not operating too close to resonance, as long as it runs in CCM,
the pole distribution tends not to change significantly. In DCM operation, instead, the beat
frequency double pole will more pronouncedly move to higher frequencies and the low
frequency pole to lower frequencies. At light load, the converter can then be regarded as a
single-pole system.
Concerning how the resonant tank characteristics affect the small-signal behavior, the
parallel inductor Lp has no practical effect. Conversely, increasing the impedance of the
resonant tank (i.e. increasing Ls and reducing Cr while keeping the same fR1), the DC gain
will increase. Also the low frequency pole changes with the resonant tank impedance (it

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The LLC resonant half-bridge converter AN2644

gets higher at low impedance). In fact, the low frequency pole is not determined by the load
resistor alone but by the output impedance of the tank circuit as well.

2.8.2 Operation below resonance (fR2 < f < fR1, R>Rcrit)

In this operating mode the converter's dynamics changes considerably. In the left half-plane,
there are three poles and one zero but no beat frequency double pole. The pole distribution
is quite insensitive to switching frequency as compared to that in the above resonance
operation. The pole that in the above resonance operation was moving to higher frequency
when switching frequency was approaching resonance here moves back to lower
frequencies as switching frequency is further reduced going away from resonance. Its
position, however does not change much. The low-frequency double pole is minimally
affected too.
A Right Half Plane Zero (RHPZ) can be observed that moves with switching frequency but,
fortunately, it stays typically away from the low frequency region of interest in the design of
the feedback loop.
Approaching capacitive region, beat frequency dynamics tends to appear again. The phase
has an abrupt 180º shift just beyond the capacitive region threshold (feedback from negative
turns into positive).
Starting from heavy load conditions, at first the Q associated to the low frequency double
pole decreases. The RHPZ shifts to higher frequencies and leaves the stage. Further
reducing the load, the Q of the low frequency double pole increases. At very light load the
low frequency double pole splits, one moves to higher frequencies and the other to lower
frequencies. Again, at very light load the converter can be regarded as a single-pole system.
Unlike in the above resonance operation, in this case the parallel inductor Lp has a
considerable impact on the DC gain of the converter. Additionally, it affects the RHPZ as
well. Larger values for Lp tends to shift it to lower frequencies. As far as the impedance of
the resonant tank is concerned, the effect is the same as in the above resonance operation.

2.8.3 Operation at resonance (f = fR1)

Operation at resonance can be regarded as the borderline between the two previously
considered operating modes. The behavior will not be different from that seen just above
(and just below) resonance: two low-frequency poles, one high-frequency pole and the ESR
zero. The same behavior can be seen as far as load dependence is concerned.
The compensation of the error amplifier must consider the different types of small-signal
behavior that the converter can exhibit, especially if it is designed to operate both above and
below resonance. The challenge comes essentially from its second-order behavior exhibited
in its operation close to resonance frequency due to the low frequency double pole. To
properly compensate that, the best option is a type 3 amplifier, i.e. a compensator with one
pole at the origin plus two poles and two zeros at finite frequencies. The pole at the origin
gives excellent load and line regulation characteristics. The two zeros are placed at low
frequency to compensate the double pole of the control-to-output transfer function, by
counteracting their phase lag. The poles are placed to compensate the ESR zero and
provide more attenuation at switching frequency. A practical implementation of this
compensator is shown in Figure 28 along with the relationship between the component
values and its transfer function.

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AN2644 The LLC resonant half-bridge converter

Figure 28. Frequency compensation with an isolated type 3 amplifier (3 poles + 2

zeros)

Vo
RF2
Ic RB1
RF3 R1
CF2

RB2

CF3 CF1 RF1

CTR

TL431
R2

Equation 18
^
IC CTR 1 + s ( RB1 + RF2 )CF2 1 + s ( R1 + RF1 )CF1
------ = ------------------------------------------------- ⋅ ------------------------------------------------------------- ⋅ --------------------------------------------------------
V o s ( R1 ⋅ RB1 ⋅ CF1 ) 1 + sRF2 ⋅ CF2 1 + sRF3 ⋅ CF3
^

45/64
Conclusion AN2644

3 Conclusion

The operation of the LLC resonant converter has been examined in detail and its most
important properties have been deduced by inspection of its salient waveforms under
different operating conditions. To summarize, the most significant merits of this topology are:
● Soft-switching of all semiconductor devices: ZVS (zero-voltage switching) at turn-on for
the MOSFETs and ZCS (zero-current switching) at both turn-on and turn-off for the
secondary rectifiers. The first property results from a correct design of the resonant
tank. The second one is a natural feature of the topology.
● Ability to accommodate an extremely broad load range, including zero load, with an
acceptable frequency variation. Also this property results from a correct design of the
resonant tank.
● Magnetic integration, which allows the combination of different magnetic devices into a
single physical device.
● Smooth waveforms: the current is piecewise sinusoidal with no steep edges. The
voltage, although a square wave, does not have very high dv/dt edges. EMI emissions
are considerably low and filtering requirements are relatively loose.
● As a result of all the above merits, high-efficiency, high switching frequency capability,
high power density are typical characteristics of the converters based on this topology.
The most significant facts concerning the design of an LLC resonant converter are:
● The quantities that determine whether the converter operates at resonance, above
resonance or below resonance are essentially the input and the output voltages and
the transformer's turn ratio. There is just a second-order dependence on the load
current due to the variation of the voltage drop across parasitic elements such as
winding resistance, rectifier drop, etc.
● Operation at resonance looks like the preferred operating point, where load regulation
is ideally zero, where tank current is maximally sinusoidal and where CCM operation
minimizes peak tank current for a given power throughput. Whenever possible (e.g.
when the LLC converter is powered by a PFC preregulator) it seems a good design
strategy to design the converter to work at resonance under nominal conditions, and
use below resonance operation to handle mains voltage dips and above resonance
operation to handle light load or transient overshoots of the input voltage.
● The ability to operate under no-load conditions and to ensure ZVS operation depend
essentially on the transformer's magnetizing inductance. Its value has to be traded off
against the switching losses at full load operation and the input consumption at no-load.
● Avoiding capacitive mode operation is a must. It is a too risky operating mode and any
design procedure should not leave this fundamental aspect out of consideration.
● Overcurrent and short circuit protection must be provided. They will not only have to
prevent excessive currents from flowing in both the resonant tank, the transformer and
the output rectifiers but also avoid entering capacitive mode operation.
● Soft-start is highly recommended. At startup there is a situation very similar to a short
circuit and, if not properly controlled, potentially destructive currents might flow in the
half-bridge leg and the resonant tank.

46/64
AN2644 References

4 References

1. "Resonant Converter Topologies with Three and Four Energy Storage Elements", IEEE
Trans. on Power Electronics, Vol. 9, No. 1, 1994, Pages 64 - 73
2. "A Comparison of Half Bridge Resonant Converter Topologies", IEEE Trans. on Power
Electronics, 1988. Pages: 174 - 182.
3. "Steady-state Analysis of the LLC Resonant Converter", Applied Power Electronics
Conference and Exposition, 2001. APEC 2001. Pages: 728 - 735
4. "First harmonic approximation including design constraints", Telecommunications
Energy Conference, 1998. INTELEC. Pages: 321 - 328
5. "Design Optimization for an LCL-Type Series Resonant Converter",
http://www.powerpulse.net/features/techpaper.php?paperID=76
6. "Fundamentals of Power Electronics", 2nd edition, Kluwer, 2001
7. "Topology Investigation for Front End DC/DC Power Conversion for Distributed Power
System", PhD dissertation, Virginia Polytechnic Institute and State University, 2003.

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Power MOSFET driving energy in ZVS operation AN2644

Appendix A Power MOSFET driving energy in ZVS

operation

When power MOSFETs are switched on under ZVS conditions, i.e. when their drain-to-
source is already zero, Miller effect due to drain-to-source voltage modulation is absent.
This reduces the gate charge required to turn the power MOSFET fully on, the turn-on
energy, as well as the total driving energy. This can be conveniently examined on the gate-
charge characteristic of the device (see Figure 29).

Figure 29. Comparison of gate-charge characteristics with and without ZVS

The black curve is the normal piecewise-linear gate-charge curve. The first portion is that
related to the charge of the input capacitance CGS+CGD, and Qgs is the charge needed to
bring the gate voltage up to the plateau value VM that lets the power MOSFET carry the
specified current. The flat portion is the so-called "Miller plateau", where the gate voltage
does not increase because the drain-to-source voltage is falling and CGD is wiping out the
charge supplied to the gate until the charge Qgd has been supplied. The third rising portion
is related to the overcharge of CGS+CGD needed to minimize RDS(on). Note that the slope of
this line is lower than that of the first portion. This is due to the modulation of CGD, which is
now considerably larger (CGS is essentially constant). The total gate charge supplied to the
gate to bring its voltage up to the final value VGS is Qg. The values of Qgs, Qgd, Qg are
specified on the datasheet for given VGS, VDS, ID.
The grey-hatched area included between the gate-charge curve and the VGS horizontal line
is the energy lost in the gate driver to charge the gate up to the final value VGS and turn the
power MOSFET fully on. Its value can be found with simple geometric considerations:

Equation 19
1
E ONHS = --- [ QgsV M + ( Qg + Qgs + Qgd ) ( V GS – V M ) ]
- 2

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AN2644 Power MOSFET driving energy in ZVS operation

The grey-shaded area below the gate charge curve represents the energy lost in the gate
driver to discharge the gate from VGS to zero. Its value can be simply found from the
difference of the total driving energy, represented by the rectangle enclosed by the Q-V axes
and the Qg and VGS lines:

Equation 20
E HS = Qg ⋅ V GS

and EON_HS:

Equation 21
E OFFHS = Qg ⋅ V GS – E ONHS
- -

In case of ZVS, instead, the associated gate-charge curve is the red line. Its slope is equal
to that of the third portion of the normal gate-charge characteristic, because CGD has the
final value since the beginning. By geometrical considerations, the total gate charge QgZ to
provide in this case will be:

Equation 22
V GS
Qg Z = ------------------------- [ Qg – ( Qgs + Qgd ) ]
V GS – V M

while the energy lost in the gate driver to charge the gate up to the final value VGS and turn
the power MOSFET fully on and represented by the red-shaded area will be:

Equation 23
2
1 1 V GS
E ONZVS = --- Qg Z V GS = --- ⋅ ------------------------- [ Qg – ( Qgs + Qgd ) ]
- 2 2 V GS – V M

At turn-off, the Miller effect will be present but to a lower degree. In fact, the operating point
will initially move along the red line until the gate voltage reaches the Miller plateau VM (that
associated to the switched current at turn-off). From that point on, it will move along the
black curve. The energy associated to turn-off will be:

Equation 24
1 2 2
E OFFZVS = ---------------------------------- [ ( V GS + V M ) ( Qg – Qgd ) – V GS ( V GS + V M )Qgs ]
- 2 ( V GS – V M )

and the total driving energy:

Equation 25
1 2 2
E ZVS = ---------------------------------- [ ( 2V GS + V M ) ( Qg – Qgd ) – V GS ( 2V GS + V M )Qgs ]
2 ( V GS – V M )

For the power MOSFET used in the example of Figure 29 (STP14NK60Z), the datasheet
specifies: Qgs = 13.2 nC, Qgd = 38.6 nC, Qg = 75 nC @ VGS = 10 V. Substituting these
values and VM = 5.8 Vin (Equation 19) to (Equation 25) we find: EON_HS = 305 nJ, EHS = 750
nJ, EOFF_HS = 445 nJ, QgZ = 55 nC, EON_ZVS = 276 nJ, EOFF_ZVS = 331 nJ and EZVS = 607
nJ. Then, the total gate charge is decreased by 20 nC (-27%) and the total gate driving
energy by 143 nJ (-19%).

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Resonant transitions of half-bridge midpoint AN2644

Appendix B Resonant transitions of half-bridge midpoint

To analyze the transitions of the half-bridge midpoint node HB when either Q1 or Q2 is

turned off, it is necessary to schematize the equivalent circuit during the transient. For
simplicity only the turn-off of Q2 will be considered, being obvious that the turn-off of Q1 will
be exactly mirror-symmetrical. Different circuits need to be considered, depending on
whether the converter is operated in a DCM mode or a CCM mode. These equivalent
circuits are shown in Figure 30.

Figure 30. Equivalent circuit to analyze the transitions of the half-bridge midpoint
node when Q2 turns off

IR VC IR VC VLs

ON ON

OFF Cr Ls OFF Cr Ls

VHB CHB VL Lp VHB CHB a·(Vout+VF)

t=0 t=0

DCM operation CCM operation

In fact, in the case of DCM operation, since the secondary windings are open, Lp is part of
the circuit and is effectively in series to Ls to form a single inductor Ls+Lp. In CCM
operation, instead, since the secondary windings are conducting there is a constant voltage
equal to ±a·(Vout+VF) across Lp and then this can be replaced by a voltage generator
(placed as shown in Figure 30 in the case under consideration). In either circuit, Q2 is
replaced by an ideal switch that opens at t=0.
Resonant tanks are again involved during the transitions, hence the denomination "resonant
transitions" given to the swings of the node HB. Considering the operation of the LLC
resonant converter in its entirety, then, there are four associated resonant frequencies.
CHB is the total parasitic capacitance of the node HB already discussed in Section 2.2: The
switching mechanism and illustrated in Figure 8 and that will be the topic of the next section.
Note that during the transient Cr and CHB are effectively in series. However, since normally
Cr>>CHB (typically, two orders of magnitude), the combined capacitance will be ≈CHB and
the changes of the VC voltage during the transient can be neglected, so that it is possible to
assume VC = VC(0) during the transient and replace Cr with a constant voltage generator
VC(0).
The value of VC(0) can be determined on the basis of the following considerations. The
value of at the end of the conduction cycle of Q1, VC(Ts/2), is given by:

Equation 26
Ts
1 -------
V C ⎛⎝ -------⎞⎠ = V C ( 0 ) + ------ ∫ 2 I R ( t ) dt
Ts
2 Cr 0

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AN2644 Resonant transitions of half-bridge midpoint

Note that the integral in Equation 26 is the total charge provided to Cr during the conduction
time of Q1, when the converter draws current from the input source. This charge can be
expressed also as the product of the DC input current Iin times the switching period, then:

Equation 27
V C ⎛⎝ -------⎞⎠ = V C ( 0 ) + ------- Ts
Ts Iin
2 Cr

On the other hand, remembering that VC has a DC value equal to Vin/2, for symmetry the
following identity holds true:

Equation 28
Ts V in V in
V C ⎛ -------⎞ – -------- = -------
- – VC ( 0 )
⎝ 2⎠ 2 2
By combination of (Equation 39) and (28) we find:

Equation 29
V C ( 0 ) = --- ⎛ V in – ------- Ts⎞
1 Iin
2⎝ Cr ⎠

V C ⎛ -------⎞ = --- ⎛ V in + ------- Ts⎞

Ts 1 Iin
⎝ 2 ⎠ 2⎝ Cr ⎠

After some algebraic manipulations, it is possible to find that the equations governing the
operation of the circuits in Figure 30 are:

Equation 30
2
⎧ d V HB 1 VC ( 0 )
⎪ ----------------- + -----------------------------------
(
- V HB = -----------------------------------
)
- DCM
HB ( Ls + Lp )
⎪ dt C HB Ls + Lp C
⎨ 2
⎪ d V HB 1 V C ( 0 ) – a ⋅ ( V out + V F )
⎪ ----------------- + -----------------
- V HB = ----------------------------------------------------------
- CCM
⎩ dt C HB Ls C HB Ls

with the following initial conditions:

Equation 31
dV HB IR ( 0 )
V HB ( 0 ) = 0, -------------- = -------------
dt t= 0
C HB

The solutions of these equations are:

Equation 32
⎧ V DD sin ( ω DDt – ϕ DD ) + V C ( 0 ) DCM
V HB ( t ) = ⎨
⎩ V CC sin ( ω CCt – ϕ CC ) + V C ( 0 ) – a ⋅ ( V out + V F ) CCM

with

Equation 33
1 –1 ⎛ VC ( 0 ) C HB ⎞ VC ( 0 ) 1
ω DD= ----------------------------------------, ϕ DD = tan ⎜ ---------------- --------------------⎟ , V DD = -------------------, ω CC = ----------------------,
( Ls + Lp )C HB ⎝ I R ( 0 ) Ls + Lp⎠ sin ϕ DD LsC HB

–1 ⎛ VC ( 0 ) – a ⋅ ( V out + V F ) C HB⎞ V C ( 0 ) – a ⋅ ( V out + V F )

ϕ CC = tan ⎜ ----------------------------------------------------------- -----------⎟ , V CC = -----------------------------------------------------------
⎝ I R ( 0 ) Ls ⎠ sin ϕ CC

51/64
Resonant transitions of half-bridge midpoint AN2644

The expression of the tank current will be:

Equation 34
⎧ IR ( 0 )
⎪ C ⋅ V ⋅ ω DD ⋅ cos ( ω DDt – ω DD) = - cos ( ω DDt – ϕ DD )
-------------------- DCM
dV HB ( t ) ⎪ HB DD cos ω DD
I R ( t ) = C HB --------------------- = ⎨
dt ⎪ IR ( 0 )
⎪ C HB ⋅ V CC ⋅ ω CC ⋅ cos ( ω CC t – ω CC ) = - cos ( ω CC t – ϕ CC )
--------------------
cos ω CC
CCM
⎩

Equations (Equation 30) to (34) apply in the time interval (0, TT), where TT is the time
needed for the voltage VHB to reach Vin. TT can be calculated from (Equation 32) taking (33)
into account; the result is:

Equation 35
⎧ 1- – 1 ⎛ V in – V C ( 0 )⎞
⎪ ---------- ϕ DD + sin ------------------------------ DCM
⎪ ω DD
⎝ V DD ⎠
TT = ⎨
⎪ 1 – 1 ⎛ V in – V C ( 0 ) + a ⋅ ( V out + V F )⎞
- ϕ CC + sin
⎪ ---------- -------------------------------------------------------------------------- CCM
ω ⎝ V CC ⎠
⎩ CC

To achieve ZVS, the value of TT given by (Equation 35) must not exceed the deadtime TD to
make sure that Q1 is turned on with zero drain-to-source voltage.
Note that in CCM operation there may be an additional constraint on the time interval where
equations (Equation 30) to (34) are applicable. The current IR(t) will be described by
Equation 34 either until TT or until it equals the current flowing through Lp (see Figure 9),
whichever condition occurs first. We will assume that IR(t)=I(Lp) occurs after TT.
With the usual values of all the involved quantities, the phase angles ϕCC and ϕDD are both
considerably less than unity, then it is possible to use the approximation ϕ ≈ sin ϕ ≈ tan ϕ
for both of them. With this simplification (Equation 35) can be expressed as:

Equation 36
V in
T T = ------------- C HB
IR ( 0 )

for both CCM and DCM modes, which is equivalent to considering CHB charged by a
constant current IR(0).
Considering that in CCM operation above resonance it is Vin > 2·a·(Vout + VF) and, again,
that VC(0) ≤ Vin/2, ϕCC is always negative. As a result, IR(t) has its peak for negative t values
and decays in (0, TT). In DCM operation, if the input current is lower than a critical value, it is
VC(0) > 0 and, then, ϕDD positive. Thereby, IR(t) has its peak for positive t values, thus it
initially increases and then decays in (0,TT). In this case, which happens at light load and
with no load, the approximation IR(t) = IR(0) is excellent. Still in DCM operation, but with an
input current exceeding that critical value, it is VC(0) < 0 and, then, ϕDD negative, which
happens below resonance at heavy load. However, as compared to what happens in CCM
operation, the associated resonance period is longer, thus the change in IR(t) is lower and
the approximation IR(t) = IR(0) is still good. This is illustrated in Figure 31 and 32.

52/64
AN2644 Resonant transitions of half-bridge midpoint

Figure 31. Voltage of HB node vs time (see Figure 32. Resonant current vs time (see
Equation 32) Equation 34)

In the end, the approximation (Equation 36) provides a relationship that is sufficiently
accurate for design purposes under all operating conditions. Fortunately the conditions
where accuracy is worst (CCM) are not critical as far as ZVS is concerned because the
switched current IR(0) is greater than it is under all other conditions.
To achieve ZVS for both switches, a necessary condition is that TT≤TD. An additional
constraint comes from the condition that the tank current IR has to keep its sign unchanged
during the time interval (0, TD). Should the current become zero in that interval, the body
diode of Q1 would not be forward biased any more and the voltage VHB, no longer
constrained to Vin, would experience oscillations at an angular frequency equal to either
ωDD or ωCC. Q1 would then be turned on with a drain-to-source voltage in general greater
then zero.
In practical cases, when the converter is operated at or above resonance the tank current
crosses zero with a considerable delay after the end of the deadtime, especially in DCM
modes, where the phase lag ϕ described by Equation 5 or 8 or 11 or 13 tends to π /2; hence,
this constraint can be disregarded. It becomes significant when working below resonance
and close to the boundary between the capacitive and the inductive mode (CCMB mode).
Under the assumption TT < TD, in the time interval (TT, TD) Equation 34 no longer apply and
IR is again a portion of sinusoid having frequency fR1, which can be described by an
equation of the type:

Equation 37
I R ( t ) = I Rpk sin ( 2πf R1 t – ϕ )
-

In order for the tank current to keep the same sign during the remainder of the deadtime, the
following condition must be fulfilled:

Equation 38
2πf R1 T D – ϕ > 0

53/64
Power MOSFET effective Coss and half-bridge midpoint's transition times AN2644

Appendix C Power MOSFET effective Coss and half-bridge

midpoint's transition times

Unlike linear capacitors, which have a capacitance value independent of the applied voltage,
power MOSFET Coss is a nonlinear capacitance, i.e. its value is a function of the drain-to-
source voltage VDS. Assuming a p-n step junction for the body-drain diode, with good
approximation the Coss vs. VDS relationship can be expressed as:

Equation 39
C oss ( V DS1 ) V DS2
------------------------------- ≈ -------------
-
C oss ( V DS2 ) V DS1

Power MOSFETs manufacturers usually specify the value of Coss at VDS = 25 V (with VGS=0
at 1 MHZ), From (Equation 39) the Coss at a given voltage VDS will be:

Equation 40
5
25 - = --------------
C oss ( V DS ) = C oss25 ---------- - C oss25
V DS V DS

Generally speaking, Coss has a twofold role in switching losses mechanism in power
MOSFET:
1. at turn-on Coss is discharged and the energy stored in it is dissipated inside the
MOSFET's RDS(on), thus giving origin to the so-called "capacitive losses". This is not
significant in the LLC resonant converter because power MOSFETs are operated in
ZVS and capacitive losses are zero, and then it will not be considered.
2. at turn-off the rate of rise of its voltage determines the voltage-current overlap that
originates switching losses. This is significant in the LLC resonant converter.

Figure 33. Capacitance associated to the half-bridge midpoint node

Q1
Coss1
VDS1

Resonant
HB Driver

Vin Node IR
HB Tank &
Q2
Coss2 Load
VDS2
CStray

It is worth noticing that, although the Coss of the two power MOSFETs in the half-bridge are
effectively connected in parallel, however they experience different VDS voltages at any time.
If Vin is the DC input voltage, and with reference to the circuit shown in Figure 33, the
following relationship holds true:

Equation 41
V DS1 – V DS2 = V in

54/64
AN2644 Power MOSFET effective Coss and half-bridge midpoint's transition times

Then, assuming that the two MOSFETs are identical to one another (so that Coss25-1 =
Coss25-2 = Coss25), and referring to the voltage of the half-bridge midpoint VHB (= VDS2), their
individual Coss will be:

Equation 42
5 5
C oss1 = ------------------ C oss25 = ----------------------------- C oss25
V DS1 V in – V HB

Equation 43
5 5
C oss2 = ------------------ C oss25 = --------------- C oss25
V DS2 V HB

and their instantaneous cumulative value will be:

Equation 44
⎛ 1 1 ⎞
Coss ( V HB ) = C oss1 + C oss2 = 5 ⎜ -------------- -⎟ C oss25
- + ----------------------------
⎝ V HB V in – V HB⎠

The diagram of equations (Equation 43) and (Equation 44) are shown in Figure 34. The
branch-constitutive equation of the capacitor Coss:

Equation 45
dV HB
IC ( t ) = C oss ( V HB ) -------------- ⇒ I C ( t )dt = C oss ( V HB )dV HB
oss dt oss

can be integrated by variable separation.

Figure 34. Coss capacitances vs. half-bridge midpoint's voltage

F 10
3 .10

10
2.25 .10

Coss2 Coss1
10
1.5 .10
Coss

11
7.5 .10
Cstray

0
0 100 200 300 400
VHB (= VDS2) V

55/64
Power MOSFET effective Coss and half-bridge midpoint's transition times AN2644

Figure 35. Simplified schematic to analyze transition times of the node HB when Q2
turns off

Coss1 IR0
DQ1
⎛ t ⎞
IR0 I Q2 = IR0 ⎜⎜1 − ⎟⎟
Vin ⎝ Tf ⎠

⎛ t ⎞
I Q2 = IR0 ⎜⎜1 − ⎟⎟
⎝ Tf ⎠
Coss2 = IR0 – IQ2
CHB (VHB)

CStray

Assuming that VHB|t=0 it is possible to write:

Equation 46
tf V HB
∫ IC oss
( τ ) dτ = ∫ C oss ( V ) dV
0 0

Note that the left-hand side is the total charge Qoss(VHB) supplied to Coss(VHB) to raise its
voltage up to the level VHB. Substituting (Equation 44) in (Equation 46) and developing, it is
possible to find:

Equation 47
Qoss ( V HB ) = 10 ( V HB + V in – V in – V HB )C oss25

Considering again the turn-off of Q2, as a consequence of the discussion of the previous
section, the equivalent schematic of the circuit during the turn-off of Q2 is illustrated in
Figure 35, where the tank circuit is then replaced by a constant current source equal to the
switched current IR0. Additionally, the turn-off of Q2 is assumed to be linear in time:

Equation 48
⎧ ⎛ t-⎞
⎪ I R0 ⎝ 1 – ---- 0 ≤ t≤ T f
I Q2 = ⎨ T ⎠
f
⎪
⎩ 0 t > Tf

where Tf is the time the current IQ2 takes to become zero. The total capacitance of the node
HB will be:

Equation 49
C HB ( V HB ) = C Stray + C oss ( V HB )

CHB will be charged by the current ICHB = IR0 - IQ2 until VHB equals the input voltage Vin and
DQ1 turns on, thus clamping VHB at Vin. Let us assume that the time TT needed for the
voltage of the node HB to reach Vin is greater than Tf. The main quantities during the
transient are illustrated in Figure 36. The total charge QT delivered to CHB in the interval
(0, TT) will be:

Equation 50
T
Q T = --- I R0 T f + I R0 ( T T – T f ) = I R0 ⎛ T T – -----f⎞
1
2 ⎝ 2⎠

56/64
AN2644 Power MOSFET effective Coss and half-bridge midpoint's transition times

Figure 36. Schematization of Q2 turn-off transient

ICHB
QT
IR0

IQ2
t
IR0

VHB
Actual t
Vin
Approx.

Tf TT t

This charge will be partly stored in CStray and partly in Coss. The charge in CStray will
obviously be CStray·Vin, then the one stored in Coss will be given by (Equation 47)
substituting Vin in VHB:

Equation 51
Qoss ( V in ) = 20 V in C oss25

A linear capacitance CHB equivalent to CHB(Vin) will have the same total charge QT stored in
it when its voltage equals Vin. Then it is possible to write:

Equation 52
Q T = C Stray V in + 20 V in C oss25 = C HB V in

which yields:

Equation 53
20
C HB = C Stray + ------------ C oss25
V in

The capacitance value defined by (Equation 53) has to be used in calculations related to
transition time of the node HB, as far as ZVS is concerned.
As previously stated, to achieve ZVS the transition of the node HB must be completed within
the deadtime TD inserted between the transitions from one state to the other of either
switch, that is, TT ≤ TD. Combining (Equation 46) and (Equation 48) and solving for TT:

Equation 54
T C Stray V in + 20 V in C oss25 T C HB V in
T T = -----f + --------------------------------------------------------------------- = -----f + ------------------- ≤ TD
2 I R0 2 I R0

Depending on the data available, (Equation 54) can be used for finding either the minimum
value of IR0 (called IRmin in the text) or the maximum value of CHB or the minimum value of
TD .

57/64
Power MOSFET effective Coss and half-bridge midpoint's transition times AN2644

In datasheets of many power MOSFET manufacturers, it is customary to find an "equivalent

output capacitance" denoted with Cosseq and defined as a constant equivalent capacitance
giving the same charging time as Coss when the drain-to-source voltage VDS increases from
0 to 80% of the rated voltage VDSS.
From the above discussion it is easy to recognize that the linear capacitance equivalent to
the Coss of a single MOSFET charged at a voltage VDS is:

Equation 55
10
C osseq ( V DS ) = --------------- C oss25
V DS

then, as per the above definition:

Equation 56
10 11.2
C osseq = ------------------------------- ⋅ C oss25 ≈ ------------------ C oss25
0.8 ⋅ V DSS V DSS

The actual value provided in the datasheet can be different from the theoretical value given
by (Equation 56), depending on the silicon cell design and density of the particular power
MOSFET. For an assigned power MOSFET, whose Cosseq is specified, by combining with
(Equation 55), equation (Equation 53) can be re-written as:

Equation 57
V DSS
C HB = C Stray + 2 -------------
-C
V in osseq

58/64
AN2644 Power MOSFETs switching losses at turn-off

Appendix D Power MOSFETs switching losses at turn-off

The nonlinearity of Coss (refer to Figure 34) makes the voltage of the node HB increase
slowly at its low values and its high values, and much faster when it is half way in its swing
(see the solid VHB waveform labeled "Actual" in Figure 36). Typically, the current through
either Q1 or Q2 during their respective turn-off transients flows during the initial part of the
transition of the node HB, i.e. when its value is changing more slowly. This reduces the
voltage-current overlap and, consequently, the associated power loss with respect to a
linear capacitor. However, the mathematical expression of the loss is extremely complex,
therefore it is more useful to provide a conservative estimate using the equivalent linear
capacitance CHB defined by (Equation 53). The associated VHB curve is the dotted one
labeled "Approx." in Figure 36 (under the assumption Tf < TT).
Again with reference to the turn-off of Q2, the voltage on the node HB can be found by
integration of the branch-constitutive equation of CHB:

Equation 58
dV HB 1 t 1 t
I C ( t ) = C HB -------------- ⇒ V HB ( t ) = ----------- ∫ I C ( t ) dt = ----------- ∫ [ I R0 – I Q2 ( t ) ] dt
HB dt C HB 0 HB C HB 0

Power loss due to voltage-current overlap (switching loss) will occur only during the time
interval (0, Tf) where IQ2 is non-zero, then (Equation 54) will be considered in this interval
only; substituting (Equation 48) in (Equation 58) we find:

Equation 59
1 t I R0 I R0
V HB ( t ) = ----------- ∫ -------- t dt = ---------------------------- t
2
t∈ (0,Tf)
C HB 0 T f 2 ⋅ C HB ⋅ T f

Note that in the remainder interval (Tf, TT) the voltage VHB will change linearly with time
because charged by the constant current IR0. The energy lost because of voltage-current
overlap will be calculated by integration of the product of (Equation 59) times (Equation 48):

Equation 60
2
t-⎞ dt = (---------------------
I R0 ⋅ T f ) 2
Tf Tf
I Q2 ( t ) ⋅ V HB ( t ) dt = ------------------------ ∫ t ⎛ 1 – ----
I R0
∫0
2
E off ( Q2 ) = -
2C HB ⋅ T f 0 ⎝ T f⎠ 24C HB

Power loss will be obtained multiplying the energy loss given by (Equation 60) by the
operating frequency fsw:

Equation 61
2
( I R0 ⋅ T f )
P off ( Q2 ) = E off ( Q2 )f sw = ------------------------
-
24C HB

The same loss occurs to the high-side power MOSFET Q1 as well, thereby, the total
switching loss will be:

Equation 62
2
( I R0 ⋅ T f )
P off = ------------------------- ⋅ f sw
TOT 12C HB

59/64
Power MOSFETs switching losses at turn-off AN2644

A more accurate analysis could be done observing in Figure 34 that Coss1 (Coss2 in case we
consider Q1's turn-off) changes little during the first portion of the transient, so that it might
be considered constant. With this approach, from (Equation 44) it is possible to assume:

Equation 63
⎛ 1 1 -⎞
C oss ( V HB ) ≈ 5 ⎜ --------------
- + ----------- ⎟ C oss25
⎝ V HB V in⎠

and, from (Equation 49), taking (Equation 63) into account:

Equation 64
⎛ 1 1 -⎞ C
⎟ oss25 = ⎛⎝ C Stray + ------------ Coss 25⎞⎠ + --------------- C oss25
5 5
C HB ( V HB ) ≈ C Stray + 5 ⎜ --------------
- + -----------
⎝ V HB V in⎠ V in V HB

Designating:

Equation 65
5
C HBF = C Stray + ------------ C oss25
- V in

substituting (Equation 64) in (Equation 46), integrating both sides and solving for VHB it is
possible to find:

Equation 66
1 I R0 2 C oss25 ⎛ 2 C HBF I R0 2 ⎞
V HB ( t ) = -------------- -------------- t – 10 ------------------ ⎜ 25 ⋅ C oss25 ----------------------
- - t – 5C ⎟
C HBF 2 ⋅ T F C HBF ⎝ 2 ⋅ TF oss25
⎠
- -

Inserting this result in (Equation 60) and integrating would yield the turn-off energy, however
the result is complex and of little practical use, hence it will not be provided.

60/64
AN2644 Input current in LLC resonant half-bridge with split resonant capacitors

Appendix E Input current in LLC resonant half-bridge with

split resonant capacitors

An interesting property of the LLC resonant half-bridge with split resonant capacitors is the
shape of the input current. Unlike the single capacitor version, where the input current Iin
equals the current through the high-side switch Q1, I(Q1), in this case Iin is given by the
superposition of I(Q1) and the current through the high-side resonant capacitor I(Cr), as
shown in Figure 37.

Figure 37. Input current components in a split-capacitor LLC resonant half-bridge

AM01349v1

The current I(Cr) with the direction defined in Figure 37 is in phase opposition to I(Q1) and
to the current through the series resonant inductor I(Ls); also, its instantaneous amplitude is
half that of I(Ls) since it is equally split between the two resonant capacitors. As a result,
when Q1 is ON, I(Cr) is negative and Iin equals I(Q1) diminished by I(Cr); when Q1 is OFF
and I(Q1)=0, Iin = I(Cr) is positive and provides a continuous input current flow. This is
shown in the timing diagrams of Figure 38.

Figure 38. Timing diagram showing currents flow in the converter of Figure 37

AM01350v1

61/64
Input current in LLC resonant half-bridge with split resonant capacitors AN2644

Note that the input current is the same as in a full-bridge converter, where during each half
switching period there is a conducting path drawing current from the input source.
With the same DC value of Iin, then, the split capacitor configuration makes its peak and
squared rms values are cut in half. Unlike bridge converters, however, the currents I(Q1)
and I(Q2) keep the same value as in the single capacitor half-bridge version.
It is then advantageous to use the split capacitor configuration to reduce not only the ac
current requirements on the resonant capacitors but also the ac current in the input
capacitor and the differential-mode conducted noise. It is then easy to find this solution at
higher power levels but it is advisable to use it also when there is no front-end PFC pre-
regulator. In this case, in fact, the differential-mode noise that the input EMI filter is required
to mitigate is that generated by the resonant half-bridge converter (whereas, with a PFC
front-end the noise generated by this stage would be largely dominant), thus it is possible to
maximally benefit from the reduction of its differential-mode component.

62/64
AN2644 Revision history

Revision history

Table 2. Document revision history

Date Revision Changes

06-May-2008 1 Initial release

Modified: Section 2.1, 2.2, Appendix B
15-Sep-2008 2
Added: Appendix E

63/64
AN2644

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64/64
AN2450
Application note
LLC resonant half-bridge converter design guideline

Silvio De Simone

Introduction
The growing popularity of the LLC resonant converter in its half-bridge implementation (see
Figure 1 on page 4) is due to its high-efficiency, low level of EMI emissions, and its ability to
achieve high power density. Such features perfectly fit the power supply demand of many
modern applications such as LCD and PDP TV or 80+ initiative compliant ATX silver box.
One of the major difficulties that engineers are facing with this topology is the lack of
information concerning the way the converter operates and, therefore, the way to design it in
order to optimize its features.
The purpose of this application note is to provide a detailed quantitative analysis of the
steady state operation of the topology that can be easily translated into a design procedure.
Exact analysis of LLC resonant converters (see 1. of Section 9: Reference on page 34)
leads to a complex model that cannot be easily used to derive a handy design procedure.
R. L. Steigerwald (see 2. of Section 9: Reference) has described a simplified method,
applicable to any resonant topology, based on the assumption that input to output power
transfer is essentially due to the fundamental Fourier series components of currents and
voltages.
This is what is commonly known as the “first harmonic approximation” (FHA) technique,
which enables the analysis of resonant converters by means of classical complex ac circuit
analysis. This is the approach that has been used in this paper.
The same methodology has been used by T. Duerbaum (see 3. of Section 9) who has
highlighted the peculiarities of this topology stemming from its multi-resonant nature.
Although it provides an analysis useful to set up a design procedure, the quantitative aspect
is not fully complete since some practical design constraints, especially those related to soft-
switching, are not addressed. In (see 4. of Section 9) a design procedure that optimizes
transformer's size is given but, again, many other significant aspects of the design are not
considered.
The application note starts with a brief summary of the first harmonic approximation
approach, giving its limitations and highlighting the aspects it cannot predict. Then, the LLC
resonant converter is characterized as a two-port element, considering the input
impedance, and the forward transfer characteristic. The analysis of the input impedance is
useful to determine a necessary condition for Power MOSFETs' ZVS to occur and allows the
designer to predict how conversion efficiency behaves when the load changes from the
maximum to the minimum value. The forward transfer characteristic (see Figure 3 on
page 10) is of great importance to determine the input to output voltage conversion ratio and
provides considerable insight into the converter's operation over the entire range of input
voltage and output load. In particular, it provides a simple graphical means to find the
condition for the converter to regulate the output voltage down to zero load, which is one of
the main benefits of the topology as compared to the traditional series resonant converter.

March 2014 DocID12784 Rev 6 1/35

www.st.com
Contents AN2450

Contents

1 FHA circuit model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Voltage gain and input impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 ZVS constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Operation under overload and short-circuit condition . . . . . . . . . . . . 19

5 Magnetic integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6 Design procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7 Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Electrical test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.1 Efficiency measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2 Resonant stage operating waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2/35 DocID12784 Rev 6

AN2450 List of figures

List of figures

Figure 1. LLC resonant half-bridge converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. FHA resonant circuit two port model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Conversion ratio of LLC resonant half-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Shrinking effect of l value increase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Normalized input impedance magnitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Capacitive and inductive regions in M - fn plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Circuit behavior at ZVS transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Voltage gain characteristics of the LLC resonant tank . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Transformer's physical model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Transformer's APR (all primary referred) model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. Transformer construction: E-cores and slotted bobbin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. LLC resonant half-bridge converter electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13. Circuit efficiency versus output power at various input voltages. . . . . . . . . . . . . . . . . . . . . 30
Figure 14. Resonant circuit primary side waveforms at nominal dc input voltage and full load . . . . . . 31
Figure 15. Resonant circuit primary side waveforms at nominal dc input voltage and light load . . . . . 31
Figure 16. Resonant circuit primary side waveforms at nominal dc input voltage and no-load . . . . . . 32
Figure 17. Resonant circuit primary side waveforms at nominal dc input voltage and light load . . . . . 32
Figure 18. +200 V output diode voltage and current waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19. +75 V output diode voltage and current waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DocID12784 Rev 6 3/35

35
FHA circuit model AN2450

1 FHA circuit model

The FHA approach is based on the assumption that the power transfer from the source to
the load through the resonant tank is almost completely associated to the fundamental
harmonic of the Fourier expansion of the currents and voltages involved. This is consistent
with the selective nature of resonant tank circuits.

Figure 1. LLC resonant half-bridge converter

Input source Controlled Resonant Ideal Uncontrolled Low-pass Load

Switch Network tank transformer rectifier filter

Q1
Half-bridge

Cr Lr
Driver

Vdc n:1 D1 Cout Rout

Irt
Lm Vout
Q2
D2

The harmonics of the switching frequency are then neglected and the tank waveforms are
assumed to be purely sinusoidal at the fundamental frequency: this approach gives quite
accurate results for operating points at and above the resonance frequency of the resonant
tank (in the continuous conduction mode), while it is less accurate, but still valid, at
frequencies below the resonance (in the discontinuous conduction mode).
It is worth pointing out also that many details of circuit operation on a cycle-to-cycle time
base will be lost. In particular, FHA provides only a necessary condition for MOSFETs' zero-
voltage switching (ZVS) and does not address secondary rectifiers' natural ability to work
always in zero-current switching (ZCS). A sufficient condition for Power MOSFETs' ZVS will
be determined in Section 3: ZVS constraints on page 16 still in the frame of FHA approach.
Let us consider the simple case of ideal components, both active and passive.
The two Power MOSFETs of the half-bridge in Figure 1 are driven on and off symmetrically
with 50% duty cycle and no overlapping. Therefore the input voltage to the resonant tank
vsq(t) is a square waveform of amplitude Vdc, with an average value of Vdc/2. In this case the
capacitor Cr acts as both resonant and dc blocking capacitor. As a result, the alternate
voltage across Cr is superimposed to a dc level equal to Vdc/2.
The input voltage waveform vsq(t) of the resonant tank in Figure 1 can be expressed in
Fourier series:

Equation 1
V dc 2 1
v sq  t  = --------- + --- V dc
2   --- sin  n2f sw t 
n
n = 1 3 5. .…

4/35 DocID12784 Rev 6

AN2450 FHA circuit model

whose fundamental component vi.FHA(t) (in phase with the original square waveform) is:

Equation 2
2
v iFHA
.  t  = --- V dc sin  2f sw t 


where fsw is the switching frequency. The rms value Vi.FHA of the input voltage fundamental
component is:

Equation 3
2
v iFHA
. = ------- V dc

As a consequence of the above mentioned assumptions, the resonant tank current irt(t) will
be also sinusoidal, with a certain rms value Irt and a phase shift  with respect to the
fundamental component of the input voltage:

Equation 4
i rt  t  = 2I rt sin  2f sw t –   = 2I rt cos   sin  2f sw t  – 2I rt sin   cos  2f sw t 

This current lags or leads the voltage, depending on whether inductive reactance or
capacitive reactance dominates in the behavior of the resonant tank in the frequency region
of interest. Irrespective of that, irt(t) can be obtained as the sum of two contributes, the first
in phase with the voltage, the second with 90° phase-shift with respect to it.
The dc input current Ii.dc from the dc source can also be found as the average value, along
a complete switching period, of the sinusoidal tank current flowing during the high-side
MOSFET conduction time, when the dc input voltage is applied to the resonant tank:

Equation 5
T sw
---------
2
1 2
I idc
. = ---------
T sw  i rt  t  dt = ------- I rt cos 

0

where Tsw is the time period at switching frequency.

The real power Pin, drawn from the dc input source (equal to the output power Pout in this
ideal case) can now be calculated as both the product of the input dc voltage Vdc times the
average input current Ii.dc and the product of the rms values of the voltage and current's first
harmonic, times cos :

Equation 6
P in = V dc I idc
.
= V iFHA
. I rt cos 

the two expressions are obviously equivalent.

The expression of the apparent power Papp and the reactive power Pr are respectively:

Equation 7
P app = V iFHA
. I rt P r = V iFHA
. I rt sin 

DocID12784 Rev 6 5/35

35
FHA circuit model AN2450

Let us consider now the output rectifiers and filter part. In the real circuit, the rectifiers are
driven by a quasi-sinusoidal current and the voltage reverses when this current becomes
zero; therefore the voltage at the input of the rectifier block is an alternate square wave in
phase with the rectifier current of amplitude Vout.
The expressions of the square wave output voltage vo.sq(t) is:

Equation 8

4 1
.  t  = --- V out
V osq
  --- sin  n2f sw t –  
n
n = 1 3 5. .

which has a fundamental component vo.FHA(t):

Equation 9
4
.  t  = --- Vout sin  2 f sw t –  
V oFHT

whose rms amplitude is:

Equation 10
2 2
V oFHA
. = ----------- V out


where  is the phase shift with respect to the input voltage. The fundamental component of
the rectifier current irect(t) will be:

Equation 11

i rect  t  = 2I rect sin  2 f sw t –  

where Irect is its rms value.

Also in this case we can relate the average output current to the load Iout and also derive the
ac current Ic.ac flowing into the filtering output capacitor:

Equation 12
T sw
---------
2
2 2 2 P out V out
I out = ---------
T sw  i rect  t  dt = ----------- I rect = ----------- = -----------
 V out R out
0

Equation 13

2 2
I cac
. = I rect – I out

where Pout is the output power associated to the output load resistance Rout.
Since vo.FHA(t) and irect(t) are in phase, the rectifier block presents an effective resistive load
to the resonant tank circuit, Ro.ac, equal to the ratio of the instantaneous voltage and
current:

6/35 DocID12784 Rev 6

AN2450 FHA circuit model

Equation 14
v oFHA  t  V oFHA 2
. . 8 V out 8
R oac
. = ----------------------- = ----------------- = -----2- -------------- = -----2- R out
i rect  t  I rect  P out 

Thus, in the end, we have transformed the non linear circuit of Figure 1 into the linear circuit
of Figure 2, where the ac resonant tank is excited by an effective sinusoidal input source
and drives an effective resistive load. This transformation allows the use of complex ac-
analysis methods to study the circuit and, furthermore, to pass from ac to dc parameters
(voltages and currents), since the relationships between them are well-defined and fixed
(see Equation 3, Equation 5, Equation 6, Equation 10 and Equation 12 above).

Figure 2. FHA resonant circuit two port model

H (jȦ)
controlled rectifier &
switch low-pass
network filter
dc input dc output
n :1
Ii.dc Irt Cr Lr Irect Iout

Vdc Lm Ro.ac Rout Vout

Vi.FHA Vo.FHA

Zin (jȦ) ac resonant tank

The ac resonant tank in the two-port model of Figure 2 can be defined by its forward transfer
function H(s) and input impedance Zin(s):

Equation 15
2
V oFHA
.  s  1 n R oac .
 sL m
H  s  = ------------------------- = --- -----------------------------------
V.iFHA  s  n Z in  s 

Equation 16
V.iFHA  s  1 2
Z in  s  = ----------------------- = --------- + sL r + n R oac
.
 sL m
I rt  s  sC r

For the discussion that follows it is convenient to define the effective resistive load reflected
to the primary side of the transformer Rac:

Equation 17
2
R ac = n R oac
.

DocID12784 Rev 6 7/35

35
FHA circuit model AN2450

And the so-called “normalized voltage conversion ratio” or “voltage gain” M(fsw):

Equation 18
V oFHA .
M  f sw  = n H  j2f sw  = n -----------------
V iFHA
.

It can be demonstrated (by applying the relationships of Equation 3, Equation 10 and

Equation 18 to the circuit in Figure 2) that the input to output dc-dc voltage conversion ratio
is equal to:

Equation 19
V out 1
----------- = ------- M  fsw 
V dc 2n

In other words, the voltage conversion ratio is equal to one half the module of resonant
tank's forward transfer function evaluated at the switching frequency.

8/35 DocID12784 Rev 6

AN2450 Voltage gain and input impedance

2 Voltage gain and input impedance

Starting from Equation 18 we can obtain the expression of the voltage gain:

Equation 20
1
M  fn  Q  = ----------------------------------------------------------------------------
  2
 1 2
 1 +  – ------2- + Q  f n – ----
2
 fn  fn

with the following parameter definitions:

1
resonance frequency: f r = -----------------------
2 L r C r

Lr 1
characteristic impedance: Z o = ------ = 2f r L r = -----------------
Cr 2f r C r

Zo Zo 2
 Z 0 P out
quality factor: Q = --------- = ------------------
- = ------ -----2- -------------
-
R ac n R 2 8 n V2
. oac out

L
inductance ratio:  = ------r-
Lm

sw f
normalized frequency: f n = -------
fr

Under no-load conditions, (i.e. Q = 0) the voltage gain assumes the following form:

Equation 21
1
M OL  f n   = -----------------------------

1 +  – ------2-
fn

Figure 3 shows a family of plots of the voltage gain versus normalized frequency. For
different values of Q, with  = 0.2, it is clearly visible that the LLC resonant converter
presents a load-independent operating point at the resonance frequency fr (fn = 1), with
unity gain, where all the curves are tangent (and the tangent line has a slope -2).
Fortunately, this load-independent point occurs in the inductive region of the voltage gain
characteristic, where the resonant tank current lags the input voltage square waveform
(which is a necessary condition for ZVS behavior).
The regulation of the converter output voltage is achieved by changing the switching
frequency of the square waveform at the input of the resonant tank: since the working region
is in the inductive part of the voltage gain characteristic, the frequency control circuit that
keeps the output voltage regulated acts by increasing the frequency in response to a
decrease of the output power demand or to an increase of the input dc voltage. Considering
this, the output voltage can be regulated against wide loads variations with a relatively
narrow switching frequency change, if the converter is operated close to the load-
independent point. Looking at the curves in Figure 3, it is obvious that the wider the input dc
voltage range is, the wider the operating frequency range will be, in which case it is difficult

DocID12784 Rev 6 9/35

35
Voltage gain and input impedance AN2450

to optimize the circuit. This is one of the main drawbacks common to all resonant
topologies.
This is not the case, however, when there is a PFC pre-regulator in front of the LLC
converter, even with a universal input mains voltage (85 Vac - 264 Vac). In this case, in fact,
the input voltage of the resonant converter is a regulated high voltage bus of ~400 Vdc
nominal, with narrow variations in normal operation, while the minimum and maximum
operating voltages will depend, respectively, on the PFC pre-regulator hold-up capability
during mains dips and on the threshold level of its overvoltage protection circuit (about 10 -
15% over the nominal value). Therefore, the resonant converter can be optimized to operate
at the load-independent point when the input voltage is at nominal value, leaving to the step-
up capability of the resonant tank (i.e. operation below resonance) the handling of the
minimum input voltage during mains dips.

Figure 3. Conversion ratio of LLC resonant half-bridge

The red curve in Figure 3 represents the no-load voltage gain curve MOL; for normalized
frequency going to infinity, it tends to an asymptotic value M:

Equation 22
1
M  = M OL  f n     = -------------
1+

Moreover, a second resonance frequency fo can be found, which refers to the no-load
condition or when the secondary side diodes are not conducting (i.e. the condition where the
total primary inductance Lr + Lm resonates with the capacitor Cr); fois defined as:

Equation 23
1 
f o = ----------------------------------------- = f r -------------
2  L r + L m C r 1+

10/35 DocID12784 Rev 6

AN2450 Voltage gain and input impedance

or in normalized form:

Equation 24
fo 
f no = ---- = -------------
fr 1+

At this frequency the no-load gain curve MOL tends to infinity.

By imposing that the minimum required gain Mmin (at max. input dc voltage) is greater than
the asymptotic value M, it is possible to ensure that the converter can work down to no-
load at a finite operating frequency (which will be the maximum operating frequency of the
converter):

Equation 25

V out 1
M min = 2n -------------------  -------------
V dcmax . 1 + 

The maximum required gain Mmax (at min. input dc voltage) at max. output load (max. Pout),
that is at max. Q, will define the min. operating frequency of the converter:

Equation 26
V out
M max = 2n ------------------
V dcmin .

Given the input voltage range (Vdc.min - Vdc.max), three types of operations are possible:
 always below resonance frequency (step-up operations)
 always above resonance frequency (step-down operations)
 across the resonance frequency (shown in Figure 3).
Looking at Figure 4, we can see that an increase of the inductance ratio value  has the
effect of shrinking the gain curves in the M - fn plane toward the resonance frequency fnr
(which means the no-load resonance frequency fno increases) and contemporaneously
reduces the asymptotic level M of the no-load gain characteristic. At the same time the
peak gain of each curve increases.

DocID12784 Rev 6 11/35

35
Voltage gain and input impedance AN2450

Figure 4. Shrinking effect of  value increase

Starting from Equation 16 on page 7 we can obtain the expression of the normalized input
impedance Zn of the resonant tank:

Equation 27
2
Z in  f n  Q  jf n 1 – fn
Z n  f n  Q  = ------------------------------- = -------------------- + ----------------
Zo  + jf n Q jf n

whose magnitude is plotted in Figure 5, at different Q values, with  = 0.2.

The red and blue curves in the above mentioned figure represent the no-load and short-
circuit cases respectively, and are characterized by asymptotes at the two normalized
resonance frequencies fno and fnr (= 1). All the curves at different values of Q intercept at
normalized frequency fn.cross:

Equation 28
2
f ncross
. = ----------------
1 + 2

At frequencies higher than the crossing frequency fn.cross, the input impedance behaves
such that at increasing output current Iout (that is at increasing Pout and Q) it decreases
(coherently to the load resistance); the opposite happens at frequencies lower than fn.cross,
where the input impedance increases, while the output load resistance decreases.

12/35 DocID12784 Rev 6

AN2450 Voltage gain and input impedance

Figure 5. Normalized input impedance magnitude

The ac analysis can also help to estimate converter's efficiency and predict how this
changes with the load. Considering the generic model similar to the one in Figure 2 on
page 7, where the resonant tank includes also the dissipative elements (i.e. series resistors
for magnetic components winding losses and capacitor's ESR, and parallel resistors for
magnetic losses of inductors and transformer), we can compute the transfer function
HLOSS(j) and the input impedance Zin.LOSS(j). By calculating input and output power in
terms of HLOSS and Zin.LOSS, we get:

Equation 29
2
P out H LOSS  j 
 = ----------- = -----------------------------------------------------------
P in R oac . Re  Y inLOSS.
 j  

where Yin.LOSS is the admittance (reciprocal of Zin.LOSS) and the input and output power are
expressed as:

Equation 30
2 1
P in = V iFHA
. I rt cos  = V iFHA
. Re --------------------------------
Z inLOSS. .  j 

Equation 31
2 2
V o  FHA V iFHA . 2
P out = V o  FHA I rect = ----------------------- = ------------------  H LOSS  j 
R o  ac R o  ac

The region on the left-hand side of the diagram in Figure 5, i.e. for a normalized frequency
lower than fno, is the capacitive region, where the tank current leads the half-bridge square
voltage; at normalized frequency higher than the resonance frequency fnr (= 1), on the right-
hand side region, the input impedance is inductive, and the resonant tank current lags the
input voltage. In the region between the two resonance frequencies the impedance can be
either capacitive or inductive, depending on the value of the impedance phase angle.

DocID12784 Rev 6 13/35

35
Voltage gain and input impedance AN2450

By imposing that the imaginary part of Zn(fn, , Q) is zero (which means imposing that Zin
has zero phase angle, as Zo is real and does not affect the phase), we can find the
boundary condition between capacitive and inductive mode operation of the LLC resonant
converter.
The analytical results are the following:

Equation 32

2 2 2 2 2
Q –   1 +   +  Q –   1 +    + 4Q 
f nZ   Q  = ---------------------------------------------------------------------------------------------------------------
2
-
2Q

Equation 33

  2
Q Z  f n   = ---------------2- –  ----
 f n
1 – fn

where fnZ represents the normalized frequency where, for a fixed couple (- Q), the input
resonant tank impedance is real (and only real power is absorbed from the source); while
QZ is the maximum value of the quality factor, below which, at a fixed normalized frequency
and inductance ratio (fn - ) the tank impedance is inductive; hence, the maximum voltage
gain available in that condition is also found:

Equation 34
M MAX   Q  = M  f nZ   Q   Q 

By plotting the locus of operating points [MMAX(, Q), fnZ(,Q)], whose equation on M - fn
plane is the following:

Equation 35
fn
M Z  f n   = ---------------------------------------
2
fn  1 +   – 

we can draw the borderline between capacitive and inductive mode in the region between
the two resonance frequencies, shown in Figure 6. It is also evident that the peak value of
the gain characteristics for a given quality factor Q value, already lies in the capacitive
region.

14/35 DocID12784 Rev 6

AN2450 Voltage gain and input impedance

Figure 6. Capacitive and inductive regions in M - fn plane

Moreover, by equating the second term of (Equation 35) to the maximum required gain
Mmax (at minimum input voltage), and solving for fn, we get the minimum operating
frequency fn.min which allows the required maximum voltage gain at the boundary between
capacitive and inductive mode:

Equation 36
1
f nmin
. = -----------------------------------------------
1 1 
1 + ---  1 – ----------------2- 
 M 
max

Furthermore, by substituting the minimum frequency (Equation 36) into the Equation 33, we
get the maximum quality factor Qmax which allows the required maximum voltage gain at the
boundary between capacitive and inductive mode:

Equation 37
2
 1 M max
Q max = -------------- --- + --------------------------
M max  M 2
max – 1

Finally, by equating the second term of the no-load transfer function (Equation 21 on page 9)
to the minimum required voltage gain Mmin, it is possible to find the expression of the
maximum normalized frequency fn.max:

Equation 38

1
f nmax
. = ------------------------------------------
1 1
1 + --- 1 – -------------
 M min

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35
ZVS constraints AN2450

3 ZVS constraints

The assumption that the working region lies inside the inductive region of operation is only
a necessary condition for the ZVS of the half-bridge MOSFETs, but not sufficient; this is
because the parasitic capacitance of the half-bridge midpoint, neglected in the FHA
analysis, needs energy to be charged and depleted during transitions. In order to
understand ZVS behavior, refer to the half-bridge circuit in Figure 7, where the capacitors
Coss and Cstray are, respectively, the effective drain-source capacitance of the Power
MOSFETs and the total stray capacitance present across the resonant tank impedance, so
that the total capacitance Czvs at node N is:

Equation 39
C zvs = 2C OSS + C stray

which, during transitions, swings by V = Vdc. To allow ZVS, the MOSFET driving circuit is
such that a dead time TD is inserted between the end of the ON-time of either MOSFET and
the beginning of the ON-time of the other one, so that both are not conducting during TD.

Figure 7. Circuit behavior at ZVS transition

V g1

V g2

V sq

V dc
Irt

Izvs

16/35 DocID12784 Rev 6

AN2450 ZVS constraints

Due to the phase lag of the input current with respect to the input voltage, at the end of the
first half cycle the inductor current Irt is still flowing into the circuit and, therefore it can
deplete CZVS so that its voltage swings from V to zero (it will be vice versa during the
second half cycle).
In order to guarantee ZVS, the tank current at the end of the first half cycle (considering the
dead time negligible as compared to the switching period, so that the current change is
negligible as well) must exceed the minimum value necessary to deplete CZVS within the
dead time interval TD, which means:

Equation 40
T sw V V dc
I zvs = i rt  --------- = C zvs ------- =  2C OSS + C stray  ---------
 2  TD TD

This current equals, of course, the peak value of the reactive current flowing through the
resonant tank (it is 90° out-of-phase); the one that determines the reactive power level into
the circuit:

Equation 41
I zvs = 2I rt sin 

Moreover, as the rms component of the tank current associated to the active power is:

Equation 42
P in
I act = I rt cos  = ---------------
V.iFHA

we can derive also the rms value of the resonant tank current and the phase lag  between
input voltage and current (that is the input impedance phase angle at that operating point):

Equation 43
2
2 2 2 2 P in  2 I zvs
 --------------
I rt = I rt cos    + I rt sin    =  V.iFHA- + -----------
2
-

Equation 44
P in
 = a cos  ---------------------
 V iFHA
. I rt

Thus we can write the following analytic expression:

Equation 45
2
Im  Z n  f n  Q   C zvs V dc
tan    = -------------------------------------------  ------------ ------------
Re  Zn  f n  Q   T D P in

which is the sufficient condition for ZVS of the half-bridge Power MOSFETs, to be applied to
the whole operating range. The solution of Equation 45 for the quality factor Qzvs that
ensures ZVS behavior at full load and minimum input voltage is not convenient.

DocID12784 Rev 6 17/35

35
ZVS constraints AN2450

Therefore, we can calculate the Qmax value (at max. output power and min. input voltage),
where the input impedance has zero phase, and take some margin (5% - 10%) by choosing:

Equation 46
%  Q max
. = 90  95
Q zvs1 %

and check that the condition (Equation 45) is satisfied at the end of the process, once the
resonant tank has been completely defined. The process will be iterated if necessary.
Of course the sufficient condition for ZVS needs to be satisfied also at no-load and
maximum input voltage; in this operating condition it is still possible to find an additional
constraint on the maximum quality factor at full load to guarantee ZVS. In fact the input
impedance at no-load Zin.OL has the following expression:

Equation 47
 1 1
.  f n  = jZ o f n  1 + --
Z inOL - – ----
 f n

Taking into account that:

Equation 48
Z o = R ac Q

and writing the sufficient condition for ZVS in this operating condition, that is:

Equation 49
V iFHAmax
. I zvs  Vdcmax 
---------------------------------------  --------------------------------
Z inOL  f nmax .  2

we get the constraint on the quality factor for the ZVS at no-load and maximum input
voltage:

Equation 50
2 f nmax. TD
.  --- -------------------------------------------
Q zvs2 - ----------------------
   + 1 f 2
–  ac C zvs
R
nmax
.

Therefore, in order to guarantee ZVS over the whole operating range of the resonant
converter, we have to choose a maximum quality factor value lower than the smaller of
Qzvs.1 and Qzvs.2.

18/35 DocID12784 Rev 6

AN2450 Operation under overload and short-circuit condition

4 Operation under overload and short-circuit condition

An important aspect to analyze is the converter's behavior during output overload and/or
short-circuit.
Referring to the voltage gain characteristics in Figure 8, let us suppose that the resonant
tank has been designed to operate in the inductive region for a maximum output power
Pout.max (corresponding to the curve Q = Qmax) at a given output-to-input voltage ratio
(corresponding to the horizontal line M = Mx) greater than 1.
When the output power is increased from zero to the maximum value, the gain characteristic
relative to each power level changes progressively from the red curve (Q = 0) to the black
one (Qmax). The control loop keeps the value of M equal to Mx, then the quiescent point
moves along the horizontal line M = Mx and the operating frequency at each load condition
is given by the abscissa of the crossover between the horizontal line M = Mx and the voltage
gain characteristic relevant to the associated value of Q.

Figure 8. Voltage gain characteristics of the LLC resonant tank

If the load is increased over the maximum specified (associated to the curve Q = Qmax)
eventually the converter's operating point will invariably enter the capacitive region, where
hard switching of Power MOSFETs may cause device failures, if no corrective action is
taken.
In fact, for values of Q sufficiently greater than Qmax the intersection with the M = Mx line will
take place on the left-hand side of the borderline curve and, then, in the capacitive region;
moreover, if Q exceeds the value corresponding to the characteristic curve tangent to
M = Mx there will no longer be a possible operating point with M = Mx. This means that the

DocID12784 Rev 6 19/35

35
Operation under overload and short-circuit condition AN2450

converter will no longer be able to keep the output voltage regulated and the output voltage
will fall despite the reduction of the operating frequency (feedback reversal).
Limiting the minimum operating frequency (e.g. at the frequency value corresponding to the
intersection of M = Mx with Q = Qmax) is not enough to prevent the converter from entering
the capacitive region of operation. In fact, as the minimum frequency is reached, from that
point onwards a further load increase will make the operating point move along the vertical
line f = fmin and eventually cross the borderline.
Limiting the minimum operating frequency is effective in preventing capacitive mode
operation only if the minimum (normalized) frequency value is greater than 1. This suggests
that, in response to an overload/short-circuit condition at the output, the converter operating
frequency must be pushed above the resonance frequency (it is better if well above it) in
order to decrease power throughput.
It is worth noticing that, if the converter is specified to deliver a peak output power (where
output voltage regulation is to be maintained) greater than the maximum continuous output
power for a limited time, the resonant tank must be designed for peak output power to make
sure that it will not run in capacitive mode. Of course, its thermal design will consider only
the maximum continuous power.
In any case, whatever the converter specified, short-circuit conditions or, in general,
overload conditions exceeding the maximum specified for the tank circuit, need to be
handled with additional means, such as a current limitation circuit.

20/35 DocID12784 Rev 6

AN2450 Magnetic integration

5 Magnetic integration

The LLC resonant half-bridge is well suited for magnetic integration, i.e. to combine the
inductors as well as the transformer into a single magnetic device. This can be easily
recognized looking at the transformer's physical model in Figure 9, where the topological
analogy with the inductive part of the LLC tank circuit is apparent. However, the real
transformer has leakage inductance on the secondary side as well, which is completely
absent in the model considered so far. To include the effect of secondary leakage in the FHA
analysis, we need a particular transformer model and a simplifying assumption.
It is well known that there are an infinite number of electrically equivalent models of a given
transformer, depending on the choice of the turn ratio of the ideal transformer included in the
model. With an appropriate choice of this “equivalent” turn ratio n (obviously different from
the “physical” turn ratio nt = N1/N2) all the elements related to leakage flux can be located
on the primary side.
This is the APR (all primary referred) model shown in Figure 10, which fits the circuit
considered in the FHA analysis. It is possible to show that the APR model is obtained with
the following choice of n:

Equation 51
L1
n = k ------
L2

with k transformer's coupling coefficient, L1 inductance of the primary winding and L2

inductance of each secondary winding. Note that Lr still has physical meaning: it is the
primary inductance measured with the secondary windings shorted. Note also that the
primary inductance L1 must be unchanged. It is only differently split in the 2 models of
Figure 9 and Figure 10, hence, Lm will be the difference between L1 and Lr.
In the end, the analysis done so far is directly applicable to real-world transformers provided
they are represented by their equivalent APR model. Vice versa, a design flow based on the
FHA analysis will provide the parameters of the APR model; hence, an additional step is
needed to determine those of the physical model. In particular this applies to the turn
number nt, since Lr and Lm still have a connection with the physical world
(Lr + Lm = LL1 + Lµ = L1).

Figure 9. Transformer's physical model

Ideal Transformer LL2a

LL1
nt : 1 : 1
Sec. leakage
inductance
Prim. leakage Lμ
inductance
Sec. leakage
inductance

LL2b
Magnetizing
inductance

DocID12784 Rev 6 21/35

35
Magnetic integration AN2450

Figure 10. Transformer's APR (all primary referred) model

Ideal Transformer
Lr
n:1:1

The problem is mathematically undetermined: there are 5 unknowns (LL1, Lµ, nt, and LL2a,
LL2b) in the physical model and only three parameters in the APR model. The simplifying
assumption that overcomes this issue is that of magnetic circuit symmetry: flux linkage is
assumed to be exactly the same for both primary and secondary windings. This provides the
two missing conditions:

Equation 52
L L1
L L2a = L L2b = --------
2
-
nt

With this assumption it is now possible to find the relationship between n and nt:

Equation 53
Lm + Lr
n t = n ------------------ = n 1 + 
Lm

Figure 11. Transformer construction: E-cores and slotted bobbin

Slotted
bobbin Winding

Separator

Ferrite
E half-cores

Air gap symmetrically

placed between the
windings
Winding

Top view

It is not difficult to find real-world structures where the condition of magnetic symmetry is
quite close to reality. Consider for example the ferrite E-core plus slotted bobbin assembly,
using side-by-side winding arrangement, shown in Figure 11.

22/35 DocID12784 Rev 6

AN2450 Design procedure

6 Design procedure

Based on the analysis presented so far, a step-by-step design procedure of an LLC

resonant converter is now proposed, which fulfills the following design specification and
requires the additional information listed below:
 Design specification:
– Input voltage range: Vdc.min - Vdc.max
– Nominal input voltage: Vdc.nom
– Regulated output voltage: Vout
– Maximum output power: Pout
– Resonant frequency: fr
– Maximum operating frequency: fmax
 Additional info:
– Parasitic capacitance at node N: Czvs
– Dead time of driving circuit: TD
 General criteria for the design:
– The converter will be designed to work at resonance at nominal input voltage.
– The converter must be able to regulate down to zero load at maximum input
voltage.
– The converter will always work in ZVS in the whole operating range.
 10 step procedure:
– Step 1 - to fulfill the first criterion, impose that the required gain at nominal input
voltage equals unity and calculate the transformer turn ratio:

Equation 54
V out 1 V dcnom .
M nom = 2n ------------------- = 1  n = --- -------------------
V dcnom . 2 V out

– Step 2 - calculate the max. and min. required gain at the extreme values of the
input voltage range:

Equation 55

V out
M max = 2n ------------------
V dcmin .

Equation 56
V out
M min = 2n -------------------
V dcmax
.

DocID12784 Rev 6 23/35

35
Design procedure AN2450

– Step 3 - calculate the maximum normalized operating frequency (according to the

definition):

Equation 57
f max
f nmax
. = -----------
fr

– Step 4 - calculate the effective load resistance reflected at transformer primary

side, from Equation 14 on page 7 and Equation 17 on page 7:

Equation 58
2
8 2 V out
R ac = -----2- n --------------
 P out

– Step 5 - impose that the converter operates at maximum frequency at zero load
and maximum input voltage, calculating the inductance ratio from Equation 38 on
page 15:

Equation 59
2
1 – M min f nmax .
 = ---------------------- -------------------------
-
M min f 2
–1
nmax
.

– Step 6 - calculate the max Q value to work in the ZVS operating region at
minimum input voltage and full load condition, from Equation 37 on page 15 and
Equation 46 on page 18:

Equation 60
2
 1 M max
Q zvs1. = 95%  Q max = 95%  -------------- --- + --------------------------
M max  M 2
max – 1

– Step 7 - calculate the max Q value to work in the ZVS operating region at no-load
condition and maximum input voltage, applying Equation 50 on page 18:

Equation 61

2 f nmax . TD
Q zvs2
. = --
- -------------------------------------------
- ----------------------
   + 1 f 2
–  ac C zvs
R
nmax
.

– Step 8 - choose the max quality factor for ZVS in the whole operating range, such
that:

Equation 62

Q zvs  min {Q zvs1

. , Q zvs2
. }

24/35 DocID12784 Rev 6

AN2450 Design procedure

– Step 9 - calculate the minimum operating frequency at full load and minimum input
voltage, according to the following approximate formula:

Equation 63
1
f min = f r -----------------------------------------------------------------
 
 
1 1 
1 + --- 1 – -------------------------------------- -
 Q zvs  4
 ------------
 1 +
 Q max 
-
 M max 

– Step 10 - calculate the characteristic impedance of the resonant tank and all
component values (from definition):

Equation 64
1 Zo Lr
Z o = Q zvs R ac C r = ----------------- L r = ---------- L m = -----
2f r Z o 2f r 

DocID12784 Rev 6 25/35

35
Design example AN2450

7 Design example

Here below, a design example follows for a 400 W resonant converter intended to be
operated with a front-end PFC with a typical regulated bus voltage of about 400 V.
The STMicroelectronics® resonant controller L6599 is particularly suitable for this
application. In fact it incorporates the necessary functions to properly drive the two half-
bridge MOSFETs by a 50 percent fixed duty cycle with a fixed dead-time TD, (between high-
side and low-side MOSFET driving signals), changing the frequency according to the
feedback signal in order to regulate the output voltages against load and input voltage
variations. The main features of the L6599 are a non linear soft-start, a new current
protection mode allowing to program the hiccup mode timing, a dedicated pin for
sequencing or brown-out (pin LINE) and a standby pin (pin STBY) allowing for the burst
mode operation at light load.
The converter specification data are the following:
– Nominal input DC voltage: 390 V
– Input DC voltage range: from 320 to 420 V
– Output voltages: 200 V at 1.6 A continuous current - 75 V at 1.0 A continuous
current
– Resonance frequency: 120 kHz
– Max operating frequency: 150 kHz
– Delay time (L6599 datasheet): 270 ns
– Foreseen half-bridge total stray capacitance (at node N): 350 pF
The calculations have been done assuming that all power is delivered to the 200 V output
voltage. Afterward, once the turn ratio has been defined, the transformer is designed to
deliver the two output voltages, using the correct number of turns and the proper wire
section.
The results of the 10 step procedure are summarized in Table 1:

Table 1. Design results

Step Parameter

1 n = 0.975
Mmax = 1.22
2
Mmin = 0.93
3 fn.max = 1.25
4 Rac = 77.05 Ω
5  = 0.21
6 Qzvs.1 = 0.41
7 Qzvs.2 = 1.01
8 Qzvs = 0.41
9 fmin = 80.6 kHz
Zo = 31.95 Ω Cr = 41.51 nF
10
Lr = 42 μH Lm = 197 μH

26/35 DocID12784 Rev 6

AN2450 Design example

The chosen standard value of the resonant capacitor is 47 nF. The transformer has been
designed using a two slot coil former and integrating both the series inductance Lr and the
shunt inductance Lm, in order to obtain a magnetic component with the following
parameters:
 L p  SO  = L r + L m = 240 H primary inductance (with secondary windings open)

 L p  SS  = L r = 40 H primary inductance with secondary windings shorted

 n t = n  1 +  = 1.08 transformer turn ratio

The number of primary turns has been found experimentally, by measuring the “specific
leakage inductance” (i.e. the leakage inductance per square turns) of a few suitable ferrite
cores, using a two slot winding configuration. The procedure consists of winding a few
layers of turns on both slots of the coil former (same copper area for primary and secondary)
and then measuring the inductance of one winding with the other one short-circuited.
Dividing this measured value by the squared number of turns gives the specific leakage
inductance of the core - coil former construction. The chosen ferrite core is a ER-49-27-17
type, material grade PC44, and the necessary number of primary turns to obtain the
required leakage inductance is 19. Therefore, the total number of secondary turns for 200 V
output is 18 (from the required turn ratio nt).
The secondary side of the transformer consists of two center tap windings, one for each
output, and the two output voltages (+75 V and +200 V) are obtained by series connecting
the two secondary windings on the DC side (refer to the electrical schematic in Figure 12 for
better understanding of circuit configuration). The bottom winding (for +75 V output) has
7 turns, while the top winding consists of 11 (18 - 7) turns.

DocID12784 Rev 6 27/35

35
28/35
Design example

C1
R1

560k
470nF Vdc

BC327
D1 R2
Q2 +200V
C2
LL4148 R5 0R

100nF
47 STP14NK50Z T1 L1 J1
R3 T-RES-ER49-400W D2
R4 1
C3 2k7 0R 2
D3 R6 BYT08P-400 10uH C6 3
Q3 4
470nF U1 22uF/250V 5
R9 L6599 LL4148 R7 0R 6
C7 7
C4 100nF 8
2M2 47 STP14NK50Z 47nF/630V D4 CON8
C5 CSS VBOOT
C8 C9
DELAY HVG BYT08P-400
270pF 100uF/250V 100uF/250V
R8 CF OUT

RFMIN NC R10 JP
16k Vaux D5
STBY VCC
47 STTH1002C L2
LINE R11 ISEN LVG
+75V
LINE GND
10 C12 22uH C14
DIS PFC-STOP C13
4nF7 C10 C11 47uF/100V
220pF/630V D6
10uF/50V 100nF
STTH1002C
R12

150
D7

DocID12784 Rev 6
LL4148 C16 C17
C15 R13 D8
PWM-Latch 220uF/100V 220uF/100V
1uF0 100R LL4148

R14 R15 C18 R16 R17 R18

1k5 10k 10nF 56k 56k 56k

R19 D9 C19 R20 C20

3k3 C-12V 10uF/50V 75k 47nF

R21

U2B U2A R22 R23 R24

1k5 C21
SFH617A-2 1k0 75k 470R
470nF SFH617A-2

R25
C22 R26
220R

47nF 1k0
R27 R28
U3
6k2 2k7

TL431
Figure 12. LLC resonant half-bridge converter electrical schematic
AN2450
AN2450 Electrical test results

8 Electrical test results

8.1 Efficiency measurements

Table 2, Table 3 and Table 4 show the output voltage and current measurements at the
various dc input voltage (nominal 390 Vdc, min 360 Vdc and max 420 Vdc) and several load
conditions. For all measurements, both at full load and at light load operation, the input
power has been measured by a digital power meter (Yokogawa WT-210). Particular
attention has to be paid when measuring input power at full load in order to avoid
measurement errors due to the voltage drop on cables and connections (connecting the
WT-210 voltmeter termination to the board input connector). For the same reason, the
measurements of the output voltages have been taken directly at the output connector, by
using the remote sense option of the active load (Chroma 63108 and 63103) connected to
the outputs.

Table 2. Efficiency measurements at Vin = 390 Vdc

+200 V At load (A) +75 (V) At load (A) Pout (W) Pin (W) Efficiency %

198.76 1.603 76.74 1.010 396.12 408.80 96.90%

198.75 1.300 76.80 0.811 320.66 330.81 96.93%
198.76 1.001 76.87 0.613 246.08 253.90 96.92%
198.79 0.751 76.95 0.414 181.15 187.54 96.59%
198.84 0.500 77.03 0.200 114.83 120.24 95.50%
198.87 0.151 77.06 0.107 38.27 42.70 89.64%

Table 3. Efficiency measurements at Vin = 360 Vdc

+200 V At load (A) +75 (V) At load (A) Pout (W) Pin (W) Efficiency %

198.68 1.603 76.68 1.010 395.93 409.47 96.69%

198.64 1.301 76.74 0.811 320.67 331.26 96.80%
198.62 1.000 76.81 0.613 245.70 254.17 96.67%
198.60 0.751 76.88 0.414 180.98 187.23 96.66%
198.57 0.500 76.94 0.198 114.52 120.43 95.09%
198.57 0.151 76.94 0.107 38.22 43.20 88.46%

DocID12784 Rev 6 29/35

35
Electrical test results AN2450

Table 4. Efficiency measurements at Vin = 420Vdc

+200 V At load (A) +75 (V) At load (A) Pout (W) Pin (W) Efficiency %

198.35 1.601 76.57 1.008 394.74 407.45 96.88%

198.20 1.301 76.55 0.808 319.71 329.70 96.97%
197.87 1.001 76.47 0.609 244.64 252.55 96.87%
196.85 0.750 76.20 0.410 178.88 185.13 96.62%
198.01 0.504 76.74 0.198 114.99 119.78 96.00%
198.67 0.151 76.98 0.107 38.24 41.92 91.21%

The measurements have been done after 30 minutes of warm-up at maximum load. The
circuit efficiency has been calculated at each load condition and input dc voltage and is
plotted in Figure 13, showing very high values at maximum load level, higher than 96.5%.
Also at light load, at an output power of about 10% of the maximum level, the converter
efficiency is very good, reaching a value better than 88% in the whole DC input voltage
range.

Figure 13. Circuit efficiency versus output power at various input voltages

98.00%

97.00%

96.00%

95.00%

94.00%
Efficiency (%)

@ 390 Vdc
93.00% @ 360 Vdc
@ 420 Vdc

92.00%

91.00%

90.00%

89.00%

88.00%
0.00 50.00 100.00 150.00 200.00 250.00 300.00 350.00 400.00 450.00
Output power (W)

8.2 Resonant stage operating waveforms

Figure 14 shows some waveforms during steady state operation of the resonant circuit at
nominal dc input voltage and full load. The Ch1 waveform is the half-bridge square voltage
on pin 14 of the L6599, driving the resonant circuit. The trace Ch2 represents the
transformer primary current flowing into the resonant tank. As shown, it is almost sinusoidal,
because the operating frequency (about 123 kHz) is close to the resonance of the leakage
inductance of the transformer and the resonant capacitor (C6). In this condition the circuit

30/35 DocID12784 Rev 6

AN2450 Electrical test results

has a good margin for ZVS operation, providing good efficiency, while the almost sinusoidal
current waveform just allows for an extremely low EMI generation.

Figure 14. Resonant circuit primary side waveforms at nominal dc input voltage and
full load

Ch1: half-bridge square voltage

Ch2: resonant tank current
Ch3: +200 V output voltage

Figure 15 and Figure 16 show the same waveforms as Figure 14 with both outputs lightly
loaded (50 mA each) and not loaded, respectively. These graphs demonstrate the ability of
the converter to operate down to zero load, with the output voltages still within regulation
limits (as can be seen looking at Ch3 waveform, representing the +200 V output voltage).
The resonant tank current, in this load condition, assumes, obviously, an almost triangular
shape and represents the magnetizing current flowing into the transformer primary side.

Figure 15. Resonant circuit primary side waveforms at nominal dc input voltage and
light load

Ch1: half-bridge square voltage

Ch2: resonant tank current
Ch3: +200 V output voltage

DocID12784 Rev 6 31/35

35
Electrical test results AN2450

Figure 16. Resonant circuit primary side waveforms at nominal dc input voltage and
no-load

Ch1: half-bridge square voltage

Ch2: resonant tank current
Ch3: +200 V output voltage

In Figure 17, the Ch1 waveform shows a detail of the half-bridge square voltage (directly
taken across pin 14 and pin 10 of L6599 controller) to highlight the softness of voltage edge,
without abrupt negative voltage spikes that would be generated in presence of large stray
inductance of wiring. The layout is very critical in this respect and needs to be optimized in
order to minimize this effect, which could damage the controller itself.
In Figure 18 and Figure 19, waveforms relevant to the secondary side are represented. The
rectifiers reverse voltage is measured by CH1 (for both +200 V and +75 V outputs) and the
peak-to-peak value is indicated on the right of the graph. Waveform CH2 shows the current
flowing into one of the two output diodes for each output voltage (respectively D6 and D8).
Also this current shape is almost a sine wave, whose average value is one half the output
current.

Figure 17. Resonant circuit primary side waveforms at nominal dc input voltage and
light load

Ch1: half-bridge square voltage

(between pin 14 and 10 of L6599)
Ch2: resonant tank current
Ch3: low-side MOSFET gate
drive signal

32/35 DocID12784 Rev 6

AN2450 Electrical test results

Figure 18. +200 V output diode voltage and current waveforms

+200 V output waveforms:

Ch1: +200 V diode reverse voltage
Ch2: diode D6 current

Figure 19. +75 V output diode voltage and current waveforms

+75 V output waveforms:

Ch1: resonant tank current
Ch2: diode D8 current

DocID12784 Rev 6 33/35

35
Reference AN2450

9 Reference

1. Steady-state Analysis of the LLC Resonant Converter, Applied Power Electronics

Conference and Exposition, 2001. APEC 2001. Pages: 728 - 735
2. A Comparison of Half Bridge Resonant Converter Topologies, IEEE Trans. on Power
Electronics, 1988. Pages: 174 - 182.
3. First harmonic approximation including design constraints, Telecommunications
Energy Conference, 1998. INTELEC. Pages: 321 - 328
4. Design Optimization for an LCL-Type Series Resonant Converter, see
www.powerpulse.net.
5. L6599 High-voltage resonant controller datasheet, STMicroelectronics

10 Revision history

Table 5. Document revision history

Date Revision Changes

11-Jan-2007 1 First issue

06-Mar-2007 2 Minor text change
26-Mar-2007 3 Equation 53 modified
24-Jul-2007 4 Quality factor (Q) modified
25-Oct-2007 5 Modified: Equation 14 and Equation 33
Updated Equation 31 on page 13 (added “2” to “||HLOSS(j)||”).
17-Mar-2014 6 Updated cross-references throughout document.
Minor modifications throughout document.

34/35 DocID12784 Rev 6

AN2450

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DocID12784 Rev 6 35/35

35
Design Considerations for an LLC Resonant Converter
Hangseok Choi
Fairchild Semiconductor
82-3, Dodang-dong, Wonmi-gu
Bucheon-si, Gyeonggi-do, Korea

Abstract: Recently, the LLC resonant converter has drawn circulating current. This makes it difficult to apply parallel
a lot of attention due to its advantages over the conventional resonant topologies in high power applications.
series resonant converter and parallel resonant converter:
narrow frequency variation over wide load and input variation
and Zero Voltage Switching (ZVS) of the switches for entire
Q1 resonant network
load range. This paper presents an analysis and reviews
practical design considerations for the LLC-type resonant Ip
Vin n:1
converter. It includes designing the transformer and selecting Vd +
Lr Ro
the components. The step-by-step design procedure explained
Q2 VO
with a design example will help engineers design the LLC
resonant converter easily. Lm -
Ids2 Cr

I. INTRODUCTION Fig.1. Half-bridge series resonant (SR) converter

The growing demand for higher power density and low
profile in power converter designs has forced designers to
increase switching frequencies. Operation at higher
frequencies considerably reduces the size of passive Q1 resonant network
components such as transformers and filters. However, Ip
switching losses have been an obstacle to high frequency Vin n:1
operation. In order to reduce switching losses, allowing high Vd +
Llkp Ro
frequency operation, resonant switching techniques have been Q2 VO
developed [1-7]. These techniques process power in a Cr
sinusoidal manner and the switching devices are softly -
Ids2
commutated. Therefore, the switching losses and noise can be
dramatically reduced. Conventional resonant converters use an
Fig.2. Half-bridge parallel resonant (PR) converter
inductor in series with a capacitor as a resonant network. Two
basic configurations are possible for the load connection;
series connection and parallel connections.
For the series resonant converter (SRC), the rectifier-load In order to solve the limitations of the conventional resonant
network is placed in series with the L-C resonant network as converters, the LLC resonant converter has been proposed [8-
depicted in Fig.1 [2-4]. From this configuration, the resonant 12]. The LLC-type resonant converter has many advantages
network and the load act as a voltage divider. By changing the over conventional resonant converters. First, it can regulate
frequency of driving voltage Vd, the impedance of the the output over wide line and load variations with a relatively
resonant network changes. The input voltage will be split small variation of switching frequency. Second, it can achieve
between this impedance and the reflected load. Since it is a zero voltage switching (ZVS) over the entire operating range.
voltage divider, the DC gain of an SRC is always lower than 1. Finally, all essential parasitic elements, including junction
At light load condition, the impedance of the load will be very capacitances of all semiconductor devices and the leakage
large compared to the impedance of the resonant network; all inductance and magnetizing inductance of the transformer, are
the input voltage will be imposed on the load. This makes it utilized to achieve ZVS.
difficult to regulate the output at light load. Theoretically, This paper presents an analysis and design considerations
frequency should be infinite to regulate the output at no load. for a half-bridge LLC resonant converter. Using the
fundamental approximation, the voltage and current
For parallel resonant converter, the rectifier-load network
waveforms are analyzed and the gain equations are obtained.
is placed in parallel with the resonant capacitor as depicted in
A design for DC/DC converter with 120W/24V output has
Fig. 2 [5-7]. Since the load is connected in parallel with the
been selected as a typical example for describing the design
resonant network, there inevitably exists large amount of
procedure.

A-1 Fairchild Power Seminar 2007

II. OPERATION PRINCIPLES AND FUNDAMENTAL
APPROXIMATION Ip
Fig. 3 shows the simplified schematic of half-bridge LLC
resonant converter and Fig. 4 shows its typical waveforms. In Im
Fig. 3, Lm is the transformer magnetizing inductance and Llkp
and Llks are the leakage inductances on the transformer
primary and secondary sides respectively. Operation of the
Ids2
LLC resonant converter is similar to that of the conventional
LC series resonant converter. The only difference is that the
value of the magnetizing inductance is relatively small and
therefore the resonance between Lm+Llkp and Cr affects the
converter operation. Since the magnetizing inductor is ID
relatively small, there exists considerable amount of
magnetizing current (Im) as illustrated in Fig. 4. Vin
In general, the LLC resonant topology consists of three Vd
stages as shown in Fig. 3; square wave generator, resonant (Vds2)
network and rectifier network.
- The square wave generator produces a square wave voltage,
Vd by driving switches, Q1 and Q2 with alternating 50% Vgs1
duty cycle for each switch. The square wave generator
stage can be built as a full-bridge or half bridge type. Vgs2
- The resonant network consists of a capacitor, leakage
inductances and the magnetizing inductance of the Fig. 4. Typical waveforms of half-bridge LLC resonant converter
transformer. The resonant network filters the higher
harmonic currents. Thus, essentially only sinusoidal The filtering action of the resonant network allows us to use
the classical fundamental approximation to obtain the voltage
current is allowed to flow through the resonant network
gain of the resonant converter, which assumes that only the
even though a square wave voltage is applied to the
fundamental component of the square-wave voltage input to
resonant network. The current (Ip) lags the voltage applied
the resonant network contributes to the power transfer to the
to the resonant network (that is, the fundamental output. Because the rectifier circuit in the secondary side acts
component of the square wave voltage (Vd) applied to the as an impedance transformer, the equivalent load resistance is
half-bridge totem pole), which allows the MOSFET’s to be different from actual load resistance. Fig. 5 shows how this
turned on with zero voltage. As can be seen in Fig. 4, the equivalent load resistance is derived. The primary side circuit
MOSFET turns on while the current is flowing through the is replaced by a sinusoidal current source, Iac and a square
anti-parallel diode and the voltage across the MOSFET is wave of voltage, VRI appears at the input to the rectifier. Since
zero. the average of Iac is the output current, Io, Iac is obtained as
- The rectifier network produces DC voltage by rectifying
π ⋅ Io
the AC current with rectifier diodes and capacitor. The I ac = sin(ωt ) (1)
rectifier network can be implemented as a full-wave bridge 2
or center-tapped configuration with capacitive output filter. And VRI is given as
VRI = +Vo if sin(ωt ) > 0
Square wave generator (2)
VRI = −Vo if sin(ωt ) < 0

Q1 resonant network Rectifier network where Vo is the output voltage.

Vin
Ip Io Then, the fundamental component of VRI is given as
n:1 ID
4V
Vd
Ro
+ VRI F = o sin(ωt ) (3)
Llkp Llks π
Q2 VO
Im Since harmonic components of VRI are not involved in the
Lm - power transfer, AC equivalent load resistance can be
Ids2 Cr calculated by dividing VRIF by Iac as

VRI F 8 V 8
Rac = = 2 o = 2 Ro (4)
Fig. 3. A schematic of half-bridge LLC resonant converter I ac π Io π

A-2 Fairchild Power Seminar 2007

Considering the transformer turns ration (n=Np/Ns), the With the equivalent load resistance obtained in (5), the
equivalent load resistance shown in the primary side is characteristics of the LLC resonant converter can be derived.
obtained as Using the AC equivalent circuit of Fig. 6, the voltage gain, M
8n
2 is obtained as
Rac = Ro (5) 4n ⋅Vo
π
2 sin(ωt )
VRO F n ⋅VRI F π 2n ⋅Vo
By using the equivalent load resistance, the AC equivalent M= F = = =
Vd Vd F 4 Vin
sin(ωt ) Vin
circuit is obtained as illustrated in Fig. 6, where VdF and VROF
π 2 (6)
are the fundamental components of the driving voltage, Vd and
reflected output voltage, VRO (nVRI), respectively.
ω 2 Lm Rac Cr
=
ω 2
ω2
pk jω ⋅ (1 − ) ⋅ ( L + n 2
L ) + R (1 − )
I ac ωo 2 m lks ac
ωp2
Io where
8n 2
Rac = Ro
π2
+
1 1
Iac + ωo = , ωp =
VRI VO Lr Cr L p Cr
Ro
L p = Lm + Llkp , Lr = Llkp + Lm //( n 2 Llks )
- -
As can be seen in (6), there are two resonant frequencies.
One is determined by Lr and Cr while the other is determined
by Lp and Cr. In actual transformer, Lp and Lr can be measured
π ⋅ Io in the primary side with the secondary side winding open
Iac I ac = sin( wt )
2 circuited and short circuited, respectively.
VRIF One important point that should be observed in (6) is that
Vo the gain is fixed at resonant frequency (ωo) regardless of the
4Vo
VRI VRI F = sin( wt ) load variation, which is given as
π
Lm L + n 2 Llks
@ ω =ωo = = m
M (7)
L p − Lr Lm
Fig. 5 Derivation of equivalent Load resistance Rac

Without considering the leakage inductance in the

transformer secondary side, the gain in (7) becomes unity. In
Vd Cr Llkp Llks
+ previous research, the leakage inductance in the transformer
+ + VO secondary side was ignored to simplify the gain equation [8-
Vin
12]. However, as observed, there exists considerable error
Lm VRI
when ignoring the leakage inductance in the transformer
- Ro secondary side, which generally results in an incorrect design.
-
n:1 - By assuming that Llkp=n2Llks, the gain in (6) can be
simplified as
8n 2
Rac = Ro ω2 k
π2 2n ⋅VO
( 2)
ωp k +1 (8)
n2Llks M= =
Vin ω ω 2
( k + 1) 2
ω 2
j ( ) ⋅ (1 − 2 ) ⋅ Q + (1 − 2 )
ωo ωo 2k + 1 ωp
+ Cr Llkp +
VROF where Lm (9)
k=
VdF Rac F) Llkp
Lm (nVRI
- - Lr / Cr (10)
Q=
Rac
Fig. 6 AC equivalent circuit for LLC resonant converter
The gain at the resonant frequency (ωo) of (7) can be also
simplified in terms of k as

A-3 Fairchild Power Seminar 2007

Lm + n 2 Llks Lm + Llkp k + 1 around the resonant frequency, fo. This is a distinct advantage
M @ω =ωo = = = (11) of LLC-type resonant converter over the conventional series-
Lm Lm k
resonant converter. Therefore, it is natural to operate the
converter around the resonant frequency to minimize the
While the gain is expressed in terms of k in (8), a gain switching frequency variation at light load conditions.
expressed with Lp and Lr is preferred when handling an actual
transformer since these values can be easily measured with a The operating range of the LLC resonant converter is limited
transformer. Expressing Lp and Lr in terms of k, we can obtain by the peak gain (attainable maximum gain), which is
indicated with ‘*’ in Fig. 8. It should be noticed that the peak
voltage gain does not occur at fo nor fp. The peak gain
Lp = Lm + Llkp = (k + 1) Llkp (12)
frequency where the peak gain is obtained exists between fp
k and fo as shown in Fig. 8. As Q decreases (as load decreases),
Lr = Llkp + Lm // Llkp = Llkp (1 + ) (13)
k +1 the peak gain frequency moves to fp and higher peak gain is
obtained. Meanwhile, as Q increases (as load increases), the
Using (12) and (13), (8) becomes peak gain frequency moves to fo and the peak gain drops. Thus,
the full load condition should be the worst case for the
ω 2 L p − Lr
( ) resonant network design.
2n ⋅ VO ωp2 Lp (14)
M= = Another important factor that determines the peak gain is the
Vin ω ω2 L ω2
j ( ) ⋅ (1 − 2 ) ⋅ Q p + (1 − 2 ) ratio between Lm and Llkp which is defined as k in (9). Even
ωo ωo Lr ωp
though the peak gain at a given condition can be obtained by
using the gain in (8), it is difficult to express the peak gain in
(11) can be also expressed in terms of Lp and Lr as explicit form. Moreover, the gain obtained from (8) has some
error at frequencies below the resonant frequency (fo) due to
k +1 Lp
M @ω =ωo = = (15) the fundamental approximation. In order to simplify the
k Lp − Lr analysis and design, the peak gains are obtained using
simulation tool and depicted in Fig. 9, which shows how the
By using the gain at the resonant frequency of (15) as a virtual peak gain (attainable maximum gain) varies with Q for
gain of the transformer, the AC equivalent circuit of LLC different k values. It appears that higher peak gain can be
resonant converter of Fig. 6 can be simplified in terms of Lp obtained by reducing k or Q values. With a given resonant
and Lr as shown in Fig. 7. frequency (fo) and Q value, decreasing k means reducing the
magnetizing inductance, which results in increased circulating
Llks current. Accordingly, there is a trade-off between the available
Vd Cr Llkp + gain range and conduction loss.
+ VO
Vin +
VRI LLC resonant C onverter
Lm
fp fo
- Ro 2.0
-
n:1 Lr / Cr
-
Q=0.2 Q=
Lr = Llkp + Lm //(n Llks ) 2
1.8
Rac

= Llkp + Lm // Llkp Q= 1

Lp 1.6 Q = 0.8
Lp = Llkp + Lm 1:
L p − Lr Q = 0.6

1.4 Q = 0.4
ideal
+ +
G ain

Lr transform er Q = 0.2
Cr
Rac VROF
VinF Lp-Lr 1.2
(nVRIF)
- - Q=1
1.0

Fig. 7 Simplified AC equivalent circuit for LLC resonant converter

k +1 Lp
0.8 M= =
k Lp − Lr

The gain of (8) is plotted in Fig. 8 for different Q values with 0.6
40 50 60 70 80 90 100 110 120 130 140
k=5, fo=100kHz and fp=55kHz. As observed in Fig. 8, the LLC
freq (kH z)
resonant converter shows characteristics which are almost Fig. 8 Typical gain curves of LLC resonant converter
independent of the load when the switching frequency is (k=5 and fo=100kHz)

A-4 Fairchild Power Seminar 2007

[STEP-1] Define the system specifications

As a first step, the following specification should be defined.

2.4
-Estimated efficiency (Eff): The power conversion efficiency
must be estimated to calculate the maximum input power with
2.2 a given maximum output power. If no reference data is
available, use Eff = 0.88~0.92 for low voltage output
applications and Eff = 0.92~0.96 for high voltage output
2.0
applications. With the estimated efficiency, the maximum
k=1.5 input power is given as
Peak Gain

1.8
Po
k=1.75
Pin = (16)
k=2 E ff
1.6

k=2.5 -Input voltage range (Vinmin and Vinmax) : Typically, it is

1.4 k=3 assumed that the input voltage is provided from Power Factor
Correction (PFC) pre-regulator output. When the input voltage
k=4
is supplied from PFC output, the minimum input voltage
k=5
1.2
k=7 considering the hold-up time requirement is given as
k=9
2 PinTHU
1 Vin min = VO. PFC 2 − (17)
0.2 0.4 0.6 0.8 1 1.2 1.4 CDL
Q
where VO.PFC is the nominal PFC output voltage, THU is a hold
Fig. 9 peak gain (attainable maximum gain) versus Q for different k up time and CDL is the DC link bulk capacitor.
values The maximum input voltage is given as

Vin max = VO. PFC (18)

(Design Example) Assuming the efficiency is 95%,

III. DESIGN PROCEDURE Po 120
Pin = = = 126W
In this section, a design procedure is presented using the E ff 0.95
schematic of Fig.10 as a reference. A dc/dc converter with
2 PinTHU
125W/24V output has been selected as a design example. The Vin min = VO. PFC 2 −
design specifications are as follows: CDL
- Input voltage: 380Vdc (output of PFC stage) 2 ⋅126 ⋅17 × 10−3
- Output: 24V/5A (120W) = 3802 − = 319V
100 ×10−6
- Holdup time requirement: 17ms
- DC link capacitor of PFC output: 100uF Vin max = VO.PFC = 380V

[STEP-2] Determine the maximum and minimum voltage

PFC DC/DC gains of the resonant network

ID
As discussed in the previous section, it is typical to operate the
Q1
Ip
LLC resonant converter around the resonant frequency (fo) in
VDL Np:Ns normal operation to minimize switching frequency variation.
Vd VO
Llkp Llks + Ro When the input voltage is supplied from the PFC output, the
CDL Q2 Im input voltage has the maximum value (nominal PFC output
Lm -
voltage) in normal operation. Designing the converter to
Ids2 Cr
operate at fo for the maximum input voltage condition, the
minimum gain should occur at the resonant frequency (fo). As
Fig.10 Schematic of half-bridge LLC resonant converter with power observed in (11), the gain at fo is a function of the ratio
factor pre-regulator (k=Lm/Llkp) between the magnetizing inductance and primary

A-5 Fairchild Power Seminar 2007

side leakage inductance. Thus, the value of k should be chosen
to obtain the minimum gain. While a higher peak gain can be (Design Example)
obtained with a small k value, too small k value results in poor
coupling of the transformer and deteriorates the efficiency. It Np Vin max 380
is typical to set k to be 5~10, which results in a gain of 1.1~1.2 n= = ⋅ M min = ⋅1.14 = 8.6
Ns 2(Vo + 2VF ) 2(24 + 2 ⋅ 0.6)
at the resonant frequency (fo).
With the chosen k value, the minimum voltage gain for
maximum input voltage (Vinmax) is obtained as
[STEP-4] Calculate the equivalent load resistance (Rac)
VRO L + n Llks 2
Lm + Llkp k +1 With the transformer turns ratio obtained from (21), the
M min = = m = = (19)
Vin max Lm Lm k equivalent load resistance is obtained as
2 8n 2 Vo 2
Rac = E ff (22)
Then, the maximum voltage gain is given as π 2 Po
Vin max min
M max = M (20) (Design Example)
Vin min
8n 2 Vo 2 8 ⋅ 8.62 ⋅ 242
Rac = = = 288Ω
π 2 Po π 2 ⋅120
(Design Example) The ratio (k) between Lm and Llkp is
chosen as 7, which results in the minimum and maximum
gains as
VRO k +1 7 +1
M min = max
= = = 1.14 [STEP-5] Design the resonant network
Vin 2 k 7
With k chosen in STEP-2, read proper Q value from the peak
V max 380 gain curves in Fig. 9 that results in enough peak gain. 10~15%
M max = in min M min = ⋅1.14 = 1.36 margin on the peak gain is typical.
Vin 319
Then, the resonant parameters are obtained as
Gain (M) 1
Peak gain (available maximum gain) Cr = (23)
2π Q ⋅ f o ⋅ Rac
1.36 for Vinmin 1
Mmax Lr = (24)
(2π f o ) 2 Cr
(k + 1) 2
Lp = Lr (25)
1.14 (2k + 1)
Mmin for Vinmax
(Design Example)
As calculated in STEP-2, the maximum voltage gain
k +1 (Mmax) for the minimum input voltage (Vinmin) is 1.36. With
M= = 1.14
k 10% margin, a peak gain of 1.5 is required. k has been
chosen as 7 in STEP-2 and Q is obtained as 0.43 from the
fs peak gain curves in Fig. 12. By selecting the resonant
fo frequency as 85kHz, the resonant components are
Fig. 11 Maximum gain and minimum gain determined as
1 1
Cr = =
2π Q ⋅ f o ⋅ Rac 2π ⋅ 0.43 ⋅ 85 × 103 ⋅ 288
[STEP-3] Determine the transformer turns ratio (n=Np/Ns)
= 15nF
Since the full-wave bridge rectifier is used for the rectifier
1 1
network, the transformer turns ratio is given as Lr = =
(2π f o ) Cr (2π ⋅ 85 ×103 ) 2 ⋅15 ×10 −9
2

Np Vin max = 234uH

n= = ⋅ M min (21)
Ns 2(Vo + 2VF ) (k + 1)2
Lp = Lr = 998uH
where VF is the secondary side rectifier diode voltage drop. (2k + 1)

A-6 Fairchild Power Seminar 2007

(Design Example) EER3541 core (Ae=107mm2) is
2.4
selected for the transformer. From the gain curve of
Fig .13, the minimum switching frequency is obtained as
66kHz. Then, the minimum primary side turns of the
2.2 transformer is given as
n(Vo + 2VF ) ×106
N p min =
2.0 2 f s min ∆B ⋅ Ae
8.6 × 25.2
k=1.5
= = 51.1 turns
Peak Gain

1.8 2 ⋅ 66 ×103 ⋅ 0.3 ⋅107 ×10−6

k=1.75
∴ N p = n ⋅ N s = 8.6 × 6 = 51.6 > N p min
k=2
1.6

k=2.5 Choosing Ns as 6 turns, Np is given as

1.4 k=3 N p = n ⋅ N s = 8.6 × 6 = 51.6 ⇒ 52 > N p min
k=4
k=5
1.2
k=7
k=9
1
0.2 0.4 0.6 0.8 1 1.2 1.4

Fig. 12 Resonant network design using the peak gain (attainable

maximum gain) curve for k=7

[STEP-6] Design the transformer

The worst case for the transformer design is the minimum

switching frequency condition, which occurs at the minimum
input voltage and full load condition. To obtain the minimum
switching frequency, plot the gain curve using the gain
equation of (8) and read the minimum switching frequency.
Then, the minimum number of turns for the transformer Fig. 13 Gain curve
primary side is obtained as
n(Vo + 2VF )
N p min = (26) [STEP-7] Transformer Construction
2 f s min ⋅ ∆B ⋅ Ae Parameters Lp and Lr of the transformer were determined in
STEP-5. Lp and Lr can be measured in the primary side with
where Ae is the cross-sectional area of the transformer core in the secondary side winding open circuited and short circuited,
m2 and ∆B is the maximum flux density swing in Tesla. If respectively. Since LLC converter design requires a relatively
there is no reference data, use ∆B =0.25~0.30 T. large Lr, a sectional bobbin is typically used as shown in
Figure 14 to obtain the desired Lr value. For a sectional bobbin,
Then, choose the proper number of turns for the secondary the number of turns and winding configuration are the major
side that results in primary side turns larger than Npmin as factors determining the value of Lr, while the gap length of the
core does not affect Lr much. Whereas, Lp can be easily
N p = n ⋅ N s > N p min (27) controlled by adjusting the gap length. Table 1 shows
measured Lp and Lr values with different gap lengths. With a
gap length of 0.15mm, the desired Lp and Lr values are
obtained.

A-7 Fairchild Power Seminar 2007

(Design Example)

Np=52T Ns1=Ns2=7T π Io n(Vo + 2 ⋅ VF )

I Cr RMS ≅ [ ]2 + [ ]2
Bifilar 2 2n 4 2 f o Lm
π ⋅5 8.6 ⋅ (24 + 1.2)
= [ ]2 + [ −6
]2
2 2 ⋅ 8.6 4 2 ⋅ 873 ×10 ⋅ 85 ×103

= 0.87 A
Vin max 2 ⋅ I Cr RMS
Fig. 14 Sectional bobbin VCr max ≅ +
2 2 ⋅ π ⋅ fo ⋅ Cr
380 2 ⋅ 0.916
= + = 343V
Table. 1 Measured Lp and Lr with different gap lengths 2 2 ⋅ π ⋅ 85 ×103 ⋅15 ×10−9
Gap length Lp Lr
0.0 mm 5,669 µH 237 µH
0.05 mm 2,105 µH 235 µH
IV. CONCLUSION
0.10 mm 1,401 µH 233 µH
0.15 mm 1,065 µH 230 µH
0.20 mm 890 µH 225 µH This paper has presented the design of an LLC resonant
0.25 mm 788 µH 224 µH converter utilizing the leakage inductance and magnetizing
0.30 mm 665 µH 223 µH inductance of transformer as resonant components. The
0.35 mm 623 µH 222 µH leakage inductance in the transformer secondary side was also
considered in the gain equation.

Even though the integrated transformer approach in LLC

resonant converter design can implement the magnetic
V. REFERENCES
components in a single core and save one magnetic
component, the value of Lr is not easy to control in real
transformer design. Thus, the resonant network design [1] Robert L. Steigerwald, “A Comparison of Half-bridge resonant
sometimes requires iteration with an actual Lr value after the converter topologies,” IEEE Transactions on Power Electronics,
Vol. 3, No. 2, April 1988.
transformer is actually built. Or, an additional resonant [2] A. F. Witulski and R. W. Erickson, “Design of the series resonant
inductor can be added in series with the resonance capacitor to converter for minimum stress,” IEEE Transactions on Aerosp.
obtain the desired Lr value. Electron. Syst., Vol. AES-22, pp. 356-363, July 1986
[3] R. Oruganti, J. Yang, and F.C. Lee, “Implementation of Optimal
Trajectory Control of Series Resonant Converters,” Proc. IEEE
[STEP-8] Select the resonant capacitor PESC ’87, 1987.
When choosing the resonant capacitor, the current rating [4] V. Vorperian and S. Cuk, “A Complete DC Analysis of the Series
should be considered since a considerable amount of current Resonant Converter,” Proc. IEEE PESC’82, 1982.
[5] Y. G. Kang, A. K. Upadhyay, D. L. Stephens, “Analysis and
flows through the capacitor. The RMS current through the design of a half-bridge parallel resonant converter operating
resonant capacitor is given as above resonance,” IEEE Transactions on Industry Applications
Vol. 27, March-April 1991 pp. 386 - 395
[6] R. Oruganti, J. Yang, and F.C. Lee, “State Plane Analysis of
π Io n(Vo + 2 ⋅ VF ) 2 Parallel Resonant Converters,” Proc. IEEE PESC ’85, 1985.
I Cr RMS ≅ [ ]2 + [ ] (28) [7] M. Emsermann, “An Approximate Steady State and Small Signal
2 2n 4 2 f o Lm Analysis of the Parallel Resonant Converter Running Above
Resonance,” Proc. Power Electronics and Variable Speed
Then, the maximum voltage of the resonant capacitor in Drives ’91, 1991, pp. 9-14.
[8] Yan Liang, Wenduo Liu, Bing Lu, van Wyk, J.D, " Design of
normal operation is given as integrated passive component for a 1 MHz 1 kW half-bridge
LLC resonant converter", IAS 2005, pp. 2223-2228
Vin max 2 ⋅ I Cr RMS
VCr max ≅ + (29) [9] B. Yang, F.C. Lee, M. Concannon,"Over current protection
2 2 ⋅ π ⋅ f o ⋅ Cr methods for LLC resonant converter" APEC 2003, pp. 605 - 609

A-8 Fairchild Power Seminar 2007

[10] Yilei Gu, Zhengyu Lu, Lijun Hang, Zhaoming Qian, Guisong
Huang, "Three-level LLC series resonant DC/DC converter"
IEEE Transactions on Power Electronics Vol.20, July 2005,
pp.781 - 789
[11] Bo Yang, Lee, F.C, A.J Zhang, Guisong Huang, "LLC resonant
converter for front end DC/DC conversion" APEC 2002.
pp.1108 – 1112
[12] Bing Lu, Wenduo Liu, Yan Liang, Fred C. Lee, Jacobus D. Van
Wyk, “Optimal design methology for LLC Resonant
Converter,” APEC 2006. pp.533-538

Hang-Seok Choi received the B.S., M.S. and Ph.D degrees in

electrical engineering from Seoul National University, in 1996,
1999 and 2002, respectively. He is currently working for
Fairchild Semiconductor in Bucheon, Korea as a system and
application engineer. His research interests include soft-
switching technique, and modeling and control of converters.
He has published 15 papers in IEEE conferences and
transactions and 10 application notes in Fairchild
semiconductor.

A-9 Fairchild Power Seminar 2007

Design guideline for magnetic integration in
LLC resonant converters
S. De Simone, C. Adragna, C. Spini
STMicroelectronics, via C. Olivetti 2, 20041 Agrate Brianza (MI), (Italy)

Abstract -- The aim of this paper is to present a and, furthermore, the transformer leakage inductance can
comprehensive design methodology for the magnetic be used as the series resonant inductor.
integration of the series and shunt inductances of the The aim of this paper is to give guidelines for the
resonant tank in an LLC resonant converter within the
magnetic integration of the series and shunt inductances
transformer.
The design procedure applies to symmetrical core-bobbin
of the resonant tank inside the transformer, in order to get
structures with two separate slots for the primary and a resonant circuit composed only of a capacitor and a
secondary windings. A specific leakage inductance Aσ (per resonant transformer.
square turn) that depends on geometrical parameters only is The article starts illustrating the LLC resonant
derived. This is used, together with the cross section and converter principle of operation, recalling the FHA (first
winding area of the core, to define two other core harmonic approximation) approach used in [1] and the
parameters that allow the designer to identify the minimum
ferrite core size suitable for the application.
design procedures proposed in [1] and [2] to calculate the
resonant tank. Then, we discuss various transformer
Index Terms – First harmonic approximation (FHA), models, including the APR (all-primary-referred) one,
LLC resonant converter, zero-voltage switching (ZVS), which better fits with the basic LLC resonant tank circuit.
magnetic integration, transformer “all primary referred” Afterwards, considering the case of a symmetrical two-
(APR) model. slot coil-former, the specific leakage inductance of the
core-bobbin structure is introduced, a parameter that only
I. INTRODUCTION depends on the shape and size of the ferrite core.
The interest in resonant topologies is continuously Finally, we outline the proposed design process for the
growing in the power conversion market, due to better magnetic integration; and we define two core specific
efficiency and lower EMI pollution, with respect to parameters, KGM and KGW, which allow the designer to
traditional PWM solutions, inherent to these kinds of choose the minimum ferrite core size that meets the
converters. This, in turn, allows for higher operating electrical requirements and, at the same time, guarantee a
frequencies and consequently for a size reduction of the maximum specified temperature rise of the transformer.
magnetic components and, generally, of the overall
volume of the power supply. II. CIRCUIT DESCRIPTION
One of the most popular resonant topologies nowadays A resonant converter basically applies a square voltage
is the multi-resonant LLC converter in its half-bridge or current generated by a power switch network to a
implementation, which directly derives from the LC resonant circuit; the energy circulates in the resonant tank
series resonant converter, by adding a shunt inductor in and part of it is delivered to the load. Fig. 1 shows a
parallel to the load (see Fig. 1). typical LLC resonant half-bridge converter: the half-
The LC series resonant converter suffers from a few bridge MOSFETs, driven on and off symmetrically with
drawbacks, which limit its use in several applications: in 50% duty cycle, generate a square waveform with peak-
fact it only allows for buck operation (step-down) and to-peak amplitude Vdc, and an average value of Vdc/2.
cannot regulate the output voltage when unloaded; This voltage is applied to the resonant tank, composed of
furthermore, at light load (when the resonant tank current the series capacitor Cr, the series inductor Lr and the
is very low), the ZVS (zero voltage switching) behavior shunt inductor Lm, so that energy can be transferred to the
that minimizes power consumption is lost. load, which is coupled to the resonant tank by the ideal
The LLC converter overcomes all of these problems, transformer T. The capacitor Cr acts both as a resonant
as shown in [1], where its behavior is analyzed, and a dc blocking capacitor: so, at the end, the alternate
demonstrating that the resonant tank can be designed in square voltage across the resonant tank has an amplitude
order to always operate the half-bridge MOSFETs in of ±Vdc/2. The transformer also provides insulation from
ZVS condition, while regulating the output voltage down the mains.
to zero-load. This operation is achieved essentially for The design procedure of an LLC converter is not as
free, as the additional shunt inductor can be implemented straightforward as for a PWM converter; in [1] a design
simply by introducing an air gap in the transformer core guideline is presented that is based on the FHA approach;
this tremendously simplifies the circuit model, leading to
a linear circuit, which can be dealt with through the (fn = 1), where the required gain is unity: therefore, in the
classical complex ac-circuit analysis. The FHA approach frame of the ten-step procedure, this is the operating point
is based on the assumption, that the power transfer from at nominal input voltage.
the source to the load through the resonant tank is almost The regulation of the output voltage of the resonant
completely associated to the fundamental harmonic of the converter is achieved by changing the switching
Fourier expansion of the currents and voltages involved, frequency of the square waveform: as the working region
in accordance to the selective nature of a resonant circuit. is in the inductive part of the voltage gain characteristics
of the resonant tank, the frequency control acts by
Q1 increasing the frequency to lower the output power and
by decreasing the frequency at decreasing input voltage
T
Half-bridge

Cr Lr
(because the required voltage gain increases with
Driver

Vdc n:1 D1 Cout Rout

Irt decreasing input voltage).
Lm Vout Because the FHA model of an LLC resonant converter
Q2 is not so accurate in the below-resonance region (where
D2
the current waveforms exhibit both the resonance
frequency of Cr with Lr and the resonance frequency of Cr
Figure 1. Half-bridge LLC resonant converter schematic with the total inductance Lr+Lm), in [2] a further model is
Fig. 2 shows the linear equivalent circuit, derived from presented that is based on the inspection of the tank
the FHA assumption, where Vi.FHA and Vo.FHA are the first current in a particular operating mode. In this operating
harmonic of the Fourier series expansion of the input and mode, the tank current, during the time interval when the
output square voltages of the resonant converter, output diodes are conducting, has a sinusoidal shape at
respectively, while Ro.ac is the ac equivalent resistance of resonance frequency (while the current in Lm is linear,
the output load: because the voltage across it is clamped to the output
2 2 2 2
8 Vout 8 voltage reflected at primary). In the time interval when
Vi. FHA = Vdc Vo.FHA = Vout Ro.ac = = 2 Rout diodes are not conducting, the tank current (and therefore
π π π 2
Po π
the magnetizing current, too) is imposed to stay flat,
The ten-step procedure proposed in [1], allows the equal to the value at the end of the previous time interval:
designer to calculate the resonant-tank circuit parameters, in this way, the induction level B, which only depends on
Cr, Lr, Lm and n, which fulfill a set of input/output the current flowing in the magnetizing inductance, also
specifications, including the ZVS condition and the no- does not increase, and the transformer can be designed as
load operation, and assuming that the circuit operates at
if it was operated at resonance frequency instead of the
resonance frequency when the input voltage has the
real operating frequency, below resonance. Also the nine-
nominal value. The resonance frequency and the
step procedure proposed in [2] allows the designer to
maximum operating frequency are input parameters,
chosen by the designer. calculate the values of the circuit parameters of Fig. 2,
according to the same specification requirements as in
[1].

Figure 2. LLC resonant converter FHA equivalent model

The circuit in Fig. 2 is completely characterized by its

input impedance Zin(j2πfsw) and forward transfer function
H(j2πfsw). These are used in [1] to identify all the
relationships and conditions to solve for the unknowns of
the circuit (Cr, Lr, Lm and n). Fig. 3 shows the resonant
tank voltage gain M (M = n|H|) versus normalized Figure 3. Voltage gain of an LLC resonant converter
frequency fn, at different values of the circuit quality Looking at Fig. 2, it is evident that the LLC resonant
factor Q (which means, at different power levels). The converter is well suited for the magnetic integration of
red curve in this graph represents the no-load voltage the series and shunt inductances (Lr, Lm) as well as the
gain. The load independent point, where all the curves transformer (T) into one magnetic component. In fact, the
touch, is the operating point at the resonance frequency tank configuration recalls one of the most popular models
of a transformer: the APR one, where the series of the primary and secondary coupling coefficients k1 and
inductance Lr can be seen as the total leakage inductance, k2 (which represent the portions of flux generated by the
that is, the one measured on the primary side with the primary and secondary windings, respectively, that link
secondary windings short circuited. to the other winding):
k = k1 k 2
III. TRANSFORMER MODEL
Fig. 4 shows a system of two coupled inductors (as a In fact, by the definitions of the coupling coefficients, we
two winding transformer can be generally termed), with have:
L1 and L2, respectively, primary and secondary self- M N2 and M N1
= (*)
= k1 k2
inductance and M mutual inductance; we can derive an L1 N1 L2 N 2
electrical-equivalent model of this magnetically coupled By multiplying the two expressions above and solving for
system, formed by the inductors La, Lb, Lµ and an ideal M, we get:
transformer with turn ratio N. By comparing the branch-
constitutive equations of the two circuits: M = k1 k 2 L1 L2 = k L1 L2

L µ + La Lµ N Therefore, for the physical model we find the following

V1 L M I1 V1 I
= s⋅ 1 ⋅ ⇔ = s⋅ Lµ ⋅ 1 relationships:
V2 M L2 I 2 V2 Lµ N + Lb I 2
N2 ⎧ M
⎧LM = k1 L1
N1 ⎪ where ⎪ k1 = L n t
we can find the relationships to pass from one model to nt = ⎨Lσ 1 = (1 − k1 ) L1 ⎪ 1
N2 ⎨
the other: ⎪L = (1 − k ) L ⎪k = M 1
⎩ σ2 2 2
⎧ L1 = Lµ + La ⎪⎩ 2 L2 nt
⎧ La = L1 − Lµ = L1 − N M
⎪ ⎪
⎪ ⎪⎪ Another interesting transformer model comes out when N
⎪ Lµ
⎨M = ⇔ ⎨ Lµ = N M is chosen equal to the square root of primary to secondary
⎪ N ⎪ inductance ratio (see Fig. 5) which leads to the following
⎪ Lµ ⎪ L = L − Lµ = L − M set of relationships:
⎪ L2 = 2 + Lb ⎪⎩ b 2
N2
2
N
⎩ N
⎧ Lµ = k L1
The equivalent model presents one degree of freedom, L1 ⎪ M
ne = ⎨ LS1 = (1 − k ) L1 k=
as it has four unknowns (La, Lb, Lµ and N), while the L2 L1 L2
⎪
⎩ LS 2 = (1 − k ) L2 = LS1 / ne
2
coupled inductor has only three unknowns (L1, L2 and
M); that means we can fix one of these arbitrarily and where ne is the effective turns ratio. In this case, Lµ, LS1
determine all the others: the logic choice is to fix N. and LS2 do not have the physical meaning of magnetizing
and leakage inductances, but they are only model
parameters. Furthermore, it is worth noting that the
secondary side series inductance reflected to the primary
side equals the primary side series inductance:
Figure 4. Coupled inductor equivalent model LS 1 = LS 2. p = ne2 LS 2
In case N equals the real winding turns ratio nt =
N1/N2 (where N1 and N2 are the number of turns of the
two windings), the model represents the real physical
model of the coupled inductor (see Fig. 5), where LM is
the magnetizing inductance (associated to the flux that
mutually links the two windings), while Lσ1 and Lσ2 are Figure 5. Coupled inductor equivalent models for N = nt and N = ne
the primary and secondary leakage inductances (which The two models with N = nt and N = ne are perfectly
are associated to the primary and secondary leakage identical in case that k1 = k2, which might happen when
fluxes). This physical model is exactly equal to that the system of coupled inductors is symmetrical, such as
coming from the reluctance model approach. From a in a two-slot symmetrical bobbin, with each winding of
physical standpoint it must be verified that: equal number of turns wound in each slot. In fact, by
M ≤ L1 L2 dividing the two expressions above in (*) and root
squaring, we get:
where the equality sign means perfect coupling between
the windings (which cannot be reached in reality, as L1 N1 k2 k2
ne = = = nt
leakage fluxes are always present, though they can be L2 N 2 k1 k1
very small). A coupling coefficient k (k < 1) is therefore
Another very useful equivalent model of the coupled
introduced, so that it is possible to write:
inductor is the APR one illustrated in Fig. 6, derived by
M =k L1 L2 imposing the secondary side series inductance Lb (in Fig.
and it can be demonstrated that k is the geometric mean 4) is zero, which translates to:
M M L1 world structures where the condition of magnetic
N= = = k ne = n symmetry is quite close to reality: consider for example
L2 L1 L2 L2
the ferrite E-core plus slotted bobbin assembly, using
The resulting relationships for this model (both in side-by-side winding arrangement, as shown in Fig. 7.
direct and inverse form) are:
⎧ Lm
⎧⎪ Lm = n M = k 2 L1 ⎪⎪ L1 = k 2 Lm
⎨ ⎨ M =
⎪⎩ Lr = L1 − n M = (1 − k 2 ) L1 n
⎪ L = Lm
⎩⎪
2
n2

Figure 7. Transformer construction: E-cores and slotted bobbin

Figure 6. Transformer APR model This type of transformer construction is well suited for
this application, where the leakage inductance is used as
The transformer equivalent circuit (for N = ne and for the resonant-tank series inductance, and therefore needs
N = n = k ne) can be completely identified through three to be well controlled and reliable for the circuit operation.
measurements: the inductances L1 and L2 of the primary Furthermore, the side-by-side winding technique allows
and secondary windings and the inductance Ltot of the for a wide range of values of leakage inductance, and
series connection of the two windings (such that the hence coupling coefficient k, and is simpler and more
current has the same flowing direction through both the effective than the layer winding arrangement.
dotted winding terminals), that is: Once the transformer model is completely defined, the
==> Ltot − ( L1 + L2 ) next step is to find out the relationships to pass from the
Ltot = L1 + L2 + 2 M M=
2 model parameters to the transformer construction
Once L1, L2 and M are known, you can calculate the parameters: N1, N2 and lG, respectively, primary and
model parameters (n, Lm, Lr) and (ne, k, LS1, LS2) through secondary number of turns and thickness of the air gap.
the above sets of equations. If the primary and secondary These parameters are the only ones that can be changed
number of turns (or turns ratio) are also known, you can within a certain design to get the desired transformer,
also completely define the physical model (for N = nt) by once the ferrite core and bobbin are chosen.
calculating (k1, k2, LM, Lσ1, Lσ2). The inductance factor AL (i.e. the inductance per
It is easy to recognize that the LLC resonant circuit is square turn) can be alternatively used, instead of the air
well suited for magnetic integration, i.e. to combine the gap thickness lG. Magnetic material suppliers usually
inductors as well as the transformer in Fig. 2 into a single specify AL and lG data in the form of a table in their
magnetic device; in fact, the magnetic part of the basic ferrite core datasheets, or give the AL values as a
LLC resonant circuit is topologically identical to the APR parameterised function of the air gap size.
model of a transformer.
The design flow based on the procedures proposed in IV. SPECIFIC LEAKAGE INDUCTANCE
[1] and [2] provides the parameters of the APR model Lr, In this section we derive a semi-empirical formula
Lm and n (together with the resonant capacitance Cr); based on the energy calculation approach. It allows the
hence, the further step is to determine the parameters of designer to estimate the leakage inductance of a two-
the physical model. winding transformer employing a two-section coil-
The problem is mathematically undetermined: there former.
are four unknowns (nt, Lµ, Lσ1 and Lσ2) in the physical Fig. 8 shows a symmetrical two-slot bobbin with N1
model and only three parameters in the APR one. One turns primary winding (in red) and N2 turns secondary
simplifying assumption that overcomes this issue is the (in yellow). In the next discussion we will neglect the coil
magnetic circuit symmetry: flux linkage is assumed to be former thickness and dimensions, except the safety
exactly the same for both primary and secondary distance dS between primary and secondary windings,
windings (that is k1 = k2). In this case, the physical model and we will assume that the two windings are equally and
(N = nt) and the model with N = ne are the same, which evenly distributed inside their respective slots.
provides the missing condition for solving the system It is possible to derive the expression of the energy
(LS1 = ne2 LS2). The complete solution is the following: associated to the leakage flux, which is stored in the
⎧⎪k = Lm /( Lr + Lm ) ⎧L1 = Lr + Lm ⎧ LS 1 = (1 − k ) L1 = Lσ 1 winding volume. If the secondary winding is short
⎨ ⎨ ⎨ circuited, the current I1 flowing into the primary winding
⎩LM = Lµ = k L1 ⎩ LS 2 = LS1 / ne = Lσ 2
2
⎪⎩ne = nt = n / k
causes a current I2 = I1 N1/N2 flowing into the secondary,
As previously mentioned, it is not difficult to find real- such that the flux inside the magnetic core is almost zero.
Int. path dS
dH

dTX dL
lG

MTL = lW

dW dH dT

Hx(x)
dH
N1 I1
dH

dB 0 x
dW-dS dS dW-dS
2 2

Figure 8. Two section slotted transformer and magnetic field distribution along winding section width direction

Due to the high permeability of ferrite materials, the field height dH; therefore the energy stored in the magnetic
intensity, H, inside the magnetic core is negligible too; field is:
therefore, we can neglect the energy stored into the core µo
dW
µo
dW

E = Lσ 1 I12 = ∫ H x ( x) Ax dx = ∫H ( x) lW d H dx =
2 2
and assert that the energy of the magnetic field, generated x
2 2
by the primary current I1, is only dislocated within the 0 0

winding volume. Referring to Fig. 6, we can also assert ⎡ dW − d S 2 dS

⎤
µo lW ⎢ 2 ⎛ 2 x ⎞
(N1 I1 ) ⎟⎟ dx + ∫ dx ⎥⎥ =
d H ⎢ ∫0 ⎜⎝ dW − d S
that this energy equals the one associated to the leakage = 2
2
⎜
2 ⎠
inductances Lσ1 and Lσ2 of the transformer model, when ⎢⎣ 0 ⎥⎦
the secondary is short circuited, that is (due to symmetry µ d + 2dS
assumption) it is equal to twice the energy associated to = o lW W (N1 I1 )2
6 dH
Lσ1:
The average length of turn (lW), in case of an E core
2
1 1 ⎛ N1 ⎞ 1 µ type (square center leg), can be evaluated as follows:
E = Lσ 1 I 12 + Lσ 2 ⎜⎜ I 1 ⎟⎟ = Lσ 1 I 12 = ∫ B H dv = o ∫H
2
dv
2 2 ⎝ N2 ⎠ 2 Vol 2 Aext .T − ACS
Vol
lW =
dH
=
2
dH
( )
d H2 + d H (dT + dTX ) = d H + dT + dTX
The field intensity H (see Fig. 8), considered
approximately uniform along the window height (dH) while in the case of an ETD core type (round center leg
direction, is derived through Ampere’s law: diameter DCL) it can be approximated by the expression:
N1 I1 2 x dW − d S Aext .T − ACS 1 π
∫ H dl = N 1 I1 ⇔ H x ( x) =
d H dW − d S
0≤ x≤
2 lW =
dH
=
dH 4
(
(d H + DCL ) 2 − DCL
2
)
In fact, considering an integration path as indicated in where ACS is the area of the center leg cross section of the
Fig. 8, which encircles more and more current along the x core, while Aext.T is the area of the most external winding
direction, the Hx field increases linearly from zero to the turn. From the above calculated energy expression, we
maximum value (N1I1/dH) when all the turns are can obtain the series inductance Lr in the transformer
encircled, then it stays constant through the safety APR model:
distance spacer and at last decreases linearly again down
L = A (1 + k ) N 2 where µo dW + 2 d S
to zero, when all of the secondary turns are encircled. r σ 1 Aσ = lW
6 dH
The differential volume element dv is equal to the
product of dx times the area Ax of the cross section of the The term Aσ is the “specific leakage inductance per
winding area orthogonal to the x axis (see Fig. 8), which squared turn” associated with the core and winding
is a sort of ring surface, whose area is approximately the construction: it depends only on the geometrical
product of the mean turn length lW times the window area parameters of the chosen core and coil-former and, in
spite of all simplifying assumptions, its expression where Ae is the effective ferrite core cross section and Vo
provides quite accurate results, within 10-15% of is the transformer output voltage, which includes the
experimental measurements. diode voltage drop VF as well. Of course, the peak
The above relationships have been found in the operating flux density Bpk must be lower than the
hypothesis in which the windings completely fill the saturation value Bsat.
available area, but they are still valid when the winding The second constraint is represented by the modified
area is not completely used; they allow us to pass from Steinmetz equation that expresses the core losses as a
the model parameters to the construction ones (once a function of the core volume Ve, the operating frequency
magnetic core and bobbin have been chosen) according to fop and the peak flux density Bpk (supposed sinusoidal):
the following expressions: ⎛8⎞
α −1
Pfe = ⎜ ⎟ Ve K m f opα B pk
β (3)
N1 =
Lr 1 k N
N 2 = N1 = 1 AL =
Ltot (1) ⎝π ⎠
Aσ 1 + k n nt ( N1 + N 2 ) 2 The parameters Km, α and β depend on the chosen
where Ltot is the total inductance of the primary and material grade and can be derived from the data or loss
secondary windings series connected (with the flowing charts provided by the ferrite manufacturers for the
current path entering the dotted terminals): specific material. The numerical coefficient (8/π2)α-1 is a
form factor taking into account that the applied voltage
Ltot = L1 + L2 + 2 M = L1 + L2 + 2 k L1 L2
(and hence induction) is a square waveform with 50%
In literature there are several models and expressions duty cycle.
for the AL value of the core versus the air gap thickness A further constraint is that the temperature rise caused
lG; the one proposed by McLyman [3] results in very by the total losses should not exceed the maximum
good agreement with empirical data, and is suitable when allowed by specification, that is:
the thickness of the air gap is larger than 0.1 mm. The (4)
∆Tmax ≤ Rth Pdiss = Rth ( Pfe + Pcu )
expression below takes the fringing flux around the air
gap into account, whose effect (increasing with lG) is to where Pfe and Pcu are respectively the core and copper
increase the effective cross section of the magnetic path: losses; it is assumed that the temperature rise will be
⎡ accordingly apportioned:
ACS l ⎛2d ⎞⎤
AL = µ o ⎢1 + G ln⎜⎜ W ⎟⎟⎥ P
lG ⎢⎣ ACS ⎝ lG ⎠⎥⎦ ∆Tcu = cu ∆Tmax = K cu ∆Tmax
Pdiss (5)
where ACS and dW are the ferrite core cross section area
Pfe
and the winding area width, respectively: the above ∆T fe = ∆Tmax = (1 − K cu ) ∆Tmax
expression shows that AL only depends on geometrical Pdiss
parameters (like the specific leakage inductance Aσ). where ∆Tcu and ∆Tfe are the amount of temperature rise
associated to the copper losses and to the ferrite core
V. DERIVATION OF THE KGM AND KGW CONSTANTS losses, respectively. The thermal resistance Rth of the
In this section, a set of basic constraining equations is magnetic structure is usually specified by the supplier: an
presented that, if combined together, allows selecting the empirical formula is also available, which estimates the
minimum core size of the transformer that fulfills the thermal resistance as a function of the core area product
electrical specifications and guarantees a maximum AP (product of the cross section area Ae and the winding
temperature rise. The first constraint is derived by area Aw of the ferrite core):
Faraday’s law applied on the transformer secondary side: Rth = 23 AP −0.37 °C / W (with AP in cm4)
Ts
Vout + V F V Another constraint is constituted by a further empirical
N 2 ∆Φ = N 2 ∆B Ae = ∫ 2
vo (t ) dt = = o
0 2 f op 2 f op equation that relates the current density J (responsible for
where ∆Φ is the flux generated by the magnetizing the temperature rise ∆Tcu inside the winding area) to the
current that is linked to all primary and secondary turns; area product AP (expressed in cm4):
the corresponding peak value of the flux density ∆Tcu ∆Tmax (6)
J = J 30 AP −0.24 = J 30 K cu AP −0.24
Bpk=∆B/2 is responsible for the core losses. The worst 30°C 30°C
condition occurs at the resonance frequency, when the where J30=420 A/cm2 is the current density that produces
resonant tank circuit design is made according to the 30°C temperature rise in the windings; it is worth
procedure presented in [2], otherwise the minimum pointing out that AP in (6) is dimensionless: it just
operating frequency has to be chosen, in which case the represents the number of cm4 of core area product.
above equation overestimates the flux density: here we Considering that the primary ampere-turns equal the
follow the fop = fres option. Taking the primary to current density times the total primary conductor area, we
secondary turn ratio into account, the above relationship can write:
becomes:
N1 I p.rms = K ut Aw J (7)
n Vo (2)
N1 =
4 k f res B pk Ae where Ip.rms is the rms value of the resonant tank current
flowing in the transformer primary winding and Kut is the inequality in (12) is satisfied. The second core parameter,
window utilization factor (that is the ratio between the KGW, is related to the core capability to dissipate the Joule
primary winding copper area to the winding area); this losses generated inside the copper windings. In this
factor, in case Litz wire is used for windings (the real procedure, the parameter Kcu (apportionment of copper to
case in this application type, in order to reduce the copper total losses) is arbitrarily chosen: it can be initially set to
losses due to skin and proximity effect), can be as low as 50% and then, in case only one of the two inequalities
0.2. above is verified, it can be changed in the attempt to get
The last constraint is the relationship, already found in both of them verified for the chosen core. For example, in
the previous section, between the specific leakage case the second inequality is not verified, it is possible to
inductance Aσ, the number of primary turns and the total gradually increase Kcu and check if in the end both the
leakage inductance, here rewritten for convenience: relationships are true, that is, the ferrite core is suitable to
Lr = Aσ (1 + k ) N12 = Λσ µo (1 + k ) N12 (8) manage the total amount of power dissipation without
exceeding the maximum allowed temperature rise.
It is worth pointing out that the quantity Λσ=Aσ/µo is
dimensionally a length and only depends on the core and VI. DESIGN PROCEDURE
coil-former geometry.
Based on the analysis presented so far, the following
Combining the equations (2) to (5) with (8), it is
procedure is proposed to design the integrated
possible to write the following expression:
2
transformer in Fig. 2. The input data are the values of
2
⎞ ⎡
2α −1 parameters n, Lr, Lm, previously calculated according to
⎛ 8 ⎞ ⎤β
α
Ae2 ⎛ 1 ⎞ β µ o Lr ⎛ n Vo
K m f res
⎜⎜ ⎟⎟ = ⎟⎟ ⎢ ⎜⎜ ⎜ 2⎟ ⎥ [2] in order to fulfill the converter specifications. Further
Λσ ⎝ Ve Rth ⎠ ⎠ ⎢⎣ (1 − K cu ) ∆Tmax ⎝ π ⎠ ⎦⎥
1− k ⎝ 4k f res input data are the maximum allowed temperature rise
(9) ∆Tmax, the output voltage Vo (including the output diode
Combining the equations (5) to (8), a second forward drop), the rms value of current flowing into the
expression can be found: primary and secondary windings (Ip.rms and Is.rms), the
2 resonance frequency fr and the operating frequency range
⎛ I ⎞ 1 + k 30°C (10)
Aw2 Λσ AP −0.48 = µo ⎜⎜ p.rms ⎟⎟ (fmin - fmax).
⎝ ut 30 ⎠ K cu ∆Tmax
K J 1- first, select a material grade suitable for the
The terms on the left side of equations (8) and (9) operating frequency range of the application, identifying
depend on the core geometry (and β coefficient), while the parameters Km, α and β.
the terms on the right side depend on the circuit and 2- then, calculate the terms on the right side of
application parameters and chosen material grade. expressions (12), considering that the coupling
Therefore the left side of above equations can be defined coefficient k is found through: k = Lm /( Lr + Lm )
as the core geometrical constants KGM and KGW: 3- select a core-bobbin shape and size such that the
2
core geometrical constants KGM and KGW, defined in (11),
Ae2 ⎛ 1 ⎞β (11)
K GM = ⎜⎜ ⎟⎟ K GW = Aw2 Λ σ AP −0.48 satisfy the inequalities in (12). The designer can initially
Λσ ⎝ Ve Rth ⎠ set the copper to total losses apportionment Kcu = 50%
Hence, to design a transformer which integrates the and then play with it (+/- 15%) if needed, in order to get
series and shunt inductances for the LLC resonant the inequalities verified. In case the inequalities are both
converter application, first the suitable material grade has satisfied, the designer can try to reduce the core size by
to be chosen, depending on the operating frequency range using a better material grade, with lower losses in the
of the application; then the second terms of equations (9) application frequency range.
and (10) have to be calculated and finally, a core has to 4- calculate the number of primary turns N1, to get the
be selected, whose geometrical constants exceed these required leakage inductance, by using the first equation
values: of (1): this number is only the first attempt and may need
2
2 to be fine tuned once the first sample is built and
α −1
⎛ n Vo ⎞ Lr ⎡ α
K m f res ⎛ 8 ⎞ ⎤β measured. Also, define the number of secondary turns N2
K GM ≥ µ o ⎜⎜ ⎟⎟ ⎢ ⎜ 2⎟ ⎥ (12)
⎝ 4 k f res ⎠ 1 − k ⎢⎣ (1 − K cu ) ∆Tmax ⎝ π ⎠ ⎦⎥ and the AL value through the other two equations of (1).
2 5- define the wire section for primary and secondary
⎛ I p.rms ⎞ 1 + k 30°C
K GW ≥ µ o ⎜⎜ ⎟⎟ windings. High frequency copper losses must be
⎝ K ut J 30 ⎠ K cu ∆Tmax particularly addressed, because eddy currents and
The first core parameter, KGM, is related to the proximity losses are considerable and, consequently,
capability of the chosen ferrite core to handle the losses suggest the use of Litz wires or multi-strand wires for
into the magnetic material, while assuring the required both primary and secondary windings. If the strand
leakage: therefore, in case the inequality related to this diameter and the number of strands are optimized (see
parameter is not verified with a chosen material grade, [4]) to minimize the total copper losses (ohmic and eddy),
the designer can try to use a better one, if available, with usually this leads to select a wire cross section such that
lower specific losses, and check again if the first the losses due to eddy currents are one half of the ohmic
losses: this means that the ohmic losses Pcu.ohm are 2/3 of TABLE I
DESIGN SPECIFICATION OF THE EXEMPLARY LLC CONVERTER
the maximum allowed copper losses Pcu. From this Parameter Symbol Value Unit
consideration the designer can find out the required wire Input voltage range Vinmin - Vinmax 320 - 430 V
section of the primary and secondary windings: the last Nominal input voltage Vinnom 390 V
step is then to select the strand configuration (strand Regulated output voltage Vout 36 V
Maximum (peak) output current Iout 8.35 A
diameter and number of parallel strands with the
Expected efficiency (@ Vinmin) η 95 %
calculated total cross section) that presents the lowest ac Parasitic capacitance of node HB CHB 200 pF
resistance. Dead time of driver circuit Td 200 ns
Throughout the various sections presented so far, the
transformer has been considered composed of one TABLE II
primary winding and one secondary winding (single RESONANT TANK ELECTRICAL AND OPERATING PARAMETERS
ended), that is the case where the full-bridge rectification Parameter Symbol Value Unit
is used at converter output. In case of secondary center- Resonance frequency fr 120 kHz
Turn ratio of transformer in Fig. 2 n 5.335 -
tap windings and full-wave rectification (as in Fig. 1), the Shunt inductance (see Fig. 2) Lm 305 µH
rms value of the current flowing into each secondary Series inductance (see Fig. 2) Lr 56 µH
winding is 1/√2 times the current flowing through the Coupling coefficient k 0.92 -
single-ended winding of the previous output Tank primary current (rms value) Ip.rms 2.1 A
Total rectified output current (rms value) Is.rms 9.3 A
configuration: therefore the wire section of each center-
tap can be half the copper section, necessary for the
single-ended secondary winding (while the number of
CONCLUSIONS
secondary turns N2 is obviously the same in both cases).
There is another important aspect to consider in case In this article a design procedure has been outlined to
of a transformer with secondary center-tap: the two completely define the parameters of a transformer (N1,
windings need to be tightly coupled to each other, so that N2, lG) that integrates all the magnetic parts of an LLC
the leakage inductance, measured on the primary side resonant converter (Fig. 2) into a single component. This
with either secondary winding short circuited, is almost procedure allows the designer to choose the minimum
the same. In fact, during each half cycle of operation, the ferrite core size to satisfy the electrical specifications and
resonant capacitor in Fig. 2 rings with the leakage guarantee a maximum temperature rise of the
inductance between the primary winding and the transformer, once a suitable ferrite material grade has
corresponding center-tap winding that is conducting been selected for the operating frequency range. For this
current on the secondary side. Therefore, in case these purpose, the two constants KGM and KGW have been
two leakage inductances are substantially different, the defined, related to the core and bobbin geometry, that
tank current will be not symmetrical and the circuit will estimate the capability of the core-bobbin assembly to
exhibit two different resonance frequencies during each handle the total losses, while assuring the required
half cycle, that can make it very difficult (or even leakage inductance, necessary for the correct operation of
impossible) to compensate the feedback loop of the the resonant tank. These two constants also depend on a
converter. In order to get good coupling between the further parameter of the core-bobbin set: the specific
center-tap windings, a good practice is to wound them in leakage inductance Aσ (or equivalently Λσ), that has been
parallel (in bifilar). estimated (in section IV) using the energy calculation
An integrated transformer with secondary center-tap approach, that is, by evaluating the energy associated to
for the LLC resonant converter specified in Table I has the leakage flux in the winding volume.
been designed, following the proposed procedure and a
prototype has been built and tested on the bench. The REFERENCES
resonant tank parameters, calculated through the [1] S. De Simone, C. Adragna, C. Spini, G. Gattavari: Design-
procedure in [2], are summarized in Table II and used as oriented steady state analysis of LLC resonant converters
input data for the transformer design. The chosen ferrite based on FHA, Speedam 2006 Symposium
[2] C. Adragna, S. De Simone, C. Spini: Design methodology
core is ETD49, grade 3F3 Ferroxcube (with α=1.6, β=2.5 for LLC resonant converters based on inspection of
Km=0.25 W/m3), for which the core parameters are: resonant tank current, APEC 2008
KGM=829.3 cm3(W/°C m3)2/β, KGW=29.6 cm5 (assuming [3] C. W. T. McLyman: Transformer and inductor design
Rth=8°C/W and Λσ=5.05 cm). The second terms of (9) handbook, ed. Marcel Dekker Inc (3rd edition), ISBN 0-
and (10), calculated for Kcu=0.5 and ∆Tmax=40°C, make 8247-5393-3
the inequalities (12) verified according to: [4] A. van den Bossche, V. Cekov Valchev: Inductors And
Transformers For Power Electronics, ed. Marcel Dekker
KGM ≥ 737.4 cm3(W/°C m3)2/β and KGW ≥ 10.6 cm5. Inc, ISBN 1574446797
The prototype has been built with N1=23 primary turns [5] R. W. Erickson, D. Maksimovic: Fundamentals of power
(calculated 21.4) of litz wire 30x0.2 mm, N2=4 secondary electronics, ed. Kluwer Academic Publishers, (2nd edition)
turns of Litz wire 75x0.2 mm, for each cente-tap winding, ISBN 0792372700
and a gap of about 0.45mm. The coil-former has a spacer [6] An introduction to LLC resonant half-bridge converters,
between the two slots, whose thickness is ds=3 mm. AN2644, www.st.com.
www.fairchildsemi.com

AN-9730
LED Application Design Guide Using Half-Bridge LLC
Resonant Converter for 160W Street Lighting
Introduction Among various kinds of resonant converters, the simplest
and most popular is the LC series resonant converter, where
This application note describes the LED driving system the rectifier-load network is placed in series with the L-C
using a half-bridge LLC resonant converter for high resonant network, as depicted in Figure 1[2-4]. In this
power LED lighting applications, such as outdoor or street configuration, the resonant network and the load act as a
lighting. Due to the existence of the non-isolation DC-DC voltage divider. By changing the frequency of driving
converter to control the LED current and the light voltage Vd, the impedance of the resonant network changes.
intensity, the conventional PWM DC-DC converter has The input voltage is split between this impedance and the
the problem of low-power conversion efficiency. The half- reflected load. Since it is a voltage divider, the DC gain of a
bridge LLC converter can perform the LED current LC series resonant converter is always <1. At light-load
control and the efficiency can be significantly improved. condition, the impedance of the load is large compared to
Moreover, the cost and the volume of the whole LED the impedance of the resonant network; all the input voltage
driving system can be reduced. is imposed on the load. This makes it difficult to regulate
the output at light load. Theoretically, frequency should be
Consideration of LED Drive infinite to regulate the output at no load.
LED lighting is rapidly replacing conventional lighting
sources like incandescent bulbs, fluorescent tubes, and
halogens because LED lighting reduces energy
consumption. LED lighting has greater longevity, contains
no toxic materials, and emits no harmful UV rays, which
are 5 ~ 20 times longer than fluorescent tubes and
incandescent bulbs. All metal halide and fluorescent
lamps, including CFLs, n contain mercury.
The amount of current through an LED determines the Figure 1. Half-Bridge, LC Series Resonant Converter
light it emits. The LED characteristics determine the
forward voltage necessary to achieve the required level of To overcome the limitation of series resonant converters,
current. Due to the variation in LED voltage versus the LLC resonant converter has been proposed[8-12]. The
current characteristics, controlling only the voltage across LLC resonant converter is a modified LC series resonant
the LED leads to variability in light output. Therefore, converter implemented by placing a shunt inductor across
most LED drivers use current regulation to support the transformer primary winding, as depicted in Figure 2.
brightness control. Brightness can be controlled directly When this topology was first presented, it did not receive
by changing the LED current. much attention due to the counterintuitive concept that
increasing the circulating current in the primary side with
Consideration of LLC Resonant a shunt inductor can be beneficial to circuit operation.
However, it can be very effective in improving efficiency
Converter for high-input voltage applications where the switching
The attempt to obtain ever-increasing power density of loss is more dominant than the conduction loss.
switched-mode power supplies has been limited by the In most practical designs, this shunt inductor is realized
size of passive components. Operation at higher using the magnetizing inductance of the transformer. The
frequencies considerably reduces the size of passive circuit diagram of LLC resonant converter looks much the
components, such as transformers and filters; however, same as the LC series resonant converter: the only
switching losses have been an obstacle to high-frequency difference is the value of the magnetizing inductor. While
operation. To reduce switching losses and allow high- the series resonant converter has a magnetizing inductance
frequency operation, resonant switching techniques have larger than the LC series resonant inductor (Lr), the
been developed. These techniques process power in a magnetizing inductance in an LLC resonant converter is
sinusoidal manner and the switching devices are softly just 3~8 times Lr, which is usually implemented by
commutated. Therefore, the switching losses and noise introducing an air gap in the transformer.
can be dramatically reduced[1-7].
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.0 • 3/22/11
AN-9730 APPLICATION NOTE

network even though a square-wave voltage is

applied to the resonant network. The current (Ip) lags
the voltage applied to the resonant network (that is,
the fundamental component of the square-wave
voltage (Vd) applied to the half-bridge totem pole),
which allows the MOSFETs to be turned on with zero
voltage. As shown in Figure 4, the MOSFET turns on
while the voltage across the MOSFET is zero by
flowing current through the anti-parallel diode.
Figure 2. Half-Bridge LLC Resonant Converter
The rectifier network produces DC voltage by
rectifying the AC current with rectifier diodes and a
An LLC resonant converter has many advantages over a capacitor. The rectifier network can be implemented
series resonant converter. It can regulate the output over as a full-wave bridge or center-tapped configuration
wide line and load variations with a relatively small with capacitive output filter.
variation of switching frequency. It can achieve zero
voltage switching (ZVS) over the entire operating range.
All essential parasitic elements, including junction
capacitances of all semiconductor devices and the leakage
inductance and magnetizing inductance of the transformer,
are utilized to achieve soft switching.
This application note presents design considerations of an
LLC resonant half-bridge converter employing Fairchild’s
FLS-XS series. It includes explanation of the LLC
resonant converter operation principles, designing the
transformer and resonant network, and selecting the
components. The step-by-step design procedure,
explained with a design example, helps design the LLC
Figure 3. Schematic of Half-Bridge LLC
resonant converter.
Resonant Converter

LLC Resonant Converter and Ip

Im
Fundamental Approximation
Figure 3 shows a simplified schematic of a half-bridge
LLC resonant converter, where Lm is the magnetizing
inductance that acts as a shunt inductor, Lr is the series
resonant inductor, and Cr is the resonant capacitor. IDS1
Figure 4 illustrates the typical waveforms of the LLC
resonant converter. It is assumed that the operation
frequency is same as the resonance frequency, determined
by the resonance between Lr and Cr. Since the ID
magnetizing inductor is relatively small, a considerable
amount of magnetizing current (Im) exists, which VIN
freewheels in the primary side without being involved in Vd
the power transfer. The primary-side current (Ip) is sum of
the magnetizing current and the secondary-side current
referred to the primary. Vgs1
In general, the LLC resonant topology consists of three
stages shown in Figure 3; square-wave generator, resonant Vgs2
network, and rectifier network.
Figure 4. Typical Waveforms of Half-Bridge LLC
The square-wave generator produces a square-wave Resonant Converter
voltage, Vd, by driving switches Q1 and Q2 alternately
with 50% duty cycle for each switch. A small dead The filtering action of the resonant network allows use of
time is usually introduced between the consecutive the fundamental approximation to obtain the voltage gain
transitions. The square-wave generator stage can be of the resonant converter, which assumes that only the
built as a full-bridge or half-bridge type. fundamental component of the square-wave voltage input
The resonant network consists of a capacitor, leakage to the resonant network contributes to the power transfer
inductances, and the magnetizing inductance of the to the output. Because the rectifier circuit in the secondary
transformer. The resonant network filters the higher side acts as an impedance transformer, the equivalent load
harmonic currents. Essentially, only sinusoidal resistance is different from actual load resistance. Figure 5
current is allowed to flow through the resonant shows how this equivalent load resistance is derived. The
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.0 • 3/22/11 2
AN-9730 APPLICATION NOTE

primary-side circuit is replaced by a sinusoidal current Cr Lr

Vd +
source, Iac, and a square wave of voltage, VRI, appears at + VO
the input to the rectifier. Since the average of |Iac| is the VIN +

output current, Io, Iac, is obtained as: Lm VRI

- Ro
-
π ⋅ Io Np:Ns -
I ac = sin(ωt ) (1)
2 2
8n
and VRI is given as: n=Np/Ns Rac = Ro
π2
VRI = +Vo if sin(ωt ) > 0
(2)
VRI = −Vo if sin(ωt ) < 0 Cr Lr VRoF
where Vo is the output voltage. VdF Rac
Lm (nVRIF)
The fundamental component of VRI is given as:
4Vo Figure 6. AC Equivalent Circuit for LLC
VRI F = sin(ωt ) (3)
π Resonant Converter

Since harmonic components of VRI are not involved in the With the equivalent load resistance obtained in Equation
power transfer, AC equivalent load resistance can be 5, the characteristics of the LLC resonant converter can be
calculated by dividing VRIF by Iac as: derived. Using the AC equivalent circuit of Figure 6, the
voltage gain, M, is obtained as:
VRI F 8 V 8
Rac = = 2 o = 2 Ro (4) 4n ⋅ Vo
sin(ωt )
I ac π Io π VRO F n ⋅ VRI F 2n ⋅ Vo
M = F = F
= π =
Vd Vd 4 Vin Vin
Considering the transformer turns ratio (n=Np/Ns), the sin(ωt )
π 2
equivalent load resistance shown in the primary side is (6)
obtained as: ω 2
(
) (m − 1)
ωo
2 =
8n ω2 ω ω2
Rac = Ro (5) ( 2 − 1) + j ( 2 − 1)( m − 1)Q
π
2
ωp ωo ωo

By using the equivalent load resistance, the AC where:

equivalent circuit is obtained, as illustrated in Figure 6, 8n 2 Lp
where VdF and VROF are the fundamental components of L p = Lm + Lr , Rac =
π2
Ro , m =
Lr
the driving voltage, Vd and reflected output voltage,
VRO (nVRI), respectively. Lr 1 1 1
Q= , ωo = , ωp =
Cr Rac Lr Cr L p Cr
I ac
pk As can be seen in Equation (6), there are two resonant
frequencies. One is determined by Lr and Cr, while the
other is determined by Lp and Cr.
Equation (6) shows the gain is unity at resonant frequency
(ωo), regardless of the load variation, which is given as:
2
2n ⋅ Vo (m − 1) ⋅ ω p
M= = = 1 at ω = ωo (7)
Vin ωo 2 − ω p 2
The gain of Equation (6) is plotted in Figure 7 for
different Q values with m=3, fo=100kHz, and fp=57kHz.
π ⋅ Io
I ac = sin( wt ) As observed in Figure 7, the LLC resonant converter
2
shows gain characteristics that are almost independent of
the load when the switching frequency is around the
4Vo resonant frequency, fo. This is a distinct advantage of
VRI F = sin( wt )
π LLC-type resonant converter over the conventional series
resonant converter. Therefore, it is natural to operate the
Figure 5. Derivation of Equivalent Load Resistance Rac converter around the resonant frequency to minimize the
switching frequency variation.
The operating range of the LLC resonant converter is
limited by the peak gain (attainable maximum gain),
which is indicated with ‘ ’ in Figure 7. Note that the peak
voltage gain does not occur at fo or fp. The peak gain
frequency where the peak gain is obtained exists between
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.0 • 3/22/11 3
AN-9730 APPLICATION NOTE

fp and fo, as shown in Figure 7. As Q decreases (as load In Figure 8, the effective series inductor (Lp) and shunt
decreases), the peak gain frequency moves to fp and higher inductor (Lp-Lr) are obtained by assuming n2Llks=Llkp and
peak gain is obtained. Meanwhile, as Q increases (as load referring the secondary-side leakage inductance to the
increases), the peak gain frequency moves to fo and the primary side as:
peak gain drops; the full load condition should be worst
case for the resonant network design. L p = Lm + Llkp
(8)
fp =
1
fo =
1 Lr = Llkp + Lm //(n 2 Llks ) = Llkp + Lm // Llkp
2π L p Cr 2π Lr Cr
When handling an actual transformer, equivalent circuit
Lr / Cr with Lp and Lr is preferred since these values can be
Q=
Rac measured with a given transformer. In an actual
transformer, Lp and Lr can be measured in the primary side
with the secondary-side winding open circuited and short
circuited, respectively.
In Figure 9, notice that a virtual gain MV is introduced,
which is caused by the secondary-side leakage inductance.
By adjusting the gain equation of Equation (6) using the
modified equivalent circuit of Figure 9, the gain equation
M @ fo = 1 for integrated transformer is obtained by:

ω 2
(
) ⋅ ( m − 1) ⋅ M V
2n ⋅ VO ωo
M = =
Vin ω2 ω ω2
( 2 − 1) + j ( ) ⋅ ( 2 − 1) ⋅ ( m − 1)Q e
ωp ωo ωo
Figure 7. Typical Gain Curves of LLC Resonant
Converter (m=3) ω2
(
) m(m − 1)
ωo 2
=
Consideration for Integrated ω2 ω ω2
( 2 − 1) + j ( ) ⋅ ( 2 − 1) ⋅ ( m − 1) ⋅ Q e
ωp ωo ωo
Transformer
where: (9)
For practical design, it is common to implement the
2
magnetic components (series inductor and shunt inductor) 8n Ro L
Rac e = , m= p
using an integrated transformer; where the leakage π 2 MV 2 Lr
inductance is used as a series inductor, while the Lr 1 1 1
magnetizing inductor is used as a shunt inductor. When Qe = , ωo = , ωp =
Cr Rac e Lr Cr L p Cr
building the magnetizing components in this way, the
equivalent circuit in Figure 6 should be modified as shown The gain at the resonant frequency (ωo) is fixed regardless
in Figure 8 because leakage inductance exists, not only in of the load variation, which is given as:
the primary side, but also in the secondary side. Not
considering the leakage inductance in the transformer Lp m
secondary side generally results in an ineffective design. M = MV = = at ω = ωo (10)
Lp − Lr m −1
The gain at the resonant frequency (ωo) is unity when
using individual core for series inductor, as shown in
Equation 7. However, when implementing the magnetic
components with integrated transformer, the gain at the
resonant frequency (ωo) is larger than unity due to the
Lr = Llkp + Lm //(n 2 Llks ) virtual gain caused by the leakage inductance in the
= Llkp + Lm // Llkp transformer secondary side.
Lp
(MV = )
Lp = Llkp + Lm 1: M V L p − Lr
The gain of Equation (9) is plotted in Figure 10 for different
Qe values with m=3, fo=100kHz, and fp=57kHz. As
observed in Figure 9, the LLC resonant converter shows
Rac
gain characteristics almost independent of the load when the
switching frequency is around the resonant frequency, fo.

Figure 8. Modified Equivalent Circuit to

Accommodate the Secondary-Side Leakage
Inductance

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 • 3/22/11 4
AN-9730 APPLICATION NOTE

1 1
fp = fo =
2π L p Cr 2π Lr Cr Gain (M) B

Lr / Cr A
Qe =
Rac e
Load Increase

II
Below Above
Resonance Resonance
(fs<fo) (fs>fo )

M @ fo = MV
fo fs

Figure 10. Operation Modes According to the

Operation Frequency

Figure 9. Typical Gain Curves of LLC Resonant 1

2 fo
Converter (m=3) Using an Integrated Transformer Ip (I) fs < fo
1
Im 2 fS

Consideration of Operation Mode

and Attainable Maximum Gain IDS1

Operation Mode
ID IO
The LLC resonant converter can operate at frequency
below or above the resonance frequency (fo), as illustrated
in Figure 10. Figure 11 shows the waveforms of the (II) fs > fo
currents in the transformer primary side and secondary Ip
side for each operation mode. Operation below the Im
resonant frequency (case I) allows the soft commutation of
the rectifier diodes in the secondary side, while the
IDS1
circulating current is relatively large. The circulating
current increases more as the operation frequency moves
downward from the resonant frequency. Meanwhile, ID IO
operation above the resonant frequency (case II) allows
the circulating current to be minimized, but the rectifier
diodes are not softly commutated. Below-resonance Figure 11. Waveforms of Each Operation Mode
operation is preferred for high output voltage applications,
such as street LED lighting systems where the reverse- Required Maximum Gain and Peak Gain
recovery loss in the rectifier diode is severe. Below-
resonance operation has a narrow frequency range with Above the peak gain frequency, the input impedance of the
respect to the load variation since the frequency is limited resonant network is inductive and the input current of the
below the resonance frequency even at no-load condition. resonant network (Ip) lags the voltage applied to the
resonant network (Vd). This permits the MOSFETs to turn
On the other hand, above-resonance operation has less on with zero voltage (ZVS), as illustrated in Figure 12.
conduction loss than the below-resonance operation. It Meanwhile, the input impedance of the resonant network
can show better efficiency for low output voltage becomes capacitive and Ip leads Vd below the peak gain
applications, such as Liquid Crystal Display (LCD) TV or frequency. When operating in capacitive region, the
laptop adaptor, where Schottky diodes are available for MOSFET body diode is reverse recovered during the
the secondary-side rectifiers and reverse-recovery switching transition, which results in severe noise.
problems are insignificant. However, operation above the Another problem of entering the capacitive region is that
resonant frequency may cause too much frequency the output voltage becomes out of control since the slope
increase at light-load condition. Above-frequency of the gain is reversed. The minimum switching frequency
operation requires frequency skipping to prevent too much should be limited above the peak gain frequency.
increase of the switching frequency.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 • 3/22/11 5
AN-9730 APPLICATION NOTE

Even though the peak gain at a given condition can be

M obtained using the gain in Equation (6), it is difficult to
Capacitive Inductive express the peak gain in explicit form. To simplify the
Peak Gain Region analysis and design, the peak gains are obtained using
Region
simulation tools and depicted in Figure 14, which shows
how the peak gain (attainable maximum gain) varies with
Q for different m values. It appears that higher peak gain
can be obtained by reducing m or Q values. With a given
fs resonant frequency (fo) and Q value, decreasing m means
reducing the magnetizing inductance, which results in
Vd Vd increased circulating current. There is a trade-off between
the available gain range and conduction loss.
Ip Ip 2.2

2.1

IDS1 IDS1 2

1.9
Reverse Recovery ZVS
1.8

Figure 12. Operation Waveforms for Capacitive

and Inductive Regions 1.7

Peak Gain
The available input voltage range of the LLC resonant 1.6
converter is determined by the peak voltage gain. Thus,
the resonant network should be designed so that the gain 1.5

curve has an enough peak gain to cover the input voltage m=2.25
1.4
range. However, ZVS condition is lost below the peak m=2.5
gain point, as depicted in Figure 12. Therefore, some
1.3
margin is required when determining the maximum gain to m=3.0
guarantee stable ZVS operation during the load transient m=3.5
1.2 m=4.0
and startup. Typically 10~20% of the maximum gain is m=4.5
m=5.0
used as a margin, as shown in Figure 13. 1.1 m=6.0
m=9.0 m=8.0 m=7.0

Gain (M) 1
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4

Peak Gain Q
10~20% of Mmax Maximum Operation Figure 14. Peak Gain (Attainable Maximum Gain)
Gain vs. Q for Different m Values
(Mmax)

fo fs
Figure 13. Determining the Maximum Gain

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 • 3/22/11 6
AN-9730 APPLICATION NOTE

Features of FLS-XS Series Table 1. Pin Description

FLS-XS series is an integrated Pulse Frequency Pin# Name Description
Modulation (PFM) controller and MOSFETs specifically
This pin is the drain of the high-side
designed for Zero Voltage Switching (ZVS) half-bridge
1 VDL MOSFET, typically connected to the
converters with minimal external components. The input DC link voltage.
internal controller includes an under-voltage lockout,
This pin is for discharging the external
optimized high-side / low-side gate driver, temperature-
soft-start capacitor when any
compensated precise current controlled oscillator, and protections are triggered. When the
self-protection circuitry. Compared with discrete 2 AR
voltage of this pin drops to 0.2V, all
MOSFET and PWM controller solutions, FLS-XS series protections are reset and the controller
can reduce total cost, component count, size, and weight; starts to operate again.
while simultaneously increasing efficiency, productivity, This pin is to program the switching
and system reliability. frequency. Typically, opto-coupler and
3 RT
resistor are connected to this pin to
regulate the output voltage.
This pin is to sense the current flowing
through the low-side MOSFET.
4 CS
Typically negative voltage is applied
on this pin.
5 SG This pin is the control ground.
This pin is the power ground. This pin
6 PG is connected to the source of the low-
side MOSFET.
This pin is the supply voltage of the
7 LVCC
control IC.
8 NC No connection.
Figure 15. Package Diagram This pin is the supply voltage of the
9 HVCC
high-side drive circuit.
This pin is the drain of the low-side
10 VCTR MOSFET. Typically transformer is
connected to this pin.

Figure 16. Functional Block Diagram of FSFR-Series

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 • 3/22/11 7
AN-9730 APPLICATION NOTE

FLS-XS
Series

Figure 17. Reference Circuit for Design Example of LLC Resonant Half-Bridge Converter

Design Procedure
In this section, a design procedure is presented using the
Even though the input voltage is regulated as constant by
schematic in Figure 17 as a reference. An integrated
PFC pre-regulator, it drops during the hold-up time. The
transformer with center tap, secondary side is used and
minimum input voltage considering the hold-up time
input is supplied from Power Factor Correction (PFC) pre-
requirement is given as:
regulator. A DC-DC converter with 160W/115V output has
been selected as a design example. The design 2 PinTHU
specifications are as follows: Vin min = VO.PFC 2 − (13)
CDL
Nominal input voltage: 400VDC (output of PFC stage)
where VO.PFC is the nominal PFC output voltage, THU is
Output: 115V/1.4A (160W) a hold-up time, and CDL is the DC link bulk capacitor.
Hold-up time requirement: 30ms (50Hz line freq.)
DC link capacitor of PFC output: 240µF (Design Example) Assuming the efficiency is 92%,
P 161
[STEP-1] Define System Specifications Pin = o = = 175W
E ff 0.92

Estimated Efficiency (Eff): The power conversion Vin max = VO.PFC = 400V
efficiency must be estimated to calculate the maximum min 2 2 PinTHU
input power with a given maximum output power. If no Vin = VO.PFC −
reference data is available, use Eff = 0.88~0.92 for low- CDL
voltage output applications and Eff = 0.92~0.96 for high- 2 ⋅ 175 ⋅ 30 × 10 −3
voltage output applications. With the estimated efficiency, = 400 2 − = 341V
the maximum input power is given as: 240 × 10 −6

Po [STEP-2] Determine Maximum and Minimum

Pin = (11) Voltage Gains of the Resonant Network
E ff
Input Voltage Range (Vinmin and Vinmax): The maximum As discussed in the previous section, it is typical to operate
input voltage would be the nominal PFC output voltage as: the LLC resonant converter around the resonant frequency
(fo) to minimize switching frequency variation. Since the
Vin max = VO. PFC (12) input of the LLC resonant converter is supplied from PFC
output voltage, the converter should be designed to operate
at fo for the nominal PFC output voltage.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 • 3/22/11 8
AN-9730 APPLICATION NOTE

As observed in Equation (10), the gain at fo is a function of [STEP-4] Calculate Equivalent Load Resistance
m (m=Lp/Lr). The gain at fo is determined by choosing that
value of m. While a higher peak gain can be obtained with With the transformer turns ratio obtained from Equation
a small m value, too small m value results in poor coupling (16), the equivalent load resistance is obtained as:
of the transformer and deteriorates the efficiency. It is 8n 2 Vo 2
Rac = (17)
typical to set m to be 3~7, which results in a voltage gain π 2 Po
of 1.1~1.2 at the resonant frequency (fo). (Design Example)
With the chosen m value, the voltage gain for the nominal 8n 2 (Vo + V F ) 2 8 ⋅ 1.93 2 ⋅ 115.9 2
PFC output voltage is obtained as: Rac = = = 252Ω
π2 Po π 2 ⋅ 161
m @f=f
M min = o (14) [STEP-5] Design the Resonant Network
m −1
With m value chosen in STEP-2, read proper Q value from
which would be the minimum gain because the nominal the peak gain curves in Figure 14 that allows enough peak
PFC output voltage is the maximum input voltage (Vinmax). gain. Considering the load transient and stable zero-
The maximum voltage gain is given as: voltage-switching (ZVS) operation, 10~20% margin should
be introduced on the maximum gain when determining the
Vin max min peak gain. Once the Q value is determined, the resonant
M max = M (15) parameters are obtained as:
Vin min
1
Cr = (18)
2π Q ⋅ f o ⋅ Rac
(Design Example) The ratio (m) between Lp and Lr is
chosen as 5. The minimum and maximum gains are 1
Lr = (19)
obtained as: (2π f o ) 2 Cr
V RO m 5 L p = m ⋅ Lr
M min = = = = 1.12 (20)
Vin max m −1 5 −1
2
Vin max 400 (Design Example)
M max = m min = ⋅ 1.12 = 1.31
Vin min 341 As calculated in STEP-2, the maximum voltage gain
(M max) for the minimum input voltage (Vinmin) is 1.31. With
Gain (M) Peak Gain 15% margin, a peak gain of 1.51 is required. m has been
(Available Maximum Gain) chosen as 5 in STEP-2 and Q is obtained as 0.38 from the peak
1.31 gain curves in Figure 19. By selecting the resonant frequency
Mmax for VINmin
as 100kHz, the resonant components are determined as:
1 1
Cr = = = 16.64nF
for 2πQ ⋅ f o ⋅ Rac 2π ⋅ 0.38 ⋅ 100 × 10 3 ⋅ 252
1.12 VINmax 1 1
Mmin Lr = = = 152uH
( VO.PFC ) 2
(2πf o ) C r ( 2π × 100 × 10 ) ⋅ 16.64 × 10 −9
3 2

L p = m ⋅ Lr = 760uH
m
M = = 1.12
m −1

fs
fo
Figure 18. Maximum Gain / Minimum Gain

[STEP-3] Determine the Transformer Turns

Ratio (n=Np/Ns)
With the minimum gain (Mmin) obtained in STEP-2, the
transformer turns ratio is given as:
Np Vin max
n= = ⋅ M min (16)
Ns 2(Vo + VF )
where VF is the secondary-side rectifier diode voltage drop.

(Design Example) assuming VF is 0.9V,

Np Vin max 400 Figure 19. Resonant Network Design Using the Peak Gain
n= = ⋅ M min = ⋅1.12 = 1.93 (Attainable Maximum Gain)
Ns 2(VO + V F ) 2(115 + 0.9)
Curve for m=5

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 • 3/22/11 9
AN-9730 APPLICATION NOTE

[STEP-6] Design the Transformer

The worst case for the transformer design is the minimum
switching frequency condition, which occurs at the
minimum input voltage and full-load condition. To obtain
the minimum switching frequency, plot the gain curve
using gain Equation 9 and read the minimum switching
frequency. The minimum number of turns for the
transformer primary-side is obtained as:
n(Vo + VF )
N p min = (21)
2 f s min ⋅ M V ⋅ ∆B ⋅ Ae
where Ae is the cross-sectional area of the transformer
core in m2 and ∆B is the maximum flux density swing in
Tesla, as shown in Figure 20. If there is no reference
data, use ∆B =0.3~0.4 T.

n (Vo+VF)/MV Figure 21. Gain Curve

VRI 1/(2fs)
[STEP-7] Transformer Construction
Parameters Lp and Lr of the transformer were determined in
-n (Vo+VF)/MV STEP-5. Lp and Lr can be measured in the primary side
with the secondary-side winding open circuited and short
circuited, respectively. Since LLC converter design
requires a relatively large Lr, a sectional bobbin is typically
∆B used, as shown in Figure 22, to obtain the desired Lr value.
B For a sectional bobbin, the number of turns and winding
configuration are the major factors determining the value of
Lr, while the gap length of the core does not affect Lr much.
Figure 20. Flux Density Swing
Lp can be controlled by adjusting the gap length. Table 2
Choose the proper number of turns for the secondary side shows measured Lp and Lr values with different gap
that results in primary-side turns larger than Npmin as: lengths. A gap length of 0.05mm obtains values for Lp and
Lr closest to the designed parameters.
N p = n ⋅ N s > N p min (22)
Np
N s2
N s1
(Design Example) EER3542 core (Ae=107mm2) is
selected for the transformer. From the gain curve of
Figure 21, the minimum switching frequency is obtained
as 82KHz. The minimum primary-side turns of the
transformer is given as:
n(Vo + V F )
N p min = min
2 f s ∆B ⋅ 1.11 ⋅ Ae
1.93 × 115.9 Figure 22. Sectional Bobbin
= = 29 turns
2 × 82 × 10 3 ⋅ 0.4 ⋅ 1.11 ⋅ 107 × 10 −6

Choose Ns so that the resultant Np is larger than Npmin: Table 2. Measured Lp and Lr with Different Gap Lengths
min
N p = n ⋅ N s = 1.93 × 14 = 27 < N p Gap Length Lp Lr
N p = n ⋅ N s = 1.93 × 15 = 29 < N p min 0.0mm 2,295µH 123µH
N p = n ⋅ N s = 1.93 × 16 = 31 > N p min 0.05mm 943µH 122µH
0.10mm 630µH 118µH
N p = n ⋅ N s = 1.93 × 17 = 33 > N p min
0.15mm 488µH 117µH
N p = n ⋅ N s = 1.93 × 18 = 35 > N p min 0.20mm 419µH 115µH
N p = n ⋅ N s = 1.93 × 19 = 37 > N p min 0.25mm 366µH 114µH

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 • 3/22/11 10
AN-9730 APPLICATION NOTE

The nominal voltage of the resonant capacitor in normal

(Design Example)
operation is given as:
Final Resonant Network Design
Vin max 2 ⋅ I Cr RMS
Even though the integrated transformer approach in LLC VCr nom ≅ + (24)
resonant converter design can implement the magnetic 2 2 ⋅ π ⋅ fo ⋅ Cr
components in a single core and save one magnetic However, the resonant capacitor voltage increases higher
component, the value of Lr is not easy to control in real than this at overload condition or load transient. Actual
transformer design. Resonant network design sometimes capacitor selection should be based on the Over-Current
requires iteration with a resultant Lr value after the Protection (OCP) trip point. With the OCP level, IOCP,
transformer is built. The resonant capacitor value is also the maximum resonant capacitor voltage is obtained as:
changed since it should be selected among off-the-shelf
capacitors. The final resonant network design is Vin max I OCP
VCr nom ≅ + (25)
summarized in Table 3 and the new gain curves are shown 2 2 ⋅ π ⋅ f o ⋅ Cr
in Figure 23.
Table 3. Final Resonant Network Design Parameters (Design Example)

Parameters Initial Design Final Design 1 πI O n(Vo + VF )

I Cr RMS ≅ [ ]2 + [ ]2
Lp 760µH 625µH E ff 2 2n 4 2 f o M v ( L p − Lr )
Lr 152H 125µH
1 π ⋅ 1.4 2 1.93(115 + 0.9)
Cr 16.64nF 22nF = [ ] +[ ]2
fo 100kHz 96kHz
0.92 2 2 ⋅ 1.93 4 2 ⋅ 96 × 10 3 ⋅ 1.12 ⋅ 500 × 10 − 6
m 5 5 =1.18A
Q 0.38 0.3
M@fo 1.12 1.12 The peak current in the primary side in normal operation is:
peak
Minimum I Cr = 2 ⋅ I Cr rms = 1.67 A
75kHz 74.4kHz
Frequency
OCP level is set to 2.5A with 50% margin on ICrpeak:
RMS
Vin max 2 ⋅ I Cr
VCr nom ≅ +
2 2 ⋅ π ⋅ f o ⋅ Cr
400 2 ⋅ 1.18
= + = 326V
2 2 ⋅ π ⋅ 96 × 10 3 ⋅ 22 × 10 −9
Vin max I OCP
VCr max ≅ +
2 2 ⋅ π ⋅ f o ⋅ Cr
Gain

400 2.5
= + = 388.5V
2 2 ⋅ π ⋅ 96 × 10 3 ⋅ 22 × 10 −9
A 630V rated low-ESR film capacitor is selected for the
resonant capacitor.

[STEP-9] Rectifier Network Design

When the center tap winding is used in the transformer
secondary side, the diode voltage stress is twice of the
Figure 23. Gain Curve of the Final Resonant
output voltage expressed as:
Network Design
VD = 2(Vo + VF ) (26)
[STEP-8] Select the Resonant Capacitor
The RMS value of the current flowing through each
When choosing the resonant capacitor, the current rating rectifier diode is given as:
should be considered because a considerable amount of
current flows through the capacitor. The RMS current π
I D RMS = Io (27)
through the resonant capacitor is given as: 4
Meanwhile, the ripple current flowing through output
RMS 1 π Io 2 n(Vo + VF ) capacitor is given as:
I Cr ≅ [ ] +[ ]2 (23)
E ff 2 2n 4 2 fo M V ( Lp − Lr )
π Io π2 −8
ICo RMS = ( )2 − I o 2 = Io (28)
2 2 8

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 • 3/22/11 11
AN-9730 APPLICATION NOTE

The voltage ripple of the output capacitor is:

π
∆Vo = I o ⋅ RC (29)
2
where RC is the effective series resistance (ESR) of the
output capacitor and the power dissipation is the output
capacitor is:

PLoss .Co = ( ICo RMS )2 ⋅ RC (30)

(Design Example) The voltage stress and current stress of

the rectifier diode are:

V D = 2(Vo + V F ) = 2(115 + 0.9) = 231.8V

π Figure 24. Typical Circuit Configuration for RT Pin
I D RMS = I o = 1.1A
4 Soft-Start To prevent excessive inrush current and
The 600V/8A Ultra fast recovery diode is selected for the overshoot of output voltage during startup, increase the
rectifier, considering the voltage overshoot caused by the voltage gain of the resonant converter progressively. Since
stray inductance. the voltage gain of the resonant converter is reversely
The RMS current of the output capacitor is: proportional to the switching frequency, soft-start is
implemented by sweeping down the switching frequency
πI o π 2 −8 from an initial high frequency (f ISS) until the output voltage
I Co RMS = ( )2 − Io2 = I o = 0.675 A
2 2 8 is established, as illustrated in Figure 25. The soft-start
When two electrolytic capacitors with ESR of 100mΩ are circuit is made by connecting RC series network on the RT
used in parallel, the output voltage ripple is given as: pin as shown in Figure 24. FLS-XS series also has an
π π 0.1 internal soft-start for 3ms to reduce the current overshoot
∆V o = I o ⋅ RC = ⋅ 1.4 ⋅ ( ) = 0.1V during the initial cycles, which adds 40KHz to the initial
2 2 2
The loss in electrolytic capacitors is: frequency of the external soft-start circuit, as shown in
Figure 25. The actual initial frequency of the soft-start is
PLoss ,Co = ( I Co RMS ) 2 ⋅ RC = 0.675 2 ⋅ 0.05 == 0.02W
given as:
5.2k Ω 5.2k Ω
[STEP-10] Control Circuit Configuration f ISS = ( + ) × 100 + 40 (kHz ) (33)
Rmin RSS
Figure 24 shows the typical circuit configuration for the RT
It is typical to set the initial frequency of soft-start (f ISS) as
pin of FLS-XS series, where the opto-coupler transistor is
2~3 times of the resonant frequency (fo).
connected to the RT pin to control the switching frequency.
The minimum switching frequency occurs when the opto- The soft-start time is determined by the RC time constant:
coupler transistor is fully tuned off, which is given as:
TSS = 3 ~ 4 times of RSS ⋅ CSS (34)
5.2k Ω
f min = × 100( kHz ) (31)
Rmin
Assuming the saturation voltage of opto-coupler
transistor is 0.2V, the maximum switching frequency is
determined as:
5.2k Ω 4.68k Ω
f max = ( + ) × 100(kHz ) (32)
Rmin Rmax

Figure 25. Frequency Sweep of the Soft-Start

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 • 3/22/11 12
AN-9730 APPLICATION NOTE

(Design Example) The minimum frequency is 75kHz in (Design Example) Since the OCP level is determined as
STEP-6. Rmin is determined as: 2.5A in STEP-8 and the OCP threshold voltage is -0.6V, a
100 KHz sensing resistor of 0.24Ω is used. The RC time constant is
Rmin = × 5.2 KΩ = 6.93KΩ
f min set to 100ns (1/100 of switching period) with 1kΩ resistor
Considering the output voltage overshoot during transient and 100pF capacitor.
(10%) and the controllability of the feedback loop, the
maximum frequency is set as 140kHz. Rmax is determined as: [STEP-12] Voltage and Current Feedback
4.68 KΩ Power supplies for LED lighting must be controlled by
Rmax =
f o × 1.40 5.2 KΩ Constant Current (CC) Mode as well as a Constant Voltage
( − )
100 KHz Rmin (CV) Mode. Because the forward-voltage drop of LED
4.68KΩ varies with the junction temperature and the current also
= = 7.88KΩ increases greatly consequently, devices can be damaged.
96 KHz × 1.40 5.2 KΩ
( − ) Figure 28 shows an example of a CC and CV Mode
100 KHz 6.93KΩ
Setting the initial frequency of soft-start as 250kHz feedback circuit for single output LED power supply.
(2.5 times of the resonant frequency), the soft-start resistor During normal operation, CC Mode is dominant and CV
RSS is given as: control circuit does not activate as long as the feedback
voltage is lower than reference voltage, which means that
5.2 KΩ CV control circuit only acts as OVP for abnormal modes.
RSS =
f ISS − 40 KHz 5.2 KΩ
( − )
100 KHz Rmin (Design Example) The output voltage (VO) is 115V in
5.2 KΩ design target. VO is determined as:
= = 3.85KΩ
250 KHz − 40 KHz 5.2 KΩ R FU
( − )
100 KHz 6.93KΩ Vo = 2.5(1 + )
R FL
Set the upper-side feedback resistance (RFU) as 330KΩ.
[STEP-11] Current Sensing and Protection RFL is determined as:
FLS-XS series senses low-side MOSFET drain current as a 2.5 × R FU 2.5 × 330 KΩ
R FL = = = 7.33KΩ
negative voltage, as shown in Figure 26 and Figure 27. (Vo − 2.5) (115 − 2.5)
Half-wave sensing allows low-power dissipation in the
sensing resistor, while full-wave sensing has less switching The output voltage of op-amp is given as:
noise in the sensing signal. Typically, RC low-pass filter is Vsense V REF
used to filter out the switching noise in the sensing signal. + + sC 201 ⋅ VOC
The RC time constant of the low-pass filter should be 0 = R 201 R 203
1 1
1/100~1/20 of the switching period. + + sC 201
R 201 R 203
Cr 1 V V
VOC = − ( sense + REF )
sC 201 R 201 R 203
Np Ns
Actually, the Vsense has a negative value and assume all
Ns resistors have the same value for simplification;
Control 1
IC VOC = − (Vsense − VREF )
V CS
I DS sC 201 × R
CS

SG PG
The output voltage of the op-amp for CC control keeps zero
R sense
voltage as long as the sensing voltages are lower than the
VCS reference voltage.
IDS

VAUX VOUT

Figure 26. Half-Wave Sensing Rbias

C201 R202 R201

Current
Feedback
VREF=2.5V
VOC R203
1N4148 KA431
1K

1N4148 RFU
C202 R205
R204

VOV

RFL

Figure 28. Example of CC and CV Feedback Circuit

Figure 27. Full-Wave Sensing
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.0 • 3/22/11 13
AN-9730 APPLICATION NOTE

Figure 29 shows another example of a CC and Over- increase output power. This can cause SLP or thermal
Voltage Regulation (OVR) Mode feedback circuit for stress problems in the other channel. OLP function has
multi-output LED power supply. The FAN7346 is a LED auto-recovery: As soon as drain voltage is higher than
current-balance controller that controls four LED arrays to 0.3V, OLP is finished and drain voltage feedback system is
maintain equal LED current. To prevent LED driving restored.
voltage being over the withstanding voltage of component,
To sense over-current condition, the FAN7346 monitors
the FAN7346 controls LED driving voltage. The OVR
FBx pin voltage. If FBx voltage is higher than 1V for 20µs,
control circuit activates when the ENA pin is in HIGH
CHx is considered in over-current condition. After sensing
state. If OVR pin voltage is lower than 1.5V, the Feedback
OCP condition, individual channel switch is latched off.
Control (FB) pin voltage follows headroom control to
So, even if a channel is in OCP condition, other channels
maintain minimum voltage of drain voltages as 1V. If OVR
keep operating. Any OCP channel is restarted after UVLO
pin voltage is higher than 1.5V, the FAN7346 controls FB
is reset.
(FB is pulled LOW) through FB regulation so the OVR pin
voltage is not over 1.5V.

LED current is controlled by FBx pin voltage. The external (Design Example) The output voltage (VO) is 115V in
current balance switch is operating in linear region to design target. VO is determined as:
control LED current. Sensed voltage at the FBx pin is
R8
compared with internal reference voltage and controller Vo = 1.5(1 + )
signals the gate (or base) for external current balance R10
switch. Internal reference voltage is made from ADIM Set the upper-side feedback resistance (R8) as 1MΩ. R10
voltage. The LED current is determined as: is determined as:

V ADIM 1.5 × R8 1.5 × 1MΩ

I LED = R10 = = = 13.2 KΩ
10 × RSENSE (35) (Vo − 1.5) (115 − 1.5)

ADIM voltage is clamped internally from 0.5V to 4V. The The output channel current (ILED) is 350mA in design target.
protections; such as open LED Protection (OLP), Short Setting the VADIM is above 4V, the current sense RSENSE is
LED Protection (SLP), and Over-Current Protection determined as:
(OCP); which increase system reliability, are applied in V ADIM 4V
individual string protection method. RSENSE = = = 1.14Ω
10 × I LED 10 × 350mA
To sense a short LED condition, the FAN7346 senses drain
voltage level. If LEDs are shorted, the LED forward Choose the sense resistor (R29,R30,R31, and R32) is
voltage is lower than other LED strings, so its drain voltage 1.2 Ω , the OCP level is determined as:
of external balance switch is higher than other drain VOCP _ TH 1V
voltage. The SLP condition detection threshold voltage can I OCP = = = 833mA
RSENSE 1.5Ω
be programmed by SLPR voltage. The internal short LED
protection reference is determined as:
VSLP _ TH = 10 × VSLPR (36) VLED

Minimum SLP threshold voltage is 0V and maximum SLP RS8

threshold voltage is 45V. If any string is in SLP condition, CS6 RS10

SLP string is turned off and other string is operated

normally. If the sensed drain voltage (CHx voltage) is REF
OVR

higher than the programmed threshold voltage for 20µs, RS12

CH1
OUT1
RS11
Q1

CHx goes to short LED protection. As soon as PC101

FB1
CH2
RS16
encountering SLP, the corresponding channel is forced off. RS22
FB OUT2
FB2
Q2

PWM1
CH3 RS23
RS18
To sense an open LED condition, the FAN7346 senses RS17
PWM2 OUT3
FB3
Q3

PWM3
drain voltage level. If LED string is opened, its drain RS15

PWM4 OUT4
CH4
RS25
Q4
RS14

voltage of external balance switch is grounded, so the PWM5

FB4
RS19

CS13
RS21

RS20

CS10

CS11

RS32
CS7

RS29

RS30

RS31

FAN7346 detects the open-LED condition. The detection ENA

threshold voltage is 0.3V. If CHx voltage is lower than SLPR

ADIM
GND

0.3V for 20µs, its drain voltage feedback is pulled up to CMP VDD
RS13 CS9

VCC VCC
5V. This means the opened LED string is eliminated from
RS24

CS12

CS15

CS14
RS28

RS27

CS8

drain feedback loop. Without OLP, minimum drain voltage

is 0V, so drain voltage feedback forces the FB signal to Figure 29. Example of CC and OVR Feedback Circuit

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 • 3/22/11 14
AN-9730 APPLICATION NOTE

Design Summary
design example. EER3543 core with sectional bobbin is
Figure 30 and Figure 31 show the final schematic of the used for the transformer. Efficiency at full-load is around
LLC resonant half-bridge converter for LED lighting 94%.

Figure 30. Final Schematic of Half-Bridge LLC Resonant Converter for Single Channel

CS7

CS11
RS11

CS10

RS30
RS23

RS25

CS13

RS32
RS29
RS16

RS31
FLS-XS
Series

FAN7346
OVR
CH1
OUT1

FB1

CH2
OUT2

FB2

CH3
OUT3

FB3

CH4
OUT4

FB4
GND
VCC
PWM5

PWM4

PWM3

PWM2

PWM1

SLPR

ADIM
VMIN

ENA
REF

FB
RS14

RS15

RS17

RS18

RS22

Figure 31. Final Schematic of Half-Bridge LLC Resonant Converter for Multi Channel

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

Rev. 1.0.0 • 3/22/11 15
AN-9730 APPLICATION NOTE

VCR [200V/div]
320V
Experimental Verification
To show the validity of the design procedure presented in
this application note, the converter of the design example IP [2A/div] 1.7A
was built and tested. All the circuit components are used as
designed in the design example.
Figure 32 and Figure 33 show the operation waveforms at
full-load and no-load conditions for nominal input voltage.
As observed, the MOSFET drain-to-source voltage (VDS)
drops to zero by resonance before the MOSFET is turned VDS [200V/div] Time (5µs/div)
on and zero voltage switching is achieved.
Figure 34 shows the waveforms of the resonant capacitor Figure 34. Resonant Capacitor Voltage and Primary-
voltage and primary-side current at full-load condition. The Side Current Waveforms at Full-Load Condition
peak values of the resonant capacitor voltage and primary-
side current are 320V and 1.7A, respectively, which are IP [1A/div]
well matched with the calculated values in STEP-8 of
design procedure section.
Figure 35 shows the rectifier diode voltage and current
waveforms at full-load condition. Due to the voltage
overshoot caused by stray inductance, the voltage stress is ID [1A/div]
257V
a little bit higher than the value calculated in STEP-9.
Figure 36 shows the output load current and output voltage
of op-amp waveforms for constant-current control when
output load is step changed from 240mA to 1400mA at t0.
VD [100V/div]
Time (5µs/div)
Figure 37 shows the operation waveform when LED string
is opened and restored condition Figure 35. Rectifier Diode Voltage and Current
Waveforms at Full-Load Condition
IP [2A/div]

VOP_CC [2V/div]
IDS [1A/div]

1400mA

VDS [200V/div]

240mA CC Control Mode

t0 t1
Time (5µs/div)
ILOAD [0.5A/div]
Time (50ms/div)

Figure 32. Operation Waveforms at Full-Load Condition

Figure 36. Constant-Current Control Waveforms
IP [2A/div]
VLED
[100V/div]
Open LED Restore LED

IDS [1A/div]
VDS_NORMAL_LED
[500mV/div]
VDS [200V/div]

VDSD_OPEN_LED
[500mV/div]

Time (5µs/div)
Figure 37. Open LED Protection Operation

Figure 33. Operation Waveforms at No-Load Condition

References
[1] Robert L. Steigerwald, “A Comparison of Half-bridge [7] M. Emsermann, “An Approximate Steady State and Small
resonant converter topologies,” IEEE Transactions on Signal Analysis of the Parallel Resonant Converter Running
Power Electronics, Vol. 3, No. 2, April 1988. Above Resonance,” Proc. Power Electronics and Variable
Speed Drives ’91, 1991, pp. 9-14.
[2] A. F. Witulski and R. W. Erickson, “Design of the series
resonant converter for minimum stress,” IEEE Transactions [8] Yan Liang, Wenduo Liu, Bing Lu, van Wyk, J.D, “Design
on Aerosp. Electron. Syst., Vol. AES-22, pp. 356-363, of integrated passive component for a 1MHz 1kW half-
July 1986. bridge LLC resonant converter,” IAS 2005, pp. 2223-2228.
[3] R. Oruganti, J. Yang, and F.C. Lee, “Implementation of [9] B. Yang, F.C. Lee, M. Concannon, “Over-current protection
Optimal Trajectory Control of Series Resonant Converters,” methods for LLC resonant converter” APEC 2003, pp. 605 - 609.
Proc. IEEE PESC ’87, 1987. [10] Yilei Gu, Zhengyu Lu, Lijun Hang, Zhaoming Qian,
Guisong Huang, “Three-level LLC series resonant DC/DC
[4] V. Vorperian and S. Cuk, “A Complete DC Analysis of the
converter,” IEEE Transactions on Power Electronics
Series Resonant Converter,” Proc. IEEE PESC’82, 1982.
Vol.20, July 2005, pp.781 – 789.
[5] Y. G. Kang, A. K. Upadhyay, D. L. Stephens, “Analysis and [11] Bo Yang, Lee, F.C, A.J Zhang, Guisong Huang, “LLC
design of a half-bridge parallel resonant converter operating resonant converter for front-end DC/DC conversion,” APEC
above resonance,” IEEE Transactions on Industry 2002. pp.1108 – 1112.
Applications, Vol. 27, March-April 1991, pp. 386 – 395.
[12] Bing Lu, Wenduo Liu, Yan Liang, Fred C. Lee, Jacobus D.
[6] R. Oruganti, J. Yang, and F.C. Lee, “State Plane Analysis of Van Wyk, “Optimal design methodology for LLC Resonant
Parallel Resonant Converters,” Proc. IEEE PESC ’85, 1985. Converter,” APEC, 2006, pp.533-538.

This application note written based on Fairchild Semiconductor Application Note AN-4137.

Related Datasheets
FLS1800XS — Half-Bridge LLC Resonant Control IC for Lighting
FLS2100XS — Half-Bridge LLC Resonant Control IC for Lighting
FAN7346 — 4-Channel LED Current Balance Control IC

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Rev. 1.0.0 • 3/22/11 17
Application Report
SLUA582A – October 2010 – Revised November 2010

Feedback Loop Design of an LLC Resonant Power

Converter
Hong Huang ......................................................................................... Power-Supply Control Products

ABSTRACT
This application note describes an approach to design feedback loop compensation for an LLC resonant
half-bridge power converter. The approach described here is based on the measured Bode plots of the
modulator generated by a network analyzer. As we know, as long as the modulator Bode plots are
obtained, the frequency domain poles and zeros in the feedback loop compensation can be analytically
determined, then fine-tuned with a bench test. This measurement is necessary as part of feedback loop
design because a practical small-signal model is not available for LLC resonant converters. This document
uses the Texas Instruments' UCC25600 as the frequency controller. A detailed description of the
UCC25600 and its associated example design fixture, the UCC25600EVM-341, can be found in the
product data sheet and the evaluation module user’s guide, respectively; both additional documents are
available for download at www.ti.com.

Contents
1 Control Loop Description of an LLC Converter ......................................................................... 2
2 Loop Compensation Design Approach ................................................................................... 4
3 Methodology ................................................................................................................. 5
4 References ................................................................................................................... 8

List of Figures
1 Block Diagram of a Typical LLC Resonant Half-Bridge Converter ................................................... 2
2 Another Way to Define Gm(w) and Gc(w) ................................................................................. 3
3 Initial Gm(w) Measurement ................................................................................................. 6
4 Re-Measurement of Gm(w) ................................................................................................. 7
5 Design of Gc(w) .............................................................................................................. 7
6 Feedback Loop Bode Plots After Final Values Set ..................................................................... 8

SLUA582A – October 2010 – Revised November 2010 Feedback Loop Design of an LLC Resonant Power Converter 1
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1 Control Loop Description of an LLC Converter

NOTE: For complete details on the design of an LLC resonant power converter, the recommended
reference is SEM1900 Topic 3, Designing an LLC Resonant Half-Bridge Power Converter.
This application note will not repeat the discussion of these details.

Figure 1 shows a typical block diagram of an LLC resonant converter.

Q1
Vin
T1
Lr D1 Vout
n:1:1

FBO
Lm
Q2
RSC VSC
D2
Cr

Vr FBR

C1 R1
R2
VS
UCC25600
R4
RT FBC R3
Gate -
Drive fSW
Control RX
Frequency Vref
Modulator
R5 CTR

Gc(s)
Gm(s)

Figure 1. Block Diagram of a Typical LLC Resonant Half-Bridge Converter

This diagram consists of two blocks: the modulator and the compensator, expressed in the respective
transfer functions of Gm(s) and Gc(s), or Gm(jw) and Gc(jw). In Figure 1, the red outline defines the Gm(s)
transfer function, and the blue outline defines the Gc(s) transfer function.
Gm(w) and Gc(w) can be used to express Gm(jw) and Gc(jw) respectively in shorthand, where j = √–1 can
be omitted without confusion. Then the loop gain transfer function Glp(s), or Glp(w), is expressed as
Equation 1.
V (s)
Glp(s) = out = Gc(s) · Gm(s)
Vr(s)
(1)
or as Equation 2:
V (w)
Glp(w) = out = Gc(w) · Gm(w)
Vr(w)
(2)

2 Feedback Loop Design of an LLC Resonant Power Converter SLUA582A – October 2010 – Revised November 2010
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Both Gm(w) and Gc(w) can be measured with a frequency sweeping signal applied on resistor RSC, as
these equations show:
Gm(w) = FBO
FBC
(3)

Gc(w) = FBC
FBR
(4)
The loop gain transfer function Glp(w) is measurable and obtained as Equation 5.
Glp(w) = FBO
FBR
(5)
It is obvious that FBC can be assigned at different locations in the converter circuit. For example, it can be
moved to the optocoupler input as Figure 2 illustrates. Here, the red area and the blue area represent the
Gm(w) and Gc(w) functions, respectively, as they do in Figure 1.

Q1
Vin
T1
Lr D1 Vout
n:1:1

FBO
Lm
Q2
RSC VSC
D2
Cr

Vr FBR

C1 R1
R2
VS
UCC25600
R4
RT R3
Gate - FBC
Drive fSW
Control RX
Frequency Vref
Modulator
R5 CTR

Gm(w)
Gc(w)

Figure 2. Another Way to Define Gm(w) and Gc(w)

In this position, then, the measured Gm(w) and Gc(w) are different from those measured in Figure 1.
Note that it is possible to define Gm(w) and Gc(w) in several different ways. But Glp(w) will be the same,
regardless of how Gm(w) and Gc(w) are defined. In this document, we use the definition as shown in
Figure 1 to avoid confusion.

SLUA582A – October 2010 – Revised November 2010 Feedback Loop Design of an LLC Resonant Power Converter 3
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2 Loop Compensation Design Approach

Unlike Gm(w), Gc(w) can be expressed analytically. As shown in Figure 1, if we use Type I compensation,
then Gc(w) is expressed as Equation 6:
s
1 +1
R1· C1
Gc(s) =
s s
( +1
(
w · w
I p_opto

(6)
Where wp_opto is the angular frequency of the optocoupler frequency-domain pole. This value can be
typically considered to be approximately wp_opto = 2p ×10 kHz, although the value varies with the particular
optocoupler in the circuit as well as with the bias point. CTR is the optocoupler current transfer ratio; the
angular frequency wI is the gain of the frequency domain pole at origin; and therefore, we arrive at:
R4 · CTR
wI =
R3 · R2 · C1
(7)
The angular frequency wI is the 0-dB crossover of Gc(w) when we set R1 = 0 and ignore wp_opto at a
low-frequency range. In fact:
jw
+1
1
R1· C1 with: R1 = 0 1 wI
Gc(s) = Gc(w) = jw =
jw jw w << w p_opto j w
( +1
( wI
w · w
I p_opto

(8)
If we let |Gc(w)| = 1, then:
wI
|Gc(w)| = = 1 ® w = wI
jw
(9)
To compensate the LLC converter feedback loop, Gm(w) must first be obtained by measurement. To make
Gm(w) measurable, the feedback loop must be stable, which is our design goal yet to be achieved. So we
are now in a circle that we must break in order to achieve our design goal. To break this circle, one
common technique is to use a large-value capacitor for C1 in Figure 1 to push the loop bandwidth (that is,
the gain crossover frequency) low enough in the expectation that the loop can be stable enough for initial
measurement. This idea is workable and allows us to obtain initial Gm(w) value. Sometimes, though, we
may be confused about how large a capacitor is adequate for a specific application in order to make a
stable Gm(w) measurement. If an estimated C1 value is not sufficient, we have a potential risk that the
resulting loop may not be stable to measure Gm(w), and potential circuit damage can occur.
To avoid these issues, we propose a more reliable approach that combines with the practice of using an
initial low bandwidth measurement from a large value C1. As we know, to maintain output voltage
regulation in an LLC resonant converter, the input voltage must be great enough to achieve the desired
output voltage. If the input voltage is not sufficient, the output voltage regulation cannot be achieved
because the maximum gain has already reached its limit. However, even if output regulation is not
achieved, the converter is stable, and this stability is not related to the feedback loop parameters. During
such an operation, bench tests show a Gm(w) can continue to be measured in the usual way. Although the
measured Gm(w) is not exactly the same as that obtained from an operation when the output comes into
regulation, it is sufficient to give us an idea of how large the value of C1 must be and how wI should be
designed. Then, we will be able to complete the remaining design and avoid the risks noted earlier.

4 Feedback Loop Design of an LLC Resonant Power Converter SLUA582A – October 2010 – Revised November 2010
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3 Methodology
To implement this approach, we first must make sure that all other segments of the converter work
properly, especially the associated power stage. This operation is usually called an open-loop test, which
must be passed to assure full functionality. Then we can close the feedback loop and measure Gc(w) in
this way:
• We first increase the input voltage slowly from zero and observe the output voltage.
Because the input voltage is low, the controller in the feedback loop will generate the maximum gain to
raise the output voltage as much to the point of regulation as it can.
• We then continue to increase the input voltage until the output voltage is close to the regulation (within
10%). At that point, we stop increasing the input voltage.
The converter should now be stable and quite independent of the feedback loop compensation
parameters.
• Then, we apply a frequency sweeping signal to RSC and measure the Bode plots between FBO and
FBC. This measurement gives us the initial Gm(w) value.
We can make several more measurements by further increasing the input voltage in 1% increments if
Gm(w) does not show good measurement results. However, do not risk increasing the voltage to bring the
output voltage into regulation yet.
Here, we offer an example to show how to make this type of initial Gm(w) measurement, then how to
design the subsequent feedback loop once the measurement is complete. We use the
UCC25600EVM-341 as our example with the corresponding circuit diagram shown in Figure 1. Complete
schematics for this device are found in the UCC25600EVM-341 User Guide.
This converter has these electrical specifications:
• Input voltage: 375 VDC to 405 VDC
• Output power (rated): 300 W
• Output voltage: 12 VDC
• Output current (rated): 25 A
• Output voltage line regulation (with IO = 1.0 A): ≤ 1%
• Output voltage load regulation (at VIN = 390 V): ≤ 1%
• Output voltage peak-to-peak ripple (at VIN = 390 V and IO = 25 A): ≤ 120 mV
• Efficiency (at VIN = 390 V and IO = 25 A): ≥ 90%
• Switching frequency: 70 kHz to 150 kHz in normal operation
• Converter topology: LLC resonant half-bridge converter

3.1 Procedure and Results

Step 1. Gm(w) measurement; C1 initial value.
In the expression:
R4 · CTR
wI =
R3 · R2 · C1
(10)
C1 is only the parameter we must determine initially for a stable Gm(w) measurement. The remaining
parameters are determined by other design factors and generally have a limited adjustable range. For
example, CTR is fixed after an optocoupler is selected. Additionally, R3 and R4 are determined by the
requirements of the frequency range and the optocoupler configuration.
The value of C1 is not critical from our proposed approach. For example, an initial C1 value can be
between 0.1 mF and 1 mF; this range is given only to show some commonly-used values. If C1 is
outside these values, the process should work. In this example, we use C1 = 1.0 mF (note that it does
not make much difference to use C1 = 0.1 mF).
Step 2. Gm(w) measurement with output voltage not in regulation.
As shown in Step 1, the output voltage regulation is 12 V with minimum input voltage 375 V. If we use
a voltage much lower than 375 V, the output voltage is not able to enter regulation. A good rule of
thumb is to use an input voltage low enough to keep the output voltage out of regulation, but close to

SLUA582A – October 2010 – Revised November 2010 Feedback Loop Design of an LLC Resonant Power Converter 5
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the regulation voltage; say, within 10%. This technique generally should give an acceptable
measurement. If it does not, a value closer to regulation may be tested, using a 1% increment each
time until a good measurement is obtained. In this example, when we slowly increase VIN to 285 V with
IO = 1 A, the output voltage showed to be approximately 11 V, which is 8.3% below 12 V. Then we
measured Gm(w) with an acceptable result. A 25-mV frequency sweeping signal was used during this
test. The Gm(w) measurement is shown in Figure 3.
UCC25600EVM MODULATOR PLOT (285 V, 1 A)

60 180

40 120

Phase (degrees)
20 60
Gain (dB)

0 0

-20 -60

-40 -120
Gain
Phase
-60 -180
10 100 1k 10 k 100 k 1M
Frequency (Hz)

Figure 3. Initial Gm(w) Measurement

Step 3. Determine initial Gc(w) based on Gm(w) measurement.

Now we need to design a proper Gc(w) to allow the converter output to enter into regulation. The
minimum switching frequency of the converter is specified at 70 kHz. As a rule of thumb, the gain
crossover frequency should be below one-fifth of its minimum switching frequency. If we use one-tenth
of its minimum switching frequency, that allows approximately 7 kHz to cover the entire operating
range. Keep in mind, though, that we are only at the beginning stages and our primary purpose is to
establish an initial operating point. The Gm(w) obtained so far is also a very preliminary value. As such,
we may want to make the target crossover frequency very conservative. Based on the measurement
just obtained, it appears acceptable to set the crossover frequency somewhere around 100 Hz. One
advantage to selecting 100 Hz is that it has a flat phase angle close to 0°; this response helps to
achieve the desired stability as a 90° phase margin can be expected at 100 Hz. Notice, again, this
target is only an initial design; the final desired value can be adjusted further.
At 100 Hz, | Gm(w) | = 28 dB. Therefore, we would need to design | Gc(w) | to have:
20log(| Gc(w) |)w = 2p × 100Hz = –28 dB
Because the crossover frequency of 100 Hz is a rough number to be used initially, we can simply do a
quick design with only wI while leaving out the zero of R1-C1 by making R1 = 0, such that the zero of
R1-C1 is pushed beyond its effect to the 100-Hz crossover.
-28
wI = 10 20 · 2p · 100(Hz) = 25.0 rad/s
(11)
R4 · CTR
wI =
R3 · R2 · C1
(12)
If C1 = 0.22 mF, we can obtain a wI =25.0 rad/s, or ƒI = 3.98 Hz, with a given CTR = 120%, R4 = 510 Ω,
R2 = 110 kΩ, and R3 = 1.00 kΩ.

6 Feedback Loop Design of an LLC Resonant Power Converter SLUA582A – October 2010 – Revised November 2010
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Step 4. Re-measurement of Gm(w).

Now we are confident enough to increase the input voltage so the output is in regulation, and then
make a stable measurement of Gm(w). The measured Gm(w) is shown in Figure 4, at 390-V input.
UCC25600EVM MODULATOR PLOT (TEST)

60 180

40 120

Phase (degrees)
20 60
Gain (dB)

0 0

-20 -60

-40 -120
Gain
Phase
-60 -180
10 100 1k 10 k 100 k 1M
Frequency (Hz)

Figure 4. Re-Measurement of Gm(w)

Certainly, one can make additional measurements between 280 V and 390 V, say in 20-V increments,
to gain confidence in what has already been obtained. An important note for test manipulation here is
that the input voltage increase should progress slowly until the feedback loop compensation is
complete. A slow increase of the input voltage can allow time for the designer to decide to stop if there
is any sign that the feedback loop may become unstable.
Step 5. Design Gc(w) based on measured Gm(w).
To achieve the crossover frequency of 7 kHz with a minimum 45° phase margin, Gc(w) would need to
be designed to achieve the Bode plot responses shown in Figure 5. This result can be easily
accomplished by arranging the pole and the zero shown in Equation 6. Below is one possible set of
parameters to achieve the illustrated Bode plots:
• R1 = 5.1 kΩ
• R2 = 19.7 kΩ
• R3 = 1.0 kΩ
• R4 = 510 Ω
• C1 = 0.22 mF
• CTR = 120%
GAIN OF TYPE I COMPENSATOR

40 180
32
24
100
16
Phase (degrees)

8
Gain (dB)

0 0
-8
-16
-100
-24
Gain
-32
Phase
-40 -180
10 100 1k 10 k 100 k 1M
Frequency (Hz)

Figure 5. Design of Gc(w)

SLUA582A – October 2010 – Revised November 2010 Feedback Loop Design of an LLC Resonant Power Converter 7
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Step 6. Bench testing and fine tuning.

The last step is to plug in the obtained parameter values to perform a bench test. Usually, fine tuning is
necessary to cover all operating conditions and to adapt to the parameters not modeled in the Gc(w) for
example parasitic variables.
The compensation values are finalized as R1=17.8 kΩ, R2 = 19.7 kΩ, R3 = 1.0 kΩ, R4 = 0.51 kΩ, and
C1 = 47 nF. Figure 6 shows the control loop Bode plots at VIN = 390 V, Vo = 12 V, and a 25-A load.
UCC25600EVM LOOP PLOT (TEST)

60 180

40 120

Phase (degrees)
20 60
Gain (dB)

0 0

-20 -60

-40 -120
Gain
Phase
-60 -180
10 100 1k 10 k 100 k 1M
Frequency (Hz)

Figure 6. Feedback Loop Bode Plots After Final Values Set

4 References
Unless otherwise noted, these documents are available for download from the TI website (www.ti.com).
1. UCC25600 Product data sheet. Texas Instruments literature number SLUS846.
2. UCC25600EVM User guide. Texas Instruments literature number SLUU361.
3. TI Power Supply Design Seminar SEM1900 Topic 3, Designing an LLC Resonant Half-Bridge Power
Converter. (2010-11). Texas Instruments literature number SLUP252.

Revision History

Changes from Original (October, 2010) to A Revision ................................................................................................... Page

• Corrected Figure 1 ....................................................................................................................... 2

• Updated Figure 2 ......................................................................................................................... 3
• Replaced Figure 6 ........................................................................................................................ 8

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

8 Revision History SLUA582A – October 2010 – Revised November 2010

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Power Supply Design Seminar

Designing an LLC Resonant

Half-Bridge Power Converter

Topic Category:
Design Reviews – Functional Circuit Blocks

Reproduced from
2010 Texas Instruments Power Supply Design Seminar
SEM1900, Topic 3
TI Literature Number: SLUP263

© 2010, 2011 Texas Instruments Incorporated

Power Seminar topics and online power-

training modules are available at:
power.ti.com/seminars

Designing an LLC Resonant
Half-Bridge Power Converter
Hong Huang

AbstrAct

While half-bridge power stages have commonly been used for isolated, medium-power applications,
converters with high-voltage inputs are often designed with resonant switching to achieve higher efficiency,
an improvement that comes with added complexity but that nevertheless offers several performance
benefits. This topic provides detailed information on designing a resonant half-bridge converter that uses
two inductors (LL) and a capacitor (C), known as an LLC configuration. This topic also introduces a
unique analysis tool called first harmonic approximation (FHA) for controlling frequency modulation.
FHA is used to define circuit parameters and predict performance, which is then verified through
comprehensive laboratory measurements.

Topic 3
IntroductIon A. Brief Review of Resonant Converters
There are many resonant-converter topologies,
Higher efficiency, higher power density, and
and they all operate in essentially the same way: A
higher component density have become common
square pulse of voltage or current generated by the
in power-supply designs and their applications.
power switches is applied to a resonant circuit.
Resonant power converters—especially those with
Energy circulates in the resonant circuit, and some
an LLC half-bridge configuration—are receiving
or all of it is then tapped off to supply the output.
renewed interest because of this trend and the
More detailed descriptions and discussions can be
potential of these converters to achieve both higher
found in this topic’s references.
switching frequencies and lower switching losses.
Among resonant converters, two basic types
However, designing such converters presents many
are the series resonant converter (SRC), shown in
challenges, among them the fact that the LLC
Fig. 1a, and the parallel resonant converter (PRC),
resonant half-bridge converter performs power
shown in Fig. 1b. Both of these converters regulate
conversion with frequency modulation instead of
their output voltage by changing the frequency of
pulse-width modulation, requiring a different
the driving voltage such that the impedance of the
design approach.
resonant circuit changes. The input voltage is split
This topic presents a design procedure for the
between this impedance and the load. Since the
LLC resonant half-bridge converter, beginning
SRC works as a voltage divider between the input
with a brief review of basic resonant-converter
and the load, the DC gain of an SRC is always
operation and a description of the energy-transfer
function as an essential requirement for the design
process. This energy-transfer function, presented Lr Cr Lr

as a voltage ratio or voltage-gain function, is used

along with resonant-circuit parameters to describe
the relationship between input voltage and output RL Cr RL
voltage. Next, a method for determining parameter
values is explained. To demonstrate how a design
is created, a step-by-step example is then presented a. Series resonant b. Parallel resonant
for a converter with 300 W of output power, a 390- converter. converter.
VDC input, and a 12-VDC output. The topic
concludes with the results of bench-tested per- Fig. 1. Basic resonant-converter configurations.
formance measurements.

3-1
Texas Instruments 1 SLUP263
lower than 1. Under light-load conditions, the Lr Cr1 Lr Cr
impedance of the load is very large compared to
the impedance of the resonant circuit; so it becomes
difficult to regulate the output, since this requires
the frequency to approach infinity as the load
Cr2 RL Lm RL

approaches zero. Even at nominal loads, wide

frequency variation is required to regulate the
output when there is a large input-voltage range. a. LCC configuration. b. LLC configuration.
In the PRC shown in Fig. 1b, the load is Fig. 2. Two types of SPRC.
connected in parallel with the resonant circuit,
inevitability requiring large amounts of circulating
current. This makes it difficult to apply parallel inductance, Lr, and the transformer’s magnetizing
resonant topologies in applications with high inductance, Lm.
power density or large load variations. The LLC resonant converter has many addi-
tional benefits over conventional resonant con-
B. LCC and LLC Resonant Converters verters. For example, it can regulate the output
Topic 3

To solve these limitations, a converter over wide line and load variations with a relatively
combining the series and parallel configurations, small variation of switching frequency, while main-
called a series-parallel resonant converter (SPRC), taining excellent efficiency. It can also achieve zero-
has been proposed. One version of this structure voltage switching (ZVS) over the entire operating
uses one inductor and two capacitors, or an LCC range. Using the LLC resonant configuration in
configuration, as shown in Fig. 2a. Although this an isolated half-bridge topology will be described
combination overcomes the drawbacks of a simple next, followed by the procedure for designing
SRC or PRC by embedding more resonant fre- this topology.
quencies, it requires two independent physical
capacitors that are both large and expensive II. LLc resonAnt
because of the high AC currents. To get similar HALf-brIdge converter
characteristics without changing the physical com- This section describes a typical isolated LLC
ponent count, the SPRC can be altered to use two resonant half-bridge converter; its operation; its
inductors and one capacitor, forming an LLC reso- circuit modeling with simplifications; and the
nant converter (Fig. 2b). An advantage of the LLC relationship between the input and output voltages,
over the LCC topology is that the two physical called the voltage-gain function. This voltage-gain
inductors can often be integrated into one physical function forms the basis for the design procedure
component, including both the series resonant described in this topic.

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2 SLUP263
Square-Wave Generator Resonant Circuit Rectifiers for
DC Output Cr Lr

Q1
D1
I m Ios
n:1:1 Vo
Ir
Cr Lr + +
Vin = + Io
Vsq
VDC –
Vsq Vso Lm R´L
+
Ir
Q2 Vso Lm Co RL

–
Vsq Vso
D2

a. Typical configuration. b. Simplified converter circuit.

Fig. 3. LLC resonant half-bridge converter.

A. Configuration together with the losses from the transformer

and output rectifiers.

Topic 3
Fig. 3a shows a typical topology of an LLC
resonant half-bridge converter. This circuit is very 3. On the converter’s secondary side, two diodes
similar to that in Fig. 2b. For convenience, Fig. 2b constitute a full-wave rectifier to convert AC
is copied as Fig. 3b with the series elements input to DC output and supply the load RL. The
interchanged, so that a side-by-side comparison output capacitor smooths the rectified voltage
with Fig. 3a can be made. The converter and current. The rectifier network can be
configuration in Fig. 3a has three main parts: implemented as a full-wave bridge or center-
1. Power switches Q1 and Q2, which are usually tapped configuration, with a capacitive output
MOSFETs, are configured to form a square- filter. The rectifiers can also be implemented
wave generator. This generator produces a with MOSFETs forming synchronous
unipolar square-wave voltage, Vsq, by driving rectification to reduce conduction losses,
switches Q1 and Q2, with alternating 50% especially beneficial in low-voltage and high-
duty cycles for each switch. A small dead time current applications.
is needed between the consecutive transitions,
both to prevent the possibility of cross- B. Operation
conduction and to allow time for ZVS to be This section provides a review of LLC
achieved. resonant-converter operation, starting with series
2. The resonant circuit, also called a resonant resonance.
network, consists of the resonant capacitance, Resonant Frequencies in an SRC
Cr, and two inductances—the series resonant Fundamentally, the resonant network of an
inductance, Lr, and the transformer’s magnet- SRC presents a minimum impedance to the
izing inductance, Lm. The transformer turns sinusoidal current at the resonant frequency,
ratio is n. The resonant network circulates the regardless of the frequency of the square-wave
electric current and, as a result, the energy is voltage applied at the input. This is sometimes
circulated and delivered to the load through the called the resonant circuit’s selective property.
transformer. The transformer’s primary wind- Away from resonance, the circuit presents higher
ing receives a bipolar square-wave voltage, impedance levels. The amount of current, or
Vso. This voltage is transferred to the secondary associated energy, to be circulated and delivered
side, with the transformer providing both to the load is then mainly dependent upon the
electrical isolation and the turns ratio to deliver value of the resonant circuit’s impedance at that
the required voltage level to the output. In Fig. frequency for a given load impedance. As the
3b, the load R′L includes the load RL of Fig. 3a frequency of the square-wave generator is varied,

3-3
Texas Instruments 3 SLUP263
the resonant circuit’s impedance varies to control It is apparent from Fig. 3b that f0 as described
that portion of energy delivered to the load. by Equation (1) is always true regardless of the
An SRC has only one resonance, the series load, but fp described by Equation (2) is true only
resonant frequency, denoted as at no load. Later it will be shown that most of the
time an LLC converter is designed to operate in
1
f0 = . (1) the vicinity of f0. For this reason and others yet to
2π L r C r be explained, f0 is a critical factor for the converter’s
The circuit’s frequency at peak resonance, fc0, operation and design.
is always equal to its f0. Because of this, an SRC Operation At, Below, and Above f0
requires a wide frequency variation in order to The operation of an LLC resonant converter
accommodate input and output variations. may be characterized by the relationship of the
fc0 , f0 , and fp in an LLC Circuit switching frequency, denoted as fsw, to the series
However, the LLC circuit is different. After the resonant frequency (f0). Fig. 4 illustrates the
second inductance (Lm) is added, the LLC circuit’s typical waveforms of an LLC resonant converter
frequency at peak resonance (fc0) becomes a function with the switching frequency at, below, or above
Topic 3

of load, moving within the range of fp ≤ fc0 ≤ f0 as the series resonant frequency. The graphs show,
the load changes. f0 is still described by Equation from top to bottom, the Q1 gate (Vg_Q1), the Q2
(1), and the pole frequency is described by gate (Vg_Q2), the switch-node voltage (Vsq), the
resonant circuit’s current (Ir), the magnetizing
1 current (Im), and the secondary-side diode current
fp = . (2)
2π (L r + L m )Cr (Is). Note that the primary-side current is the sum
of the magnetizing current and the secondary-side
At no load, fc0 = fp. As the load increases, fc0 current referred to the primary; but, since the
moves towards f0. At a load short circuit, fc0 = f0. magnetizing current flows only in the primary
Hence, LLC impedance adjustment follows a side, it does not contribute to the power transferred
family of curves with fp ≤ fc0 ≤ f0, unlike that in from the primary-side source to the secondary-
SRC, where a single curve defines fc0 = f0. This side load.
helps to reduce the frequency range required from
an LLC resonant converter but complicates the
circuit analysis.

Vg_Q1 Vg_Q1 Vg_Q1

Vg_Q2 Vg_Q2 Vg_Q2

Vsq Vsq Vsq

0 0 0
Ir
Im Ir Im Ir Im
0 0 0

Is Is Is
D1 D2 D1 D2 D1 D2
0 0 0
t0 t1 t2 t3 t4 t0 t1 t2 t3 t4 t0 t1 t2 t3 t4
time, t time, t time, t

a. At f0 . b. Below f0 . c. Above f0 .
Fig. 4. Operation of LLC resonant converter.

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4 SLUP263
Operation at Resonance (Fig. 4a) Operation Above Resonance (Fig. 4c)
In this mode the switching frequency is the In this mode the primary side presents a smaller
same as the series resonant frequency. When circulating current in the resonant circuit. This
switch Q1 turns off, the resonant current falls to reduces conduction loss because the resonant
the value of the magnetizing current, and there is circuit’s current is in continuous-current mode,
no further transfer of power to the secondary side. resulting in less RMS current for the same amount
By delaying the turn-on time of switch Q2, the of load. The rectifier diodes are not softly
circuit achieves primary-side ZVS and obtains a commutated and reverse recovery losses exist, but
soft commutation of the rectifier diodes on the operation above the resonant frequency can still
secondary side. The design conditions for achieving achieve primary ZVS. Operation above the reso-
ZVS will be discussed later. However, it is obvious nant frequency may cause significant frequency
that operation at series resonance produces only a increases under light-load conditions.
single point of operation. To cover both input and The foregoing discussion has shown that the
output variations, the switching frequency will converter can be designed by using either fsw ≥ f0
have to be adjusted away from resonance. or fsw ≤ f0, or by varying fsw on either side around
f0. Further discussion will show that the best

Topic 3
Operation Below Resonance (Fig. 4b) operation exists in the vicinity of the series resonant
Here the resonant current has fallen to the frequency, where the benefits of the LLC converter
value of the magnetizing current before the end of are maximized. This will be the design goal.
the driving pulse width, causing the power transfer
to cease even though the magnetizing current C. Modeling an LLC Half-Bridge Converter
continues. Operation below the series resonant To design a converter for variable-energy
frequency can still achieve primary ZVS and transfer and output-voltage regulation, a voltage-
obtain the soft commutation of the rectifier diodes transfer function is a must. This transfer function,
on the secondary side. The secondary-side diodes which in this topic is also called the input-to-
are in discontinuous current mode and require output voltage gain, is the mathematical relation-
more circulating current in the resonant circuit to ship between the input and output voltages.
deliver the same amount of energy to the load. This section will show how the gain formula is
This additional current results in higher conduction developed and what the characteristics of the
losses in both the primary and the secondary sides. gain are. Later the gain formula obtained will be
However, one characteristic that should be noted used to describe the design procedure for the LLC
is that the primary ZVS may be lost if the switching resonant half-bridge converter.
frequency becomes too low. This will result in
high switching losses and several associated issues.
This will be explained further later.

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5 SLUP263
Cr Lr Cr Lr

I m Ios
Ir Ir
+ + + +
Vsq Vso Lm RĹ Vge Lm Re Voe
– –
Im I oe

Vsq Vso

a. Nonlinear nonsinusoidal circuit. b. Linear sinusoidal circuit.

Fig. 5. Model of LLC resonant half-bridge converter.

Traditional Modeling Methods Do Not Work Well The FHA method can be used to develop the
To develop a transfer function, all variables gain, or the input-to-output voltage-transfer
should be defined by equations governed by the function. The first steps in this process are as
Topic 3

LLC converter topology shown in Fig. 5a. These follows:

equations are then solved to get the transfer • Represent the primary-input unipolar square-
function. Conventional methods such as state- wave voltage and current with their fundamental
space averaging have been successfully used in components, ignoring all higher-order
modeling pulse-width-modulated switching harmonics.
converters, but from a practical viewpoint they • Ignore the effect from the output capacitor and
have proved unsuccessful with resonant converters, the transformer’s secondary-side leakage
forcing designers to seek different approaches. inductance.
Modeling with Approximations • Refer the obtained secondary-side variables to
As already mentioned, the LLC converter is the primary side.
operated in the vicinity of series resonance. This • Represent the referred secondary voltage, which
means that the main composite of circulating is the bipolar square-wave voltage (Vso), and the
current in the resonant network is at or close to the referred secondary current with only their
series resonant frequency. This provides a hint that fundamental components, again ignoring all
the circulating current consists mainly of a single higher-order harmonics.
frequency and is a pure sinusoidal current. With these steps accomplished, a circuit model
Although this assumption is not completely of the LLC resonant half-bridge converter in Fig.
accurate, it is close—especially when the square 5a can be obtained (Fig. 5b). In Fig. 5b, Vge is the
wave’s switching cycle corresponds to the series fundamental component of Vsq , and Voe is the fun-
resonant frequency. But what about the errors? damental component of Vso . Thus, the nonlinear
If the square wave is different from the series and nonsinusoidal circuit in Fig. 5a is approxi-
resonance, then in reality more frequency mately transformed into the linear circuit of Fig.
components are included; but an approximation 5b, where the AC resonant circuit is excited by an
using the single fundamental harmonic of the effective sinusoidal input source and drives an
square wave can be made while ignoring all higher- equivalent resistive load. In this circuit model,
order harmonics and setting possible accuracy both input voltage Vge and output voltage Voe are
issues aside for the moment. This is the so-called in sinusoidal form with the same single frequency—
first harmonic approximation (FHA) method, now i.e., the fundamental component of the square-
widely used for resonant-converter design. This wave voltage (Vsq), generated by the switching
method produces acceptable design results as long operation of Q1 and Q2.
as the converter operates at or close to the series This model is called the resonant converter’s
resonance. FHA circuit model. It forms the basis for the

3-6
Texas Instruments 6 SLUP263
design example presented in this topic. The which can be simplified as
voltage-transfer function, or the voltage gain, is
ω = ωsw = 2πfsw . (11)
also derived from this model, and the next section
will show how. Before that, however, the electrical The capacitive and inductive reactances of Cr, Lr,
variables and their relationships as used in Fig. 5b and Lm, respectively, are
need to be obtained.
1
X Cr = , X Lr = ωL r , and X Lm = ωL m . (12)
Relationship of Electrical Variables ωC r
On the input side, the fundamental voltage of
The RMS magnetizing current is
the square-wave voltage (Vsq) is
2 Voe 2 2 n × Vo
vge (t) = × VDC × sin(2πfsw t), (3) Im = = × . (13)
π ωL m π ωL m
and its RMS value is The circulating current in the series resonant
circuit is
2
Vge = × VDC . (4)
π I r = I 2m + Ioe
2
. (14)

Topic 3
On the output side, since Vso is approximated as a With the relationships of the electrical variables
square wave, the fundamental voltage is established, the next step is to develop the voltage-
4 gain function.
voe (t) = × n × Vo × sin(2πfsw t − ϕV ), (5)
π
D. Voltage-Gain Function
where φV is the phase angle between Voe and Vge,
Naturally, the relationship between the input
and the RMS output voltage is
voltage and output voltage can be described by
2 2 their ratio or gain:
Voe = × n × Vo . (6)
π n × Vo n × Vo
M g _DC = = (15)
The fundamental component of current corre- Vin / 2 VDC / 2
sponding to Voe and Ioe is
As described earlier, the DC input voltage and
π 1 output voltage are converted into switching mode,
ioe (t) = × × Io × sin(2πfsw t − ϕi ), (7)
2 n and then Equation (15) can be approximated as the
where φi is the phase angle between ioe and voe, ratio of the bipolar square-wave voltage (Vso) to
and the RMS output current is the unipolar square-wave voltage (Vsq):

π 1 Vso
Ioe = × × Io . (8) M g _DC ≈ M g _ sw = (16)
2 2 n Vsq

Then the AC equivalent load resistance, Re, can be The AC voltage ratio, Mg_AC, can be approx-
calculated as imated by using the fundamental components, Vge
and Voe, to respectively replace Vsq and Vso in
Voe 8 × n 2 Vo 8 × n 2 Equation (16):
Re = = 2 × = 2 × RL. (9)
Ioe π Io π
n × Vo
Since the circuit in Fig. 5b is a single-frequency, M g _DC = ≈ M g _ sw
Vin /2
sinusoidal AC circuit, the calculations can be (17)
made in the same way as for all sinusoidal circuits. V V
= so ≈ M g _ AC = oe
The angular frequency is Vsq Vge
ωsw = 2πfsw , (10)

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7 SLUP263
To simplify notation, Mg will be used here in Further, to combine two inductances into one, an
place of Mg _AC. From Fig. 5b, the relationship inductance ratio can be defined as
between Voe and Vge can be expressed with the Lm
electrical parameters Lr, Lm, Cr, and Re. Then the Ln = . (21)
input-to-output voltage-gain or voltage-transfer Lr
function becomes The quality factor of the series resonant circuit is
defined as
Voe jX Lm || R e
Mg = = L r /Cr
Vge ( jX Lm || R e ) + j(X Lr − X Cr ) Qe = . (22)
Re
(18)
( jωL m ) || R e Notice that fn, Ln, and Qe are no-unit variables.
= , With the help of these definitions, the voltage-
1
( jωL m ) || R e + jωL r + gain function can then be normalized and
jω C r
expressed as
––
where j = √ –1. L n × f n2
Topic 3

Equation (18) depicts a connection from the Mg = . (23)

input voltage (Vin) to the output voltage (Vo) [(L n + 1) × f n2 − 1] + j[(f n2 − 1) × f n × Qe × L n ]
established in relation to Mg with LLC-circuit
The relationship between input and output voltages
parameters. Although this expression is only
can also be obtained from Equation (23):
approximately correct, in practice it is close
enough to the vicinity of series resonance. 1 V 1 V
Vo = M g × × in = M g (f n , L n ,Qe ) × × DC , (24)
Accepting the approximation as accurate allows n 2 n 2
Equation (19) to be written:
where Vin = VDC.
1 V
Vo = M g × × in . (19)
n 2 Behavior of the Voltage-Gain Function
In other words, output voltage can be determined The voltage-gain function expressed by Equation
after Mg, n, and Vin are known. (23) and the circuit model in Fig. 5b form the basis
for the design method described in this topic;
Normalized Format of Voltage-Gain Function therefore it is necessary to understand how Mg
The voltage-gain function described by behaves as a function of the three factors fn, Ln,
Equation (18) is expressed in a format with and Qe. In the gain function, frequency fn is the
absolute values. It is difficult to give a general control variable. Ln and Qe are dummy variables,
description of design issues with such a format. It since they are fixed after their physical parameters
would be better to express it in a normalized are determined. Mg is adjusted by fn after a design
format. To do this, the series resonant frequency is complete. As such, a good way to explain how
(f0) can be selected as the base for normalization. the gain function behaves is to plot Mg with
Then the normalized frequency is expressed as respect to fn at given conditions from a family of
values for Ln and Qe.
fsw
fn = . (20)
f0

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8 SLUP263
2 2

1.8 Q e = 0.1 1.8 Q e = 0.1

Q e = 0.2 Q e = 0.2
Q e = 0.5 Q e = 0.5
1.6 Q e = 0.8 1.6 Q e = 0.8
Qe = 1 Qe = 1
1.4 Qe = 2 1.4 Qe = 2
Qe = 5 Qe = 5
Q e = 0.5
Gain, Mg

Gain, Mg
1.2 Qe = 8 1.2 Qe = 8
Q e = 10 Q e = 10
1 2 = 0 1 2 = 0

0.8 0.8

0.6 Q e = 0.1 0.6 Q e = 0.1

0.4 0.4

0.2 Q e = 0.5 0.2 Q e = 0.5

0 0
0.1 1 Q e = 10 10 0.1 1 Q e = 10 10
Normalized Frequency, fn Normalized Frequency, fn

Topic 3
a. Ln = 1. b. Ln = 5.

2 2
Q e = 0.1 Q e = 0.1
1.8 Q e = 0.2 1.8 Q e = 0.2
Q e = 0.1 Q e = 0.5 Q e = 0.1 Q e = 0.5
1.6 Q e = 0.8 1.6 Q e = 0.8
Qe = 1 Qe = 1
1.4 Qe = 2 1.4 Qe = 2
Qe = 5 Qe = 5
Qe = 8 Qe = 8
Gain, Mg

Gain, Mg

1.2 1.2 Q e = 10
Q e = 10
Q e = 0.5 2 = 0 2 = 0
1 1
Q e = 0.5
0.8 0.8
Q e = 0.1 Q e = 0.1
0.6 0.6

0.4 0.4
Q e = 0.5 Q e = 0.5
0.2 0.2

0 0
0.1 1 Q e = 10 10 0.1 1 Q e = 10 10
Normalized Frequency, fn Normalized Frequency, fn

c. Ln = 10. d. Ln = 20.
Fig. 6. Plots of voltage-gain function (Mg) with different values of Ln.

Figs. 6a to 6d illustrate several possible represent both magnitude and phase angle, but
relationships. Each plot is defined by a fixed value only the magnitude is useful in this case.
for Ln (Ln = 1, 5, 10, or 20) and shows a family of Within a given Ln and Qe, Mg presents a
curves with nine values, from 0.1 to 10, for the convex curve shape in the vicinity of the circuit’s
variable Qe. From these plots, several observations resonant frequency. This is a typical curve that
can be made. shows the shape of the gain from a resonant
The value of Mg is not less than zero. This is converter. The normalized frequency correspond-
obvious since Mg is from the modulus operator, ing to the resonant peak (fn_c0, or fsw = fc0) is
which depicts a complex expression containing moving with respect to a change in load and thus
both real and imaginary numbers. These numbers to a change in Qe for a given Ln.

3-9
Texas Instruments 9 SLUP263
Changing Ln and Qe will reshape the Mg curve effect of Lm and shift fc0 towards f0. As a simple
and make it different with respect to fn. As Qe is a illustration, it is helpful to examine two extremes:
function of load described by Equations (9) and 1. If RL is open, then Qe = 0, and fc0 = fp as
(22), Mg presents a family of curves relating described by Equation (2). fc0 sits to the far left
frequency modulation to variations in load. of f0, and the corresponding gain peak is very
Regardless of which combination of Ln and Qe high and can be infinite in theory.
is used, all curves converge and go through the
2. If RL is shorted, then Qe = ∞ and Lm is com-
point of (fn, Mg) = (1, 1). This point is at fn = 1, or pletely bypassed or shorted, making the effect
fsw = f0 from Equation (20). By definition of series
of Lm on the gain disappear. The corresponding
resonance, XLr – XCr = 0 at f0. In other words, the peak gain value from the Lm effect then
voltage drop across Lr and Cr is zero, so that the becomes zero, and fc0 moves all the way to the
input voltage is applied directly to the output load, right, overlapping f0.
resulting in a unity voltage gain of Mg = 1.
Notice that the operating point (fn, Mg) = (1, 1) Therefore, if RL changes from infinite to zero,
is independent of the load; i.e., as long as the gain the resonant peak gain changes from infinite to
(Mg) can be kept as unity, the switching frequency unity, and the corresponding frequency at peak
Topic 3

will be at the series resonant frequency (f0) no resonance (fc0) moves from fp to the series
matter what the load current is. In other words, in resonant frequency (f0).
a design whose operating point is at (fn, Mg) = For a fixed Qe, a decrease in Ln shrinks the
(1, 1) or its vicinity, the frequency variation is curve; the whole curve is squeezed, and fc0 moves
narrowed down to minimal. At (fn, Mg) = (1, 1), towards f0. This results in a better frequency-
the impedance of the series resonant circuit is control band with a higher peak gain. There are
zero, assuming there are no parasitic power losses. two reasons for this. First, as Ln decreases due to
The entire input voltage is then applied to the the decrease in Lm, fp gets closer to f0, which
output load no matter how much the load current squeezes the curves from fp to f0. Second, a
varies. However, away from (fn, Mg) = (1, 1), the decreased Ln increases Lr, resulting in a higher Qe.
impedance of the series resonant circuit becomes A higher Qe shrinks the curve as just described.
nonzero, the voltage gain changes with different At first glance, it appears that any combination
load impedances, and the corresponding operation of Ln and Qe would work for a converter design
becomes load-dependent. and that the design could be made with fn operating
For a fixed Ln, increasing Qe shrinks the curve, on either side of fn = 1. However, as explained in
resulting in a narrower frequency-control band, the following section, there are many more
which is expected since Qe is the quality factor of considerations.
the series resonant circuit. In addition, as the
whole curve shifts lower, the corresponding peak III. desIgn consIderAtIons
value of Mg becomes smaller, and the fn As discussed earlier, fn is the control variable
corresponding to that value moves towards the
in frequency modulation. Therefore the output
right and closer to fn = 1. This frequency shift with
voltage can be regulated by Mg through controlling
increasing Qe is due to an increased load. It is
fn , as indicated by Fig. 6 and Equation (24), which
apparent from reviewing Equations (9) and (22)
can be rearranged as
that an increase in Qe may come from a reduction
in RL, as both Lm and Lr are fixed. For the same 1 V
Vo = M g (f n , L n , Qe ) × × in . (25)
series resonant frequency, Cr is fixed as well. RL is n 2
in parallel with Lm, so reducing RL will reduce the

Texas Instruments 3-10

10 SLUP263
Although this discussion has so far determined 2
that the design should operate in the vicinity of the
series resonance, or near fn = 1, it is recommended
1.8
Qe = 0

that the optimum design be restricted to the area

1.6
Mg_max
described by a1 through a4 in Fig. 7, for reasons to 1.4 a3 a2
be explained.

Gain, Mg
1.2

A. What Does “In the Vicinity” Mean?

a0
1
Mg_min
Obviously, “in the vicinity” is a loose designa- 0.8 a1
Curve 1
tion; but, as stated before in the discussion of the 0.6
a4 Cu (Qe = 0)
FHA concept, if a pure sinusoidal current flowing
rv
e
2
through the resonant circuit is assumed, and if the
0.4 (Q
Cu e =m
rve
circuit is made to operate at the exact location of
3 ax)
0.2 Curv
f0, then the design result is accurate. This can also
e4
0
be verified easily by a bench test or a computer
0.1 fn_min 1 fn_max 10

simulation, but so far there is no verification in Normalized Frequency, fn

Topic 3
theory. A potential insight into such verification
a. In the vicinity of series resonance (near fn = 1).
can be made through Equation (19). Assigning a
value of 1 to Mg in Equation (19) as an indication
of operation at fn = 1 will remove the approxima- 1.6

tions made to Equation (17). A precise relationship

Qe = 0
n x Vo_max

is then achieved between the DC input and DC

Mg_max =
1.4 Vin_min /2

output as described by Equation (15).

a3 a2

A design that operates only at f0 certainly

Gain, Mg

1.2

cannot be made, but when it includes operating

Q e = max

frequencies away from f0, it starts to show errors

a0 n x Vo_min
1 Mg_min =
when compared with bench-test measurements. So
Vin_max /2

the common understanding in an FHA design 0.8 a1

approach is that it can help to create an initial a4

design, with all design variables retaining their 0.6 Qe = 0

clear physical concepts and meanings, which is fn_min

1Q e = max fn_max
important in order for designers to understand the Normalized Frequency, fn
behavior of the LLC converter. However, it should
b. Operation boundary set by a1 through a4.
be expected that some bench testing to optimize
and finalize the design may be necessary. This Fig. 7. Recommended design area.
could be an iterative process, but computer-based
circuit simulation will save iteration cycles. As a
matter of fact, computer simulation plays an voltage variation over a specified range, at a given
important role in LLC-converter design after an output load current.
initial design is made with the FHA approach.
Load regulation is defined as the maximum
B. Basic Design Requirements output-voltage variation caused by a change in
For a typical design of a power-supply load over a stated range, usually from no load to
converter, as is well-known, three basic require- maximum.
ments are almost always considered first—line These two types of regulation are actually achieved
regulation, load regulation, and efficiency. through the voltage-gain adjustment—and in an
LLC converter, the gain adjustment is made
Line regulation is defined as the maximum through frequency modulation. The recommended
output-voltage variation caused by an input- area of operation described in Fig. 7 shows a

Texas Instruments 3-11

11 SLUP263
relatively steep slope for the gain, which can n × Vo _ max
narrow the range of the frequency modulation. As M g _ max = , (28)
Vin _ min /2
such, a design has to make the gain adequately
adjustable in a range that meets the required and
regulating specifications.
Ln
Efficiency is one big benefit of using an LLC Mg _∞ = . (29)
Ln + 1
converter. The converter’s switching losses can be
reduced significantly by ensuring that primary- Mg_∞ is a special value of Mg that presents the
side ZVS is maintained over the whole operating gain value at no load when fn is approaching
range. As will be explained, ZVS cannot be infinity. In other words, at no load, the gain curve
achieved everywhere in the gain-plot area, but (Mg) is approaching an asymptotic horizontal line
keeping the design within the recommended region with its value described by Equation (29), which
will ensure ZVS. can be easily obtained from Equation (23) when
the value of fn approaches infinity.
Line Regulation
Mg_min and Mg_max each form a horizontal
Achieving line regulation for the design of a
Topic 3

line in Fig. 7. For the no-load condition (Io = 0),

power-supply converter can be based on Equation
the quality factor (Qe) equals zero, shown in Fig.
(25) and the recommended design areas in Fig. 7.
7a as Curve 1. Since the gain curves are deter-
A minimum and maximum output voltage, Vo_min
mined by Ln and Qe, and Qe = 0, Ln is the sole
and Vo_max, respectively, will be assumed. To
design factor at this stage. As such, a value for Ln
simplify the discussion, it will also be assumed
needs to be selected that will provide a gain curve
that all parasitic voltage drops—for example, from
that meets the conditions of Equation (26). In
PCB traces, the MOSFET’s Rds_on, the diode’s
other words, the value of Ln needs to make Curve
forward voltage, etc.—are already converted or
1 cross over the two horizontal lines defined by
lumped into a part of the output-voltage range. It
Equations (27) and (28) inside the frequency
will also be assumed that the design requires a
limits. This is depicted in Fig. 7 by design points
maximum switching-frequency range; i.e., that it
a1 and a2.
is limited within fn_min ≤ fn ≤ fn_max. In reality, the
Similarly, if the load condition is not zero (Io >
frequency limits may need adjustment in order to
0), then an appropriate curve can be selected by
adapt the line- and load-regulation requirements,
making Qe correspond to the required maximum
or vice versa.
load and following the same process.
With these conditions and assumptions, to
achieve line regulation (and load regulation as Load Regulation
discussed later), Mg should be designed to meet
Normal Load Operation
the conditions described by Equation (26), which
As illustrated in Fig. 7, the gain presents a
says that all possible Mg values must contain the
family of curves. For a fixed Ln, each value for Qe
value of both Mg _min and Mg _max within the fn
generates a different gain curve. A bigger Qe
limits. For Io = 0,
makes the gain curve shift lower with a lower
{M g M g > M g _ ∞ } ⊃ {M g _ min , M g _ max }, (26a) peak. As such, when load current increases, the
gain curve moves away from its no-load shape
and for Io > 0, (Curve 1) to a lower representation. In Fig. 7,
Curve 2 corresponds to the maximum load current
{M g M g ≥ 0} ⊃ {M g _ min , M g _ max }, (26b) (Qe = max) while still meeting the conditions of
Equation (26) with the same Ln. This yields design
where
points a3 and a4 in the recommended design area.
n × Vo _ min If the load is increased further, Curve 2 will be
M g _ min = , (27) reshaped towards Curve 3. Horizontal line Mg_max
Vin _ max /2
will not be able to cross over with the gain curve,

3-12
Texas Instruments 12 SLUP263
so the conditions of Equation (26) cannot be met. that a zero gain transfers a zero percentage of
Output-voltage regulation is then lost. When this input voltage to the load short circuit. In this way,
happens, a design modification will be needed, the converter can be protected from a load short-
such as adjusting Ln or the switching-frequency circuit fault.
limits to reshape the gain curve. However, it is worth noting that the effec-
Since Qe is associated with the load current, it tiveness of such a protection method depends on
is appropriate to extend this discussion to include how quickly the short-circuit signal can be sent to
the possibility of overload and short-circuit the controller to activate the frequency increase. In
conditions. the recommended design area, the gain will
inevitably be forced to the left side of the resonant
Overload Current peak for some time until it eventually reaches
In the example, the recommended design area Curve 4. This could cause several severe issues,
in Fig. 7 includes an overload because Qe_max was including the possibility of a polarity reversal of
defined to include a value for it. As stated earlier, the feedback control. Considering this, an inde-
any further increase in load causes Curve 2 to pendent overcurrent shutdown may be a preferable
move towards Curve 3 or beyond, which places solution. However, if a frequency increase is still

Topic 3
the design outside of the design area and towards preferred, two other possible solutions are recom-
the condition of a short circuit. mended. Either (1) add a separate high-speed
Load Short Circuit control loop to rapidly initiate the frequency shift,
Since a load short circuit causes a potentially or (2) shift the recommended design area to where
excessive amount of current in the converter the minimum switching frequency (fn_min) is never
circuit, it is necessary to examine the gain plot of a less than the series resonant frequency (f0)—i.e.,
load short circuit to know what happens and how to where fn_min ≥ 1.
to deal with it. The corresponding gain plot is Zero-Voltage Switching (ZVS)
shown by Curve 4 in Fig. 7a. fc0 will become f0 A major benefit of the LLC converter topology
when Lm is bypassed by a load short circuit, and is its potential for significantly reduced switching
this defines Curve 4 as the gain shape with a losses, primarily achieved through primary-side
shorted output. ZVS; however, as stated earlier, it is ZVS consid-
Curve 4 provides insight into possible solutions erations that drive the recommended design area
for protecting the LLC converter. One possibility to be only on the right side of the resonant gain
is to increase the switching frequency to reduce curves in Fig. 7. This section discusses how ZVS
the gain. Based on Figs. 6 and 7, if the switching is achieved and why it affects the design area.
frequency is increased to more than two times the
series resonant frequency (f0), the gain will be Achieving ZVS
reduced to below 10%. If the frequency can be To achieve ZVS, a MOSFET is turned on only
pulled up to ten times f0, the gain becomes after its source voltage, Vds, has been reduced to
practically zero. From Equation (25) it can be seen zero by external means. One way of ensuring this

Texas Instruments 3-13

13 SLUP263
is to force a reversal of the current flowing through where the input impedance, Zin (shown in Fig. 9a),
the MOSFET’s body diode while a gate-drive can be inductive, making the circuit’s Ir lag behind
turn-on signal is applied (see Fig. 8). its Vge.
As shown in Fig. 8, when Q1 turns off at t1, Zin can be expressed in its polar form:
the Q2 gate’s turn-on drive signal is not applied
until t2, such that there exists a dead time, tdead, Zin = Zin e jϕz, (30a)
from t1 to t2. During tdead, the current in the reso- where φz is the phase angle between Ir and Vge.
nant circuit (Ir) is diverted from Q1 to Q2, first From Equation (30a), it is apparent that Zin varies
discharging Q2’s drain-to-source capacitance, Cds, in relation to φz (–π/2 ≤ φz ≤ π/2):
to make its voltage zero, and then forward biasing
• When φz > 0, the impedance is inductive.
Q2’s body diode. At t2, conduction through the Q2
• When φz < 0, the impedance is capacitive.
body diode maintains zero Vds_Q2 (ignoring the Q2
body diode’s forward-voltage drop) until the Q2 • When φz = 0, the impedance is resistive.
gate’s turn-on drive signal is applied. So the critical The φz angle is a function of frequency, or
condition is when Q1 turns off. A nonzero current switching frequency in this case. As such, a
(Ir) should still continue in its same direction as frequency boundary formed by the locus of the
Topic 3

when Q1 was on, normally accomplished by exter- resonant peaks corresponds to φz = 0 and is the
nal circuit inductance. And, of course, the same dividing line between the capacitive and inductive
conditions are necessary for a Q1 ZVS turn-on. regions (see Fig. 9b). Therefore, ZVS can be
Since there is inductive impedance, the circuit’s
current lags behind its applied voltage. To achieve + Vr –
ZVS, the designer must determine the conditions Lr
Cr Ir
+ +
Q1 + Vge Lm Re Voe
Vg Vds_Q1 –
–
n:1:1 Im I oe
Ids_Q1 Lr
+
Vin Vsq
– Lm
+ Ir
Q2 Z in
Vg Vds_Q2 Im
a. Input impedance.
Ids_Q2 Cr

a. LLC resonant circuit.

2
Qe = 0 Qe = 0
1.8 Q e = 0.2
Q e = 0.8
1.6 Qe = 1
Vg_Q1 Capacitive Qe = 2
1.4 Region Q e = 10
Q1 Turns Off
Vg_Q2
Gain, Mg

1.2 Inductive
Region
Vsq Q2 Turns On 1
Vds_Q2 = 0 Qe = 0
0.8
0
0.6
Ir Q2: Cds Discharge,
Im Body Diode 0.4
Turns On
0 Q e = 10
0.2
tdead 0
0.1 1 Frequency 10
t0 t1 t2 t3 t4 Boundary
time, t Normalized Frequency, fn

b. ZVS timing waveform. b. Gain regions.

Fig. 8. ZVS operation. Fig. 9. LLC resonant circuit.

Texas Instruments 3-14

14 SLUP263
Vg_Q1
Q1 Turns Off
Vg_Q2
Q1
Cds
Vg n:1:1
Lr Ceq Vsq Q2 Turns On
+ Lm
Vin Vsq
– Ir Vds_Q2 = 0
Q2 + I m_max
Cds Im Vin 0
–
Vg Ir Q2: Cds Discharge,
Cr Im Body Diode
Ceq Turns On
0
Cr
a. LLC resonant circuit showing (Short)
tdead
parasitic capacitance.
b. Equivalent circuit. t0 t1 t2 t3 t4
time, t

c. ZVS timing waveform.

Fig. 10. Obtaining sufficient inductive energy for ZVS.

Topic 3
achieved only when the converter’s input phase Ensuring Sufficient Inductive Energy
angle is greater than zero: To realize sufficient inductive energy for ZVS,
it is necessary to understand how ZVS is achieved
ϕz = ∠( Zin e jϕz ) > 0 (30b) in the inductive region. Fig. 10 can be used to
describe the ZVS mechanism. During the dead-
All resonant peaks corresponding to fc0 are in time interval between t1 and t2 (tdead), the resonant
the capacitive region, although the boundary line circuit’s current (Ir) equals the magnetizing current
is very close to the peaks. To distinguish resonant (Im). Im is by nature sinusoidal. In tdead, Im is
peaks from the gain values on the resonant bound- circulating through the capacitances (Cds) of Q1
ary, the gain values on the frequency boundary are and Q2 before Q2’s body diode begins to conduct.
defined as attainable peak-gain values, denoted as In tdead, the magnetic-field energy associated with
Mg _ap. Practically, though, Mg _ap is usually very Im converts into the electric-field energy of the
close to Mg _peak, where two capacitances; i.e., it charges up the Cds of Q1
M g _ peak = M g (31) and discharges the Cds of Q2 before Q2’s body
f = f c0 diode can turn on. Cr is much larger than Cds × 2,
and fc0 is the frequency when the maximum value so any energy-conversion effect from Cr can be
of Mg is achieved from Equation (18) or (23) ignored. An equivalent circuit in tdead can then be
during a frequency sweep from zero to infinity derived as shown in Fig. 10b. Ceq is used since
with a given Lm, Lr, Cr, and Re. parasitic capacitances exist in addition to Cds × 2.
From Fig. 7, it is clear that the recommended Hence, in order for the body diode of Q2 to be
operating area, a1 through a4, is in the inductive turned on within tdead, the conditions in Equations
region; so the design example should achieve (32a) and (32b) must be met:
ZVS. Although this is true, it is worth pointing out 1 1
that the recommendation is only a condition (L m + L r ) × I 2m _ peak ≥ (2Ceq ) × Vin2 (32a)
2 2
necessary to ensure ZVS. There must also be
sufficient inductive energy for the converter to t dead ≥ 16 × Ceq × fsw × L m (32b)
operate with ZVS.

3-15
Texas Instruments 15 SLUP263
Why the Capacitive Region Is Not Used
As already discussed, ZVS cannot be achieved
in the capacitive region; and, without it, switching 1.5

losses become high and the efficiency benefit of

using an LLC converter is lost. Several additional
issues arise if operation is allowed in the capacitive

Gain, Mg
1

region:
With C w

• This region yields hard switching on the primary

side, since ZVS is lost. 0.5 Without C w
• Because of hard switching and a capacitive
current, the primary-side MOSFET’s body diodes fCw
present reverse-recovery losses, and these diodes 0
are usually of a type with slow reverse recovery. 0.1 1 10

The slow reverse recovery may allow severe

Normalized Frequency, fn

shoot-through of the two primary MOSFETs, Fig. 11. Effect of transformer windings’ parasitic
resulting in high current and causing the capacitance (Cw ) on gain function at high
Topic 3

MOSFETs to fail. frequency.

• Even if the MOSFETs can be selected to tolerate
shoot-through current caused by power dissipa-
tion from the reverse recovery, high current spikes may need consideration. As is well-known, the
are still present, leading to high EMI noise. lower the switching frequency is, the bulkier the
• The frequency relationship is reversed, which converter, and the less important switching losses
changes the feedback control to positive. and ZVS efficiency become. Conduction losses
become dominant, making the LLC converter less
C. Selecting Design Parameters fsw, n, Ln, attractive. A higher switching frequency makes the
and Qe benefits of the LLC converter more pronounced,
With a better understanding of the gain behavior, particularly in comparison with hard-switched
it is now possible to move ahead and create the converters. If the switching frequency is very
design. Thus far, all discussion has been based on high, additional factors may have to be considered,
knowing the values of fsw, n, Ln, and Qe and their such as component availability and the associated
potential effect on circuit operation; but, at the additional cost; additional board-layout concerns;
beginning of a design, nothing is known about and additional switching losses despite MOSFET
these variables, so where does the designer start? ZVS, such as magnetic-core losses. Also, the
parasitic capacitance, Cw , of the transformer
Selecting the Switching Frequency (fsw) windings may begin to change the nature of the
Acceptable switching frequency is usually resonant gain curves, as shown in Fig. 11.
defined for particular applications. For example,
most off-line AC/DC applications require a Selecting the Transformer Turns Ratio (n)
switching frequency below 150 kHz for normal As shown in Fig. 7, the gain magnitude in the
operation, and usually between 100 and 150 kHz recommended design area can be greater or smaller
as a rule of thumb. This is usually because con- than unity. This provides flexibility in selecting
duction EMI testing starts at 150 kHz. Maintain- the transformer turns ratio. Initially the gain can
ing the switching frequency below the EMI test’s be set at unity (Mg = 1) for the output voltage at its
lower boundary helps the application to pass the middle value between Vo_min and Vo_max. This
test. Therefore, circuit components corresponding middle value can be called the output voltage’s
to such a frequency range are usually well- nominal value, Vo_nom , although the middle value
developed, more available, and less expensive. may not necessarily always be the nominal value.
If a different frequency range is required for Similarly, the input voltage’s nominal value can be
unique applications, there are several factors that called Vin_nom . Then the transformer turns ratio

3-16
Texas Instruments 16 SLUP263
may be initially designed based on Equation (25): 3.0

Vin / 2 Vin _ nom / 2 Ln = 1.5

n = Mg × = (33)
2.8
Ln = 2.0
Vo Vo_ nom

Attainable Peak Gain, Mg_ap

Ln = 3.0
Mg = 1
2.6
Ln = 3.0 Ln = 4.0
2.4 Ln = 5.0
Ln = 6.0
Selecting Ln and Qe 2.2 Ln = 3.5 by
Ln = 8.0

Recall that in order to achieve line and load

Ln = 9.0
Interpolation
regulation across the operation range, the design
2.0 Mg_ap = 1.56

must meet the conditions of Equation (26), which

Qe = 0.45
1.8
defines two horizontal lines crossing over two Ln = 1.5

gain curves within frequency limits. Designing

1.6
Ln = 5
circuit parameters to select Ln and Qe values that 1.4 Mg_ap = 1.2
satisfy Equation (26) will be discussed next.
Qe = 0.5
1.2

How Are the Proper Ln and Qe Selected? 1.0

First, recall the discussion on Fig. 7. The most
0.15 0.35 0.55 0.75 0.95 1.15

Topic 3
critical point for normal operation is the point a3.
Quality Factor, Q e

This point corresponds to Qe_max, determined by a. Peak-gain curves.

the maximum load current. This point should be
designed to avoid operation that would enter the
capacitive region. Since a required maximum gain Attainable Peak Gain, Mg_ap
1.8

(Mg _max) can be determined from Equation (28),

Mg _max can be plotted to the gain curves to obtain 1.6

point a3 by finding the cross point between the Ln = 5

Mg _max line and the gain curves. Because the gain 1.4 Mg_ap = 1.2

curves are dependent on Ln and Qe, several gain

Qe = 0.5

curves may need to be drawn to find a proper point 1.2

a3. This is certainly one way to make the initial

selection of Ln and Qe, but it is a difficult way and
1.0

most likely will require some wild guess.

0.15 0.35 0.55 0.75

A more desirable approach is to create a

Quality Factor, Q e

common tool to represent the gain curves that can

1.4

be shared and reused by different designs. Since

Qe = 0.5
1.2 Ln = 5
the attainable peak gain (Mg _ap) corresponding to Mg_max = 1.2
Qe_max is the highest gain of concern for a design,
1
Gain, Mg

gain-curve plots can be created beforehand to show

0.8

Mg _ap with different values of Ln and Qe . Then Ln 0.6

and Qe can be selected to achieve Mg _ap > Mg_max
based on a common tool—the Mg _ap curves. How
0.4

this method is used will be described after a 0.2

discussion of how the Mg _ap curves are obtained. 0

0.1 1
How Are the Mg _ap Curves Obtained? Normalized Frequency, fn

The created Mg_ap curves are shown in Fig. 12a. b. Obtaining peak-gain curves.
The horizontal axis is Qe and the vertical axis is
Mg _ap with respect to a family of fixed values for Fig. 12. Using peak-gain curves in a design.
Ln. Fig. 12b is used to illustrate how Fig. 12a is
formed.

Texas Instruments 3-17

17 SLUP263
From a plot of gain curves, for example from optimal design. However, LLC converters have
Fig. 6b, which is partially copied to the lower half some things in common that can be used to guide
of Fig. 12b, one attainable peak-gain value, Mg_ap the selection:
= 1.2, can be located at the curve with (Ln, Qe) = • A smaller Ln can make the peak gain higher for a
(5, 0.5). This point can be plotted to Fig. 12a at fixed Qe, keeping the design’s operation out of
(Mg _ap, Qe) = (1.2, 0.5). (Note that Ln = 5 at this the capacitive region. Since Ln is a ratio of the
point.) Because all curves in Fig. 6b have a fixed magnetizing inductance (Lm) to the series reso-
Ln = 5, that figure can be used to repeat the process nant inductance (Lr), a smaller Ln usually results
with different Qe values. Then a peak-gain curve from a smaller Lm, and vice versa. Equation (13)
can be formed as a function of Qe with a fixed Ln indicates that a smaller Lm will introduce higher
= 5, shown in Fig. 12a. The process can be repeated magnetizing current. This can help ZVS but will
for different Ln values of interest, producing the increase conduction losses.
results in Fig. 12a. • A smaller Qe makes the peak gain higher while
associated gain curves have a larger frequency
How Are Mg _ap Curves Used in a Design?
variation for a given gain adjustment. A large Qe
With Mg _max already determined for a partic-
results in a very low peak gain, which may not
Topic 3

ular design from Equation (28), Mg _max can be

meet the design requirements.
plotted as a horizontal line on Fig. 12a. Any Mg_ap
values above this line are greater than Mg_max , so • With these considerations in mind and from
the designed converter should operate in the design practice, a good start is to select a value
inductive region. For example, for Mg_max = 1.2, any for Ln around 5 and for Qe around 0.5 so that the
corresponding gain curves will be neither too
values of Mg _ap can be selected that are greater
than 1.2, as shown in Fig. 12a. Then the selected flat nor too steep.
value meets the maximum-gain requirement. • Reiteration is usually needed after an initial
From the selected Mg _ap value, Ln and Qe values selection.
can then be selected. For example, selecting a
D. Peak-Gain Curves from a Bench Test
value from the curve of Ln = 5 provides the Ln
The attainable peak-gain curves shown in Fig.
value right away. Since a gain value greater than
12a were made from the gain function described
Mg _max needs to be selected, Qe would have to be
by Equation (23), but Equation (23) was developed
less than 0.5, based on Fig. 12a. Similarly, a
with approximations. These approximations allow
smaller Ln provides more gain and Ln can be
errors in the peak-gain curves, causing accuracy
selected by interpolating as shown in Fig. 12a. For
concerns. To test the accuracy, a comparison was
example, if a value of 0.45 is selected for Qe, the
made between the gain function of Equation (23)
corresponding Mg _ap value with Ln = 3.5 would be
and a bench test with a 135-kHz series resonant
1.56 > Mg _max = 1.2, which satisfies the design
frequency. The peak-gain values were found to
requirements.
differ from those shown in Fig. 12a and from the
What Ln and Qe Values Are Best if They Are All gain curves shown in Fig. 6.
Greater than Mg _max?
Different applications may require the selection
of unique values for Ln and Qe to achieve an

Texas Instruments 3-18

18 SLUP263
The comparison results are plotted in Fig. 13a. obvious that this can be done by selecting proper
The solid line shows the result based on Equation values for Ln and Qe. After Ln and Qe are
(23), and the discrete points (t) show the results obtained, the resonant circuit’s parameters (Cr,
from the bench test. This comparison supports the Lr, and Lm) can be calculated based on Equations
argument that the FHA-based gain function of (22), (1), and (21), respectively:
Equation (23), while diverging for frequencies
away from resonance, is accurate enough and 1
Cr = (34)
acceptable in the vicinity of series resonance. 2πfsw R e Qe fsw = f 0
One other interesting observation is that the
peak gain and attainable peak gain from the test
are much larger than those obtained from the
2.0
(65, 1.90)
FHA-based gain function. Certainly this is good
Bench Test
Measurements
for a design, as it yields more design margin (80, 1.58) Plot Based on
before operation enters the capacitive region. From
(60, 1.57) Equation 18

this viewpoint, computer-based circuit simulation

1.4

should be conducted to supplement an FHA design

(55, 1.27) (100, 1.21)

Topic 3
Gain, Mg
if more accuracy is desired prior to hardware
(135, 0.99)

implementation. (170, 0.87)

In practice, to reduce the potential effect of (200, 0.78)

inaccuracy, peak-gain curves may be regenerated

(40, 0.70) (240, 0.72)
0.6
by experiment and/or by computer-based circuit (30, 0.51) (400, 0.56)

simulation to replace the curves from Equation

(23). Fig. 13b shows the peak-gain curves resulting
from the experiment. Compared to Fig. 12a, Fig.
f0 = 135 kHz
0.0
13b presents higher gain values. For example, for 10 100 1000

Ln = 5 and Qe = 0.5, the attainable peak gain from

Frequency, fsw (kHz)

Fig. 13b is Mg_ap = 1.65, versus 1.2 from Fig. 12a. a. Comparison of FHA-based gain function and
bench test.
E. Resonant-Network Design Flow
The design procedure that has been described 3
can be summarized as follows:
• First, terminal voltages Vo_min and Vin_max, used
2.8
Attainable Peak Gain, Mg_ap

in Equation (27), and Vo_max and Vin_min, used in

2.6

Equation (28), must be taken from the converter 2.4 Ln = 1.5

specifications. 2.2
• Second, the transformer turns ratio (n) can be Mg_ap = 1.65
obtained from Equation (33). Then the two hori-
2
Qe = 0.5 Ln = 2.0
zontal lines represented by Mg _min and Mg_max
1.8

can be calculated. From the converter’s load 1.6 Ln = 3.0

specifications, the load current with its 1.4
corresponding resistance (RL ) can be obtained at Ln = 5.0
any specified load condition. Then the AC
1.2
Ln = 9.0
equivalent load resistance (Re ) in the FHA circuit 1

model can be determined from Equation (9).

0.15 0.35 0.55 0.75 0.95 1.15
0.25 0.45 0.65 0.85 1.05 1.25
• Third, two proper gain curves must be found that Quality Factor, Q e
will cross over the two horizontal lines b. Peak-gain curves from test.
represented by Mg _min and Mg _max within
selected or specified frequency limits. It is Fig. 13. Peak-gain curves from experiment.

Texas Instruments 3-19

19 SLUP263
Iv. desIgn exAmpLe
1
Lr = (35)
(2πfsw ) 2 Cr This section will demonstrate step-by-step
fsw = f 0 how to use the described method to design an LLC
resonant half-bridge converter. The design is
Lm = Ln Lr (36) oriented to applications with low output voltage,
The design method can also be summarized such as the ATX12 power supplies used in
with the flowchart shown in Fig. 14. computers and servers, where energy conservation
is important.

Vin
Converter Specifications n
2Vo
3.0

2.8 Ln = 1.5
Topic 3

Ln = 2.0
Attainable Peak Gain, Mg_ap

2.6 Ln = 3.0
Ln = 3.0 Ln = 4.0
2.4 Ln = 5.0 n  Vo_min
Ln = 6.0 M g_min 
Ln = 8.0
2.2 Ln = 3.5 by Ln = 9.0
Interpolation
Vin_max / 2
2.0 Mg_ap = 1.56
Qe = 0.45
1.8
Ln = 1.5
1.6
Ln = 5 n  Vo_max
1.4 Mg_ap = 1.2
Qe = 0.5
M g_max  Magnetizing Inductance
1.2 Vin_min / 2
1.0
0.15 0.35 0.55 0.75 0.95 1.15 L m  Ln  Lr
Quality Factor, Qe

Resonant Inductor

Choose L n and Q e 1
Lr  2
(2fsw)  Cr
Change L n and Q e Resonant Capacitor
Check Mg and fn
Against Graph
No 1
Cr 
1.9 Ln = 3.5 Are Values 2 fsw R eQe
Qe = 0
Within
1.7
fn_min = 0.65 Limits? Yes
1.5 Mg_max Calculate R e
Q e = 0.47 Mg_max = 1.3
Gain, Mg

Mg_min
1.3
fn_max 2 2 V2
1.1
Mg_min = 0.99 fn_min Re  8 ×2n × R L  8 ×2n × o
  Pout
0.9

Q e = 0.52
0.7
fn_max = 1.02
0.5
0 0.5 1 1.5
Normalized Frequency, fn

Fig. 14. Flowchart of resonant-network design.

3-20
Texas Instruments 20 SLUP263
The converter’s electrical specifications are as efficiency-boosting features and high-level protec-
follows: tion features that provide a cost-effective solution.
• Input voltage: 375 to 405 VDC The step-by-step design demonstration will focus
• Rated output power: 300 W mainly on the power stage. For those interested in
• Output voltage: 12 VDC how to use and program the UCC25600, please
• Rated output current: 25 A refer to its data sheet (Reference [1]).
• Output-voltage line regulation (Io = 1.0 A): ≤ 1%
B. Design Steps
• Output-voltage load regulation (Vin = 390 V):
≤ 1% 1. Determine Transformer Turns Ratio (n)
• Output-voltage peak-to-peak ripple (Vin = 390 V The transformer turns ratio is determined by
and Io = 25 A): ≤ 120 mV Equation (33):
• Efficiency (Vin = 390 V and Io = 25 A): ≥ 90%
Vin / 2 Vin _ nom / 2
• Switching frequency (normal operation): 70 to n = Mg × =
150 kHz Vo Vo_ nom
Mg = 1

A. Block Diagram of Proposed From the specifications, the nominal values

Topic 3
Converter Circuit for input voltage and output voltage are 390 V and
A block diagram of the proposed circuit is 12 V, respectively, so the turns ratio can be
shown in Fig. 15. For clarity, some auxiliary func- calculated as
tions are not included. For the LLC resonant-mode Vin _ nom /2 (390 V)/2
controller, the UCC25600 can be a good choice. n= = = 16.25 ⇒ 16.
Vo _ nom 12 V
This eight-pin device has built-in, state-of-the-art,

DT1 Q1
Lr T1
Cin
n:1:1 Vo
Ir
Io
Lm
Q2
Co +
Cr RL
ID1 ID2
D1 D2
U1
8 3
GD1 OC Vs
UCC25600 RT1 R o1
5 2
GD 2 RT
U2
7 1
VCC DT
RT2
Cf Rf1
6 4
GND SS
CB R DT R o2
C SS
U3

Fig. 15. Proposed circuit for the design example.

Texas Instruments 3-21

21 SLUP263
2. Determine Mg _min and Mg _max 4. Determine the Equivalent Load Resistance
Mg _min and Mg _max can be determined by using (Re ) in Fig. 5b
Equations (27) and (28), respectively: Re is determined from Equation (9). At full load,
n × (Vo _ min + VF ) 8× n2 Vo 8 ×162 12 V
M g _ min = Re = × = × = 99.7 Ω .
Vin _ max /2 π2 Io π2 25 A
16 × [12 V × (1 − 1%) + 0.7 V] At 110% overload,
= = 0.99
(405 V)/2 8× n2 Vo 8 ×162 12 V
Re = × = × = 90.6 Ω .
n × (Vo _ max + VF + Vloss ) π2 Io π 2 25 A ×110%
M g _ max =
Vin _ min /2
5. Design Resonant Circuit’s Parameters
16 × [12 V × (1 + 1%) + 0.7 V + 1.05 V] The resonant circuit’s parameters are determined
= from Equations (34), (35), and (36). A switching
375/2
frequency of 130 kHz may be selected initially for
Topic 3

= 1.18 the series resonant frequency, and then the resonant

In these calculations, 1% is used to adjust circuit’s parameters can be calculated at full load:
output voltage from the line and load regulation. 1
VF = 0.7 V is assumed for the secondary-side Cr =
2π× Qe × f 0 × R e
diode’s forward-voltage drop. Vloss = 1.05 V is
assumed for the voltage drop due to power losses. 1
If the efficiency is assumed to be 92% (> 90% as =
2π× 0.45 ×130 ×103 Hz × 99.7 Ω
required by the specifications), then 8% of the
total power would be power losses. If all losses are = 27.3 nF ⇒ 12 nF × 2 + 3.3 nF
referred to the output voltage, then 8% loss at 25 A
would drop the output voltage to 1
Lr =
300 W (2π× f 0 ) 2 Cr
× 8%
92%
= 1.05 V. 1
25 A =
This is added to Mg _max to maintain voltage-load (2π×130 ×10 Hz) 2 × 27.3 ×10−9 F
3

regulation. = 54.9 µH ⇒ 60 µH
To keep operation within the inductive region
with an overload-current capability of 110%,
L m = L n × L r = 3.5 × 60 = 210 µH
Mg_max is increased from 1.18 to 1.18 × 110% = 1.30.
3. Select Ln and Qe 6. Verify the Resonant-Circuit Design
From Fig. 12a, if the values Ln = 3.5 and Qe = 0.45 The design parameters are as follows:
are selected, the corresponding Mg _ap = 1.56, • Series resonant frequency:
which is greater than Mg _max = 1.30. A curve for
Ln = 3.5 is not shown in Fig. 12a, but it can be 1
f0 =
obtained by interpolating the curves of Ln = 3 and 2π× L r × Cr
Ln = 4.
1
=
2π× 60 ×10−6 H × 27.3 ×10−9 F
= 124.4 kHz

Texas Instruments 3-22

22 SLUP263
• Inductance ratio:
Ln = 3.5
210 µH
1.9
L
Ln = m = = 3.5
Qe = 0
Lr 60 µH 1.7
fn_min = 0.65
• Quality factor at full load: 1.5 Q e = 0.47 Mg_max = 1.3

Gain, Mg
L r /Cr
Qe =
1.3
Re Mg_min = 0.99
1.1

(60 ×10−6 H) / (27.3 × 10−9 F)

= = 0.47
99.7 Ω
0.9

Q e = 0.52
• Quality factor at 110% overload: 0.7
fn_max = 1.02

L r /Cr
Qe =
0.5
0 0.5 1 1.5
Re

Topic 3
Normalized Frequency, fn

(60 ×10−6 H) / (27.3 ×10

−9
F) Fig. 16. Verification of resonant-circuit design.
= = 0.52
90.6 Ω
Plot the gain curves corresponding to the The resonant circuit’s current (Ir) is determined
design parameters (Fig. 16). The plot shows that from Equation (14):
the initial design meets the requirements of both
Equation (26) and the following frequency I r = I 2m + Ioe
2
= (1.63 A) 2 + (1.91 A) 2 = 2.51 A
specifications:
This is also the transformer’s primary winding
• The frequency at series resonance is f0 = 124.4
current at fsw_min.
kHz.
• The frequency at (Mg _min, fsw_max) is fn_max × f0 8. Determine the Secondary-Side Currents
= 1.02 × 124.4 kHz = 126.9 kHz. The total secondary-side RMS load current is the
• The frequency at (Mg _max, fsw_min) with an overcurrent referred from the primary-side current (Ioe)
load (Qe = 0.52) is fn_min × f0 = 0.65 × 124.4 kHz to the secondary side:
= 80.7 kHz. Ioe _ s = n × Ioe = 16 ×1.91 A = 30.6 A
7. Determine the Primary-Side Currents
Since the transformer’s secondary side has a
The primary-side RMS load current (Ioe) with a
center-tapped configuration, this current is equally
110% overload is determined from Equation (8):
split into two transformer windings on the
π Io 25 A ×110% secondary side. The current of each winding is
Ioe = × = 1.11× = 1.91 A
2 2 n 16 then calculated as
The RMS magnetizing current (Im) at fsw_min = 2 × Ioe _ s 2 × 30.6 A
80.7 kHz is determined from Equation (13): Isw = = = 21.6 A.
2 2
nVo The corresponding half-wave average current is
I m = 0.901×
ωL m
2 × Ioe _ s 2 × 30.6 A
Isav = = = 13.8 A.
16 ×12 V π π
= 0.901×
2π× 80.7 ×103 Hz × 210 ×10−6 H
= 1.63 A

Texas Instruments 3-23

23 SLUP263
9. Selectthe Transformer 1000
The transformer can be built or purchased from a
catalog. The specifications for this example are: 500
12 nF,

• Turns ratio (n): 16

300 V,

AC Voltage, Vin_max (VRMS )

100 kHz

• Primary terminal voltage: 450 VAC

• Primary winding’s rated current, Iwp: 2.6 A
• Secondary terminal voltage: 36 VAC 6.2 nF

• Secondary winding’s rated current, Iws: 21.6 A

100

(center-tapped configuration) 50
• Frequency at no load: 127 kHz 12 nF
• Frequency at full load: 80 kHz 33 nF
• Insulation between primary and secondary sides:
IEC60950 reinforced insulation
10
10. Selectthe Resonant Inductor
10 k 100 k 1M 10 M

The inductor can be built or purchased from a

Frequency, f (Hz)
Topic 3

catalog, with these specifications: Fig. 17. Voltage derating from frequency.
• Series resonant inductance, Lr: 60 μH
• Rated current, ILr: 2.6 A
• Terminal AC voltage: Ir
VCr = X Cr × I r =
VLr = ωL r × I r = 2π× 80.7 ×103 × 60 ×10−6 × 2.6 ω× Cr

= 75.7 V ⇒ 100 V 2.6 A

= = 187.9 V
2π× 80.7 ×10 Hz × 27.3 ×10−9 F
3
• Frequency range: 80 to 127 kHz
11. Select the Resonant Capacitor • RMS voltage:
The resonant capacitor (Cr) must have a low 2
 Vin _ max 
dissipation factor (DF) due to its high-frequency, VCr _ RMS =  2
 + VCr
high-magnitude current. Capacitors such as elec-  2 
trolytic and multilayer X7R ceramic types usually
have high DF and therefore are not preferred. NP0  405 V 
2
2
capacitors can be used due to their low DF, but =   + (187.9 V) = 276.3 V
their capacitance range presents limitations.  2 
Capacitors often used for LLC converters are • Corresponding peak voltage:
made with metalized polypropylene film. These
capacitors present very low DF and are capable of Vin _ max
VCr _ peak = + 2 × VCr
handling high-frequency current. 2
Before a capacitor is selected, its voltage rating
has to be derated with regard to the switching 405 V
= + 2 ×187.9 V = 467.4 V
frequency in use. Fig. 17 shows an example where 2
a 12-nF capacitor rated at 600 VRMS can be used
only up to 300 VRMS with a 100-kHz switching 12. Select the Primary-Side MOSFETs
frequency. Specify the MOSFET parameters required for the
The selected capacitor (Cr) must meet these converter. Each MOSFET sees the input voltage
additional specifications: as its maximum applied voltage:
• Rated current, ICr: 2.6 A VQ1_ peak = VQ2 _ peak = Vin = 405 V ⇒ 500 V
• AC voltage, calculated from the circuit in Fig. 9a:

Texas Instruments 3-24

24 SLUP263
Each MOSFET conducts half of the resonant net- These calculations verify that Equation (32a) is
work’s current in steady state after the resonant true:
capacitor’s voltage has been established. However, 1 1
during the initial start-up and transient, the current (L m + L r ) × I 2m _ peak ≥ (2Ceq ) × Vin2
in each MOSFET can be as high as the resonant 2 2
current (Ir) with a 110% overload: To meet the requirements of Equation (32b), the
IQ1_ RMS = IQ2 _ RMS = I r = 2.51 A dead time should be designed as

MOSFET switching losses are minimized by t dead ≥ 16 × 200 ×10−12 F × 127 ×103 Hz
ZVS; therefore, the MOSFETs’ conduction losses × 210 × 10−6 H = 85.0 × 10−9 s.
may become the main concern for the design. This
suggests that MOSFETs with a low Rds_on should A tdead of 100 ns will meet the requirement.
be used, but with the recognition that there is
14. Select the Rectifier Diodes
usually a trade-off between Rds_on and Cds.
The diodes’ voltage rating is determined as
13. Design for ZVS Vin _ max /2

Topic 3
The converter’s input phase angle must be greater VDB = ×2
n
than zero, as described by Equation (30b). Based
on Step 6, this requirement has been met. (405 V)/2
The conditions under which the converter has = × 2 = 25 V ⇒ 30 V.
16
sufficient inductive energy and sufficient switching
dead time for ZVS are described by Equations The diodes’ current rating is determined as
(32a) and (32b), respectively. To check these 2 × Ioe _ s 2 × 30.6 A
conditions, it can be assumed that Ceq is mainly Isav = = = 13.8 A.
π π
from the MOSFETs’ Cds. For typical 500-V
MOSFETs, Cds is around 200 pF. If it is assumed
15. Select the Type of Output Filter and Specify
that Ceq = 200 pF and that the worst-case minimum
the Capacitors
magnetizing current (Im_min) is
In an LLC converter, the output filter may consist
n × Vo of capacitors alone instead of the LC filter seen in
I m _ min = 0.901× most pulse-width-modulated converters, although
2π× fsw × L m fsw =
127 kHz a small second-stage LC filter can be an option. If
the filter has only capacitors, they should be chosen
16 × 12 V to allow conduction of the rectifier current through
= 0.901×
2π×127 ×103 × 210 ×10−6 all AC components.
The rectifier’s full-wave output current is
= 1.03 A, expressed as
then, to verify Equation (32a), π
I rect = Isw = × Io .
1 2 2
(L + L r ) × I 2m _ peak
2 m Then, for the load current (Io), the capacitor’s RMS
1 current rating at about 100 kHz is calculated as
= (210 ×10−6 H + 60 ×10−6 H) × ( 2 ×1.03 A) 2
2
2
 π  π2
= 286.5 ×10 −6
joules, I Co =  × Io − Io2 = − 1 × Io
2 2  8
and
= 0.482 × Io = 0.482 × 25 A = 12.1 A.
1
(2Ceq ) × Vin2 = 200 ×10−12 F × (405 V) 2
2 Usually a single capacitor will not allow such a high
= 32.8 ×10−6 joules. RMS current, so several capacitors connected in

Texas Instruments 3-25

25 SLUP263
parallel are often used and may offer a lower pro- along with the FHA method. Using the two
file. Aluminum solid capacitors with conductive- methods together is effective and provides a good
polymer technology have a high current rating and balance. The FHA method is very effective for
a low equivalent series resistance (ESR), making initiating a design because it provides a functional
them a good choice. connection between a frequency-modulated
The ripple voltage is a function of the amount switching-mode converter and established sinu-
of AC current that flows in and out of the capacitors soidal AC circuit design and analysis, giving
with each switching cycle, multiplied by the designers insight into the converter’s operation.
capacitors’ ESR. Since all electric current, includ- Computer-based circuit simulation, on the other
ing the load’s DC current, can be assumed to flow hand, compensates the FHA method with accurate
in and out of the filter capacitors, this is a very design values. The combined design approach can
good estimate of the ripple voltage. To meet the significantly reduce the number of design itera-
specification for a 120-mV ripple voltage, the max- tions, shortening the time from starting a design to
imum ESR should be realizing its final product.
Vo _ pk-pk Vo _ pk-pk vI. concLusIon
ESR max = =
Topic 3

I rect _ peak  π 
 4 × Io  × 2 This topic has presented comprehensive
  considerations for designing an isolated LLC
0.12 V resonant half-bridge converter. It has been shown
= = 3.05 mΩ. that the FHA method is especially effective for
π
× 25 A initiating a new design of this type. A step-by-step
2
design example has also been presented to
Any capacitance value can be used as long as demonstrate how to use this method.
combined capacitors meet the following speci-
fications: vII. AcknowLedgments
• Voltage rating: 16 V The author would like to express sincere grati-
• Ripple-current rating: 12.1 A at 100 kHz tude to Richard Garvey, Bob Mammano, Bing Lu,
• ESR: < 3 mΩ and Bob Neidorff for their valuable discussions
during the preparation of this topic.
16. Verify the Design with a Bench Test
To verify the design’s performance, a physical vIII. references
converter needs to be built and bench tested.
Generally, one or more design iterations may be [1] “8-Pin High-Performance Resonant Mode
needed to meet all specifications and to optimize Controller,” UCC25600 Data Sheet, TI
the design. The final design used the following Literature No. SLUS846
parameters:
• Transformer turns ratio: n = 17:1:1 [2] “Using the UCC25600EVM,” User’s Guide,
TI Literature No. SLUU361
• Resonant network’s parameters: Lm = 280 μH,
Lr = 60 μH, and Cr = 24 nF [3] Bob Mammano, “Resonant Mode Converter
Topologies,” Unitrode Design Seminar, 1985,
Detailed design files and test results can be
TI Literature No. SLUP085
found in Reference [2]. Physical EVM boards are
also available from TI. Several critical test wave- [4] Bing Lu et al., “Optimal design methodology
forms are shown in Fig. 18 for immediate reference. for LLC resonant converter,” Applied Power
Electronics Conference and Exposition
V. Computer Simulation and FHA (APEC) 2006, pp. 533–538.
For designing an LLC resonant half-bridge
[5] S. De Simone, et al., “Design-oriented steady-
converter, it is strongly recommended that a
state analysis of LLC resonant converters
computer-based circuit-simulation method be used
based on first-harmonic approximation,”

Texas Instruments 3-26

26 SLUP263
International Symposium on Power Electron- [7] Thomas Duerbaum, “First harmonic approxi-
ics, Electrical Drives, Automation and Motion mation including design constraints,” Twentieth
(SPEEDAM) 2006, pp. S41-16 to S41-23. International Telecommunications Energy
[6] Hangseok Choi, “Analysis and design of LLC Conference (INTELEC) 1998, pp. 321–328.
resonant converter with integrated trans- [8] R.L. Steigerwald, “A comparison of half
former,” Applied Power Electronics Confer- bridge resonant converter topologies,” IEEE
ence and Exposition (APEC) 2007, pp. 1630– Transactions on Power Electronics, Vol. 3,
1635. No. 2, pp. 174–182, April 1988.

Topic 3
Input Voltage, Output Ripple Voltage 90 mV
Efficiency (%)

85 (50 mV/div)
Vin
405 V
390 V
375 V

65
1 5 10 15 20 25 Time (5 µs/div)
Load Current (A)

a. Efficiency. b. Output ripple voltage (full load).

VCr Vgs_Q2 (20 V/div)

1
(200 V/div)
1
(200 V/div) Ir
VL (1.2 A/div)
3 r 3

VLm
4
(200 V/div) VCr
(100 V/div)
Vds_Q2
(500 V/div)
2 4
Vds_Q2 (500 V/div)
2
Time (5 µs/div) Time (1 µs/div)

c. Voltage waveforms in resonant d. Resonant network’s current and

network (full load). voltage (full load).
Fig. 18. Critical test waveforms of the design.

3-27
Texas Instruments 27 SLUP263
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SLUP263
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Understanding and using LLC

Converters to Great Advantage

PART 1: Overview of the Transition from Conventional PWM Power Conversion to

Resonant Topologies
Introduction
At an early moment during the development of conventional “square-wave” switching power conversion, it was
said that nature abhors any attempt to suddenly turn OFF the current passing through an inductor. That fear
prompted early attempts at creating “resonant topologies”. But for various reasons, in particular a very wide,
almost uncontrolled switching frequency and resulting EMI spread, resonant topologies did not become
mainstream, and still aren’t. But nowadays there is a sudden resurgence of interest, primarily through the “LLC
topology”. This unique combination of two inductors and one capacitor (“L-L-C”), offers a relatively narrow
range of switching frequencies, which are much easier to design a standard EMI filter for, combined with the
capability of producing zero-voltage switching (soft-switching) through careful design which can significantly
improve EMI and efficiency over a wide load range. But the overall topic and analysis is still considered
complex, almost mystical, and is poorly understood. A majority of successful LLC designs are simply based on
trial and error, i.e. the art of tweaking, both in a real lab environment, and in a virtual lab using Spice-based
simulators. This has significantly hindered their adoption in a modern design-and-development, flowchart-
based, commercial product environment.

To tackle the underlying “fear of resonance”, in these pages, emphasis is laid on first understanding the guiding
principles of resonance and soft-switching. Only after acquiring the underlying intuition and analytical depth, do
we start to build the LLC converter, and we do that in steps: assembling the building-blocks one by one, at each
stage analyzing the performance, providing the necessary simplified math, and validating each step via Mathcad
and Simplis (Spice). In the process, a very unique method is being proposed on these pages perhaps for the very
first time.

Soft and Hard Switching

To close loose ends, we need to revisit some of the originally expressed anxiety against interrupting inductor
current in “square-wave” switching power conversion. That fear too is admittedly somewhat true, because
energy is stored in an inductor as ½ ×L ×I2, which depends on the current passing through it at any given
moment. Since by the Law of Conservation of Energy, energy cannot just be “willed away” in an instant, we
should never try to interrupt the inductor current by simply placing a switch (or FET) in series with it and turning
that OFF. That attempt will destroy the switch --- on account of a huge voltage spike (induced voltage) which will
suddenly appear. But there is a way out as people soon discovered: we can consciously provide an alternate
“freewheeling” path for the inductor current --- to keep it flowing smoothly (without any discontinuity) once the
switch turns OFF. That led to the “catch diode” seen in conventional switching power conversion. The provision
of this diversionary diode path, a detour in effect for inductor current, is a much wiser option than trying to
contain the current in a cul-de-sac of sorts, leaving it no way out. And that diode is the reason we can, by now,
manage to get away turning the switch (FET) of any conventional power converter, ON and OFF, repetitively,

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hundreds of thousands of times every second, and reliably so. Nature is clearly not complaining. But there was
a price to pay for this inductor-driven brinksmanship of sorts. Diverting the current at the very last moment, and
we mean very last moment here, does create penalties. Because whenever we try to turn OFF inductor current,
by say dragging the Gate of the series FET to ground (or to its Source terminal as applicable), we do not manage
to instantaneously reduce the current in the FET as we had perhaps hoped to do. On closer analysis we see that
there needs to be a full rail-to-rail voltage swing completed (across the FET), just to be able to forward-bias the
catch diode, to get it to even start taking up some of the current away from the FET. But before that happens,
we cannot afford to somehow force the FET to relinquish its current, for fear of the induced voltage effect. In
other words, there is a transitory moment where there is a full voltage swing taking place across the FET.
Though the average value of this voltage swing is half its peak-to-peak value, this is present with the full pre-
existing inductor current continuing to pass through the FET. There is no reduction in FET current yet, because
the diode is still in the process of being “set up” to start taking up slack. And that does not even happen till the
entire voltage swing is completed and the diode gets forward-biased. Geometrically speaking, we see an
“overlap” of voltage and current across the FET as shown in Figure 1, and that constitutes “crossover”
(switching) losses in the FET. Mathematically speaking, there is a non-zero V x I product across the FET during
the switch transition. Yes, there are other subtle contributors to this crossover loss component too, such as the
forcible discharging (burning up of energy) of the parasitic capacitance across the FET, and also the Drain to
Gate “Miller effect” causing an increase in switching (transition) time and causing even more V-I crossover
energy to be wasted, etc. Therefore, as we go to higher and higher switching frequencies, this useless “work”
done by the input source (in the form of dissipation), leads to several percentage points of degradation in
overall efficiency. It is for these reasons that the small, but extremely significant moment of switch transition, is
garnering a lot of attention today, piquing renewed interest in resonant topologies which offer hope in this
regard.

The reduction of switching losses during the few nanoseconds of switch state-transition (crossover of the FET),
is critical to improving conversion efficiency. But we are also hoping to reduce EMI by the softer “resonant
transitions”, since we know that conventional “hard transitions” are the main source of most of the EMI in
conventional converters. We are almost intuitively expecting that by using resonant topologies, the voltage will
be softly reduced by self-resonant action, so that the V-I “overlap” will be likely reduced, or become almost
zero, as also displayed in Figure 1. If so, that should help reduce EMI too.

Note: Another way out, suitable for low power applications, is to use discontinuous conduction mode (DCM), because we can thereby
ensure the current is zero whenever we turn the FET ON. We can implement this using the well-known “ringing choke converter” (RCC)
principle, which basically senses the ringing voltage of the inductor/transformer, to gauge when there is no residual current left (i.e.
core is de-energized), and turns the FET ON at that moment. This is variable frequency PWM, in the form of boundary-conduction
mode (BCM). It was actually used on a very wide scale in the 1980s in the form of the ubiquitous and historic Television Power Supply
flyback controller IC, the TDA4601, originally from Philips, and still available from Infineon. The modern iPhone charger uses the L6565
from ST microelectronics, which though based on the same old ringing choke principle of the TDA4601, prefers to call itself a QR (
quasi-resonant), ZVS (zero voltage switching) topology SMPS controller chip, in keeping with the times. But there are switching losses
when we turn OFF the FET!
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Keep in mind however, that the resonant soft-switching sketched intuitively in Figure 1, is only a “wish list” so
far. It is all much easier said than done. On deeper examination, all resonant topologies are not similar or
identical in all respects. Not all “naturally” offer soft-switching for example. In the well-known words of Bob
Mammano (quoted from his presentation titled “Resonant Mode Converter Topologies”, Topic 6, in the
1988/89 series of Unitrode Power Supply Design Seminars): “While basically simple, this principle can be applied
in a wide variety of ways, creating a bewildering array of possible circuits and operating modes”. In fact not all
resonant topologies and modes are necessarily even conducive to the task of reducing switching losses,
reducing stresses, improving efficiency, or even reducing EMI. In fact, some do not even lend themselves to a
proper control strategy as we will see. This last aspect is extremely important but often overlooked in a virtual
lab. The entire topic of resonant power conversion turns out to be an extremely complex one: to a) understand,
and b) implement effectively.

But do we at least fully understand conventional power conversion well-enough? We may realize we need to do
better in that regard, because some critical hints for the successful analysis and implementation of resonant
topologies are contained in conventional power conversion. We may have missed the signs. For example, a
potentially puzzling question in a conventional converter is: Why do we not have any overlap of voltage and
current across the catch diode? As indicated in Figure 1, there is in fact no significant V-I overlap across the
diode, which is the reason we typically assume almost zero switching losses for the diode in an efficiency
calculation. This does remain a valid assumption to make, even when we move to synchronous topologies ---- in
which we replace (or supplement) the catch diode with another FET. So now, consider this puzzle: We now have
a totem pole of near identical FETs (in a synchronous Buck for example), yet we somehow still disregard the
switching losses in the lower FET, but not in the upper FET. How come? In what way is the location of the lower
FET so different from that of the upper FET? Why does nature seem to favor the top location from the bottom
one?

Even more surprisingly, if we delve deeper we will learn that in one particular operating mode, for just part of
the cycle, even the synchronous Buck exhibits almost no crossover loss in the top (control) FET, and actually
shifts those losses to the lower (synchronous) FET! How did this role-reversal happen? Once we understand all
this, we will understand the intuitive direction we need to take in designing good resonant topologies too.

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Conventional hard-switching

1 Diode current
6
3

Voltage at Switching Node

4
(across diode)

5 Voltage across Switch

Crossover
losses in
2 7 Switch

V-I overlap V-I overlap

Switch Current

Turn-on transition Turn-off transition

Wishlist: soft (resonant) switching

Voltage across Switch

Switch Current

Figure 1: Hard switching compared to resonant (soft) switching

Two Key Concerns (Guiding Criteria)

These form our guiding criteria towards identifying suitable resonant topologies. The most basic questions we
need to ask of any proposed circuit are:

Question 1: Does it really reduce switching losses? If so, in which region of its operation (or operating mode)?
We need to know the line and load boundaries of any such soft-switching region, and thus try to ensure that at
least at max load we can significantly reduce switching losses (and preferably continue to do so at light loads
too). Finally, we hope we can do this, without asking for, or somehow creating, too wide a variation in the
switching frequency. Because, though we may have soft- switching, if we have a very wide variation in switching
frequency, that too cannot be good from the viewpoint of either the economics or the size of the EMI filtering

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stage. We do not gain by simply shifting the cost and dissipation, from one circuit block to another: the EMI
stage in this case.

Question 2: The simplest, seemingly most obvious, question can in fact become the hardest to answer: how do
we “regulate” the output voltage (of a resonant converter)? Do we do pulse width modulation (PWM) or do
something else? And is there a simple way to implement an unambiguous, almost “knee-jerk” (rapid) response
to disturbances, analogous to what we do in conventional power conversion? We remember that in
conventional converters, we pretty much blindly increase the duty cycle in response to a fall in the output below
a set/reference level, for any reason whatsoever. Similarly, we decrease the duty cycle if the output rises. That is
the heart of basic PWM implementation. We also know that, luckily, for all conventional topologies, a falling
input rail, or an increasing load, both tend to cause the output to fall, both therefore demanding an increase in
duty cycle (pulse width) to correct. Though that rapid response does in effect, lead to the complicated area of
loop stability, the good news is that we do have a simple, immediate, and unambiguous response to line/load
disturbances, one which is guaranteed to always be in the right “direction” for achieving correction. We do not
for example have a complicated control scenario which asks of us something like this: “increase the duty cycle if
the input rail falls to 80% of its set value, but thereafter decrease the duty cycle (to correctly regulate the
output)”. This algorithm would be impossible to implement practically. But unfortunately, in resonant
topologies, we can get exactly this odd situation. If we do not define a very clear region of operation (the
allowable/expected line and load variation, related to component selection), we will end up in an area of
operation where we are expecting the output to get corrected by our response, but in fact the output veers
away in the opposite direction, hopefully collapsing, not overshooting. This becomes another additional, and
very tricky, part of the resonant topology puzzle that we seek to uncover in these pages.

Above we have listed the two key concerns or guiding criteria which will be addressed as we go along. But
before we do that, as mentioned, first we need to understand a little more about conventional converters, and
understand in particular, why the switching losses are “lop-sided” --- i.e. losses in one FET, not in the other, in a
synchronous Buck converter for example. That will take us to the next step of development of resonant
topologies.

Switching Losses in a Synchronous Buck and Lessons Learned

In Figure 1, we first consider the turn-on transition (on the left side). Prior to this, the diode is observed carrying
the full inductor current (circled “1”). It is obviously forward-biased. But then the switch starts to turn ON, trying
to take away the inductor current (circled “2”). Correspondingly, the diode current starts to fall (circled “3”).
However, the important point is that while the switch current is still changing, and has not yet taken over the
full inductor current, the diode needs to continue to conduct whatever remaining current, i.e. the difference
between the inductor current and the switch current, at any given moment. However, to conduct even some
current, the diode must remain fully forward-biased. So, there is no change in the voltage across the diode
(circled “4”), or therefore, across the FET (circled “5”) as the current through the FET swings from zero to max,

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and in the diode from max to zero (crossover). Finally, only when the entire inductor current has shifted over to
the switch, does the diode “let go” of the voltage. The switching node is released, and it flies up very close (a
little higher) to the input voltage rail (circled “6”) --- and so now, the voltage across the switch is allowed to fall
(circled “7”) by Kirchhoff’s voltage law.

We therefore see that at turn-on, the voltage across the switch does not change till the current waveform has
completed its transition. We thus get a significant V-I overlap in the switch (FET). That is “hard-switching” by
definition.

If we do a similar analysis for the turn-off transition (right side of Figure 1), we will see that for the switch
current to start decreasing by even a small amount, the diode must first be “positioned” (in terms of voltage) to
take up any current coming its way (relinquished by the switch). So the voltage at the switching node must first
fall close to zero (a little below ground), so as to forward-bias the diode. That also means the voltage across the
switch must first transition fully, before the switch current is even allowed to decrease.
We therefore see that at turn-off, the current through the switch does not change till the voltage waveform has
completed its transition. We thus get a significant V-I overlap in the switch (FET).

But in neither transition, turn-on or turn-off, is there any significant V-I overlap across the diode. We therefore
typically assume that there are negligible switching losses in the diode in a conventional topology --- it is the
switch (FET) that gets hard-switched during both transitions.
Note: In a Boost topology, despite no measurable V-I overlap term present across the diode, the diode can surprisingly cause
significant additional switching losses to appear in the FET rather than in itself. For example, we can get losses in the FET due to shoot-
through (poor reverse recovery characteristics of the catch diode, or the relatively “poor” body diode of a synchronous boost
converter’s synchronous FET). In other words, the diode may technically never “see” any significant V-I crossover loss across itself, but
can certainly cause, or instigate, the switch (FET) to experience significant, perhaps even externally invisible, losses. This particular
situation is often tackled by trying to achieve zero-current switching (ZCS), rather than the more common ZVS (zero-voltage switching)
which are focusing on in these pages. One simple way out, especially for low-power applications, is to run the converter in DCM,
because if the boost diode is no longer carrying current, it has no reverse recovery issues either (it has already recovered when the
switch tries to turn ON).

However, now let us look at the synchronous Buck in Figure 2 more closely, at what really happens when the
inductor current is momentarily negative (below zero, i.e. flowing from top to bottom, through the lower FET).
Suppose during this negative current phase, the lower FET turns OFF, while the top FET is forced ON. It turns out
we have to pay close attention to what happens during the deadtime, i.e. during the small interval between one
FET turning OFF and the other turning ON. Most engineers are aware that the primary purpose of deadtime is to
avoid any brief possibility of both top and bottom FETS being ON at the very same moment, which would cause
efficiency loss due to cross-conduction/shoot-through, and possible destruction of the FETs too. But there is
another, subtle advantage that deadtime provides, as explained in Figure 2.

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From Figure 2 we can conclude that if the current is momentarily negative, and we turn OFF the lower FET at
that moment, the inductor will in effect resonate with the Drain-Source parasitic capacitances of the FETs,
causing the voltage at the switching node to rise, eventually causing a flow of current back into the input rail via
the body-diode of the top FET. Keep in mind that to cause the body diode to conduct, it must be forward-
biased. So the voltage on the switching node must swing. Now when the top FET turns ON, it does so with near-
zero voltage across it (a forward-biased body diode drop across it). That is “ZVS” by definition. We see the Top-
FET being “soft-switched” for a change. Though this effect is occurring only during part of the switching cycle, it
is exactly the way it can be made to happen in both (or more) FETs in resonant power conversion too.

Note: Hypothetically, if the average of the inductor current of the Buck falls completely below zero (no part of it positive), we would be
now constantly drawing current from the “output” (now really an input), and delivering it to the “input” (now really an output). We
would have in effect a full-fledged Boost topology, not a Buck anymore. And we also know that in a Boost, it is the lower FET that is the
“control FET” and the upper FET is the synchronous FET. We therefore intuitively expect to see only the lower (control) FET to have
switching losses in a Boost. And, quite expectedly, all the crossover losses of this reversed Buck (which actually makes it a Boost), will
now shift to the lower FET over the entire switching cycle. We will have no crossover loss anymore in the top FET. So the role-reversal
now makes sense. When only part of the inductor current is negative (in a synchronous Buck), a switch transition during that negative-
current time will produce switching losses in the synchronous (bottom) FET, not in the upper (control) FET. When a transition occurs
during the positive-current part of the cycle, the switch loss is in the control (top) FET as usual.
We have learned that if we can achieve ZVS for whichever FET has current flowing through its body diode (or an
anti-parallel diode placed externally across it) during the preceding dead time (just before transition). So, the
direction of inductor current at the moment of transition is the key that identifies (or distinguishes) which FET
position receives soft-switching and which one gets hard-switched. Keep in mind that what constitutes a
“positive” or a “negative” current depends completely on what we are calling the “input” and what is the
“output”, and which direction we consider “normal” energy flow.

Note that in either scenario above, we certainly need current passing through an inductance to try and “force
matters”. And of course, we also need to leave a small (but not too small) an intervening deadtime for the
induced voltage to be able to act. We also need enough inductance to force a full voltage swing. Very similarly,
in resonant topologies too, whatever the type of simple or complex L-C network being switched, we learn that
the tank circuit needs to appear “inductive” to the input source, for being able to achieve ZVS.

Summarizing, the two basic prerequisites for achieving ZVS are:

We need the current to “slosh” back and forth --- something that occurs naturally in resonant topologies, but is
also enforced in conventional half-bridge, full-bridge wave and push-pull topologies. All these are suitable
candidates for ZVS, subject to the following stated condition.

The tank circuit (network) impedance must appear inductive to the input voltage source, because that is what is
responsible, eventually, for trying to brute-force the current through (using induced voltage), in the process
creating zero voltage switching across the FETs --- though as mentioned, we also must have enough inductance
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(vis-à-vis available deadtime and parasitic FET output capacitances), so that the voltage on the swinging node
can be forced to swing in a timely manner (before deadtime runs out), so to reduce the voltage across the FET
before the FET is turned ON.

Note: Even in ZVS-eligible conventional topologies such as the full-bridge, we can enforce the second requirement above, and produce
“quasi-resonant (QR) ZVS”. These topologies are all based on the Forward converter topology using a transformer. We need to add a
small Primary-side inductance (often just the transformer leakage) for this purpose.
LIGHT LOADS:
SYNCHRONOUS MODE VIN OFF
VO
TOP FET

Q
OFF-TIME ON-TIME OFF-TIME ON-TIME OFF-TIME
A Q
Drives
Gate

ON
Dead Time
Qs
BOTTOM FET
Current
Ind.

VIN OFF
VO

Q
B Qs

OFF
CLOSEUP OF WAVEFORMS DURING ABOVE HIGHLIGHTED REGION
We get soft-switching in Top-FET (Q) here
GATE OF BOTTOM FET GATE OF TOP FET VIN OFF
DEAD TIME VO

Q
C Qs
ON

N T
R RE
CU Resonant action
R
TO
D UC
IN

VIN OFF
VO

Q
OFF

Qs
D
OSS TOP FET
V-I in TOP FET

D-S VOLTAGE ACR

Either ID or VDS almost zero here: no losses T
FE
P
TO
IN
T
D-S CURRRENT IN TOP FET EN
R RR
CU VIN ON
D-
S
VO

Resonant
E Q
action Qs
OFF
V-I in BOTTOM FET

T D-S VOLTAGE ACROSS BOTT

FE OM FET
M
TO
OT
NB
TI
RE
N Top FET turns ON with zero voltage
RR
CU across it (ZVS/lossless transition)
D- S

Roles are reversed for negative currents: we

A B C D E
V-I Overlap in
do have crossover loss in the bottom FET
bottom FET now, not in the top FET
Figure 2: We do get ZVS naturally, in some cases/modes of the synchronous Buck too
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Building Basic Resonant Circuits from Components: the “PRC”

In resonant topologies, just as in conventional switching power conversion, we try to pick reactive components
(inductors and capacitors). Because we know that ideally, they store energy, but cannot dissipate any. We
always require resistance, either in the form of intervening parasitics, or in the form of the load itself, to
dissipate any energy, either usefully or wastefully. But in addition, the L and C can pass energy back and forth
between each other on account of their complementary phase angles. We can try to use that useful property to
transport energy on their shoulders, from the input (source) to the output (load), somehow creating DC
regulation too along the way if possible, which is a fundamental requirement of any type of practical power
converter.

That is the general direction for implementing any “lossless” (high-efficiency) power conversion methodology.
The key difference between resonant topologies and conventional switching topologies is primarily related to
the actual “values” of the L and C components used. In conventional power conversion, we use relatively “large”
capacitors at the input and output, so the natural LC frequency happens to be very large relative to the
switching frequency. We just do not “see” resonant effects anymore, because we do not wait that long before
we switch. But if we reduce the L and C values significantly, we will start to see resonant effects even in
conventional power conversion. Keep in mind though, that just because they are “resonant”, doesn’t make
them acceptable or useful. Their eventual usefulness is judged mainly on the basis of the two “guiding criteria”
described previously.

Note: Modifying conventional topologies by reducing their L and C values is usually that is not the best way to go in creating
resonance, except for example in the “ZVS phase-modulated full-bridge”, which is best described as a “crossover converter” (in the
sense of a crossover-vehicle category), literally bridging conventional power conversion with resonant effects (but resonance occurring
only during the transition deadtimes). This maintains the desirable characteristics of constant clock frequency of conventional PWM
topologies, but uses resonance during deadtime for inducing soft-switching (in all the FETs).

To create proper resonant circuits, let us start with a simple inductance and a simple capacitance. But they are
not connected to each other yet. To make this “real”, let us pick some numerical values. We choose L = 100mH
and C= 10µF. These may seem rather big, but as a result, our switching frequency is also going to be low, and
that is quite helpful initially at least, for ease-of-discussion, and for cleaner and faster circuit simulations etc. So,
everything is initially being scaled to a lower switching frequency just for convenience.

Let us connect each separated L and C component to identical AC sources, of 30V (amplitude, or half peak-to-
peak value) with a frequency of 300Hz, and just see the currents through each. We run this through a Simplis
simulator. The results are presented in Figure 3.

As expected the input and output voltages on either component are the same, at 30V. The currents are
different. We expect the corresponding current amplitudes to be:

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ZC=1/(2×π×f×C) =1/(2×π×300×10-5) = 53.05Ω. So IC = V/ZC = 30/53.05 = 0.565 A.

ZL= (2×π×f×L) = (2×π×300×0.1) = 188.5 Ω. So IL = V/ZL = 30/188.5 = 0.159 A.

This is exactly what we got through the simulations shown in Figure 3. But via that figure, we see another
possibility, one that we can hopefully exploit: the peak of the inductor current comes a little later (exactly 1/4th
of a cycle) after the peak of the inductor voltage (which is the same as input voltage in this case). That is why we
usually say that the current lags the voltage in an inductor by 90°. We can confirm from conventional switching
power conversion too, that when we apply a voltage across an inductor, the current ramps up slowly. So current
does lag the voltage in that sense, though unfortunately, we can’t really visualize or define what the “lag” is for
non-sinusoidal waveforms as in conventional power conversion. Now, looking at Figure 3 once again, we see
that the cap voltage peak lags the cap current peak by exactly the same amount, i.e. 90°. In other words, the
capacitor and inductor currents are relatively exactly 180° out of phase. They are “complementary”, because
180° is just a change of sign or direction (with respect to each other). Note that we have implicitly
chosen/assumed the convention that current into the component (L or C) is “positive”, whereas current coming
out of it is “negative”. So a 180° relative phase shift simply means that when 159 mA is coming out of the
inductor, exactly at that moment, 565 mA is going into the capacitor. We can confirm this from Figure 3.

The preceding logic also leads us to the following thought process: Could we have “X” mA coming out of the
inductor and exactly “X” mA going into the capacitor at the same moment? Yes, by varying the frequency we
can always do that --- because in one case (inductor) the impedance increases with frequency whereas in the
other case (capacitor) it decreases with frequency. So certainly, we can get the two values to converge at some
“intersection” point, at which point their impedances would be equal in magnitude (opposite in sign, though).
See Figure 4. That intersection then forms a “natural (or resonant) frequency” for the chosen L and C. The only
question is: at what frequency? That is just the point at which the inductor’s impedance 2πf×L, equals the
capacitor’s impedance 1/(2πf ×C). Equating the two, we solve to get the well-known equation for “resonant
frequency”: fRES = 1/{2π×√(LC)}. We will describe resonance more clearly now, based on the above observations.
We could connect the two components (L and C) in parallel across each other, inject some energy into the
“tank”, say by tuning the applied AC source to the natural frequency of the two. Thereafter, theoretically
speaking, once injected into this tank, energy could just slosh back and forth forever between the L and the C. It
would be self-sustaining. See Figure 4. See also Figure 5 for a more detailed explanation of the phenomenon.

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Frequency =300Hz (for both cases)

CAPACITOR ONLY INDUCTOR ONLY

Cap Cap Cap Ind Ind Ind

Input Input Output Input Input Output
Voltage Current Voltage Voltage Current Voltage
Probe Probe Probe Probe Probe Probe
Cap Ind
Sine 10µF Sine 100mH
wave, wave,
± 30V, ESR ± 30V, DCR
300Hz 100mΩ 300Hz 100mΩ

30V Cap
CAPACITOR CASE

Input
Voltage

30V Cap
Output
Voltage
Current
leads
565mA Cap
Input
Current

30V
Ind
INDUCTOR CASE

Input
Voltage
MOMENT OF
OPPOSITE
CURRENTS 30V
Ind
If we equalize Output
Current these, we can Voltage
lags create “resonance”
159mA
Ind
Input
Current

Figure 3: Response of a 100mH inductor and a 10µF capacitor to identical 30V/300Hz AC sources

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Linear scales 3
Log scales
110

ZC
100 Ω
Impedance (Ω)

200 100
ZC

Zl( f ) ZL Zl( f )
Zc( f ) Zc( f ) ZL
100 10

~159 Hz
 freq  1/ freq

0 1
0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 3
10 100 110
f
Frequency (Hz) f
Frequency (Hz)

At 159 Hz, the impedances are the

same (100 Ω), leading to equal and
opposite currents (180° out of phase
100 mH with respect to each other), so energy
10 µF
just sloshes back and forth
indefinitely. Also no current is drawn
from input source (not required), so
Parallel
the source sees in effect, a very high
LC Tank impedance across it.

Impedance of the LC at resonance is not 100 ‖ 100 = 50Ω. It is infinite!

Figure 4: Explaining the energy storage capabilities of the parallel resonance tank circuit when driven at its resonant (natural)
frequency

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PARALLEL LC AT RESONANCE

CYCLIC PROCESS (one intermediate state) CYCLIC PROCESS (another intermediate state)

+ I + +
I
+
+ “V” Voltage
“I” Current Magnetic “V” Voltage “I” Current Magnetic
+ ++ (capacitor
(inductor
field (capacitor (inductor field
++ +++ energy)
fres energy)
+ Electrostatic energy) fres energy)
+ Electrostatic
max but
max but
field min but min but field
-- increasing increasing --- decreasing
decreasing
- --
dI/dt = V/L dV/dt = I/C dI/dt = V/L - dV/dt = I/C

Small DCR Small ESR Small DCR Small ESR

(dissipation) (dissipation) (dissipation) (dissipation)

I I I I
+ + + +

By physically paralleling the two components, L and C both are forced to have the same magnitude of voltage
across them at any instant. At resonance, both have the same impedance too. So their currents, though equal,
have a 180° relative phase shift --- i.e., the instantaneous current out of either one, almost exactly equals the current
into the other (difference is due to non-idealities). So, during “resonance”, energy (current) sloshes back and forth
between inductor and capacitor as shown above. When current is peaking (i.e., inductor energy is max), its rate of
rise (i.e. voltage, and therefore cap stored energy) is very small. When the voltage is peaking (i.e., max cap energy
), its rate of rise (i.e., current, and therefore inductor stored energy ) is very small. That leads to the back-and-
forth energy sloshing. Huge out-of-phase currents can be generated in the L and the C separately, but they
almost cancel out, so the voltage source does not “see” those huge currents.

This sloshing can go on forever, were it not for real-world parasitic resistances such as ESR and DCR. So, a small
amount of energy is constantly dissipated during the sloshing, and the same gets pulled in from the voltage source
to compensate for this loss and to maintain a steady state (provided that a voltage source is present, because
otherwise the LC oscillations will decay exponentially). But being a parallel circuit, the voltage across the L and
the C equals that of the voltage source, with a relatively small current (from the voltage source) passing through
the LC combination . Since this small input current is only drawn for compensating a small purely resistive loss,
the input current is in phase with the input voltage at resonance. To the input voltage source, the parallel-LCR
network appears as a simple resistance (of a typically large value, producing very small input currents), at the
resonant frequency.

Since the current drawn from the voltage source is very small, we can say that the parallel LC circuit offers a
very high net impedance at resonance.

A small (large) resistance in series with the L for example, can be treated as a high (low) resistance across an ideal
L. Though the transformation (equivalent parallel resistance) is frequency dependent. Similarly, a small (large)
resistance in series with the C for example, can also be treated as a high (low) resistance across an ideal C. Though
the transformation (equivalent parallel resistance) is frequency dependent again.

Figure 5: Explaining the energy storage of the parallel LC in more detail

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Note that once the LC “tank” has been excited and “set in motion”, we could even remove the AC source
completely, and the oscillations would continue indefinitely (ideally). But note that if we had continued to keep
the AC source connected to this tank circuit, it would make no difference at all really (unless of course the AC
source tried to drive the tank circuit at some frequency other than its natural frequency). At the resonant
(natural) frequency, provided the LC circuit has reached the voltage level of the AC source, the AC source does
not need to replenish the energy in the tank (assuming no parasitic series resistances present). In other words,
the AC source will thereafter provide no current at all, even if connected --- simply because it does not need to.
But we also know from our usual electrical definitions, that if the current drawn from the input source is zero,
then the impedance (of the LC tank connected across the source), i.e., as seen by the source, is infinite (just like
an open circuit, though only true at that specific frequency).

Above we have created our first resonant circuit: a pure “LC” parallel circuit (with no parasitic resistances). It is
our first building block. We have intuitively also just learned that this pure parallel LC tank circuit has an infinite
impedance at its resonant frequency “fRES”.

As mentioned, we have the result: fRES = 1/{2π×√(LC)}.

It is interesting to point out that at resonance, the overall impedance of the tank circuit is not half the
impedance of each equal limb as we expect in the case of paralleled resistors. That is because of the
complementary phase angles between voltage and current in the paralleled components, that the net
impedance becomes infinite in magnitude, at the resonant frequency.

In reality, any small resistances in series with the C and the L (such as ESR and DCR), will cause the oscillations to
decay exponentially. And in that case, to “replenish” the tank, the AC source will need to provide a small
amount of current, even at resonance. Which implies that though the impedance is still very high, it is not
“infinite” anymore, not even at the resonant frequency.

We have simulated an (almost unloaded) parallel LC circuit --- with a 30V AC source set exactly to the natural
(computed) frequency of 159.155 Hz for the selected components (10μF and 100mH). The results are presented
in Figure 6. Compare that with Figure 3 where we still had “unmarried” and separate components. If we had
not loaded the circuit a bit, the Simplis simulator would have complained due to infinite numbers.

The impedance of the parallel LC falls off on either side of the resonant frequency, irrespective of parasitics
being present or not. At very low frequencies, we can assume the inductor is just a short (piece of wire), and so
the AC source too will see a short (zero impedance), whereas at very high frequencies, the capacitor becomes a
short (high frequency bypass), so again, the AC source will see almost zero impedance.

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We sum this up by saying that to the left of the resonant frequency of a parallel LC circuit, the LC network
appears “inductive” (current lagging the voltage, but not necessarily by a full 90°). Whereas to the right of the
resonant peak, the network appears “capacitive” (voltage lagging the current, but not necessarily by a full 90°).
Since we have learned in the previous sections that a resonant network or circuit should appear “inductive” to
the source, to be able to create ZVS, we realize that the parallel LC circuit is useful to us only provided we
operate to the left of its resonant peak.

Any small resistances in series with the L and C (their typical parasitics like ESR and DCR) can be transformed, or
modeled, into an equivalent large resistance placed in parallel to the paralleled (pure) L and C. In any proposed
resonant converter based on this type of tank circuit, the load too will be connected in parallel to the paralleled
L and C. So the effect of all resistances is to cause a eventual decay of the stored energy if the AC source is
suddenly disconnected. If the AC source continues to be connected, it now has to constantly provide current
and energy into the system to keep it “topped up” --- in the form of a) useful energy delivered to the load, and
b) wasted energy dissipated in the series parasitics (or the equivalent parallel resistance).

Note: The “series to parallel equivalent transformation” indicated above, in effect, makes the parallel resistance a function of the AC
frequency. For any given frequency we have to recalculate it.

Finally, keep in mind that though the AC source may be providing only a tiny current at resonance, the current
sloshing back and forth in the parallel LC can be very high. It is limited only by the impedances of the individual L
and C, as we can see from Figure 6. The AC source may never “know” about these high currents since it is only
delivering a very small current, but in a practical converter, where we would have transistors in the path of the
circulating current, we are in danger of damaging our PRC (parallel resonant converter based on this building
block tank circuit). That is one limitation. Another limitation of this very basic PRC is that there is no obvious way
to regulate the output! The load is connected in parallel to the input source, so it has exactly the same voltage
as the incoming rail. What use is that if we can’t offer load and line regulation? Yes, we can add other L and C’s
to try to get this to work, but at this point we prefer to move on to another, more promising resonant converter
variation, which was in fact quite popular in older resonant converters: the SRC (series resonant converter). It is
based on the series resonant LC cell, discussed next.

Note: We can prove that the real-world actually depends on their being “parasitics” present almost everywhere. Very strange things
would happen in our “real-world” if there were no resistive parasitics present in particular. It turns out, it is also a very good idea to
include small resistive parasitics during simulation, just as we have done in Figure 6. To avoid mysterious simulation stalls, we should
also try putting in initial conditions for the L and C, for the voltage across the cap or the initial current through the inductor.

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PARALLEL LC AT RESONANT FREQUENCY (159.2Hz)

Frequency =159.155Hz

Ind Cap
Parallel Input Input
LC Current Current
Parallel- Input Probe Probe
LC Current
Input Probe
Voltage
Probe Ind Cap
100mH 10µF

Sine
wave, DCR ESR
± 30V, 100mΩ 100mΩ
159.155
Hz

LC
VIN, IIN ARE Input
IN PHASE
(RESISTIVE) Voltage

2 x 0.6µA
LC
Input
Current

300mA Cap
CAP AND IND Input
CURRENTS
ARE OUT OF Current
PHASE AND
HAVE SAME Ind
300mA
MAGNITUDE
Input
(CANCEL)
Current

Figure 6: The (almost unloaded) parallel LC at resonance, showing the high circulating currents in L and C
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PART 2: Building Resonant Tank Circuits for Future Converters

After having completed the initial transition from “PWM-thinking” to a better understanding of resonant
behavior, we now start putting the LC components together to create some “trial balloons” first. Eventually we
will then understand the best direction to take for practical converters.

Series Resonant Tank Circuit

This formed the basis of several commercial resonant converters. Let us get familiar with its pros and cons.
In Figure 7, we have simulated the series resonant tank, driven at its resonant frequency, almost fully unloaded
(i.e. small parasitic resistances too). We see very high currents at resonance, clearly limited only by the
parasitics. Then using V=I×Z, because of the very high currents, we also get very high voltages across the L and
C. However, these high voltages are out of phase, and almost fully cancel out from the viewpoint of the input
source. So we are just left with 30V (AC amplitude) to satisfy Kirchhoff’s voltage law. The AC source does not
“see” the high voltages, but does see the very high currents because they pass through it.

In a practical converter based on this series LC principle, we would typically connect the load across the L. Now
we can use a “parallel to series equivalent (frequency dependent) transformation” and visualize this parallel
load resistor as appearing in series with the L and C, just like the resistive parasitics (ESR and DCR) do. Or we
could, in fact, really place the load in series with the L and C as shown in Figure 8. Whatever way, the load helps
significantly reduce the high voltages and currents of the series LC (in any proposed SRC, i.e., series resonant
converter). This is called “damping”. It does make the series LC tank a possible practical choice, provided we do
not try to run it with no load across L--- because damping would be lost in that case, and we could easily damage
it due to the high peaking at resonance of the series LC . That is one limitation of the SRC (based on this tank
circuit).

Can we at least use the SRC to provide a regulated output rail, something we couldn’t do easily with a proposed
PRC? As shown in Figure 8, we in fact use the basic voltage divider principle we use in setting the output voltage
of a typical conventional PWM regulator, to produce a voltage rail (always) lower than the input. Nom we have
to vary the impedance of the LC appropriately to produce whatever output we want. In other words, in a series
resonant circuit (in general many types of resonant circuits), we need to vary the “switching” (driving)
frequency to create output regulation, just as in a conventional converter we need to vary the pulse width to
create regulation.

Can we ensure ZVS in a series LC based converter? For that we need the tank circuit to appear inductive to the
AC source as explained. So, without bothering to plot it out so far here, we can intuitively visualize that at low
frequencies, the inductance of the series LC would appear as a piece of wire in series with a cap, so the AC
source would only see a capacitance at low frequencies. At very high frequencies, the cap would appear shorted

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to an AC signal, so the tank would now appear inductive. We conclude that in a practical SRC, we would need to
operate to the right of the resonant frequency for achieving ZVS.

One famous “last-but-not-the-least” type of question remains: if the output falls, do we need to increase the
frequency or decrease it? To figure that out, in Figure 9, we plot out the gain of the series LC (we call gain as
“conversion ratio” at various places, but it happens to be just the output divided by the input). We see that in
the “ZVS-valid” region to the right of the resonant peak, we need to reduce the frequency as load increases (to
get the gain to increase). Conversely, at light loads, we have to significantly increase the frequency to regulate.
For the case of R = 100 Ω, we see we need to go from 300 Hz to 170 Hz to regulate the output (keeping the same
conversion ratio, since input/line has not changed here). For R = 1000 Ω, we are already in big trouble:
theoretically, we have an almost infinite switching frequency spread in an SRC, just to regulate to a set level (at ~
zero load). We also know that at very light loads, the voltages and currents can be extremely high in a series LC
tank, which not only can damage the switches of an SRC, but result in very poor efficiency at light loads. These
are all the major limitations of the series-LC and its practical form, the SRC.

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SERIES LC AT RESONANT FREQUENCY (159.2Hz)

Frequency =159.155Hz

Series LC Cap
Input 10µF
ESR
Current 100mΩ
Probe
Ind
Cap 100mH
Series-LC
Voltage
Input
Probe
Voltage
Probe
Ind
Voltage
Sine Probe
wave,
± 30V, DCR
159.155 100mΩ
Hz

2 x 15kV
CAP AND IND Ind
VOLTAGES Voltage
ARE OUT OF
PHASE AND
HAVE SAME
2 x 15kV MAGNITUDE Cap
(CANCEL) Voltage

30V LC
VIN, IIN ARE Input
IN PHASE Voltage
(RESISTIVE)
LC
150A
Input
Current

Figure 7: The
(almost unloaded) series LC at resonance, showing the high voltages across L and C

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1
ZTOTAL  R  jL 
IIN jC
VIN
I IN  VO
ZTOTAL

Rev. 0.1, March 2013

NOTE :
VIN 1
VO I IN  R VIN R R2
jC   
VIN VIN ZTOTAL VIN
So,
100mH VREF R1
VO R 
jL 
VIN ZTOTAL VIN R1  R 2 VREF
(voltage divider action using impedances)
Similar to voltage divider equation
R=? used in conventional power supplies R1
LOAD VO=?

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Figure 8: Using the series resonant circuit to create a regulated voltage in principle

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SRC with C=10µF, L=100mH

Example of line regulation locus in regulated series resonant circuit
10

A
1
B R=1000
0.6
VR( f  Vtest1  Rtest1 )
0.2
Conversion Ratio

Vtest1 R=100
0.1
VR( f  Vtest1  Rtest2 )
Vtest1
R=10
VR( f  Vtest2  Rtest3 ) 0.01

Vtest2 300
VR( f  Vtest3  Rtest4 ) 3 For a give load, starting at operating R=1
110

600
Vtest3 point “A”: input increased by a factor of
3. To maintain regulation, down
4
110 conversion ratio must decrease by same
factor, taking it to point B. So, frequency
5
must change from 300Hz to 600Hz.
110
3
10 100 110

Frequency
f
(Hz)
A) At light loads, line regulation will cause a huge swing in frequency (e.g. R = 1000 Ω curve above).
B) Line regulation can also be achieved to the left of the resonant frequency, but the circuit will
appear capacitive (see phase plot), and so, ZVS will be lost.

Example of load regulation locus in regulated series resonant circuit

B A
1 R=1000
0.6
VR( f  Vtest1  Rtest1 )
Conversion Ratio

0.2
Vtest1 R=100
0.1
VR( f  Vtest1  Rtest2 )
Vtest1
R=10
VR( f  Vtest2  Rtest3 ) 0.01

Vtest2
300
170

VR( f  Vtest3  Rtest4 ) 3 For a give input (keeping a fixed R=1

110
Vtest3 output to input ratio), starting at
operating point “A”: if load increases
4
110 from 100 Ω to 10 Ω, the frequency
must be reduced to 170 Hz to
5
maintain ratio, taking it to point B.
110
3
10 100 110

Frequency (Hz)
f

A) Large down conversion ratios in design will lead to wider frequency shifts for load regulation

If operating to the right side of the resonant peak, in both cases above we see that if output
tends to rise, we need to increase frequency, and if output falls, we need to reduce frequency
Figure 9: The series resonant LC tank, showing gain (conversion ratios), and how line and load regulation can possibly be carried out in
a practical SRC (series resonant converter)

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Introducing the LLC Tank for creating future LLC converters

Here all we do is to take the series LLC tank and add a relatively large inductor in parallel to the load, as shown
in Figure 10. So, now we have two inductors and one capacitor. We call this “LLC” for L-L-C (two inductors, one
capacitor).

Historically, the LLC was not really an unknown topology. But its full significance was not clearly understood till
just a few years ago when engineers started looking rather keenly once again at resonant topologies in an effort
to reduce switching losses.

Note: It is paradoxical though that the design of LLC converters is still so poorly understood that even though LLC converters are based
on a principle that should help achieve very high efficiencies at very high frequencies, (where the last stumbling block was always the
“switching loss” term), yet, most commercial LLC converters are still operating only in the range of 80kHz to 200kHz. Technology will
certainly improve with a better understanding. There have been 1 MHz LLC prototypes already reported.

We need to understand very clearly how to properly and optimally design an LLC converter --- based on physical
principles and deeper understanding, rather than just relying on “trial and error” in a real lab, or on simulations
in a virtual lab. It is tricky. As even Bob Mammano admitted: it can be “bewildering”. We hope to overcome
some, if not all, the mystique behind the LLC converter through these pages.
We expect two resonances, because we have one C, which can “resonate” with not one, but two inductors.
Note that two L’s cannot “resonate” with each other, because we need complementary phase angles to
resonate! We have to see how this additional L modifies the series LC circuit, and if it helps overcome some of
the previously discussed limitations of the SRC.

In Figure 10, we show how the voltage divider principle can be made to work here too, this time similar to the case of a
three-resistor voltage divider which i principle, can be used for setting the output in any conventional PWM converter.
Then, in Figure 11, we have used Mathcad to plot the equation introduced in Figure 10. But before we get to fully
discussing Figure 11 (the gain), let us first analyze the phase relationships accruing from the basic equation in Figure 10 ,
so we can be sure to identify the region of operation in which the circuit appears “inductive” and is therefore conducive to
establishing ZVS. We have to admit, we cannot analyze all this very intuitively anymore, and need to plot it out
mathematically as shown in Figure 12. Note that as for the series LC circuit, we have chosen L1 to be 100mH, and C is still
10μF. The newly introduced inductance is L2, and we have used a seemingly arbitrary value of 900mH (a factor of 9 higher
as compared to L1). Actually, that factor is optimally set. If the ratio is larger, the frequency variations are more, and if it is
made too small (similar to L1), the currents cam be much higher and the efficiency much lower.

In the next section, we start by analyzing Figure 12 and then Figure 11 again, going back and forth to draw pointers
towards designing a practical LLC switching converter. Note that for now, we are only discussing how the LLC tank circuit
behaves, and that too only under a sine wave stimulus (AC source). Later we will build a practical switching converter out
of it in several steps.

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R  jL 2  1
ZTOTAL   jL1 
R  jL 2  jC
IIN
VIN jL 2  VIN jL 2 
I IN  . Splits into resistor as: I IN _ R  I IN    VO

Rev. 0.1, March 2013

VO  I IN _ R  R 
1 jL 2   R
VIN
jC NOTE : R2
L1 VO I IN _ R  R jL 2  VIN R jL 2 
     . So,
100mH VIN VIN jL 2   R ZTOTAL VIN jL 2   R
VO 1 R  jL 2  VREF R1
jL1    VREF
VIN ZTOTAL jL 2   R VIN R1  R 2
(voltage divider action using impedances) where
R1A  R1B
R1 
R=? R1A  R1B R1A R1B
VO=?
LOAD Similar to voltage divider equation
L2 used in conventional power supplies
900mH
jL 2 

Assume L2 is about 7 times L1

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Figure 10: Using the LLC resonant circuit to create a regulated voltage in principle

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LLC with C=10µF, L1=100mH, L2=900mH

Example of line regulation locus in regulated LLC resonant circuit
Frequency must be
100
50.3Hz
VR ( f  Vtest1  Rtest1 )
Vtest1
adjusted down if
VR ( f  Vtest1  Rtest2 )
10 input falls
B A 159.2Hz
Conversion Ratio

Vtest1
Low line R=10k
VR ( f  Vtest2  Rtest3 )
High line 1 R=1k
Vtest2 R=500
VR ( f  Vtest3  Rtest4 ) R=200
Vtest3 R=100
0.1
VR ( f  Vtest3  Rtest5 )
Vtest3
R=10
VR ( f  Vtest3  Rtest6 ) 0.01
Vtest3

VR ( f  Vtest3  Rtest7 ) R=1

3
Vtest3 1 10

4
1 10
10 Rtest2  1 100 1 10
3

Frequency (Hz)
f fRES_1 = 159.2 Hz
fRES_2 = 50.3 Hz
Example of
100
load regulation locus in regulated LLC resonant circuit
Frequency must be
VR ( f  Vtest1  Rtest1 )
Vtest1 adjusted down if
VR ( f  Vtest1  Rtest2 )
10
load increases
B A
Conversion Ratio

Vtest1
R=10k
VR ( f  Vtest2  Rtest3 )
1 R=1k
Vtest2 R=500
VR ( f  Vtest3  Rtest4 ) R=200
Vtest3 R=100
0.1
VR ( f  Vtest3  Rtest5 )
Vtest3
R=10
VR ( f  Vtest3  Rtest6 ) 0.01
Vtest3

VR ( f  Vtest3  Rtest7 ) R=1

3
Vtest3 1 10

4
1 10
10 Rtest2  1 100 1 10
3

Frequency (Hz)
f

Increasing the load or reducing the input, both tend to cause the output to fall, and thus the regulation loop will
need to try and correct this by increasing the conversion ratio (Output/Input). A) If the system is operated
between the two resonant frequencies at all loads, we can set that the logic that the control loop will always
simply decrease the switching frequency in response to a falling output. B) We can also restrict ourselves
completely to the right side of the right-hand resonant peak at all loads. But that has all the disadvantages of
conventional series resonant circuits (e.g., huge, uncontrolled swing in frequency at light loads). C) We can also
decide to restrict ourselves completely to the left side of the left-hand resonant peak, and set the logic such
that the control loop will always simply increase the switching frequency in response to a falling output.
That too will work in terms of regulation too, but it will not be ZVS. D) But we can never set an easy control
algorithm if we allow operation across either resonant peak, since conversion ratio slope changes on either side.
Figure 11: The gain (conversion ratio) of the LLC resonant circuit for different loads

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Understanding and using LLC

Converters to Great Advantage

Series LC with C=10µF, L=100mH,

Input 10µF SERIES RESONANT INPUT IMPEDANCE
For 10µF, 100mH
100mH
100
Output
LOAD
“Inductive”

180
arg( Z ( f Rtest1) )  50

Phase Angle of Impedance

180
arg( Z ( f Rtest2) ) 

0 R=1k
(degrees)

180
arg( Z ( f Rtest3) ) 

“Capacitive”

180
0

arg( Z ( f Rtest4) ) 
10


SET MAX
R=

 50
LOAD AT MIN
R= 10

INPUT HERE
R=
1

 100
10 100 fRES 110
3

Frequency
f (Hz)
LLC with C=10µF, L1=100mH, L2=900mH
Input 10µF LLC RESONANT INPUT IMPEDANCE
BEST REGION OF
OPERATION For 10µF, 100mH, 900mH
100mH
Output
100
R=1
argLOAD
( Z ( f  Rtest1 ) ) 
180 R=10k
900m
0
1

0
R=

0
10 = 20
“Inductive”

180
arg ( Z ( f  Rtest2 ) ) 
0
 50
R= R R=50
180
Phase Angle of Impedance

arg ( Z ( f  Rtest3 ) ) 
 R=1k
180
arg ( Z ( f  Rtest4 ) ) 

(degrees)

0
0
180
20
R=
arg ( Z ( f  Rtest5 ) ) 
“Capacitive”


SET MAX
00

180 LOAD AT MAX

arg ( Z ( f  Rtest6 ) ) 
R=


 50 INPUT HERE
180
arg ( Z ( f  Rtest7 ) ) 
R= 10


R=
1

 100
3
1  10
10
fRES_2 100
fRES_1
f
Frequency (Hz)
1 1 1 1
f RES  f RES_1    159.2Hz;fRES_ 2    50.3Hz
2 LC 2 100mH 10F 2  L1  L2  C 2 (100  900)mH 10F

Figure 12: The phase of the LLC resonant circuit for different loads, compared to the series LC

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Understanding and using LLC

Converters to Great Advantage

Analyzing the Gain- Phase Relationships of the LLC Tank Circuit

Looking at Figure 12, we see that in a series resonant LC, for any load, we always had to be to the right of the
resonant peak (~159 Hz), for the phase to be greater than 0° (“inductive”, i.e. for current to lag the voltage as
desired). That would mean ZVS was possible only for >159Hz (potentially up to very high frequencies). In the LLC
tank, we get a “low-frequency phase boost” arising from the lower resonant peak, which in turn is related to L 2,
and this makes a wide range of load resistances with ZVS possible even at lower frequencies. In fact when we do
the full math, we see that we get two resonant peaks, one formed by C and L 1 (as for series resonant tank), and
another one formed by C and (L1+L2). Hence we have the resonant frequencies designated “fRES_1” and “fRES_2”
shown at the bottom of Figure 12. Numerically, for the values chosen, the second peak appears very close to
50Hz. So, we can typically operate to the right of 50 Hz and up to 159 Hz for all loads ranging from open-circuit
to R = 200 Ω (it seems so far), and achieve ZVS. For loads greater than that (say R < 200 Ω), we have to operate
above 159 Hz, otherwise we cannot get ZVS because the phase angle is negative (“capacitive”).

You might say: “So what” (if we can operate down to lower frequencies for a range of loads)? That by itself
doesn’t seem to matter! In fact we usually want to operate at high frequencies anyway, and want to try and
ensure ZVS at high loads primarily. So what is the advantage of the LLC? The real advantage of the second peak
in the LLC tank shows up only in Figure 11 (in the gain plots). In this figure, we have plotted out the gain, which
we often call “conversion ratio” (i.e., output voltage of the LLC stage, divided by input voltage, where output is
just the voltage across the inductor in our simple AC case so far), versus frequency (for different loads).

For very high loads (e.g. R = 1), we get a conversion ratio always less than 1. That is just like a series resonant LC
in which we only get step-down ratios. If we decide to operate in that region with our LLC tank, we can do that.
But there is a major stumbling block: For very light loads (such as 1k or 5k, as shown in Figure 11), we cannot
even get much less than gain = 1, unless we move to infinite frequencies. We could have a case where we can’t
even regulate anymore over the full load range. Or worse, maybe we deigned our entire converter to step
down, but at light loads the control loop moves in the “wrong direction” --- and ends up on stepping up
(perhaps because the shape of the curve, in particular its slope, flipped signs as we moved from one side of the
resonant peak, to the other side side. Yes, maybe we can “preload” the converter (at a huge expense to light-
load efficiency), so our tank circuit never sees very light loads. In fact, we always need to do that in the SRC just
to avoid the huge frequency variation we mentioned previously, but we could end up in the same situation with
LLC too, if we are not careful in designing our region of operation, and our control strategy.

Therefore looking at things very practically, we decide we should not try and operate an LLC based converter to
the right of the higher-frequency resonant peak (159 Hz in our case).

Let us keep in mind that designing our system to be “step-up” or “step-down” is actually our initial design
decision, whatever the relationship of the input and output voltage levels. Because eventually, we will use a
transformer with an appropriate turns ratio to correct for that. For example, we could design our LLC for a 1:1.1

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Understanding and using LLC

Converters to Great Advantage

ratio (an output 10% higher than the input), and then use a transformer with a Primary to Secondary turns ratio,
of say 2:1, to bring the output down to about half the input voltage. That is very similar to what we do, or can
do, with the conventional Flyback topology too. For example, in a typical universal-input off-line (AC to DC)
Flyback power supply, we create an “invisible” intermediate Primary-side regulated rail of about 100V. This is for
all practical purposes, the output rail as “seen” by the Primary side, and it regulates (and sets duty cycle) to keep
this level fixed at 100V. But after that, a 20:1 transformer ratio is inserted via the transformer, to produce 5V
from the 100V intermediate rail. Likewise, in transformer-based resonant topologies too, we have an additional
degree of design freedom coming to us from the turns ratio, and we can voluntarily pick whether we want to
operate the Primary side to act as a step-up, or step-down stage. As a corollary, since we will use a transformer
anyway (also for creating the magnetic elements of the LLC), isolation is a natural advantage that accrues from
an LLC converter (whether we like it/need it, or not).

We have decided not to operate to the right of 159 Hz in Figure 12. What about to the left of the second (lower-
frequency) peak: i.e. below 50Hz? Unfortunately, looking at the phase diagrams in Figure 12, we realize that the
phase is below 0° in that region, and therefore the network will capacitive to the input source. We know that is
not going to lead us to ZVS operation. In other words, finally we are left only with the region between 50Hz and
159Hz to operate over the entire line and load variation. We have no other practical and unambiguous choice
really, given the guiding criteria discussed previously and the shape of the gain curves. But one question
remains: does this (available) region (fully) meet all our needs? Do we need to look more closely?

Let us look again at Figure 11 and see how we intend to implement line and load regulation. We can see that,
depending on the load, we can get either step-up or step-down (i.e., conversion ratio greater or less than unity).
Most of the curves are in fact with a step-up ratio. We can actually close-up in this vital region, as we do in
Figure 13, and we realize that the curve of R = 200 Ω, which on the basis of its positive (inductive) phase had
been previously deemed “ZVS-capable” and therefore acceptable, won’t work for an entirely different reason.
That is related to one of the two guiding criteria we talked about earlier: do we have a “simple way to
implement an unambiguous, almost “knee-jerk” (rapid) response to disturbances, analogous to what we do in
conventional power conversion?”. For the 200 Ω curve we are failing this requirement for line regulation. We
can see from Figure 13 that the 200 Ω curve slopes downwards as frequency decreases from fRES_1 to fRES_2 (159
Hz to 50 Hz). This is opposite to all other neighboring curves here. In all the other cases, based on Figure 11 we
have obviously designed the converter in such a way that if input falls, we lower the frequency (in knee-jerk
fashion), to correct for that. But for the 200 Ω case (as per the closeup in Figure 13), decreasing the frequency
will cause the conversion ratio to fall even more, so the output will collapse. This is not in the “right direction”
for correction, commensurate with neighboring trends and our control strategy.

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Understanding and using LLC

Converters to Great Advantage

We therefore conclude that:

Resistive loads less than 200 Ω are definitely considered “overloads” (based on the LLC tank circuit values
chosen so far). Output foldback will occur in this case. These values cannot be supported, even though the
phase seemed right.

This “dropping off” of gain is coincidentally almost commensurate with the phase just going negative (below
zero degrees), as indicated in Figure 13. While plotting these curves, the spreadsheet was set to “test the gain
versus the phase condition”, and “appear dotted” if the phase was reported to be negative. In general we can
safely conclude that whenever the gain starts “heading down”, the phase simultaneously is close to dropping
below the zero degree line (it becomes negative, and thus capacitive). Therefore, for two reasons, not one, the
dotted part of the curves in Figure 13 is considered “no man’s land” from now on. If the system enters that
region, it won’t be destroyed, but its efficiency will suddenly worsen (no ZVS), and also, any attempt at output
correction, will most likely cause output foldback. On this basis, we rule out 200 Ω --- we can see from Figure 13
that it just doesn’t go far enough into the lower frequency region (starting from f RES_1), before it turns “dotted”.
We also conclude that the max usable load for any LLC converter, based on the LLC tank circuit values we picked
in this example, is 250 Ω, but also, adding some design margin, we fix preferably 300 Ω. Higher loads than that
(i.e. smaller load resistance values), are “overloads” by definition.

At very light loads, the frequency will shift close to 159Hz, not more (certainly unlike an SRC which tries to go to
infinite frequencies to regulate at light loads).

At very heavy loads, the frequency will shift closer to 50Hz.

We can easily sense, based on the equations for f RES_1 and fRES_2, that increasing L2 significantly will move fRES_2
towards much lower frequencies. Though that may help in some way, it is clear that there is a penalty for
making L2 much larger than L1. For one, the frequency variation spread, going from min load to max load, and
from low line to high line, will become much larger.

We have decided we need to design for conversion ratios higher than unity so we can cover the full load range
from 250 Ω (peak load) to higher values (unloaded). In particular, to ensure ZVS, we will set the LLC converter at
peak load, at high line, to be at the encircled point at the lower right tip of the shaded area in the LLC phase
diagram of Figure 12. At that particular design entry point (shown more clearly and precisely with an
ellipse/circle in Figure 13), we will have a frequency closer to the higher resonant peak (~ 125 Hz in our case
here), and a corresponding gain (conversion ratio) of about 1.05. This gain target of 1.05 at max load and high
line is actually our universal recommended entry point for all LLC converters designs, because otherwise the
gain curve “droops”, and the correction loop will take it in the “wrong direction” (foldback) as discussed

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Converters to Great Advantage

previously. If we set it closer to 1, say at 1.02, our design entry point will shift closer to the higher-frequency
resonant peak. But that is too marginal.

The full optimum region of operation is also shown (shaded) in the gain curves of Figure 13. This area is the part
of the gain curve for which phase angle is positive (inductive). As indicated, we have “AND-ed” the gain and
phase curves using Mathcad, so the curves become dotted if unacceptable. As also indicated, this does not
mean the system will necessarily stay in this optimum region, or we are somehow constraining it too. That locus
of movement is determined solely by the regulation loop, as it relates to the specific line or load variations. So
certainly, our selected design entry point must lie within this shaded region (at the circle/ellipse), so that we get
ZVS at max load and at high line, but we may just lose the advantage of ZVS if we leave this shaded area. For
example, if we set the max load as 300 Ω, we will be able to reach a conversion ratio of about 1.18, as per Figure
13, before we leave the ZVS region. That seems to equate to an allowed 18% reduction in input (but we will
soon show it is only 12% actually). Either way, we can produce derating curves to show how we can tradeoff
max load versus input operating range, weighing it against the price of overall expected efficiency, provided of
course the range can be achieved or is acceptable in terms of our guiding criteria.

The fear of predicting and/or really losing efficiency at low line is perhaps one reason LLC converters are still
largely being used only where the input is relatively stable (and comfortably so), such as where the LLC
converter is driven off the output HVDC rail of a front-end PFC stage. We can see that if we really want wide-
input variation, we have to overdesign the converter (300 Ω in our example, will only get us 12% input voltage
variation factor as explained later). Holdup time can also be a major issue in AC-DC designs in which the LLC
converter stage typically follows a conventional PFC stage.

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Understanding and using LLC

Converters to Great Advantage

LLC with C=10µF, L1=100mH, L2=900mH

100
R=1M
180
arg( Z ( f Rtest1) ) 
 R=200
Phase Angle of Impedance

R=300
180 R=400
arg( Z ( f Rtest2) ) 
 50 QUALIFIES AS R=500
R=600
180
POTENTIALLY R=800
arg( Z ( f Rtest3) )  GOOD REGION

(degrees)

OF OPERATION:
arg( Z ( f Rtest4) ) 
180 A) Frequency vs.
 QUALIFIES AS BEST
0 Conversion
DESIGN ENTRY POINT:
180 Ratio trend
arg( Z ( f Rtest5) )  Should be set here at
 seems OK
MAX load (300 Ω) and at
B) Inductive
180 MAX Input of desired range
arg( Z ( f Rtest6) )  Impedance will

 50 enable ZVS
180
arg( Z ( f Rtest7) ) 

fRES_1 = 159.2 Hz
fRES_2 = 50.3 Hz
 100
3
10 100 110
f
fRES_2 fRES_1
R=600
R=800
R=1M

QUALIFIES AS BEST
2 REGION OF
2
OPERATION:
VR( f( 
VRm Vtes t1
f Vtest1 Rtes t1
Rtest1 )) A) Frequency vs.
Vtes t1
Vtest1
~1.8 Conversion Ratio
VR( f( 
VRm Vtes t1
f Vtest1 RtesR=500
Rtest2t2
))
trend is quite OK
Vtes t1
B) This is ALSO the
Vtest1
region with
Conversion Ratio

VR( f( 
VRm Vtes t2
f Vtest2 Rtes t3
Rtest3 )) inductive
1.51.5
Vtes t2
Vtest2 impedance (AND-ed
R=400
VR( f( 
VRm Vtes t3
f Vtest3 Rtes t4
Rtest4 )) logically with above
phase curve) and
Vtes t3
Vtest3
~1.2
VR( f( 
VRm Vtes t3
f Vtest3 Rtes t5
Rtest5 ))
will thus enable ZVS
Vtes t3
Vtest3 R=300
VR( f( 
VRm Vtes t3
f Vtest3 Rtes t6
Rtest6 ) )1 1
Vtes t3
Vtest3
R=200
VR( f( 
VRm Vtes t3
f Vtest3 Rtes t7
Rtest7 ))
Vtes t3
Vtest3
QUALIFIES AS BEST DESIGN ENTRY
POINT: Should be set here at MAX load
(~250 Ω) and at MAX Input of desired range
0.5
50 60 70 80 90 100 110 120 130 140 150
f
fRES_2 Frequency (Hz) fRES_1
Figure 13: Closeup of phase for different loads, and corresponding conversion ratio (gain) in the usable area of the LLC tank circuit
between the two resonant frequencies

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Understanding and using LLC

Converters to Great Advantage

Two Resonances in LLC Tank

In related literature, it is often said that the LLC converter has two resonant peaks: one a series resonance
between C and L1, and another “parallel” resonance between C and (L1 + L2). So, people call it by many names:
fr, fs, fp, fm, fo, f∞ and so on. It can become confusing, which is why we have just preferred to call them f RES_1 and
fRES_2, based on the simple order they actually appeared in our discussions. Yes, f RES_1 does come about from the
resonance between C and L1, whereas the lower frequency peak, fRES_2 comes from the resonance between C
and (L1+L2). But are these series or parallel LC resonances?

We should not get confused by the fact that the conversion ratio (gain) at the first (higher) frequency is less than
1, as is typical of a series LC circuit, whereas the gain at the second (lower) frequency is greater than 1 (which is
perceived as true for parallel resonant circuits, in tuned circuits for radio applications etc.). To really find out
whether the peaks are series or parallel resonances, we need to plot out the input impedance (as seen by the
source). This is presented in Figure 14.

It is interesting that going from a shorted load to no load, the impedance presented to the AC input shifts
between what are clearly two resonant peaks of series resonant characteristics, because in parallel LC
resonance, the impedance becomes very high at resonance, not low as indicated by Figure 14.

One of the contributors to efficiency is switching losses, which we have tried to minimize by invoking ZVS. But
that advantage could be easily lost by excessively high conduction losses, as caused by high circulating currents.
One of the contributors to that circulating current is indeed L 2, which is why typically, L2 is kept at least 5× larger
than L1 (usually less than 10× though, as explained further below). Especially when we insert a transformer with
output diodes, we will see L2 significantly affects the current distributions in the LLC tank. Therefore, it is
recommended to keep L2 between 7 to 11 times L1 in any practical LLC converter. In our case we have fixed on
a factor of 9.

Note that in a parallel LC, the circulating current sloshes back and forth between the L and C, so the input source
may never “see” the high current. But in a series resonant case, the current does pass through the input source
and is inversely proportional to the impedance the network presents at its input terminals (to the source). If the
impedance is high, we will get small circulating currents (and higher efficiency). In Figure 14 we see that there is
a shaded encircled area of high impedance for almost any load. It is recommended in related literature that we
should try to remain here as much as possible. But note that our previously honed choices, R = 250 Ω or R = 300
Ω, fall in a very flat part of the encircled region. In other words, our previous design choice is actually good even
from the viewpoint of low conduction losses. We have to do nothing more to optimize.

Just for information, we mention that in related literature, the cusp labeled “fX” in Figure 14, is mentioned as
some sort of LLC converter “design target” because it offers high impedance. Its equation is f X = 1/ 2π√[C×{L1+
(L2/2)}]. We have however preferred to generalize our approach by describing a certain load resistor
Copyright © 2013 Microsemi Page 31
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Understanding and using LLC

Converters to Great Advantage

corresponding to max load at high line, one which a) gives an unambiguous direction of correction, and b),
makes the network appear just slightly inductive to the source (for ZVS). The desire for high input impedance is
automatically taken care of as we see from Figure 14.

LLC with C=10µF, L1=100mH, L2=900mH

4
110
In this region we have highest
impedance for all loads, so
there are less current stresses Previously suggested R=5k
Impedance presented by LLC circuit

and higher efficiency here. design entry point

R=1.5k
3
110
to input source (Ω)

R=800
R=400
R=300
R=200
R=100
100
R=50
~125Hz

fRES_1 = 159.2 Hz
fRES_2 = 50.3 Hz
OVERLOAD
(“SHORT”)
NO LOAD
(“OPEN”)

10
3
10 100 110
fX

Frequency (Hz)
To the right of the dotted locus line above, for any load, we have
inductive phase angle (good for ZVS). To the left we have
capacitive. We should thus choose switching frequency so we
consciously stay only to the right of this line, at least at max load.

CAUTION: Note that these curves only tell us the input impedance for a given load and frequency, so that
we can check whether the network appears inductive (for ZVS) or not. They do not provide the
frequency variation as we change the load or help pick a good design entry point! That is discussed later.
Figure 14: Plotting input impedance of the LLC tank circuit

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Understanding and using LLC

Converters to Great Advantage

PART 3: Microsemi Innovation

One of the perceived disadvantages of the LLC topology is that it handles input line variations poorly. This has
restricted it into a niche market, mainly AC-DC, and placed after a Power Factor Correction stage supplying a
steady 400V DC to the LLC Half-Bridge. It certainly could be of great advantage to achieve a wide input variation
with LLC, say 2:1 or better.

Another perceived disadvantage is that at light loads, LLC engineers are still not able to guarantee operation is
restricted at the upper end, especially at light loads. So most LLC controllers only place bounds on the
lowermost frequency. However it is advantageous to specify the upper limit too, because for example, the
designer may wish to stay decisively below 150kHz, which is the start of the CISPR 22 (EN55022) conducted
emissions band. If operation can be guaranteed below 150 kHz for a wide line variation, say 4:1 (e.g. 100VDC to
400VDC, or 110VAC to 240VAC), along with a full load variation (zero to max), it can be of great help in almost
eliminating input filtering, especially in AC-DC applications. It could also be of great help in minimizing effects of
switching converters on signal integrity where power and data coexist, such as in networking applications.

However the biggest stumbling block to widespread adoption of LLC in industry is simply this: it does not yet fill
into a predictable design schedule, so essential in modern development…and that in turn is because engineers
still adopt a trial and error approach to fixing the L, L and C values, along with the turns ratio.

In December 2012, Microsemi achieved a breakthrough, and as a result, a predictable design methodology is
emerging to account for all the weaknesses above --- wide input variation (4:1 estimated), set upper and lower
frequency limits and a commercially acceptable design procedure with minimum bench tweaking.

Copyright © 2013 Microsemi Page 33

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PRELIMINARY/ CONFIDENTIAL
AND8311/D

Understanding the LLC

Structure in Resonant
Applications
Prepared By: Christophe Basso http://onsemi.com
ON Semiconductor

The resonant LLC topology, member of the Series understand the resonant structure alone, object of the present
Resonant Converters (SRC) begins to be widely used in application note.
consumer applications such as LCD TVs or plasma display
panels. In these applications, a high level of safety and The LLC converter
reliability is required to avoid catastrophic failures once The LLC converter implies the series association of two
products are shipped and operated in the consumer field. To inductors (LL) and one capacitor (C). Figure 1 shows a
face these new challenges, ON Semiconductor has recently simplified representation of the resonant circuit where:
released to new controllers, the NCP1395 (low-voltage) and Ls is the series inductor
the NCP1396 (high-voltage) dedicated to driving resonant Lm is the magnetizing inductor
power supplies, usually of LLC type. However, before Cs represents the series capacitor
rushing to design a converter of this type, it is important to

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Lm
Rload
Cout

ÎÎÎÎÎÎÎÎÎ
CS D2

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Figure 1. The LLC Topology Uses a Half-Bridge Configuration to Drive the Resonant Circuit

© Semiconductor Components Industries, LLC, 2008 1 Publication Order Number:

January, 2008 - Rev. 0 AND8311/D
AND8311/D

The operating principle is rather simple: a constant 50% associated with leaky transformers (radiated noise) has to be
duty-cycle switching pattern drives QA - QB gates and a kept in mind when selecting the final configuration.
high-voltage square wave appears on node HB. By When studying the resonant converter, it is convenient to
adjusting the switching frequency, the controller can control reduce the architecture to a passive element arrangement
the power flow depending on the output demand. As a such as presented on Figure 2. The high-voltage square
transformer is needed for isolation purposes, its magnetizing signal is replaced by its fundamental content thanks to the
inductance plays the role of the second inductor Lm. The first harmonic approximation (the so-called FHA in the
series inductor, Ls, can either be a separated element or literature): because we operate a tuned LC filter, all
physically lump into the transformer. In this case, a harmonics can be considered as rejected and only the
voluntary degradation of both primary and secondary fundamental passes through. Of course, this statement holds
coupling naturally increases the leakage inductance which as long the controller drives the resonating work in the
can act as the series element. There are pros and cons to vicinity of its resonant frequency. Figure 2 offers such a
include the leakage element in the transformer. The cost and simplified representation of the resonant cell, actually
the absence of saturation play in favor of the integration but pointing out a series impedance (Ls and Cs) with a parallel
the difficulty to keep a precise value from lots to lots impedance (Lm and the reflected load).

Figure 2. The Impedance Representation Makes the LCC Operation Easier to Understand

Depending on the loading, the network resonant frequency • RL = ∞, light or no load condition, Lm appears in series
varies between two different values: with Ls and the whole network resonates to
• RL = 0, short-circuit, Lm disappears and Zseries 1
becomes a short. The series resonant point for Zseries is F min +
thus 2p ǸǒLS ) LmǓCS (eq. 2)

F max + F S +
1 • 0 < RL < ∞, the resonance which combines Lm and Ls ,
(eq. 1)
2p ǸL SC S shifts depending on the total quality coefficient.

At Fsw = FS, Zseries becomes a short and the ac transfer

function drops to 1 or 0 dB.

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AND8311/D

Lm = 600 mH
24.0 LS = 100 mH
Vout = 24 V Pout = 10 W, Q = 60
CS = 33 nF
N=8
Pout = 50 W, Q = 13

12.0
Pout = 100 W, Q = 6.7

V out(s)
20log 10 dB Pout = 200 W, Q = 3
V in(s)
0

Pout = 300 W, Q = 2
-12.0

-24.0

10k 20k FREQUENCY (Hz) 50k 200k

1 1
F min + F max + F S
2p ǸL S ) Lm)CS 2p ǸLSC S
Figure 3. The AC Response of Figure 2 Circuit with Various Load Conditions

This is actually what Figure 3 plots suggest by showing the ac transfer function of Figure 2 as the load changes.
If we now study the impedance seen from the half-bridge node, we have an expression showing a series association of
inductors and a capacitor. Sticking to Figure 2 sketch and writing the impedance seen between ground and Node 3, we have:
Z in + Z L ) Z C ) Z L ŦR ac (eq. 3)
S S in

ƪ Ǔƫ
2

ǒ
4 2
(wL m) R ac 2 1 R ac2
Z in + ) wL S * ) wL m (eq. 4)
ǒR ac
2 wC S R ac 2 ) w2L m 2
2 ) w 2L m Ǔ
2

In the low frequency portion, the terms associated with inductors are of less importance and Cs dominates. The impedance
is thus capacitive. As the frequency increases, the inductive portion starts to kick-in and the impedance goes up. This is what
Figure 4 describes. As one can see, all the curves go through point A whose value is independent from the resistive loading.
For the sake of a friendly exercise, we can solve Equation 4 with two different Rac values and find the frequency at which input
impedances equal. We obtain:
wA + ǸL Cm S ) 2L SC S
2
(eq. 5)

If we substitute this value into Equation 4, the impedance at point A is:

2L
L Sw S
S
ZA +
Ǹ
(eq. 6)
Lm
)1
2L
S
If we define the ratio R by Lm/Ls, we can re-arrange equation 6:

ZA +
Ǹ2(R ) 2)
R
Ǹ LS
CS
+
R
Ǹ2(R ) 2)
ZO (eq. 7)

Where Z0 represents the characteristic impedance of the series resonant network. Using the numerical values noted in the
graphs, we obtain a frequency of 43.8 kHz and an impedance of 38.3 dBW (82.6 W).

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3
AND8311/D

5
1
2
3
4

62.0
Inductive Region

Capacitive Region Pout = 300 W, Q = 2

50.0

38.0
Pout = 100 W, Q = 6.7 A

Pout = 50 W, Q = 13
26.0 Pout = 200 W, Q = 3

Lm = 600 mH
dBW LS = 100 mH
Pout = 10 W, Q = 60 Vout = 24 V
14.0
CS = 33 nF
N=8

10k 20k FREQUENCY (Hz) 50k 200k

1
F min
2p ǸL S ) L in)C S
Figure 4. Impedance Plots at Various Power Levels

If we now observe the resonant current waveforms in a LLC body diode turns on first. Observing figure 3, the output
converter working below or above the series resonance Fs , level goes down as the frequency increases.
we have different types of operation: Most of the LLC converters operate in the inductive region
• Capacitive mode: in this mode, where the current leads for the second bullet reason. Also, given the feedback
the voltage, the bridge MOSFETs operate in zero polarity, if by mistake the closed-loop LLC enters the left
current switching (ZCS). ZCS means that power side of the resonance, the control law reverses and a power
MOSFETs are turned-off at zero current. Back to figure runaway obviously occurs. It is thus extremely important to
3, we can see that the output level goes up as the clamp down the lower frequency excursion in fault
frequency increases. condition or during the startup sequence to avoid falling on
• Inductive mode: in this mode, the current lags the the other slope of the characteristics.
voltage and the power switches are turned-on at zero The inductive region can be split into two other regions,
volt (ZVS), virtually eliminating all capacitive losses. depending where you operate compared to the resonant
This operating way implies that a certain delay exists series frequency Fs, as defined by Equation 1. Figure 5
before operating the concerned MOSFET so that its represents the classical set of curves often found in the
dedicated literature:

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AND8311/D

Region 2
4.00
Q = 10

Region 1
3.00

Q=5

2.00
Q=2

Q=1

1.00
1
2
3
4
5
0
Q = 0.5
Region 3

200m 600m 1.00 1.40 1.80

Vf/FS (V)
F sw < F s F sw = F s F sw > F s

Figure 5. Typical Transmittance Curves with Various Loading Conditions, Highlighting Three Distinct Regions

Region 3 is the capacitive mode where you do not want to 1 1

F max + F S + +
2p ǸL SC S Ǹ116m
operate since ZVS is a wanted feature for the power 6.28 28n
switches. In regions 1 and 2, you still have ZVS on the power
MOSFET's and the output diodes are operated in Zero + 88.3kHz
Current Switching (ZCS), cancelling all associated losses at 1
F min +
2p Ǹ(L S ) L m)C S
turn-off. Before discussing the benefits of a particular
solution, let us have a look at the various operating phases
the LLC converter is made of. 1
+ + 33kHz
6.28 Ǹ(116m ) 700m) 28n
Operating Waveforms Below the Series Resonance,
Fsw < Fs Fsw = 70 kHz at full load and nominal input voltage.
For this example, we have selected a set of elements which The converter delivers 24 V@10 A from a 380 Vdc input
operate the converter below the series resonance defined by source and a simulation has been performed using the above
Equation 1. The following value have been used: values. Figure 6 shows the main waveforms obtained from
Lm = 700 mH the simulator. Let us study the switching events step by step
Ls = 116 mH to learn about the LLC behavior in this region.
Cs = 28 nF
N=8

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AND8311/D

14.0
V V
GS,lower GS,upper

vgsl, vgsu in volts

10.0 23

Q is on Q is off

plot1
6.00 B B
Q is off DT Q is on
A A
2.00 Gate voltages
22
-2.00

V
4.00 400 HB
Resonant currents
ils, ilmag in amperes

vbridge in volts

2.00 300
I
mag
plot2

0 200
25
26
-2.00 100
I
L
-4.00 0 I =I 24
L mag

30.0
id(d3a), idiode in amperes

I
d,peak
20.0 I I
d2 d1
I
plot3

out
10.0
28
0 27

-10.0 Diode current

478u 482u 486u 490u 494u
time in seconds

Figure 6. Waveforms Obtained for a Converter Operated Below the Series Resonant Frequency

QA is off, QB is on, D2 is conducting : resonates to Fs as Lm is shorted. Figure 7 depicts the

The low-side MOSFET QB imposes a 0 V potential on the situation during this period of time.
half-bridge node and the current circulates from its drain to
source (first quadrant). The upper parasitic capacitor CossA QA is off, QB is on, D2 turns off:
is fully charged to the input voltage Vbulk since the HB node As the network current IL resonates in a sinusoidal
is grounded by QB. The secondary diode D2 is conducting manner, its amplitude peaks and then starts to dip towards 0.
and imposes a voltage reflection -NVout over the When it reaches a level equal to that of the magnetizing
magnetizing inductor Lm. Its current linearly decreases with current, no current circulates in the transformer anymore: D2
a slope of -NVout/Lin. As this inductor is dynamically blocks and the voltage reflection over Lm disappears. The
shorted by the voltage reflection, it does not participate to magnetizing inductor now comes back in series with Ls and
the on-going resonance between Ls and Cs which deliver the Cs and changes the resonant frequency from Fs to Fmin: the
output energy (the input source is out of the picture). The LLC converter is really a multi-resonant structure and the
current flowing into the transformer primary side (given its plateau - actually a small arch of a lower sinewave
theoretical representation, Lm associated to a perfect oscillation - in the current as it appears on figure 6 testifies
transformer) is the main current IL minus the magnetizing for it. Both diodes are now blocked and this moment lasts
current Imag. D1 is blocked and undergoes twice the output until QB opens. Figure 8 represents the circuit during this
voltage given the transformer coupling. The circuit time. As one can see, the output capacitor alone supplies the
energy to the load.

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AND8311/D

Vbulk Vbulk

QA Vbulk QA
CossA CossA
LS IL-Imag LS IL-Imag
Iout Vout Vout
N:1 D1 N:1 D1

Imag Iout Imag

VLm Vout VLm
IL IL

Lm + Lm +
QB QB
Vout
Imag
Imag

IL-Imag D2 Iout IL-Imag D2

IL CS IL CS
IL
IL IL

Figure 7. QA is Off, QB is On and Diode D2 Conducts Figure 8. QA is Off, QB is On and Diode D2 Blocked.
Current. Lm is Off the Picture as it is Dynamically Lm Comes Back Again in the Resonating Network
Shorted by the Output Voltage Reflection. and Changes the Resonant Frequency to Fmin.

QA is off, QB is Off, Both Secondary Diodes are reversing (Figure 9). At this moment, when the HB node
Blocked reaches Vbulk + Vf, the body-diode of QA conducts and
Both transistors are now open, this is the dead-time period ensures energy re-cycling through the input source
(DT on Figure 6). The dead-time is placed here to avoid (Figure 10). You understand that this dead-time period must
cross-conduction between both MOSFETs but also to favor last a time long enough to allow for the complete discharge
Zero Voltage Switching as we will see in a moment. Because of CossA before re-activating QA so that its body-diode
the current was circulating from drain to source in QB, the turns on first. If not, hard switching occurs and efficiency
circuit no longer sees an ohmic path when this transistor suffers.
opens. The current strives to find a way through the parasitic As currents are oscillating, a time is reached where IL and
drain-source capacitors Coss of both QA and QB: CossB starts Imag are no longer equal (end of the plateau) and a current
to charge (it was previously discharged by QB being on) and circulates again in the primary side. D1 starts to conduct and
given the rise of VHB towards the high voltage rail, CossA NVout appears across Lm :the resonant frequency goes back
sees its terminals voltage going down to zero and then from Fs to Fmin. Figure 10 describes this moment.

Vbulk Vbulk
The Voltage is Falling
CossA
QA Reaches (Vin + Vf) when
The Voltage is Rising
QA Body-Diode Conducts
Iout Vout QA Vout
LS N:1 D1 LS N:1 D1
Vf
IL IL
Imag VLm Imag VLm

Lm + Lm +

QB
CossB QB
CossB
Imag Imag
IL-Imag D2 D2
CS CS
IL IL
The Voltage is Rising

Figure 9. QA is Off, QB is Off. The Current Finds a Figure 10. QA and QB are Still Off. The Current Finds
Circulating Path Through Both Transistors Coss, a Circulating Path through the Upper-side Body
Both Secondary-Side Diodes are Off. Diode. D1 Starts Conducting at the End of the
Plateau when IL 0 Imag.

QA is on, QB is off, D1 is on can therefore safely turn it on and benefit from Zero Voltage
Now that QA body-diode is conducting, we have a Conditions. As we have a sinusoidal waveform in the
negligible voltage across its drain and source terminals: we network, the resonating current reaches zero and reverses.

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AND8311/D

Lm is still dynamically shorted as D1 is conducting. The Figure 6. At this point, no current circulates in the
energy is delivered by the source to the output load. This is transformer and D1 naturally blocks. As explained before,
illustrated by Figure 11. the magnetizing inductor re-appears in the circuit since the
output voltage reflection is gone. The resonant frequency
QA is on, QB is off, D1 turns off changes from Fmin to Fs and the energy to the load is
The current IL is moving down and reaches the delivered by the output capacitor alone. Figure 12 shows the
magnetizing current level, we are the second plateau on circuit state during this event.

Vbulk Vbulk

QA QA
+ IL-Imag N:1 Vout + Vout
D1 LS N:1
LS
IL IL
Imag Imag
VLm Vout VLm

Lm + Lm +

QB
CossB Vout
QB
CossB
Imag Imag
IL-Imag
D2
CS CS
IL IL

Figure 11. The Current is Now Flowing from the Figure 12. As Both Diodes are Off, the Network
Source to the Output Via the Upper-Side Includes the Magnetizing Inductance which
Transistor QA. Changes the Resonant Frequency.

QA is of, QB is off, both secondary diodes are blocked towards ground. The drain falls down in a resonating
At a certain time, both transistors block and only their manner, involving both Coss in parallel and the equivalent
drain-source capacitors remain in the circuit. The current inductor made of Ls + Lm. Figure 13 represents the circuit
keeps circulating in the same direction but CossA starts to during this event.
charge: the voltage on the HB node drops and CossB depletes

Vbulk Vbulk
The Voltage is Rising
CossA CossA
QA QA
The Voltage is Falling
+ Vout + Vout
LS N:1 D1 LS N:1 D1

IL IL
Imag VLm Imag VLm

Lm + Lm +

QB
CossB QB
Imag Imag
D2 D2
CS CS
IL IL

Figure 13. The Current is Still Flowing through the Figure 14. When the Voltage on the Node HB
Source and Contributes to Discharge CossB. Swings Below Ground, QB Body-Diode Conducts.

The bridge voltage further dips and becomes negative is not playing any role here. The controller now activates QB
until the body-diode of QB conducts. This is what Figure 14 in ZVS and the transistor conducts in its 3rd quadrant for a
suggests. At the end of the plateau, where IL = Imag, D2 will few moments, until the current reaches zero and swings
start conducting, reflecting -NVout over the primary negative: we are back at the beginning of the first phase.
inductance. The energy comes from Cs and Ls, as the source

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AND8311/D

Zero Voltage Switching

Figure 15 zooms on these ZVS events and show the turns-on at a Vf across its drain-source terminals but the
various signals in play. The MOSFET current starts to be current is still negative: we are in the 3rd quadrant
negative before the appearance of its gate-source bias: this conduction. Finally, the current becomes positive and flows
is the body-diode conduction period. Then the MOSFET from drain to source, back to the 1st quadrant.

400 V GS,lower 8
V HB
200
Vbridge (V)

I D,lower

0 6
2

Body 1st
-200
diode quadrant
3rd
-400 Q B quadrant

7
400 V GS,upper
9
V HB
200 I D,upper
Vbridge (V)

Body -200 1st

Diode quadrant

-400 3rd
Q A
quadrant
485u 488u 491u 494u 497u
TIME (s)

Figure 15. Simulation Results Zooming on the MOSFET Variables

ZVS A
V bridge
V gsB

V gsA

I L(t) ZVS B

Figure 16. Measured Signals on a Demonstration Board Showing the ZVS Operation on QA.

The selection of a controller where the dead-time is Zero Current Switching

adjustable therefore represents an important selection By the term ZCS, we assume a natural blocking event
argument to fine tune the behavior and ensure a minimum when the current in the semiconductor is zero. When
conduction period of both body-diodes. operating the LLC converter below Fs, as it is the case in this

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9
AND8311/D

example, both secondary-side diodes are operated in ZCS. resonating current IL. This is the plateau on figure 6.
The current in the concerned diode (D1 or D2) naturally Observing the diode current in this particular mode gives
reaches 0 when the magnetizing current Imag equals the main smooth signals as shown on Figure 17.

I
d
48.0 22.0 4.00
I -I
L mag

Diode blocks
24.0 11.0 2.00
here as I =0
d
idiodein amperes

iprim in amperes
vdiodein volts
Plot1

0 0 0 12
10

Both diodes

are blocked.

11
-24.0 -11.0 -2.00

The other diode

conducts, V = -2 V
-48.0 -22.0 -4.00 R out

484u 487u 490u 493u 495u

TIME (s)

Figure 17. The Secondary-Side Diodes are Naturally Blocked When the Primary Current Vanishes to Zero

Startup sequence and short-circuit differentiating the voltage across the capacitor Cs and
During startup or short-circuit, the magnetizing inductor routing the resulting voltage to a fast latch input. Figure 19
is shorted and the resonant frequency becomes Fs. Because shows this solution where the component values must be
we designed the LLC converter to operate at a frequency adjusted to avoid false triggering in normal operating
lower than Fs, the operating fault mode (lack of feedback) of transients.
the controller naturally lies below Fs. In other words, if the Reference [1] has experimented a solution where the
LLC converter quickly starts-up, without soft-start at all, resonating capacitor is split in two values - Cs/2 - and two
the controller will quickly sweep from a high frequency high voltage diodes clamp the voltage excursion between
value down to the minimum authorized in case of fault. The ground and the bulk rail. As the voltage across the capacitor
current in the network can therefore peak to a high value (at is limited, the resonant current is also clamped. The solution
resonance, the LC impedance is only limited by ohmic appears in Figure 20. There are several drawbacks
losses) and destroy the power MOSFETs instantaneously. associated to the usage of this diode arrangement such as a
Figure 18a shows an oscilloscope shot captured on a LLC variable clamping level in relationship to the high-voltage
circuit started with a short soft-start period (≈20 ms): the rail. However, experience shows that this simple circuit
current peaks to 6 A. Increasing the soft-start period to a few brings an efficient protection to the converter experiencing
hundred of milliseconds clearly helps to smooth the peak a short-circuit. The diodes must be of fast types, MUR260
and keep it below 4 A. can be selected for this purpose.
Short-circuit protection is more difficult to achieve given
the resonating nature of the circuit. Some solutions exist like

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10
AND8311/D

Imax = 6.2 A

Imax = 3.8 A

Css = 1 μF IL(t) Css = 10 μF IL(t)

a b

Figure 18. The LLC converter peaks to a high current if started too quickly. Increasing the soft-start sequence
naturally calms down the current excursion.

Vbulk

LS N:1 D1
Vout

QB Lm
+
Rload
R15 C8 Cout
10k 100p D2
To Latch
Open
C4 R16 D2 R14 CS
10n 1k 1N4937 10k

Figure 19. Differentiating the Voltage Across the Resonant Capacitor Gives an Indication of the Current Flowing
Through it

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AND8311/D

Vbulk

QA
CS/2

LS N:1 D1
Vout

QB Lm
+
Rload
Cout
D2

CS/2

Figure 20. To Keep the Voltage Excursion on the Resonant Capacitor within Safe Limits, a Diode Network Forbids
any Lethal Runaways

Operating Waveforms Above the Series Resonance, secondary diode is always conducting. In other
Fsw > Fs words, a single resonance occurs in this mode at
For this example, we have selected a set of elements which full power, implying Ls and Cs only. Lm is out of
operate the converter above the series resonance defined by the picture as long as the converter operates in
equation 1. The following values have been used: continuous conduction mode (full load operation).
Lm = 1.2 mH 2. Observing Figure 21, we can see that the main
Ls = 200 mH resonant current IL changes from a sinusoidal
Cs = 44 nF waveshape to a straight line, implying a change in
N=6 the operating mode. This change occurs when a
1 1 voltage discontinuity appears across Ls terminals.
F max + F S + + This discontinuity comes from the delay between
2p ǸL SC S 6.28 Ǹ200m 44n the bridge signal VHB and the reflected voltage
+ 53.7kHz polarity across the magnetizing inductor Lm.
Figure 22 zooms on this particular moment where
1
F min + we can see that the bridge voltage goes down to
2p Ǹ(L S ) L m)C S zero via the body-diode activation of QB, but
1 because there is still current flowing in the
+ + 20kHz
6.28 Ǹ(200m ) 1.2m) 44n
transformer primary side (IL is different than Imag),
one of the secondary diode is still conducting,
Fsw = 70 kHz at full load and nominal input voltage. imposing a constant reflected output voltage
The converter still delivers 24 V@10 A from a 380 Vdc across Lm. The voltage across Ls is up by one step
input source and a simulation has been conducted using the which starts to reset it towards zero. This is the
above values. Figure 21 shows the main waveforms beginning of the linear segment, if we consider the
obtained from the simulator. There are several differences voltage across Ls almost constant. When IL
between this operating mode and the previous one: reaches the magnetizing current Imag, the
1. In the previous mode, the magnetizing inductance conducting diode blocks and the primary current
was released at a point where both secondary-side transitions to the second diode which now
diodes were blocked (IL = Imag). The resonant conducts. The voltage polarity across Lm reverses
frequency was therefore moved from Fs to Fmin and the resonant current goes back to its sinusoidal
during a certain time (the plateau on Figure 6). shape. The next segment occurs when QB opens
When operated above the series frequency Fs, the and the bridge voltage jumps to Vin via QA
magnetizing inductance is always shorted by the body-diode. This segment lasts until IL reaches
reflected voltage NVout or -NVout as one of the Imag again.

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AND8311/D

14.0 V GS,lower V GS,upper

vgsl,vgsuin volts
10.0 5
Q B is off

Plot1
Q B is on
6.00
DT
Q A is off Q A is on
2.00
6
-2.00 Gate voltages

4.00 400
ils,i(lmag)in amperes

Resonant currents
vbridge in volts

2.00 300 V HB
I mag
Plot2

0 200 9

-2.00 100 IL
8
-4.00 0 7
id(d3a),id(d3b)in amperes

35.0
Diode current
25.0 I d,peak
I d2 I d1
11
Plot3

15.0 I out

5.00
10
-5.00

473u 477u 481u 485u 490u

time in seconds

Figure 21. Figure 6 Waveforms Updated with a Converter now Operating Above the Series-Resonant Frequency
Fs

8.00 200 400 VL mag 15

vbridge in volts
ils in amperes

vprim in volts

4.00 100 300 ZVS

14
Plot2

0 0 200
IL s
-4.00 -100 100
V HB 19
0 S [( V
Lmag+ VC s ) L s
-8.00 -200

ZVS S [ ( V L + V bulk) L s
mag
14.0
vgsl,vgsuin volts

17
10.0
V GS,upper V GS,lower V GS,upper
Plot1

6.00

2.00
16
-2.00

800 + VC s
vls,vcapresoin volts

VL
mag
400 VC s
Plot3

0 21
7
-400 VL s
VL + V in
mag
-800

484u 487u 490u 494u 497u

time in seconds
Figure 22. The Voltage Discontinuity Across Ls Induces a Linear Segment in the Resonant Waveform

1. The diode are still operated in ZCS despite a (the segment on IL(t)) which smoothly leads the
switching frequency above Fs. This is thanks to the concerned diode to a blocking state. Figure 23
linear reset taking place on the resonant current illustrates this fact.

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AND8311/D

I
d
4.00 20.0 40.0
I -I
L mag

2.00 10.0 20.0

S [ (V L + VC s) L s 2
mag
idiodein amperes
iprimin amperes

vdiodein volts
Plot1

0 0 0 1

-2.00 -10.0 -20.0

-4.00 -20.0 -40.0 The other diode

conducts, V = -2 V
R out
3
481u 484u 487u 490u 493u
time in seconds

Figure 23. A Zoom on the Switching Diodes Reveal a ZCS Operation for Fsw greater than Fs

Operating Waveforms at the Series Resonance, Fsw = 1

F min +
2p Ǹ(L S ) L m)C S
Fs
For this final example, we have selected a set of elements
which operate the converter at the series resonance defined 1
+ + 28.2kHz
by Equation 1. The following values have been used: 6.28 Ǹ(277m ) 1.6m) 44n
Lm = 1.6 mH
Fsw = 73 kHz at full load and nominal input voltage.
Ls = 277 mH
When operated at the tank resonant frequency, the main
Cs = 17 nF
current IL(t) is sinusoidal as confirmed by Figure 24.
N=8
1 1
F max + F S + +
2p ǸL SC S 6.28 Ǹ277m 17n
+ 73.4kHz

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14
AND8311/D

16.0
Gate voltages

vgsu, vgsl in volts

12.0
V V 15

plot3
GS,upper GS,lower
8.00
Q is off Q is on
B B
4.00 DT
Q is on Q is off
A A
0 14

400 4.00
16
ils, i(lmag) in amperes
vbridge in volts

300 2.00
I
mag 17
plot1

200 0 20

I
100 -2.00 L I =I
I =I L mag
L mag V
HB
0 -4.00 Resonant currents
id(d3a), id(d3b) in amperes

20.0 I
d,peak
I I
d1 d2
10.0
I
plot2

out 19
0 18

-10.0

-20.0 Diode current

677u 681u 685u 688u 692u
time in seconds

Figure 24. At the Resonant Frequency, the Main Current is Sinusoidal. Also, There is no Deadtime Between the
Secondary-Side Diode Conduction Periods.

In this mode, the EMI signature is excellent as the 2I d.peak

I dc + (eq. 9)
distortion is least compared to the other modes. The p
secondary-side currents are at the boundary between the
segment-like shape and the dead-time period, as We can then evaluate the ac current flowing into the output
respectively observed for Fsw > Fs and Fsw < Fs. As we capacitor applying the following equation:
observed before, the diode block when the resonant current
equal the magnetizing current Imag. I Cou.RMS + ǸI2RMS * I2dc + Ǹ I2
peak
2
*
4I 2
d.peak
p2
(eq. 10)
[ 0.3I d.peak
Operating the LLC at the series resonant frequency offers
another advantage. Back to Figure 3, we can see a point In the simulated example, if we have a diode peak current of
where all curves cross. This point, for which Vout/Vin = 1, is 15.7 A at steady-state, the RMS current flowing in the
reached at the series resonance. When operated at this capacitor is therefore 4.7 A. If we simulate a similar
particular position, the LLC resonant network transfer converter in a 100 kHz 2-switch forward configuration, the
function becomes insensitive to load variations. This RMS current in the output capacitor reduces down to 0.5
characteristics is sometimes exploited when a LLC Arms. That is one of the major disadvantage of the resonant
converter is designed to operate at a fixed switching operation. The switching losses are almost removed,
frequency locked to Fs and the feedback loop drives the allowing high-frequency operation, but conduction losses
output voltage of a pre-converter. increase significantly.
The RMS current in the output capacitor is also at its
lowest value as no discontinuity, or deadtime, exists as Conclusion
shown on figure 6 for Fsw < Fs. We can quickly derive its This quick study of the LLC converter explores the
value in presence of sinusoidal signals: various operating modes of the power supply, mainly
dictated by the switching frequency value in relationship to
I d.peak
I d.RMS + (eq. 8) the series resonant frequency Fs. Most of LLC designs are
Ǹ2 operated at the series resonance in full load and nominal
input voltage conditions. The controller allows operation
The total dc current contributed by both diodes in the output
below Fs during an input voltage drop and lets the frequency
current delivered by the converter. This dc current can be
exceed Fs in light load conditions. Despite sinusoidal
linked to the equivalent full-wave rectification and equals:

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15
AND8311/D

currents, care must be taken in the selection of the output 2. Bo Yang, “Topology Investigation for Front-End
capacitor given the high ac ripple. Compared to dc-dc Power Conversion for Distributed Power
buck-derived applications, this is the penalty to pay with System”, Virginia Tech Dissertation, 2003”
LLC converters, however, largely compensated by the http://scholar.lib.vt.edu/theses/available/etd-09152
reduction in switching losses on both the primary transistors 003-180228/unrestricted/
(ZVS) and the secondary-side diodes (ZCS).

References:
1. Bo Yang, Fred C. Lee, Matthew Concannon, Over
Current Protection Methods for LLC Resonant
Converter, IEEE Conference 2003

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16
MODELLING AND CONTROL OF THE LLC RESONANT CONVERTER

Brian Cheak Shing Cheng

B.Sc., Queen's University, 2010

A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF

THE REQUIREMENT FOR THE DEGREE OF

MASTER OF APPLIED SCIENCE

The Faculty of Graduate Studies

(Electrical & Computer Engineering)

THE UNIVERSITY OF BRITISH COLUMBIA

(Vancouver)

December 2012

c Brian Cheak Shing Cheng, 2012
Abstract
To achieve certain objectives and specications such as output voltage regulation, any power elec-

tronics converter must be coupled with a feedback control system. Therefore, a topic of considerable

interest is the design and implementation of control systems for the LLC resonant converter. Addi-

tionally, with the current trend of smaller, more cost eective and reliable digital signal processors,

the implementation of digital feedback control systems has garnered plenty of interest from academia

as well as industry.

Therefore, the scope of this thesis is to develop a digital control algorithm for the LLC resonant

converter. For output voltage regulation, the LLC resonant converter varies its switching frequency

to manipulate the voltage gain observed at the output. Thus, the plant of the control system is
Vo
represented by the small signal control-to-output transfer function, and is given by P (s) = f .
The diculty in designing compensators for the LLC resonant converter is the lack of known

transfer functions which describe the dynamics of the control-to-output transfer function. Thus,

the main contribution of this thesis is a novel derivation of the small signal control-to-output

transfer function. The derivation model proposes that the inclusion of the third and fth harmonic

frequencies, in addition to the fundamental frequency, is required to fully capture the dynamics of

the LLC resonant converter. Additionally, the eect of higher order sideband frequencies is also

considered, and included in the model.

In this thesis, a detailed analysis of the control-to-output transfer function is presented, and
R

based on the results, a digital compensator was implemented in MATLAB . The compensator's

functionality was then veried in simulation.

A comparison of the derivation model and the prototype model (based on bench measurements)

showed that the derivation model is a good approximation of the true system dynamics. It was

therefore concluded that both the bench measurement model and the derivation model could be used

to design a z-domain digital compensator for a digital negative feedback control system. By using

the derivation model, the main advantages are reduced computational power and the requirement

for a physical prototype model is diminished.

ii
Table of Contents
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
List of SI Units and Prexes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 LLC Resonant Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 H-bridge Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1.1 Zero Voltage Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Resonant Tank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.1 Resonant Frequencies ωr1 ,ωr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.2 High Frequency Isolation Transformer . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Rectier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.1 Synchronous Rectication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4.1 Region 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4.2 Region 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Control of LLC Resonant Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.0.3 Variable Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.0.4 Pulse Width Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1 Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.1 Eects of Sampling Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 20

iii
3.1.2 Design of Digital Control Systems . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1.3 2-Pole-2-Zero Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2 Compensator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.1 Root Locus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.2 Bode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3.1 Bode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3.2 Nyquist Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Implementation and Verication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1 Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1.2 Bench Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.3 Compensator Design Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

R
4.1.4 Verication in PSIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
R

4.2 Texas Instruments DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5 Derivation of Control-to-Output Transfer Function . . . . . . . . . . . . . . . . . . 36

5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2 Transfer Function Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2.1 Frequency Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.2.2 Square Wave Approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.2.3 Bessel Functions of the First Kind . . . . . . . . . . . . . . . . . . . . . . . . 39

5.2.4 Amplitude Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.2.5 Results of Frequency and Amplitude Modulation . . . . . . . . . . . . . . . . 45

5.2.6 Isolation Transformer and Rectication Stage . . . . . . . . . . . . . . . . . . 47

5.2.7 Results of Analysis of the Derivation Model . . . . . . . . . . . . . . . . . . . 47

5.2.8 Phase Response of Control-to-Output Transfer Function . . . . . . . . . . . . 48

R
5.3 Verication of Derivation Model in PSIM . . . . . . . . . . . . . . . . . . . . . . . 50

6 Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Appendix A: Observation of Stability in Continuous and Discrete-time domains . . . . . . 59

A1: Continuous-time domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

iv
A2: Discrete-time domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
R

Appendix B: PSIM simulation schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
R

Appendix C: MATLAB derivation model code . . . . . . . . . . . . . . . . . . . . . . . . 62

v
List of Tables
1 Results of prototype model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2 Results of derivation model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

vi
List of Figures
1 A direct link between DC source(s) and load(s) . . . . . . . . . . . . . . . . . . . . . 1

2 Resonant tank circuits of resonant converter topologies . . . . . . . . . . . . . . . . . 3

3 LCC resonant tank circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 Comparison of LCC and LLC DC gain characteristic with varying Q-factors . . . . . 5

5 LLC resonant converter circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . 5

6 H-bridge inverter circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Resonant tank circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

8 Rectier circuit modelled as Rac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

9 SR phase delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
R

10 Synchronous rectication PSIM model . . . . . . . . . . . . . . . . . . . . . . . . . 13

11 Regions 1, 2, and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

12 Operation of LLC resonant converter in region 1 . . . . . . . . . . . . . . . . . . . . 16

13 Operation of LLC resonant converter in region 2 . . . . . . . . . . . . . . . . . . . . 17

14 Block diagram of negative feedback loop . . . . . . . . . . . . . . . . . . . . . . . . . 18

15 Block diagram of digital negative feedback loop . . . . . . . . . . . . . . . . . . . . . 19

16 2 pole 2 zero DSP implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

17 Bench test result of DC gain characteristic for Region 1 . . . . . . . . . . . . . . . . 26

18 Plot of relative frequency response of prototype model under dierent loading conditions 27
R

19 Prototype model frequency response data in MATLAB SISOTOOL GUI environment 28

20 Open-loop Bode plot of prototype frequency response data . . . . . . . . . . . . . . . 29

21 R
MATLAB step response of closed-loop system using prototype model . . . . . . . 30

22 R
PSIM circuit schematic of LLC resonant converter . . . . . . . . . . . . . . . . . . 31

23 R controller schematic of LLC resonant converter

PSIM . . . . . . . . . . . . . . . . 31

24 Error voltage of prototype model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

25 Output voltage ripple of prototype model . . . . . . . . . . . . . . . . . . . . . . . . 32

26 R
PSIM closed-loop response to step load change using prototype model . . . . . . . 33

27 Voltage loop ow diagram for DSP implementation . . . . . . . . . . . . . . . . . . . 35

28 Analysis road map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

29 Tank lter circuit schematic with equivalent resistance Rac . . . . . . . . . . . . . . 43

30 Comparison of the signicance between fundamental, third and fth harmonics . . . 46

31 Comparison of the fundamental component, with and without sideband frequencies . 46

32 Comparison of prototype frequency response data and derivation model (magnitude) 48

33 Comparison of derivation model and curve t model (magnitude) . . . . . . . . . . . 49

34 Comparison of prototype frequency response data and curve t model (phase) . . . . 50

35 R
MATLAB step response of closed-loop system using derivation model . . . . . . . 50

vii
36 Error voltage of derivation model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

37 Output voltage ripple of derivation model . . . . . . . . . . . . . . . . . . . . . . . . 51

38 R
PSIM closed-loop response to step load change using prototype model . . . . . . . 52

A-1 Unit circle in the z-domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

B-1 R
PSIM closed loop circuit schematic of LLC resonant converter . . . . . . . . . . . 61

B-2 R
PSIM open loop circuit schematic of LLC resonant converter . . . . . . . . . . . . 61

viii
List of Symbols
an nth coecient of 2P2Z transfer function denominator
th
bn n coecient of 2P2Z transfer function numerator

Co output capacitor

Cp parallel resonant capacitor

Cr series resonant capacitor

E energy of carrier and sideband frequency signals

e[k − n] nth previous error term

fs switching frequency

fsample sampling frequency

fmax maximum bandwidth frequency

Jn (β) Bessel function of the rst kind

KV CO VCO gain constant

LM magnetizing inductor

Lr series resonant inductor

N transformer turns ratio

Nprimary number of turns on primary side of transformer

Nsecondary number of turns on secondary side of transformer

pi ith pole

Psw power loss of semiconductor switch device

Q ratio between the characteristic impedance and the output load

r reference input

Rac equivalent AC resistance

Rc output capacitor equivalent series resistance

Ro output resistance

Rr series resistance

T sampling time

Tof f semiconductor switch device turn o time

Ton semiconductor switch device turn on time

u[k − n] nth previous term of compensator output

Vctrl control voltage

Vds drain-source voltage

Vg input voltage

Vo output voltage

Vp peak voltage

ix
Vs,1 fundamental component voltage expression

Vs,3 third harmonic voltage expression

Vs,5 fth harmonic voltage expression

zi ith zero

β modulation index

amplitude of small signal perturbation

Γ(x) gamma function

ωc angular carrier frequency

ωm angular modulation frequency

ωr angular resonant frequency

ω̂ voltage controlled oscillator free-running angular frequency

= equals

6= not equal to

≈ approximately equal to

± plus and minus

x
List of Abbreviations
2P2Z 2-pole-2-zero

AC alternating current

ADC analog-to-digital converter

AM amplitude modulation

DAC digital-to-analog converter

CLA Control Law Accelerator

TM
CPU central processing unit

DC direct current

DSP digital signal processor

EMI electromagnetic interference

FM frequency modulation

GUI graphical user interface

LCC inductor-capacitor-capacitor

LLC inductor-inductor-capacitor

LPF low pass lter

MOSFET metal oxide semiconductor eld eect transistor

P proportional control

PI proportional, integral control

PID proportional, integral, derivative control

PWM pulse-width modulation

RHPZ right hand plane zero

SISO single input single output

SMPS switched-mode power supply

SR synchronous rectier

UPS uninterruptible power supply

VCO voltage-controlled oscillator

ZVS zero-voltage switching

ZCS zero-current switching

ZOH zero-order hold

xi
List of SI Units and Prexes
A amperes

dB decibel

Hz hertz

s seconds

V volts
◦
degrees

−12
p pico(10 )
−9
n nano (10 )
−6
µ micro (10 )
−3
m milli (10 )
3
k kilo (10 )
6
M Mega (10 )
9
G Giga (10 )
12
T Tera (10 )

xii
Acknowledgments
I would rst like to express my sincere and utmost gratitude to my research supervisor, Dr. William

Dunford, for his patience and guidance throughout my studies at UBC. His support and mentorship

in both my academic and professional endeavors has been invaluable, and I am indebted to him for

his help over the past two years.

Secondly, I would like to thank my friends and colleagues at the UBC Electric Power and En-

ergy Systems Group. My time at UBC has been much more memorable because of the people I

have met here. In particular, I'd like to thank Rahul Baliga, Justin Wang, and William Wang for

the many technical and non-technical discussions that have been had. Additionally, I would like to

thank my former classmates and friends Colin Clark and Kyle Ingraham for their technical advice

and friendship.

I would also like to thank the Natural Sciences and Engineering Research Council of Canada

(NSERC) and Alpha Technologies Ltd. for their generous nancial support of this research project.

I must give my extended gratitude to Mr. Victor Goncalves for giving me the opportunity to com-

plete my internship at Alpha Technologies Ltd., as well as the many people I was fortunate enough

to collaborate with at Alpha Technologies Ltd. The technical expertise I received over the course of

this work was indispensable. Additionally, I would also like to thank Mr. Brian Bella of the Faculty

of Graduate Studies at UBC for his assistance with the application to the Industrial Postgraduate

Scholarship program.

Last but not least, I must thank my family for their unconditional support throughout the years.

Growing up, they have been my source of inspiration, and have provided me with exemplary exam-

ples of the person I one day hope to become. To each of them, I owe my deepest gratitude. I would

like to take this opportunity to individually thank each of these people who have made it possible

for me to get to where I am today. My grandmother; my parents Tom and Daisy, my uncles and

aunts Patrick and Janet; Millie and Gilbert, Cora and Joe; and Juno and Alex. A special `thank

you' also needs to extended to my cousins Jerey, Steven, Gibson, Jackie and Megan, who have all

become like my own brothers and sisters.

Finally, I would like to acknowledge and thank my grandfather, whose memory remains strong

with us to this very day.

xiii
Dedicated to my parents

xiv
1 Introduction
1.1 Background
Switched-mode power supplies (SMPS) are now found in many dierent industrial applications

and their function can vary from high power electric vehicles to low power biomedical devices and

equipment. There is particular interest in applying SMPS to medium and high power applications

for uninterruptible power supplies (UPS) designed for telecommunications-grade applications.

The next generation of SMPS aim to achieve high eciency, high reliability, high power density,

as well as low cost. As an example, in renewable energy applications, due to constraints in cost and

the physical limitations of energy storage, the benets of a well designed SMPS are immediate.

The application of DC-DC converters has recently become an important area of SMPS design as

the emergence of distributed generation and battery-based systems continues to grow. Additionally,

as the number of DC loads increases [1], using local DC power sources becomes more of a sensible

solution, and further encourages the development of DC-DC conversion technology.

For some applications, DC-DC converters are particularly useful, as it provides a direct interface

between energy storage elements, which are typically DC voltage sources, and DC loads. By

reducing the number of intermediate energy conversion processes, the overall eciency of the system

can be increased, while also potentially minimizing the cost of the system. To meet safety and

protection requirements, DC-DC converters can also be implemented with galvanic isolation between

the input source and output load.

AC Input
≈/= =/=
VS

DC Input
=/=
Figure 1: A direct link between DC source(s) and load(s)

A particular form of DC-DC converter is the resonant converter. In literature, resonant con-

verters have been thoroughly studied and it has been shown that they can oer many benets in

performance, size, and cost [2]. For example, resonant converters are able to achieve low switching

losses through the use of soft-switching techniques, and are able to be operated at greater switching

1
frequencies than other comparable converters.

The ability to operate at higher switching frequencies has the superior advantage of increasing

eciency, as well as decreasing the size of the discrete components, notably inductors and capacitors,

within the hardware. This is in comparison to pulse-width modulation (PWM) converters, where

the turn-on and turn-o losses of the switching devices at high switching frequencies can be high

enough to prohibit operation of the converter, even when soft-switching techniques are used [3].

Moreover, PWM converters utilizing high switching frequency operation can cause disturbances

such as electromagnetic interference (EMI) and suer from the eects of parasitic impedances.

However, under proper design, it is possible for resonant converters to utilize the leakage inductances

of the circuit as part of the resonant tank circuit. It was also found that certain resonant converters

are able to operate with low EMI [4]. Because of these advantages, resonant converters with

switching frequencies in the range of MHz are conceivable [2][5].

Some typical resonant topologies include the series resonant, parallel resonant, and the series-

parallel resonant converters.

1.2 Motivation
Because of the demand for resonant conversion, methods on how to design eective feedback con-

trol systems for resonant converters becomes a topic of considerable interest. To make a converter

valuable for practical system applications, and to achieve specications such as output voltage regu-

lation, it is necessary to adopt some form of feedback control. Furthermore, with the advancements

in digital signal processors, digital control techniques have become a feasible option. The applica-

tion of digital controllers has allowed for more exible designs when compared to analog controllers,

and allows for much greater reliability and system integration.

Consequently, this thesis will be centered around designing and implementing a digital control

system for a resonant power electronics converter topology to be used in a medium power appli-

cation. Chapter 2 will discuss in detail a resonant converter topology, followed by discussion on

implementing a digitally controlled negative feedback control loop for output voltage regulation in

Chapters 3 and 4. Lastly, a novel mathematical model of the small signal control-to-output transfer

function is presented in Chapter 5.

2
2 LLC Resonant Converter
Resonant power converters contain L-C networks, or resonant tanks, whose voltage and current

waveforms vary sinusoidally during one or more subintervals of each switching period [6]. Three

well-known resonant topologies include the series resonant, parallel resonant, and series-parallel

resonant. Although there are peculiar dierences in each of these topologies, the essential operation

is the same: a square pulse of voltage or current is generated, and applied to the resonant tank

circuit. Energy circulating within the resonant tank will then either be fully supplied to the output

load, or be dissipated within the tank circuit [2].

As documented in [7], the series and parallel resonant topologies shown in Figure 2 have several

limiting factors which make them the non-ideal choice for practical applications. For the series
Lr
resonant converter topology, light load operation requires a very wide range of switching frequencies

in order to retain output voltage regulation. It was also observed that for high input voltage

Lr conditions, the series resonant converter suers from high conduction losses, and the switching

network transistors
Vsquare(t) experience high turn-o current.
Cp V(t)
Compared to the series resonant converter, the parallel resonant converter topology does not

require a wide range of switching frequencies to maintain output voltage regulation. However, at

Cp V(t) input voltage conditions, the parallel resonant converter shows worse conduction losses, and
high

higher turn-o currents.

Lr Lr
Cr

Lr
Cr V(t) Vsquare(t)
Vsquare(t) Cp V(t)

Vsquare(t) Cp V(t)

(a) Series resonant converter (b) Parallel resonant converter

Figure 2: Resonant tank circuits of resonant converter Ltopologies

r
Cr

One possible solution to overcome the deciencies found in the above two converters is the series-

parallel or LCC (inductor-capacitor-capacitor) converter shown in Figure 3. Since it is known that

the operation around the resonant frequencyVhas V(t)

square(t)the greatest eciency, it is desired to operate the

converter around this operating point [7].

3
Lr

Lr
Cr Vsquare(t)

Vsquare(t) Cp V(t)

Lr
Cr
Figure 3: LCC resonant tank circuit schematic

Figure 4a plots the DC gain characteristic of the LCC resonant converter with dierent values

of the variable Q, and it can be seen in Figure 4a that more than one resonant frequency exists,
Vsquare(t)
depending on value of Q. Q is dened as the ratio between the characteristic impedance and the

output load and can be given by Equation 1 [8].

q
Lr
Cr
Q= (1)
R
where R is dened as the value of the output load resistance.

Furthermore, from the DC gain characteristic of Figure 4, it is understood that the segments of

the DC gain characteristic with a positive gradient are regions intended for zero-current switching

(ZCS) operation [7]. Given that the designed converter is to use metal-oxide eld eect transistors

(MOSFET) as the semiconductor switching device, the desired region of operation should therefore

be on the negative gradient, a region intended for zero-voltage switching (ZVS) operation [7]. This

is because the preferred soft-switching mechanism of MOSFET devices is ZVS. As outlined in [6],

ZVS mitigates the switching loss otherwise caused by diode recovery charge and semiconductor

capacitance often found in MOSFET switching devices.

Since it is known that operation on the negative gradient of the DC gain characteristic is desired,

the characteristics of this operating region should be observed. As an example, it can be seen in

Figure 4a that to achieve a gain value of 1.0 for increasing values of Q, the range of the ratio of the
fs
switching frequency to the resonant frequency
fr varies from 0.7 to 1.2. Therefore, it can be noted
that a fairly large range of switching frequencies is required to maintain a gain value of 1.0 when

the output load is changing.

4
Lr Lr
Rr Cr Rr Cr

V(t) Vsquare(t) LM V(t)

V(t) LM Rac

(a) LCC (b) LLC

Figure 4: Comparison of LCC and LLC DC gain characteristic with varying Q-factors

DC
With this understanding of the LCC
Vsquare (t) converter characteristics,
V(t) the LLC
Co (inductor-inductor-
Ro Vo(t)
Rac Vo(t)

capacitor) resonant converter shown in Figure 5 becomes a potential solution. Essentially the dual

of the LCC converter, the DC gain characteristics of Figure 4a are reversed in the LLC resonant

converter and are shown in Figure 4b.

Lr
Rr Cr

DC Co Ro Vo(t)
LM

Figure 5: LLC resonant converter circuit schematic

b0
e(k)
+ +
From Figure 4b, it can be seen that the operation at around the resonant frequency, the operation
u(k)

is in a region such that the DC gain characteristic has a negative gradient and therefore, ZVS

capabilities can be achieved in this

-1 region. Furthermore, by observing the DC characteristic
-1 of
z z
Figure 4b, and what was noted about the switching frequency range of the LCC, it can be seen

that in the LLC resonant converter, the gain value of 1.0 can be achieved for all loading conditions
b -a1
within a very narrow range of switching1 frequencies.

+ +
An additional benet of the LLC DC gain characteristic is that the resonant frequency of

Figure 4b has now shifted to a higher switching frequency in comparison to the equivalent ZVS

region resonant frequency of Figure 4a, and thus the potential for improvements in eciency and
z-1 z-1

b2 -a2
5
power density are greatly improved.

Some other advantages of the LLC resonant converter over other resonant topologies is its ability

to maintain ZVS characteristics under light load conditions, and low electromagnetic interference

(EMI) [4].

Since it has now been determined that the LLC resonant converter has many favorable features

for DC-DC conversion applications, Sections 2.1 - 2.4 will discuss each stage of the LLC resonant

converter, as well as the theory of operation.

2.1 H-bridge Inverter

The rst stage of the LLC resonant circuit is the H-bridge inverter. It is composed of four triode-

mode MOSFET transistors which are used to invert the input DC voltage to an AC sinusoidal

waveform. The use of MOSFET switches are preferred since they have high input impedance and

can operate at very fast switching speeds [9]. And as previously discussed, for eciency purposes,

the LLC resonant converter utilizes ZVS to eliminate the switching losses of the MOSFETs. Finally,

the frequency at which the switches are turned on and o will determine the frequency to be applied

to the resonant tank.

To be more precise, the H-bridge generates a square wave with frequency fs equal to the fre-

quency of the MOSFET switching. This quasi-square wave is established by switching on diagonally

placed switches at the same time to generate the high and low values of the square-wave waveform.

It can also be noted that to prevent a shoot through condition, a small dead band time can be

included between the turn-on and turn-o times of the diagonal switches.

Finally, the quasi-square wave output can be mathematically characterized by Equation 2 and

the basic circuit conguration of the H-bridge inverter can be given by Figure 6.

∞
X 4Vg
vsquare (t) = sin(n2πfc t) (2)
n=1,3,5,...
nπ

6
V(t)
V(t) LM Rac

DC
Vsquare(t) V(t)

Figure 6: H-bridge inverter circuit schematic

Lr
2.1.1 Zero Voltage Switching Rr Cr
Zero voltage switching (ZVS) is the preferred soft-switching mechanism for MOSFET devices, as it

mitigates the switching loss caused by diode recovery charge and semiconductor output capacitance

[6]. In [10], switching loss is dened as the simultaneous overlap of voltage and current in power
DC
MOSFET switches. LM
It is shown in [10] that by allowing the drain-to-source voltage Vds to reach zero before the

switch turns on, the switching power loss is made to be zero. However, when there is overlap

between Vds and the current ids , a non-zero loss can be observed. To allow Vds to reach zero, the

internal capacitance of the MOSFET must be discharged by reversing the direction of the current

ow through the MOSFET.

In general, ZVS occurs when the switching network is presented with an inductive load, and

hence, the switch voltage zero crossings lead the zero crossings of the switch current [6]. In the

case of the LLC resonant converter, ZVS operation of the H-bridge inverter switching devices is

achieved and maintained by the presence of the magnetizing inductance [3][11].

b0
An additional benet of ZVS is the reduction of electromagnetic interference (EMI) typically

associated with switching device capacitances [6].

e(k)
+
z-1
7

b1
+
2.2 Resonant Tank
The resonant tank circuit is the chief constituent of the LLC resonant converter, and is comprised

of series resonant inductor Lr , series resonant capacitor Cr , and a parallel resonant inductor LM .
There are numerous possible congurations in which the tank components can be arranged, but the

most frequently used arrangement found in literature is the connection of Lr and Cr in series and

inductor LM in parallel to the load. This arrangement is identical to the series resonant topology

with the addition of inductor LM . For a more complete model of the resonant tank, a series resistor

can also be included.

Lr
Rr Cr

Vsquare(t) LM V(t)
Rac

Figure 7: Resonant tank circuit schematic

The no-load transfer function of the LLC resonant tank circuit shown Figure 7 is given by

Equation 3

s2 (LM Cr )
H(s) = (3)
s2 Cr (LM + Lr ) + sCr Rr + 1
V(t) C Rac V (t)
Well-known relationships between
o o Vo(t)R
impedance o
and frequency are given by Equation 4.

ZL = jωL
(4)

1
ZC =
jωC

From these fundamental equations, it is shown that the impedance of the resonant tank can be

tuned according to the frequency applied to the tank circuit. It can then be said that by varying

Lr the impedance of the resonant tank, that the voltage gain seen at the output will dier, depending

LM Co Ro Vo(t)
on the frequency applied to the resonant tank. It is then concluded that this voltage gain will

determine the attainable output voltage value, and thus is the method in which output voltage

regulation can be achieved with the LLC resonant converter.

2.2.1 Resonant Frequencies ωr1 ,ωr2

From the values of Lr , Cr , and LM , two important operating conditions can be identied: ωr1 and

ωr2 . These operating points are dened as the resonant frequencies, and are dened by the applied

loading condition. From Figure 7, it can be seen that at the no-load condition, the inductance

LM is seen by the tank circuit as a passive load and thus, the resonant frequency can be given by

Equation 5.

1
ωr2 = p (5)
(Lr + LM )Cr
In the case where a nominal load is applied, the load seen by the resonant tank is eectively the

large output capacitance Co in parallel with inductance LM . Thus, the inductor LM is bypassed

by the eective AC short circuit and the resonant frequency can be given by Equation 6.

1
ωr1 = √ (6)
Lr Cr
In this thesis, operation is focused around the resonant frequency given by Equation 6, as this

operating point allows for greater eciency, and allows for regulation using only a narrow range of

switching frequencies.

2.2.2 High Frequency Isolation Transformer

Following the resonant tank circuit is a high frequency isolation transformer that can be used to

either buck or boost the sinusoidal voltage to the secondary side of the converter. The transformer

also serves the dual purpose of providing galvanic isolation, such that no direct current ows between

the input and output.

A rather remarkable feature of the transformer is that the magnetizing and leakage inductances

can be used as part of the tank circuit. For instance, the magnetizing inductance of the transformer

can be used as or part of the parallel resonant inductance LM , therefore potentially reducing the

number of additional discrete components required. Similarly, the leakage inductance can be made

a part of the series inductor Lr , depending on the design of the transformer parameters. This so-

called integrated magnetic can therefore be designed to serve the purpose of potentially increasing

the converter's power density.

The transformer ratio between the primary and secondary sides is given by the transformer

turns ratio and shown by Equation 7.

9
Nsecondary
N= (7)
Nprimary

2.3 Rectier
r L
The last stage of the LLC resonant converter is the full bridge rectier with capacitor output lter,
r R r C
which transforms the AC waveform to DC output. Similar to what was found in [6] and [12], the

full bridge rectier with capacitor lter is modelled as resistor Rac . The relationship between Rac
and the output load is given by

V(t) Vsquare(t) LM V(t)

LM Rac VI 8Vo 8
Rac = = 2 = 2 Ro (8)
Iac π Io π
Rac can then be reected onto the primary side by multiplying Equation 8 by the transformer

turns ratio given by Equation 7.

are(t) V(t) Co Rac Vo(t)

Ro Vo(t)

Figure 8: Rectier circuit modelled as Rac

Lr
From [6], the nal DC value of the output voltage and the output voltage ripple can also be
Rr Cr
determined by the following relationships.

1
Vo,dc = Vp (1 − ) (9)
2fs Co Ro
L
For the case of an
o C o V (t) R
M ideal full bridge rectier that has negligible ripple,o the switching frequency

fs and output capacitance Co are large such that the DC output voltage can be approximated by

b0
u(k)
Equation 10.

Vo,dc ≈ Vp (10)

where Vp is the peak value of the AC input voltage, V (t).

2.3.1 Synchronous Rectication

To further increase the eciency of the LLC resonant converter, a synchronous rectication (SR)

network can be implemented in lieu of the full bridge diode rectier. In a synchronous rectier,

the diodes are replaced with MOSFET devices, and when current ow is detected on the secondary

side, the MOSFETs are turned on to allow current ow to the load.

This is a much more ecient strategy in comparison to the diode rectier, as the voltage drop

across the diode is eliminated. Additionally, unlike diodes, which are only able to provide unidirec-

tional ow of power, a SR network makes bidirectional power ow between the input and output

feasible.

The disadvantage of implementing SR with the LLC resonant converter is the increased com-

plexity. Computer simulations of Figure B-1 found in Appendix B show the presence of a phase

delay between the voltage and current when the switching frequency is away from the resonant

frequency. The results of the simulation are shown in Figure 9.

Because of this, it is dicult to determine the timing of the SR turn-on and turn-o. Usually,

additional detection circuitry is required on the secondary side to determine when there is current

ow through the rectier, and to determine the control signal to the gates of the SR MOSFETs.

Furthermore, since MOSFETs do not have the ability for automatic reverse current blocking, the

timing of the turn-o is also important, such that shoot through conditions are avoided.

Some literature has been produced on the control of the SR gate drive signals in [13][14][15]. It

is known that the critical event for triggering the SR gate drive signal is the detection of current in

the secondary side. It was outlined in [15], that there are two main methods in which this can be

accomplished. The rst is to directly sense the current using a current transformer. Although this

may be the simplest method of detection, the use of a current transformer introduces limitations

of the power density as well as the maximum achievable switching frequency. Additionally, the

increased series inductance is detrimental to current commutation in the synchronous rectication

switch network [15].

Another possible method is to detect the drain-source voltage, Vds of the synchronous rectier

switches. The sensed value of Vds is then processed by control circuits to determine the turn-on

and turn-o time of the SRs. This approach can be relatively easily veried in simulation, but

the diculty of this method is determining a method in which Vds can be accurately measured.

Because there exists a package inductance from the MOSFETs in the SR, the measured value of

11
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Date: 05:07PM 09/27/12

Vtank Itra

150

100

-50

-100

-150

C:\Users\Brian\Documents\PSIM\difference_eq_CL_May17.smv
(a) Voltage and current waveforms in phase when fs = fr1 Date: 05:08PM 09/27/12

Vtank Itra

-20

-40

-60

(b) Voltage and current waveforms out of phase when fs 6= fr1

Figure 9: SR phase delay

12
Vds becomes highly deviated if the package inductance is not properly considered. If the physically

sensed value is far deviated from the true value of Vds , a false trigger of the SR circuits may occur,

and the potential for shoot through condition increases.

Some literature proposed by [13][14], have shown a number of methods to improve the accuracy

of sensing Vds . This is at the expense of circuit complexity, as several additional compensating

components are required.

A computer simulation using a current-sensing method has been proposed and is shown in

Figure 10.

Vout
V Iload
A

Vmos1 Vmos3

Vmos1
A V
Imos1
Isec Vmos1

Vmos3
V
Imos3
Vmos3

Vmos3 Vmos1

R

Figure 10: Synchronous rectication PSIM model
Title
Designed by
Revision Page 1 of 2

13
2.4 Theory of Operation
The fundamental operation of the LLC resonant converter is based on applying a voltage with

frequency fs to the resonant tank to vary the impedance of the tank circuit, thus controlling the

achievable gain seen at the output. From Figure 11, it can be seen that as the switching frequency is

increased, the output gain is decreasing. This implies that as the switching frequency is increased,

the impedance of the resonant tank is increased, and therefore, a larger voltage drop is observed

across the resonant tank circuit components, and less voltage is transferred to the load. The reverse

is true as well, such that as the switching frequency decreases, the DC gain increases, implying that

the voltage drop across the tank circuit has decreased, and the output voltage gain can be increased.

In the following sections, the operation of the LLC resonant converter is more closely considered,

and a single switching interval is analyzed.

There are three main regions of operation, commonly described as Region 1, 2, and 3. Operation

in Region 1, 2, and 3 is determined by the location of the operating point on the DC gain curve

shown in Figure 11. Region 1 and 2 are located on the negative gradient of the DC gain curve, and

Region 3 is located on the positive gradient. Region 1 is the set of switching frequencies greater

than the resonant frequency, while Region 2 is the set of switching frequencies below the resonant

frequency.

Figure 11: Regions 1, 2, and 3

Depending on the design specications and requirements that are desired, operation in any of

these regions is possible. As it is preferred to switch the MOSFET devices under ZVS conditions,

the focus will be on operation in Regions 1 and 2, which is graphically shown in Figure 11 as the

negative gradients of the DC gain curves.

14
2.4.1 Region 1
In Region 1, the magnetizing inductance LM from the transformer does not resonate with the other

tank circuit components, and is viewed as a passive load by the resonating series inductor and series

capacitor. Because there is always this passive load, it is possible for the LLC resonant converter to

operate at no load without having to force the switching frequency to very high levels. The passive

load also ensures ZVS is achieved for all loading conditions [7]. Region 1 operates at the resonant

frequency given by Equation 6.

2.4.2 Region 2
In Region 2, there are two distinct operating modes. In the rst time sub-interval, the series

inductor and series capacitor resonate together while the magnetizing inductance is clamped to the

output voltage, and has operation similar to that of Region 1. Therefore, the resonance only occurs

between Lr and Cr . The current in the resonant tank Ir then begins to increase and continues to

increase until the magnetizing current IM and Ir are the same. When the two currents are equal,

LM starts to resonate with Lr and Cr , and the second sub-interval begins. Since LM is now also

resonating with the Lr and Cr , the resonant frequency is given by Equation 5.

In Region 2, since multiple resonant frequencies are observed over one switching period, the

LLC resonant converter is considered to be a multi-resonant converter. Figure 13 shows the plots

of the LLC resonant converter operating in Region 2. Operation in the second sub-interval begins

during the time interval in which the output current is equal to zero.

Figures 12 and 13 show the plots of the gate-source drive signal Vgs , the resonant current Ir ,
the magnetizing current ILM , the capacitor voltage VCr and the output current Io . Figure B-2 in

Appendix B shows the labelled circuit schematic used to obtain the plots of Figures 12 and 13.

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Date: 05:22PM 09/27/12

Vgs1

0.8

0.6

0.4

0.2

I_r I_LM

100

-50

-100

V_Cr

-20

-40

I_o

-5

0.00055 0.00056 0.00057 0.00058 0.00059 0.0006

Time (s)

Figure 12: Operation of LLC resonant converter in region 1

16
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Date: 05:23PM 09/27/12

Vgs1

0.8

0.6

0.4

0.2

I_r I_LM

200

100

-100

-200

V_Cr

100

-50

-100

I_o

-10

0.00055 0.00056 0.00057 0.00058 0.00059 0.0006

Time (s)

Figure 13: Operation of LLC resonant converter in region 2

17
3 Control of LLC Resonant Converter
When correctly applied, the application of control theory and feedback can eliminate steady state

errors, moderate system sensitivity to parameter changes and disturbances, modify the gain or

phase of the system over a desired frequency range, and make unstable systems stable.

For this thesis, the objective is to design a voltage control loop to regulate the output voltage,

according to a predened reference voltage. In other words, regardless of disturbances to the system,

and more specically, the load; the output voltage is to remain at a constant value. Consequently,

a negative feedback loop was designed to achieve these specications.

Disturbances

r
Reference Input

+ e Compensation
Network
Actuator Switching Converter Vo
(VCO) P(s)
- G(s)

Sensor Gain

Figure 14: Block diagram of negative feedback loop

From Figure 14, it can be seen that the function of the negative feedback control loop is to

determine an input to the plant, such that the desired output behavior can be obtained. Specically,

for the LLC resonant converter, the objective is to generate a set of gate driving signals of frequency
r
f
Reference Inputfor the primary side switch network.
s
Figure 14 shows that by sensing the output y and comparing it to reference input r , the com-
e + Digital
Compensator
u Actuator Digital-to-Analog Plant
pensator network G(s) can generate the gate drive
(VCO) signals based on the given error signal
Converter P(s) e. The
- D(s)

error signal is the

y dierence between the y and r, and in a functional control loop, tends to zero

after some time period.

3.0.3 Variable Frequency Control Analog-to-Digital

Converter
Sensor Gain

Under normal operating conditions, the LLC resonant converter uses variable frequency control to

regulate the output voltage. This type of control requires a gate drive signal that has constant duty

cycle, but varying frequency.

18
To implement variable frequency control, an actuator that can produce a variable frequency

signal is required and can be realized by a voltage controlled oscillator (VCO). The VCO is an

electronic circuit designed to produce an oscillation frequency based on the control voltage Vctrl
and can be implemented as an analog circuit or with a digital signal processor. The relationship

between the input signal Vctrl and the output frequency signal ωo is shown in Equation 11.

ωo = ω̂ − KV CO Vctrl (11)

In Equation 11, ω̂ is the free-running frequency of the VCO, and KV CO is the gain of the voltage

controlled oscillator.

3.0.4 Pulse Width Modulation

Disturbances
Pulse-width modulation (PWM) is a xed frequency control method, and modies the duty cycle

of the pulses to regulate the output voltage. It has been suggested in the literature [16][17] that for
r
Reference Input
light and no load conditions that it may be more eective to control the LLC resonant converter

by using PWM rather than variable frequency

Network
+
control.Actuator
e
However, in this
Compensation
Switching work,
Converter it will be oassumed
V
(VCO) P(s)
- G(s)
that the converter always operates under nominal loading conditions, and therefore only requires
y
the use of the variable frequency control method.

3.1 Digital Control Sensor Gain

Digital controllers have many advantages over analog designs. Digital controllers can be designed to

be more robust, and can be easily manipulated for optimal control performance. Additionally, the

recent decreases in the cost and size of programmable micro-controllers and digital signal processors

(DSP) has made digital control a viable option for power electronics applications.

r
Reference Input

+ e Digital
Compensator
u Actuator Digital-to-Analog Plant
(VCO) Converter P(s)
- D(s)

Analog-to-Digital
Sensor Gain
Converter

Figure 15: Block diagram of digital negative feedback loop

19
3.1.1 Eects of Sampling Frequency
An essential consideration that is relevant to digital systems is the principle of sampling, a non-zero

timed event to capture the continuous-time data. Sampling is required to convert continuous-time

data to discrete-time for processing in the digital signal processor and is physically realized with

an analog-to-digital (A/D) converter. The aim of the A/D converter is to accept measured signals

from the output of the power electronic converter and then convert these signals into an electrical

voltage level that can be read by the DSP. Conversely, once the processing has been completed in

the DSP, a digital-to-analog (D/A) converter is used to produce a physical signal to be read by the

power electronic converter.

A crucial factor in digital design is the sampling rate at which the continuous-time signal is

sampled. Ideally, the sampling rate is innite such that the discrete-time system is equivalent to

the continuous-time model. Unfortunately, since this is not a realistic solution, the alternative

solution is to apply the Nyquist rate shown in Equation 12.

fsample ≥ 2fmax (12)

The Nyquist rate states that the sampling frequency must be at least twice the maximum band-

width in the system. By satisfying this criterion, aliasing and signal distortion in the reconstructed

signal can be avoided. It can be added that, in fact, it is recommended in [6] to make the sampling

frequency ten times the maximum bandwidth.

3.1.2 Design of Digital Control Systems

Digital controllers can be implemented using two primary methods: emulation and direct digital

design.

Digital controllers designed through emulation method use the continuous-time plant model, and

obtain the compensator model in continuous-time. The continuous-time s-domain model is then

converted to a discrete-time z-domain compensator by applying mathematical transformations.

Numerous methods to transform continuous-time transfer functions to discrete-time transfer

functions exists. Some typical methods include the Tustin method, zero-order hold, rst-order

hold, etc. From [18], it was found that for the most accurate models, the rst-order hold is the

most accurate discretization method, but at the expense of computational complexity. A more

general method that is typically used is the zero-order hold discretization as it provides a balance

of accuracy and computational eciency.

The advantage of the emulation method is that well-developed and familiar continuous-time

design methods can be applied. This method produces reasonably accurate results given that the

sampling rate is very fast. The main disadvantage of the emulation method is that after mapping

20
the compensator from continuous to discrete-time, it is possible that the control system can no

longer achieve the same performance characteristics as in the continuous-time domain model [18].

The other method which can be used to design a digital compensator is by using the direct

digital design methodology. Compensators implemented using the direct digital design technique

usually have signicantly better performance when implemented on digital signal processors. This

method of design immediately begins with a plant model already in discrete-time, and then the

compensator is designed based o the digitized plant model in the z-domain [19]. Thus, the proba-

bility of obtaining unexpected controller response and dynamics are mitigated when the controller

is implemented using a DSP.

3.1.3 2-Pole-2-Zero Compensator

Irrespective of which compensator design method is used, the end goal is to design a compensator

G(s) to supply the correct signals to maintain output voltage regulation. Loop compensation is

achieved by the placement of additional poles and zeros to the feedback system, in conjunction

with the system's natural poles and zeros. The system loop gain can then be shaped to the desired

performance and stability characteristics by the new poles and zeros introduced to the system. An

example of compensator in the digital domain is the 2-pole-2-zero compensator (2P2Z).

The 2-pole-2-zero compensator was selected as the compensator of choice as it can be simply

implemented in the z-domain as a dierence equation. Its transfer function is given by Equation 13.

bo + b1 z −1 + b2 z −2
H2p2z (z) = (13)
1 + a1 z −1 + a2 z −2
Determining the roots of the quadratic numerator and denominator of Equation 13 gives the

location of the zeros and poles of the compensator respectively.

Compared to P, PI, or PID controllers, the 2P2Z compensator allows for ve degrees of freedom,

and allows for the use of complex poles and zeros [20]. In fact, the P, PI, and PID controllers are

simply particular cases of the 2P2Z. For example, the PID controller uses the assumption that the

coecients a1 = −1 and a2 = 0.

bo + b1 z −1 + b2 z −2
HP ID (z) = (14)
1 − z −1
Furthermore, for implementation in the digital signal processor, the 2P2Z compensator transfer

function can be easily re-written in the form of a dierence equation.

u(k) = bo e(k) + b1 e(k − 1) + b2 e(k − 2) − a1 u(k − 1) − a2 u(k − 2) (15)

A functional block diagram of the 2P2Z is shown in Figure 16.

21
DC Co Ro Vo(t)
LM

b0
e(k)
+ + u(k)

z-1 z-1

b1 -a1
+ +
z-1 z-1

b2 -a2

Figure 16: 2 pole 2 zero DSP implementation

3.2 Compensator Design

Two popular methods in which a compensator can be designed for a feedback system are the Bode

diagram and root locus.

3.2.1 Root Locus

The root locus method is a plot of all system poles of the closed loop transfer function as some

parameter of the system is varied. This design method relocates the closed-loop poles to meet

performance specications such as overshoot, rise and settling times. This method is ensures that

acceptable transient response characteristics are reached, as well as robust compensator design

[21]. A disadvantage of the root locus method is that the system under test must be able to be

approximated as a second order system.

3.2.2 Bode Diagram

The Bode diagram displays the magnitude and phase response of a feedback system as two separate

plots with respect to the logarithmic frequency [22]. The Bode diagram is useful since the multi-

plication of transfer functions simply become problems of summation. The phase plot is generally
◦
given in degrees ( ) and the magnitude plot is given in decibels (dB) scale.

The conversion of magnitude to magnitude in decibels is given by Equation 16.

XdB = 20log10 |X| (16)

22
The performance of compensators designed using the Bode diagram method are based on the

bandwidth, gain margin and phase margin [21].

In the Bode diagram, a pole is represented by a 20 dB per decade decay, and a zero is a 20 dB

per decade increase.

3.3 Stability
To verify that the designed compensator and plant form a stable system, the stability of the closed

loop feedback system can be studied in either the continuous-time domain or the discrete-time

domain. The dierences in characteristic between the continuous-time and discrete-time domains

are discussed in Appendix A.

In this thesis, the stability of the control system will be observed using the Bode and Nyquist

diagrams.

3.3.1 Bode Diagram

The stability of the feedback system can be determined from the Bode diagram by observing the
◦
gain and phase margins. The phase margin is dened as the phase dierence from -180 at the

crossover frequency fc . The crossover frequency is dened as the instance at which the magnitude

plot is at unity. The phase margin can be calculated using Equation 17.

P.M. = 180 + 6 P (jωcrossover ) (17)

The gain margin is the point on the magnitude plot that corresponds to the point on the phase
◦
plot at which the phase crosses the -180 axis.
◦ ◦
Typically, the target phase margin is between 45 60 , and can be negotiated depending on the

requirements for the transient settling time and the stability. For the gain margin, it is generally

accepted that good gain margin is greater than 9 dB [23].

3.3.2 Nyquist Plot

Alternatively, the stability of the system can be observed using the Nyquist plot. The Nyquist

plot displays the frequency response as a single plot in the complex plane, and is a graphical

representation of the loop transfer function as jω traverses the contour map [24].

Stability in the Nyquist plot can be observed by applying the Nyquist stability criterion. This

criterion is determined by examination of the enclosure around the critical point (−1, 0). For closed

loop stability, the Nyquist plot must encircle the critical point once for each right hand pole, in a

direction that is opposite to the contour map [24].

23
It would be appropriate and useful to relate the Nyquist stability criterion to the Bode diagram

magnitude and phase plots [25]. There are two main relationships that can be made:

• The unit circle of the Nyquist plot is equivalent to the 0 dB line of the magnitude plot.

◦
• The negative real axis of the Nyquist plot is equivalent to the -180 phase line of the phase

plot.

24
4 Implementation and Verication
In this thesis, the plant process is given by the ratio of the output voltage to the switching frequency,

and is expressed in Equation 18. Since it was determined that the direct digital design method

gives superior results, it is the selected method for the design of the compensator.

Vo
P (s) = (18)
fs
Consequently, the rst step is to obtain a description of the plant process model, in either

continuous or discrete time, which can be discretized so that the compensator may be directly

designed in the discrete-time z-domain.

However, since the mathematical relationship described by Equation 18 is not well-dened in the

literature, one proposed solution is to measure the frequency response of the LLC resonant converter

using a network analyzer. The frequency response can be obtained by probing the output voltage,

and the switching frequency while the switching frequency is undergoing small signal perturbations

around a designated operating point.

This methodology has the main advantage of capturing the true behavior and dynamics of the

LLC resonant converter, as well as any additional behaviors that appear due to parasitic compo-

nents. This measurement method provides the most realistic representation of the plant process

model, however it assumes a prototype model has already been designed and is functional.

4.1 Design Methodology

4.1.1 Overview
The approach taken to design the digital controller was to rst use a laboratory bench prototype

model and network analyzer to obtain the frequency response data of the plant process model.

Dierent loading conditions were then applied to the prototype model to observe the changes in the

frequency response. Additionally, bench data of the DC gain characteristics under dierent loading

conditions were obtained to compare with the theoretical models presented in Chapter 2.

The obtained frequency response data of the physical plant model was then imported into
R

the MATLAB environment, and based on the obtained data, a compensator was designed in
R

MATLAB . To verify that the compensator design is satisfactory, the designed compensator
R

coecients can be extracted from MATLAB , and then exported to a software more suitable for

power electronics simulation.

R

Finally, an example implementation using a Texas Instruments -based digital signal processor

(DSP) is given.

25
4.1.2 Bench Test Results

1.03

1.02

1.01

0.99 0.35A
0.98A
Voltage Gain (V/V)

0.98 2.3A
2.92A
0.97 3.6A
4.6A
0.96

0.95

0.94

0.93
100 105 110 115 120 125 130 135 140 145
Switching Frequency (kHz)

Figure 17: Bench test result of DC gain characteristic for Region 1

Figure 17 shows the DC voltage gain characteristic of the prototype model when operated above

the resonant frequency. From these results, it is evident that for light loading conditions, the LLC

resonant converter begins to display non-linear characteristics, which suggests a separate control

loop may be necessary for light load operation. For loading conditions approaching the nominal

load, it appears that the prototype model follows the theoretical DC gain characteristics as given

by Figure 4b. Figure 17 also shows that the boundary condition between nominal and light loading

conditions for this particular converter lies around 2.3 A.

Given that the resonant frequency is the quiescent operating point, Figure 18 shows the fre-

quency response of the prototype model with dierent loading conditions. Figure 18 plots the

magnitude of the ratio between the output voltage and control voltage in decibels (dB) with re-

spect to the relative frequency in Hertz (Hz). From these results, it was determined that the

frequency response of the plant model also has a large dependency on the loading conditions.

Since there may be frequent changes to the load, the compensator design should be based on the

plant process model that represents the worst-case scenario. For this thesis, it will be assumed that

the converter is operated under nominal operating conditions, and thus, the worst-case is dened

as the loading condition such that the phase margin is minimum, as this is the condition that is

26
Bode Diagram
-10
1A
-15 2.3 A
3A
-20
3.6 A
-25 4.6 A
Magnitude (dB)

-30

-35

-40

-45

-50

-55

-60
180

90
Phase (deg)

-90

-180
2 3 4
10 10 10
Frequency (Hz)

Figure 18: Plot of relative frequency response of prototype model under dierent loading conditions

most likely to be overcome by problems of instability. In Figure 18, this scenario is represented by

the curve `4.6 A.'

It can be noted that the frequency response generally follows the form of a low-pass lter (LPF),

with the addition of a high frequency pole-zero combination. Because this system appears to be

greater than second order, design of the compensator using the Bode diagram technique is preferred

over other design methods.

4.1.3 Compensator Design Results

R

MATLAB has several useful tools for digital controller development. Firstly, built-in functions

such as `c2d ' make it straightforward to convert continuous-time s-domain models to discrete-time

z-domain models. Secondly, the Control System Toolbox features the SISO Design Tool which

27
allows for simple, visual design of control systems.

Root Locus Editor for Open Loop 1 (OL1) Open-Loop Bode Editor for Open Loop 1 (OL1)
1 -10
2.5e4
3e4 2e4
-15

0.8 3.5e4 0.1

1.5e4 -20
0.2
-25
0.3
0.6

Magnitude (dB)
4e4 0.4 1e4 -30

0.5 -35
0.4 0.6
-40
0.7
4.5e4 5e3
0.8 -45
0.2
0.9
-50
G.M.: 77.5 dB
Imag Axis

5e4 -55 Freq: 5e+004 Hz

0 Stable loop
5e4
-60
180
P.M.: Inf
-0.2
135 Freq: NaN
4.5e4 5e3
90
-0.4
45
Phase (deg)

4e4 1e4 0
-0.6
-45

-0.8 3.5e4 1.5e4 -90

-135
3e4 2e4
2.5e4
-1 -180
-1 -0.5 0 0.5 1 2 3 4
10 10 10
Real Axis Frequency (Hz)

R

Figure 19: Prototype model frequency response data in MATLAB SISOTOOL GUI environment

In this case, the frequency response data of the plot `4.6 A,' a continuous-time domain function,

is transformed into a discrete-time z-domain frequency response plot with the `c2d ' command and

an appropriate sampling time.

With the z-domain frequency response in hand, the `sisotool ' command opens the SISO Design

GUI for interactive compensator design, and allows for controller design using root locus, Bode

diagram, and Nichols techniques.

Using the Bode diagram design editor, the `sisotool ' GUI environment allows the user to manu-

ally add and position the poles and zeros of the compensator according to the specications required

for the control system [26]. The bandwidth, gain and phase margins, as well as the closed-loop step

response can then be easily obtained from the GUI environment to verify the stability and perfor-

mance of the designed compensator model.

28
Figure 20 shows the response of the open-loop system with the designed digital compensator.
◦
The open loop response appears to be stable and has a gain and phase margin of 53.8 dB and 60

respectively.

Open-Loop Bode Editor for Open Loop 1 (OL1)

0
Magnitude (dB)

-10

-20

-30 G.M.: 53.8 dB

Freq: 5e+004 Hz
Stable loop
-40
-90
Phase (deg)

-135

P.M.: 60 deg
Freq: 481 Hz
-180
2 3 4
10 10 10
Frequency (Hz)

Figure 20: Open-loop Bode plot of prototype frequency response data

Given that a step change to the control voltage input is applied to the system, the closed-loop

step response of the system is given by Figure 21, and shows a rise time of approximately 1 ms,

and after 2.5 ms, the steady state error is reduced to zero. The overshoot of the step response is

approximately 10%.

From the results of Figure 20 and Figure 21, it appears that a stable compensator with appro-

priate gain and phase margin has been designed. Since these results appear to be reasonable, the
R

designed compensator coecients can be exported to the PSIM simulation model for verication.

29
Step Response
1.4

1.2

0.8
Amplitude

0.6

0.4

0.2

0
0 0.5 1 1.5 2 2.5 3 3.5
-3
x 10
Time (sec)

R
Figure 21: MATLAB step response of closed-loop system using prototype model

R
4.1.4 Verication in PSIM
The negative feedback control loop of Figure 15 was implemented and simulated using Powersim's
R

PSIM simulation software, a software specically designed for power electronics simulation [27].

The simulation le includes a model of the LLC resonant converter in a negative feedback loop

conguration. Additionally, to more closely model the eects of the DSP circuit, the sample-and-

hold, and quantization eects of the analog-to-digital converter are also included in the model. As

seen in [28], the A/D converter can be approximately modelled as an ideal switch switching at

frequency fsample and a zero-order hold (ZOH) block. It will be assumed that the sampling rate

is high enough such that the sampling can be considered ideal. Additionally, a quantization block

been included to simulate the quantization error during typical A/D conversion [27].
R

The complete circuit schematic of the PSIM simulation model is shown in Figure 22, and the

controller components are shown in Figure 23. The model of the 2P2Z compensator is implemented

in the dierence equation format according to Figure 16, and the VCO actuator is designed according

to Equation 11.

In the simulation, the reference set point value of the voltage control loop was set to be 190 V.

Figure 24 shows that the steady-state value of the error voltage approaches zero, and conrms that

the controller meets the output regulation requirement.

30
C:\Users\Brian\Documents\PSIM\LOW2HI_FINALplay.smv
Date: 11:49PM 10/09/12

Verror

2.5 Vout

V Iload

A
2
Vgs1
Vmos1 Vmos3
V MOS1 MOS3
Vds1 Vc
Vgs1 Vgs3
1.5 Q1 V
Q3
Ires Ip
A A A
Vg 1 Isec
Vtank
Vm Vsec

0.5
Vgs3

V
Vds3 Vmos3 Vmos1
Vgs3 Vgs1 MOS2 MOS4
0 Q2 Q4

Isw
-0.5

R
Imos2
Figure 22: PSIM circuit schematic of LLC resonant converter
60

Verror f_s

40 V V
r
K H(z) K ZOH K sin K Vgs1

2P2Z_Compensator
Vgs3
Title
V_ref Designed by
20 Revision Page 1 of 1

Voltage Controlled Oscillator

Error Signal Generator

-20 R
Figure 23: PSIM controller schematic of LLC resonant converter

Verror
0.14

0.12

0.1

Title
0.08 Designed by
Revision Page 1 of 1

0.06

0.04

0.02

0.005 0.01 0.015 0.02 0.025 0.03

Time (s)

Figure 24: Error voltage of prototype model

31
Imos2

A study of the eects of a steady-state load step change are shown in Figure 26. A step load

change in the simulation is applied at t = 15ms, and from the results of Figure 26, it has been veried
20
that the designed control system that has been implemented is functional and is able to maintain

output voltage regulation even when undergoing changing loading conditions. As expected, the

switching
0 frequency fs increases when the load was decreased. Figure 26 also shows the response

of the current through the resonant tank, and the switching frequency.

For interest, the ripple voltage of the output voltage was also observed and was found to be
-20
approximately 1.4 mV and is shown in Figure 25.

Vout

190.0165

190.016

190.0155

190.015

190.0145

190.014
0.0295 0.02952 0.02954 0.02956
Time (s)

Figure 25: Output voltage ripple of prototype model

The results of the simulation are summarized in Table 1. Based on the nal results, it can be

concluded that a sucient digital controller has been designed to achieve output regulation.

Output voltage value: 190 V

Steady-state error: 0 V
Output voltage ripple 1.4 mV
% overshoot: 10%
Rise-time: 1 ms
Settling-time: 2.5 ms

Table 1: Results of prototype model

32
C:\Users\Brian\Documents\PSIM\LOW2HI_FINALplay.smv
Date: 10:43PM 09/27/12

Vout

190

185

180

Ires

200

100

-100

-200

f_s

300K

200K

100K

0 0.01 0.02 0.03 0.04

Time (s)

R
Figure 26: PSIM closed-loop response to step load change using prototype model

33
R DSP
4.2 Texas Instruments
R

To implement the voltage control loop digitally, a DSP is required. Texas Instruments (TI) has

a large portfolio of micro-controllers and digital signal processors available for use.

In this thesis, the TMS320F28035 Piccolo was selected as the ideal digital signal processor

as it has the capability to use both the on-board central processing unit (CPU) as well as the

additional Control Law Accelerator

TM (CLA) platform. The CLA has the advantage of minimizing
the processing latency of regular DSPs since it can execute time-critical control algorithms in parallel

with the main CPU [29].

The voltage control loop can be implemented onto the CLA partition of the TMS320F28035

DSP using assembly language programming. To assist with the programming related to the CLA,

the controlSUITE
TM package oered by TI provides many example code snippets for use.
Figure 27 shows an algorithm that can be used to implement the voltage control loop with the

CLA.

34
VOLTAGE LOOP MCU DESIGN FOR UPS LLC
Voltage Setpoint 2P2Z Digital Voltage Controlled LLC Resonant Voltag
Voltage Divider
Compensator Oscillator Converter

Setpoint, max output Initialize Code

voltage, 2p2z 1) Initialize Code:
coefficients · Define voltage setpoint, max
output voltage
· Define 2p2z coefficients
Output Voltage · Initialize CLA processor
ADC Read-in
· Disable primary PWM

2) ADC Read:
· Read output voltage (find
YES Overvoltage
Vo > Vomax
Protection average value?)
· If (Voltage Value > Vomax)
à OVP triggered and
NO
PWM disabled.

Calculate Error
Disable PWM 3) Voltage Control Loop (in CLA):
Voltage
· Calculate error
Verror = (Vsetpoint – Vo)
· Send error value to 2p2z
compensator
End Process
2P2Z à 2p2z outputs VCTRL
Compensator · Limit VCTRL between 6V – 8V.
· Send VCTRL to VCO
àVCO outputs fswitching

Control Voltage 4) PWM Update/Enable:

Limiter
· Update bit.TBPRD in “Main”
code.
· Enable primary PWMs.

Voltage Controlled
5) Restart:
Oscillator · Read new output voltage
value
· Loop steps 2 – 5.

Update PWM
switching
frequency/period

Enable Primary
side PWM

Figure 27: Voltage loop ow diagram for DSP implementation

35
5 Derivation of Control-to-Output Transfer Function
5.1 Overview
The control-to-output transfer function of the LLC resonant converter represents the ratio of the

output voltage Vo to small signal variations in the switching frequency fs . The diculty in designing

compensators for the LLC resonant converter lies in the fact that there are few known examples in

literature of the control-to-output transfer function, which in this case represents the plant process

model of the control loop.

Modelling the small signal characteristics of the LLC resonant converter is particularly dicult

because many averaging techniques, such as state space models cannot be used. In [7] and [30],

it is noted that unlike PWM converters, the control-to-output transfer of the converter cannot be

obtained by the state space averaging methods, due to the way energy is processed in the LLC

resonant converter.

Currently, most known applications ([30][31]) rely on bench measurements and frequency re-

sponse data to help determine the plant process model for the design of the compensation network.

In practice, the transfer function can be obtained by using a network analyzer to measure the fre-

quency response of the plant process model, and then using the data to design the compensator.

This methodology has the inherent disadvantage of requiring a pre-built functioning prototype

model.

A proposed control-to-output transfer function that does not use frequency response data was

presented in [32]. It was proposed that the control-to-output transfer function could be approxi-

mated as a third order polynomial. However, for the transfer function to be computed, variables

such as the damping factor and the beat frequency of the converter need to be known. Additionally,

a third order polynomial equation would not be able to predict the high frequency pole-zero shown

in Figure 32.

Finally, similar to the method proposed in [7], computer simulation can also be used. The

diculty in creating a simulation model that can accurately model the true component and parasitic

models may be dicult. With digital controllers, computer simulation is further complicated since

the modelling of the eects of the DSP hardware can only be approximated. Additionally, as noted

in [7], the computer simulation method requires extensive computing power.

5.2 Transfer Function Derivation

In the proceeding sections, a novel model of the small signal characteristics of the control-to-output
R

transfer for the LLC resonant converter will be presented. A MATLAB -based software program

has been developed to determine the frequency response of the derivation results, and will be

compared to the frequency response data obtained in Chapter 4.

36
Square V x H(jω) Full Bridge
Full Bridge Resonant Tank Power
DC Input Wave V x H(j(ω+ωm)) Rectifier with DC Output
As per Chapter 2, resonant converters
Converter H(jω) that utilize variable frequency
Transformercontrol regulate the output
Vs(t) V x H(j(ω-ωm)) Capacitor Filter
voltage by supplying sinusoids of dierent frequencies to the input of the resonant tank. The eect

of this is to alter the tank impedance, and thus control the voltage drop across the resonant tank.

Generating the appropriate sinusoid is accomplished by varying the switching frequency of the
Voltage Controlled
primary side switch network. Compensator
Oscillator
In order to develop a method to calculate the small signal control-to-output transfer function of

the LLC resonant converter, techniques borrowed from communications theory can be used. More

specically, the operation and analysis of the converter can be described by using analogies similar

to that of frequency modulation (FM), as well as amplitude modulation (AM).

The generalized block diagram shown in Figure 28 shows the steps of the analysis that will be

taken for the development of the derivation model.

ωc Amplitude
Square wave Frequency Resonant Tank
ωc +ωm modulation
Voltage modulation Voltage Output
ωc -ωm H(jω)

Figure 28: Analysis road map

5.2.1 Frequency Modulation

Recall that the general equation for a sinusoid is given by

v(t) = A cos (φ(t)) (19)

Frequency modulation is dened as a deviation in frequency from the carrier signal frequency.

Mathematically, this deviation in frequency can be expressed as the addition of an additional cosine

term to the carrier frequency [33]. The radial frequency of a signal undergoing frequency modulation

can be expressed as

ωs (t) = nωc t + ∆ω cos(ωm t) (20)

In the above equation, ∆ω is dened as the amplitude of the deviation from the carrier frequency,
and ωm , the modulating frequency, is dened as the rate of carrier deviation.

To arrive at an equation that can be substituted into Equation 19, the following relationship

between the angular velocity ωs (t) and the angle φ(t) is used.

37
Z
φ(t) = ωs (t)dt

(21)

∆ω sin(ωm t)
φ(t) = nωc t +
ωm

In the scope of this thesis, it is known that the deviation is actuated by a voltage controlled

oscillator and ∆ω can be substituted by

∆ω = 2πKV CO (22)

where KV CO is the gain of the voltage controlled oscillator, and the amplitude of the applied

small signal perturbation is given by the constant .

Therefore, Equation 21 can be expressed as

KV CO sin(ωm t)
φ(t) = 2π nfc t + (23)
ωm
To simplify Equation 23, the modulation index β can be substituted and is dened as

2πKV CO
β= (24)
ωm

5.2.2 Square Wave Approximation

The aforementioned mathematical relationships give a description of the eects of frequency modu-

lation on the carrier frequency. However, prior to applying the above equations for use in analysis,

the form of the original unmodulated signal must be determined.

The aperiodic square wave waveform is supplied from a DC voltage source and is produced as

a result of switching complementary pairs of eld eect transistor (FET) switches in the primary

side FET bridge. Mathematically, a generic square wave signal undergoing frequency modulation

is given as

∞
X 4Vg
Vs (t) = sin(n2πfc t + β sin(ωm t)) (25)
n=1,3,5,...
nπ

In [7], it is acknowledged that analysis including harmonics up to the fth harmonic may be

useful in modelling the control-to-output transfer function of the LLC resonant converter. Computer

simulations recorded in [7] show that by including the harmonic content, the accuracy of the models

are improved.

38
The model proposed in this thesis includes the third and fth harmonics, in addition to the

fundamental frequency of the square wave waveform. By including the third and fth harmonics in

the model, a more accurate understanding of the true dynamics of the converter can be observed.

Additionally, the eects of including supplementary sideband frequencies (for the case where |β|
does not meet the condition |β| << 1) are studied and included in the new model.

Equation 25 is therefore dened as

4Vg
Vs (t) = sin (ωc t + β sin(ωm t))
π
4Vg
+ sin (3ωc t + β sin(ωm t)) (26)
3π
4Vg
+ sin (5ωc t + β sin(ωm t))
5π

For simplicity, each individual harmonic component is redened as Vs1 (t), Vs3 (t), and Vs5 (t).

5.2.3 Bessel Functions of the First Kind

To gain better insight to the eects of frequency modulation, Bessel functions are used to determine

the amplitudes of the carrier and resulting sideband frequencies.

Expanding Equation 26 by using Bessel functions has the advantage of determining the locations

of the modulated frequencies in the frequency spectrum, as well as giving the amplitude of each

frequency component. As an example, Vs1 (t) can be expanded using Bessel functions and is given

4Vg 4Vg
Vs1 (t) = Jo (β) sin(ωc t) ± J1 (β) sin ((ωc ± ωm )t)
π π
(27)

4Vg 4Vg
±J2 (β) sin ((ωc ± 2ωm )t) ± ... ± Jn (β) sin ((ωc ± nωm )t)
π π

Jn (β) is denoted as a Bessel function of the rst kind and can be calculated by

∞ 2m+n
X (−1)m β
Jn (β) = (28)
m=0
m!Γ(m + n + 1) 2

In Equation 28, the variable n is the nth sideband frequency, and β is the modulation index.

In lieu of Equation 28, there are existing tables developed in [34], which can be used to determine

corresponding values of Jn (β) given the value of β.

39
In [35], there is an assumption that the value of |β| is much less than one. This is normally a

useful assumption as the following simplications of the Bessel functions become valid.

J0 (β) ≈ 1
(29)

βn
Jn (β) ≈
n!2n

As can be seen in Equation 29, for values of β much less than one, higher order sideband

frequencies will be approximately equal to zero.

However, since the assumption that β is much less than one is not always valid, the use of

Equation 29 is quite restrictive. Therefore, in this thesis, the assumption of |β| being much less
R

than one is not used. Instead, the values of |β| are determined and calculated in MATLAB with

the function `besselj'. This function is based on the tables found in [34].

Since the |β| value is no longer assumed to be small, the higher order values of Jn (β) become
th
signicant. Therefore, the n highest sideband to be considered remains to be determined.

It is known that the number of sidebands for the fundamental and harmonic components are

determined by the value of the modulation index β. Theoretically, under frequency modulation,

there are an innite number of sideband frequencies, and therefore, a nite number of sideband

frequencies must be selected in a way such that the majority of the signal's energy is captured.

According to Equation 24, β is inversely proportional to ωm . From this, the conclusion can be

drawn that as ωm increases, the modulation index becomes small, and the total number of sideband

frequencies is reduced.

Therefore, it can be said that the "worst-case" is the scenario when ωm is at its smallest value,

such that the value of |β| becomes large. For the purpose of this thesis, the value of ωm is taken to

be located at 1000π rad/s. By setting ωm to 1000π rad/s, a corresponding value of β is determined,

and the number of sidebands required can also be determined.

To verify that there are a sucient number of sideband frequencies, the sideband frequencies

that account for 99% of the signal energy (in the pre-determined worst case) are considered.

The energy of a carrier and sideband signals is determined by

x
X
E = Jo (β)2 + 2(Jn (β))2 (30)
n=1

To determine how many sidebands are needed to have 99% of the signal energy, an increasing

number of sidebands x is added to the carrier frequency amplitude until the value of E is equal to

0.99.

It was determined that by including three pairs of symmetrical sideband frequencies to the fun-

40
damental, third and fth harmonic components, that 99% of the signal energy would be accounted

for the case where ωm is greater than 1000π rad/s. Thus, Equation 27 can be written as

4Vg 4Vg
Vs1 (t) = Jo (β) sin(ωc t) ± J1 (β) sin ((ωc ± ωm )t)
π π
(31)

4Vg 4Vg
±J2 (β) sin ((ωc ± 2ωm )t) ± J3 (β) sin ((ωc ± 3ωm )t)
π π

5.2.4 Amplitude Modulation

Each individual frequency component is then passed through and ltered by the resonant tank

circuit at their respective frequencies. This is equivalent to amplitude modulation (AM) and is

mathematically equivalent to multiplying each frequency component with the resonant tank transfer

function at the corresponding frequency. The resulting signal represents a voltage, that will be

eventually applied to the secondary side of the converter.

As an example, the carrier, upper and lower sideband frequencies of the third harmonic under-

going amplitude modulation are given by Equations 32 - 38. Similar equations can be determined

for the fundamental and fth harmonic components.

4Vg
Vs3,carrier = J0 (β) × sin(3ωc t) × H(3j(ωc )) (32)
3π

4Vg
Vs3,upper1 = J1 (β) × sin ((3ωc + ωm )t) × H(j(3ωc + ωm )) (33)
3π

4Vg
Vs3,lower1 = −J1 (β) × sin ((3ωc − ωm )t) × H(j(3ωc − ωm )) (34)
3π

4Vg
Vs3,upper2 = J2 (β) × sin ((3ωc + 2ωm )t) × H(j(3ωc + 2ωm )) (35)
3π

4Vg
Vs3,lower2 = −J2 (β) × sin ((3ωc − 2ωm )t) × H(j(3ωc − 2ωm )) (36)
3π

4Vg
Vs3,upper3 = J3 (β) × sin ((3ωc + 3ωm )t) × H(j(3ωc + 3ωm )) (37)
3π

4Vg
Vs3,lower3 = −J3 (β) × sin ((3ωc − 3ωm )t) × H(j(3ωc − 3ωm )) (38)
3π

41
The Euler formula is useful in this case, and is given by

ejθ − e−jθ
sin(θ) = (39)
j2

Applying Equation 39 to the trigonometric term of the resonant tank outputs, the above equa-

tions can be rewritten. As an example, the equations of the carrier and sideband frequencies for

the third harmonic are shown in Equations 40 - 46. The equations for the fundamental and fth

harmonic components can be determined similarly.

Bo ej3ωc t − Bo∗ e−j3ωc t

Vs3,carrier = (40)
j2

(Bu ej3ωm t )ejωc t − (Bu ejωm t )∗ e−j3ωc t

Vs3,upper = (41)
j2

(Bl e−jωm t )ej3ωc t − (Bl e−jωm t )∗ e−j3ωc t

Vs3,lower = (42)
j2

(Bu,2 ej2ωm t )ej3ωc t − (Bu,2 ej2ωm t )∗ e−j3ωc t

Vs3,upper2 = (43)
j2

(Bl,2 e−j2ωm t )ej3ωc t − (Bl,2 e−j2ωm t )∗ e−j3ωc t

Vs3,lower2 = (44)
j2

(Bu,3 ej3ωm t )ej3ωc t − (Bu,3 ej3ωm t )∗ e−j3ωc t

Vs3,upper3 = (45)
j2

(Bl,3 e−j3ωm t )ej3ωc t − (Bl,3 e−j3ωm t )∗ e−j3ωc t

Vs3,lower3 = (46)
j2
Where Bo , Bu , Bl , Bu,2 , Bl,2 , Bu,3 , Bl,3 are dened by Equations 47 - 53

4Vg
Bo = J0 (β) × H(j3ωc ) (47)
π

4Vg
Bu = J1 (β) × H(j(3ωc + ωm )) (48)
3π

4Vg
Bl = −J1 (β) × H(j(3ωc − ωm )) (49)
3π

4Vg
Bu,2 = J2 (β) × H(j(3ωc + 2ωm )) (50)
3π

42
4Vg
Bl,2 = −J2 (β) × H(j(3ωc − 2ωm )) (51)
3π

4Vg
Bu,3 = J3 (β) × H(j(3ωc + 3ωm )) (52)
3π

4Vg
Bl,3 = −J3 (β) × H(j(3ωc − 3ωm )) (53)
3π
The resonant tank circuit H(s) is given by Figure 29 and the s-domain transfer function is given
by Equation 54.

Lr
Rr Cr

V(t) LM Rac V(t)

Figure 29: Tank lter circuit schematic with equivalent resistance Rac

s2 Cr Rac LM
H(s) = (54)
s3 Lr Cr LM + s2 (Cr Rac LM + LM Cr Rr + Lr Cr Rac ) + s(LM + Rr Cr Rac ) + Rac

In the above equations, the frequency domain variable s is taken such that s = jωm , and jωc
DC
is the quiescent operating point. This is done in order to work in Vsquare(t)
terms of the relative frequency, V(t)
rather than the absolute frequency.

The individual mathematical representations of the fundamental, third and fth harmonic volt-

age outputs from the resonant tank have now been determined. The total output voltage of the

resonant tank is then the sum of the harmonic output equations. The complete output voltage

equation can therefore be written as

v(t) = ||A|| sin(ωc t + 6 A) + ||B|| sin(3ωc t + 6 B) + ||C|| sin(5ωc t + 6 C) (55)

Continuing with the previous given example, the vector B is therefore dened as
Lr
Rr Cr
43

DC
LM
B = Bo + Bu ejωm t + Bl e−jωm t + Bu,2 ej2ωm t + Bl,2 e−j2ωm t + Bu,3 ej3ωm t + Bl,3 e−j3ωm t (56)

Equation 55 represents the output voltage as a sinusoid having time-varying amplitude and also

time-varying phase.

Since the goal of this analysis is to determine the change in output voltage due to the eect

of small variations to the switching frequency, the magnitude of Equation 55 must be evaluated.

As was discussed, the eect of passing frequency signals through the resonant tank is the same as

applying amplitude modulation (AM). Therefore, similar to AM analysis techniques, the envelope

of the waveform should be extracted to study the change in the output voltage [33].

From AM analysis, it is known that the magnitude of the coecients ||A||, ||B||, and ||C|| contain
the envelope of the signal. The square of the magnitude can rstly be determined by multiplying

the vector with its complex conjugate. E.g. for B, the magnitude can be determined by

||B||2 = BB ∗ (57)

To make use of some mathematical simplications, it is assumed that only the dominant DC

components are relevant. If this is true, then the following approximation can be made.

p 1
1+ξ ≈1+ ξ (58)
2

Thus, the magnitudes of A, B, and C are determined to be

||A|| = ||Ao || + ||Al ||

||Ao A∗l + Au A∗o + Al A∗l,2 + Au,2 A∗u ||
+ sin(ωm t + 6 (Ao A∗l + Au A∗o + Al A∗l,2 + Au,2 A∗u ))
||Ao ||
||Ao A∗l,2 + Au A∗l + Al A∗l,3 + Au,2 A∗o + Au,3 A∗u ||
+ sin(3ωm t+ 6 (Ao A∗l,2 +Au A∗l +Al A∗l,3 +Au,2 A∗o +Au,3 A∗u ))
||Ao ||
||Ao A∗l,3 + Au A∗l,2 + Au,2 A∗l + Au,3 A∗o ||
+ sin(5ωm t + 6 (Ao A∗l,3 + Au A∗l,2 + Au,2 A∗l + Au,3 A∗o )) (59)
||Ao ||

44
||B|| = ||Bo || + ||Bl ||
||Bo Bl∗ + Bu Bo∗ + Bl Bl,2
∗
+ Bu,2 Bu∗ ||
+ sin(ωm t + 6 (Bo Bl∗ + Bu Bo∗ + Bl Bl,2
∗
+ Bu,2 Bu∗ ))
||Bo ||
∗
||Bo Bl,2 + Bu Bl∗ + Bl Bl,3
∗
+ Bu,2 Bo∗ + Bu,3 Bu∗ || ∗
+ sin(3ωm t+6 (Bo Bl,2 +Bu Bl∗ +Bl Bl,3
∗
+Bu,2 Bo∗ +Bu,3 Bu∗ ))
||Bo ||
∗ ∗
||Bo Bl,3 + Bu Bl,2 + Bu,2 Bl∗ + Bu,3 Bo∗ || ∗ ∗
+ sin(5ωm t + 6 (Bo Bl,3 + Bu Bl,2 + Bu,2 Bl∗ + Bu,3 Bo∗ )) (60)
||Bo ||

||C|| = ||Co || + ||Cl ||

||Co Cl∗ + Cu Co∗ + Cl Cl,2
∗
+ Cu,2 Cu∗ ||
+ sin(ωm t + 6 (Co Cl∗ + Cu Co∗ + Cl Cl,2
∗
+ Cu,2 Cu∗ ))
||Co ||
∗
||Co Cl,2 ∗
+ Cu Cl∗ + Cl Cl,3 + Cu,2 Co∗ + Cu,3 Cu∗ || ∗
+ sin(3ωm t+ 6 (Co Cl,2 +Cu Cl∗ +Cl Cl,3
∗
+Cu,2 Co∗ +Cu,3 Cu∗ ))
||Co ||
∗ ∗
||Co Cl,3 + Cu Cl,2 + Cu,2 Cl∗ + Cu,3 Co∗ || ∗
+ sin(5ωm t + 6 (Co Cl,3 + Cu A∗l,2 + Cu,2 Cl∗ + Cu,3 Co∗ )) (61)
||Co ||

In Equations 59, 60, and 61, it is shown that each harmonic component has a DC and a small

signal cosine term. It is known that the envelope function is represented by the amplitude of the

small signal term, and this is the value of output voltage that is to be observed in the control-to-

output transfer function.

Vo
Therefore, to get the transfer function P (s) =
f , the magnitude of the envelope voltage ex-
∆ω
pression is divided by the small signal variation in frequency represented by
2π , as dened by
Equation 22.

5.2.5 Results of Frequency and Amplitude Modulation

Figure 30 shows the frequency response of each harmonic component and shows the contribution

of each harmonic after being ltered by the resonant tank circuit. The results of Figure 30 conrm

the third and fth harmonic components have signicant contribution to the transfer function, and

therefore it has been shown that they may not be neglected in analysis.

The result of the summation of the fundamental, third and fth harmonic components is also

shown in Figure 30.

For comparison, Figure 31 is a plot of the fundamental harmonic component and shows the

eect of including and not including the sideband frequencies in the derivation model. From the

results of Figure 31, it can be seen that the sideband frequencies have a signicant eect on the

resulting magnitude plot.

45
Figure 30: Comparison of the signicance between fundamental, third and fth harmonics

Figure 31: Comparison of the fundamental component, with and without sideband frequencies

46
5.2.6 Isolation Transformer and Rectication Stage
The next stage of the LLC resonant topology is the high frequency isolation transformer, located

after the resonant stage. To model the eect of the transformer on the control-to-output transfer

function, the transformer turns ratio can be multiplied to the magnitude of Equation 55 in order

to get an equation of the voltage seen on the secondary side of the converter.

N1
vsecondary (t) = × v(t) (62)
N2
The frequency response data of Figure 18 shows that a pole-zero combination appears at high

frequencies. It was determined that the cause of the zero is a result of the output capacitor equivalent

series resistance, as well as the presence of a right hand plane zeros (RHPZ). In [36], it is stated

that the RHPZ is a result of the inductor current not being able to instantaneously change, and is

a function of the inductance and load [37].

The ESR zero is located at a xed frequency, and is given by Equation 63.

1
ωesr = (63)
C o Rc
The ESR and RHPZ zeros are compensated by high frequency poles which were determined to

be contributed by system delays [38]. A system delay in the s-domain can be given by

Hdelay (s) = e−sT (64)

To evaluate Equation 64, the third order Padé approximation is used and the transfer function

of the high frequency pole is given by Equation 65 [39].

60 − 24sT + 3(sT )2
e−sT ≈ (65)
60 + 36sT + 9(sT )2 + (sT )3
By combining all of the above eects presented with the results of Figure 30, the analysis nally

gives the magnitude plot of the derivation model of the control-to-output transfer function. The

results of the analysis can be compared to the frequency response data of Chapter 4 and are shown

in Figure 32.

5.2.7 Results of Analysis of the Derivation Model

Figure 32 compares the results of the derivation model and the frequency response data of the

prototype model. From the results, it can be seen that the derivation model is a good approximation

of the frequency response data, and therefore conrms the proposed model is adequate for modelling

the small signal control-to-output transfer function. Therefore, it has been shown that by including

47
Figure 32: Comparison of prototype frequency response data and derivation model (magnitude)

harmonics up to the fth harmonic, as well as sideband frequencies in the derivation model, a

reasonably accurate model of the small signal control-to-output transfer function can be achieved.

From Figure 32, it is observed that at the lower frequencies, the error is largest, and there

is approximately a maximum of 5 dB dierence between the frequency response data and the

derivation model. This non-conformity can be attributed to have not included enough of the

sideband frequencies in the model.

As was discussed in Section 5.2.3, the derivation model only considers the sideband frequencies

that appear under the condition ωm = 1000π rad/s. The equivalent value of this ωm in frequency

is at 500 Hz, and from Figure 32, it can be seen that this is approximately the point at which the

discrepancies appear. Therefore, if the chosen value of ωm was smaller, more sideband frequencies

would have been added to the model, and the accuracy of the derivation model would improve for

the low frequency region.

The importance of the sideband frequencies is further shown in Figure 32, such that for frequen-

cies greater than 2 kHz, the derivation model gives a very close approximation of the magnitude

response of the bench prototype model.

5.2.8 Phase Response of Control-to-Output Transfer Function

To gain an understanding of the phase response of the control-to-output transfer function, the

asymptotic Bode tracing technique of [40] can be applied to the magnitude response. This method

approximates the s-domain transfer function of frequency response plots by using knowledge of the

behaviors of simple poles and zeros.

48
Qm
|(s − zi )|
|H(s)| = k Qni=1 (66)
i=1 |(s − pi )|
m
X n
X
6 H(s) = 6 (s − zi ) − 6 (s − pi ) (67)
i=1 i=1

By extracting an approximate s-domain transfer function equation of the magnitude response,

the corresponding phase response can be obtained. The accuracy of the plot can be increased simply

by increasing the number of poles and zeros used to model the magnitude response.

The curve t result is shown in Figure 33 and is compared to the frequency response phase data.

Figure 33: Comparison of derivation model and curve t model (magnitude)

Figure 33 shows a reasonable curve tting of the derivation model frequency response. As

previously stated, the accuracy of the curve t can be adjusted by increasing the number of poles

and zeros used during the curve tting process.

There are several alternative methods in which a curve t of the frequency response can be ob-

tained. However, compared to asymptotic Bode tracing, many of the analytical methods presented

in literature such as [41] [42], are cumbersome and unmanageable for normal use, and methods

that use software tools are costly to acquire and oer little to no exibility in terms of pole/zero

placement [30].

Figure 34 compares the results of the phase plot from the derivation model and is compared with

the frequency response data of Chapter 4. The results appear to be a good quality approximation

of the obtained data. However, it can be noted that the curve t model presents a more pessimistic

view of the phase response, and was unable to capture phase lead characteristic between 2 and 4

kHz.

49
Figure 34: Comparison of prototype frequency response data and curve t model (phase)

R
5.3 Verication of Derivation Model in PSIM
To verify that the derivation model can be used as an approximation of the control-to-output transfer
R

function, a compensator based on the derivation model results was designed in MATLAB . The

results are shown in Figures 35 - 38, and are summarized in Table 2.

Step Response
1.4

1.2

0.8
Amplitude

0.6

0.4

0.2

0
0 0.5 1 1.5 2 2.5
-3
x 10
Time (sec)

R
Figure 35: MATLAB step response of closed-loop system using derivation model

50
6
-100

4
-200

2 Verror
0.12
Ip
0.1
200
0.08

0.06
100

0.04

0
0.02

0
-100
0.01 0.02 0.03 0.04
Time (s)

-200 Figure 36: Error voltage of derivation model

Vout
190.0175

190.017

190.0165

190.016

190.0155

190.015

0.025 0.02502 0.02504

Time (s)

Figure 37: Output voltage ripple of derivation model

The results of the digital negative feedback control system designed by using the derivation

model are summarized in Table 2. It was found that the results of Table 2 are comparable to those

of Table 1 found in Chapter 4. Therefore, it can be concluded that the derivation model can be used

for digital compensator design, and is able to produce similar results to a compensator designed

based on physical prototype data.

51
C:\Users\Brian\Documents\PSIM\LOW2HI_FINALplay.smv
Date: 06:55PM 10/02/12

Vout

192

190

188

186

184

182

Ires

200

100

-100

-200

f_s

200K

-200K

-400K

-600K
0 0.01 0.02 0.03 0.04
Time (s)

R
Figure 38: PSIM closed-loop response to step load change using prototype model

52
Output voltage value: 190 V
Steady-state error: 0 V
Output voltage ripple 1.5 mV
% overshoot: 10%
Rise-time: 0.9 ms
Settling-time: 2 ms

Table 2: Results of derivation model

The merit of these results is the conrmation that the small signal control-to-output transfer

function obtained by the derivation model can also be used to determine a digital compensator in

lieu of using prototype frequency response data. The rst advantage of the derivation model method

is that only the circuit parameters of the proposed LLC resonant converter are required, and no

physical prototype model is needed to obtain the frequency response data. Secondly, compared

to computer simulation software which can also be used to obtain the plant transfer function, the

derivation model requires signicantly less computational power, and is considerably faster in terms

of simulation run-time.

53
6 Conclusions and Future Work
6.1 Summary
In this thesis, the LLC resonant converter topology and the variable frequency control method for

output voltage regulation was discussed in detail.

In Chapter 2, it was determined that the LLC resonant converter is an excellent choice for a

power electronic converter topology to be used in isolated DC-DC conversion applications. The

LLC resonant converter was found to feature high eciency, high power density, and the ability to

operate over a wide range of loading conditions. The LLC resonant converter also has many other

advantageous features including low electromagnetic interference, and soft-switching capabilities.

Chapter 3 discusses the application of a controller to the LLC resonant converter. It was

determined that the preferred control method under nominal loading conditions is variable frequency

control, a method which varies the switching frequency of the converter to regulate the output

voltage. The 2-pole-2-zero compensator was introduced as a possible suitor for a digital control

system, as it can be easily implemented within digital signal processors by using dierence equations.

The stability of continuous and discrete-time control systems was also discussed and the application

of Bode diagrams and Nyquist plots for control system design was explored.

It was then shown in Chapter 4 that by using a combination of laboratory bench measurements,

and computer simulation, that a digital compensator could be designed to very tightly regulate the

output voltage. An algorithm was then presented to implement the voltage control loop in a digital

signal processor.

In Chapter 5, a novel derivation of the small signal control-to-output transfer function was

completed. The model includes the use of the fundamental, third and fth harmonics, and showed

that the higher order harmonics have a signicant contribution to the overall transfer function, and

it should be necessary to include them to capture the true dynamics of the control-to-output transfer

function. The new model also includes higher order sideband frequencies and it was conrmed that

the higher order sideband frequencies are required for modelling the converter for the case(s) where

the magnitude of the modulation index β does not meet the condition |β| << 1.
It was then veried that the small signal control-to-output transfer function developed in the

derivation model could used to design a digital compensator for a digital negative feedback control

system. The simulation results show that an acceptable closed-loop step response and output

voltage regulation was achieved, and had comparable results to the results of Chapter 4.

Finally, it was concluded that the results of Chapter 5 were comparable to the results of Chap-

ter 4 and that the small signal control-to-output transfer function could be obtained using the

derivation model. The advantages of using the derivation model are reduced computational com-

plexity and the diminished requirement for a physical prototype model.

54
6.2 Future Work
There are several areas which can be explored further to improve the modelling of the LLC resonant

converter control-to-output transfer function.

Firstly, development of the model for the low frequency range can be investigated, and can be

achieved by decreasing the value of ωm , and therefore, introducing the case where modulation index
β is large. To calculate large values of β, a dierent method to calculate and obtain the Bessel

function coecient Jn (β) may be required.

Secondly, a more in depth method to describe the rectier model is also needed. As there

are certain loading conditions which cause the LLC resonant converter to go into discontinuous

conduction mode, the linearizion of the rectier circuit may not be valid for all scenarios.

Thirdly, another topic of interest would be to determine a practical method in which synchronous

rectication can be achieved. In addition to an increase in the eciency of the converter, there is

also potential of having bidirectional power ow between the input and output. In the case where

a battery is used to provide DC power at the input, this means the battery could also be charged

by the load without any additional conversion processes.

Fourthly, it was also observed that there was a signicant eect on the control-to-output transfer

function from the output capacitance and its equivalent series resistance. Therefore, a self-tuning

controller has potential to be of great value for the design of controllers for the LLC resonant

converter. It may be able to oset errors in the modelling process that are caused by the tolerances,

the eects of aging capacitance, or the variation in capacitance from operation in environments with

non-ideal temperatures.

Lastly, there have also been several improvements in switching device technology since the be-

ginning of this work. Silicon carbide-based transistors and diodes have been shown many signicant

advantages including lower conduction losses, higher frequency operation, as well as higher operable

temperatures.

55
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58
Appendices
Appendix A: Observation of Stability in Continuous and Discrete-time
domains
A1: Continuous-time domain
To determine the stability and the dynamic characteristics of the closed loop feedback system of

Figure 14, the transfer function of Figure 14 can be described by Equation A-1. Assuming that the

actuator has a gain equal to 1,

G(s)P (s)
T (s) = (A-1)
1 + G(s)P (s)
In the continuous-time domain, the stability of the feedback system is observed on the s-domain

plane. The stability can be determined by evaluating the denominator of Equation A-1, also known

as the characteristic equation. Solving for the roots of the characteristic equation gives the poles

of the system, which are indicators of the system's stability.

A system that contains only poles on the left hand side of the jω axis of the s-domain plane are

considered to be stable, while systems with poles on the right hand side of the jω axis are unstable.

Marginally stable systems have poles on the jω axis.

59
A2: Discrete-time domain
In the discrete-time domain, the stability of the feedback system is observed with respect to the

z-domain unit circle. Stable systems have all poles located inside of the unit circle, while unstable

systems have poles located outside of the unit circle. Finally, marginally stable systems have poles

located on the unit circle.

Figure A-1: Unit circle in the z-domain

60
R simulation schematics
Appendix B: PSIM

Vout

V Iload

A
Vgs1
Vmos1 Vmos3
V MOS1 MOS3
Vds1 Vc
Vgs1 Vgs3
Q1 V
Q3
Ires Ip
A A A Vout_digital
Isec
Vm V
Vtank Vsec
ZOH Vout
V
Vgs3

V
Vds3 Vmos3 Vmos1
Vgs3 Vgs1 MOS2 MOS4
Q2 Q4

Isw

Vmos1

Verror f_s
V
Imos1
V V Vmos1
r
K Error Vctrl K ZOH K sin K Vgs1 Vmos3
V
Vgs3 Imos3
Vmos3
V_ref

R
Figure B-1: PSIM closed loop circuit schematic of LLC resonant converter

Vout
I_o V Iload
A A
Vgs1
Title
V
Vds1 V_Cr Designed by
Vgs1 Vgs3 Revision Page 1 of 1
Q1 V
Q3 A
I_r Ip Isec
A A
Vin
Vtank Vm

I_LM
Vgs3
V
Vds3
Vgs3 Vgs1
Q2 Q4

f
Isw
V
r
K ZOH K sin K Vgs1

Vgs3

R
Figure B-2: PSIM open loop circuit schematic of LLC resonant converter

Title
Designed by
Revision Page 1 of 1

61
R derivation model code
Appendix C: MATLAB
1 clear a l l
2 close a l l
3 clc
4
5 Vg = 48;
6 Kvco = 32779;
7 Tratio = 15/4;
8
9 delta_w = 2 ∗ pi ∗ (Kvco) ∗ 0.02;
10
11 Lm = (80e −6) ∗ ((4/15) ^2) ;
12 Lr = (10e −6)/((15/4) ^2) ;
13 Cr = 9 ∗ 270e − 9;
14 R = 1;
15 Rr = R;
16 Ro = 170/4.6;
17 Rac = ((8 ∗ Tratio ^2)/ pi ^2) ∗Ro;
18
19 res_freq = 1/( sqrt (Lr ∗ Cr) ∗ 2 ∗ pi )
20 w_so = 2 ∗ pi ∗ res_freq ;
21
22 V_s1 = (4/ pi ) ∗Vg;
23 V_s3 = (4/(3 ∗ pi ) ) ∗Vg;
24 V_s5 = (4/(5 ∗ pi ) ) ∗Vg;
25
26 Rc = 0.159;
27 C = 470e − 6;
28 ESRzero = t f ( [ (C∗ Rc) 1 ] , [ 1 ] ) ;
29 [ mag_ESRzero phase_ESRzero ] = bode (ESRzero , logspace (1 ,6 ,200) ) ;
30 mag_ESRzero = squeeze (mag_ESRzero) ;
31 phase_ESRzero = squeeze (phase_ESRzero) ;
32
33 fz = 3100;
34 RHPzero = t f ([ − 1/(2 ∗ pi ∗ fz ) 1 ] , [ 1 ] ) ;
35 [mag_RHPzero phase_RHPzero ] = bode (RHPzero , logspace (1 ,6 ,200) ) ;
36 mag_RHPzero = squeeze (mag_RHPzero) ;
37 phase_RHPzero = squeeze (phase_RHPzero) ;
38
39 T = 1/8000;
40 ZOHpole = t f ([3 ∗ T^2 −24∗T 60] ,[T^3 9 ∗T^2 36 ∗T 60]) ;
41 [ mag_ZOHpole phase_ZOHpole ] = bode (ZOHpole , logspace (1 ,6 ,200) ) ;
42 mag_ZOHpole = squeeze (mag_ZOHpole) ;
43 phase_ZOHpole = squeeze (phase_ZOHpole) ;
44
45 %%%%%%%%fundamental frequency

62
46 a = Cr ∗ Rac ∗Lm;
47 b = Lr ∗ Cr ∗Lm;
48 c = (Cr ∗ Rac ∗Lm)+(Lm∗ Cr ∗ Rr)+(Lr ∗ Cr ∗ Rac) ;
49 d = Lm+(Rr ∗ Cr ∗ Rac) ;
50 e = Rac ;
51
52 %with Rload
53 H_jwso = t f ( [ a ∗ ( i ∗ w_so) ^2] ,[ b ∗ ( i ∗ w_so)^3+c ∗ ( i ∗ w_so)^2+d ∗ ( i ∗ w_so)+e ] ) ;
54 H_jwsoConj = t f ( [ a ∗( − i ∗ w_so) ^2] ,[ b∗( − i ∗ w_so)^3+c ∗( − i ∗ w_so)^2+d∗( − i ∗ w_so)+e ] ) ;
55
56 %with Rload
57 H_jwsoPluswm = t f ( [ a a ∗ 2 ∗ i ∗ w_so −a ∗ w_so^2] ,[ b (b ∗ 3 ∗ i ∗ w_so+c ) (−b ∗ 3 ∗ w_so^2+c ∗ 2 ∗ i ∗ w_so
+d) (e−c ∗ w_so^2−b ∗ i ∗ w_so^3+d ∗ i ∗ w_so) ] ) ;
58 H_jwsoPluswmConj = t f ( [ a a ∗ 2 ∗ i ∗ w_so −a ∗ w_so^2] ,[ − b (−b ∗ 3 ∗ i ∗ w_so+c ) (b ∗ 3 ∗ w_so^2+c ∗ 2 ∗ i
∗ w_so−d) (b ∗ i ∗ w_so^3− c ∗ w_so^2−d ∗ i ∗ w_so+e ) ] ) ;
59
60 %with Rload
61 H_jwsoMinuswm = t f ( [ a −2∗ i ∗ w_so ∗ a −a ∗ w_so^2] ,[ − b (b ∗ 3 ∗ i ∗ w_so+c ) (b ∗ 3 ∗ w_so^2− c ∗ 2 ∗ i ∗
w_so−d) (e−b ∗ j ∗ w_so^3− c ∗ w_so^2+d ∗ i ∗ w_so) ] ) ;
62 H_jwsoMinuswmConj = t f ( [ a −2∗ i ∗ w_so ∗ a −a ∗ w_so^2] ,[ b (−b ∗ 3 ∗ i ∗ w_so+c ) (−b ∗ 3 ∗ w_so^2− c
∗ 2 ∗ i ∗ w_so+d) (e−c ∗ w_so^2+b ∗ i ∗ w_so^3−d ∗ i ∗ w_so) ] ) ;
63
64 %with Rload
65 H_jwsoPlus2wm = t f ([4 ∗ a 4 ∗ a ∗ i ∗ w_so −a ∗ w_so^2] ,[8 ∗ b (12 ∗ b ∗ i ∗ w_so+4∗ c ) (−b ∗ 6 ∗ w_so^2+4∗
i ∗ c ∗ w_so+2∗d) ( e+d ∗ i ∗ w_so−b ∗ i ∗ w_so^3− c ∗ w_so^2) ] ) ;
66 H_jwsoPlus2wmConj = t f ([4 ∗ a 4 ∗ a ∗ i ∗ w_so −a ∗ w_so^2] ,[ − 8 ∗ b ( −12∗ b ∗ i ∗ w_so+4∗ c ) (b ∗ 6 ∗ w_so
^2+4∗ i ∗ w_so ∗ c −2∗d) (b ∗ i ∗ w_so^3− c ∗ w_so^2−d ∗ i ∗ w_so+e ) ] ) ;
67
68 %with Rload
69 H_jwsoMinus2wm = t f ([4 ∗ a −4∗ a ∗ i ∗ w_so −a ∗ w_so^2] ,[ − 8 ∗ b (12 ∗ b ∗ i ∗ w_so+4∗ c ) (6 ∗ b ∗ w_so
^2−4∗ c ∗ i ∗ w_so−2∗d) ( e+d ∗ i ∗ w_so−b ∗ j ∗ w_so^3− c ∗ w_so^2) ] ) ;
70 H_jwsoMinus2wmConj = t f ([4 ∗ a −4∗ a ∗ i ∗ w_so −a ∗ w_so^2] ,[8 ∗ b ( −12∗ b ∗ i ∗ w_so+4∗ c ) ( −6∗ b ∗
w_so^2−4∗ c ∗ i ∗ w_so+2∗d) (e− i ∗ d ∗ w_so−c ∗ w_so^2+b ∗ i ∗ w_so^3) ] ) ;
71
72 %wth Rload
73 H_jwsoPlus3wm = t f ([9 ∗ a 6 ∗ a ∗ i ∗ w_so −a ∗ w_so^2] ,[27 ∗ b (27 ∗ b ∗ i ∗ w_so+9∗ c ) ( −9∗ b ∗ w_so
^2+6∗ c ∗ i ∗ w_so+3∗d) ( e+d ∗ i ∗ w_so−c ∗ w_so^2−b ∗ i ∗ w_so^3) ] ) ;
74 H_jwsoPlus3wmConj = t f ([9 ∗ a 6 ∗ a ∗ i ∗ w_so −a ∗ w_so^2] ,[ − 27 ∗ b ( −27∗ b ∗ i ∗ w_so+9∗ c ) (9 ∗ b ∗
w_so^2+6∗ c ∗ i ∗ w_so−3∗d) (e− i ∗ d ∗ w_so−c ∗ w_so^2+b ∗ i ∗ w_so^3) ] ) ;
75
76 %with Rload
77 H_jwsoMinus3wm = t f ([9 ∗ a −6∗ a ∗ i ∗ w_so −a ∗ w_so^2] ,[ − 27 ∗ b (27 ∗ b ∗ i ∗ w_so+9∗ c ) (9 ∗ b ∗ w_so
^2−6∗ c ∗ i ∗ w_so−3∗d) ( e+d ∗ i ∗ w_so−c ∗ w_so^2−b ∗ i ∗ w_so^3) ] ) ;
78 H_jwsoMinus3wmConj = t f ([9 ∗ a −6∗ a ∗ i ∗ w_so −a ∗ w_so^2] ,[27 ∗ b ( −27∗ b ∗ i ∗ w_so+9∗ c ) ( −9∗ b ∗
w_so^2−6∗ c ∗ i ∗ w_so+3∗d) (e−d ∗ i ∗ w_so−c ∗ w_so^2+b ∗ i ∗ w_so^3) ] ) ;
79
80 beta = t f ( [ delta_w ] ,[ − 1 ∗ i 0]) ;

63
81 [ mag_beta phase_beta wout ] = bode ( beta , logspace (1 ,6 ,200) ) ;
82 mag_beta = squeeze (mag_beta) ;
83 phase_beta = squeeze ( phase_beta ) ;
84
85 %fundamental , sideband 0
86 alpha = 0;
87 J0_1 =b e s s e l j ( alpha , mag_beta) ;
88
89 [mag_H_jwso phase_H_jwso ] = bode (H_jwso , logspace (1 ,6 ,200) ) ;
90 mag_H_jwso = squeeze (mag_H_jwso) ;
91 phase_H_jwso = squeeze (phase_H_jwso) ;
92
93 [ mag_H_jwsoConj phase_H_jwsoConj ] = bode (H_jwsoConj , logspace (1 ,6 ,200) ) ;
94 mag_H_jwsoConj = squeeze (mag_H_jwsoConj) ;
95 phase_H_jwsoConj = squeeze (phase_H_jwsoConj) ;
96
97 Ao_mag = V_s1∗ J0_1. ∗ mag_H_jwso;
98 AoConj_mag = V_s1∗ J0_1. ∗ mag_H_jwsoConj ;
99
100 %fundamental sideband 1
101 alpha1_1 = 1;
102 J1_1 =b e s s e l j ( alpha1_1 , mag_beta) ;
103
104 %plus
105 [mag_H_jwsoPluswm phase_H_jwsoPluswm ] = bode (H_jwsoPluswm , logspace (1 ,6 ,200) ) ;
106 mag_H_jwsoPluswm = squeeze (mag_H_jwsoPluswm) ;
107 phase_H_jwsoPluswm = squeeze (phase_H_jwsoPluswm) ;
108
109 [ mag_H_jwsoPluswmConj phase_H_jwsoPluswmConj ] = bode (H_jwsoPluswmConj , logspace
(1 ,6 ,200) ) ;
110 mag_H_jwsoPluswmConj = squeeze (mag_H_jwsoPluswmConj) ;
111 phase_H_jwsoPluswmConj = squeeze (phase_H_jwsoPluswmConj) ;
112
113 Au_mag = V_s1∗ J1_1. ∗ mag_H_jwsoPluswm;
114 AuConj_mag = V_s1∗ J1_1. ∗ mag_H_jwsoPluswmConj ;
115
116 %minus
117 [mag_H_jwsoMinuswm phase_H_jwsoMinuswm ] = bode (H_jwsoMinuswm , logspace (1 ,6 ,200) ) ;
118 mag_H_jwsoMinuswm = squeeze (mag_H_jwsoMinuswm) ;
119 phase_H_jwsoMinuswm = squeeze (phase_H_jwsoMinuswm) ;
120
121 [ mag_H_jwsoMinuswmConj phase_H_jwsoMinuswmConj ] = bode (H_jwsoMinuswmConj , logspace
(1 ,6 ,200) ) ;
122 mag_H_jwsoMinuswmConj = squeeze (mag_H_jwsoMinuswmConj) ;
123 phase_H_jwsoMinuswmConj = squeeze (phase_H_jwsoMinuswmConj) ;
124
125 Al_mag = −V_s1∗ J1_1. ∗ mag_H_jwsoMinuswm;

64
126 AlConj_mag = −V_s1∗ J1_1. ∗ mag_H_jwsoMinuswmConj ;
127
128 %fundamental , sideband 2
129 alpha2 = 2;
130 J2_1 =b e s s e l j ( alpha2 , mag_beta) ;
131
132 %plus2wm
133 [ mag_H_jwsoPlus2wm phase_H_jwsoPlus2wm ] = bode (H_jwsoPlus2wm , logspace (1 ,6 ,200) ) ;
134 mag_H_jwsoPlus2wm = squeeze (mag_H_jwsoPlus2wm) ;
135 phase_H_jwsoPlus2wm = squeeze (phase_H_jwsoPlus2wm) ;
136
137 [ mag_H_jwsoPlus2wmConj phase_H_jwsoPlus2wmConj ] = bode (H_jwsoPlus2wmConj , logspace
(1 ,6 ,200) ) ;
138 mag_H_jwsoPlus2wmConj = squeeze (mag_H_jwsoPlus2wmConj) ;
139 phase_H_jwsoPlus2wmConj = squeeze (phase_H_jwsoPlus2wmConj) ;
140
141 Au2_mag = V_s1∗ J2_1. ∗ mag_H_jwsoPlus2wm ;
142 Au2Conj_mag = V_s1∗ J2_1. ∗ mag_H_jwsoPlus2wmConj ;
143
144 %minus2wm
145 [mag_H_jwsoMinus2wm phase_H_jwsoMinus2wm ] = bode (H_jwsoMinus2wm , logspace (1 ,6 ,200) ) ;
146 mag_H_jwsoMinus2wm = squeeze (mag_H_jwsoMinus2wm) ;
147 phase_H_jwsoMinus2wm = squeeze (phase_H_jwsoMinus2wm) ;
148
149 [ mag_H_jwsoMinus2wmConj phase_H_jwsoMinus2wmConj ] = bode (H_jwsoMinus2wmConj ,
logspace (1 ,6 ,200) ) ;
150 mag_H_jwsoMinus2wmConj = squeeze (mag_H_jwsoMinus2wmConj) ;
151 phase_H_jwsoMinus2wmConj = squeeze (phase_H_jwsoMinus2wmConj) ;
152
153 Al2_mag = V_s1∗ J2_1. ∗ mag_H_jwsoMinus2wm;
154 Al2Conj_mag = V_s1∗ J2_1. ∗ mag_H_jwsoMinus2wmConj ;
155
156 %fundamental , sideband3
157 alpha3 = 3;
158 J3_1 =b e s s e l j ( alpha3 , mag_beta) ;
159
160 %plus3wm
161 [ mag_H_jwsoPlus3wm phase_H_jwsoPlus3wm ] = bode (H_jwsoPlus3wm , logspace (1 ,6 ,200) ) ;
162 mag_H_jwsoPlus3wm = squeeze (mag_H_jwsoPlus3wm) ;
163 phase_H_jwsoPlus3wm = squeeze (phase_H_jwsoPlus3wm) ;
164
165 [ mag_H_jwsoPlus3wmConj phase_H_jwsoPlus3wmConj ] = bode (H_jwsoPlus3wmConj , logspace
(1 ,6 ,200) ) ;
166 mag_H_jwsoPlus3wmConj = squeeze (mag_H_jwsoPlus3wmConj) ;
167 phase_H_jwsoPlus3wmConj = squeeze (phase_H_jwsoPlus3wmConj) ;
168
169 Au3_mag = V_s1∗ J3_1. ∗ mag_H_jwsoPlus3wm ;

65
170 Au3Conj_mag = V_s1∗ J3_1. ∗ mag_H_jwsoPlus3wmConj ;
171
172 %minus3wm
173 [mag_H_jwsoMinus3wm phase_H_jwsoMinus3wm ] = bode (H_jwsoMinus3wm , logspace (1 ,6 ,200) ) ;
174 mag_H_jwsoMinus3wm = squeeze (mag_H_jwsoMinus3wm) ;
175 phase_H_jwsoMinus3wm = squeeze (phase_H_jwsoMinus3wm) ;
176
177 [ mag_H_jwsoMinus3wmConj phase_H_jwsoMinus3wmConj ] = bode (H_jwsoMinus3wmConj ,
logspace (1 ,6 ,200) ) ;
178 mag_H_jwsoMinus3wmConj = squeeze (mag_H_jwsoMinus3wmConj) ;
179 phase_H_jwsoMinus3wmConj = squeeze (phase_H_jwsoMinus3wmConj) ;
180
181 Al3_mag = V_s1∗ J3_1. ∗ mag_H_jwsoMinus3wm;
182 Al3Conj_mag = V_s1∗ J3_1. ∗ mag_H_jwsoMinus3wmConj ;
183
184 a1 = (Ao_mag. ∗ AlConj_mag)+(Au_mag. ∗ AoConj_mag)+(Al_mag. ∗ Al2Conj_mag)+(Au2_mag. ∗
AuConj_mag) ;
185 a2 = (Ao_mag. ∗ Al2Conj_mag)+(Au_mag. ∗ AlConj_mag)+(Al_mag. ∗ Al3Conj_mag)+(Au2_mag. ∗
AoConj_mag)+(Au3_mag. ∗ AuConj_mag) ;
186 a3 = (Ao_mag. ∗ Al3Conj_mag)+(Au_mag. ∗ Al2Conj_mag)+(Au2_mag. ∗ AlConj_mag)+(Au3_mag. ∗
AoConj_mag) ;
187
188 fundamentalOutput = ( sqrt ((1/3) ∗ ( a1.^2+a2.^2+a3 .^2) ) ) ./(Ao_mag) ;
189 fundamentalOutput = ((1/ delta_w ) ∗ fundamentalOutput ) ;
190
191 %%%%%%%%third harmonic
192
193 %with Rload
194 H_3jwso = t f ( [ a ∗ (3 ∗ i ∗ w_so) ^2] ,[ b ∗ (3 ∗ i ∗ w_so)^3+c ∗ (3 ∗ i ∗ w_so)^2+d ∗ (3 ∗ i ∗ w_so)+e ] ) ;
195 H_3jwsoConj = t f ( [ a ∗( −3∗ i ∗ w_so) ^2] ,[ b ∗( −3∗ i ∗ w_so)^3+c ∗( −3∗ i ∗ w_so)^2+d ∗( −3∗ i ∗ w_so)+e
]) ;
196
197 %with Rload
198 H_3jwsoPluswm = t f ( [ a a ∗ 6 ∗ i ∗ w_so −a ∗ 9 ∗ w_so^2] ,[ b (b ∗ 9 ∗ i ∗ w_so+c ) (−b ∗ 27 ∗ w_so^2+c ∗ 6 ∗ i ∗
w_so+d) (e −9∗ c ∗ w_so^2 −27∗b ∗ i ∗ w_so^3+3∗d ∗ i ∗ w_so) ] ) ;
199 H_3jwsoPluswmConj = t f ( [ a a ∗ 6 ∗ i ∗ w_so −a ∗ 9 ∗ w_so^2] ,[ − b (−b ∗ 9 ∗ i ∗ w_so+c ) (b ∗ 27 ∗ w_so^2+c
∗ 6 ∗ i ∗ w_so−d) (27 ∗ b ∗ i ∗ w_so^3− c ∗ 9 ∗ w_so^2 −3∗ d ∗ i ∗ w_so+e ) ] ) ;
200
201 %with Rload
202 H_3jwsoMinuswm = t f ( [ a −6∗ i ∗ w_so ∗ a −9∗ a ∗ w_so^2] ,[ − b (b ∗ 9 ∗ i ∗ w_so+c ) (b ∗ 27 ∗ w_so^2− c ∗ 6 ∗
i ∗ w_so−d) (e −27∗b ∗ j ∗ w_so^3−9∗ c ∗ w_so^2+3∗d ∗ i ∗ w_so) ] ) ;
203 H_3jwsoMinuswmConj = t f ( [ a −6∗ i ∗ w_so ∗ a −9∗ a ∗ w_so^2] ,[ b (−b ∗ 9 ∗ i ∗ w_so+c ) (−b ∗ 27 ∗ w_so
^2− c ∗ 6 ∗ i ∗ w_so+d) (e−c ∗ 9 ∗ w_so^2+27∗ b ∗ i ∗ w_so^3−3∗d ∗ i ∗ w_so) ] ) ;
204
205 %with Rload
206 H_3jwsoPlus2wm = t f ([4 ∗ a 12 ∗ a ∗ i ∗ w_so −9∗ a ∗ w_so^2] ,[8 ∗ b (36 ∗ b ∗ i ∗ w_so+4∗ c ) (−b ∗ 54 ∗
w_so^2+12∗ i ∗ c ∗ w_so+2∗d) ( e+3∗d ∗ i ∗ w_so−27∗b ∗ i ∗ w_so^3−9∗ c ∗ w_so^2) ] ) ;

66
207 H_3jwsoPlus2wmConj = t f ([4 ∗ a 12 ∗ a ∗ i ∗ w_so −9∗ a ∗ w_so^2] ,[ − 8 ∗ b ( −36∗ b ∗ i ∗ w_so+4∗ c ) (b
∗ 54 ∗ w_so^2+12 ∗ i ∗ w_so ∗ c −2∗d) (27 ∗ b ∗ i ∗ w_so^3 −9∗ c ∗ w_so^2 −3∗ d ∗ i ∗ w_so+e ) ] ) ;
208
209 %with Rload
210 H_3jwsoMinus2wm = t f ([4 ∗ a −12∗ a ∗ i ∗ w_so −9∗ a ∗ w_so^2] ,[ − 8 ∗ b (36 ∗ b ∗ i ∗ w_so+4∗ c ) (54 ∗ b ∗
w_so^2 −12∗ c ∗ i ∗ w_so−2∗d) ( e+3∗d ∗ i ∗ w_so−27∗b ∗ j ∗ w_so^3−9∗ c ∗ w_so^2) ] ) ;
211 H_3jwsoMinus2wmConj = t f ([4 ∗ a −12∗ a ∗ i ∗ w_so −9∗ a ∗ w_so^2] ,[8 ∗ b ( −36∗ b ∗ i ∗ w_so+4∗ c )
( −54∗ b ∗ w_so^2 −12∗ c ∗ i ∗ w_so+2∗d) (e −3∗ i ∗ d ∗ w_so−9∗ c ∗ w_so^2+27∗ b ∗ i ∗ w_so^3) ] ) ;
212
213 %wth Rload
214 H_3jwsoPlus3wm = t f ([9 ∗ a 18 ∗ a ∗ i ∗ w_so −9∗ a ∗ w_so^2] ,[27 ∗ b (81 ∗ b ∗ i ∗ w_so+9∗ c ) ( −81∗ b ∗
w_so^2+18∗ c ∗ i ∗ w_so+3∗d) ( e+3∗d ∗ i ∗ w_so−9∗ c ∗ w_so^2 −27∗b ∗ i ∗ w_so^3) ] ) ;
215 H_3jwsoPlus3wmConj = t f ([9 ∗ a 18 ∗ a ∗ i ∗ w_so −9∗ a ∗ w_so^2] ,[ − 27 ∗ b ( −81∗ b ∗ i ∗ w_so+9∗ c ) (81 ∗
b ∗ w_so^2+18∗ c ∗ i ∗ w_so−3∗d) (e −3∗ i ∗ d ∗ w_so−9∗ c ∗ w_so^2+27∗ b ∗ i ∗ w_so^3) ] ) ;
216
217 %with Rload
218 H_3jwsoMinus3wm = t f ([9 ∗ a −18∗ a ∗ i ∗ w_so −9∗ a ∗ w_so^2] ,[ − 27 ∗ b (81 ∗ b ∗ i ∗ w_so+9∗ c ) (81 ∗ b ∗
w_so^2 −18∗ c ∗ i ∗ w_so−3∗d) ( e+3∗d ∗ i ∗ w_so−9∗ c ∗ w_so^2 −27∗b ∗ i ∗ w_so^3) ] ) ;
219 H_3jwsoMinus3wmConj = t f ([9 ∗ a −18∗ a ∗ i ∗ w_so −9∗ a ∗ w_so^2] ,[27 ∗ b ( −81∗ b ∗ i ∗ w_so+9∗ c )
( −81∗ b ∗ w_so^2 −18∗ c ∗ i ∗ w_so+3∗d) (e −3∗d ∗ i ∗ w_so−9∗ c ∗ w_so^2+27∗ b ∗ i ∗ w_so^3) ] ) ;
220
221 %third Harmonic , sideband 0
222 alpha0_3 = 0;
223 J0_3 = b e s s e l j ( alpha0_3 , mag_beta) ;
224
225 [mag_H_3jwso phase_H_3jwso ] = bode (H_3jwso , logspace (1 ,6 ,200) ) ;
226 mag_H_3jwso = squeeze (mag_H_3jwso) ;
227 phase_H_3jwso = squeeze (phase_H_3jwso) ;
228
229 [ mag_H_3jwsoConj phase_H_3jwsoConj ] = bode (H_3jwsoConj , logspace (1 ,6 ,200) ) ;
230 mag_H_3jwsoConj = squeeze (mag_H_3jwsoConj) ;
231 phase_H_3jwsoConj = squeeze (phase_H_3jwsoConj) ;
232
233 Bo_mag = V_s3∗ J0_3. ∗ mag_H_3jwso;
234 BoConj_mag = V_s3∗ J0_3. ∗ mag_H_3jwsoConj ;
235
236 %thirdHarmonic , sideband1
237 alpha1_3 = 1;
238 J1_3 =b e s s e l j ( alpha1_3 , mag_beta) ;
239
240 %3 plus
241 [ mag_H_3jwsoPluswm phase_H_3jwsoPluswm ] = bode (H_3jwsoPluswm , logspace (1 ,6 ,200) ) ;
242 mag_H_3jwsoPluswm = squeeze (mag_H_3jwsoPluswm) ;
243 phase_H_3jwsoPluswm = squeeze (phase_H_3jwsoPluswm) ;
244
245 [ mag_H_3jwsoPluswmConj phase_H_3jwsoPluswmConj ] = bode (H_3jwsoPluswmConj , logspace
(1 ,6 ,200) ) ;

67
246 mag_H_3jwsoPluswmConj = squeeze (mag_H_3jwsoPluswmConj) ;
247 phase_H_3jwsoPluswmConj = squeeze (phase_H_3jwsoPluswmConj) ;
248
249 Bu_mag = V_s3∗ J1_3. ∗ mag_H_3jwsoPluswm ;
250 BuConj_mag = V_s3∗ J1_3. ∗ mag_H_3jwsoPluswmConj ;
251
252 %3minus
253 [mag_H_3jwsoMinuswm phase_H_3jwsoMinuswm ] = bode (H_3jwsoMinuswm , logspace (1 ,6 ,200) ) ;
254 mag_H_3jwsoMinuswm = squeeze (mag_H_3jwsoMinuswm) ;
255 phase_H_3jwsoMinuswm = squeeze (phase_H_3jwsoMinuswm) ;
256
257 [ mag_H_3jwsoMinuswmConj phase_H_3jwsoMinuswmConj ] = bode (H_3jwsoMinuswmConj ,
logspace (1 ,6 ,200) ) ;
258 mag_H_3jwsoMinuswmConj = squeeze (mag_H_3jwsoMinuswmConj) ;
259 phase_H_3jwsoMinuswmConj = squeeze (phase_H_3jwsoMinuswmConj) ;
260
261 Bl_mag = −V_s3∗ J1_3. ∗ mag_H_3jwsoMinuswm;
262 BlConj_mag = −V_s3∗ J1_3. ∗ mag_H_3jwsoMinuswmConj ;
263
264 %thirdHarmonic , sideband2
265 alpha2_3 = 2;
266 J2_3 =b e s s e l j ( alpha2_3 , mag_beta) ;
267
268 %3 plus2
269 [ mag_H_3jwsoPlus2wm phase_H_3jwsoPlus2wm ] = bode (H_3jwsoPlus2wm , logspace (1 ,6 ,200) ) ;
270 mag_H_3jwsoPlus2wm = squeeze (mag_H_3jwsoPlus2wm) ;
271 phase_H_3jwsoPlus2wm = squeeze (phase_H_3jwsoPlus2wm) ;
272
273 [ mag_H_3jwsoPlus2wmConj phase_H_3jwsoPlus2wmConj ] = bode (H_3jwsoPlus2wmConj ,
logspace (1 ,6 ,200) ) ;
274 mag_H_3jwsoPlus2wmConj = squeeze (mag_H_3jwsoPlus2wmConj) ;
275 phase_H_3jwsoPlus2wmConj = squeeze (phase_H_3jwsoPlus2wmConj) ;
276
277 Bu2_mag = V_s3∗ J2_3. ∗ mag_H_3jwsoPlus2wm ;
278 Bu2Conj_mag = V_s3∗ J2_3. ∗ mag_H_3jwsoPlus2wmConj ;
279
280 %3minus2
281 [mag_H_3jwsoMinus2wm phase_H_3jwsoMinus2wm ] = bode (H_3jwsoMinus2wm , logspace
(1 ,6 ,200) ) ;
282 mag_H_3jwsoMinus2wm = squeeze (mag_H_3jwsoMinus2wm) ;
283 phase_H_3jwsoMinus2wm = squeeze (phase_H_3jwsoMinus2wm) ;
284
285 [ mag_H_3jwsoMinus2wmConj phase_H_3jwsoMinus2wmConj ] = bode (H_3jwsoMinus2wmConj ,
logspace (1 ,6 ,200) ) ;
286 mag_H_3jwsoMinus2wmConj = squeeze (mag_H_3jwsoMinus2wmConj) ;
287 phase_H_3jwsoMinus2wmConj = squeeze (phase_H_3jwsoMinus2wmConj) ;
288

68
289 Bl2_mag = −V_s3∗ J2_3. ∗ mag_H_3jwsoMinus2wm;
290 Bl2Conj_mag = −V_s3∗ J2_3. ∗ mag_H_3jwsoMinus2wmConj ;
291
292 %thridHarmonic , sideband3
293 alpha3_3 = 3;
294 J3_3 =b e s s e l j ( alpha3_3 , mag_beta) ;
295
296 %3 plus3
297 [ mag_H_3jwsoPlus3wm phase_H_3jwsoPlus3wm ] = bode (H_3jwsoPlus3wm , logspace (1 ,6 ,200) ) ;
298 mag_H_3jwsoPlus3wm = squeeze (mag_H_3jwsoPlus3wm) ;
299 phase_H_3jwsoPlus3wm = squeeze (phase_H_3jwsoPlus3wm) ;
300
301 [ mag_H_3jwsoPlus3wmConj phase_H_3jwsoPlus3wmConj ] = bode (H_3jwsoPlus3wmConj ,
logspace (1 ,6 ,200) ) ;
302 mag_H_3jwsoPlus3wmConj = squeeze (mag_H_3jwsoPlus3wmConj) ;
303 phase_H_3jwsoPlus3wmConj = squeeze (phase_H_3jwsoPlus3wmConj) ;
304
305 Bu3_mag = V_s3∗ J3_3. ∗ mag_H_3jwsoPlus3wm ;
306 Bu3Conj_mag = V_s3∗ J3_3. ∗ mag_H_3jwsoPlus3wmConj ;
307
308 %3minus3
309 [mag_H_3jwsoMinus3wm phase_H_3jwsoMinus3wm ] = bode (H_3jwsoMinus3wm , logspace
(1 ,6 ,200) ) ;
310 mag_H_3jwsoMinus3wm = squeeze (mag_H_3jwsoMinus3wm) ;
311 phase_H_3jwsoMinus3wm = squeeze (phase_H_3jwsoMinus3wm) ;
312
313 [ mag_H_3jwsoMinus3wmConj phase_H_3jwsoMinus3wmConj ] = bode (H_3jwsoMinus3wmConj ,
logspace (1 ,6 ,200) ) ;
314 mag_H_3jwsoMinus3wmConj = squeeze (mag_H_3jwsoMinus3wmConj) ;
315 phase_H_3jwsoMinus3wmConj = squeeze (phase_H_3jwsoMinus3wmConj) ;
316
317 Bl3_mag = −V_s3∗ J3_3. ∗ mag_H_3jwsoMinus3wm;
318 Bl3Conj_mag = −V_s3∗ J3_3. ∗ mag_H_3jwsoMinus3wmConj ;
319
320 b1 = (Bo_mag. ∗ BlConj_mag)+(Bu_mag. ∗ BoConj_mag)+(Bl_mag. ∗ Bl2Conj_mag)+(Bu2_mag. ∗
BuConj_mag) ;
321 b2 = (Bo_mag. ∗ Bl2Conj_mag)+(Bu_mag. ∗ BlConj_mag)+(Bl_mag. ∗ Bl3Conj_mag)+(Bu2_mag. ∗
BoConj_mag)+(Bu3_mag. ∗ BuConj_mag) ;
322 b3 = (Bo_mag. ∗ Bl3Conj_mag)+(Bu_mag. ∗ Bl2Conj_mag)+(Bu2_mag. ∗ BlConj_mag)+(Bu3_mag. ∗
BoConj_mag) ;
323
324 thirdHarmonicOutput = ( sqrt ((1/3) ∗ (b1.^2+b2.^2+b3 .^2) ) ) ./(Bo_mag) ;
325 thirdHarmonicOutput = ((1/ delta_w ) ∗ thirdHarmonicOutput ) ;
326
327 %%%%%%%%f i f t h harmonic
328
329 %with Rload

69
330 H_5jwso = t f ( [ a ∗ (5 ∗ i ∗ w_so) ^2] ,[ b ∗ (5 ∗ i ∗ w_so)^3+c ∗ (5 ∗ i ∗ w_so)^2+d ∗ (5 ∗ i ∗ w_so)+e ] ) ;
331 H_5jwsoConj = t f ( [ a ∗( −5∗ i ∗ w_so) ^2] ,[ b ∗( −5∗ i ∗ w_so)^3+c ∗( −5∗ i ∗ w_so)^2+d ∗( −5∗ i ∗ w_so)+e
]) ;
332
333 %with Rload
334 H_5jwsoPluswm = t f ( [ a a ∗ 10 ∗ 1 i ∗ w_so −a ∗ 25 ∗ w_so^2] ,[ b (b ∗ 15 ∗ i ∗ w_so+c ) (−b ∗ 75 ∗ w_so^2+c
∗ 10 ∗ i ∗ w_so+d) (e −25∗ c ∗ w_so^2 − 125 ∗ b ∗ i ∗ w_so^3+5∗ d ∗ i ∗ w_so) ] ) ;
335 H_5jwsoPluswmConj = t f ( [ a a ∗ 10 ∗ i ∗ w_so −a ∗ 25 ∗ w_so^2] ,[ − b (−b ∗ 15 ∗ i ∗ w_so+c ) (b ∗ 75 ∗ w_so
^2+c ∗ 10 ∗ i ∗ w_so−d) (125 ∗ b ∗ i ∗ w_so^3− c ∗ 25 ∗ w_so^2−5∗d ∗ i ∗ w_so+e ) ] ) ;
336
337 %with Rload
338 H_5jwsoMinuswm = t f ( [ a −10∗ i ∗ w_so ∗ a −25∗ a ∗ w_so^2] ,[ − b (b ∗ 15 ∗ i ∗ w_so+c ) (b ∗ 75 ∗ w_so^2− c
∗ 10 ∗ i ∗ w_so−d) (e − 125 ∗ b ∗ j ∗ w_so^3 −25∗ c ∗ w_so^2+5∗ d ∗ i ∗ w_so) ] ) ;
339 H_5jwsoMinuswmConj = t f ( [ a −10∗ i ∗ w_so ∗ a −25∗ a ∗ w_so^2] ,[ b (−b ∗ 15 ∗ i ∗ w_so+c ) (−b ∗ 75 ∗
w_so^2− c ∗ 10 ∗ i ∗ w_so+d) (e−c ∗ 25 ∗ w_so^2+125∗ b ∗ i ∗ w_so^3−5∗d ∗ i ∗ w_so) ] ) ;
340
341 %with Rload
342 H_5jwsoPlus2wm = t f ([4 ∗ a 20 ∗ a ∗ i ∗ w_so −25∗ a ∗ w_so^2] ,[8 ∗ b (60 ∗ b ∗ i ∗ w_so+4∗ c ) (−b ∗ 150 ∗
w_so^2+20∗ i ∗ c ∗ w_so+2∗d) ( e+5∗d ∗ i ∗ w_so−125∗ b ∗ i ∗ w_so^3 −25∗ c ∗ w_so^2) ] ) ;
343 H_5jwsoPlus2wmConj = t f ([4 ∗ a 20 ∗ a ∗ i ∗ w_so −25∗ a ∗ w_so^2] ,[ − 8 ∗ b ( −60∗ b ∗ i ∗ w_so+4∗ c ) (b
∗ 150 ∗ w_so^2+20 ∗ i ∗ w_so ∗ c −2∗d) (125 ∗ b ∗ i ∗ w_so^3 −25∗ c ∗ w_so^2 −5∗ d ∗ i ∗ w_so+e ) ] ) ;
344
345 %with Rload
346 H_5jwsoMinus2wm = t f ([4 ∗ a −20∗ a ∗ i ∗ w_so −25∗ a ∗ w_so^2] ,[ − 8 ∗ b (60 ∗ b ∗ i ∗ w_so+4∗ c ) (150 ∗ b ∗
w_so^2 −20∗ c ∗ i ∗ w_so−2∗d) ( e+5∗d ∗ i ∗ w_so−125∗ b ∗ j ∗ w_so^3 −25∗ c ∗ w_so^2) ] ) ;
347 H_5jwsoMinus2wmConj = t f ([4 ∗ a −20∗ a ∗ i ∗ w_so −25∗ a ∗ w_so^2] ,[8 ∗ b ( −60∗ b ∗ i ∗ w_so+4∗ c )
( − 150 ∗ b ∗ w_so^2 −20∗ c ∗ i ∗ w_so+2∗d) (e −5∗ i ∗ d ∗ w_so−25∗ c ∗ w_so^2+125∗ b ∗ i ∗ w_so^3) ] ) ;
348
349 %wth Rload
350 H_5jwsoPlus3wm = t f ([9 ∗ a 30 ∗ a ∗ i ∗ w_so −25∗ a ∗ w_so^2] ,[27 ∗ b (135 ∗ b ∗ i ∗ w_so+9∗ c ) ( − 225 ∗ b ∗
w_so^2+30∗ c ∗ i ∗ w_so+3∗d) ( e+5∗d ∗ i ∗ w_so−25∗ c ∗ w_so^2 −125∗ b ∗ i ∗ w_so^3) ] ) ;
351 H_5jwsoPlus3wmConj = t f ([9 ∗ a 30 ∗ a ∗ i ∗ w_so −25∗ a ∗ w_so^2] ,[ − 27 ∗ b ( − 135 ∗ b ∗ i ∗ w_so+9∗ c )
(225 ∗ b ∗ w_so^2+30∗ c ∗ i ∗ w_so−3∗d) (e −5∗ i ∗ d ∗ w_so−25∗ c ∗ w_so^2+125∗ b ∗ i ∗ w_so^3) ] ) ;
352
353 %with Rload
354 H_5jwsoMinus3wm = t f ([9 ∗ a −30∗ a ∗ i ∗ w_so −25∗ a ∗ w_so^2] ,[ − 27 ∗ b (135 ∗ b ∗ i ∗ w_so+9∗ c ) (225 ∗
b ∗ w_so^2 −30∗ c ∗ i ∗ w_so−3∗d) ( e+5∗d ∗ i ∗ w_so−25∗ c ∗ w_so^2 −125∗ b ∗ i ∗ w_so^3) ] ) ;
355 H_5jwsoMinus3wmConj = t f ([9 ∗ a −30∗ a ∗ i ∗ w_so −25∗ a ∗ w_so^2] ,[27 ∗ b ( − 135 ∗ b ∗ i ∗ w_so+9∗ c )
( − 225 ∗ b ∗ w_so^2 −30∗ c ∗ i ∗ w_so+3∗d) (e −5∗d ∗ i ∗ w_so−25∗ c ∗ w_so^2+125∗ b ∗ i ∗ w_so^3) ] ) ;
356
357 %fifthHarmonic , sideband0
358 alpha0_5 = 0;
359 J0_5 = b e s s e l j ( alpha0_5 , mag_beta) ;
360
361 [mag_H_5jwso phase_H_5jwso ] = bode (H_5jwso , logspace (1 ,6 ,200) ) ;
362 mag_H_5jwso = squeeze (mag_H_5jwso) ;
363 phase_H_5jwso = squeeze (phase_H_5jwso) ;

70
364
365 [ mag_H_5jwsoConj phase_H_5jwsoConj ] = bode (H_5jwsoConj , logspace (1 ,6 ,200) ) ;
366 mag_H_5jwsoConj = squeeze (mag_H_5jwsoConj) ;
367 phase_H_5jwsoConj = squeeze (phase_H_5jwsoConj) ;
368
369 Co_mag = V_s5∗ J0_5. ∗ mag_H_5jwso;
370 CoConj_mag = V_s5∗ J0_5. ∗ mag_H_5jwsoConj ;
371
372 %fifthHarmonic , sideband1
373 alpha1_5 = 1;
374 J1_5 =b e s s e l j ( alpha1_5 , mag_beta) ;
375
376 %5 plus
377 [ mag_H_5jwsoPluswm phase_H_5jwsoPluswm ] = bode (H_5jwsoPluswm , logspace (1 ,6 ,200) ) ;
378 mag_H_5jwsoPluswm = squeeze (mag_H_5jwsoPluswm) ;
379 phase_H_5jwsoPluswm = squeeze (phase_H_5jwsoPluswm) ;
380
381 [ mag_H_5jwsoPluswmConj phase_H_5jwsoPluswmConj ] = bode (H_5jwsoPluswmConj , logspace
(1 ,6 ,200) ) ;
382 mag_H_5jwsoPluswmConj = squeeze (mag_H_5jwsoPluswmConj) ;
383 phase_H_5jwsoPluswmConj = squeeze (phase_H_5jwsoPluswmConj) ;
384
385 Cu_mag = V_s5∗ J1_5. ∗ mag_H_5jwsoPluswm ;
386 CuConj_mag = V_s5∗ J1_5. ∗ mag_H_5jwsoPluswmConj ;
387
388 %5minus
389 [mag_H_5jwsoMinuswm phase_H_5jwsoMinuswm ] = bode (H_5jwsoMinuswm , logspace (1 ,6 ,200) ) ;
390 mag_H_5jwsoMinuswm = squeeze (mag_H_5jwsoMinuswm) ;
391 phase_H_5jwsoMinuswm = squeeze (phase_H_5jwsoMinuswm) ;
392
393 [ mag_H_5jwsoMinuswmConj phase_H_5jwsoMinuswmConj ] = bode (H_5jwsoMinuswmConj ,
logspace (1 ,6 ,200) ) ;
394 mag_H_5jwsoMinuswmConj = squeeze (mag_H_5jwsoMinuswmConj) ;
395 phase_H_5jwsoMinuswmConj = squeeze (phase_H_5jwsoMinuswmConj) ;
396
397 Cl_mag = −V_s5∗ J1_5. ∗ mag_H_5jwsoMinuswm;
398 ClConj_mag = −V_s5∗ J1_5. ∗ mag_H_5jwsoMinuswmConj ;
399
400 %fifthHarmonic , sideband2
401 alpha2_5 = 2;
402 J2_5 =b e s s e l j ( alpha2_5 , mag_beta) ;
403
404 %5 plus2
405 [ mag_H_5jwsoPlus2wm phase_H_5jwsoPlus2wm ] = bode (H_5jwsoPlus2wm , logspace (1 ,6 ,200) ) ;
406 mag_H_5jwsoPlus2wm = squeeze (mag_H_5jwsoPlus2wm) ;
407 phase_H_5jwsoPlus2wm = squeeze (phase_H_5jwsoPlus2wm) ;
408

71
409 [ mag_H_5jwsoPlus2wmConj phase_H_5jwsoPlus2wmConj ] = bode (H_5jwsoPlus2wmConj ,
logspace (1 ,6 ,200) ) ;
410 mag_H_5jwsoPlus2wmConj = squeeze (mag_H_5jwsoPlus2wmConj) ;
411 phase_H_5jwsoPlus2wmConj = squeeze (phase_H_5jwsoPlus2wmConj) ;
412
413 Cu2_mag = V_s5∗ J2_5. ∗ mag_H_5jwsoPlus2wm ;
414 Cu2Conj_mag = V_s5∗ J2_5. ∗ mag_H_5jwsoPlus2wmConj ;
415
416 %5minus2
417 [mag_H_5jwsoMinus2wm phase_H_5jwsoMinus2wm ] = bode (H_5jwsoMinus2wm , logspace
(1 ,6 ,200) ) ;
418 mag_H_5jwsoMinus2wm = squeeze (mag_H_5jwsoMinus2wm) ;
419 phase_H_5jwsoMinus2wm = squeeze (phase_H_5jwsoMinus2wm) ;
420
421 [ mag_H_5jwsoMinus2wmConj phase_H_5jwsoMinus2wmConj ] = bode (H_5jwsoMinus2wmConj ,
logspace (1 ,6 ,200) ) ;
422 mag_H_5jwsoMinus2wmConj = squeeze (mag_H_5jwsoMinus2wmConj) ;
423 phase_H_5jwsoMinus2wmConj = squeeze (phase_H_5jwsoMinus2wmConj) ;
424
425 Cl2_mag = −V_s5∗ J2_5. ∗ mag_H_5jwsoMinus2wm;
426 Cl2Conj_mag = −V_s5∗ J2_5. ∗ mag_H_5jwsoMinus2wmConj ;
427
428 %fifthHarmonic , sideband3
429 alpha3_5 = 3;
430 J3_5 =b e s s e l j ( alpha3_5 , mag_beta) ;
431
432 %5 plus3
433 [ mag_H_5jwsoPlus3wm phase_H_5jwsoPlus3wm ] = bode (H_5jwsoPlus3wm , logspace (1 ,6 ,200) ) ;
434 mag_H_5jwsoPlus3wm = squeeze (mag_H_5jwsoPlus3wm) ;
435 phase_H_5jwsoPlus3wm = squeeze (phase_H_5jwsoPlus3wm) ;
436
437 [ mag_H_5jwsoPlus3wmConj phase_H_5jwsoPlus3wmConj ] = bode (H_5jwsoPlus3wmConj ,
logspace (1 ,6 ,200) ) ;
438 mag_H_5jwsoPlus3wmConj = squeeze (mag_H_5jwsoPlus3wmConj) ;
439 phase_H_5jwsoPlus3wmConj = squeeze (phase_H_5jwsoPlus3wmConj) ;
440
441 Cu3_mag = V_s5∗ J3_5. ∗ mag_H_5jwsoPlus3wm ;
442 Cu3Conj_mag = V_s5∗ J3_5. ∗ mag_H_5jwsoPlus3wmConj ;
443
444 %5minus3
445 [mag_H_5jwsoMinus3wm phase_H_5jwsoMinus3wm ] = bode (H_5jwsoMinus3wm , logspace
(1 ,6 ,200) ) ;
446 mag_H_5jwsoMinus3wm = squeeze (mag_H_5jwsoMinus3wm) ;
447 phase_H_5jwsoMinus3wm = squeeze (phase_H_5jwsoMinus3wm) ;
448
449 [ mag_H_5jwsoMinus3wmConj phase_H_5jwsoMinus3wmConj ] = bode (H_5jwsoMinus3wmConj ,
logspace (1 ,6 ,200) ) ;

72
450 mag_H_5jwsoMinus3wmConj = squeeze (mag_H_5jwsoMinus3wmConj) ;
451 phase_H_5jwsoMinus3wmConj = squeeze (phase_H_5jwsoMinus3wmConj) ;
452
453 Cl3_mag = −V_s5∗ J3_5. ∗ mag_H_5jwsoMinus3wm;
454 Cl3Conj_mag = −V_s5∗ J3_5. ∗ mag_H_5jwsoMinus3wmConj ;
455
456 c1 = (Co_mag. ∗ ClConj_mag)+(Cu_mag. ∗ CoConj_mag)+(Cl_mag. ∗ Cl2Conj_mag)+(Cu2_mag. ∗
CuConj_mag) ;
457 c2 = (Co_mag. ∗ Cl2Conj_mag)+(Cu_mag. ∗ ClConj_mag)+(Cl_mag. ∗ Cl3Conj_mag)+(Cu2_mag. ∗
CoConj_mag)+(Cu3_mag. ∗ CuConj_mag) ;
458 c3 = (Co_mag. ∗ Cl3Conj_mag)+(Cu_mag. ∗ Cl2Conj_mag)+(Cu2_mag. ∗ ClConj_mag)+(Cu3_mag. ∗
CoConj_mag) ;
459
460 fifthHarmonicOutput = ( sqrt ((1/3) ∗ ( c1.^2+c2.^2+c3 .^2) ) ) ./(Co_mag) ;
461 fifthHarmonicOutput = ((1/ delta_w ) ∗ fifthHarmonicOutput ) ;
462
463
464 finalOutput = ( fundamentalOutput+thirdHarmonicOutput+fifthHarmonicOutput ) ∗ 2 ∗ pi ∗
Tratio . ∗ ( mag_ESRzero) .^1. ∗ (mag_RHPzero) .^2. ∗ (mag_ZOHpole) .^3;
465
466 % plots
467 plota = semilogx (wout/(2 ∗ pi ) ,20 ∗ log10 ( fundamentalOutput ) , 'b ' ) ; hold on ,
468 plotb = semilogx (wout/(2 ∗ pi ) ,20 ∗ log10 ( thirdHarmonicOutput ) , 'g ' ) ; hold on ,
469 plotc = semilogx (wout/(2 ∗ pi ) ,20 ∗ log10 ( fifthHarmonicOutput ) , ' r ' ) ; hold on ,
470 hold on , plotd= semilogx (wout/(2 ∗ pi ) ,20 ∗ log10 ( finalOutput ) , 'k ' )
471 hold on , bode ( [ 0 ] , [ 1 ] , [ 2 ∗ pi ∗ 600 ,2 ∗ pi ∗ 1e4 ] )
472 hold on
473 legend ( [ plota , plotb , plotc , plotd ] )

73
A design methodology for LLC resonant converters
based on inspection of resonant tank currents.
C. Adragna, S. De Simone and C. Spini
STMicroelectronics, via C. Olivetti 2, 20041 Agrate Brianza (MI), (Italy)

Abstract -- This paper presents a simple and accurate design The paper starts with a brief review of the LLC resonant
methodology for LLC resonant converters, based on a semi- converter and its main features, recalls its most significant
empirical approach to model steady-state operation in the “be- operating modes, and provides the general guidelines of the
low-resonance” region. This model is framed in a design strategy
design strategy. The conditions for zero-voltage-switching
that aims to design a converter capable of operating with soft-
switching in the specified input voltage range with a load ranging (ZVS) to occur and no-load operation to be ensured are
from zero up to the maximum specified level. reviewed.
Then the current waveforms for the below-resonance
Index Terms – Large-signal model, LLC resonant converter, operating region are considered, suitable approximations
soft-switching, zero-current switching, zero-voltage switching. based on simple geometrical considerations are made, and the
analysis is carried out, leading to relationships that can be used
I. INTRODUCTION to calculate all the main electrical quantities.
Finally, the design procedure is detailed and a design
Although resonant conversion has been with us for many
example given. The experimental results are compared to the
years, the use of this technique in offline powered equipment
theoretical predictions to validate the approach.
has for a long time been confined to niche applications. Quite
recently, emerging applications, such as flat panel TVs, and
the introduction of new regulations concerning an efficient use II. LLC RESONANT CONVERTER MAIN FEATURES
of energy, are pushing power designers to find increasingly The circuit schematic of an LLC resonant converter in its
efficient ac-dc conversion systems. This has revamped the half-bridge implementation is shown in Figure 1. In this paper
interest in resonant conversion, especially in the so-called we refer to this case in particular but, with obvious adap-
LLC resonant converter that seems to be one of the topologies tations, the results that are provided are entirely applicable to
with the most favorable benefit/drawback ratio. the full-bridge implementation too.
Many design methodologies are available today for this The half-bridge driver switches the two MOSFETs Q1 and
converter. Those based on exact models [1-5] are accurate, but Q2 on and off 180º out-of-phase at the frequency fs. The on-
not simple to handle without sophisticated calculation tools. time of each MOSFET is exactly the same and is slightly
Additionally, it is not easy to frame design constraints and shorter than 50% of the switching period Ts = 1/fs. In fact, a
objectives into the models. small dead-time Td is inserted between the turn-off of either
The methodologies based on first harmonic approximation MOSFET and the turn-on of the other one. This is essential for
(FHA) analysis [6-12] are much simpler to handle but lack the operation of the converter: it ensures that Q1 and Q2 do
accuracy, especially in the so-called below-resonance region, not cross-conduct and allows soft-switching for both of them,
as shown in [13]. This is a problem because the closed-loop that is, zero-voltage switching at turn-on (ZVS). This concept
operating frequency and the tank peak current in that region is clarified in section V.
need to be quite accurately predicted to design the current The resonant tank includes three reactive elements (Cr, Ls
limitation circuitry properly. and Lp) and thus features two resonance frequencies.
In [10], it has been shown how to incorporate the design
constraints related to achieving soft-switching under all
operating conditions, as well as zero-load operation ability, in
an organic design procedure based on the FHA approach.
In this paper, a design procedure based on the same strategy
used in [10] is proposed, but using different mathematical
tools. The core of this procedure is a model of the converter
operating in the below-resonance region, derived from
inspection of the tank current waveforms under a particular
operating mode that is the design target. Figure 1. LLC resonant half-bridge converter

One is related to secondary winding conduction: only Ls is
active, while Lp disappears because there is a constant voltage
across it reflected back from the secondary side; its value is:
1
f R1 = . (1)
2 π Ls Cr
The other resonant frequency corresponds to the condition
of the secondary winding(s) being open. The tank circuit turns
from LLC to LC because Ls and Lp are effectively in series:
1
f R2 = . (2)
2 π (Ls + Lp ) Cr
The following, of course, is true: fR1 > fR2. The separation
between fR1 and fR2 depends on the Lp to Ls ratio: the larger it
is, the further the two frequencies are and vice versa.
Power flow is controlled by the operating frequency fs; Figure 2. Typical waveforms of the LLC resonant half-bridge operated below
normally, a reduced power demand from the load produces a resonance.
frequency rise, while an increased power demand causes a and Cr rings with (Ls + Lp), so that the second resonance
frequency decrease. frequency fR2 appears.
When working at a frequency fs = fR1, the converter is said This is one of the fundamental advantages of the LLC
to operate at resonance; naturally, therefore, operation at resonant converter. In fact, it extends the ZVS range for both
frequencies fs > fR1 is termed above-resonance and in the MOSFETs: at t = Tz, the tank circuit current iR(t) is decaying
frequency region fs < fR1 below-resonance. and would approach zero and reverse before t = Ts/2 if it
This last region is practically limited to a relatively narrow followed the same sinusoid at frequency f = fR1 (see the
range fmin < fs < fR1, with fmin > fR2, to prevent the converter extrapolated black dotted line). This lower frequency sinusoid
from losing soft-switching of the half-bridge leg. In fact, this prevents the tank current from decreasing and then the
is what would happen if fs got too close to fR2. Losing ZVS switched current iR(Ts/2) from reversing before t = Ts/2, which
would cause such adverse effects that the converter’s safety is a necessary condition to achieve ZVS.
would be seriously compromised.
Neglecting power losses, whether the converter operates at, III. GENERAL DESIGN GUIDELINES
above or below resonance depends only on the input voltage
(Vin), the output voltage (Vout) and the transformer turn ratio Assuming the LLC resonant half-bridge is powered by a
a. For the half-bridge, we have specifically: PFC pre-regulator providing a regulated Vin, changes in Vin
are due to either the dynamic response of the PFC stage or to
Vin < 2 a ( Vout + V F ) → Below resonance
abnormal line conditions, such as missing line cycles.
Vin = 2 a ( Vout + V F ) → At resonance (3) In [10] it is pointed out that a good design strategy is:
Vin > 2 a ( Vout + V F ) → Above resonance 1. make the converter work at resonance under nominal
where VF is the estimated voltage drop across each of the input voltage Vinnom (e.g. ≈400 V) to take advantage of
secondary rectifiers. operation at the load-independent point (see [6]);
From the design point of view, since Vin and Vout are 2. use the above-resonance region to handle the PFC’s
specified, it is the selection of the turn ratio a that determines output overvoltage conditions, e.g. resulting from an abrupt
whether the converter operates at, below or above resonance. load decrease;
In these three fundamental operating regions, essentially 3. use the below-resonance region to both handle the PFC’s
related to the input voltage, different operating modes can be output undervoltage conditions (e.g. due to an abrupt increase
seen [3], depending on the load. In this context, we focus on of the load) and provide the converter with the specified hold-
the operating modes occurring at full load in the below- up capability while the line voltage is abnormally low and the
resonance operating region, that is, at the lower end of Vin. resonant converter is delivering the maximum power
The waveforms of a typical below-resonance mode are energized only by the PFC’s output bulk capacitor.
shown in Figure 2. This mode, which is unique to the below- Point 1) of the strategy allows an easy determination of the
resonance region, is a discontinuous conduction mode (DCM), transformer’s turn-ratio a; from (3) we have:
because in the time interval (Tz, Ts/2), no current flows on the Vin nom
a= , (4)
secondary side. 2 ( Vout + V F )
Here the multi-resonant nature of the LLC converter As to point 2) of the strategy, the worst-case scenario occurs
appears: whereas in the interval (0, Tz), where Cr resonates when the load of the LLC resonant converter drops to zero and
with Ls only, the tank current is a sinusoid with a frequency the output overvoltage protection (OVP) of the PFC is tripped.
fR1, in the interval (Tz, Ts/2), both secondary rectifiers are open The converter must then be able to regulate with no load at the

1362
maximum input voltage (Vinmax = PFC’s OVP level) at a Equation (5) can be re-written as:
reasonably specified operating frequency fsmax (that is, not too λ ⎛π 1 f R1 ⎞⎟
high). This is expanded in the next section. = cos⎜ ; (8)
Concerning point 3), when the input voltage is at the 2 a M min ( 1 + λ ) ⎜
⎝
2 1 + λ f co ⎟⎠
minimum specified value (Vinmin) the input current reaches the Expanding the cosine function in MacLaurin series to the
maximum peak and rms values and the switching frequency its second order, the resulting equation can be solved for λ:
minimum value (fsmin); the overcurrent protection circuits have ⎡ 2⎤
to be designed so that the converter is still able to regulate the 1 a M min ⎢ ⎛ f R1 ⎞
λ= 8 − ⎜π ⎟ ⎥ . (9)
output voltage under these conditions, but should trip in case 4 1 − 2 a M min ⎢ ⎜⎝ f max ⎟ ⎥
⎠
⎣ ⎦
of further input current increase. For this, the tank peak
current must be known with a certain degree of accuracy; if Figure 3 shows the most important waveforms during no-
the switching frequency is bottom-limited as an additional load operation. The currents iR(t) and iM(t) are coincident and
overcurrent countermeasure, also fsmin should be quite composed of pieces of sinusoids of frequency fR2. However,
accurately predicted. Unfortunately these operating conditions since it is normally fco >> fR2, they look triangular.
are also those where the FHA-based models are less accurate. It is of practical interest to find their common peak value
Hence the need for a different model, as simple as the FHA- IMco at t = Ts/2. Again from the results provided in [3], and
based ones, but more accurate. after adapting the formula to the notation used in this text, it is
possible to find:
IV. NO-LOAD OPERATION CAPABILITY
Vin max λ2
Typically, the converter is required to regulate the output I Mco = 4 ( 1 + λ ) a 2 M min
2
− . (10)
voltage even under no-load conditions. 4 π f R1 Lp 1+ λ
For any input and output voltage, a frequency region exists
where the LLC resonant converter delivers zero power to the V. ZVS OPERATION CAPABILITY
output. This is called cutoff region and its lowest frequency is For the MOSFETs Q1 and Q2 to operate with ZVS, it is
called cutoff frequency. In [3] it is shown that the cutoff necessary and sufficient that:
frequency is: 1. The switched current IS, that is, the tank current iR(t)
when either MOSFET is switched off, and the fundamental
π 1 1
f co = f R1 , (5) component of the square wave voltage applied to the tank
2 1+ λ ⎡ λ ⎤
cos −1 ⎢ circuit have the same sign. In other words, the tank current has
( )
⎥
⎣2a M 1+ λ ⎦ to lag behind the input voltage; this is often referred to as
with the following parameter definitions: inductive-mode operation. Obviously, if the tank current leads
Lp the applied voltage, we have capacitive-mode operation,
λ= : parallel-to-series inductance ratio; which prevents ZVS.
Ls
2. The tank current lags behind the applied voltage by an
Vout + VF
M = : dc voltage conversion ratio; angle large enough so as not to change sign during the dead-
Vin times Td: in this way, after the rail-to-rail swing, the voltage of
and where a is the transformer turn ratio.
the half-bridge leg midpoint (the node HB in Figure 1) has no
Mathematically, a necessary condition for the cutoff region
oscillations before the other MOSFET is switched on.
to exist is that the argument of the inverse cosine function be
less than unity, that is: 3. The (absolute) value of IS is larger than a minimum value
1 λ ISmin such that the node HB swings rail-to-rail within Td.
M≥ , (6) Note once again that operating in inductive-mode is only
2 a 1+ λ
one necessary condition. This is due to the existence of a
which is the same result found in [6], [10]. parasitic capacitance associated to the node HB, which needs
Physically, cutoff occurs when the voltage developed energy to be completely charged or depleted during Td.
across Lp and reflected to the secondary side is not large
enough to forward bias the secondary rectifiers over an entire
switching cycle. This is essentially what (6) states.
It is intuitive that in a closed-loop regulated converter, the
switching frequency under no-load conditions is equal to the
cutoff frequency. Making sure that the converter is able to
regulate the output voltage at no-load and maximum input
voltage can therefore be translated into solving (5) for λ with
an assigned value for fco = fmax and with:
Vout + V F
M = M min = . (7)
Vin max Figure 3. Typical waveforms of the LLC resonant half-bridge operated with
no load.

1363
To accomplish this task, the energy is obviously taken from This approximation is better when the LLC resonant
that of the resonant tank, which therefore must have an converter operates in DCM (see the timing diagram of Figure
adequate level. This is the physical meaning of points 2 and 3. 5), which is actually the condition we are more interested in:
It is useful to consider the circuit in Figure 4, where the the converter works in this mode both at full-load with
drain-to-source capacitances Coss1, Coss2 of Q1 and Q2, as minimum input voltage and at no-load with maximum input
well as other contributors (the capacitance formed between the voltage. It is possible to show that in CCM operation (that is,
case of the MOSFETs and the heat sink, the transformer’s when |iR(jTs/2)| > |iM(jTs/2)|), this approximation may be not as
intrawinding capacitance, etc.) combined together into CStray, good; however, this condition is of no concern for ZVS
are shown. Note that Coss1 is effectively connected in parallel because it is less critical than DCM [14].
to Coss2 and CStray; they can thus all be conveniently combined The minimum value ISmin that provides a rail-to-rail swing
into a single capacitor CHB connected from HB to ground. of the node HB in a time TT ≤ Td is given by:
Since the same MOSFET is typically used for Q1 and Q2, C
Coss1 = Coss2 = Coss; thereby: I S min = HB Vin . (13)
Td
C HB = 2 Coss + C Stray . (11)
and the actual value of IS must be greater than ISmin under all
Note also that Coss1 and Coss2 are non-linear capacitors, operating conditions.
that is, their value is a function of the drain-to-source voltage;
their time-related equivalent value should be considered [14].
VI. MODELING OPERATION BELOW RESONANCE
If the necessary and sufficient conditions for ZVS to occur
are met, normally the tank current iR(t) does not change much Let us refer again to Figure 2, where the main waveforms of
during Td, and changes even less during the time TT ≤ Td an LLC resonant converter in the below-resonance region are
while the node HB swings. shown. In the time interval (0, Tz), the tank current and the
With good approximation, it is possible to assume: magnetizing current are respectively expressed by:
i R ( t ) ≈ i R ( j Ts 2) = I S , t ∈ ( j Ts 2 , j Ts 2 + Td ), ∀j , (12) I
and then, neglecting the MOSFET switching time at turn-off, i R1 ( t ) = S sin(2π f R1 t − θ1 ) (14)
sin θ1
it is possible to state that CHB is charged/depleted by a
I + IS
constant current source equal to IS. iM 1 ( t ) = − I S + M t (15)
Tz
The secondary current, flowing through the rectifier D1, is:
i D1 ( t ) = a [ i R1 ( t ) − i M 1 ( t )] . (16)
In the interval (Tz, Ts/2), iR(t) = iM(t) (DCM operation) and
they both are described by the equation:
i R 2 ( t ) = i M 2 ( t ) = I A sin (2π f R 2 t − θ 2 ) , (17)
while the secondary current iD1(t) is identically zero. The tank
current iR2(t) looks flat and we now make the fundamental
assumption:
⎛ Ts ⎞ ⎛ Ts ⎞
Figure 4. Reference circuit for analysis of resonant transitions in the LLC i R1 (Tz ) = i M 1 (Tz ) = I M = i R 2 ⎜ ⎟ = iM 2 ⎜ ⎟ = I S , (18)
resonant half-bridge to determine ZVS conditions. ⎝ 2 ⎠ ⎝ 2 ⎠
that is, the tank current IM at t = Tz equals the switched current
I S.
This equality holds true if the peak of the sinusoid (17)
occurs exactly at the midpoint Tx of the interval (Tz, Ts/2):
1⎛ Ts ⎞
Tx = ⎜ Tz + ⎟ . (19)
2⎝ 2 ⎠
In turn, for this to occur, the voltage across the
transformer’s primary winding (Ls + Lp) must be zero at this
point, so the voltage VC across the resonant capacitor Cr,
VC(Tx), must equal the input voltage to the converter Vin. We
use this condition later to finalize the model.
Because of the symmetry of the tank current, it is always:
⎛ Ts ⎞
− i R1 (0) = i R 2 ⎜ ⎟ = I S (20)
⎝ 2 ⎠
regardless of the operating conditions for the converter; the
Figure 5. Detail of resonant transition with ZVS in DCM operation. assumption (19) implies –iR1(0) = iR1(Tz) and, consequently:

1364
1 the tangent function in (30), we get the same result. In the end,
Tz = TR1 (TR1 = 1 f R1 ) . (21)
2 (30) can be rewritten as:
Figure 2 shows that even if the instant Tc when VC = Vin is I ⎡⎛ 2 ⎞T ⎤
Iin = S ⎢⎜ − 1⎟⎟ R1 + 1⎥ (32)
not exactly coincident with Tx, the IM = IS approximation is 2 ⎢
⎣⎝
⎜ π tan ( θ1 ) ⎠ Ts ⎥⎦
still excellent.
Considering (21), (15) and (19) can be rewritten as follows: The simultaneous solution of (28) and (32) provides:
⎛ 4 ⎞ ⎧ ⎛ 2a Iin − Iout ⎞
iM 1 ( t ) = I S ⎜⎜ t − 1⎟⎟ (22) ⎪ fs = ⎜⎜1 − ⎟ f R1
⎟
T ⎪ ⎝ a IS ⎠
⎝ R1 ⎠ ⎨ (33)
1 ⎪tan( θ ) = 2 ⎛⎜1 − a 2 Iin − I S ⎞⎟
Tx = (TR1 + Ts ) . (23) ⎪ 1
π⎝ Iout ⎠
4 ⎩
Concerning (17), another consequence of (18) is: Table 1 shows the most important electrical quantities
I S = I A sin (πf R 2TR1 − θ 2 ) = I A sin(πf R 2Ts − θ 2 ) , (24) useful for the design of the converter that can be derived from
from which it is possible to derive the value of θ2, (28), (32) and (33).
remembering that supplementary angles have the same sine: The voltage VC across the resonant capacitor Cr can be
expressed as:
π ⎛ Ts + TR1 ⎞
θ2 = ⎜ − 1⎟⎟ , (25) ⎧ 1 t
VC (0 ) + ∫0 i R1 (t )dt
T
2 ⎜⎝ TR 2 ⎠ ⎪
⎪
0 ≤ t ≤ 2R1
Cr
VC ( t ) = ⎨ (34)
and that of IA: ⎛T ⎞ 1 t TR1 Ts
∫TR1 2 i R 2 (t )dt
⎪VC ⎜ R1 ⎟ + ≤t ≤
IS ⎪
⎩ ⎝ 2 ⎠ Cr 2 2
IA = , (26)
⎛π Ts − TR1 ⎞ As to the value of VC(Ts/2), on the one hand it is given by:
cos⎜⎜ ⎟
⎝2 TR 2 ⎟⎠ ⎛ Ts ⎞
VC ⎜ ⎟ = VC (0 ) +
1 ⎡ TR1 2
i R1 ( t ) dt + ∫
Ts 2 ⎤
i R 2 ( t ) dt ⎥ , (35)
⎢∫
where TR2 = 1/fR2. ⎝ 2 ⎠ Cr ⎣ 0 TR1 2 ⎦
As to the converter’s dc output current Iout, considering which, by comparison with (29), can be written as:
that each secondary rectifier carries half the total value, it is ⎛ Ts ⎞ Iin
VC ⎜ ⎟ = VC (0 ) + Ts . (36)
possible to write: ⎝ 2 ⎠ Cr
TR1 2
2
Iout = Ts ∫ i D1 ( t ) dt . (27) On the other hand, remembering that VC has a dc value
0 equal to Vin/2, for symmetry the following identity holds true:
Substituting (16) in (27), taking (14) and (22) into ⎛ Ts ⎞ Vin Vin ⎛ Ts ⎞
VC ⎜ ⎟ − = − VC (0 ) → VC ⎜ ⎟ = −VC (0 ) + Vin (37)
consideration and developing the integral, we find: ⎝ 2 ⎠ 2 2 ⎝ 2 ⎠
2a I S TR1 Combining (36) and (37) it is possible to find:
Iout = . (28)
π tan( θ1 ) Ts 1⎛ Iin ⎞
VC (0) = ⎜ Vin − Ts ⎟ (38)
The dc input current Iin can be found by integrating the tank 2⎝ Cr ⎠
current along a switching half-cycle: With this information, (35) is totally defined and can be
⎡ TR1 2 Ts 2 used to calculate the peak voltage on Cr listed in Table 1, as
1
Iin = Ts ⎢∫ i R1 ( t ) dt + ∫ ⎤
i R 2 ( t ) dt ⎥ . (29) well as VC(Tx); after some algebra we find:
⎣ 0 TR1 2 ⎦
Developing the two integrals separately and taking (25) and TABLE 1
(26) into account, after some calculations we find: MAIN ELECTRICAL QUANTITIES
Parameter Value
I ⎡ TR1 T ⎛ π Ts − TR1 ⎞ ⎤
Iin = S ⎢ + R 2 tan⎜⎜ ⎟⎥ . (30) Is
Ts ⎣⎢ π tan( θ1 )
Primary peak current
π ⎝2 TR 2 ⎟⎠ ⎦⎥ sin θ1

2 fs ⎛⎜ 1 ⎞
To find the unknown quantities Ts (fs) and θ1, this equation Primary rms current 2
IS 2 +
f R1 ⎜⎝ sin 2 θ1
− 2⎟
⎟
⎠
should be solved simultaneously with (28), but unfortunately 1 fs ⎛⎜ 1 ⎞
they form a transcendent system that does not have a closed- Q1 and Q2 rms current 2
IS 2 +
f R1 ⎜⎝ sin 2 θ1
− 2⎟
⎟
⎠
form solution. However, in the interval (TR1/2, Ts/2) the tank ⎡ ⎤
1 4 2⎛ −1 ⎛ 2 ⎞⎞
current iR2(t) is maximally flat. It can be approximated by a Secondary peak current aI S ⎢1 + − − ⎜ θ1 + cos ⎜ sin θ1 ⎟ ⎟ ⎥
⎢ sin 2 θ1 π2 π ⎜⎝ ⎝π
⎟
⎠ ⎠⎥
⎣ ⎦
horizontal line (iR2(t) ≈ IS) and the area below the curve by that
aI S fs ⎛⎜ 2 48 − 2π2 ⎞
of a rectangle. Then, the result of the second integral in (30) Secondary rms current (x diode)
2π sin θ1 f R1 ⎜⎝
π −
3
sin 2 θ1 ⎟
⎟
⎠
can be replaced by:
2 aI S fs ⎛⎜ 2 48 − 2π 2 ⎞
Secondary total rms current π − sin 2 θ1 ⎟
⎛ Ts T ⎞ 1
I S ⎜ − R1 ⎟ = I S ( Ts − TR1 ) 2π sin θ1 f R1 ⎜⎝ 3 ⎟
(31) ⎠

⎝ 2 2 ⎠ 2 Vin IS ⎡ ⎛ f R1 ⎞ 2 ⎤
Resonant cap peak voltage + ⎢ π⎜ − 1⎟⎟ + ⎥
2 4π f R1 Cr ⎣⎢ ⎜⎝ fs ⎠ sin θ1 ⎦⎥
Note that if we consider the first-order series expansion of

1365
1⎛ 1 IS ⎞ ZVS under no-load conditions is ensured if the switched
Vc (Tx ) = ⎜Vin + TR1 ⎟⎟ (39) current IMco given by (10) is larger than ISmin given by (13) at
⎜
2⎝ π tan( θ1 ) Cr ⎠ maximum input voltage. Solving for Lp yields:
As previously said, for model consistency, the voltage
Td λ2
VC(Tx) must equal the input voltage Vin; this condition needs Lp ≤ 4 ( 1 + λ ) a 2 M min
2
− (43)
to be fulfilled at the minimum input voltage Vinmin. Then: 4 π f R1 C HB 1+ λ
1 IS Actually, the switched current given by (41) should also be
T R1= Vin min . (40) checked for being greater than ISmin. However, remember that
π tan( θ1 ) Cr
always |IS | = |iR(jTs/2)| ≥ |iM(jTs/2)| as long as the converter
Note that the switched current IS, by virtue of (18), can be works in the inductive region; note also that with the present
expressed as a function of the parallel inductance Lp: design, iM(jTs/2) is nearly constant in the below-resonance
a Vout + V F region and is inversely proportional to frequency in the above-
IS = . (41)
4 Lp f R1 resonance region; thus it takes its minimum value at f = fmax,
where it equals IMco given by (10), by design.
If now we substitute the expression (33) of tan(θ1) and ex-
Therefore, if the value resulting from (42) fulfills (43), the
press Cr in terms of TR1 (fR1) in (40), then solve for IS and
compare the result with (41), a constraint may be found on the IS given by (41) is also larger than ISmin and ZVS is ensured
parallel inductor Lp. Introducing the series-to-parallel induc- throughout the operating range. If (43) is not fulfilled, one or
tance ratio λ and the dc conversion ratio M defined in section more of the following actions can solve the issue:
IV, the required Lp value may be found: a) reduce fsmax; b) increase fR1; c) reduce a; d) reduce CHB.
An Lp value much smaller than the limit given by (43) is
a2 λ (Vout +V F ) not good either: this would imply IS >> ISmin, which would lead
Lp =
( )
2 f R1 4aλ Iin + π 2 a M max − 2λ Iout
. (42)
to higher switching losses at turn-off. Ideally, the optimum
condition is when the value of Lp given by (42) equals the
limit (43). However, since component tolerance must be taken
VII. DISCUSSION OF THE MODEL into account, some margin (10-15 %) is recommended.
The waveforms of Figure 2 and the model derived by their
inspection in the previous section actually refer to a particular VIII. DESIGN PROCEDURE
operating condition, the DCMB2 mode described in [3]. This The proposed design procedure, based on the previous
can be considered a good design choice for the converter when analysis, can be outlined in nine steps, starting from the design
it works at the lower end of its input voltage range and with its specification detailed in Table 2.
maximum or peak load. Step 1 – Calculate the min. and max. dc conversion ratios
There are at least two reasons for this. One is that it is a Mmin, Mmax, and the dc input current Iin at Vin = Vinmin:
reasonable trade-off between a good utilization of the below- Vout Iout
Iin = .
resonance region, and a reasonably safe distance - the entire ηVin min
DCMB1 operating region [3] – from the undesired capacitive Step 2 – Calculate the transformer turn ratio a using (4). Set
operating mode, which takes parameter spread of both the tank VF = 0.6 V for Schottky rectifiers, VF = 0.2 V if synchronous
circuit and the control circuit into consideration. rectification is going to be used.
Another reason is that in the time interval (Tz, Ts/2) where Step 3 – Calculate the parallel-to-series inductance ratio λ
the total primary inductance resonates with the tank capacitor, using (9).
the tank and the magnetizing currents are nearly constant, and Step 4 – Calculate the parallel inductance Lp required for
the induction level inside the magnetic core does not increase maximum model validity using (42).
significantly either. In terms of ∆B, then, the transformer can Step 5 – Check that the value of Lp fulfills the ZVS
be designed as if it was operated at the resonance frequency fR1 condition (43). If not, try either reducing fsmax or increasing fR1
instead of the actual (lower) operating frequency fs. or else reducing a or CHB and go back to Step 4. Adjust one or
The accuracy of the model is expected to be excellent: the more of the above parameters also if Lp is much lower than
approximation concerns just a minor portion of the waveform. the minimum needed for ZVS.
The biggest source of error is probably in the value of Iin, Step 6 – Calculate the value of Ls and Cr:
which depends on a correct estimate of the converter’s effi- Lp 1
ciency η. Experience and comparison with similar designs will Ls = ; Cr = .
help make an estimate as close to reality as possible. λ Ls (2π f R1 )2
CHB is another crucial parameter. However, just the maxi- Step 7 – Calculate the switched current IS at full load and
mum expected value needs to be estimated and, again, experi- minimum input voltage from (41).
ence and comparison with similar designs will be a guide. Step 8 – Calculate the operating frequency at full load and
Equation (42) provides the value of the parallel inductor Lp minimum input voltage fsmin = fs and the tank current dis-
that makes the converter operate in the desired DCMB2 mode placement angle θ1 from (33).
and provides no-load operation capability. This Lp value, Step 9 – Calculate all the tank circuit’s electrical quantities
however, must be such that ZVS is ensured as well. using the relationships in Table 1.

1366
TABLE 2 X. CONCLUSIONS
DESIGN SPECIFICATION OF THE EXEMPLARY LLC CONVERTER
Parameter Symbol Value Unit The LLC resonant converter has been analyzed in a well-
Input voltage range Vinmin - Vinmax 320 - 430 V defined below-resonance operating condition with a semi-em-
Nominal input voltage Vinnom 390 V pirical approach based on inspection of the tank current wave-
Regulated output voltage Vout 36 V forms. This has lead to a simple yet accurate design-oriented
Maximum (peak) output current Iout 8.5 A model and to a simple step-by-step design procedure that
Resonance frequency fR1 120 kHz
ensures stable operation at no load, ZVS under all operating
Maximum operating frequency fsmax 200 kHz
Expected efficiency (@ Vinmin) η 95 % conditions, and optimum operation under nominal conditions.
Parasitic capacitance of node HB (max.) CHB 200 pF The validity of the approach and the points that need more
Dead time of driver circuit (min.) Td 200 ns attention in the design procedure have been discussed.
To validate the model, a converter has been designed fol-
IX. EXPERIMENTAL VERIFICATION lowing the proposed step-by-step procedure and a prototype
An LLC resonant half-bridge based on the electrical speci- built and evaluated on the bench. This has shown that the
fication given in Table 2 has been designed using the proce- theoretical predictions match the experimental results very
dure previously outlined, and a prototype has been built and well, thus proving the accuracy of the model.
evaluated on the bench.
The resonant-tank parameters, as well as the converter’s REFERENCES
operating conditions @ Vin = 320 V dc, Iout = 8.5 A resulting [1] H. Jiang; G. Maggetto: Identification of Steady-State Operational Modes
from the design procedure are listed in Table 3, where actual of the Series Resonant DC–DC Converter Based on Loosely Coupled
values and bench measurements are shown too. Notice that the Transformers in Below-Resonance Operation, IEEE transactions on
measured values match the calculated ones very well. Power Electronics, Vol. 14, No. 2, March 1999 Pages 359 – 371
[2] H. Jiang; G. Maggetto; P. Lataire: Steady-State Analysis of the Series
The oscilloscope picture in Figure 6 shows some significant Resonant DC–DC Converter in Conjunction with Loosely Coupled
waveforms of the converter’s operation under the same Vin Transformer—Above Resonance Operation, IEEE transactions on Power
and Iout conditions. Electronics, Vol. 14, No. 3, May 1999 Pages 469 – 480
[3] J.F. Lazar; R. Martinelli: Steady-state Analysis of the LLC Resonant
TABLE 3 Converter, Applied Power Electronics Conference and Exposition, 2001.
RESONANT TANK PARAMETERS AND OPERATING CONDITIONS OF THE APEC 2001. Pages: 728 – 735
CONVERTER SPECIFIED IN TABLE 2 [4] H. de Groot; E. Janssen; R. Pagano; K. Schetters: Design of a 1 MHz
Parameter (Symbol) Calculated Measured Unit LLC Resonant Converter based on a DSP-driven SOI Half-Bridge
Parallel resonant inductance (Lp) 305 296 µH Power MOS Module, Power Electronics Specialists Conference, 2006.
Series resonant inductance (Ls) 56.3 54 µH PESC '06. 37th IEEE 18-22 June 2006 Page(s):1 – 14
[5] T. Liu; Z. Zhou; A. Xiong; J. Zeng; J. Ying: A novel Precise Design
Primary-to-secondary turns ratio (a) 5.783 23/4=5.75 ---
Method for LLC Series Resonant Converter, Telecommunications En-
Resonant capacitance (Cr) 31.3 33 nF ergy Conference, 2006. INTELEC '06. 28th Annual International Sept.
Resonance frequency (fR1) 120 119.2 kHz 2006 Page(s):1 – 6
Min. switching frequency (fs) 80.7 80.6 kHz [6] T. Duerbaum: First harmonic approximation including design con-
Max. switching frequency (fs) 200 202.4 kHz straints, Telecommunications Energy Conference, 1998. INTELEC.
Peak primary current (Ippk) 3.96 3.92 A Pages: 321 – 328
Switched current (IS) 1.37 1.33 A [7] M.B. Borage; S.R. Tiwari; S. Kotaiah: Design Optimization for an LCL-
Type Series Resonant Converter, www.powerpulse.net
Tank current phase angle (θ1) 20.3 19.1 Deg
[8] G. Ivensky; S. Bronstein; S. Ben-Yaakov: Approximate analysis of the
Resonant capacitor peak voltage (VCpk) 362.3 360 V Resonant LCL Converter, 23rd IEEE Israel Convention, Tel-Aviv 2004,
Pages 44 - 48
[9] B. Lu; W. Liu; Y. Liang; Lee, F.C.; van Wyk, J.D.: Optimal design
methodology for LLC resonant converter Applied Power Electronics
Conference and Exposition, 2006. APEC '06. Twenty-First Annual IEEE
19-23 March 2006. Pages: 533 – 538
[10] S. De Simone; C. Adragna; C. Spini; G. Gattavari: Design-oriented
steady-state analysis of LLC resonant converters based on FHA, Power
Electronics, Electrical Drives, Automation and Motion, 2006.
SPEEDAM 2006. International Symposium, May, 23rd - 26th, 2006
Page(s):200 – 207
[11] H. Choi: Analysis and Design of LLC Resonant Converter with Inte-
grated Transformer, Applied Power Electronics Conference, APEC
2007 - Twenty Second Annual IEEE Feb. 2007 Page(s):1630 – 1635
[12] Y. Fang; D. Xu; Y. Zhang; F. Gao; L. Zhu: Design of High Power
Density LLC Resonant Converter with Extra Wide Input Range, Applied
Power Electronics Conference, APEC 2007 - Twenty Second Annual
IEEE Feb. 2007 Page(s):976 - 981
[13] B. Yang: Topology Investigation for Front End DC/DC Power Conver-
sion for Distributed Power System, PhD dissertation, Virginia Poly-
technic Institute and State University, 2003
Figure 6. Main waveforms taken on a prototype of the LLC converter speci- [14] An Introduction to LLC resonant Half-bridge converters, AN2644,
fied in Table 2 @ Vin = 320 V dc, Iout = 8.5 A. www.st.com.

1367
Analysis and Design of LLC Resonant Converter
with Integrated Transformer
Hangseok Choi
Fairchild Semiconductor
82-3, Dodang-dong, Wonmi-gu
Bucheon-si, Gyeonggi-do, Korea

Abstract- LLC resonant converter has a lot of advantages over buck mode operation as well as on the boost mode operation,
the conventional series resonant converter and parallel resonant but no design consideration was given. References [8-12]
converter; narrow frequency variation over wide load and input
variation, Zero Voltage Switching (ZVS) for entire load range and investigated LLC topology in detail using fundamental
integration of magnetic components. This paper presents analysis approximation, but simplified the AC equivalent circuit by
and design consideration for half-bridge LLC resonant converter ignoring the leakage inductance in the secondary side. In
with integrated transformer. Using the fundamental general, the magnetic components of the LLC resonant
approximation, the gain equation is obtained, where the leakage converter are implemented with one core by utilizing the
inductance in the transformer secondary side is also considered.
Based on the gain equation, the practical design procedure is leakage inductance as the resonant inductor and consequently
investigated to optimize the resonant network for a given the leakage inductance exists not only in the primary side but
input/output specifications. The analysis and design procedure also in the secondary side. Since the leakage inductance in the
are verified through an experimental prototype converter. secondary side affects the gain equation, ignoring the leakage
inductance in the secondary side results in incorrect design.
I. INTRODUCTION This paper presents design consideration for half bridge LLC
The Conventional PWM technique processes power by resonant converter. Using the fundamental approximation, the
controlling the duty cycle and interrupting the power flow. All gain equation is obtained, where the leakage inductance in the
the switching devices are hard-switched with abrupt change of transformer secondary side is also considered. Based on the
currents and voltages, which results in severe switching losses gain equation, the practical design procedure is investigated to
and noises. Meanwhile, the resonant switching technique optimize the resonant network for a given input/output
process power in a sinusoidal form and the switching devices specifications. The design procedure is verified through an
are softly commutated. Therefore, the switching losses and experimental prototype converter of 120W half-bridge LLC
noises can be dramatically reduced. This also allows the resonant converter.
reduction of the passive component size by increasing the
switching frequency. For this reason, resonant converters have
drawn a lot of attentions in various applications [1-3]. Among II. OPERATION PRINCIPLES AND FUNDAMENTAL
many resonant converters, half-bridge LLC-type series- APPROXIMATION
resonant converter has been the most popular topology for
many applications since this topology has many advantages Fig. 1 shows the simplified schematic of half-bridge LLC
over other topologies; it can regulate the output over wide line resonant converter. The magnetic components are integrated
and load variations with a relatively small variation of into a transformer; L, is the magnetizing inductance and Llkp
switching frequency, it can achieve zero voltage switching and Llk, are the leakage inductances in the primary and
(ZVS) over the entire operating range, the magnetic secondary, respectively. Fig. 2 shows the typical waveforms of
components can be integrated into a transformer and all LLC resonant converter. Operation of the LLC resonant
essential parasitic elements, including junction capacitances of converter is similar as that of the conventional LC series
all semi-conductor devices, are utilized to achieve ZVS. resonant converter. The only difference is that the value of the
While a lot of researches have been done on the LLC magnetizing inductance is relatively small and therefore the
resonant converter topology ever since this topology was first resonance between Lm+Llkp and Cr affects the converter
introduced in 1990's [4], most of the researches have focused operation. Since the magnetizing inductor is relatively small,
on the steady state analysis rather than practical design there exists considerable amount of magnetizing current (I).
consideration. In [5], the low noise features were mainly In general, the LLC resonant topology consists of three
investigated and no design procedure was studied. Reference stages as shown in Fig. 1; square wave generator, resonant
[6] discussed the above resonance operation in buck mode only, network and rectifier network.
where LLC topology was introduced as "LCL type series
resonant converter." In [7], detailed analysis was done on the

1-4244-0714-1/07/$20.00 C 2007 IEEE. 1630

The square wave generator produces a square wave voltage, The filtering action of the resonant network allows the classical
Vd by driving switches, Ql and Q2 with alternating 50% fundamental approximation to obtain the voltage gain of the
duty cycle for each switch. The square wave generator resonant converter, which assumes that only the fundamental
stage can be built as a full-bridge or half bridge type. component of the square-wave voltage input to the resonant
network contributes to the power transfer to the output.
-The resonant network consists of capacitor and leakage Because the rectifier circuit in the secondary side acts as an
inductances and magnetizing inductance of the transformer. impedance transformer, the equivalent load resistance is
The resonant network has an effect of filtering the higher different from actual load resistance. Fig. 3 shows how this
harmonic currents. Thus, essentially only sinusoidal current equivalent load resistance is derived. The primary side circuit
is allowed to flow through the resonant network even is replaced by a sinusoidal current source, Iac and a square
though square wave voltage is applied to the resonant wave of voltage, VRO appears at the input to the rectifier. Since
network. The current is lagging the voltage applied to the harmonic components of VRO are not involved in the power
resonant network (that is, the fundamental component of transfer, AC equivalent load resistance can be calculated by
the square wave applied by the half-bridge totem pole), dividing the fundamental component of VRO by Iac as
which allows the MOSFETs to be turned on with zero
voltage. As can be seen in Fig. 2, the MOSFET turns on
VF 817 8R
RIa
= ac
R = 2 -= i2 RO(2)
while the current is flowing through the anti-parallel diode
and the voltage across the MOSFET is zero.
- The rectifier network produces DC voltage by rectifying the By using the equivalent load resistance, the AC equivalent
AC current with a capacitor. The rectifier network can be circuit is obtained as illustrated in Fig. 4.
implemented as a full-wave bridge or center-tapped
configuration with capacitive output filter. ac _pk _I
No No

Square wave generator

resonant network Rectifier network VO

ac 'ac 2 (wt)
VROF VR F 7-i
Figure 1. A schematic of half-bridge LLC resonant converter
vigureDrivtio ofequvalnt
3.RO v VRO Ss
i e
n(wt)

Figure 3. Derivation of equivalent Load resistance Rac

Vi _ I

n=NI/N
p s

v F
VROF
in

Figure 2. Typical waveforms of half-bridge LLC resonant converter Figure 4. AC equivalent circuit for LLC resonant converter

1631
With the equivalent load resistance obtained in (2), the m +Likp
characteristics of the LLC resonant converter can be derived. m@ co=c L. +n2LIks
L - L+L
k+l
(8)
Using the AC equivalent circuit of Fig. 4, the voltage gain is L L k
obtained as
As observed in Fig. 5, the LLC resonant converter shows
M= 2n.-Vo (i)21LR 0C (3) nearly load independent characteristics when the switching
frequency is around the resonant frequency. This is a
jco.(I- ).(L +nL distinctive advantage of LLC-type resonant converter over
COO COP
conventional series-resonant converter. Therefore, it is natural
where to operate the converter around the resonant frequency to
minimize the switching frequency variation at light load
8n2
condition.
z
Lp Lm + Llkp Lr = Llkp + Lm HI(n2LlkS) LLC resonant Converter
1 1 p fo
V'L LlPC,~ 2.0

As can be seen in (3), there are two resonant frequencies. 1.8

One is determined by Lr and Cr while the other is determined
by Lp and Cr. In actual transformer, Lp and Lr can be measured 1.6
in the primary side with the secondary side winding open
circuited and short circuited, respectively. 1.4
Important feature that should be observed in (3) is that the .Fl
gain is fixed at resonant frequency (wo) regardless of the load 1.2
variation, which is given as
M _ L. _Lm+n2LIks (4)
1.0

@Co=co Lp Lr Lm
0.8
Without considering the leakage inductance in the
transformer secondary side, the gain in (4) becomes unity. In 0.6
40 50 60 70 80 90 100 110 120 130 140
the previous research, the leakage inductance in the freq (kHz)
transformer secondary side was ignored to simplify the gain
equation [7-12]. However, as observed, there exists Figure 5. Typical gain curves of LLC resonant converter
considerable error when ignoring the leakage inductance in the
transformer secondary side, which generally results in non The operation range of LLC resonant converter is
optimized design. determined by the available peak voltage gain. As shown in
By assuming that Llkp=n2Ljks, the gain in (2) can be Fig. 5, higher peak gain is obtained as Q decreases (as load
simplified as decreases). Another important factor that determines the peak
co2 k gain is the ratio between Lm and Llk which is defined as k in
M (- 2)
k+1 (5) (5). Even though the peak gain at a given condition can be
2n VO obtained by using the gain in (4), it is difficult to express the
Vin co
Q (k + )2+(1 2t
2

A ) (1- peak gain in explicit form. Moreover, the gain obtained from
COOhCOO2e2k+1 lo (4) has some error at frequencies below the resonant frequency
where (fo) due to the fundamental approximation. In order to simplify
the analysis and design, the peak gains are obtained using
k= m t0) simulation tool and depicted in Fig. 6, which shows how the
Llkp
gain varies with Q for different k values. It appears that higher
Q Lr I Cr (7) peak gain can be obtained by reducing k or Q values. With a
R ac
given resonant frequency (f,), decreasing k or Q means
reducing the magnetizing inductance, which results in
The equation (4) is plotted in Fig. 5 for different Q values increased circulating current. Accordingly, there is a trade-off
with k=5 and f=lIOOkHz. The gain at the resonant frequency between the available gain range and conduction loss.
(w0) is also simplified in terms of k as

1632
the proper Q and k values can be obtained from Fig. 6. Even
though higher gain is obtained with small k, too small k value
2.4
results in poor coupling of the transformer. It is typical to set k
to be 5-10, which results in a gain of 1.1-1.2 at the resonant
2.2 frequency.
The value of k affects the losses of the converter. The major
portion of the conduction loss is caused by the magnetizing
2.0
current whose peak value is given by
k=1.5
eM 1.8 I pk nV0 T (8)
k=1.75 m L4
The value of k also affects the switching loss. Since the turn-
0, 1.6 on switching loss is removed by zero voltage switching, the
k=2.5 turn-off switching loss is dominant. The turn off switching loss
1.4 k=3 is proportional to the turn-off current, which is same as the
peak magnetizing current of (8). Therefore, magnetizing
k=4 current should be minimized for high efficiency.
k=5
1.2
k=7
k=9
I M|
0.2 0.4 0.6 0.8 1 1.2 1.4
Q / sm,,..---~~-~~~~-- ,, / ---- --'--"--
Figure 6. Peak gain versus Q for different k values
...---- X X X , . - .

III. DESIGN CONSIDERATION L \A XII)fIQ

Based on the previous analysis, the practical design
procedure is presented in this section. It discusses optimizing
the resonant network for a given input/output specifications.
(1) Operation mode: While the conventional LC series
resonant converter always operates at a frequency above the ID
resonant frequency, LLC resonant converter can operate at
frequency below or above the resonance frequency. Fig 8
shows the waveforms of the currents in the transformer Figure 7. Waveforms of current in the transformer primary side and secondary
primary side and secondary side. As can be observed, sides for difference operation modes
operation below the resonant frequency (case I) allows the soft
commutation of the rectifier diodes in the secondary side while IV. EXPERIMENTAL RESULTS
the circulating current is relatively large. Meanwhile, operation
above the resonant frequency (case II) allows the circulating In order to show validity of the previous analysis and design
current to be minimized, but the rectifier diodes are not softly consideration, an experimental prototype converter of 120W
commutated. Thus, below resonance operation is preferred for half-bridge LLC resonant converter has been built and tested.
high output voltage application where reverse recovery loss in The schematic of the converter and circuit components are
the rectifier diode is severe. On the other hand, above shown in Fig. 8. The input voltage is 220Vac-270Vac and the
resonance operation can show better efficiency for application output is 24V/5A. In terms of DC voltage, the input voltage is
where the output voltage is low and schottky diodes are 260-380V considering holdup time.
available for the secondary side rectifiers since the conduction The ratio (k) between L, and Llkp is determined as 6.5, which
loss is minimized. results in the gain at the resonant frequency as
(2) Maximum Gain: The operation range of LLC resonant
converter is determined by the available peak voltage gain.
M O - =
k= k = 1.15 (9)
Since the peak gain takes place when the converter operates at As observed in the previous analysis, there is a trade-off
the boundary of zero voltage switching (ZVS) and zero current between the available gain range and conduction loss. Since
switching (ZCS) mode, ZVS condition is lost at the maximum the input voltage varies over wide range, if the converter is
gain condition [12]. Therefore, some margin is required when designed to operate only at below resonance frequencies, the
determining the maximum gain. Based on the maximum gain, excessive circulating current can deteriorate the efficiency.

1633
---

Core: EER3541
Np=54T (0.12x 30, Litz wire)
Nsl=Ns2=7T (O.lx 100, Litz wire)
Sectional winding
Lp=800uH (Measured with secondary side open),
Lr-200uH (Measured with secondary side short)

vv
FI Llkpi7. uRotil
N Ns
_R
lLmc.
713iH N
L
----- -
D2 CFRF
FYP201ODN
KA431

Figure.8 Schematic of half-b:)ridge LLC resonant converter

Thus, the converter is designed to operate above resonance at

high input voltage condition and below resonance at low input By selecting the resonant frequency as 85kHz, the resonant
network is determined as L=713uH, Lwk=107uH (Lp=800uH,
voltage to minimize the conduction loss caused by circulating
current. The minimum gain at full load is determined as 1.0. Lr=200uH) and C= 1 8nF The transformer is implemented with
a sectional stacking method to increase the leakage inductance
With the minimum gain, the transformer turn ratio is obtained
as depicted in Fig. 8.
as
N 'Vin max22
M mm66_ 1380/2 76 Fig. 10 and 11 show the operation waveforms for full load
P= - _0 condition with input voltage of 22IVac and 270Vac,
NS (VO +VF) (24+0.8) respectively. Fig. 12 and 13 show the operation waveforms for
where VF is the diode forward voltage drop. no load condition with input voltage of 220Vac and 270Vac,
The maximum gain to cover the input voltage variation is respectively. As can be seen, ZVS is achieved for entire
380/260=1.46. With 10% margin, maximum gain of 1.6 is input/output range.
required. From the gain curves in Fig 9, Q is obtained as 0.4. Fig. 14 shows the measured efficiency. As expected,
efficiency decreases for low input voltage condition due to the
2.0 increased circulating current.

._F.
CM 1.8

00
; 1.6

1.4 k v V-^; -k=3

k=4
1.2
-J^r
~ ^~~;k=5
k=9

Meaur gat dr~iv(

fe )P:enC3 C3PDai
signal P40V/div tC), vltg (2 /dv
0.2 0.4 0.6 0.8 1 1.2 1.4

Q
Figure 9. Design gain curves
C4: Drain current (|AIdiv)

1634
94%

92%

90%

- 88%

L 86%
-
-1-22OVac 25OVac 27OVac
84%

Measure Pl:freq@W(Cl P2mean(C3) P3:--- PCnpoInts(C4) P5.--- P6;--- P7 --- P8o---

value 11:12.41 49 kHz
status v

80%
0. OW 20.OW 40. OW 60. OW 80. OW 100. OW 120.OW
Figure 11. Operation waveforms: 27OVac input and full load
Output Power
Cl: gate drive signal (20V/div), C3: Drain voltage (200V/div)
C4: Drain current (lA/div) Figure 14. Measured efficiency

V. CONCLUSION

This paper has presented design consideration for LLC

resonant converter with integrated transformer, which utilizes
the leakage inductances and magnetizing inductance of
transformer as resonant components. The leakage inductance in
the transformer secondary side was also considered in the gain
equation. The design procedure was verified through
experimental results.

Measure Plfreq@W(Ci1) P2 mean(C3 PCnpbnts(C4)

P3M4--- P5.- - P6.--- P8O-- P7
value 62.25172 kHz
status
REFERENCES
Figure 12. Operation waveforms: 22OVac input and no load [1] Robert L. Steigerwald, "A Comparison of Half-bridge resonant converter
Cl: gate drive signal (20V/div), C3: Drain voltage (200V/div) topologies", IEEE Transactions on Power Electronics, Vol. 3, No. 2,
C4: Drain current (lA/div) April 1988.
[2] A. F. Witulski and R. W. Erickson, "Design of the series resonant converter
for minimum stress," IEEE Transactions on Aerosp. Electron. Syst., Vol.
AES-22, pp. 356-363, July 1986
[3] Y. G. Kang, A. K. Upadhyay, D. L. Stephens, "Analysis and design of a
half-bridge parallel resonant converter operating above resonance," IEEE
Transactions on Industry Applications Vol. 27, March-April 1991 pp.
386- 395
[4] Yasuhito Furukawa, Kouichi Morita, Taketoshi Yoshikawa "A High
Efficiency 150W DC/DC Converter" Intelec 1994, pp.148-153
[5] Koichi Morita "Novel Ultra Low-noise Soft switch-mode Power Supply",
Intelec 1998, pp.115-122
[6] Ashoka K. S. Bhat, "Analysis and Design of LCL-Type Series Resonant
Converter", IEEE Transactions on Industrial Electronics, Vol. 41, No. 1,
Feb. 1994.
[7] J. F. Lazar and R. Martineli "Steady-state analysis of the LLC series
resonant converter, APEC 2001, 728-735
Fiur 13. Oprto waeom .7 a inu and no loa
[8] Yan Liang, Wenduo Liu, Bing Lu, van Wyk, J.D, " Design of integrated
,a
passive component for a 1 MHz 1 kW half-bridge LLC resonant
converter", IAS 2005, pp. 2223-2228
[9] B. Yang, F.C. Lee, M. Concannon,"Over current protection methods for
LLC resonant converter" APEC 2003, pp. 605 - 609
[10] Yilei Gu, Zhengyu Lu, Lijun Hang, Zhaoming Qian, Guisong Huang,
Cl: gate drive signal (20V/div), C3: Drain voltage (200V/div)
"Three-level LLC series resonant DC/DC converter" IEEE Transactions
C4: Drain current (IAIdiv)
on Power Electronics Vol.20, July 2005, pp.781 - 789
[11] Bo Yang, Lee, F.C, A.J Zhang, Guisong Huang, "LLC resonant converter
for front end DC/DC conversion" APEC 2002. pp. 1 108 - 1112
[12] Bing Lu, Wenduo Liu, Yan Liang, Fred C. Lee, Jacobus D. Van Wyk,
"Optimal design methology for LLC Resonant Converter," APEC 2006.
pp.533-538

1635

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Introduction To LLC Resonant Converters (PDFDrive)

Uploaded by

Introduction To LLC Resonant Converters (PDFDrive)

Uploaded by

Introduction to LLC resonant

LLC resonant converter training, Brno 2012

2 LLC resonant converter training. Brno 2012

Korea e-Standby program[8]

3 LLC resonant converter training. Brno 2012

Set-Top Boxes (STB)

5 LLC resonant converter training. Brno 2012

- Significant portion of energy is lost during power conversion and

- Conversion efficiency has to be increased and no-load consumption

- Energy agencies releasing various national programs that define

6 LLC resonant converter training. Brno 2012

7 LLC resonant converter training. Brno 2012

Lower Upper Complementary

8 LLC resonant converter training. Brno 2012

Lower Upper Complementary

- Body diode can be used as a freewheeling diode in complementary

Buck converter topology

10 LLC resonant converter training. Brno 2012

Two switch forward topology Demagnetization phase

11 LLC resonant converter training. Brno 2012

Inverting B-B topology

- Minimum current and voltage overlap i.e. negligible switching losses

- Parasitic inductances and capacitances causes unwanted resonances

- Ringing can be damped by snubbers that however uses dissipative

17 LLC resonant converter training. Brno 2012

- Coss energy (1/2*Coss*Vds^2) is burnt during each turn-on

- Llk energy (1/2*Llk*Id^2) is burnt during each turn-off

- Diode is commutated under high current => Qrr related losses

- Various parasitic resonances are present causing voltage spikes that

- Passive and thus dissipative snubber networks are usually needed to

- Application EMI signature is affected by parasitic oscillations and

ZVS – Zero Voltage Switching: Switch is turned ON when there is

ZCS – Zero Current Switching: Switch is turned OFF when there is

Note: ZVS/ZCS techniques eliminates switching losses however, usually

- Example: Half wave mode ZVS QR buck

20 LLC resonant converter training. Brno 2012

- Example: Full wave mode ZCS QR buck

21 LLC resonant converter training. Brno 2012

22 LLC resonant converter training. Brno 2012

23 LLC resonant converter training. Brno 2012

Series resonant converter

24 LLC resonant converter training. Brno 2012

25 LLC resonant converter training. Brno 2012

- Lr, Cr and load resistance forms series resonant circuit.

- Lr and Cr forms the series resonant circuit again

27 LLC resonant converter training. Brno 2012

- Contains three resonant components Lr, Csr and Cpr

28 LLC resonant converter training. Brno 2012

29 LLC resonant converter training. Brno 2012

- Operation at fs is possible for nominal load and line conditions

30 LLC resonant converter training. Brno 2012

• Limited number of components: resonant tank elements can be

• Zero Voltage Switching (ZVS) condition for the primary switches

• Zero Current Switching (ZCS) for secondary diodes, no reverse

Cost effective, highly efficient and EMI friendly solution

Classical •Low ripple current on the •Switching under high

32 LLC resonant converter training. Brno 2012

33 LLC resonant converter training. Brno 2012

- Higher input current ripple and RMS value

34 LLC resonant converter training. Brno 2012

Compared to the single capacitor solution this connection offers:

35 LLC resonant converter training. Brno 2012

Disadvantages of this solution are:

38 LLC resonant converter training. Brno 2012

39 LLC resonant converter training. Brno 2012

40 LLC resonant converter training. Brno 2012

41 LLC resonant converter training. Brno 2012

42 LLC resonant converter training. Brno 2012

43 LLC resonant converter training. Brno 2012

45 LLC resonant converter training. Brno 2012

46 LLC resonant converter training. Brno 2012

47 LLC resonant converter training. Brno 2012

48 LLC resonant converter training. Brno 2012

Lm/Ls ratio: Gain of the converter:

Region3: ZCS region Region 1 and 2: ZVS operating regions

51 LLC resonant converter training. Brno 2012

- Coss energy (1/2CossVds^2) is burnt during each turn-on

- Llk energy (1/2LlkId^2) is burnt during each turn-off