MT29CxGxxMAxxxJA 6IT

Micron Confidential and Proprietary Preliminary‡
137-Ball NAND Flash with LP-DRAM MCP

Features
NAND Flash with LP-DRAM

137-Ball Multiple-Chip Package (MCP)
MT29CxGxxMAxxxJA
Current Production Part Numbers: Table 1 on page 2
Features Figure 1: MCP Block Diagram

• All-Micron® NAND Flash and LP-DRAM
components
• RoHS compliant, “green” package
• Separate NAND Flash and LP-DRAM interfaces
• Space-saving multi-chip package NAND Flash
NAND Flash NAND Flash
• Low-voltage operation (1.70–1.95V) Power Device Interface
• Industrial temperature range: –40C° to +85C°
NAND Flash-Specific Features

• Organization:
– Page size:
x8: 2,112 bytes (2,048 + 64 bytes)
x16: 1,056 words (1,024 + 32 words)
– Block size: 64 pages (128K + 4K bytes) LP-DRAM Power LP-DRAM LP-DRAM
Interface
– Device size: Device
1Gb: 1,024 blocks
2Gb: 2,048 blocks
4Gb: 4,096 blocks
8Gb: 8,192 blocks
LP-DRAM-Specific Features
• No external voltage reference required
• No minimum clock rate requirement Options Marking
• 1.8V LVCMOS-compatible inputs • LP-DRAM
• Programmable burst lengths 200 MHz CL33 -5
• Partial-array self refresh (PASR) 166 MHz CL3 -6
• Deep power-down (DPD) mode 133 MHz CL3 -75
• Selectable output drive strength
• STATUS REGISTER READ (SRR) supported2
Notes: 1. For part numbering and physical part mark-
ings, see Figure 2 and Table 1 on page 2.
2. Contact factory for remapped SRR output.
3. CL = CAS (READ) latency.
PDF: 09005aef82ff4431 / Source: 09005aef82ff448c Micron Technology, Inc., reserves the right to change products or specifications without notice.
137ball_nand_lpdram_j4xx.fm - Rev. L 12/08 EN 1 ©2007 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron Products are only warranted by Micron to meet Micron’s production data sheet specifications.
Micron Confidential and Proprietary Preliminary

Part Numbering
Part Numbering
Micron NAND Flash and LP-DRAM devices are available in several different
configurations and densities (see Figure 2).
Figure 2: 137-Ball Marketing Part Number Example
MT 29C 2G 24M A K L A JA -6 IT ES
Micron Technology Production Status

Blank = Production
Product Family ES = Engineering sample
29C = NAND + LP-DRAM MCP MS = Mechanical sample
NAND Density Operating Temperature Range

1G = 1Gb IT = Industrial (–40° to +85°C)
2G = 2Gb
4G = 4Gb LP-DRAM Access Time
8G = 8Gb -5 200 MHz CL3
-6 166 MHz CL3
LP-DRAM Density -75 133 MHz CL3
12M = 512Mb
24M = 1,024Mb Package Codes
48M = 2,048Mb JA = 137-ball TFBGA
Operating Voltage Range Chip Count

A = 1.8V (1.70–1.95V) CE#,CS# Chip Count
A 1, 1 1 NAND, 1 LP-DRAM
NAND Flash Configuration B 1, 1 2 NAND, 1 LP-DRAM
Width Density Generation C 1, 2 1 NAND, 2 LP-DRAM
C x8 1Gb First
LP-DRAM Configuration
D 1, 2 2 NAND, 2 LP-DRAM
Type Width Density Generation
D x16 1Gb First
A DDR x16 512Mb First
J x8 2Gb Second
C DDR x32 512Mb First
K x16 2Gb Second
J DDR x16 1Gb First
N x8 4Gb First
L DDR x32 1Gb First
P x16 4Gb First
N DDR x16 512Mb Second
U x8 1Gb Second
P SDR x16 512Mb Second
V x16 1Gb Second
R DDR x32 512Mb Second
T SDR x32 512Mb Second
Note: Not all possible combinations are available. Contact factory for availability.
Table 1: Production Part Numbers for 137-Ball MCP Package
Production Marketing
Part Numbers NAND Flash Product Mobile SDRAM Product Physical Part Marking
MT29C1G24MADLAJA-6 IT MT29F1G16ABBHC-ET MT46H32M32LFCM-6 IT JW181
MT29C1G24MADLAJA-75 IT MT29F1G16ABBHC-ET MT46H32M32LFCM-75 IT JW182
MT29C2G24MAKLAJA-6 IT MT29F2G16ABDHC-ET MT46H32M32LFCM-6 IT JW190
MT29C2G24MAKLAJA-75 IT MT29F2G16ABDHC-ET MT46H32M32LFCM-75 IT JW191
MT29C4G24MAPLAJA-6 IT MT29F4G16ABCHC-ET MT46H32M32LFCM-6 IT JW215
MT29C4G24MAPLAJA-75 IT MT29F4G16ABCHC-ET MT46H32M32LFCM-75 IT JW212
MT29C4G48MAPLCJA-6 IT MT29F4G16ABCHC-ET MT46H32M32LFCM-6 IT JW258
MT29C4G48MAPLCJA-75 IT MT29F4G16ABCHC-ET MT46H32M32LFCM-75 IT JW257

MCP General Description

The Micron® multiple-chip package (MCP) family of products includes both NAND
Flash and LP-DRAM devices, in a single MCP. These products target applications with
low-power, high-performance, and minimal package footprint design requirements. The
NAND Flash and LP-DRAM devices are also members of the Micron discrete memory
products portfolio.
The NAND Flash and LP-DRAM devices are packaged with separate interfaces (no
shared address, control, data, or power pins). This bus architecture supports an opti-
mized interface to processors with separate NAND Flash and LP-DRAM buses. The
NAND Flash and LP-DRAM devices have separate core power connections and share a
common ground (i.e., VSS is tied together on the two devices).
The bus architecture of this device also supports separate NAND Flash and LP-DRAM
functionality, without concern for device interaction. Operational characteristics for the
NAND Flash and LP-DRAM devices are found in the standard Micron data sheets for
each of the discrete devices.
For device specifications and complete Micron NAND Flash features documentation,
please refer to the component data sheet at www.micron.com/products/nand or con-
tact your local Micron sales office.
For device specifications and complete LP-DRAM features documentation, please refer
to the component data sheet at www.micron.com/products/mobiledram, or contact
your local Micron sales office.

Figure 3: Ball Assignment: 137-Ball TFBGA (LPDDR-SDRAM)

1 2 3 4 5 6 7 8 9 10
A DNU DNU DNU
B NC CKE1 RE# CLE VCC CE# WE# VDD VSS NC
C VSS A4 WP# ALE VSS R/B# DQ31 DQ30 VDDQ VSSQ
D VDD A5 A7 A9 DQ25 DQ27 DQ29 DQ28 VSSQ VDDQ
E A6 A8 CKE0 DQ18 DQS3 DQ22 DM3 DQ26 VDDQ VSSQ
F A12 A11 CS1# DQ17 DQ19 DQ24 DQ23 DM2 VSSQ VDDQ
G DNU RAS# DQ15 DQ16 DQS1 DM1 DQ9 CK VDDQ VSSQ
H VDD CAS# DQ20 DQ21 DQ13 DQ12 DQS2 CK# VSS VDD
J VSS CS0# BA0 DQ14 DQ11 DQ10 DQS0 DM0 VSSQ VDDQ
K WE# BA1 A10 A0 DQ7 DQ8 DQ6 DQ4 VDDQ VSSQ
L A1 A2 A3 DQ0 DQ1 DQ2 DQ3 DQ5 VDDQ VSSQ
M VDD VSS A13 RFU I/O3 I/O5 I/O14 I/O7 VSSQ VDDQ
N I/O0 I/O1 I/O2 I/O10 VCC I/O6 I/O13 I/O15 VDDQ VSSQ
P RFU I/O8 I/O9 I/O11 I/O12 VSS I/O4 VDD VSS LOCK
R DNU DNU DNU DNU
Top View—Ball Down
NAND LPDDR-DRAM Supply Ground

Figure 4: Ball Assignment: 137-Ball TFBGA (LP-SDRAM)

1 2 3 4 5 6 7 8 9 10
A DNU DNU DNU
B NC CKE1 RE# CLE VCC CE# WE# VDD VSS NC
C VSS A4 WP# ALE VSS R/B# DQ31 DQ30 VDDQ VSSQ
D VDD A5 A7 A9 DQ25 DQ27 DQ29 DQ28 VSSQ VDDQ
E A6 A8 CKE0 DQ18 RFU DQ22 DQM3 DQ26 VDDQ VSSQ
F A12 A11 CS1# DQ17 DQ19 DQ24 DQ23 DQM2 VSSQ VDDQ
G DNU RAS# DQ15 DQ16 RFU DQM1 DQ9 CLK VDDQ VSSQ
H VDD CAS# DQ20 DQ21 DQ13 DQ12 RFU RFU VSS VDD
J VSS CS0# BA0 DQ14 DQ11 DQ10 RFU DQM0 VSSQ VDDQ
K WE# BA1 A10 A0 DQ7 DQ8 DQ6 DQ4 VDDQ VSSQ
L A1 A2 A3 DQ0 DQ1 DQ2 DQ3 DQ5 VDDQ VSSQ
M VDD VSS RFU RFU I/O3 I/O5 I/O14 I/O7 VSSQ VDDQ
N I/O0 I/O1 I/O2 I/O10 VCC I/O6 I/O13 I/O15 VDDQ VSSQ
P RFU I/O8 I/O9 I/O11 I/O12 VSS I/O4 VDD VSS LOCK
R DNU DNU DNU DNU
Top View—Ball Down
NAND LP-SDRAM Supply Ground

Ball Descriptions
Ball Descriptions
Table 2: NAND Flash Ball Assignments
137-Ball MCP
NAND Flash x8 NAND Flash x16 Symbol Type Description
C4 C4 ALE Input Address latch enable: When ALE is HIGH, addresses
can be transferred to the on-chip address register.
B6 B6 CE# Input Chip enable: Gates transfers between the host
system and the NAND Flash device.
B4 B4 CLE Input Command latch enable: When CLE is HIGH,
commands can be transferred to the on-chip
command register.
P10 P10 LOCK Input When LOCK is HIGH during power-up, the BLOCK
LOCK function is enabled. To disable BLOCK LOCK,
connect LOCK to VSS during power-up, or leave it
unconnected (internal pull-down).
B3 B3 RE# Input Read enable: Gates information from the NAND
Flash device to the host system.
B7 B7 WE# Input Write enable: Gates information from the host
system to the NAND Flash device.
C3 C3 WP# Input Write protect: Driving WP# LOW blocks ERASE and
PROGRAM operations.
M8, N6, M6, P7, M5, N8, M7, N7, P5, P4, I/O[7:0] Input/ Data inputs/outputs: The bidirectional I/Os transfer
N3, N2, N1 N4, P3, P2, M8, N6, (x8) output address, data, and instruction information. Data is
M6, P7, M5, N3, N2, output only during READ operations; at other times
N1 I/O[15:0] the I/Os are inputs.
(x16) I/O[15:8] are RFU1 for NAND x8 devices.
C6 C6 R/B# Output Ready/busy: Open drain, active LOW output that
indicates when an internal operation is in progress.
B5, N5 B5, N5 VCC Supply VCC: NAND Flash power supply.
Notes: 1. Balls marked “RFU” may or may not be connected internally. These balls should not be
used. Contact factory for details.
Table 3: LP-DRAM Ball Assignments for LPDDR-SDRAM
137-Ball MCP
LPDDR-SDRAM x16 LPDDR-SDRAM x32 Symbol Type Description
M3, F1, F2, K3, D4, F1, F2, K3, D4, E2, D3, A[13:0] Input Address inputs: Specifies the row or column
E2, D3, E1, D2, C2, L3, E1, D2, C2, L3, L2, L1, (x16) address. Also used to load the mode registers. The
L2, L1, K4 K4 maximum LPDDR-SDRAM address is determined by
A[12:0] density and configuration. Consult the
(x32] LPDDR-SDRAM product datasheet for the maximum
address for a given density and configuration.
Unused address pins become “RFU.1”
J3, K2 J3, K2 BA0, BA1 Input Bank address inputs: Specifies one of the four
banks.
H2 H2 CAS# Input Column select: Specifies which command to
execute.

Ball Descriptions
Table 3: LP-DRAM Ball Assignments for LPDDR-SDRAM (continued)
137-Ball MCP (continued)

LPDDR-SDRAM x16 LPDDR-SDRAM x32 Symbol Type Description
G8, H8 G8, H8 CK, CK# Input CK is the system clock. CK and CK# are differential
clock inputs. All address and control signals are
sampled and referenced on the crossing of the
rising edge of CK with the falling edge of CK#.
E3, B2 E3, B2 CKE0, CKE1 Input Clock enable.
CKE0 is used for a single LPDDR-SDRAM product.
CKE1 is used for dual LPDDR-SDRAM products, and
is considered RFU for single LPDDR-SDRAM MCPs.
J2, F3 J2, F3 CS0#, CS1# Input Chip select:
CS0# is used for a single LPDDR-SDRAM product.
CS1# is used for dual LPDDR-SDRAM products, and
is considered RFU for single LPDDR-SDRAM MCPs.
J8, G6 E7, F8, G6, J8 LDM, UDM Input Data mask: Determines which bytes are written
(x16) during WRITE operations.
For x16 LPDDR-SDRAM, unused DM balls become
DM[3:0] RFU.
(x32)
G2 G2 RAS# Input Row select: Specifies the command to execute.
K1 K1 WE# Input Write enable: Specifies the command to execute.
G3, J4, H5, H6, J5, J6, C7, C8, D7, D8, D6, DQ[15:0] Input/ Data bus: Data inputs/outputs.
G7, K6, K5, K7, L8, E8, D5, F6, F7, E6, H4, (x16) output DQ[31:16] are RFU for x16 LPDDR-SDRAM devices.
K8, L7, L6, L5, L4 H3, F5, E4, F4, G4,
G3, J4, H5, H6, J5, J6, DQ[31:0]
G7, K6, K5, K7, L8, (x32)
K8, L7, L6, L5, L4
J7, G5 E5, H7, G5, J7 LDQS, UDQS Input/ Data strobe: Coordinates read/write transfers of
(x16) output data; one DQS per DQ byte.
For x16 LPDDR-SDRAM, unused DQS balls become
DQS[3:0] RFU.
(x32)
B8, D1, H1, H10, M1, B8, D1, H1, H10, M1, VDD Supply VDD: LPDDR-SDRAM power supply.
P8 P8
C9, D10, E9, F10, G9, C9, D10, E9, F10, G9, VDDQ Supply VDDQ: LPDDR-SDRAM I/O power supply.
J10, K9, L9, M10, N9 J10, K9, L9, M10, N9
C10, D9, E10, F9, G10, C10, D9, E10, F9, G10, VSSQ Supply VSSQ: LPDDR-SDRAM I/O ground.
J9, K10, L10, M9, N10 J9, K10, L10, M9, N10
M3 RFU1 – Reserved for future use.
Note: Balls marked “RFU” may or may not be connected internally. These balls should not be

Ball Descriptions
Table 4: LP-DRAM Ball Assignments for LP-SDRAM
137-Ball Device
LP-SDRAM x16 LP-SDRAM x32 Symbol Type Description
F1, F2, K3, D4, E2, D3, F2, K3, D4, E2, D3, E1, A[12:0] Input Address inputs: Specifies the row or column
E1, D2, C2, L3, L2, L1, D2, C2, L3, L2, L1, K4 (x16) address. Also used to load the mode registers. The
K4 maximum LP-SDRAM address is determined by
A[11:0] density and configuration. Consult the LP-SDRAM
(x32) product datasheet for the maximum address for a
given density and configuration. Unused address
pins become “RFU.1”
J3, K2 J3, K2 BA0, BA1 Input Bank address inputs: Specifies one of the four
banks.
H2 H2 CAS# Input Column select: Specifies which command to
execute.
E3, B2 E3, B2 CKE0, CKE1 Input Clock enable.
CKE0 is used for a single LP-SDRAM product.
CKE1 is used for dual LP-SDRAM products, and is
considered RFU for single LP-SDRAM MCPs.
G8 G8 CLK Input CLK is the system clock. All address and control
signals are sampled on the rising edge of CLK.
J2, F3 J2, F3 CS0#, CS1# Input Chip select:
CS0# is used for a single LP-SDRAM product.
CS1# is used for dual LP-SDRAM products, and is
considered RFU for single LP-SDRAM MCPs
J8, G6 E7, F8, G6, J8 LDQM, Input Input/output mask: DQM is sampled HIGH and is an
UDQM input mask signal for WRITE accesses and an output
(x16) enable signal for READ accesses.
For x16 LP-SDRAM, unused DQM balls become RFU.
DQM[3:0]
(x32)
G2 G2 RAS# Input Row select: Specifies the command to execute.
K1 K1 WE# Input Write enable: Specifies the command to execute.
G3, J4, H5, H6, J5, J6, C7, C8, D7, D8, D6, DQ[15:0] Input/ Data bus: Data inputs/outputs.
G7, K6, K5, K7, L8, E8, D5, F6, F7, E6, H4, (x16) output DQ[31:16] are RFU for x16 LP-SDRAM devices.
K8, L7, L6, L5, L4 H3, F5, E4, F4, G4, G3,
J4, H5, H6, J5, J6, G7, DQ[31:0]
K6, K5, K7, L8, K8, L7, (x32)
L6, L5, L4
B8, D1, H1, H10, M1, B8, D1, H1, H10, M1, VDD Supply VDD: LP-SDRAM power supply.
P8 P8
C9, D10, E9, F10, G9, C9, D10, E9, F10, G9, VDDQ Supply VDDQ: LP-SDRAM I/O power supply.
J10, K9, L9, M10, N9 J10, K9, L9, M10, N9
C10, D9, E10, F9, G10, C10, D9, E10, F9, G10, VSSQ Supply VSSQ: LP-SDRAM I/O ground.
J9, K10, L10, M9, N10 J9, K10, L10, M9, N10
H8, H8 NC – No connect: Not internally connected.
C7, C8, D5, D6, D7, E5, F1, G5, H7, J7, M3 RFU1 – Reserved for future use.
D8, E4, E5, E6, E7, E8,
F1, F4, F5, F6, F7, F8,
G4, G5, H3, H4, H7,
J7, M3

Ball Descriptions
Table 5: Non-Device-Specific Ball Assignments
137-Ball MCP
Shared Symbol Type Description
B9, C1, C5, H9, J1, VSS Supply VSS: Shared ground.
M2, P6, P9
Miscellaneous Symbol Type Description
B1, B10 NC – No connect: Not internally connected.
A2, A9, A10, G1, R1, DNU – Do not use: Must be grounded or left floating.
R2, R9, R10
M4, P1 RFU1 – Reserved for future use.

Electrical Specifications
Electrical Specifications
Table 6: Absolute Maximum Ratings
Parameters/Conditions Symbol Min Max Unit

VCC, VDD, VDDQ supply voltage VCC, VDD, –1.0 2.4 V
relative to VSS VDDQ
Voltage on any pin VIN –0.5 2.4 or (VDDQ + 0.3V), V
relative to VSS whichever is less
Storage temperature range –55 +150 °C
Stresses greater than those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Table 7: Recommended Operating Conditions
Parameters Symbol Min Typ Max Unit

Supply voltage VCC, VDD 1.70 1.80 1.95 V
I/O supply voltage VDDQ 1.70 1.80 1.95 V
Operating temperature range – –40 – +85 °C

Device Diagrams
Device Diagrams
Figure 5: Functional Block Diagram: 137-Ball TFBGA (LPDDR-SDRAM) Example
CE#
Vcc
CLE
ALE
NAND Flash
RE#
I/O
WE#
WP#
R/B#
LOCK
Vss
CS# VDD
CK VDDQ
CK# DM
CKE LPDDR-SDRAM
RAS# DQ
CAS#
WE# DQS
Vss
Address, VssQ
BA0, BA1
Table 8: Chip Select Signal Assignments per Chip Count Configuration
Chip Count 1st DRAM 2nd DRAM Notes

1 NAND, 1 LP-DRAM CS0#, CKE0 N/A
1 NAND, 2 LP-DRAM CS0#, CKE0 CS1#, CKE1 1
2 NAND, 2 LP-DRAM CS0#, CKE0 CS1#, CKE1 1, 2
Notes: 1. All other signals are shared between both DRAM devices.
2. When multiple NAND chips are included, they share a single CE signal.

Device Diagrams
Figure 6: Functional Block Diagram: 137-Ball TFBGA (LP-SDRAM) Example
CE#
Vcc
CLE
ALE
NAND Flash
RE#
I/O
WE#
WP#
R/B#
LOCK
Vss
CS# VDD
CLK VDDQ
CKE DQM
RAS# LP-SDRAM
CAS# DQ
WE#
Vss
VssQ
Address,
BA0, BA1

Package Dimensions
Package Dimensions
Figure 7: 137-Ball TFBGA
0.85 ±0.1
Seating
plane
A
0.12 A
137X Ø0.45
Solder ball
material: SAC105.
Dimensions apply
to solder balls post- Ball A1 ID Ball A1 ID
reflow on Ø0.4 10 9 8 7 6 5 4 3 2 1
SMD ball pads.
A
B
C
D
0.8 TYP
E
F
G
11.2 CTR H 13 ±0.1

J
K
L
M
N
P
0.8 TYP 1.2 MAX

7.2 CTR 0.25 MIN
10.5 ±0.1
Note: All dimensions are in millimeters.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.

Revision History
Revision History
Rev. L, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/08

• “Options” on page 1: Added 200 MHz option.
• Figure 2: 137-Ball Marketing Part Number Example on page 2: Added 200 MHZ LP-
DRAM Access Time.
Rev. K, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/08

• Figure 2: 137-Ball Marketing Part Number Example on page 2: Updated chip-count
options.
• Table 1, Production Part Numbers for 137-Ball MCP Package, on page 2: Added JW257
and JW 258 details.
Rev. J, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/08

• Figure 2, 137-Ball Marketing Part Number Example, on page 2: Removed low power
option.
Rev. I, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/08

• “NAND Flash-Specific Features” on page 1 added 8Gb NAND option.
• Figure 2, 137-Ball Marketing Part Number Example, on page 2 added 8Gb NAND
option and 2 NAND, 2 DRAM chip count option, corrected typographical error on
NAND Flash Configuration.
• Figure 3, Ball Assignment: 137-Ball TFBGA (LPDDR-SDRAM), on page 4: changed pin
P1 from NC to RFU.
• Figure 4, Ball Assignment: 137-Ball TFBGA (LP-SDRAM), on page 5: changed pins E5,
G5, H7, H8, J7, P1 from NC to RFU.
• Table 2, NAND Flash Ball Assignments, on page 6 and Table 3, LP-DRAM Ball Assign-
ments for LPDDR-SDRAM, on page 6 and Table 4, LP-DRAM Ball Assignments for LP-
SDRAM, on page 8: changed unused (based on configuration) DQ, I/O, command
pins and P1 from NC to RFU.
• Figure 7, 137-Ball TFBGA, on page 13: Updated package diagram to reflect 0.10 toler-
ances.
Rev. H, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/08

• Figure 2: 137-Ball Marketing Part Number Example on page 2: Updated diagram.
• Table 1, Production Part Numbers for 137-Ball MCP Package, on page 2: Added new
production part numbers.
Rev. G, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/08

• Capacitance tables deleted.
Rev. F, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/08


Revision History
• Table 3, LP-DRAM Ball Assignments for LPDDR-SDRAM, on page 6, and Table 4, LP-
DRAM Ball Assignments for LP-SDRAM, on page 8: Corrected CKE1 ball.
• Table 5, Non-Device-Specific Ball Assignments, on page 9: Updated NC ball listing.
Rev. E, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/08

• Figure 2: 137-Ball Marketing Part Number Example on page 2: Updated diagram.
• Table 1, Production Part Numbers for 137-Ball MCP Package, on page 2: Added table
(and current production part number on page 1).
• Figure 3: Ball Assignment: 137-Ball TFBGA (LPDDR-SDRAM) on page 4 and Figure 4:
Ball Assignment: 137-Ball TFBGA (LP-SDRAM) on page 5: Updated titles and ball
assignments.
• Table 3, LP-DRAM Ball Assignments for LPDDR-SDRAM, on page 6: Updated table
title, headings, and LDM, UDM, LDQS, UDQS assignments; updated CKE and CS
descriptions; added RFU content and note.
• Table 4, LP-DRAM Ball Assignments for LP-SDRAM, on page 8: Added table and note.
• Table 5, Non-Device-Specific Ball Assignments, on page 9: Added note.
• Figure 5: Functional Block Diagram: 137-Ball TFBGA (LPDDR-SDRAM) Example on
page 11 and Figure 6: Functional Block Diagram: 137-Ball TFBGA (LP-SDRAM) Exam-
ple on page 12: Updated titles.
Rev. D, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/08

• Figure 7: 137-Ball TFBGA on page 13: Updated package diagram.
Rev. C, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/08

• Table 3, LP-DRAM Ball Assignments for LPDDR-SDRAM, on page 6: Removed M3
from DQ row, x16 LPDDR-DRAM column.
• Table 5, Non-Device-Specific Ball Assignments, on page 9: Removed P10 from both
NC columns.
• Figure 4: Ball Assignment: 137-Ball TFBGA (LP-SDRAM) on page 5: Corrected color of
ball B5.
• Figure 5: Functional Block Diagram: 137-Ball TFBGA (LPDDR-SDRAM) Example on
page 11: Added LOCK input to NAND Flash.
Rev B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/07

• “NAND Flash with LP-DRAM 137-Ball Multiple-Chip Package (MCP)” on page 1:
Removed “Mobile” from title.
• “LP-DRAM-Specific Features” on page 1: Added SRR feature.
• Table 2, NAND Flash Ball Assignments, on page 6: Revised table.
• Separated original single ball-assignment table into individual tables: Table 2, NAND
Flash Ball Assignments, on page 6, Table 3, LP-DRAM Ball Assignments for LPDDR-
SDRAM, on page 6, and Table 5, Non-Device-Specific Ball Assignments, on page 9.
• Removed “Mobile” from LP-DRAM references and changed LP-DRAM to LPDDR-
DRAM as applicable.
Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/07

• Initial release.

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Micron Confidential and Proprietary Preliminary‡

137-Ball NAND Flash with LP-DRAM MCP

NAND Flash with LP-DRAM

Features Figure 1: MCP Block Diagram

NAND Flash-Specific Features

137-Ball NAND Flash with LP-DRAM MCP

Figure 2: 137-Ball Marketing Part Number Example

Micron Technology Production Status

NAND Density Operating Temperature Range

Operating Voltage Range Chip Count

Table 1: Production Part Numbers for 137-Ball MCP Package

137-Ball NAND Flash with LP-DRAM MCP

MCP General Description

137-Ball NAND Flash with LP-DRAM MCP

Figure 3: Ball Assignment: 137-Ball TFBGA (LPDDR-SDRAM)

A DNU DNU DNU

B NC CKE1 RE# CLE VCC CE# WE# VDD VSS NC

C VSS A4 WP# ALE VSS R/B# DQ31 DQ30 VDDQ VSSQ

D VDD A5 A7 A9 DQ25 DQ27 DQ29 DQ28 VSSQ VDDQ

E A6 A8 CKE0 DQ18 DQS3 DQ22 DM3 DQ26 VDDQ VSSQ

G DNU RAS# DQ15 DQ16 DQS1 DM1 DQ9 CK VDDQ VSSQ

K WE# BA1 A10 A0 DQ7 DQ8 DQ6 DQ4 VDDQ VSSQ

L A1 A2 A3 DQ0 DQ1 DQ2 DQ3 DQ5 VDDQ VSSQ

R DNU DNU DNU DNU

Top View—Ball Down

NAND LPDDR-DRAM Supply Ground

137-Ball NAND Flash with LP-DRAM MCP

Figure 4: Ball Assignment: 137-Ball TFBGA (LP-SDRAM)

A DNU DNU DNU

B NC CKE1 RE# CLE VCC CE# WE# VDD VSS NC

C VSS A4 WP# ALE VSS R/B# DQ31 DQ30 VDDQ VSSQ

D VDD A5 A7 A9 DQ25 DQ27 DQ29 DQ28 VSSQ VDDQ

E A6 A8 CKE0 DQ18 RFU DQ22 DQM3 DQ26 VDDQ VSSQ

K WE# BA1 A10 A0 DQ7 DQ8 DQ6 DQ4 VDDQ VSSQ

L A1 A2 A3 DQ0 DQ1 DQ2 DQ3 DQ5 VDDQ VSSQ

R DNU DNU DNU DNU

Top View—Ball Down

NAND LP-SDRAM Supply Ground

137-Ball NAND Flash with LP-DRAM MCP

Table 3: LP-DRAM Ball Assignments for LPDDR-SDRAM

137-Ball NAND Flash with LP-DRAM MCP

Table 3: LP-DRAM Ball Assignments for LPDDR-SDRAM (continued)

137-Ball MCP (continued)

137-Ball NAND Flash with LP-DRAM MCP

Table 4: LP-DRAM Ball Assignments for LP-SDRAM

137-Ball NAND Flash with LP-DRAM MCP

Table 5: Non-Device-Specific Ball Assignments

137-Ball NAND Flash with LP-DRAM MCP

Parameters/Conditions Symbol Min Max Unit

Table 7: Recommended Operating Conditions

Parameters Symbol Min Typ Max Unit

137-Ball NAND Flash with LP-DRAM MCP

Table 8: Chip Select Signal Assignments per Chip Count Configuration

Chip Count 1st DRAM 2nd DRAM Notes

137-Ball NAND Flash with LP-DRAM MCP

Figure 6: Functional Block Diagram: 137-Ball TFBGA (LP-SDRAM) Example

137-Ball NAND Flash with LP-DRAM MCP

11.2 CTR H 13 ±0.1

0.8 TYP 1.2 MAX