39th International Symposium on Multiple-Valued Logic

Multi-Level Signaling for Chip-to-Chip and Backplane Communication

(A Tutorial)
Ali Sheikholeslami
Dept. of Electrical & Computer Engineering, University of Toronto, Canada
[email protected]

Abstract This paper is organized as follows: First, we present

the electrical characteristics of a typical channel, followed
The signal attenuation in chip-to-chip and backplane by the effects they have on signal integrity. Next, in
communication increases with the data rate. Depending Section 3, we present methods of overcoming these signal
on the channel’s frequency response, this attenuation may impairments. Section 4 reviews the costs and the benefits
be mitigated if multi-level signaling is employed instead of multi-level signaling, followed by an example of a 4-
of binary signaling. This paper reviews the basics of level receiver in Section 5.
binary signaling and how multi-level signaling could help
improve the signal quality. 2. Channel Characteristics

1. Introduction A channel can be characterized in the frequency

domain by its signal attenuation at any given frequency.
With technology scaling, the integrated circuits (IC’s) For example, Fig. 2 [2] shows the characteristics of a 40’’
are no longer the speed bottleneck for communication PCB trace on FR4 material. For a target bit rate of 6Gb/s,
between two chips on the same board; the communication which corresponds to a Nyquist frequency of 3GHz, the
channels are. In chip-to-chip and backplane signaling, the signal attenuation is around 20dB. Fig. 2 also shows that
communication channel consists of a trace on a Printed the level of crosstalk, i.e. the unwanted signal coupled
Circuit Board (PCB). This trace can be a meter long and from adjacent channels, could exceed the actual signal
may pass through one or two connectors and several vias level. In the example shown, the crosstalk level is almost
(see Fig. 1) [1]. As data rates increase well into the Gb/s at the same level of the input signal at the Nyquist
range, such channels behave as distributed transmission frequency of 4GHz.
lines, and as such attenuate the transmitted signal, and
cause inter-symbol interference (ISI), reflection, and In time domain, the channel attenuation is translated
crosstalk. The goal of a transceiver design is therefore that into ISI. As shown in Fig. 3, a transmitted ideal square
of the design of low-power transmitter and receiver pulse smears in time and spreads itself onto adjacent
(transceiver) in order to reliably detect the transmitted symbols by the time it arrives at the receiver. This will
sequence in the face of these signal impairments.
Signal
Via 0
TX

Connector
-20
T-Line

-40
dB

-60
RX

< 40”
-80
Crosstalk

0 1 2 3 4 5 6
GHz
Fig. 1: Chip-to-chip signaling on a backplane
Fig. 2: Signal attenuation and crosstalk

0195-623X/09 $25.00 © 2009 IEEE 203

DOI 10.1109/ISMVL.2009.64
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 Transmitted signal
200mV/div
Received signal

+pre., no ref.-c.

time
0 1T 2T 3T 4T 62.5ps/div
Fig. 3: Inter-Symbol Interference (ISI)
obviously interfere with the adjacent symbols and make
the task of data recovery more difficult. The techniques to
combat this signal attenuation are known as
“equalization”, which we will discuss in the next section.

Another source of signal impairment is signal

reflection, which occurs at any discontinuity in the
channel. A typical PCB trace is designed to have a 50Ω
characteristic impedance, whereas any via or connector Fig. 5: Eye-diagrams with & w/o ref. cancellation
may present a different resistance to the transmission line.
This mismatch in resistance creates a reflected signal sequence to match the timing of the reflected signal, and
which in turn will interfere with the incoming signal and shaping it by an 8-tap feed-forward digital filter. Fig. 5
cause potential data errors. compares the eye diagram at the receiver for when the
cancellation scheme is enabled and disabled.
The best way to avoid reflections is to eliminate
mismatches in the channel. This may be possible to 3. Channel Equalization
accomplish when both chips are on the same board as the
PCB trace does not have to leave a board through a As mentioned in the previous section, the transmit
connector. But when the signal reflection is unavoidable, signal is attenuated by the frequency response of the
one must design circuits to cancel this reflection. One channel. This frequency-dependent attenuation can be
example of such a design is shown in Fig. 4 [3], where the compensated for at the transmitter, at the receiver, or at
reflected signal is predicted and cancelled directly at the both ends by including appropriate circuit blocks such
transmitter. This is achieved by delaying the input that the combined frequency response of these blocks and
the channel is constant across the frequency range of
TXout
interest. This is known as channel equalization.

When the equalization is performed at the transmitter,

it is often referred to as pre-equalization or pre-emphasis.
8 taps ref . An example of this is shown in Fig. 6, where the transmit
sequence Dn is delayed and multiplied by α, to be
3 taps pre. subtracted from Dn itself. This simple operation
D 2N:2N+7x[n]
emphasizes data transitions and, in a sense, amplifies the
1 tap
high-frequency content of the transmit signal. The circuit
D 1:3x[n] implementation consists of two differential pairs with
appropriately weighted current tails. For pre-emphasis of
x[n] higher order, a higher number of differential pairs are
used.

main

Fig. 4: TX pre-emphasis and reflection cancellation

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 IL
ΔV
OUT
Dn Dn

Dn-1 Dn-1 ΔV/3

ΔV/3
I0 I1 ΔV/3

Fig. 8: 2-level and 4-level eye diagrams

noise, this scheme is known to only boost the high-
Dn frequency content of the signal and not that of the noise.
0 1 1 0 0

4. Multi-Level Signaling
-a Dn-1
Among various signaling schemes, Non-Return-to-
OUT Zero (NRZ) binary signaling has been the most common
in chip-to-chip and backplane applications. As mentioned
in the previous section, the conventional approach in
detecting this binary sequence is to first equalize the
Fig. 6: Pre-emphasis circuit and timing example
channel, so as to eliminate or reduce ISI, and then to
compare the equalized signal against a reference voltage
in order to produce “0” or “1”. However, there has been a
x[n] y[n] ŷ[n] move in recent years of using an Analog to Digital
Converter (ADC) in the front end to immediately sample
the received signal, using 4 bits for example, and to
perform all the necessary equalization in the digital
domain [4][5]. At the time of this writing, the cost of an
ADC front end (in terms of silicon area and power) is still
W[z] larger than its binary counterpart, but it is well predicted
[6] that this cost will reduce in near future with
technology scaling and with innovative circuit techniques.
N Using this approach, the design of a receiver for the chip-
w [ z] = ∑ w i z −i to-chip and backplane signaling reduces to the careful
i =1 design of an ADC, as the rest of the design are all in
Fig. 7: Decision Feedback Equalizer (DFE) digital and can be synthesized using RTL. Another
implication of using an ADC front end is the ease of
signaling in multiple levels instead of in binary. Since the
When the equalization is preformed at the receiver it is
received signal is an analog signal (and hence contains
referred to as post-equalization. Equalization at the
many levels already), it makes sense to extend this
receiver can be either linear or nonlinear. A linear
technique to having multi-level signaling. The question
equalizer boosts the high-frequency components of the
that needs to be addressed here is under what conditions
received signal (similar to pre-emphasis), but also boosts
multi-level signaling provides an advantage over binary
the noise at the receiver. For this reason, linear equalizers
signaling. We address this question in the following.
are often used in conjunction with nonlinear equalizers
such as the Decision Feedback Equalizer (DFE).
Given the same transmitter properties, the maximum
voltage difference between the levels produced by the
The block diagram of a DFE is shown in Fig. 7. Here,
transmitter is often limited by the power supply and the
an estimate of the channel’s ISI (the output of W[z]
block) is subtracted from the input sequence, x[n], and fed circuit configuration used. Let us denote by ΔV (around
to a binary slicer to recover the transmit data. Since the 100mV) the voltage difference between logic “1” and “0”
output of the slicer is binary, and does not contain any at the receiver input. Given this ΔV and the level of noise
(and crosstalk) at the receiver input, one can determine
the signal-to-noise ratio (SNR) in this scheme. The larger

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 dB 4-Level Slicer

Signal attenuation (dB)

x[n] y[n] 2 ŷ[n]
-8
0
14dB -2
-22

W[z]

N
f b/4 f b/2
Freq.
w [ z] = ∑ w i z −i
i =1
Fig. 9: Example channel attenuation characteristic
when 4-level signaling is beneficial Fig. 10: 4-Level DFE block diagram
the SNR, the less the bit error rate (BER). If we choose 4 5. 4-Level Receiver with DFE
levels of signaling, instead of 2, then the distance between
two adjacent levels will be reduced by a factor of 3, to In the previous section, we motivated the use of multi-
ΔV/3. This is shown with the help of two eye diagrams in level signaling by the prospects of receivers with ADC
Fig. 8. It may appear at first that this loss of signal may front ends. However, the use of 4-level signaling is not
favor binary signaling. However, by moving to 4 levels limited to receivers with ADC front ends. There are in
instead of 2 levels, we also reduce the signal bandwidth in fact several implementation of 4-level signaling [7][8][9]
the frequency domain. As a consequence, the 4-level that use DFE to equalize the 4-level received signal. One
signal is subjected to less attenuation from the channel such example [9] is shown in Fig. 10, where the received
compared with the binary signal. Note that for the bit rate signal, x[n] is fed to a DFE in order to form an equalized
of fb (in units of bits/sec), the Nyquist frequency for signal, y[n]. This signal is then compared against three
binary signaling is fb/2 whereas for 4-level is fb/4. Since reference levels to produce 3 bits in thermometer code.
the channel is often a low-pass filter in nature, it The 3 bits are fed to W[z] in order to reproduce the
attenuates the fb/2 component more than it does the fb/4 channel ISI, which in turn is subtracted from the received
component. Therefore, the deciding factor becomes that signal.
of a comparison between the signal attenuation in the
channel versus the signal attenuation due to multi-level
Since the channel is not known in advance or, if it is, it
signaling.
may change with process and temperature, the filter W[z]
in this design must be made adaptive [9]. Also, to support
Fig. 9 plots the signal loss (in terms of dB) as a high bit rates, the loop delay of the DFE must be
function of frequency for an example channel. For this minimized. One candidate circuit for this purpose is
example, if we move from binary to 4-level signaling, we shown in Fig. 11, where the summation is performed on
lose 9.5dB due to the nature of 4-level signaling, but we low impedance nodes in order to increase speed.
gain 14dB as the channel does not attenuate the 4-level
signal as much. Therefore, overall it would be
advantageous to move to the 4-level signaling. This same
6. Conclusions
argument can be generalized to the case of M-level
signaling when M is larger than 4. The use of 4-level and 8-level signaling in chip-to-chip
and backplane applications will become more dominant
Another point of comparison between various as the use of ADC front-end becomes more common with
signaling schemes relates to crosstalk and its spectrum. the advance of technology. The design choice between
Since crosstalk is often of the high-pass nature, there may binary or 4-level would depend on the channel
be more crosstalk at fb/2 than there is at fb/4. Therefore characteristics and on how much the signal is attenuated
moving to multi-level has a potential advantage in at the Nyquist frequencies of respective signaling.
reducing the crosstalk.

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 VB1
Current-summing nodes [3] R. Yuen, M. van Ierssel, A. Sheikholeslami, et al., “A
5Gb/s Transmitter with Reflection Cancellation for
xn Backplane Transceivers,” IEEE Custom Integrated
xn VB2 Circuit Conference (CICC), Proceedings, Sep. 2006, pp.
ŷ n-i 413-416.
ŷn-i
CK CK CK [4] O. Agazzi, D. Crivelli, M. Hueda, et al., “A 90nm
Wi
CMOS DSP MLSD Transceiver with Integrated AFE for
Electronic Dispersion Compensation of Multi-mode
Optical Fibers at 10Gb/s,” Dig. of Tech. Papers, IEEE
ith-bit Int’l Solid-State Circuits Conference (ISSCC), Feb. 2008,
f eedback pp. 232-233.
Input CK
[5] J. Cao, B. Zhang, U. Singh, et al., “A 500mW
CK Digitally Calibrated AFE in 65nm CMOS for 10Gb/s
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Fig. 11: Circuit implementation example of DFE [9]
Acknowledgment [6] A. Sheikholeslami, B. Payne, and J. Lin, “Will ADCs
Overtake Binary Frontends in Backplane Signaling
The author acknowledges the financial support from (Special Evening Session, SE3),” Dig. of Tech. Papers,
Natural Sciences and Engineering Research Council IEEE Int’l Solid-State Circuits Conference (ISSCC), Feb.
(NSERC) of Canada, as well as the technical and financial 2009, p. 514.
support from Fujitsu Laboratories of Japan and Fujitsu
Laboratories of America. [7] A. Varzaghani, and C. K. Yang, “A 6-GSamples/s
Multi-Level Decision Feedback Equalizer Embedded in a
4-Bit Time-Interleaved Pipeline A/D Converter,” J. of
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