semiconductor group

263 k r e a l Dailey P k iu y ., M a lu e rn , Pa 19355

5 5 0 3 DIGITAL OSCILLATOR CHIP

GENERAL DESCRIPTION

The 5503 digital o sc illa tor chip u»as designed to proulde

high quality electronic music synthesis capabilities f o r
any music re lated applications. These applications rangs
from professional music products (s yn thesizer's etc.) to
| arcaiic or home uideo games. The 5503 chip contains 52
• oscillators, uarious co ntro l r e g i s te r s and an R/D
i

tiL O lM O
-• Directly addresses 64k bytes o f m e m o ry
- Ek-afc select ou tp ut enpands addressing to 128k
bi-jtes of m emory
- niioms w a u e fo r m ou tp u t to be assigned to
d i f f e r e n t channels (uoices)
- Generates clock signals co m pa tib le Luith the
Motoro la 6809e micropro cessor (E & Q clock inputs)
- Generates the r o w and column address strobes
used by dynamic memories (RRS O' CRS)
- Rutomatically refreshes 64k h 1 compatible
dynamic memories
- On chip 0 bit linear nnalog to dig ital c o n v e r te r
- Compatible w i t h 6800/6500 f a m ily microprocessors
 5 5 0 3 P IN DESCRIPTION
CLK [ 1 4 0 ] BS

RflS [ 2 3 9 ] Udd

CHS [ 3 38 ] RO

Q [ 4 3 7 ] R1

E C 5 3 6 1 R2
«

CSTRB [ 6 3 5 ] R3

cno [ 7 3 4 ] R4

CR1 C 8 33 : R5

CR2 C 9 32 : R6

CR3 [ 10 31 : R7
1

UUREF C 11 30 ] R 8 / D 0

UOLFDBK [ 12 2 9 3 R9/ D1

UOL- C 13 28 D R 1 0 / D 2

LUUREF C 1 4 ' 27 3 R11/03

SIG+ [ 15 26 ] R 1 2 /D 4

S1G- C 16 25 ] R 1 3 /D 5

R/ D C 17 2 4 ]• R 1 4 / D 6

IRQ C 18 23 ] R 1 5 / 0 7

Uss C 19 2 2 ] uje
#
RES C 2 0 2 i ;] cs
 5505 PIN DESCRIPTION
...... - .............
PIN SIGNRL
NUMBER NRME FUNCTION

I-:-"- CLK CLOCK INPUT - M a s t e r cl ock l o r t h e

5 5 0 3 chi p. M o s t be 507o d o t y cy cl e . I t
is i n t e r n a l l y d i u i d e d b y 8 to g e t t h e
basic cycle time.
*
2 RRS ROW RDDRESS STROBE OUTPUT - S t r o b e
f o r accessing dynamic m e m ory.

3 CHS COLUMN RDDRESS STROBE OUTPUT -

S t r o b e Tor a c c e s s i n g d y n a m i c m e m o r y .

4 Q Q CLOCK OUTPUT - C o m p a t i b l e w i t h t h e
M 6 8 0 9 E m i c r o p r o c e s s o r Q cl ock. This
cl ock l e a d s t h e E cl ock ( pi n 5) by 1 / 4
c y c l e a n d has a 507> d o t y cy c l e .

5 E E CLOCK OUTPUT - C o m p a t i b l e Luith t h e

M 6 8 0 9 E m i c r o p r o c e s s o r E cl ock. This
c l o ck al so has a 507> d u t y cycl e .

6 CSTRB CHRNNEL STROBE OUTPUT - L o w a c t i u e

s i g na l i n d i c a t e s t ohen t h e c h a n n e l
a s s i g n o u t p u t s (CRO - CR3) a r e ual i d.

7 -1 0 CRO - CHRNNEL RSSIGN OUTPUTS - RII olus t h e

CR3 o u t p u t s o f t h e o s c i l l a t o r s (SIG+ O' S I G- )
t o be d i r e c t e d t o d i f f e r e n t c h a n n e l s .

11 UDREF UOLUME UOLTRGE REFERENCE INPUT -

* R efe re n c e uoltage fo r the internal
u o l u m e D/ R c o n u e r t e r . M u s t be - 5 u
+ o r - 57o.

12 UOLFDBK UOLUME FEEDBACK I NPUT - This si gnal

is t h e o u t p u t o f t h e UOL- o u t p u t a f t e r
it ha s b e e n c o n u e r t e d to a u o l t a g e
 5503 PIN DESCRIPTION (CONT.)

PIN SIGNRL
NUMBER NRME FUNCTION'

13 UOL- UOLUME OUTPUT - This si g na l is a c u r r e n t

o u t p u t uj hi ch s h o u l d be c o n u e r t e d t o
a u o l t a g e , t h e o u t p u t o f w h i c h is f e d
i n t o t h e LUDREF i n p u t ( pi n 14). This
u o l t a g e ujill be u s e d as t h e r e f e r e n c e
■v
u o l t a g e f o r t h e i n t e r n a l D/ R c o n u e r t e r
f o r t h e SIG+ RND SI G- o u t p u t s . I t m u s t
al so be f e d b a c k i n t o t h e u o l f d b k i n p u t
(pin 1 2) .

14 IDUREF UJRUEFORM UOLTRGE REFERENCE I NPUT -

This i n p u t luill p r o u i d e t h e r e f e r e n c e
u o l t a g e f o r t h e i n t e r n a l D/ R c o n u e r t e r
f o r t h e SIG+ RND SI G- o u t p u t s (pi ns 15
O' 16).

15 - 16 SI G* O' LURUEFORM SIGNRL - AND - OUTPUTS -

S I G- These t L u o o u t p u t s a r e d i f f e r e n t i a l
c u rre n ts r e p r e s e n t i n g the final
w a u e f o r m ou tput ualue (sample).

17 R/ D RNRLOG/ DI GI TRL CONUERTER INPUT -

This is t h e i n p u t f o r t h e a n a l o g to
d i g i t a l c o n u e r t e r on t h e 5 5 0 3 chi p.
The c o n u e r s i o n t i m e is 3 0 u s e e and
t h e i n p u t r a n g e is Ou to 2 . 5 u . The
l i n e a r i t y e r r o r is + o r - 1 / 2 LSB.

18 IRQ INTERRUPT REQUEST OUTPUT - This l o w

a ct iue signal i n d i c a t e s t h a t one or
more oscillators haue co m p le te d their
cycl e . This o u t p u t con be d i s a b l e d
th rough the indiuidual oscillators
c o n t r o l r e g i s t e r s . I t is an o p e n
collector output.
 *
5503 PIN DESCRIPTION (CONT.)

PIN SIGNRL
NUMBER NRME FUNCTION

19 Uss UOLTRGE INPUT - This is t h e g r o u n d

r e f e r e n c e f o r t h e 5 5 0 3 chi p.

20 RES RESET INPUT - This pin w h e n l o w mi l l

i n te r n a l ly re s e t the 5503's regis ters.
i
21 CS CHI P SELECT INPUT - This pin w h e n l o w
mi l l e n a b l e t h e 5 5 0 3 t o c o m m u n i c a t e
w i t h a mi cro pro ce ss or or o t h e r
controlling deuice.

22 LUE UJRITE ENRBLE INPUT - This pin is t h e

r e a d / w r i t e s i g na l f o r t h e 5 5 0 3 . fl h i g h
s i g n a l on t h i s pin i n i t i a t e s a r e a d c y c l e
a n d a l o w s i g n a l on thi s pin i n i t i a t e s a
w r i t e cycle.

23 - 30 R15/D7 - RDDRESS/DRTR LINES I NPUT/ OUT PUT-

A8/D0 T h e s e pi ns a r e a d d r e s s lines R8 - R15
a n d d a t a l i nes DO - D7 w h e n t h e 5 5 G 3
is a c c e s s i n g w a u e f o r m d a t a (E cl ock
o u t p u t is l o w ) a nd t h e y a r e d a t a l i nes
DO - D7 w h e n t h e 55 D3 is b e i n g
a c c e s s e d by an e w t e r n a l c o n t r o l l i n g
d e u i c e (E cl ock o u t p u t is hi gh) .

31 - 38 RO - R7 RDDRESS LINES INPUT/OUTPUT - T h e s e

pi ns a r e a d d r e s s l i nes RO - R7 o u t
w h e n t h e 5 5 0 3 is a c c e s s i n g w a u e f o r m
d a t a a n d a r e a d d r e s s lines RO - R7 in
w h e n t h e 5 5 0 3 is be i ng a c c e s s e d by an
e n t e r n a l co ntr ol ling deuice.

39 Udd UOLTRGE I NPUT - This is t h e p o s i t i u e

p o w e r s u p p l y pin - +5u + o r - 5%.

40 BS BRNK SELECT OUTPUT - This o u t p u t pin is

e s s e n t i a l l y a d d r e s s line R16.
 5 5 0 3 E L E C T R IC A L SP E C IFIC A T IO N

ABSOLUTE MAXIMUM RATINGS

A m b i e n t T e m p e r a t u r e Under B i a s - 1 0 to 8 0 degrees C
S to ra g e T e m p e r a t u r e ; - 6 5 to 1 5 0 d e q r e e s C
V o l t a g e on any P i n - 0 . 3 v to +7 v

D.C. CHARACTERISTICS
Ta = 0 to 5 0 deg re e s C, Vdd = 5 v + / - 5%
CHARACTERISTIC MIN. MAX. TYP. UNITS
R/W, CS, AO - A 7 ,
A S / DO - A 1 5 / D 7 , RES
Vil 0.0 0.4 - V o lts
Vih 2.4 5.0 V o lts

CSTRB, CAO - CA 3, ■
VSTR3, WSTRB, BS ’ .
AO - A 7 , A 8 / D 0 - A 1 5 / D 7 .
Vol 0.8 V o lts
Voh 2.4 - - V o lts
lo l - Sink C u r r e n t , Vol = 0.4 - 2.0 - mA
1oh - Source C u r r e n t , Voh = 2.4 -
1 100 - uA

CLOCK INPUT (CLK) •

Frequency » -
16 8 Mhz
Vil 0.0 0.4 -
V o lts
Vih 4.5 - -
V o lts

CLOCK OUTPUTS (RAS, CAS, E Q)

Frequency (RAS, CAS) • - -
2 Mhz
Frequency (E,Q) - 1 Mhz
Vof - 0.8 - V o lts
’ Voh 2.4 - - . V o lts
lol - S in k C u r r e n t , Vol = 0.4 - 2.0 —• mA
loh - Sourc e C u r r e n t , Voh = 2.4 —
100 -
uA
 DIGITAL OSCILLATOR CHIP SPECIFICATION

There are 32 oscillators in the chip. Each osc illator is controlled by a

set of seven registers:
..A

' 1. Frequency Low

2. Frequency High
3. Volume
A Data Sample
5. Address Pointer
6. Control Register
7. Resolution/Table Size Registers

In addition to these 224 o s c illa to r control registers, there are three

other registers: .

1. Oscillator IRQ
2. Oscillator Enable \ *r
3. Analog to Digital Converter

The seven o s c il la to r control regi ste rs are grouped as a set of 32

registers. In other words, oil 32 frequency low control registers ore
grouped together and addresses consecutively, e.g., frequency low for
o scil la to r 0 is address at location $00, OSC 1 frequency low is at $01.
Frequency High Control for OSC is at $20, which is 32 locations above
frequency low control. The re g iste r map fo r each of the seven
. oscill ato r control groups is as follows:

Address Register Function Description

00- IF Frequency low for OSCO thru 0SC31

20-3F Frequency high for OSCO thru 0SC31
'40-5F ' Volume
60-7F Waveform Data Sample
B0-9F Address Pointer
AO-BF Control Register
CO-DF Resolution/Table Size
EO Oscilla tor Interrupt Register
El Oscillato r Enable Register
E2 Analog to Digital Converter
Note that the os c il la to r s are also grouped into 8 "voices". Each voice
consists of four os cilla to rs , e.g., OSCO, OSC1, 0SC2 and 0SC3 are
referred to as Voice 0, 0SC4, 0SC5, 0SC6, and 0sc7 are Voice 1.

CONTROL REGISTER (AO-BF)

The fo llo wing chart indicates the decomposition of the control

register into i t s b it definitions:

D7 D6 D5 D4 D3 D2 D1 DO '
C43 CA2 CA1 CAO IE M2 Ml H

For each OSC the control register is used to control three functions.

1. Channel Assignment (CA3-CAQ)

Bits 7 thru 4 of the control regi ster are defined as CA3 thru CAO.
These four b its are used to control the final voice multiplexor.
Sixteen d iffe r e n t channel assignments are possible; only eight are
normally used. Channel assignment is usually synonomous w i t h
voice assignment.

2. Interrupt Assignment (IE) - ~ ...

Bit 3 of the control register is used to stop an inte rr up t from being
passed to the Oscillaor Interrupr Register (OIR). If IE is set, then
the o s c illa t o r w i l l cause an interrupt to be passed to the OIR when
i t completes a cycle, which n turn w i l l interrupt the processor. If
IE is clear, then the interrupt w i l l be put into the o s c illa t o r
interrupt table, but not passed to the OIR. When more than one
o s c il la to r inte rru pt occurs, the interrupt stack w i l l retain the
status and pass interrupts to the OIR as they are serviced by the
processor. If the interrupt has been stored into the in te rr u p t table
while IE = 0 , when IE is changed to a 1 the IRQ w i l l be passed to
the OIR.
T

Oscillator Mode (M2, M l, H)

Bits 2,1, 0 control the functional mode of each oscillator.

The fo llo wing chart describes these modes: .

M2 Ml Oscillato r Mode

0 0 Free run

0 1 Address one cycle, reset OSC accumulator

' . ......... - - to zero, and set halt bit. • * •

1 0 Sync 0SC2 to OSC1 or amplitude

v£W • modulate OSC1 by OSCO.

If set fo r an Even voice then the Odd

..........j ; : voice w i l l sync to the Even voice,

it w i l l reset the accumulators for both the

Even and Odd voices to zero and the cycle
w i l l s ta rt again.

’ ' If set fo r an Odd voice then the.Odd voice

• r envelopes the next Even voice. Note: voice
0 has no modulation source. * ■ ...

I 1 Address one cycle, reset OSC accumulator

to zero, and set halt bit then reset halt b it
of associated o sc illa to r (togle mode)

Whenever the halt b it is set by DOC or the processor and Ml is set, the
OSC w i l l be reset to zero. ,

Ml * H = 1 causes o s c illa t o r to be reset

Sync w i l l cause 0SC2 to sync to OSC 1 in each voice group. (0SC6

syncs to 0SC5 fo r voice 1 etc.)
t
Amplitude mosulation w i l l cause OSCO to be used as an envelope fo r
OSC 1 in each voice group. (0SC4 modulates 0SC5 in voice 3 etc.)
Volume for OSCO ond OSC 1 is ignored.
DATA SAMPLE (60-7F)

This set of registers is used to indicate the current 6 - b it value of the

waveform sample. This value w i l l be fed to the DOC for that
particularosci 11ator. This function is useful for LFO or modulation
applications where the DOC o scilla to rs are used to fetch sine wave
samples that can be read by the processor f o r additional processing.
These registers ere read only.

VOLUME (40-5F)

This set of registers is used to control the volume level of the

waveform data. The 9 - b i t volume level is multiplied by the 8 - b i t
waveform value to form the final analog output for each oscillator.

FREQUENCY CONTROL HIGH AND LOW (00-3F)

This group of registers is the 16-bit value which defines in part the
octual frequency of the oscWalor. These VWufeyiSierS ai"9
concatonated and become the incremental value for the linear
accumulating oscillators. THe o s c il la t o r block diagram is'indicated
below:
 ADDRESS POINTER (80-9F)

This is an 6 - b i t register which defines the stra rtin g base address of

the waveform table. The number of address pointer bits actually used
in the final address depends on the size of t he waveform table
specified. The following chart indicates the use of the pointer bits:

WAVEFORM TABLE SIZE A 15 A 14 A 13 A 12 A ll A 10 A9 A8

256 P7 P6 P5 P4 P3 • P2 PI PO
512 P7 P6 P5 P4 P3 P2 PI -

1024 P7 P6 P5 P4 P3 P2 -

2048 P7 P6 P5 P4 P3 -

4096 P7 P6 P5 P4 -

, p7
8192 P6 P5 -

'1 6 38 4 P7 P6 -

32768 P7

WAVEFORM TABLE SIZE/RESOLUTION/BANK SELECT (CO-DF)

This r gister controls three o s c ill a to r functions. The following chart

indicates the bit positions w i t h i n the regi ster to control the three
functions.

D7 D6 D5 D4 D3 D2 D1 DO
N.U. B.S. T2 T1 TO R2 Rl RO

1. Bank Select Bit (B.S. = bit 6)

This bit is used to extend the addressinq rangeof theDOC from 64K
■to 120K.

2. Table Size (T = b5, b4, b3)

These 3 - b its are used to specify the size of the waveform table
addressed by the oscillator.
2 T1 TO Table Size

0 0 0 256
0 0 1 512
0 1 0 1024
0 1 1 2048
1 0 0 4096
1 0 1 8192
1 1 0 16384
1 1 1 32768
3. Resolution
These three bits determine which set of 16 bits, of the 24 in the
o s c illa to r accumulator, are used to address the waveform table.
The purpose of this occumulotor bit selection is to allow the
frequency resolution to be adjusted to the waveform table size. For
example, when using o 32K waveform table, accumulator bits 6 thru
23would normally be used, but in a 256 byte table a lowe r resolution
setting would be used to step through the table faster.

There ore eight occumulotor oddress bit selections ovoiloble.

R2 R1 RO Accumulator Bits Used
as Addresses

0 0 0 1 through 16
0 0 2 through 17
0 1 0 3 through 18
0 1 4 through 19
1 0 0 5 through 20
1 0 6 through 21
0 7 through 22
B through 23
ADDRESS CALCULATION

The f i n a l address t h a t i s used to a c c e s s a w a v e f o r m t a b l e is a

f u n c t i o n of th e address p o i n t e r v a l u e , the t a b l e s iz e , and the
r e s o l u t i o n . The f o l l o w i n g t a b le i n d i c a t e s the v a r i o u s address
p o s s i b i l i t i e s f o r the DOC.

Tab le A 1 5 A 1 4 A 1 3 A 1 2 A1 1 A 10 A 9 A 8 A 7 A6 A5 A 4 A 3 A2 A1 a o ;
Size A23 A A A A A A A 16 1 1 1
2 5 6 P7 P6 P5 P4 P3 P2 P I PO t t t t i t t $ t t t
A 16 A A A A A A A9 0 0 0
A23 A A A A A A A A 15
5 1 2 P7 PI t t $ $ $ t t $
A 16 A A A A A A A A8

A23 A A A A A A A A A 14
1024 P7 P2 $ * $ $ $ t $ $ v..$ $
A 16 A A A A A A A A A 7

A23; A A A A A A A A A A 13
2 0 4 8 P7 P3 t t t t t t $ * t * $
A 16 A A A A A A A A A A6

A23 A A A A A A A A A A A 12
4 0 9 6 P7 P4 t t t t t $ $ t t t + t
A 16 A A A A A A A A A A A5

A23 A A A A A A A A A A A A 11
8 1 9 2 P7 P5 t t t t t t t t t t t t
t A 16 A A A A A A A A A A A A4

A23 A A A A A A A A A A A A A 10
1 6 3 8 4 P7 P6 t t t t t t t t t t t t t t t
A 16 A A A A A A A A A A A A A3

A23 A A A A A A A A A A A A A A9
3 2 7 6 8 P7 t I X t t t t t t I t t S
A 16 A A A A A A A A A A A A A A2
OSCILLATOR INTERRUPT REGISTER

The OIR is used to info rm the processor which osc illato r hos caused en
interrupt request to occur. When on oscilla to r completes o waveorm
table on interrupt is generated. THis interrupt w i l l be passed to the OIR
if IE = 1. The OIR w i l l thenissue an IRQ to the processor. Upon
recognizing th IRQ, the processor reads the oIR to determine which
oscillator issued the IRQ. The OIR is an 8 - b i t register where Bit 7
indicates the state of the IRQ line, (bit 7 = 0 for valid IRQ). Bits 5
through 1 contain the o s c il la to r number Othrough 31. Bits 6 and 0 are
always I.

D7 OS D5 D4 D3 D2 D1 DO

IR 1 04 03 02 01 00 1

A ft e r the processor reads the OIR, the DOC w i l l clear the appropriate
oscillator in terru pr request, e.g., i f o sc il la to r 4 causes on IRQ, then the
processor w i l l read: OIR = 65 + 4.

OSCILLATOR ENABLE REGISTER (El)

This register determines the number of active oscillators on the DOC.

Load the register w i t h the number of oscillators to be enabled,
multiplied by 2, e.g., to enable all oscillators, load register w i t h a 62.

Note: There are 32 o sc il la to r s on DOC plus 2 additional time slots f o r

RAM refresh. Therefore, 34 actual oscil la to r time slots are used. If the
number of o scil la to rs is halved to 16 the frequency is not doubled since
the two refresh tim e slots s t i l l exist. To halve the frequency, the
number of enabled os c il la to r s should be 15. Oscillators which are
disabled w i l l not hold th e ir associated register data since they are not
refreshed.
 5503 REGISTER MRP SUMMRRY

RDDRESS FUNCTI ON D7 D6 D5 D4 D3 D2 D! DO
(HEH)

00 - IF FREQUENCY LOUJ FL7 FL6 FL5 FL4 FL3 FL2 FL 1 FLO

2 0 - 3F FREQUENCY HIGH FH7 FH6 FH5 FH4 FH3 FH2 FH1 FHO

4 0 - 5F UOLUME U7 U6 LI 5 U4 U3 U2 Ul UO

6 0 - 7F LURUEFORM DRTR LU7 UJ6 LU5 LU4 UJ3 UJ2 LU1 LUO
SAMPLE

8 0 - 9F LURUEFORM P7 P6 P5 P4 P3 P2 PI PO
TRBLE POINTER

RO - BF CONTROL CR3 CR2 CR1 CRO IE M2 Ml H

CO - DF BRNK SELECT/ H BS T2 Tl TO R2 R1 RO
TRBLE S I Z E /
RESOLUTION

EO OSCILLRTOR IRQ 1 04 03 02 01 00 1
INTERRUPT

El OSCILLATOR H H E4 E3 E2 El EO H
ENRBLE

E2 R / D CONUERTER S7 S6 S5 S4 S3 S2 SI SO
>_ ..

NOTES: 1) DITS LRDELED 1 ORE NOT USED RND RLUJRVS RERO

BACK R S f l I .

2) BITS LABELED II RRE NOT USED RND RLUJRVS RERO

BRCK RS fl ! .
 5503 SYSTEM TIMING

INPUT CLOCK TIMING

CHARACTERISTIC SYMBOL MIN. TYP. MAX. UNITS

I n p u t Clock Cycle T i m e Tcycl 100 - 125 ns
C lo c k High Tpwn 50 - — ns
C lo c k Lo^/ Tpwl 50 - - ns
R is e and Fall T i m e s Tr, Tf — 10 ns

OUTPUT CLOCK TIMING

CHARACTERISTIC SYMBOL MIN. TYP. MAX. UNITS
T w o MHz C lo ck Cycle T i m e Tcyc2 480 — 500 ns
RAS/CAS C lo c k Outp ut High T oh 1 270 — 290 ns
RAS/CAS C lo ck Outp ut L ow T o ll 190 — 210 ns
RAS High a f t e r E Low Trd -
— 40 ns
CAS High a f t e r RAS High Ted 40 - 70 ns
1MHz u P r o c e s s o r Clo cks Tcyc3 980 1000 ns
Cycle T i m e s
E/Q Clock O u tp u t High Toh2 480 - 500 ns
E / Q C l o c k O u tp u t L o w Tol2 480 - 500 ns
E High f r o m Q High Tqd 240 - 250 ns
(Q leads E)
R ise and F all T i m e s Tr, Tf - — 10 ns
(E, Q, RAS, CAS)

' /?
MICROPROCESSOR READ /W RITE TIMING TO 5 5 0 3
CHARACTERISTIC SYMBOL MIN. TYP. MAX. UNITS
Address Setup T i m e T as 350 - -
ns
Address Hold T i m e Teh 0 - 100 ns
R/W Signal Delay From E Low Trs - -
-
ns
R/W Signal V a l i d f o r Read Trw 3 50 -
-
ns
Chip Select Hold From E L o w Th 0 - -
ns
Data In Setup T i m e Tds 150 - -
ns
Data In Hold T i m e Td h 30 - -
ns
R/W Signal V a l i d f o r W r i t e Tww 350 — -
ns
Data Out Hold T i m e Tdh 30 - — ns

5 5 0 3 READ FROM MEMORY

CHARACTERISTIC SYMBOL MIN. TYP. MAX. UNITS
T i m e to V a l i d Ad dress Tas — _
50 ns
Prom E
Address Hold T i m e (AO - A 7) Tah 0 -
To ns
AS - A 15 Hold T i m e Thh - -
30 ns
From RAS Fall
A 8 / D 0 - A 15 / D 7 Lin es Tof 30 -
ns
Sw itching Time
Data In Setup T i m e Tds 100 ns
Data In Hold T i m e Tdh 20 - - ns
 RflS

RO - H7

R8/D0 -
R15/D7

5 5 0 3 RERD FROM MEMORY

MICROPROCESSOR RERD/LURITE T I M I N G TO 5 5 0 3

\
 CLK

INPUT CLOCK

ifto/sig>0

RRS

CHS

OUTPUT CLOCKS
 I
Stfrr, b<T> 1 narj m e t e r tWhi r v p i / i A y

time. J o £ hi if)® HO 6 0 ns

itL
firm io £ L$iP 5 o ^3 ZOnj

-/•___ tirmz ~[d R f \ S h i ^ h so 60 t o n5

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