Department of Electrical Engineering, IIT Bombay

EE 705 - VLSI Design Lab

Project Report

Error Correction for NAND Flash

Memory in Solid State Drives

Prepared by:
Aayush Shrivastava (19D070002)
Jay Vijay Sonawane (19D070026)
Kimaya Shikarkhane (19D070053)
Siddhant Shingade (19D070057)
Instructor: Prof. Sachin Patkar
Date: August 16, 2023
Contents
1 Introduction 1

2 System Design 1
2.1 LDPC Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 Encoder Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.3 Decoder Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Implementation 3

4 Decoding Algorithm Used 4

5 Simulation and Results 5

6 Openlane Implementation 7

7 Static Time Analysis 9

8 Video Links 9

9 References 9

I
1 Introduction
LDPC (Low Density Parity Check) codes are a type of error-correcting code that
can be used to detect and correct errors in digital communication systems. One of the
most popular decoding algorithms for LDPC codes is the bit flipping algorithm, which
is an iterative algorithm that passes binary messages between variable nodes and check
nodes in the Tanner graph representation of the code.

In the bit flipping algorithm, the received codeword is initially assumed to be error-
free, and the algorithm starts by calculating the parity of the received word using the
parity check matrix of the LDPC code. If the parity check fails, the algorithm attempts to
flip some of the bits in the received codeword to correct the error. The algorithm continues
iterating until either the maximum number of iterations is reached or the parity check
passes.

In each iteration, the algorithm selects a variable node and flips the value of its
corresponding bit if it reduces the number of unsatisfied parity checks. The algorithm
then updates the parity check equations to reflect the changes made to the variable nodes.
This process is repeated for all variable nodes until the maximum number of iterations is
reached, or the parity check passes.

The bit flipping algorithm has a lower computational complexity compared to other
decoding algorithms for LDPC codes such as belief propagation, and it can achieve a
good balance between performance and complexity. However, the performance of the
bit flipping algorithm is sensitive to the initial assumption of the received word, and the
convergence rate can be slow for certain codes.

2 System Design
The system consists of an encoder and decoder. We will be using a AWGN channel,
to mimic the generation of errors in the encoded word. The decoder on the other end
should be able to decode correctly even in the presence of errors.

Figure 2.1: System Design Flowchart (from reference paper)

2.1 LDPC Algorithm

A word is encoded in the following way:-

C = UG

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Where U is the block of information bits and G is the generator matrix. A valid codeword
can be verified using
HCT = 0
Where H is the parity check matrix. If the result is nonzero, the codeword C is invalid
and an error correction procedure should be used in this case.

2.2 Encoder Design

The encoder uses a regular matrix to create the generator matrix. Regular matrix
is one in which column weight Wc is same for all columns and row weight is given by
Wr = Wc (n/m). In this project, regular parity matrix size of 8x16 for coding 8-bit
message blocks has been used. The we use the following H matrix in it’s standard form
 
1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
 
0 1 0 1 1 1 1 0 0 1 0 0 0 0 0 0
 
 
 
1 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0
 
 
 
0 1 0 1 1 1 1 1 0 0 0 1 0 0 0 0
H= 



0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0
 
 
 
0 0 1 1 1 0 1 0 0 0 0 0 0 1 0 0
 
 
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
 
 
 
0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1

The encoder finds the generator matrix (G) using this code and then the information
message bits are coded by multiplying message blocks with generator matrix to obtain
the codeword’s, i.e. C= [U][G]

2.3 Decoder Design

The LDPC architecture is designed to use the Bit Flipping decoding technique for
error correction. When a codeword is received, it is checked for errors, and if any errors
are found, they are corrected using the Bit Flipping algorithm. The messages passed
along the edges of the Tanner graph in this algorithm are binary. At first, a bit node
sends a message declaring whether it is a one or a zero, and each check node sends a
message to each connected bit node, declaring what value the bit should be based on the
information available to the check node. The check node determines if its parity-check
equation is satisfied if the modulo 2 sum of the incoming bit values is zero. If a bit node
receives a majority of messages that differ from its current value, the bit node flips its
value.

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 Figure 2.2: Decoder block diagram (from reference paper)

3 Implementation

Figure 3.1: Blocks to be implemented

Input : An 8 bit input is used here. It is encoded and then noise is added to the
input. A decoder is then used to decode and apply noise correction algorithm. We expect
the output to be the same as the input.

LDPC encoder module: This module performs the LDPC encoding algorithm to
the data.

Noise Adder: This module mimics the noise added during transmission.

LDPC decoder module: This module performs the LDPC decoding of the encoded
data. It includes input and output ports for the encoded input and decoded output
signals, as well as the parity-check matrix and encoding of the FIR filter output. It
includes input and output ports for the input and encoded output signals, as well as
the parity-check matrix and the encoding algorithm. The VHDL code performs the
encoding calculations, which involve generating a parity-check matrix based on the filter
output and applying the LDPC encodithe decoding algorithm. The VHDL code performs

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the decoding calculations, which involve applying the LDPC decoding algorithm to the
encoded data and generating the decoded output.

Top-level module: This module integrates the FIR filter moduleNoise adder with
the LDPC encoder and decoder modules. It includes input and output ports for the filter
input and output signals, as well as the filter coefficientsnoise, the parity-check matrix,
and the LmDPC encoding and decoding algorithms. The VHDL code coordinates the
operation of the filternoise, encoder, and decoder modules to perform the desired signal
processing operations.

4 Decoding Algorithm Used

1. We Use a version of Bit Flipping Algorithm.

2. We receive the 16 bit encoded input that has some noise added to it.

3. We assign the received message to the 16 variable nodes of the tanner graph.

4. We compute the check node values from the variable node values. The parity
matrix or the tanner graph exactly tells us how the check nodes are connected to
the variable nodes. In this project, each check node is connected to 4 variable nodes
and each variable node is connected to two check nodes.

5. Once we have computed all the check node values, we check if all values are 0. If all
of them are 0, then we don’t have any error. We directly provide the output.The
output is the first 8 MSB bits of the received message.

6. If the values are not zero, then we compute the maximum occurrence value. Since
each variable node is connected to two check node we all together have 3 values or
bits; 2 from the connected check nodes and one stored in the variable node. If out
of these 3 bits, two are 0 then variable node is assigned 0; if two of them are 1 then
variable node is assigned 0.

7. Doing this for each variable node flips the variable node bit if there is an error
i.e. when the check node values are equal are different from that stored in variable
node.

8. After correction we provide the output.The output is the first 8 MSB bits of the
received message.

9. Hence, 6.66 % error in the received bit stream can be corrected easily with this
method.

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5 Simulation and Results

Figure 5.1: Encoder Netlist

Figure 5.2: Decoder Netlist

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Figure 5.3: Combining the modules

Figure 5.4: Top module netlist

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 Figure 5.5: Encoder Simulation

Figure 5.6: Decoder for error message

Figure 5.7: Decoder for message with no error

6 Openlane Implementation
Since our code is in VHDL, we had to use vhdl to verilog convertor to implement on
OpenLane. Thus we have synthesised the Encoder block over here.

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Figure 6.1: Successful synthesis in Openlane

Figure 6.2: Encoder Layout

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7 Static Time Analysis

Figure 7.1: STA Report

8 Video Links
1. Simulation

2. Xen10 Board Implementation

3. OpenLane Colab Code

9 References
1. FPGA Implementation of LDPC Encoder and Decoder using Bit Flipping Algorithm:B.
Sai Reddy1 , V. Seetha Rama Rao2

2. LDPC — low density parity check code | by EventHelix | 5G NR | Medium

3. .Low-Density Parity-Check Codes: Construction and Implementation

4. Low-Density Parity Check (LDPC)