System Design Choices Programmable Logic

• Programmable Logic
– PLD
e.g. Lattice ispGAL22V10, Atmel ATF1502 CPLD
– Field Programmable Gate Array (FPGA)
e.g. Altera Cyclone III, Xilinx Artix-7/Zync-7000

• Semi-Custom Design
– Mask Programmable Gate Array
e.g. ECS CMOS Gate Array
Altera HardCopy II structured ASICs
– Standard Cell Design ICT PEEL22CV10 Source: ICT
e.g. Alcatel Mietec MTC45000 0.35µm cell library
• One time use - Fuse programmable.
• Full Custom Design • Reprogrammable - UV/Electrically Erasable.

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System Design Choices Field Programmable Gate Array – Xilinx XC4000

Programmable
I/O Buffers
• Programmable Logic START HERE Interconnection
Point

– Best possible design turnaround time CLB CLB

Vertical Routing Channel

– Cheapest for prototyping
CLB CLB
– Best time to market Switching Matrix

I/O Buffers

I/O Buffers
– Minimum skill required CLB

• Semi-Custom Design
• Full Custom Design Horizontal Routing Channel

– Cheapest for mass production

– Fastest I/O Buffers

– Lowest Power
– Highest Density1 • Configurable Logic Blocks (CLBs) & I/O Blocks2
– Most skill required • Programmable Interconnect

1 2
optimization limited by speed/power/area trade off Xilinx XC4013 has 576 (24 × 24) CLBs and up to 192 (4 × 48) user I/O pins.

8002 8004
 C6:1 A6:A1
W6:W1 C
C
O6
O5 FF/LAT
CX INIT1 Q CQ
D INIT0
CK DI1 SRHI
CE
WEN MC31 SRHI SRLO
D CK
SRLO
INIT1 Q SR
CI
CE INIT0
CK SR

Field Programmable Gate Array

Product Obsolete or Under– Xilinx XC4000 CLB
Obsolescence
XC4000E and XC4000X Series Field Programmable Gate Arrays
R Xilinx Artix-7 – SLICEM CLB
BX

B6:1
DI2
A6:A1
W6:W1
3 BMUX

B
B
O6
O5 FF/LAT
BX INIT1 Q BQ
D INIT0
CK DI1
CE SRHI
WEN MC31 CK SRLO
4 SRHI
D SRLO SR
C1 • • • C4 BI INIT1 Q
CE INIT0
CK SR

H1 D IN /H 2 SR/H 0 EC AX
AMUX
DI2
A6:1 A6:A1
W6:W1 A
A
G4 S/R Bypass O6
O5 FF/LAT
CONTROL AX INIT1 Q AQ
D INIT0
CK DI1 SRHI
DIN YQ CE
G3 LOGIC WEN MC31 SRLO
F' SD CK
FUNCTION G' D Q SR
G' AI 0/1
OF
H' SR
G2 G1-G4
CE
CLK
G1 CK
WEN
LOGIC WE CIN
EC UG474_c2_02_110510
FUNCTION RD
G'
OF H' H' Figure 2-3: Diagram of SLICEM
F', G', 1
AND
H1
Y Source: Xilinx
F4 Bypass
• 4x 6-input Look-Up Tables (LUTs) for combinational logic
S/R
7 Series FPGAs CLB User Guide www.xilinx.com 19
CONTROL
DIN XQ UG474 (v1.7) November 17, 2014
F3 LOGIC SD
F'
FUNCTION F' D Q

• Carry chain supporting fast carry lookahead

G'
OF
H'
F2 F1-F4

F1

EC
• 8x storage elements
RD
K
(CLOCK) 1 LUTs can be alternatively configured as
H'
X

• 256 bits RAM

F'

Multiplexer Controlled
by Configuration Program
X6692
• 32-bit shift register
Figure 1: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)
Source: Xilinx 3
Xilinx XC7A200T has 16,825 CLBs (each containing 2 slices) and up to 500 user I/O pins.
Flip-Flops Clock Enable
The CLB can pass the combinatorial output(s) to the inter- 8005The clock enable signal (EC) is active High. The EC pin is 8007
connect network, but can also store the combinatorial shared by both storage elements. If left unconnected for
results or other incoming data in one or two flip-flops, and either, the clock enable for that storage element defaults to
connect their outputs to the interconnect network as well. the active state. EC is not invertible within the CLB.
The two edge-triggered D-type flip-flops have common
clock (K) and clock enable (EC) inputs. Either or both clock Table 2: CLB Storage Element Functionality
inputs can also be permanently enabled. Storage element (active rising edge is shown)
Slice Description

functionality is described in Table 2.

Mode K EC SR D Q
FPGA - System On Chip
X-Ref Target - Figure 2-3

Latches (XC4000X only) D

Power-Up
SRHI
SRLO
or
X Reset Type
X X X SR
INIT1 Q
CE INIT0GSR Sync/Async
COUT
The CLB storage elements can also be configured as CK SR FF/LAT

latches. The two latches have common clock (K) and clock X X 1 X SR
DX
enable (EC) inputs. Storage DI2 element functionality is Flip-Flop __/ 1* DMUX 0* D D
D6:1 A6:A1
described in Table 2. W6:W1 0 X D 0* X Q
Modern FPGAs are big enough for:
O6 D
FF/LAT
O5
DX 1 INIT1 Q 1* DQ 0* X Q
Clock Input CK DI1 Latch D INIT0
SRHI
WEN MC31 D
SRHI
SRLO
0CE
CK
SRLO 1* 0* D D
Each flip-flop can be triggered
DI on either the rising or falling CE
INIT1 Q
INIT0 Both X
SR
0 0* X Q
CK

• One or more soft-core processors

SR
clock edge. The clock pin is shared by both storage ele- Legend:
CX
ments. However, the clock is individually
DI2
invertible for each X Don’t care CMUX

C6:1 A6:A1
storage element. Any inverter placed on the clock input is __/ Rising edge
• Program memory
W6:W1 C
C
automatically absorbed into the CLB. O6
O5
SR Set or Reset
FF/LAT value. Reset is default.
CX INIT1 Q CQ
CK DI1 0* Input Dis Low
INIT0 or unconnected (default value)
CE SRHI
1* Input CKis High
SRLO or unconnected (default value)

• Data memory
WEN MC31 SRHI
D SRLO
INIT1 Q SR
CI
CE INIT0
CK SR

BX
DI2
BMUX + specialist hardware
B6:1 A6:A1
W6:W1 B
B
O6
6-10 O5
BX
FF/LAT
INIT1 Q BQ
May 14, 1999 (Version 1.6)
The new trend is for FPGAs with hard processors built in:
D INIT0
CK DI1
CE SRHI
WEN MC31 CK SRLO
SRHI
D SRLO SR
BI INIT1 Q
CE INIT0
CK SR

AX
DI2
AMUX • Xilinx Zync-7000 includes dual-core ARM A9
A6:1 A6:A1
W6:W1 A

• Altera Arria V includes dual-core ARM A9

A
O6
O5 FF/LAT
AX INIT1 Q AQ
D INIT0
CK DI1 SRHI
CE
WEN MC31 SRLO
CK

• Cypress PSoC 4 includes ARM Cortex-M0 and programmable digital4 and ana-
SR
AI 0/1
SR
CE
CLK
CK log blocks
WEN
WE CIN UG474_c2_02_110510

Figure 2-3: Diagram of SLICEM

Artix-7 – SLICEM CLB Source: Xilinx 4

here the digital block is PLD rather than FPGA
7 Series FPGAs CLB User Guide www.xilinx.com 19
UG474 (v1.7) November 17, 2014
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Mask Programmable Gate Array Standard Cell Design

9 Output Pads • Logic Functions

VDD Pad

8 Input Pads
68 Gate Sites
arranged as 4 columns
of 17 sites each.

• Auto Generated Macro Blocks

– PLA
– ROM
– RAM
8 Input Pads • System Level Blocks
GND Pad – Microprocessor core5
9 Output Pads
5
Will support System On Chip applications.

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Mask Programmable Gate Array Full Custom

GND Vdd GND Vdd

X X X X
All design styles need full custom designers
O O O O

C C C C
• to design the base programmable logic chips
B B B B
• to design building blocks for semi-custom
A A A A

Where large ASICs use full custom techniques they are likely to be
used alongside semi-custom techniques.
Vdd

A B C
e.g. Hand-held computer game chip
O
C • Full custom bitslice datapath
B hand crafted for optimum area efficiency and low power consumption
A
GND • Standard cell controller
• Macro block RAM, ROM
• Customize Metal and Contact Window masks only.

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