UNIT 4

Synchronous Sequential Logic

4.1 Sequential circuit
Sequential circuit design depends largely on combinational circuit. It consists of combinational circuit
which accepts digital signals from external inputs and from outputs of memory elements and generates
signal for external output and inputs to memory elements.
A memory element is some medium in which one bit of information (1 or 0) can be stored or
retained until necessary, thereafter it’s contents can replaced by new value.

Sequential circuit is classified in to main categories depending on the timing of their signals, known as
asynchronous sequential circuit and synchronous sequential circuit.
An asynchronous sequential circuit behavior depends on change in input signals. The output is affected
whenever input changes. The commonly used memory elements in these circuits are time delay devices
(combinational circuit with feedback). It’s design is rather difficult hence it’s use is limited.
A synchronous sequential circuit behavior can be defined from knowledge of it’s signal at discrete
instant of time. The synchronization is achieved by a timing device known as system clock which
generates a periodic train of clock pulses. The outputs are affected only with clock pulse, also known as
clocked sequential circuit. Memory elements used are Flip-Flops to store binary information.
4.2 Latches
It is a group of flip-flops sensitive to pulse duration is called latch. It is a storing element. Flip-flops are
constructed using latches (either 2 NAND or 2 NOR gates). The circuit remembers the state till the power
supplied, triggered by input post. It is also considered as bi-stable latch.

S R Q Q

0 0 1 0

0 1

0 1 0 1

1 0 1 0 Invalid
1 1 0 1

It is also called as active high latch.

 S R Q Q
0 0 1 1 Invalid
0 1 1 0

1 0 0 1
1 1 0 1
1 0

It is also called as active low latch. Both the latches does the same job but in different way.
4.2.1 Flip-flops
Flip-flop is a memory element which is capable of storing one bit information and it is used in clocked
sequential circuit. It has two outputs, one for normal value and other for complement value of the bit
stored in it. It can maintain a binary state indefinitely (till power supplied) and until directed by an input
signal to switch states. It is also known as bi-stable multivibrator.

Fig: block diagram of flip-flop.

Flip flops are of different types depending on how their inputs and clock pulses cause transition
between two states. The types of flip flop are:
i) SR Flip-Flop ii) D Flip-Flop iii) JK Flip-Flop iv) T Flip-Flop

4.2.1.1 Clocked SR Flip Flop

The clocked Flip SR Flop consists of the basic NAND latch and other two NAND gates to provide clock
pulse. Clock pulse is used for the synchronization and act as an additional control input.

Fig: Logic diagram. Fig: Graphical symbol

 Characteristics table

Q S R Q(t+1) The outputs of the two AND remain at 0 as long as

0 0 0 0 the clock pulse is 0, regardless of S and R values.
0 0 1 0 When the clock pulse goes to 1, the information from
0 1 0 1 the S and R input reaches to basic flip flops. The set
0 1 1 X state is reached to is reached with S=1, R-0 and CK
1 0 0 1 =1. To change the clear state, the inputs must be S=0,
1 0 1 0 R=1, and CK=1. With both S=1 and R=1, the
1 1 0 1 occurrence of a clock pulse causes both outputs
1 1 1 X momentarily go to 0. Q is binary state of the Flip
Flop at a given time (present state), S and R columns
gives the possible values of inputs, Q(t+1) is the state
K-map from the characteristics table. of Flip Flop after the occurrence of clock pulse.

Q(t+1)=S+QR

4.2.1.2 D Flip-Flop
D Flip-flop is a modification of clocked SR Flip-flop. The D input is sampled during the occurrence of a
clock pulse. If it is 1, the output of gate 3 goes to 0, switching the flip flop to the set state (unless already
in set state). If it is 0, the output of gate 4 goes to 0, switching the flip flop to clear state.
It is basically an RS flip flop with an inverter in the R input. The added inverter reduces the
number of inputs two to one. It is sometimes also gated D latch. when D is HIGH, the Q output goes
HIGH on triggering edge of clock pulse, and the flip flop is SET. When D is low, the Q output goes LOW
on the triggering edge of the clock pulse and the flip flop is RESET.

Fig: Logic diagram Fig: Graphical symbol

Characteristics table Q(t) D D D

Q(t) D Q(t+1) 1
0 0 0 Q(t+1)=D
0 1 1 1
1 0 0
1 1 1

The characteristics equation shows that the next state of the flip flop is same as the D input and is
independent of the value of the present state.

4.2.1.2 JK Flip flop

A JK flip-flop is a refinement of the RS flip-flop in that the indeterminate state when both inputs are 1.
Inputs J and K behave like inputs S and R to set and clear the flip-flop, respectively. The input marked J is
for set and the input marked K is for reset. When both inputs J and K are equal to 1, the flip-flop switches
to its complement state, that is, if Q = 1, it switches to Q = 0, and vice versa.
A JK flip-flop constructed with two cross-coupled NOR gates and two AND gates is shown in
Fig. below:  A JK flip-flop is constructed with two cross-
coupled NOR gates and two AND gates.
 Output Q is ANDed with K and CP inputs so that
the flip-flop is cleared during a clock pulse only if
Q was previously 1.
 Similarly, output Q' is ANDed with J and CP
inputs so that the flop-flop is set with a clock pulse
only when Q' was previously 1.
 Because of the feedback connection in the JK
flipflop, a CP pulse that remains in the 1 state
while both J and K are equal to 1 will cause the
output to complement again and repeat
complementing until the pulse goes back to 0.
 To avoid this undesirable operation, the clock
pulse must have a time duration that is shorter than
the propagation delay time of the flip-flop. This is
a restrictive requirement of JK which is eliminated
with a master-slave or edge-triggered construction.
4.2.1.2 T Flip flop
The T flip-flop is a single-input version of the JK flip-flop and is obtained from the JK flip-flop when both
inputs are tied together. The designation T comes from the ability of the flip-flop to "toggle," or
complement, its state. Regardless of the present state, the flip-flop complements its output when the
clock pulse occurs while input T is 1. The characteristic table and characteristic equation show that:
When T = 0, Q(t + 1) = Q, that is, the next state is the same as the present state and no change
occurs.
When T = 1, then Q (t + 1) = Q', and the state of the flip-flop is complemented.
Characteristics table

K map and Characterristics equation.

Fig: graphical symbol

4.3 Triggering of Flip-Flops

The state of a flip-flop is switched by a momentary change in the input signal. This momentary change is
called a trigger and the transition it causes is said to trigger the flip-flop. Clocked flip-flops are triggered
by pulses. A pulse starts from an initial value of 0, goes momentarily to 1, and after a short time, returns
to its initial 0 value.
The clocked flip-flops introduced earlier are triggered during the positive edge of the pulse, and
the state transition starts as soon as the pulse reaches the logic-1 level. Edge triggering is achieved by
using a master -slave or edge triggered flip-flop as discussed in what follows.
Master-slave Flip-Flop
A master-slave flip-flop is constructed from two separate flip-flops. One circuit serves as a master and
the other as a slave, and the overall circuit is referred to as a master slave flip-flop.
4.3.1 Master-slave J-K Flip-Flop
Master-slave JK flip-flop constructed with NAND gates is shown in Fig. below. It consists of two flip-flops;
gates 1 through 4 form the master flip-flop, and gates 5 through 8 form the slave flip-flop. The
information present at the J and K inputs is transmitted to the master flip-flop on the positive edge of a
clock pulse and is held there until the negative edge of the clock pulse occurs, after which it is allowed to
pass through to the slave flip-flop.

Fig: Graphical symbol of master slave flip-flop.

Fig: Logical diagram of JK master slave Flip flop

Operation:
 The clock input is normally 0, which prevents the J and K inputs from affecting the master flip-flop.
 The slave flip-flop is a clocked RS type, with the master flip-flop supplying the inputs and the clock
input being inverted by gate 9.
 When the clock is 0, Q = Y, and Q' = Y'.
 When the positive edge of a clock pulse occurs, the master flip-flop is affected and may switch
states.
 The slave flip-flop is isolated as long as the clock is at the 1 level
 When the clock input returns to 0, the master flip-flop is isolated from the J and K inputs and the
slave flip-flop goes to the same state as the master flip-flop.
4. 4 Analysis of clocked sequential circuits
The behavior of a sequential circuit is determined from the inputs, the outputs, and the state of its
flip-flops. The outputs and the next state are both a function of the inputs and the present state.
The analysis of a sequential circuit consists of obtaining a table or a diagram for the time sequence
of inputs, outputs, and internal states. It is also possible to write Boolean expressions that describe
the behavior of the sequential circuit.
Example
An example of a clocked sequential circuit is shown in Fig. below. The circuit consists of two D flip-flops
A and B, an input x, and an output y.

Fig: example of sequential circuit.

In above example, D inputs determine the flip-flop’s next state, so it is possible to write a set of next-
state equations for the circuit:
Can be written conveniently as:
A(t + 1) = Ax + Bx
B(t + 1) = A'x
Similarly, the present-state value of the output y can be expressed algebraically as follows:
y(t) = [A(t) + B(t)]x'(t)
Removing the symbol (t) for the present state, we obtain the output Boolean function:
y = (A + B)x'

State table
The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state table. The state
table for the example circuit above is shown in the table below.
 The table consists of four sections:
 Present state: shows the states of flip-flops
A and B at any given time t
 Input: gives a value of x for each possible
present state
 Next state: shows the states of the flip-
flops one clock period later at time t + 1.
 Output: gives the value of y for each
present state.
 The derivation of a state table consists of
first listing all possible binary
combinations of present state and inputs.
 Next state and output column is derived
from the state equations.

State Diagram
The information available in a state table can be represented graphically in a state diagram. In this type
of diagram, a state is represented by a circle, and the transition between states is indicated by directed
lines connecting the circles.

Fig: state diagram of example above.

4.4.1 State reduction and assignment

The analysis of sequential circuits starts from a circuit diagram and culminates in a state table or
diagram. The design of a sequential circuit starts from a set of specifications and culminates in a logic
diagram. Any design process must consider the problem of minimizing the cost of the final circuit
(reduce the number of gates and flip-flops during the design).
Example
Consider a sequential circuit with following specification. States marked inside the circles are denoted by
letter symbols instead of by their binary values.
Algorithm: "Two states are said to be equivalent if, for each member of the set of inputs, they give
exactly the same output and send the circuit either to the same state or to an equivalent state. When
two states are equivalent, one of them can be removed without altering the input-output relationships."

Look for two present states that go to the same next state and have the same output for both input
combinations. States g and e are two such states: they both go to states a and f and have outputs of 0
and 1 for x = 0 and x = 1, respectively. Therefore, states g and e are equivalent; one can be removed.
Final reduced table and state diagram for the reduced table consists of only five states.

4.4.2 Design procedure

The design of a clocked sequential circuit starts from a set of specifications (state table) and ends in a
logic diagram or a list of Boolean functions from which the logic diagram can be obtained.

Procedure:
The procedure can be summarized by a list of consecutive recommended steps:
1) State the word description of the circuit behavior. It may be a state diagram, a timing diagram, or
other pertinent information.
2) From the given information about the circuit, obtain the state table.
3) Apply state-reduction methods if the sequential circuit can be characterized by input-output
relationships independent of the number of states.
4) Assign binary values to each state if the state table obtained in step 2 or 3 contains letter symbols.
5) Determine the number of flip-flops needed and assign a letter symbol to each.
6) Choose the type of flip-flop to be used.
7) From the state table, derive the circuit excitation and output tables.
8) Using the map or any other simplification method, derive the circuit output functions and the flip-
flop input functions.
9) Draw the logic diagram.
 Procedure step: (1) and (2)
 The state diagram consists of four states with
binary values already assigned.
 Directed lines contain single binary digit
without a slash, we conclude that there is one
input variable and no output variables. (The
state of the flip-flops may be considered the
outputs of the circuit).
 The two flip-flops needed to represent the four
states are designated A and B.
 The input variable is designated x.

Fig: state diagram of design example.

Procedure step: (3)

The state table for this circuit, derived
from the state diagram. Note that there is
no output section for this circuit.

In the derivation of the

excitation table, present state
and input variables are
arranged in the form of a truth
table.
 JK type is used here. (PS
(6))
 Since JK flip-flops are used
we need columns for the J
and K inputs of flip-flops A
(denoted by JA and KA) and
B (denoted by JB and KB).
  Shows the two JK flip-
flops needed for the circuit
and a box to represent the
combinational circuit.
 From the block diagram, it
is clear that the outputs of
the combinational circuit
go to flip-flop inputs and
external outputs (if
specified).
 The inputs to the
combinational circuit are
the external inputs and the
present state values of the
flip-flops.

Derivation of simplified
Boolean functions for the
combinational circuit.
 The information from the
truth table is transferred
into the maps.
 The inputs are the
variables A, B, and x; the
outputs are the variables
JA, KA, JB, and KB.

The logic diagram is drawn in

by side and consists of two flip-
flops, two AND gates, one
exclusive-NOR gate, and one
inverter.